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rtlwifi: btcoexist: Fix "always true" warning from commit ed364abffd6e
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
108f4f3c 10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
e4d6b795 11
3dbba8e2
AH		 12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
e4d6b795
MB		 15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
ac5c24e9 37#include <linux/module.h>
e4d6b795
MB		 38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
e4d6b795 40#include <linux/firmware.h>
e4d6b795
MB		 41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795 44#include <linux/dma-mapping.h>
5a0e3ad6 45#include <linux/slab.h>
e4d6b795
MB		 46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
ef1a628d
MB		 51#include "phy_common.h"
52#include "phy_g.h"
3d0da751 53#include "phy_n.h"
e4d6b795 54#include "dma.h"
5100d5ac 55#include "pio.h"
e4d6b795
MB		 56#include "sysfs.h"
57#include "xmit.h"
e4d6b795
MB		 58#include "lo.h"
59#include "pcmcia.h"
3dbba8e2
AH		 60#include "sdio.h"
61#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 62
63MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64MODULE_AUTHOR("Martin Langer");
65MODULE_AUTHOR("Stefano Brivio");
66MODULE_AUTHOR("Michael Buesch");
0136e51e 67MODULE_AUTHOR("Gábor Stefanik");
108f4f3c 68MODULE_AUTHOR("Rafał Miłecki");
e4d6b795
MB		 69MODULE_LICENSE("GPL");
70
6021e08d
TG		 71MODULE_FIRMWARE("b43/ucode11.fw");
72MODULE_FIRMWARE("b43/ucode13.fw");
73MODULE_FIRMWARE("b43/ucode14.fw");
74MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 75MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 76MODULE_FIRMWARE("b43/ucode5.fw");
77MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 78
79static int modparam_bad_frames_preempt;
80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
e4d6b795
MB		 84static char modparam_fwpostfix[16];
85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
e4d6b795
MB		 88static int modparam_hwpctl;
89module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92static int modparam_nohwcrypt;
93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
035d0243 96static int modparam_hwtkip;
97module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
403a3a13
MB		 100static int modparam_qos = 1;
101module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
1855ba78
MB		 104static int modparam_btcoex = 1;
105module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 107
060210f9
MB		 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109module_param_named(verbose, b43_modparam_verbose, int, 0644);
110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
df766267 112static int b43_modparam_pio = 0;
9e3bd919
LT		 113module_param_named(pio, b43_modparam_pio, int, 0644);
114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 115
8960400e
RM		 116static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
117module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
118MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
119
3c65ab62
RM		 120#ifdef CONFIG_B43_BCMA
121static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
3c65ab62
RM		 123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
15be8e89 125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
3c65ab62 126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
15be8e89
RM		 127 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
128 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
129 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
3c65ab62
RM		 130 BCMA_CORETABLE_END
131};
132MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
133#endif
134
aec7ffdf 135#ifdef CONFIG_B43_SSB
e4d6b795
MB		 136static const struct ssb_device_id b43_ssb_tbl[] = {
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 143 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 144 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 145 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 146 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 147 SSB_DEVTABLE_END
148};
e4d6b795 149MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 150#endif
e4d6b795
MB		 151
152/* Channel and ratetables are shared for all devices.
153 * They can't be const, because ieee80211 puts some precalculated
154 * data in there. This data is the same for all devices, so we don't
155 * get concurrency issues */
156#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 157 { \
158 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
159 .hw_value = (_rateid), \
160 .flags = (_flags), \
e4d6b795 161 }
8318d78a
JB		 162
163/*
164 * NOTE: When changing this, sync with xmit.c's
165 * b43_plcp_get_bitrate_idx_* functions!
166 */
e4d6b795 167static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 168 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
169 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
170 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
171 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
172 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
176 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
177 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
178 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
179 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 180};
181
182#define b43_a_ratetable (__b43_ratetable + 4)
183#define b43_a_ratetable_size 8
184#define b43_b_ratetable (__b43_ratetable + 0)
185#define b43_b_ratetable_size 4
186#define b43_g_ratetable (__b43_ratetable + 0)
187#define b43_g_ratetable_size 12
188
e9cdcb74 189#define CHAN2G(_channel, _freq, _flags) { \
bb1eeff1
MB		 190 .band = IEEE80211_BAND_2GHZ, \
191 .center_freq = (_freq), \
192 .hw_value = (_channel), \
193 .flags = (_flags), \
194 .max_antenna_gain = 0, \
195 .max_power = 30, \
196}
96c755a3 197static struct ieee80211_channel b43_2ghz_chantable[] = {
e9cdcb74
RM		 198 CHAN2G(1, 2412, 0),
199 CHAN2G(2, 2417, 0),
200 CHAN2G(3, 2422, 0),
201 CHAN2G(4, 2427, 0),
202 CHAN2G(5, 2432, 0),
203 CHAN2G(6, 2437, 0),
204 CHAN2G(7, 2442, 0),
205 CHAN2G(8, 2447, 0),
206 CHAN2G(9, 2452, 0),
207 CHAN2G(10, 2457, 0),
208 CHAN2G(11, 2462, 0),
209 CHAN2G(12, 2467, 0),
210 CHAN2G(13, 2472, 0),
211 CHAN2G(14, 2484, 0),
bb1eeff1 212};
3695b932
RM		 213
214/* No support for the last 3 channels (12, 13, 14) */
215#define b43_2ghz_chantable_limited_size 11
e9cdcb74 216#undef CHAN2G
bb1eeff1 217
91211739
RM		 218#define CHAN4G(_channel, _flags) { \
219 .band = IEEE80211_BAND_5GHZ, \
220 .center_freq = 4000 + (5 * (_channel)), \
221 .hw_value = (_channel), \
222 .flags = (_flags), \
223 .max_antenna_gain = 0, \
224 .max_power = 30, \
225}
bb1eeff1
MB		 226#define CHAN5G(_channel, _flags) { \
227 .band = IEEE80211_BAND_5GHZ, \
228 .center_freq = 5000 + (5 * (_channel)), \
229 .hw_value = (_channel), \
230 .flags = (_flags), \
231 .max_antenna_gain = 0, \
232 .max_power = 30, \
233}
234static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
91211739
RM		 235 CHAN4G(184, 0), CHAN4G(186, 0),
236 CHAN4G(188, 0), CHAN4G(190, 0),
237 CHAN4G(192, 0), CHAN4G(194, 0),
238 CHAN4G(196, 0), CHAN4G(198, 0),
239 CHAN4G(200, 0), CHAN4G(202, 0),
240 CHAN4G(204, 0), CHAN4G(206, 0),
241 CHAN4G(208, 0), CHAN4G(210, 0),
242 CHAN4G(212, 0), CHAN4G(214, 0),
243 CHAN4G(216, 0), CHAN4G(218, 0),
244 CHAN4G(220, 0), CHAN4G(222, 0),
245 CHAN4G(224, 0), CHAN4G(226, 0),
246 CHAN4G(228, 0),
bb1eeff1
MB		 247 CHAN5G(32, 0), CHAN5G(34, 0),
248 CHAN5G(36, 0), CHAN5G(38, 0),
249 CHAN5G(40, 0), CHAN5G(42, 0),
250 CHAN5G(44, 0), CHAN5G(46, 0),
251 CHAN5G(48, 0), CHAN5G(50, 0),
252 CHAN5G(52, 0), CHAN5G(54, 0),
253 CHAN5G(56, 0), CHAN5G(58, 0),
254 CHAN5G(60, 0), CHAN5G(62, 0),
255 CHAN5G(64, 0), CHAN5G(66, 0),
256 CHAN5G(68, 0), CHAN5G(70, 0),
257 CHAN5G(72, 0), CHAN5G(74, 0),
258 CHAN5G(76, 0), CHAN5G(78, 0),
259 CHAN5G(80, 0), CHAN5G(82, 0),
260 CHAN5G(84, 0), CHAN5G(86, 0),
261 CHAN5G(88, 0), CHAN5G(90, 0),
262 CHAN5G(92, 0), CHAN5G(94, 0),
263 CHAN5G(96, 0), CHAN5G(98, 0),
264 CHAN5G(100, 0), CHAN5G(102, 0),
265 CHAN5G(104, 0), CHAN5G(106, 0),
266 CHAN5G(108, 0), CHAN5G(110, 0),
267 CHAN5G(112, 0), CHAN5G(114, 0),
268 CHAN5G(116, 0), CHAN5G(118, 0),
269 CHAN5G(120, 0), CHAN5G(122, 0),
270 CHAN5G(124, 0), CHAN5G(126, 0),
271 CHAN5G(128, 0), CHAN5G(130, 0),
272 CHAN5G(132, 0), CHAN5G(134, 0),
273 CHAN5G(136, 0), CHAN5G(138, 0),
274 CHAN5G(140, 0), CHAN5G(142, 0),
275 CHAN5G(144, 0), CHAN5G(145, 0),
276 CHAN5G(146, 0), CHAN5G(147, 0),
277 CHAN5G(148, 0), CHAN5G(149, 0),
278 CHAN5G(150, 0), CHAN5G(151, 0),
279 CHAN5G(152, 0), CHAN5G(153, 0),
280 CHAN5G(154, 0), CHAN5G(155, 0),
281 CHAN5G(156, 0), CHAN5G(157, 0),
282 CHAN5G(158, 0), CHAN5G(159, 0),
283 CHAN5G(160, 0), CHAN5G(161, 0),
284 CHAN5G(162, 0), CHAN5G(163, 0),
285 CHAN5G(164, 0), CHAN5G(165, 0),
286 CHAN5G(166, 0), CHAN5G(168, 0),
287 CHAN5G(170, 0), CHAN5G(172, 0),
288 CHAN5G(174, 0), CHAN5G(176, 0),
289 CHAN5G(178, 0), CHAN5G(180, 0),
91211739 290 CHAN5G(182, 0),
e4d6b795
MB		 291};
292
b453fda6
RM		 293static struct ieee80211_channel b43_5ghz_nphy_chantable_limited[] = {
294 CHAN5G(36, 0), CHAN5G(40, 0),
295 CHAN5G(44, 0), CHAN5G(48, 0),
296 CHAN5G(149, 0), CHAN5G(153, 0),
297 CHAN5G(157, 0), CHAN5G(161, 0),
298 CHAN5G(165, 0),
299};
300
bb1eeff1
MB		 301static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
302 CHAN5G(34, 0), CHAN5G(36, 0),
303 CHAN5G(38, 0), CHAN5G(40, 0),
304 CHAN5G(42, 0), CHAN5G(44, 0),
305 CHAN5G(46, 0), CHAN5G(48, 0),
306 CHAN5G(52, 0), CHAN5G(56, 0),
307 CHAN5G(60, 0), CHAN5G(64, 0),
308 CHAN5G(100, 0), CHAN5G(104, 0),
309 CHAN5G(108, 0), CHAN5G(112, 0),
310 CHAN5G(116, 0), CHAN5G(120, 0),
311 CHAN5G(124, 0), CHAN5G(128, 0),
312 CHAN5G(132, 0), CHAN5G(136, 0),
313 CHAN5G(140, 0), CHAN5G(149, 0),
314 CHAN5G(153, 0), CHAN5G(157, 0),
315 CHAN5G(161, 0), CHAN5G(165, 0),
316 CHAN5G(184, 0), CHAN5G(188, 0),
317 CHAN5G(192, 0), CHAN5G(196, 0),
318 CHAN5G(200, 0), CHAN5G(204, 0),
319 CHAN5G(208, 0), CHAN5G(212, 0),
320 CHAN5G(216, 0),
321};
91211739 322#undef CHAN4G
bb1eeff1
MB		 323#undef CHAN5G
324
325static struct ieee80211_supported_band b43_band_5GHz_nphy = {
326 .band = IEEE80211_BAND_5GHZ,
327 .channels = b43_5ghz_nphy_chantable,
328 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
329 .bitrates = b43_a_ratetable,
330 .n_bitrates = b43_a_ratetable_size,
e4d6b795 331};
8318d78a 332
b453fda6
RM		 333static struct ieee80211_supported_band b43_band_5GHz_nphy_limited = {
334 .band = IEEE80211_BAND_5GHZ,
335 .channels = b43_5ghz_nphy_chantable_limited,
336 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable_limited),
337 .bitrates = b43_a_ratetable,
338 .n_bitrates = b43_a_ratetable_size,
339};
340
bb1eeff1
MB		 341static struct ieee80211_supported_band b43_band_5GHz_aphy = {
342 .band = IEEE80211_BAND_5GHZ,
343 .channels = b43_5ghz_aphy_chantable,
344 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
345 .bitrates = b43_a_ratetable,
346 .n_bitrates = b43_a_ratetable_size,
8318d78a 347};
e4d6b795 348
8318d78a 349static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 350 .band = IEEE80211_BAND_2GHZ,
351 .channels = b43_2ghz_chantable,
352 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
353 .bitrates = b43_g_ratetable,
354 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 355};
356
3695b932
RM		 357static struct ieee80211_supported_band b43_band_2ghz_limited = {
358 .band = IEEE80211_BAND_2GHZ,
359 .channels = b43_2ghz_chantable,
360 .n_channels = b43_2ghz_chantable_limited_size,
361 .bitrates = b43_g_ratetable,
362 .n_bitrates = b43_g_ratetable_size,
363};
364
e4d6b795
MB		 365static void b43_wireless_core_exit(struct b43_wldev *dev);
366static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 367static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 368static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 369static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
370 struct ieee80211_vif *vif,
371 struct ieee80211_bss_conf *conf,
372 u32 changed);
e4d6b795
MB		 373
374static int b43_ratelimit(struct b43_wl *wl)
375{
376 if (!wl || !wl->current_dev)
377 return 1;
378 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
379 return 1;
380 /* We are up and running.
381 * Ratelimit the messages to avoid DoS over the net. */
382 return net_ratelimit();
383}
384
385void b43info(struct b43_wl *wl, const char *fmt, ...)
386{
5b736d42 387 struct va_format vaf;
e4d6b795
MB		 388 va_list args;
389
060210f9
MB		 390 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
391 return;
e4d6b795
MB		 392 if (!b43_ratelimit(wl))
393 return;
5b736d42 394
e4d6b795 395 va_start(args, fmt);
5b736d42
JP		 396
397 vaf.fmt = fmt;
398 vaf.va = &args;
399
400 printk(KERN_INFO "b43-%s: %pV",
401 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
402
e4d6b795
MB		 403 va_end(args);
404}
405
406void b43err(struct b43_wl *wl, const char *fmt, ...)
407{
5b736d42 408 struct va_format vaf;
e4d6b795
MB		 409 va_list args;
410
060210f9
MB		 411 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
412 return;
e4d6b795
MB		 413 if (!b43_ratelimit(wl))
414 return;
5b736d42 415
e4d6b795 416 va_start(args, fmt);
5b736d42
JP		 417
418 vaf.fmt = fmt;
419 vaf.va = &args;
420
421 printk(KERN_ERR "b43-%s ERROR: %pV",
422 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
423
e4d6b795
MB		 424 va_end(args);
425}
426
427void b43warn(struct b43_wl *wl, const char *fmt, ...)
428{
5b736d42 429 struct va_format vaf;
e4d6b795
MB		 430 va_list args;
431
060210f9
MB		 432 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
433 return;
e4d6b795
MB		 434 if (!b43_ratelimit(wl))
435 return;
5b736d42 436
e4d6b795 437 va_start(args, fmt);
5b736d42
JP		 438
439 vaf.fmt = fmt;
440 vaf.va = &args;
441
442 printk(KERN_WARNING "b43-%s warning: %pV",
443 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
444
e4d6b795
MB		 445 va_end(args);
446}
447
e4d6b795
MB		 448void b43dbg(struct b43_wl *wl, const char *fmt, ...)
449{
5b736d42 450 struct va_format vaf;
e4d6b795
MB		 451 va_list args;
452
060210f9
MB		 453 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
454 return;
5b736d42 455
e4d6b795 456 va_start(args, fmt);
5b736d42
JP		 457
458 vaf.fmt = fmt;
459 vaf.va = &args;
460
461 printk(KERN_DEBUG "b43-%s debug: %pV",
462 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
463
e4d6b795
MB		 464 va_end(args);
465}
e4d6b795
MB		 466
467static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
468{
469 u32 macctl;
470
471 B43_WARN_ON(offset % 4 != 0);
472
473 macctl = b43_read32(dev, B43_MMIO_MACCTL);
474 if (macctl & B43_MACCTL_BE)
475 val = swab32(val);
476
477 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
478 mmiowb();
479 b43_write32(dev, B43_MMIO_RAM_DATA, val);
480}
481
280d0e16
MB		 482static inline void b43_shm_control_word(struct b43_wldev *dev,
483 u16 routing, u16 offset)
e4d6b795
MB		 484{
485 u32 control;
486
487 /* "offset" is the WORD offset. */
e4d6b795
MB		 488 control = routing;
489 control <<= 16;
490 control |= offset;
491 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
492}
493
69eddc8a 494u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 495{
496 u32 ret;
497
498 if (routing == B43_SHM_SHARED) {
499 B43_WARN_ON(offset & 0x0001);
500 if (offset & 0x0003) {
501 /* Unaligned access */
502 b43_shm_control_word(dev, routing, offset >> 2);
503 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 505 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 506
280d0e16 507 goto out;
e4d6b795
MB		 508 }
509 offset >>= 2;
510 }
511 b43_shm_control_word(dev, routing, offset);
512 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 513out:
e4d6b795
MB		 514 return ret;
515}
516
69eddc8a 517u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 518{
519 u16 ret;
520
e4d6b795
MB		 521 if (routing == B43_SHM_SHARED) {
522 B43_WARN_ON(offset & 0x0001);
523 if (offset & 0x0003) {
524 /* Unaligned access */
525 b43_shm_control_word(dev, routing, offset >> 2);
526 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
527
280d0e16 528 goto out;
e4d6b795
MB		 529 }
530 offset >>= 2;
531 }
532 b43_shm_control_word(dev, routing, offset);
533 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 534out:
e4d6b795
MB		 535 return ret;
536}
537
69eddc8a 538void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 539{
e4d6b795
MB		 540 if (routing == B43_SHM_SHARED) {
541 B43_WARN_ON(offset & 0x0001);
542 if (offset & 0x0003) {
543 /* Unaligned access */
544 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 545 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 546 value & 0xFFFF);
e4d6b795 547 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 548 b43_write16(dev, B43_MMIO_SHM_DATA,
549 (value >> 16) & 0xFFFF);
6bbc321a 550 return;
e4d6b795
MB		 551 }
552 offset >>= 2;
553 }
554 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 555 b43_write32(dev, B43_MMIO_SHM_DATA, value);
556}
557
69eddc8a 558void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 559{
e4d6b795
MB		 560 if (routing == B43_SHM_SHARED) {
561 B43_WARN_ON(offset & 0x0001);
562 if (offset & 0x0003) {
563 /* Unaligned access */
564 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 565 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 566 return;
e4d6b795
MB		 567 }
568 offset >>= 2;
569 }
570 b43_shm_control_word(dev, routing, offset);
e4d6b795 571 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 572}
573
e4d6b795 574/* Read HostFlags */
99da185a 575u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 576{
35f0d354 577 u64 ret;
e4d6b795 578
6e6a2cd5 579 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
e4d6b795 580 ret <<= 16;
6e6a2cd5 581 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
35f0d354 582 ret <<= 16;
6e6a2cd5 583 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
e4d6b795
MB		 584
585 return ret;
586}
587
588/* Write HostFlags */
35f0d354 589void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 590{
35f0d354
MB		 591 u16 lo, mi, hi;
592
593 lo = (value & 0x00000000FFFFULL);
594 mi = (value & 0x0000FFFF0000ULL) >> 16;
595 hi = (value & 0xFFFF00000000ULL) >> 32;
6e6a2cd5
RM		 596 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
598 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
e4d6b795
MB		 599}
600
403a3a13
MB		 601/* Read the firmware capabilities bitmask (Opensource firmware only) */
602static u16 b43_fwcapa_read(struct b43_wldev *dev)
603{
604 B43_WARN_ON(!dev->fw.opensource);
605 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
606}
607
3ebbbb56 608void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 609{
3ebbbb56
MB		 610 u32 low, high;
611
21d889d4 612 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 613
614 /* The hardware guarantees us an atomic read, if we
615 * read the low register first. */
616 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
617 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
618
619 *tsf = high;
620 *tsf <<= 32;
621 *tsf |= low;
e4d6b795
MB		 622}
623
624static void b43_time_lock(struct b43_wldev *dev)
625{
5056635c 626 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
e4d6b795
MB		 627 /* Commit the write */
628 b43_read32(dev, B43_MMIO_MACCTL);
629}
630
631static void b43_time_unlock(struct b43_wldev *dev)
632{
5056635c 633 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
e4d6b795
MB		 634 /* Commit the write */
635 b43_read32(dev, B43_MMIO_MACCTL);
636}
637
638static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
639{
3ebbbb56
MB		 640 u32 low, high;
641
21d889d4 642 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 643
644 low = tsf;
645 high = (tsf >> 32);
646 /* The hardware guarantees us an atomic write, if we
647 * write the low register first. */
648 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
649 mmiowb();
650 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
651 mmiowb();
e4d6b795
MB		 652}
653
654void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
655{
656 b43_time_lock(dev);
657 b43_tsf_write_locked(dev, tsf);
658 b43_time_unlock(dev);
659}
660
661static
99da185a 662void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 663{
664 static const u8 zero_addr[ETH_ALEN] = { 0 };
665 u16 data;
666
667 if (!mac)
668 mac = zero_addr;
669
670 offset |= 0x0020;
671 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
672
673 data = mac[0];
674 data |= mac[1] << 8;
675 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
676 data = mac[2];
677 data |= mac[3] << 8;
678 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
679 data = mac[4];
680 data |= mac[5] << 8;
681 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
682}
683
684static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
685{
686 const u8 *mac;
687 const u8 *bssid;
688 u8 mac_bssid[ETH_ALEN * 2];
689 int i;
690 u32 tmp;
691
692 bssid = dev->wl->bssid;
693 mac = dev->wl->mac_addr;
694
695 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
696
697 memcpy(mac_bssid, mac, ETH_ALEN);
698 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
699
700 /* Write our MAC address and BSSID to template ram */
701 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
702 tmp = (u32) (mac_bssid[i + 0]);
703 tmp |= (u32) (mac_bssid[i + 1]) << 8;
704 tmp |= (u32) (mac_bssid[i + 2]) << 16;
705 tmp |= (u32) (mac_bssid[i + 3]) << 24;
706 b43_ram_write(dev, 0x20 + i, tmp);
707 }
708}
709
4150c572 710static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 711{
e4d6b795 712 b43_write_mac_bssid_templates(dev);
4150c572 713 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 714}
715
716static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
717{
718 /* slot_time is in usec. */
b6c3f5be
LF		 719 /* This test used to exit for all but a G PHY. */
720 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 721 return;
b6c3f5be
LF		 722 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
723 /* Shared memory location 0x0010 is the slot time and should be
724 * set to slot_time; however, this register is initially 0 and changing
725 * the value adversely affects the transmit rate for BCM4311
726 * devices. Until this behavior is unterstood, delete this step
727 *
728 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
729 */
e4d6b795
MB		 730}
731
732static void b43_short_slot_timing_enable(struct b43_wldev *dev)
733{
734 b43_set_slot_time(dev, 9);
e4d6b795
MB		 735}
736
737static void b43_short_slot_timing_disable(struct b43_wldev *dev)
738{
739 b43_set_slot_time(dev, 20);
e4d6b795
MB		 740}
741
e4d6b795 742/* DummyTransmission function, as documented on
2f19c287 743 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 744 */
2f19c287 745void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 746{
747 struct b43_phy *phy = &dev->phy;
748 unsigned int i, max_loop;
749 u16 value;
750 u32 buffer[5] = {
751 0x00000000,
752 0x00D40000,
753 0x00000000,
754 0x01000000,
755 0x00000000,
756 };
757
2f19c287 758 if (ofdm) {
e4d6b795
MB		 759 max_loop = 0x1E;
760 buffer[0] = 0x000201CC;
2f19c287 761 } else {
e4d6b795
MB		 762 max_loop = 0xFA;
763 buffer[0] = 0x000B846E;
e4d6b795
MB		 764 }
765
766 for (i = 0; i < 5; i++)
767 b43_ram_write(dev, i * 4, buffer[i]);
768
7955d87f
RM		 769 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
770
21d889d4 771 if (dev->dev->core_rev < 11)
7955d87f 772 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
2f19c287 773 else
7955d87f
RM		 774 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
775
2f19c287 776 value = (ofdm ? 0x41 : 0x40);
7955d87f 777 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
93dbd828
RM		 778 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
779 phy->type == B43_PHYTYPE_LCN)
7955d87f
RM		 780 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
781
782 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
783 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
784
785 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
786 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
787 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
788 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
93dbd828
RM		 789
790 if (!pa_on && phy->type == B43_PHYTYPE_N)
791 ; /*b43_nphy_pa_override(dev, false) */
2f19c287
GS		 792
793 switch (phy->type) {
794 case B43_PHYTYPE_N:
93dbd828 795 case B43_PHYTYPE_LCN:
7955d87f 796 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
2f19c287
GS		 797 break;
798 case B43_PHYTYPE_LP:
7955d87f 799 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
2f19c287
GS		 800 break;
801 default:
7955d87f 802 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
2f19c287 803 }
93dbd828 804 b43_read16(dev, B43_MMIO_TXE0_AUX);
e4d6b795
MB		 805
806 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
807 b43_radio_write16(dev, 0x0051, 0x0017);
808 for (i = 0x00; i < max_loop; i++) {
7955d87f 809 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 810 if (value & 0x0080)
811 break;
812 udelay(10);
813 }
814 for (i = 0x00; i < 0x0A; i++) {
7955d87f 815 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 816 if (value & 0x0400)
817 break;
818 udelay(10);
819 }
1d280ddc 820 for (i = 0x00; i < 0x19; i++) {
7955d87f 821 value = b43_read16(dev, B43_MMIO_IFSSTAT);
e4d6b795
MB		 822 if (!(value & 0x0100))
823 break;
824 udelay(10);
825 }
826 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
827 b43_radio_write16(dev, 0x0051, 0x0037);
828}
829
830static void key_write(struct b43_wldev *dev,
99da185a 831 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 832{
833 unsigned int i;
834 u32 offset;
835 u16 value;
836 u16 kidx;
837
838 /* Key index/algo block */
839 kidx = b43_kidx_to_fw(dev, index);
840 value = ((kidx << 4) | algorithm);
841 b43_shm_write16(dev, B43_SHM_SHARED,
842 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
843
844 /* Write the key to the Key Table Pointer offset */
845 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
846 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
847 value = key[i];
848 value |= (u16) (key[i + 1]) << 8;
849 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
850 }
851}
852
99da185a 853static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 854{
855 u32 addrtmp[2] = { 0, 0, };
66d2d089 856 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 857
858 if (b43_new_kidx_api(dev))
66d2d089 859 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 860
66d2d089
MB		 861 B43_WARN_ON(index < pairwise_keys_start);
862 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 863 * Physical mac 0 is mapped to physical key 4 or 8, depending
864 * on the firmware version.
865 * So we must adjust the index here.
866 */
66d2d089
MB		 867 index -= pairwise_keys_start;
868 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 869
870 if (addr) {
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
877 }
878
66d2d089
MB		 879 /* Receive match transmitter address (RCMTA) mechanism */
880 b43_shm_write32(dev, B43_SHM_RCMTA,
881 (index * 2) + 0, addrtmp[0]);
882 b43_shm_write16(dev, B43_SHM_RCMTA,
883 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 884}
885
035d0243 886/* The ucode will use phase1 key with TEK key to decrypt rx packets.
887 * When a packet is received, the iv32 is checked.
888 * - if it doesn't the packet is returned without modification (and software
889 * decryption can be done). That's what happen when iv16 wrap.
890 * - if it does, the rc4 key is computed, and decryption is tried.
891 * Either it will success and B43_RX_MAC_DEC is returned,
892 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
893 * and the packet is not usable (it got modified by the ucode).
894 * So in order to never have B43_RX_MAC_DECERR, we should provide
895 * a iv32 and phase1key that match. Because we drop packets in case of
896 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
897 * packets will be lost without higher layer knowing (ie no resync possible
898 * until next wrap).
899 *
900 * NOTE : this should support 50 key like RCMTA because
901 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
902 */
903static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
904 u16 *phase1key)
905{
906 unsigned int i;
907 u32 offset;
908 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
909
910 if (!modparam_hwtkip)
911 return;
912
913 if (b43_new_kidx_api(dev))
914 pairwise_keys_start = B43_NR_GROUP_KEYS;
915
916 B43_WARN_ON(index < pairwise_keys_start);
917 /* We have four default TX keys and possibly four default RX keys.
918 * Physical mac 0 is mapped to physical key 4 or 8, depending
919 * on the firmware version.
920 * So we must adjust the index here.
921 */
922 index -= pairwise_keys_start;
923 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
924
925 if (b43_debug(dev, B43_DBG_KEYS)) {
926 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
927 index, iv32);
928 }
929 /* Write the key to the RX tkip shared mem */
930 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
931 for (i = 0; i < 10; i += 2) {
932 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
933 phase1key ? phase1key[i / 2] : 0);
934 }
935 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
936 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
937}
938
939static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 940 struct ieee80211_vif *vif,
941 struct ieee80211_key_conf *keyconf,
942 struct ieee80211_sta *sta,
943 u32 iv32, u16 *phase1key)
035d0243 944{
945 struct b43_wl *wl = hw_to_b43_wl(hw);
946 struct b43_wldev *dev;
947 int index = keyconf->hw_key_idx;
948
949 if (B43_WARN_ON(!modparam_hwtkip))
950 return;
951
96869a39
MB		 952 /* This is only called from the RX path through mac80211, where
953 * our mutex is already locked. */
954 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 955 dev = wl->current_dev;
96869a39 956 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 957
958 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
959
960 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 961 /* only pairwise TKIP keys are supported right now */
962 if (WARN_ON(!sta))
96869a39 963 return;
b3fbdcf4 964 keymac_write(dev, index, sta->addr);
035d0243 965}
966
e4d6b795
MB		 967static void do_key_write(struct b43_wldev *dev,
968 u8 index, u8 algorithm,
99da185a 969 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 970{
971 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 972 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 973
974 if (b43_new_kidx_api(dev))
66d2d089 975 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 976
66d2d089 977 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 978 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
979
66d2d089 980 if (index >= pairwise_keys_start)
e4d6b795 981 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 982 if (algorithm == B43_SEC_ALGO_TKIP) {
983 /*
984 * We should provide an initial iv32, phase1key pair.
985 * We could start with iv32=0 and compute the corresponding
986 * phase1key, but this means calling ieee80211_get_tkip_key
987 * with a fake skb (or export other tkip function).
988 * Because we are lazy we hope iv32 won't start with
989 * 0xffffffff and let's b43_op_update_tkip_key provide a
990 * correct pair.
991 */
992 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
993 } else if (index >= pairwise_keys_start) /* clear it */
994 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 995 if (key)
996 memcpy(buf, key, key_len);
997 key_write(dev, index, algorithm, buf);
66d2d089 998 if (index >= pairwise_keys_start)
e4d6b795
MB		 999 keymac_write(dev, index, mac_addr);
1000
1001 dev->key[index].algorithm = algorithm;
1002}
1003
1004static int b43_key_write(struct b43_wldev *dev,
1005 int index, u8 algorithm,
99da185a
JD		 1006 const u8 *key, size_t key_len,
1007 const u8 *mac_addr,
e4d6b795
MB		 1008 struct ieee80211_key_conf *keyconf)
1009{
1010 int i;
66d2d089 1011 int pairwise_keys_start;
e4d6b795 1012
035d0243 1013 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
1014 * - Temporal Encryption Key (128 bits)
1015 * - Temporal Authenticator Tx MIC Key (64 bits)
1016 * - Temporal Authenticator Rx MIC Key (64 bits)
1017 *
1018 * Hardware only store TEK
1019 */
1020 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
1021 key_len = 16;
e4d6b795
MB		 1022 if (key_len > B43_SEC_KEYSIZE)
1023 return -EINVAL;
66d2d089 1024 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 1025 /* Check that we don't already have this key. */
1026 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1027 }
1028 if (index < 0) {
e808e586 1029 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 1030 if (b43_new_kidx_api(dev))
66d2d089 1031 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 1032 else
66d2d089
MB		 1033 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1034 for (i = pairwise_keys_start;
1035 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1036 i++) {
1037 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 1038 if (!dev->key[i].keyconf) {
1039 /* found empty */
1040 index = i;
1041 break;
1042 }
1043 }
1044 if (index < 0) {
e808e586 1045 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1046 return -ENOSPC;
1047 }
1048 } else
1049 B43_WARN_ON(index > 3);
1050
1051 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1052 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1053 /* Default RX key */
1054 B43_WARN_ON(mac_addr);
1055 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1056 }
1057 keyconf->hw_key_idx = index;
1058 dev->key[index].keyconf = keyconf;
1059
1060 return 0;
1061}
1062
1063static int b43_key_clear(struct b43_wldev *dev, int index)
1064{
66d2d089 1065 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1066 return -EINVAL;
1067 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1068 NULL, B43_SEC_KEYSIZE, NULL);
1069 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1070 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1071 NULL, B43_SEC_KEYSIZE, NULL);
1072 }
1073 dev->key[index].keyconf = NULL;
1074
1075 return 0;
1076}
1077
1078static void b43_clear_keys(struct b43_wldev *dev)
1079{
66d2d089 1080 int i, count;
e4d6b795 1081
66d2d089
MB		 1082 if (b43_new_kidx_api(dev))
1083 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1084 else
1085 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1086 for (i = 0; i < count; i++)
e4d6b795
MB		 1087 b43_key_clear(dev, i);
1088}
1089
9cf7f247
MB		 1090static void b43_dump_keymemory(struct b43_wldev *dev)
1091{
66d2d089 1092 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1093 u8 mac[ETH_ALEN];
1094 u16 algo;
1095 u32 rcmta0;
1096 u16 rcmta1;
1097 u64 hf;
1098 struct b43_key *key;
1099
1100 if (!b43_debug(dev, B43_DBG_KEYS))
1101 return;
1102
1103 hf = b43_hf_read(dev);
1104 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1105 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1106 if (b43_new_kidx_api(dev)) {
1107 pairwise_keys_start = B43_NR_GROUP_KEYS;
1108 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1109 } else {
1110 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1111 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1112 }
1113 for (index = 0; index < count; index++) {
9cf7f247
MB		 1114 key = &(dev->key[index]);
1115 printk(KERN_DEBUG "Key slot %02u: %s",
1116 index, (key->keyconf == NULL) ? " " : "*");
1117 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1118 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1119 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1120 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1121 }
1122
1123 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1124 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1125 printk(" Algo: %04X/%02X", algo, key->algorithm);
1126
66d2d089 1127 if (index >= pairwise_keys_start) {
035d0243 1128 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1129 printk(" TKIP: ");
1130 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1131 for (i = 0; i < 14; i += 2) {
1132 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1133 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1134 }
1135 }
9cf7f247 1136 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1137 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1138 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1139 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1140 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1141 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1142 printk(" MAC: %pM", mac);
9cf7f247
MB		 1143 } else
1144 printk(" DEFAULT KEY");
1145 printk("\n");
1146 }
1147}
1148
e4d6b795
MB		 1149void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1150{
1151 u32 macctl;
1152 u16 ucstat;
1153 bool hwps;
1154 bool awake;
1155 int i;
1156
1157 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1158 (ps_flags & B43_PS_DISABLED));
1159 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1160
1161 if (ps_flags & B43_PS_ENABLED) {
3db1cd5c 1162 hwps = true;
e4d6b795 1163 } else if (ps_flags & B43_PS_DISABLED) {
3db1cd5c 1164 hwps = false;
e4d6b795
MB		 1165 } else {
1166 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1167 // and thus is not an AP and we are associated, set bit 25
1168 }
1169 if (ps_flags & B43_PS_AWAKE) {
3db1cd5c 1170 awake = true;
e4d6b795 1171 } else if (ps_flags & B43_PS_ASLEEP) {
3db1cd5c 1172 awake = false;
e4d6b795
MB		 1173 } else {
1174 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1175 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1176 // successful, set bit26
1177 }
1178
1179/* FIXME: For now we force awake-on and hwps-off */
3db1cd5c
RR		 1180 hwps = false;
1181 awake = true;
e4d6b795
MB		 1182
1183 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1184 if (hwps)
1185 macctl |= B43_MACCTL_HWPS;
1186 else
1187 macctl &= ~B43_MACCTL_HWPS;
1188 if (awake)
1189 macctl |= B43_MACCTL_AWAKE;
1190 else
1191 macctl &= ~B43_MACCTL_AWAKE;
1192 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1193 /* Commit write */
1194 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1195 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1196 /* Wait for the microcode to wake up. */
1197 for (i = 0; i < 100; i++) {
1198 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1199 B43_SHM_SH_UCODESTAT);
1200 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1201 break;
1202 udelay(10);
1203 }
1204 }
1205}
1206
42c9a458 1207#ifdef CONFIG_B43_BCMA
49173592 1208static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1209{
49173592 1210 u32 flags;
42c9a458 1211
49173592
RM		 1212 /* Put PHY into reset */
1213 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1214 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1215 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1216 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1217 udelay(2);
1218
50c1b59e 1219 b43_phy_take_out_of_reset(dev);
49173592 1220}
42c9a458 1221
49173592
RM		 1222static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1223{
88cceab5
RM		 1224 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1225 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1226 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1227 B43_BCMA_CLKCTLST_PHY_PLL_ST;
6b9e03e6
RM		 1228 u32 flags;
1229
1230 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1231 if (gmode)
1232 flags |= B43_BCMA_IOCTL_GMODE;
1233 b43_device_enable(dev, flags);
88cceab5 1234
49173592
RM		 1235 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1236 b43_bcma_phy_reset(dev);
88cceab5 1237 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
42c9a458
RM		 1238}
1239#endif
1240
bd7c8a59 1241#ifdef CONFIG_B43_SSB
4da909e7 1242static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1243{
4da909e7 1244 u32 flags = 0;
e4d6b795 1245
4da909e7
RM		 1246 if (gmode)
1247 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1248 flags |= B43_TMSLOW_PHYCLKEN;
1249 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1250 if (dev->phy.type == B43_PHYTYPE_N)
1251 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1252 b43_device_enable(dev, flags);
e4d6b795
MB		 1253 msleep(2); /* Wait for the PLL to turn on. */
1254
50c1b59e 1255 b43_phy_take_out_of_reset(dev);
1495298d 1256}
bd7c8a59 1257#endif
1495298d 1258
4da909e7 1259void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1260{
1261 u32 macctl;
1262
6cbab0d9 1263 switch (dev->dev->bus_type) {
42c9a458
RM		 1264#ifdef CONFIG_B43_BCMA
1265 case B43_BUS_BCMA:
1266 b43_bcma_wireless_core_reset(dev, gmode);
1267 break;
1268#endif
6cbab0d9
RM		 1269#ifdef CONFIG_B43_SSB
1270 case B43_BUS_SSB:
1271 b43_ssb_wireless_core_reset(dev, gmode);
1272 break;
1273#endif
1274 }
e4d6b795 1275
fb11137a
MB		 1276 /* Turn Analog ON, but only if we already know the PHY-type.
1277 * This protects against very early setup where we don't know the
1278 * PHY-type, yet. wireless_core_reset will be called once again later,
1279 * when we know the PHY-type. */
1280 if (dev->phy.ops)
cb24f57f 1281 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1282
1283 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1284 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1285 if (gmode)
e4d6b795
MB		 1286 macctl |= B43_MACCTL_GMODE;
1287 macctl |= B43_MACCTL_IHR_ENABLED;
1288 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1289}
1290
1291static void handle_irq_transmit_status(struct b43_wldev *dev)
1292{
1293 u32 v0, v1;
1294 u16 tmp;
1295 struct b43_txstatus stat;
1296
1297 while (1) {
1298 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1299 if (!(v0 & 0x00000001))
1300 break;
1301 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1302
1303 stat.cookie = (v0 >> 16);
1304 stat.seq = (v1 & 0x0000FFFF);
1305 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1306 tmp = (v0 & 0x0000FFFF);
1307 stat.frame_count = ((tmp & 0xF000) >> 12);
1308 stat.rts_count = ((tmp & 0x0F00) >> 8);
1309 stat.supp_reason = ((tmp & 0x001C) >> 2);
1310 stat.pm_indicated = !!(tmp & 0x0080);
1311 stat.intermediate = !!(tmp & 0x0040);
1312 stat.for_ampdu = !!(tmp & 0x0020);
1313 stat.acked = !!(tmp & 0x0002);
1314
1315 b43_handle_txstatus(dev, &stat);
1316 }
1317}
1318
1319static void drain_txstatus_queue(struct b43_wldev *dev)
1320{
1321 u32 dummy;
1322
21d889d4 1323 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1324 return;
1325 /* Read all entries from the microcode TXstatus FIFO
1326 * and throw them away.
1327 */
1328 while (1) {
1329 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1330 if (!(dummy & 0x00000001))
1331 break;
1332 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1333 }
1334}
1335
1336static u32 b43_jssi_read(struct b43_wldev *dev)
1337{
1338 u32 val = 0;
1339
5c1da23b 1340 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
e4d6b795 1341 val <<= 16;
5c1da23b 1342 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
e4d6b795
MB		 1343
1344 return val;
1345}
1346
1347static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1348{
5c1da23b
HM		 1349 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1350 (jssi & 0x0000FFFF));
1351 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1352 (jssi & 0xFFFF0000) >> 16);
e4d6b795
MB		 1353}
1354
1355static void b43_generate_noise_sample(struct b43_wldev *dev)
1356{
1357 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1358 b43_write32(dev, B43_MMIO_MACCMD,
1359 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1360}
1361
1362static void b43_calculate_link_quality(struct b43_wldev *dev)
1363{
1364 /* Top half of Link Quality calculation. */
1365
ef1a628d
MB		 1366 if (dev->phy.type != B43_PHYTYPE_G)
1367 return;
e4d6b795
MB		 1368 if (dev->noisecalc.calculation_running)
1369 return;
3db1cd5c 1370 dev->noisecalc.calculation_running = true;
e4d6b795
MB		 1371 dev->noisecalc.nr_samples = 0;
1372
1373 b43_generate_noise_sample(dev);
1374}
1375
1376static void handle_irq_noise(struct b43_wldev *dev)
1377{
ef1a628d 1378 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1379 u16 tmp;
1380 u8 noise[4];
1381 u8 i, j;
1382 s32 average;
1383
1384 /* Bottom half of Link Quality calculation. */
1385
ef1a628d
MB		 1386 if (dev->phy.type != B43_PHYTYPE_G)
1387 return;
1388
98a3b2fe
MB		 1389 /* Possible race condition: It might be possible that the user
1390 * changed to a different channel in the meantime since we
1391 * started the calculation. We ignore that fact, since it's
1392 * not really that much of a problem. The background noise is
1393 * an estimation only anyway. Slightly wrong results will get damped
1394 * by the averaging of the 8 sample rounds. Additionally the
1395 * value is shortlived. So it will be replaced by the next noise
1396 * calculation round soon. */
1397
e4d6b795 1398 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1399 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1400 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1401 noise[2] == 0x7F || noise[3] == 0x7F)
1402 goto generate_new;
1403
1404 /* Get the noise samples. */
1405 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1406 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1407 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1408 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1409 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1410 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1411 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1412 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1413 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1414 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1415 dev->noisecalc.nr_samples++;
1416 if (dev->noisecalc.nr_samples == 8) {
1417 /* Calculate the Link Quality by the noise samples. */
1418 average = 0;
1419 for (i = 0; i < 8; i++) {
1420 for (j = 0; j < 4; j++)
1421 average += dev->noisecalc.samples[i][j];
1422 }
1423 average /= (8 * 4);
1424 average *= 125;
1425 average += 64;
1426 average /= 128;
1427 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1428 tmp = (tmp / 128) & 0x1F;
1429 if (tmp >= 8)
1430 average += 2;
1431 else
1432 average -= 25;
1433 if (tmp == 8)
1434 average -= 72;
1435 else
1436 average -= 48;
1437
1438 dev->stats.link_noise = average;
3db1cd5c 1439 dev->noisecalc.calculation_running = false;
e4d6b795
MB		 1440 return;
1441 }
98a3b2fe 1442generate_new:
e4d6b795
MB		 1443 b43_generate_noise_sample(dev);
1444}
1445
1446static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1447{
05c914fe 1448 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1449 ///TODO: PS TBTT
1450 } else {
1451 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1452 b43_power_saving_ctl_bits(dev, 0);
1453 }
05c914fe 1454 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3db1cd5c 1455 dev->dfq_valid = true;
e4d6b795
MB		 1456}
1457
1458static void handle_irq_atim_end(struct b43_wldev *dev)
1459{
aa6c7ae2
MB		 1460 if (dev->dfq_valid) {
1461 b43_write32(dev, B43_MMIO_MACCMD,
1462 b43_read32(dev, B43_MMIO_MACCMD)
1463 | B43_MACCMD_DFQ_VALID);
3db1cd5c 1464 dev->dfq_valid = false;
aa6c7ae2 1465 }
e4d6b795
MB		 1466}
1467
1468static void handle_irq_pmq(struct b43_wldev *dev)
1469{
1470 u32 tmp;
1471
1472 //TODO: AP mode.
1473
1474 while (1) {
1475 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1476 if (!(tmp & 0x00000008))
1477 break;
1478 }
1479 /* 16bit write is odd, but correct. */
1480 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1481}
1482
1483static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1484 const u8 *data, u16 size,
e4d6b795
MB		 1485 u16 ram_offset,
1486 u16 shm_size_offset, u8 rate)
1487{
1488 u32 i, tmp;
1489 struct b43_plcp_hdr4 plcp;
1490
1491 plcp.data = 0;
1492 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1493 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1494 ram_offset += sizeof(u32);
1495 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1496 * So leave the first two bytes of the next write blank.
1497 */
1498 tmp = (u32) (data[0]) << 16;
1499 tmp |= (u32) (data[1]) << 24;
1500 b43_ram_write(dev, ram_offset, tmp);
1501 ram_offset += sizeof(u32);
1502 for (i = 2; i < size; i += sizeof(u32)) {
1503 tmp = (u32) (data[i + 0]);
1504 if (i + 1 < size)
1505 tmp |= (u32) (data[i + 1]) << 8;
1506 if (i + 2 < size)
1507 tmp |= (u32) (data[i + 2]) << 16;
1508 if (i + 3 < size)
1509 tmp |= (u32) (data[i + 3]) << 24;
1510 b43_ram_write(dev, ram_offset + i - 2, tmp);
1511 }
1512 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1513 size + sizeof(struct b43_plcp_hdr6));
1514}
1515
5042c507
MB		 1516/* Check if the use of the antenna that ieee80211 told us to
1517 * use is possible. This will fall back to DEFAULT.
1518 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1519u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1520 u8 antenna_nr)
1521{
1522 u8 antenna_mask;
1523
1524 if (antenna_nr == 0) {
1525 /* Zero means "use default antenna". That's always OK. */
1526 return 0;
1527 }
1528
1529 /* Get the mask of available antennas. */
1530 if (dev->phy.gmode)
0581483a 1531 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1532 else
0581483a 1533 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1534
1535 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1536 /* This antenna is not available. Fall back to default. */
1537 return 0;
1538 }
1539
1540 return antenna_nr;
1541}
1542
5042c507
MB		 1543/* Convert a b43 antenna number value to the PHY TX control value. */
1544static u16 b43_antenna_to_phyctl(int antenna)
1545{
1546 switch (antenna) {
1547 case B43_ANTENNA0:
1548 return B43_TXH_PHY_ANT0;
1549 case B43_ANTENNA1:
1550 return B43_TXH_PHY_ANT1;
1551 case B43_ANTENNA2:
1552 return B43_TXH_PHY_ANT2;
1553 case B43_ANTENNA3:
1554 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1555 case B43_ANTENNA_AUTO0:
1556 case B43_ANTENNA_AUTO1:
5042c507
MB		 1557 return B43_TXH_PHY_ANT01AUTO;
1558 }
1559 B43_WARN_ON(1);
1560 return 0;
1561}
1562
e4d6b795
MB		 1563static void b43_write_beacon_template(struct b43_wldev *dev,
1564 u16 ram_offset,
5042c507 1565 u16 shm_size_offset)
e4d6b795 1566{
47f76ca3 1567 unsigned int i, len, variable_len;
e66fee6a
MB		 1568 const struct ieee80211_mgmt *bcn;
1569 const u8 *ie;
3db1cd5c 1570 bool tim_found = false;
5042c507
MB		 1571 unsigned int rate;
1572 u16 ctl;
1573 int antenna;
e039fa4a 1574 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1575
e66fee6a 1576 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
c8e49556 1577 len = min_t(size_t, dev->wl->current_beacon->len,
e4d6b795 1578 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1579 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1580
1581 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1582 len, ram_offset, shm_size_offset, rate);
e66fee6a 1583
5042c507 1584 /* Write the PHY TX control parameters. */
0f4ac38b 1585 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1586 antenna = b43_antenna_to_phyctl(antenna);
1587 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1588 /* We can't send beacons with short preamble. Would get PHY errors. */
1589 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1590 ctl &= ~B43_TXH_PHY_ANT;
1591 ctl &= ~B43_TXH_PHY_ENC;
1592 ctl |= antenna;
1593 if (b43_is_cck_rate(rate))
1594 ctl |= B43_TXH_PHY_ENC_CCK;
1595 else
1596 ctl |= B43_TXH_PHY_ENC_OFDM;
1597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1598
e66fee6a
MB		 1599 /* Find the position of the TIM and the DTIM_period value
1600 * and write them to SHM. */
1601 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1602 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1603 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1604 uint8_t ie_id, ie_len;
1605
1606 ie_id = ie[i];
1607 ie_len = ie[i + 1];
1608 if (ie_id == 5) {
1609 u16 tim_position;
1610 u16 dtim_period;
1611 /* This is the TIM Information Element */
1612
1613 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1614 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1615 break;
1616 /* A valid TIM is at least 4 bytes long. */
1617 if (ie_len < 4)
1618 break;
3db1cd5c 1619 tim_found = true;
e66fee6a
MB		 1620
1621 tim_position = sizeof(struct b43_plcp_hdr6);
1622 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1623 tim_position += i;
1624
1625 dtim_period = ie[i + 3];
1626
1627 b43_shm_write16(dev, B43_SHM_SHARED,
1628 B43_SHM_SH_TIMBPOS, tim_position);
1629 b43_shm_write16(dev, B43_SHM_SHARED,
1630 B43_SHM_SH_DTIMPER, dtim_period);
1631 break;
1632 }
1633 i += ie_len + 2;
1634 }
1635 if (!tim_found) {
04dea136
JB		 1636 /*
1637 * If ucode wants to modify TIM do it behind the beacon, this
1638 * will happen, for example, when doing mesh networking.
1639 */
1640 b43_shm_write16(dev, B43_SHM_SHARED,
1641 B43_SHM_SH_TIMBPOS,
1642 len + sizeof(struct b43_plcp_hdr6));
1643 b43_shm_write16(dev, B43_SHM_SHARED,
1644 B43_SHM_SH_DTIMPER, 0);
1645 }
1646 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1647}
1648
6b4bec01
MB		 1649static void b43_upload_beacon0(struct b43_wldev *dev)
1650{
1651 struct b43_wl *wl = dev->wl;
1652
1653 if (wl->beacon0_uploaded)
1654 return;
5c1da23b 1655 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
3db1cd5c 1656 wl->beacon0_uploaded = true;
6b4bec01
MB		 1657}
1658
1659static void b43_upload_beacon1(struct b43_wldev *dev)
1660{
1661 struct b43_wl *wl = dev->wl;
1662
1663 if (wl->beacon1_uploaded)
1664 return;
5c1da23b 1665 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
3db1cd5c 1666 wl->beacon1_uploaded = true;
6b4bec01
MB		 1667}
1668
c97a4ccc
MB		 1669static void handle_irq_beacon(struct b43_wldev *dev)
1670{
1671 struct b43_wl *wl = dev->wl;
1672 u32 cmd, beacon0_valid, beacon1_valid;
1673
05c914fe 1674 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
8c23516f
MM		 1675 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1676 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
c97a4ccc
MB		 1677 return;
1678
1679 /* This is the bottom half of the asynchronous beacon update. */
1680
1681 /* Ignore interrupt in the future. */
13790728 1682 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1683
1684 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1685 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1686 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1687
1688 /* Schedule interrupt manually, if busy. */
1689 if (beacon0_valid && beacon1_valid) {
1690 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1691 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1692 return;
1693 }
1694
6b4bec01
MB		 1695 if (unlikely(wl->beacon_templates_virgin)) {
1696 /* We never uploaded a beacon before.
1697 * Upload both templates now, but only mark one valid. */
3db1cd5c 1698 wl->beacon_templates_virgin = false;
6b4bec01
MB		 1699 b43_upload_beacon0(dev);
1700 b43_upload_beacon1(dev);
c97a4ccc
MB		 1701 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1702 cmd |= B43_MACCMD_BEACON0_VALID;
1703 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1704 } else {
1705 if (!beacon0_valid) {
1706 b43_upload_beacon0(dev);
1707 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1708 cmd |= B43_MACCMD_BEACON0_VALID;
1709 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1710 } else if (!beacon1_valid) {
1711 b43_upload_beacon1(dev);
1712 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1713 cmd |= B43_MACCMD_BEACON1_VALID;
1714 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1715 }
c97a4ccc
MB		 1716 }
1717}
1718
36dbd954
MB		 1719static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1720{
1721 u32 old_irq_mask = dev->irq_mask;
1722
1723 /* update beacon right away or defer to irq */
1724 handle_irq_beacon(dev);
1725 if (old_irq_mask != dev->irq_mask) {
1726 /* The handler updated the IRQ mask. */
1727 B43_WARN_ON(!dev->irq_mask);
1728 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1729 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1730 } else {
1731 /* Device interrupts are currently disabled. That means
1732 * we just ran the hardirq handler and scheduled the
1733 * IRQ thread. The thread will write the IRQ mask when
1734 * it finished, so there's nothing to do here. Writing
1735 * the mask _here_ would incorrectly re-enable IRQs. */
1736 }
1737 }
1738}
1739
a82d9922
MB		 1740static void b43_beacon_update_trigger_work(struct work_struct *work)
1741{
1742 struct b43_wl *wl = container_of(work, struct b43_wl,
1743 beacon_update_trigger);
1744 struct b43_wldev *dev;
1745
1746 mutex_lock(&wl->mutex);
1747 dev = wl->current_dev;
1748 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1749 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1750 /* wl->mutex is enough. */
1751 b43_do_beacon_update_trigger_work(dev);
1752 mmiowb();
1753 } else {
1754 spin_lock_irq(&wl->hardirq_lock);
1755 b43_do_beacon_update_trigger_work(dev);
1756 mmiowb();
1757 spin_unlock_irq(&wl->hardirq_lock);
1758 }
a82d9922
MB		 1759 }
1760 mutex_unlock(&wl->mutex);
1761}
1762
d4df6f1a 1763/* Asynchronously update the packet templates in template RAM.
36dbd954 1764 * Locking: Requires wl->mutex to be locked. */
9d139c81 1765static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1766{
9d139c81
JB		 1767 struct sk_buff *beacon;
1768
e66fee6a
MB		 1769 /* This is the top half of the ansynchronous beacon update.
1770 * The bottom half is the beacon IRQ.
1771 * Beacon update must be asynchronous to avoid sending an
1772 * invalid beacon. This can happen for example, if the firmware
1773 * transmits a beacon while we are updating it. */
e4d6b795 1774
9d139c81
JB		 1775 /* We could modify the existing beacon and set the aid bit in
1776 * the TIM field, but that would probably require resizing and
1777 * moving of data within the beacon template.
1778 * Simply request a new beacon and let mac80211 do the hard work. */
1779 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1780 if (unlikely(!beacon))
1781 return;
1782
e66fee6a
MB		 1783 if (wl->current_beacon)
1784 dev_kfree_skb_any(wl->current_beacon);
1785 wl->current_beacon = beacon;
3db1cd5c
RR		 1786 wl->beacon0_uploaded = false;
1787 wl->beacon1_uploaded = false;
42935eca 1788 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1789}
1790
e4d6b795
MB		 1791static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1792{
1793 b43_time_lock(dev);
21d889d4 1794 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1795 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1796 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1797 } else {
1798 b43_write16(dev, 0x606, (beacon_int >> 6));
1799 b43_write16(dev, 0x610, beacon_int);
1800 }
1801 b43_time_unlock(dev);
a82d9922 1802 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1803}
1804
afa83e23
MB		 1805static void b43_handle_firmware_panic(struct b43_wldev *dev)
1806{
1807 u16 reason;
1808
1809 /* Read the register that contains the reason code for the panic. */
1810 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1811 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1812
1813 switch (reason) {
1814 default:
1815 b43dbg(dev->wl, "The panic reason is unknown.\n");
1816 /* fallthrough */
1817 case B43_FWPANIC_DIE:
1818 /* Do not restart the controller or firmware.
1819 * The device is nonfunctional from now on.
1820 * Restarting would result in this panic to trigger again,
1821 * so we avoid that recursion. */
1822 break;
1823 case B43_FWPANIC_RESTART:
1824 b43_controller_restart(dev, "Microcode panic");
1825 break;
1826 }
1827}
1828
e4d6b795
MB		 1829static void handle_irq_ucode_debug(struct b43_wldev *dev)
1830{
e48b0eeb 1831 unsigned int i, cnt;
53c06856 1832 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1833 __le16 *buf;
1834
1835 /* The proprietary firmware doesn't have this IRQ. */
1836 if (!dev->fw.opensource)
1837 return;
1838
afa83e23
MB		 1839 /* Read the register that contains the reason code for this IRQ. */
1840 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1841
e48b0eeb
MB		 1842 switch (reason) {
1843 case B43_DEBUGIRQ_PANIC:
afa83e23 1844 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1845 break;
1846 case B43_DEBUGIRQ_DUMP_SHM:
1847 if (!B43_DEBUG)
1848 break; /* Only with driver debugging enabled. */
1849 buf = kmalloc(4096, GFP_ATOMIC);
1850 if (!buf) {
1851 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1852 goto out;
1853 }
1854 for (i = 0; i < 4096; i += 2) {
1855 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1856 buf[i / 2] = cpu_to_le16(tmp);
1857 }
1858 b43info(dev->wl, "Shared memory dump:\n");
1859 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1860 16, 2, buf, 4096, 1);
1861 kfree(buf);
1862 break;
1863 case B43_DEBUGIRQ_DUMP_REGS:
1864 if (!B43_DEBUG)
1865 break; /* Only with driver debugging enabled. */
1866 b43info(dev->wl, "Microcode register dump:\n");
1867 for (i = 0, cnt = 0; i < 64; i++) {
1868 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1869 if (cnt == 0)
1870 printk(KERN_INFO);
1871 printk("r%02u: 0x%04X ", i, tmp);
1872 cnt++;
1873 if (cnt == 6) {
1874 printk("\n");
1875 cnt = 0;
1876 }
1877 }
1878 printk("\n");
1879 break;
53c06856
MB		 1880 case B43_DEBUGIRQ_MARKER:
1881 if (!B43_DEBUG)
1882 break; /* Only with driver debugging enabled. */
1883 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1884 B43_MARKER_ID_REG);
1885 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1886 B43_MARKER_LINE_REG);
1887 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1888 "at line number %u\n",
1889 marker_id, marker_line);
1890 break;
e48b0eeb
MB		 1891 default:
1892 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1893 reason);
1894 }
1895out:
afa83e23
MB		 1896 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1897 b43_shm_write16(dev, B43_SHM_SCRATCH,
1898 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1899}
1900
36dbd954 1901static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1902{
1903 u32 reason;
1904 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1905 u32 merged_dma_reason = 0;
21954c36 1906 int i;
e4d6b795 1907
36dbd954
MB		 1908 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1909 return;
e4d6b795
MB		 1910
1911 reason = dev->irq_reason;
1912 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1913 dma_reason[i] = dev->dma_reason[i];
1914 merged_dma_reason |= dma_reason[i];
1915 }
1916
1917 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1918 b43err(dev->wl, "MAC transmission error\n");
1919
00e0b8cb 1920 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1921 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1922 rmb();
1923 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1924 atomic_set(&dev->phy.txerr_cnt,
1925 B43_PHY_TX_BADNESS_LIMIT);
1926 b43err(dev->wl, "Too many PHY TX errors, "
1927 "restarting the controller\n");
1928 b43_controller_restart(dev, "PHY TX errors");
1929 }
1930 }
e4d6b795 1931
73b82bf0
TJ		 1932 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
1933 b43err(dev->wl,
1934 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1935 dma_reason[0], dma_reason[1],
1936 dma_reason[2], dma_reason[3],
1937 dma_reason[4], dma_reason[5]);
1938 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1939 "on your system. It will now be switched to PIO.\n");
73b82bf0
TJ		 1940 /* Fall back to PIO transfers if we get fatal DMA errors! */
1941 dev->use_pio = true;
1942 b43_controller_restart(dev, "DMA error");
1943 return;
e4d6b795
MB		 1944 }
1945
1946 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1947 handle_irq_ucode_debug(dev);
1948 if (reason & B43_IRQ_TBTT_INDI)
1949 handle_irq_tbtt_indication(dev);
1950 if (reason & B43_IRQ_ATIM_END)
1951 handle_irq_atim_end(dev);
1952 if (reason & B43_IRQ_BEACON)
1953 handle_irq_beacon(dev);
1954 if (reason & B43_IRQ_PMQ)
1955 handle_irq_pmq(dev);
21954c36
MB		 1956 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1957 ;/* TODO */
1958 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1959 handle_irq_noise(dev);
1960
1961 /* Check the DMA reason registers for received data. */
73b82bf0
TJ		 1962 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
1963 if (B43_DEBUG)
1964 b43warn(dev->wl, "RX descriptor underrun\n");
1965 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
1966 }
5100d5ac
MB		 1967 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1968 if (b43_using_pio_transfers(dev))
1969 b43_pio_rx(dev->pio.rx_queue);
1970 else
1971 b43_dma_rx(dev->dma.rx_ring);
1972 }
e4d6b795
MB		 1973 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1974 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1975 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1976 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1977 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1978
21954c36 1979 if (reason & B43_IRQ_TX_OK)
e4d6b795 1980 handle_irq_transmit_status(dev);
e4d6b795 1981
36dbd954 1982 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1983 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1984
1985#if B43_DEBUG
1986 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1987 dev->irq_count++;
1988 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1989 if (reason & (1 << i))
1990 dev->irq_bit_count[i]++;
1991 }
1992 }
1993#endif
e4d6b795
MB		 1994}
1995
36dbd954
MB		 1996/* Interrupt thread handler. Handles device interrupts in thread context. */
1997static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1998{
36dbd954 1999 struct b43_wldev *dev = dev_id;
e4d6b795 2000
36dbd954
MB		 2001 mutex_lock(&dev->wl->mutex);
2002 b43_do_interrupt_thread(dev);
2003 mmiowb();
2004 mutex_unlock(&dev->wl->mutex);
2005
2006 return IRQ_HANDLED;
e4d6b795
MB		 2007}
2008
36dbd954 2009static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 2010{
e4d6b795
MB		 2011 u32 reason;
2012
36dbd954
MB		 2013 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
2014 * On SDIO, this runs under wl->mutex. */
e4d6b795 2015
e4d6b795
MB		 2016 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2017 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 2018 return IRQ_NONE;
13790728 2019 reason &= dev->irq_mask;
e4d6b795 2020 if (!reason)
cae56147 2021 return IRQ_NONE;
e4d6b795
MB		 2022
2023 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
73b82bf0 2024 & 0x0001FC00;
e4d6b795
MB		 2025 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2026 & 0x0000DC00;
2027 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2028 & 0x0000DC00;
2029 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2030 & 0x0001DC00;
2031 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2032 & 0x0000DC00;
13790728 2033/* Unused ring
e4d6b795
MB		 2034 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2035 & 0x0000DC00;
13790728 2036*/
e4d6b795 2037
36dbd954
MB		 2038 /* ACK the interrupt. */
2039 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2040 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2041 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2042 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2043 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2044 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2045/* Unused ring
2046 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2047*/
2048
2049 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2050 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2051 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2052 dev->irq_reason = reason;
36dbd954
MB		 2053
2054 return IRQ_WAKE_THREAD;
2055}
2056
2057/* Interrupt handler top-half. This runs with interrupts disabled. */
2058static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2059{
2060 struct b43_wldev *dev = dev_id;
2061 irqreturn_t ret;
2062
2063 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2064 return IRQ_NONE;
2065
2066 spin_lock(&dev->wl->hardirq_lock);
2067 ret = b43_do_interrupt(dev);
e4d6b795 2068 mmiowb();
36dbd954 2069 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2070
2071 return ret;
2072}
2073
3dbba8e2
AH		 2074/* SDIO interrupt handler. This runs in process context. */
2075static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2076{
2077 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2078 irqreturn_t ret;
2079
3dbba8e2 2080 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2081
2082 ret = b43_do_interrupt(dev);
2083 if (ret == IRQ_WAKE_THREAD)
2084 b43_do_interrupt_thread(dev);
2085
3dbba8e2
AH		 2086 mutex_unlock(&wl->mutex);
2087}
2088
1a9f5093 2089void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2090{
2091 release_firmware(fw->data);
2092 fw->data = NULL;
2093 fw->filename = NULL;
2094}
2095
e4d6b795
MB		 2096static void b43_release_firmware(struct b43_wldev *dev)
2097{
0673effd 2098 complete(&dev->fw_load_complete);
1a9f5093
MB		 2099 b43_do_release_fw(&dev->fw.ucode);
2100 b43_do_release_fw(&dev->fw.pcm);
2101 b43_do_release_fw(&dev->fw.initvals);
2102 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2103}
2104
eb189d8b 2105static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2106{
fc68ed4f
HE		 2107 const char text[] =
2108 "You must go to " \
2109 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2110 "and download the correct firmware for this driver version. " \
2111 "Please carefully read all instructions on this website.\n";
eb189d8b 2112
eb189d8b
MB		 2113 if (error)
2114 b43err(wl, text);
2115 else
2116 b43warn(wl, text);
e4d6b795
MB		 2117}
2118
5e20a4b5
LF		 2119static void b43_fw_cb(const struct firmware *firmware, void *context)
2120{
2121 struct b43_request_fw_context *ctx = context;
2122
2123 ctx->blob = firmware;
0673effd 2124 complete(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2125}
2126
1a9f5093
MB		 2127int b43_do_request_fw(struct b43_request_fw_context *ctx,
2128 const char *name,
5e20a4b5 2129 struct b43_firmware_file *fw, bool async)
e4d6b795 2130{
e4d6b795
MB		 2131 struct b43_fw_header *hdr;
2132 u32 size;
2133 int err;
2134
61cb5dd6
MB		 2135 if (!name) {
2136 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2137 /* FIXME: We should probably keep it anyway, to save some headache
2138 * on suspend/resume with multiband devices. */
2139 b43_do_release_fw(fw);
e4d6b795 2140 return 0;
61cb5dd6
MB		 2141 }
2142 if (fw->filename) {
1a9f5093
MB		 2143 if ((fw->type == ctx->req_type) &&
2144 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2145 return 0; /* Already have this fw. */
2146 /* Free the cached firmware first. */
1a9f5093
MB		 2147 /* FIXME: We should probably do this later after we successfully
2148 * got the new fw. This could reduce headache with multiband devices.
2149 * We could also redesign this to cache the firmware for all possible
2150 * bands all the time. */
2151 b43_do_release_fw(fw);
61cb5dd6 2152 }
e4d6b795 2153
1a9f5093
MB		 2154 switch (ctx->req_type) {
2155 case B43_FWTYPE_PROPRIETARY:
2156 snprintf(ctx->fwname, sizeof(ctx->fwname),
2157 "b43%s/%s.fw",
2158 modparam_fwpostfix, name);
2159 break;
2160 case B43_FWTYPE_OPENSOURCE:
2161 snprintf(ctx->fwname, sizeof(ctx->fwname),
2162 "b43-open%s/%s.fw",
2163 modparam_fwpostfix, name);
2164 break;
2165 default:
2166 B43_WARN_ON(1);
2167 return -ENOSYS;
2168 }
5e20a4b5
LF		 2169 if (async) {
2170 /* do this part asynchronously */
0673effd 2171 init_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2172 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2173 ctx->dev->dev->dev, GFP_KERNEL,
2174 ctx, b43_fw_cb);
2175 if (err < 0) {
2176 pr_err("Unable to load firmware\n");
2177 return err;
2178 }
0673effd 2179 wait_for_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2180 if (ctx->blob)
2181 goto fw_ready;
2182 /* On some ARM systems, the async request will fail, but the next sync
0673effd 2183 * request works. For this reason, we fall through here
5e20a4b5
LF		 2184 */
2185 }
2186 err = request_firmware(&ctx->blob, ctx->fwname,
2187 ctx->dev->dev->dev);
68217832 2188 if (err == -ENOENT) {
1a9f5093
MB		 2189 snprintf(ctx->errors[ctx->req_type],
2190 sizeof(ctx->errors[ctx->req_type]),
5e20a4b5
LF		 2191 "Firmware file \"%s\" not found\n",
2192 ctx->fwname);
68217832
MB		 2193 return err;
2194 } else if (err) {
1a9f5093
MB		 2195 snprintf(ctx->errors[ctx->req_type],
2196 sizeof(ctx->errors[ctx->req_type]),
2197 "Firmware file \"%s\" request failed (err=%d)\n",
2198 ctx->fwname, err);
e4d6b795
MB		 2199 return err;
2200 }
5e20a4b5
LF		 2201fw_ready:
2202 if (ctx->blob->size < sizeof(struct b43_fw_header))
e4d6b795 2203 goto err_format;
5e20a4b5 2204 hdr = (struct b43_fw_header *)(ctx->blob->data);
e4d6b795
MB		 2205 switch (hdr->type) {
2206 case B43_FW_TYPE_UCODE:
2207 case B43_FW_TYPE_PCM:
2208 size = be32_to_cpu(hdr->size);
5e20a4b5 2209 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2210 goto err_format;
2211 /* fallthrough */
2212 case B43_FW_TYPE_IV:
2213 if (hdr->ver != 1)
2214 goto err_format;
2215 break;
2216 default:
2217 goto err_format;
2218 }
2219
5e20a4b5 2220 fw->data = ctx->blob;
61cb5dd6 2221 fw->filename = name;
1a9f5093 2222 fw->type = ctx->req_type;
61cb5dd6
MB		 2223
2224 return 0;
e4d6b795
MB		 2225
2226err_format:
1a9f5093
MB		 2227 snprintf(ctx->errors[ctx->req_type],
2228 sizeof(ctx->errors[ctx->req_type]),
2229 "Firmware file \"%s\" format error.\n", ctx->fwname);
5e20a4b5 2230 release_firmware(ctx->blob);
61cb5dd6 2231
e4d6b795
MB		 2232 return -EPROTO;
2233}
2234
a60f99f7 2235/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
1a9f5093 2236static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2237{
1a9f5093
MB		 2238 struct b43_wldev *dev = ctx->dev;
2239 struct b43_firmware *fw = &ctx->dev->fw;
a60f99f7 2240 struct b43_phy *phy = &dev->phy;
21d889d4 2241 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795 2242 const char *filename;
e4d6b795
MB		 2243 int err;
2244
61cb5dd6 2245 /* Get microcode */
a60f99f7
RM		 2246 filename = NULL;
2247 switch (rev) {
2248 case 42:
2249 if (phy->type == B43_PHYTYPE_AC)
2250 filename = "ucode42";
2251 break;
15be8e89
RM		 2252 case 40:
2253 if (phy->type == B43_PHYTYPE_AC)
2254 filename = "ucode40";
2255 break;
a60f99f7
RM		 2256 case 33:
2257 if (phy->type == B43_PHYTYPE_LCN40)
2258 filename = "ucode33_lcn40";
2259 break;
2260 case 30:
2261 if (phy->type == B43_PHYTYPE_N)
2262 filename = "ucode30_mimo";
2263 break;
2264 case 29:
2265 if (phy->type == B43_PHYTYPE_HT)
2266 filename = "ucode29_mimo";
2267 break;
2268 case 26:
2269 if (phy->type == B43_PHYTYPE_HT)
2270 filename = "ucode26_mimo";
2271 break;
2272 case 28:
2273 case 25:
2274 if (phy->type == B43_PHYTYPE_N)
2275 filename = "ucode25_mimo";
2276 else if (phy->type == B43_PHYTYPE_LCN)
2277 filename = "ucode25_lcn";
2278 break;
2279 case 24:
2280 if (phy->type == B43_PHYTYPE_LCN)
2281 filename = "ucode24_lcn";
2282 break;
2283 case 23:
2284 if (phy->type == B43_PHYTYPE_N)
2285 filename = "ucode16_mimo";
2286 break;
2287 case 16 ... 19:
2288 if (phy->type == B43_PHYTYPE_N)
2289 filename = "ucode16_mimo";
2290 else if (phy->type == B43_PHYTYPE_LP)
2291 filename = "ucode16_lp";
2292 break;
2293 case 15:
759b973b 2294 filename = "ucode15";
a60f99f7
RM		 2295 break;
2296 case 14:
2297 filename = "ucode14";
2298 break;
2299 case 13:
2300 filename = "ucode13";
2301 break;
2302 case 11 ... 12:
2303 filename = "ucode11";
2304 break;
2305 case 5 ... 10:
2306 filename = "ucode5";
2307 break;
6ff1e5cf 2308 }
a60f99f7
RM		 2309 if (!filename)
2310 goto err_no_ucode;
5e20a4b5 2311 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
61cb5dd6
MB		 2312 if (err)
2313 goto err_load;
2314
2315 /* Get PCM code */
2316 if ((rev >= 5) && (rev <= 10))
2317 filename = "pcm5";
2318 else if (rev >= 11)
2319 filename = NULL;
2320 else
2321 goto err_no_pcm;
3db1cd5c 2322 fw->pcm_request_failed = false;
5e20a4b5 2323 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
68217832
MB		 2324 if (err == -ENOENT) {
2325 /* We did not find a PCM file? Not fatal, but
2326 * core rev <= 10 must do without hwcrypto then. */
3db1cd5c 2327 fw->pcm_request_failed = true;
68217832 2328 } else if (err)
61cb5dd6
MB		 2329 goto err_load;
2330
2331 /* Get initvals */
a60f99f7 2332 filename = NULL;
61cb5dd6 2333 switch (dev->phy.type) {
61cb5dd6 2334 case B43_PHYTYPE_G:
a60f99f7 2335 if (rev == 13)
e9304882 2336 filename = "b0g0initvals13";
a60f99f7
RM		 2337 else if (rev >= 5 && rev <= 10)
2338 filename = "b0g0initvals5";
61cb5dd6
MB		 2339 break;
2340 case B43_PHYTYPE_N:
a60f99f7
RM		 2341 if (rev == 30)
2342 filename = "n16initvals30";
2343 else if (rev == 28 || rev == 25)
2344 filename = "n0initvals25";
2345 else if (rev == 24)
2346 filename = "n0initvals24";
2347 else if (rev == 23)
2348 filename = "n0initvals16"; /* What about n0initvals22? */
2349 else if (rev >= 16 && rev <= 18)
e41596a1 2350 filename = "n0initvals16";
a60f99f7 2351 else if (rev >= 11 && rev <= 12)
61cb5dd6 2352 filename = "n0initvals11";
61cb5dd6 2353 break;
759b973b 2354 case B43_PHYTYPE_LP:
a60f99f7
RM		 2355 if (rev >= 16 && rev <= 18)
2356 filename = "lp0initvals16";
2357 else if (rev == 15)
2358 filename = "lp0initvals15";
759b973b
GS		 2359 else if (rev == 14)
2360 filename = "lp0initvals14";
a60f99f7
RM		 2361 else if (rev == 13)
2362 filename = "lp0initvals13";
759b973b 2363 break;
8b9bda75
RM		 2364 case B43_PHYTYPE_HT:
2365 if (rev == 29)
2366 filename = "ht0initvals29";
a60f99f7
RM		 2367 else if (rev == 26)
2368 filename = "ht0initvals26";
8b9bda75
RM		 2369 break;
2370 case B43_PHYTYPE_LCN:
2371 if (rev == 24)
2372 filename = "lcn0initvals24";
8b9bda75 2373 break;
a60f99f7
RM		 2374 case B43_PHYTYPE_LCN40:
2375 if (rev == 33)
2376 filename = "lcn400initvals33";
2377 break;
2378 case B43_PHYTYPE_AC:
2379 if (rev == 42)
2380 filename = "ac1initvals42";
15be8e89
RM		 2381 else if (rev == 40)
2382 filename = "ac0initvals40";
a60f99f7 2383 break;
e4d6b795 2384 }
a60f99f7
RM		 2385 if (!filename)
2386 goto err_no_initvals;
5e20a4b5 2387 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
61cb5dd6
MB		 2388 if (err)
2389 goto err_load;
2390
2391 /* Get bandswitch initvals */
a60f99f7 2392 filename = NULL;
61cb5dd6 2393 switch (dev->phy.type) {
61cb5dd6 2394 case B43_PHYTYPE_G:
a60f99f7
RM		 2395 if (rev == 13)
2396 filename = "b0g0bsinitvals13";
2397 else if (rev >= 5 && rev <= 10)
61cb5dd6 2398 filename = "b0g0bsinitvals5";
61cb5dd6
MB		 2399 break;
2400 case B43_PHYTYPE_N:
a60f99f7
RM		 2401 if (rev == 30)
2402 filename = "n16bsinitvals30";
2403 else if (rev == 28 || rev == 25)
2404 filename = "n0bsinitvals25";
2405 else if (rev == 24)
2406 filename = "n0bsinitvals24";
2407 else if (rev == 23)
2408 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2409 else if (rev >= 16 && rev <= 18)
e41596a1 2410 filename = "n0bsinitvals16";
a60f99f7 2411 else if (rev >= 11 && rev <= 12)
61cb5dd6 2412 filename = "n0bsinitvals11";
61cb5dd6 2413 break;
759b973b 2414 case B43_PHYTYPE_LP:
a60f99f7
RM		 2415 if (rev >= 16 && rev <= 18)
2416 filename = "lp0bsinitvals16";
2417 else if (rev == 15)
2418 filename = "lp0bsinitvals15";
759b973b
GS		 2419 else if (rev == 14)
2420 filename = "lp0bsinitvals14";
a60f99f7
RM		 2421 else if (rev == 13)
2422 filename = "lp0bsinitvals13";
759b973b 2423 break;
8b9bda75
RM		 2424 case B43_PHYTYPE_HT:
2425 if (rev == 29)
2426 filename = "ht0bsinitvals29";
a60f99f7
RM		 2427 else if (rev == 26)
2428 filename = "ht0bsinitvals26";
8b9bda75
RM		 2429 break;
2430 case B43_PHYTYPE_LCN:
2431 if (rev == 24)
2432 filename = "lcn0bsinitvals24";
8b9bda75 2433 break;
a60f99f7
RM		 2434 case B43_PHYTYPE_LCN40:
2435 if (rev == 33)
2436 filename = "lcn400bsinitvals33";
2437 break;
2438 case B43_PHYTYPE_AC:
2439 if (rev == 42)
2440 filename = "ac1bsinitvals42";
15be8e89
RM		 2441 else if (rev == 40)
2442 filename = "ac0bsinitvals40";
a60f99f7 2443 break;
e4d6b795 2444 }
a60f99f7
RM		 2445 if (!filename)
2446 goto err_no_initvals;
5e20a4b5 2447 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
61cb5dd6
MB		 2448 if (err)
2449 goto err_load;
e4d6b795 2450
097b0e1b
JB		 2451 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2452
e4d6b795
MB		 2453 return 0;
2454
e4d6b795 2455err_no_ucode:
1a9f5093
MB		 2456 err = ctx->fatal_failure = -EOPNOTSUPP;
2457 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2458 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2459 goto error;
2460
2461err_no_pcm:
1a9f5093
MB		 2462 err = ctx->fatal_failure = -EOPNOTSUPP;
2463 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2464 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2465 goto error;
2466
2467err_no_initvals:
1a9f5093
MB		 2468 err = ctx->fatal_failure = -EOPNOTSUPP;
2469 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2470 "is required for your device (wl-core rev %u)\n", rev);
2471 goto error;
2472
2473err_load:
2474 /* We failed to load this firmware image. The error message
2475 * already is in ctx->errors. Return and let our caller decide
2476 * what to do. */
e4d6b795
MB		 2477 goto error;
2478
2479error:
2480 b43_release_firmware(dev);
2481 return err;
2482}
2483
6b6fa586
LF		 2484static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2485static void b43_one_core_detach(struct b43_bus_dev *dev);
09164043 2486static int b43_rng_init(struct b43_wl *wl);
6b6fa586
LF		 2487
2488static void b43_request_firmware(struct work_struct *work)
1a9f5093 2489{
6b6fa586
LF		 2490 struct b43_wl *wl = container_of(work,
2491 struct b43_wl, firmware_load);
2492 struct b43_wldev *dev = wl->current_dev;
1a9f5093
MB		 2493 struct b43_request_fw_context *ctx;
2494 unsigned int i;
2495 int err;
2496 const char *errmsg;
2497
2498 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2499 if (!ctx)
6b6fa586 2500 return;
1a9f5093
MB		 2501 ctx->dev = dev;
2502
2503 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2504 err = b43_try_request_fw(ctx);
2505 if (!err)
6b6fa586
LF		 2506 goto start_ieee80211; /* Successfully loaded it. */
2507 /* Was fw version known? */
2508 if (ctx->fatal_failure)
1a9f5093
MB		 2509 goto out;
2510
6b6fa586 2511 /* proprietary fw not found, try open source */
1a9f5093
MB		 2512 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2513 err = b43_try_request_fw(ctx);
2514 if (!err)
6b6fa586
LF		 2515 goto start_ieee80211; /* Successfully loaded it. */
2516 if(ctx->fatal_failure)
1a9f5093
MB		 2517 goto out;
2518
2519 /* Could not find a usable firmware. Print the errors. */
2520 for (i = 0; i < B43_NR_FWTYPES; i++) {
2521 errmsg = ctx->errors[i];
2522 if (strlen(errmsg))
e0e29b68 2523 b43err(dev->wl, "%s", errmsg);
1a9f5093
MB		 2524 }
2525 b43_print_fw_helptext(dev->wl, 1);
6b6fa586
LF		 2526 goto out;
2527
2528start_ieee80211:
097b0e1b
JB		 2529 wl->hw->queues = B43_QOS_QUEUE_NUM;
2530 if (!modparam_qos || dev->fw.opensource)
2531 wl->hw->queues = 1;
2532
6b6fa586
LF		 2533 err = ieee80211_register_hw(wl->hw);
2534 if (err)
2535 goto err_one_core_detach;
e64add27 2536 wl->hw_registred = true;
6b6fa586 2537 b43_leds_register(wl->current_dev);
09164043
LF		 2538
2539 /* Register HW RNG driver */
2540 b43_rng_init(wl);
2541
6b6fa586
LF		 2542 goto out;
2543
2544err_one_core_detach:
2545 b43_one_core_detach(dev->dev);
1a9f5093
MB		 2546
2547out:
2548 kfree(ctx);
1a9f5093
MB		 2549}
2550
e4d6b795
MB		 2551static int b43_upload_microcode(struct b43_wldev *dev)
2552{
652caa5b 2553 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2554 const size_t hdr_len = sizeof(struct b43_fw_header);
2555 const __be32 *data;
2556 unsigned int i, len;
2557 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2558 u32 tmp, macctl;
e4d6b795
MB		 2559 int err = 0;
2560
1f7d87b0
MB		 2561 /* Jump the microcode PSM to offset 0 */
2562 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2563 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2564 macctl |= B43_MACCTL_PSM_JMP0;
2565 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2566 /* Zero out all microcode PSM registers and shared memory. */
2567 for (i = 0; i < 64; i++)
2568 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2569 for (i = 0; i < 4096; i += 2)
2570 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2571
e4d6b795 2572 /* Upload Microcode. */
61cb5dd6
MB		 2573 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2574 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2575 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2576 for (i = 0; i < len; i++) {
2577 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2578 udelay(10);
2579 }
2580
61cb5dd6 2581 if (dev->fw.pcm.data) {
e4d6b795 2582 /* Upload PCM data. */
61cb5dd6
MB		 2583 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2584 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2585 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2586 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2587 /* No need for autoinc bit in SHM_HW */
2588 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2589 for (i = 0; i < len; i++) {
2590 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2591 udelay(10);
2592 }
2593 }
2594
2595 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2596
2597 /* Start the microcode PSM */
5056635c
RM		 2598 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2599 B43_MACCTL_PSM_RUN);
e4d6b795
MB		 2600
2601 /* Wait for the microcode to load and respond */
2602 i = 0;
2603 while (1) {
2604 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2605 if (tmp == B43_IRQ_MAC_SUSPENDED)
2606 break;
2607 i++;
1f7d87b0 2608 if (i >= 20) {
e4d6b795 2609 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2610 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2611 err = -ENODEV;
1f7d87b0
MB		 2612 goto error;
2613 }
e175e996 2614 msleep(50);
e4d6b795
MB		 2615 }
2616 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2617
2618 /* Get and check the revisions. */
2619 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2620 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2621 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2622 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2623
2624 if (fwrev <= 0x128) {
2625 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2626 "binary drivers older than version 4.x is unsupported. "
2627 "You must upgrade your firmware files.\n");
eb189d8b 2628 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2629 err = -EOPNOTSUPP;
1f7d87b0 2630 goto error;
e4d6b795 2631 }
e4d6b795
MB		 2632 dev->fw.rev = fwrev;
2633 dev->fw.patch = fwpatch;
5d852905
RM		 2634 if (dev->fw.rev >= 598)
2635 dev->fw.hdr_format = B43_FW_HDR_598;
2636 else if (dev->fw.rev >= 410)
efe0249b
RM		 2637 dev->fw.hdr_format = B43_FW_HDR_410;
2638 else
2639 dev->fw.hdr_format = B43_FW_HDR_351;
097b0e1b 2640 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
e48b0eeb 2641
097b0e1b 2642 dev->qos_enabled = dev->wl->hw->queues > 1;
403a3a13 2643 /* Default to firmware/hardware crypto acceleration. */
3db1cd5c 2644 dev->hwcrypto_enabled = true;
403a3a13 2645
e48b0eeb 2646 if (dev->fw.opensource) {
403a3a13
MB		 2647 u16 fwcapa;
2648
e48b0eeb
MB		 2649 /* Patchlevel info is encoded in the "time" field. */
2650 dev->fw.patch = fwtime;
403a3a13
MB		 2651 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2652 dev->fw.rev, dev->fw.patch);
2653
2654 fwcapa = b43_fwcapa_read(dev);
2655 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2656 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2657 /* Disable hardware crypto and fall back to software crypto. */
3db1cd5c 2658 dev->hwcrypto_enabled = false;
403a3a13 2659 }
097b0e1b
JB		 2660 /* adding QoS support should use an offline discovery mechanism */
2661 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
e48b0eeb
MB		 2662 } else {
2663 b43info(dev->wl, "Loading firmware version %u.%u "
2664 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2665 fwrev, fwpatch,
2666 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2667 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2668 if (dev->fw.pcm_request_failed) {
2669 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2670 "Hardware accelerated cryptography is disabled.\n");
2671 b43_print_fw_helptext(dev->wl, 0);
2672 }
e48b0eeb 2673 }
e4d6b795 2674
652caa5b
JL		 2675 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2676 dev->fw.rev, dev->fw.patch);
21d889d4 2677 wiphy->hw_version = dev->dev->core_id;
652caa5b 2678
efe0249b 2679 if (dev->fw.hdr_format == B43_FW_HDR_351) {
c557289c
MB		 2680 /* We're over the deadline, but we keep support for old fw
2681 * until it turns out to be in major conflict with something new. */
eb189d8b 2682 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2683 "Support for old firmware will be removed soon "
2684 "(official deadline was July 2008).\n");
eb189d8b
MB		 2685 b43_print_fw_helptext(dev->wl, 0);
2686 }
2687
1f7d87b0
MB		 2688 return 0;
2689
2690error:
5056635c
RM		 2691 /* Stop the microcode PSM. */
2692 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2693 B43_MACCTL_PSM_JMP0);
1f7d87b0 2694
e4d6b795
MB		 2695 return err;
2696}
2697
2698static int b43_write_initvals(struct b43_wldev *dev,
2699 const struct b43_iv *ivals,
2700 size_t count,
2701 size_t array_size)
2702{
2703 const struct b43_iv *iv;
2704 u16 offset;
2705 size_t i;
2706 bool bit32;
2707
2708 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2709 iv = ivals;
2710 for (i = 0; i < count; i++) {
2711 if (array_size < sizeof(iv->offset_size))
2712 goto err_format;
2713 array_size -= sizeof(iv->offset_size);
2714 offset = be16_to_cpu(iv->offset_size);
2715 bit32 = !!(offset & B43_IV_32BIT);
2716 offset &= B43_IV_OFFSET_MASK;
2717 if (offset >= 0x1000)
2718 goto err_format;
2719 if (bit32) {
2720 u32 value;
2721
2722 if (array_size < sizeof(iv->data.d32))
2723 goto err_format;
2724 array_size -= sizeof(iv->data.d32);
2725
533dd1b0 2726 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2727 b43_write32(dev, offset, value);
2728
2729 iv = (const struct b43_iv *)((const uint8_t *)iv +
2730 sizeof(__be16) +
2731 sizeof(__be32));
2732 } else {
2733 u16 value;
2734
2735 if (array_size < sizeof(iv->data.d16))
2736 goto err_format;
2737 array_size -= sizeof(iv->data.d16);
2738
2739 value = be16_to_cpu(iv->data.d16);
2740 b43_write16(dev, offset, value);
2741
2742 iv = (const struct b43_iv *)((const uint8_t *)iv +
2743 sizeof(__be16) +
2744 sizeof(__be16));
2745 }
2746 }
2747 if (array_size)
2748 goto err_format;
2749
2750 return 0;
2751
2752err_format:
2753 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2754 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2755
2756 return -EPROTO;
2757}
2758
2759static int b43_upload_initvals(struct b43_wldev *dev)
2760{
2761 const size_t hdr_len = sizeof(struct b43_fw_header);
2762 const struct b43_fw_header *hdr;
2763 struct b43_firmware *fw = &dev->fw;
2764 const struct b43_iv *ivals;
2765 size_t count;
e4d6b795 2766
61cb5dd6
MB		 2767 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2768 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795 2769 count = be32_to_cpu(hdr->size);
0f68423f 2770 return b43_write_initvals(dev, ivals, count,
61cb5dd6 2771 fw->initvals.data->size - hdr_len);
0f68423f 2772}
e4d6b795 2773
0f68423f
RM		 2774static int b43_upload_initvals_band(struct b43_wldev *dev)
2775{
2776 const size_t hdr_len = sizeof(struct b43_fw_header);
2777 const struct b43_fw_header *hdr;
2778 struct b43_firmware *fw = &dev->fw;
2779 const struct b43_iv *ivals;
2780 size_t count;
2781
2782 if (!fw->initvals_band.data)
2783 return 0;
2784
2785 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2786 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2787 count = be32_to_cpu(hdr->size);
2788 return b43_write_initvals(dev, ivals, count,
2789 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2790}
2791
2792/* Initialize the GPIOs
2793 * http://bcm-specs.sipsolutions.net/GPIO
2794 */
bd7c8a59
RM		 2795
2796#ifdef CONFIG_B43_SSB
c4a2a081 2797static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2798{
d48ae5c8 2799 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2800
2801#ifdef CONFIG_SSB_DRIVER_PCICORE
2802 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2803#else
2804 return bus->chipco.dev;
2805#endif
2806}
bd7c8a59 2807#endif
c4a2a081 2808
e4d6b795
MB		 2809static int b43_gpio_init(struct b43_wldev *dev)
2810{
bd7c8a59 2811#ifdef CONFIG_B43_SSB
c4a2a081 2812 struct ssb_device *gpiodev;
bd7c8a59 2813#endif
e4d6b795
MB		 2814 u32 mask, set;
2815
5056635c
RM		 2816 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2817 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
e4d6b795
MB		 2818
2819 mask = 0x0000001F;
2820 set = 0x0000000F;
c244e08c 2821 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2822 mask |= 0x0060;
2823 set |= 0x0060;
828afd26
RM		 2824 } else if (dev->dev->chip_id == 0x5354) {
2825 /* Don't allow overtaking buttons GPIOs */
2826 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
e4d6b795 2827 }
828afd26 2828
e4d6b795
MB		 2829 if (0 /* FIXME: conditional unknown */ ) {
2830 b43_write16(dev, B43_MMIO_GPIO_MASK,
2831 b43_read16(dev, B43_MMIO_GPIO_MASK)
2832 | 0x0100);
828afd26
RM		 2833 /* BT Coexistance Input */
2834 mask |= 0x0080;
2835 set |= 0x0080;
2836 /* BT Coexistance Out */
2837 mask |= 0x0100;
2838 set |= 0x0100;
e4d6b795 2839 }
0581483a 2840 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
828afd26 2841 /* PA is controlled by gpio 9, let ucode handle it */
e4d6b795
MB		 2842 b43_write16(dev, B43_MMIO_GPIO_MASK,
2843 b43_read16(dev, B43_MMIO_GPIO_MASK)
2844 | 0x0200);
2845 mask |= 0x0200;
2846 set |= 0x0200;
2847 }
e4d6b795 2848
6cbab0d9 2849 switch (dev->dev->bus_type) {
42c9a458
RM		 2850#ifdef CONFIG_B43_BCMA
2851 case B43_BUS_BCMA:
0a64baea 2852 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
42c9a458
RM		 2853 break;
2854#endif
6cbab0d9
RM		 2855#ifdef CONFIG_B43_SSB
2856 case B43_BUS_SSB:
2857 gpiodev = b43_ssb_gpio_dev(dev);
2858 if (gpiodev)
2859 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2860 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
828afd26 2861 & ~mask) | set);
6cbab0d9
RM		 2862 break;
2863#endif
2864 }
e4d6b795
MB		 2865
2866 return 0;
2867}
2868
2869/* Turn off all GPIO stuff. Call this on module unload, for example. */
2870static void b43_gpio_cleanup(struct b43_wldev *dev)
2871{
bd7c8a59 2872#ifdef CONFIG_B43_SSB
c4a2a081 2873 struct ssb_device *gpiodev;
bd7c8a59 2874#endif
e4d6b795 2875
6cbab0d9 2876 switch (dev->dev->bus_type) {
42c9a458
RM		 2877#ifdef CONFIG_B43_BCMA
2878 case B43_BUS_BCMA:
0a64baea 2879 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
42c9a458
RM		 2880 break;
2881#endif
6cbab0d9
RM		 2882#ifdef CONFIG_B43_SSB
2883 case B43_BUS_SSB:
2884 gpiodev = b43_ssb_gpio_dev(dev);
2885 if (gpiodev)
2886 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2887 break;
2888#endif
2889 }
e4d6b795
MB		 2890}
2891
2892/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2893void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2894{
923fd703
MB		 2895 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2896 u16 fwstate;
2897
2898 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2899 B43_SHM_SH_UCODESTAT);
2900 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2901 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2902 b43err(dev->wl, "b43_mac_enable(): The firmware "
2903 "should be suspended, but current state is %u\n",
2904 fwstate);
2905 }
2906 }
2907
e4d6b795
MB		 2908 dev->mac_suspended--;
2909 B43_WARN_ON(dev->mac_suspended < 0);
2910 if (dev->mac_suspended == 0) {
5056635c 2911 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
e4d6b795
MB		 2912 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2913 B43_IRQ_MAC_SUSPENDED);
2914 /* Commit writes */
2915 b43_read32(dev, B43_MMIO_MACCTL);
2916 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2917 b43_power_saving_ctl_bits(dev, 0);
2918 }
2919}
2920
2921/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2922void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2923{
2924 int i;
2925 u32 tmp;
2926
05b64b36 2927 might_sleep();
e4d6b795 2928 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2929
e4d6b795
MB		 2930 if (dev->mac_suspended == 0) {
2931 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
5056635c 2932 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
e4d6b795
MB		 2933 /* force pci to flush the write */
2934 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2935 for (i = 35; i; i--) {
2936 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2937 if (tmp & B43_IRQ_MAC_SUSPENDED)
2938 goto out;
2939 udelay(10);
2940 }
2941 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2942 for (i = 40; i; i--) {
e4d6b795
MB		 2943 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2944 if (tmp & B43_IRQ_MAC_SUSPENDED)
2945 goto out;
05b64b36 2946 msleep(1);
e4d6b795
MB		 2947 }
2948 b43err(dev->wl, "MAC suspend failed\n");
2949 }
05b64b36 2950out:
e4d6b795
MB		 2951 dev->mac_suspended++;
2952}
2953
858a1652
RM		 2954/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2955void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2956{
6cbab0d9
RM		 2957 u32 tmp;
2958
2959 switch (dev->dev->bus_type) {
42c9a458
RM		 2960#ifdef CONFIG_B43_BCMA
2961 case B43_BUS_BCMA:
36677874 2962 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2963 if (on)
2964 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2965 else
2966 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2967 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2968 break;
2969#endif
6cbab0d9
RM		 2970#ifdef CONFIG_B43_SSB
2971 case B43_BUS_SSB:
2972 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2973 if (on)
2974 tmp |= B43_TMSLOW_MACPHYCLKEN;
2975 else
2976 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2977 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2978 break;
2979#endif
2980 }
858a1652
RM		 2981}
2982
c2cb2c4c
RM		 2983/* brcms_b_switch_macfreq */
2984void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode)
2985{
2986 u16 chip_id = dev->dev->chip_id;
2987
a67d19d4
RM		 2988 if (chip_id == BCMA_CHIP_ID_BCM43131 ||
2989 chip_id == BCMA_CHIP_ID_BCM43217 ||
c2cb2c4c
RM		 2990 chip_id == BCMA_CHIP_ID_BCM43222 ||
2991 chip_id == BCMA_CHIP_ID_BCM43224 ||
2992 chip_id == BCMA_CHIP_ID_BCM43225 ||
2993 chip_id == BCMA_CHIP_ID_BCM43227 ||
2994 chip_id == BCMA_CHIP_ID_BCM43228) {
2995 switch (spurmode) {
2996 case 2: /* 126 Mhz */
2997 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
2998 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
2999 break;
3000 case 1: /* 123 Mhz */
3001 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
3002 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3003 break;
3004 default: /* 120 Mhz */
3005 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
3006 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3007 break;
3008 }
3009 } else if (dev->phy.type == B43_PHYTYPE_LCN) {
3010 switch (spurmode) {
3011 case 1: /* 82 Mhz */
3012 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
3013 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3014 break;
3015 default: /* 80 Mhz */
3016 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
3017 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3018 break;
3019 }
3020 }
3021}
3022
e4d6b795
MB		 3023static void b43_adjust_opmode(struct b43_wldev *dev)
3024{
3025 struct b43_wl *wl = dev->wl;
3026 u32 ctl;
3027 u16 cfp_pretbtt;
3028
3029 ctl = b43_read32(dev, B43_MMIO_MACCTL);
3030 /* Reset status to STA infrastructure mode. */
3031 ctl &= ~B43_MACCTL_AP;
3032 ctl &= ~B43_MACCTL_KEEP_CTL;
3033 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
3034 ctl &= ~B43_MACCTL_KEEP_BAD;
3035 ctl &= ~B43_MACCTL_PROMISC;
4150c572 3036 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 3037 ctl |= B43_MACCTL_INFRA;
3038
05c914fe
JB		 3039 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3040 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 3041 ctl |= B43_MACCTL_AP;
05c914fe 3042 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 3043 ctl &= ~B43_MACCTL_INFRA;
3044
3045 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 3046 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 3047 if (wl->filter_flags & FIF_FCSFAIL)
3048 ctl |= B43_MACCTL_KEEP_BAD;
3049 if (wl->filter_flags & FIF_PLCPFAIL)
3050 ctl |= B43_MACCTL_KEEP_BADPLCP;
3051 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 3052 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 3053 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
3054 ctl |= B43_MACCTL_BEACPROMISC;
3055
e4d6b795
MB		 3056 /* Workaround: On old hardware the HW-MAC-address-filter
3057 * doesn't work properly, so always run promisc in filter
3058 * it in software. */
21d889d4 3059 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 3060 ctl |= B43_MACCTL_PROMISC;
3061
3062 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3063
3064 cfp_pretbtt = 2;
3065 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 3066 if (dev->dev->chip_id == 0x4306 &&
3067 dev->dev->chip_rev == 3)
e4d6b795
MB		 3068 cfp_pretbtt = 100;
3069 else
3070 cfp_pretbtt = 50;
3071 }
3072 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 3073
3074 /* FIXME: We don't currently implement the PMQ mechanism,
3075 * so always disable it. If we want to implement PMQ,
3076 * we need to enable it here (clear DISCPMQ) in AP mode.
3077 */
5056635c
RM		 3078 if (0 /* ctl & B43_MACCTL_AP */)
3079 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3080 else
3081 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
e4d6b795
MB		 3082}
3083
3084static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3085{
3086 u16 offset;
3087
3088 if (is_ofdm) {
3089 offset = 0x480;
3090 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3091 } else {
3092 offset = 0x4C0;
3093 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3094 }
3095 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3096 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3097}
3098
3099static void b43_rate_memory_init(struct b43_wldev *dev)
3100{
3101 switch (dev->phy.type) {
3102 case B43_PHYTYPE_A:
3103 case B43_PHYTYPE_G:
53a6e234 3104 case B43_PHYTYPE_N:
9d86a2d5 3105 case B43_PHYTYPE_LP:
6a461c23 3106 case B43_PHYTYPE_HT:
0b4ff45d 3107 case B43_PHYTYPE_LCN:
e4d6b795
MB		 3108 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3109 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3110 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3111 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3112 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3113 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3114 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3115 if (dev->phy.type == B43_PHYTYPE_A)
3116 break;
3117 /* fallthrough */
3118 case B43_PHYTYPE_B:
3119 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3120 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3121 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3122 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3123 break;
3124 default:
3125 B43_WARN_ON(1);
3126 }
3127}
3128
5042c507
MB		 3129/* Set the default values for the PHY TX Control Words. */
3130static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3131{
3132 u16 ctl = 0;
3133
3134 ctl |= B43_TXH_PHY_ENC_CCK;
3135 ctl |= B43_TXH_PHY_ANT01AUTO;
3136 ctl |= B43_TXH_PHY_TXPWR;
3137
3138 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3139 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3140 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3141}
3142
e4d6b795
MB		 3143/* Set the TX-Antenna for management frames sent by firmware. */
3144static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3145{
5042c507 3146 u16 ant;
e4d6b795
MB		 3147 u16 tmp;
3148
5042c507 3149 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 3150
e4d6b795
MB		 3151 /* For ACK/CTS */
3152 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 3153 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3154 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3155 /* For Probe Resposes */
3156 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 3157 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3158 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3159}
3160
3161/* This is the opposite of b43_chip_init() */
3162static void b43_chip_exit(struct b43_wldev *dev)
3163{
fb11137a 3164 b43_phy_exit(dev);
e4d6b795
MB		 3165 b43_gpio_cleanup(dev);
3166 /* firmware is released later */
3167}
3168
3169/* Initialize the chip
3170 * http://bcm-specs.sipsolutions.net/ChipInit
3171 */
3172static int b43_chip_init(struct b43_wldev *dev)
3173{
3174 struct b43_phy *phy = &dev->phy;
ef1a628d 3175 int err;
858a1652 3176 u32 macctl;
e4d6b795
MB		 3177 u16 value16;
3178
1f7d87b0
MB		 3179 /* Initialize the MAC control */
3180 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3181 if (dev->phy.gmode)
3182 macctl |= B43_MACCTL_GMODE;
3183 macctl |= B43_MACCTL_INFRA;
3184 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795 3185
e4d6b795
MB		 3186 err = b43_upload_microcode(dev);
3187 if (err)
3188 goto out; /* firmware is released later */
3189
3190 err = b43_gpio_init(dev);
3191 if (err)
3192 goto out; /* firmware is released later */
21954c36 3193
e4d6b795
MB		 3194 err = b43_upload_initvals(dev);
3195 if (err)
1a8d1227 3196 goto err_gpio_clean;
e4d6b795 3197
0f68423f
RM		 3198 err = b43_upload_initvals_band(dev);
3199 if (err)
3200 goto err_gpio_clean;
3201
0b7dcd96
MB		 3202 /* Turn the Analog on and initialize the PHY. */
3203 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3204 err = b43_phy_init(dev);
3205 if (err)
ef1a628d 3206 goto err_gpio_clean;
e4d6b795 3207
ef1a628d
MB		 3208 /* Disable Interference Mitigation. */
3209 if (phy->ops->interf_mitigation)
3210 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3211
ef1a628d
MB		 3212 /* Select the antennae */
3213 if (phy->ops->set_rx_antenna)
3214 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3215 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3216
3217 if (phy->type == B43_PHYTYPE_B) {
3218 value16 = b43_read16(dev, 0x005E);
3219 value16 |= 0x0004;
3220 b43_write16(dev, 0x005E, value16);
3221 }
3222 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3223 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3224 b43_write32(dev, 0x010C, 0x01000000);
3225
5056635c
RM		 3226 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3227 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
e4d6b795 3228
e4d6b795
MB		 3229 /* Probe Response Timeout value */
3230 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
5c1da23b 3231 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
e4d6b795
MB		 3232
3233 /* Initially set the wireless operation mode. */
3234 b43_adjust_opmode(dev);
3235
21d889d4 3236 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3237 b43_write16(dev, 0x060E, 0x0000);
3238 b43_write16(dev, 0x0610, 0x8000);
3239 b43_write16(dev, 0x0604, 0x0000);
3240 b43_write16(dev, 0x0606, 0x0200);
3241 } else {
3242 b43_write32(dev, 0x0188, 0x80000000);
3243 b43_write32(dev, 0x018C, 0x02000000);
3244 }
3245 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
73b82bf0 3246 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
e4d6b795
MB		 3247 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3248 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3249 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3250 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3251 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3252
858a1652 3253 b43_mac_phy_clock_set(dev, true);
e4d6b795 3254
6cbab0d9 3255 switch (dev->dev->bus_type) {
42c9a458
RM		 3256#ifdef CONFIG_B43_BCMA
3257 case B43_BUS_BCMA:
3258 /* FIXME: 0xE74 is quite common, but should be read from CC */
3259 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3260 break;
3261#endif
6cbab0d9
RM		 3262#ifdef CONFIG_B43_SSB
3263 case B43_BUS_SSB:
3264 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3265 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3266 break;
3267#endif
3268 }
e4d6b795
MB		 3269
3270 err = 0;
3271 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3272out:
e4d6b795
MB		 3273 return err;
3274
1a8d1227 3275err_gpio_clean:
e4d6b795 3276 b43_gpio_cleanup(dev);
21954c36 3277 return err;
e4d6b795
MB		 3278}
3279
e4d6b795
MB		 3280static void b43_periodic_every60sec(struct b43_wldev *dev)
3281{
ef1a628d 3282 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3283
ef1a628d
MB		 3284 if (ops->pwork_60sec)
3285 ops->pwork_60sec(dev);
18c8adeb
MB		 3286
3287 /* Force check the TX power emission now. */
3288 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3289}
3290
3291static void b43_periodic_every30sec(struct b43_wldev *dev)
3292{
3293 /* Update device statistics. */
3294 b43_calculate_link_quality(dev);
3295}
3296
3297static void b43_periodic_every15sec(struct b43_wldev *dev)
3298{
3299 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3300 u16 wdr;
3301
3302 if (dev->fw.opensource) {
3303 /* Check if the firmware is still alive.
3304 * It will reset the watchdog counter to 0 in its idle loop. */
3305 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3306 if (unlikely(wdr)) {
3307 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3308 b43_controller_restart(dev, "Firmware watchdog");
3309 return;
3310 } else {
3311 b43_shm_write16(dev, B43_SHM_SCRATCH,
3312 B43_WATCHDOG_REG, 1);
3313 }
3314 }
e4d6b795 3315
ef1a628d
MB		 3316 if (phy->ops->pwork_15sec)
3317 phy->ops->pwork_15sec(dev);
3318
00e0b8cb
SB		 3319 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3320 wmb();
990b86f4
MB		 3321
3322#if B43_DEBUG
3323 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3324 unsigned int i;
3325
3326 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3327 dev->irq_count / 15,
3328 dev->tx_count / 15,
3329 dev->rx_count / 15);
3330 dev->irq_count = 0;
3331 dev->tx_count = 0;
3332 dev->rx_count = 0;
3333 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3334 if (dev->irq_bit_count[i]) {
3335 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3336 dev->irq_bit_count[i] / 15, i, (1 << i));
3337 dev->irq_bit_count[i] = 0;
3338 }
3339 }
3340 }
3341#endif
e4d6b795
MB		 3342}
3343
e4d6b795
MB		 3344static void do_periodic_work(struct b43_wldev *dev)
3345{
3346 unsigned int state;
3347
3348 state = dev->periodic_state;
42bb4cd5 3349 if (state % 4 == 0)
e4d6b795 3350 b43_periodic_every60sec(dev);
42bb4cd5 3351 if (state % 2 == 0)
e4d6b795 3352 b43_periodic_every30sec(dev);
42bb4cd5 3353 b43_periodic_every15sec(dev);
e4d6b795
MB		 3354}
3355
05b64b36
MB		 3356/* Periodic work locking policy:
3357 * The whole periodic work handler is protected by
3358 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3359 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3360 */
e4d6b795
MB		 3361static void b43_periodic_work_handler(struct work_struct *work)
3362{
05b64b36
MB		 3363 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3364 periodic_work.work);
3365 struct b43_wl *wl = dev->wl;
3366 unsigned long delay;
e4d6b795 3367
05b64b36 3368 mutex_lock(&wl->mutex);
e4d6b795
MB		 3369
3370 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3371 goto out;
3372 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3373 goto out_requeue;
3374
05b64b36 3375 do_periodic_work(dev);
e4d6b795 3376
e4d6b795 3377 dev->periodic_state++;
42bb4cd5 3378out_requeue:
e4d6b795
MB		 3379 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3380 delay = msecs_to_jiffies(50);
3381 else
82cd682d 3382 delay = round_jiffies_relative(HZ * 15);
42935eca 3383 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3384out:
05b64b36 3385 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3386}
3387
3388static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3389{
3390 struct delayed_work *work = &dev->periodic_work;
3391
3392 dev->periodic_state = 0;
3393 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3394 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3395}
3396
f3dd3fcc 3397/* Check if communication with the device works correctly. */
e4d6b795
MB		 3398static int b43_validate_chipaccess(struct b43_wldev *dev)
3399{
f62ae6cd 3400 u32 v, backup0, backup4;
e4d6b795 3401
f62ae6cd
MB		 3402 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3403 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3404
3405 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3406 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3407 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3408 goto error;
f3dd3fcc
MB		 3409 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3410 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3411 goto error;
3412
f62ae6cd
MB		 3413 /* Check if unaligned 32bit SHM_SHARED access works properly.
3414 * However, don't bail out on failure, because it's noncritical. */
3415 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3416 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3417 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3418 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3419 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3420 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3421 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3422 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3423 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3424 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3425 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3426 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3427
3428 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3429 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3430
21d889d4 3431 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3432 /* The 32bit register shadows the two 16bit registers
3433 * with update sideeffects. Validate this. */
3434 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3435 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3436 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3437 goto error;
3438 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3439 goto error;
3440 }
3441 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3442
3443 v = b43_read32(dev, B43_MMIO_MACCTL);
3444 v |= B43_MACCTL_GMODE;
3445 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3446 goto error;
3447
3448 return 0;
f3dd3fcc 3449error:
e4d6b795
MB		 3450 b43err(dev->wl, "Failed to validate the chipaccess\n");
3451 return -ENODEV;
3452}
3453
3454static void b43_security_init(struct b43_wldev *dev)
3455{
e4d6b795
MB		 3456 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3457 /* KTP is a word address, but we address SHM bytewise.
3458 * So multiply by two.
3459 */
3460 dev->ktp *= 2;
66d2d089
MB		 3461 /* Number of RCMTA address slots */
3462 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3463 /* Clear the key memory. */
e4d6b795
MB		 3464 b43_clear_keys(dev);
3465}
3466
616de35d 3467#ifdef CONFIG_B43_HWRNG
99da185a 3468static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3469{
3470 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3471 struct b43_wldev *dev;
3472 int count = -ENODEV;
e4d6b795 3473
a78b3bb2
MB		 3474 mutex_lock(&wl->mutex);
3475 dev = wl->current_dev;
3476 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3477 *data = b43_read16(dev, B43_MMIO_RNG);
3478 count = sizeof(u16);
3479 }
3480 mutex_unlock(&wl->mutex);
e4d6b795 3481
a78b3bb2 3482 return count;
e4d6b795 3483}
616de35d 3484#endif /* CONFIG_B43_HWRNG */
e4d6b795 3485
b844eba2 3486static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3487{
616de35d 3488#ifdef CONFIG_B43_HWRNG
e4d6b795 3489 if (wl->rng_initialized)
b844eba2 3490 hwrng_unregister(&wl->rng);
616de35d 3491#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3492}
3493
3494static int b43_rng_init(struct b43_wl *wl)
3495{
616de35d 3496 int err = 0;
e4d6b795 3497
616de35d 3498#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3499 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3500 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3501 wl->rng.name = wl->rng_name;
3502 wl->rng.data_read = b43_rng_read;
3503 wl->rng.priv = (unsigned long)wl;
3db1cd5c 3504 wl->rng_initialized = true;
e4d6b795
MB		 3505 err = hwrng_register(&wl->rng);
3506 if (err) {
3db1cd5c 3507 wl->rng_initialized = false;
e4d6b795
MB		 3508 b43err(wl, "Failed to register the random "
3509 "number generator (%d)\n", err);
3510 }
616de35d 3511#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3512
3513 return err;
3514}
3515
f5d40eed 3516static void b43_tx_work(struct work_struct *work)
e4d6b795 3517{
f5d40eed
MB		 3518 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3519 struct b43_wldev *dev;
3520 struct sk_buff *skb;
bad69194 3521 int queue_num;
f5d40eed 3522 int err = 0;
e4d6b795 3523
f5d40eed
MB		 3524 mutex_lock(&wl->mutex);
3525 dev = wl->current_dev;
3526 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3527 mutex_unlock(&wl->mutex);
3528 return;
5100d5ac 3529 }
21a75d77 3530
bad69194 3531 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3532 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3533 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3534 if (b43_using_pio_transfers(dev))
3535 err = b43_pio_tx(dev, skb);
3536 else
3537 err = b43_dma_tx(dev, skb);
3538 if (err == -ENOSPC) {
3539 wl->tx_queue_stopped[queue_num] = 1;
3540 ieee80211_stop_queue(wl->hw, queue_num);
3541 skb_queue_head(&wl->tx_queue[queue_num], skb);
3542 break;
3543 }
3544 if (unlikely(err))
78f18df4 3545 ieee80211_free_txskb(wl->hw, skb);
bad69194 3546 err = 0;
3547 }
21a75d77 3548
bad69194 3549 if (!err)
3550 wl->tx_queue_stopped[queue_num] = 0;
21a75d77
MB		 3551 }
3552
990b86f4
MB		 3553#if B43_DEBUG
3554 dev->tx_count++;
3555#endif
f5d40eed
MB		 3556 mutex_unlock(&wl->mutex);
3557}
21a75d77 3558
7bb45683 3559static void b43_op_tx(struct ieee80211_hw *hw,
36323f81
TH		 3560 struct ieee80211_tx_control *control,
3561 struct sk_buff *skb)
f5d40eed
MB		 3562{
3563 struct b43_wl *wl = hw_to_b43_wl(hw);
3564
3565 if (unlikely(skb->len < 2 + 2 + 6)) {
3566 /* Too short, this can't be a valid frame. */
78f18df4 3567 ieee80211_free_txskb(hw, skb);
7bb45683 3568 return;
f5d40eed
MB		 3569 }
3570 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3571
bad69194 3572 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3573 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3574 ieee80211_queue_work(wl->hw, &wl->tx_work);
3575 } else {
3576 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3577 }
e4d6b795
MB		 3578}
3579
e6f5b934
MB		 3580static void b43_qos_params_upload(struct b43_wldev *dev,
3581 const struct ieee80211_tx_queue_params *p,
3582 u16 shm_offset)
3583{
3584 u16 params[B43_NR_QOSPARAMS];
0b57664c 3585 int bslots, tmp;
e6f5b934
MB		 3586 unsigned int i;
3587
b0544eb6
MB		 3588 if (!dev->qos_enabled)
3589 return;
3590
0b57664c 3591 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3592
3593 memset(&params, 0, sizeof(params));
3594
3595 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3596 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3597 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3598 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3599 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3600 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3601 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3602
3603 for (i = 0; i < ARRAY_SIZE(params); i++) {
3604 if (i == B43_QOSPARAM_STATUS) {
3605 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3606 shm_offset + (i * 2));
3607 /* Mark the parameters as updated. */
3608 tmp |= 0x100;
3609 b43_shm_write16(dev, B43_SHM_SHARED,
3610 shm_offset + (i * 2),
3611 tmp);
3612 } else {
3613 b43_shm_write16(dev, B43_SHM_SHARED,
3614 shm_offset + (i * 2),
3615 params[i]);
3616 }
3617 }
3618}
3619
c40c1129
MB		 3620/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3621static const u16 b43_qos_shm_offsets[] = {
3622 /* [mac80211-queue-nr] = SHM_OFFSET, */
3623 [0] = B43_QOS_VOICE,
3624 [1] = B43_QOS_VIDEO,
3625 [2] = B43_QOS_BESTEFFORT,
3626 [3] = B43_QOS_BACKGROUND,
3627};
3628
5a5f3b40
MB		 3629/* Update all QOS parameters in hardware. */
3630static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3631{
3632 struct b43_wl *wl = dev->wl;
3633 struct b43_qos_params *params;
e6f5b934
MB		 3634 unsigned int i;
3635
b0544eb6
MB		 3636 if (!dev->qos_enabled)
3637 return;
3638
c40c1129
MB		 3639 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3640 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3641
3642 b43_mac_suspend(dev);
e6f5b934
MB		 3643 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3644 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3645 b43_qos_params_upload(dev, &(params->p),
3646 b43_qos_shm_offsets[i]);
e6f5b934 3647 }
e6f5b934
MB		 3648 b43_mac_enable(dev);
3649}
3650
3651static void b43_qos_clear(struct b43_wl *wl)
3652{
3653 struct b43_qos_params *params;
3654 unsigned int i;
3655
c40c1129
MB		 3656 /* Initialize QoS parameters to sane defaults. */
3657
3658 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3659 ARRAY_SIZE(wl->qos_params));
3660
e6f5b934
MB		 3661 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3662 params = &(wl->qos_params[i]);
3663
c40c1129
MB		 3664 switch (b43_qos_shm_offsets[i]) {
3665 case B43_QOS_VOICE:
3666 params->p.txop = 0;
3667 params->p.aifs = 2;
3668 params->p.cw_min = 0x0001;
3669 params->p.cw_max = 0x0001;
3670 break;
3671 case B43_QOS_VIDEO:
3672 params->p.txop = 0;
3673 params->p.aifs = 2;
3674 params->p.cw_min = 0x0001;
3675 params->p.cw_max = 0x0001;
3676 break;
3677 case B43_QOS_BESTEFFORT:
3678 params->p.txop = 0;
3679 params->p.aifs = 3;
3680 params->p.cw_min = 0x0001;
3681 params->p.cw_max = 0x03FF;
3682 break;
3683 case B43_QOS_BACKGROUND:
3684 params->p.txop = 0;
3685 params->p.aifs = 7;
3686 params->p.cw_min = 0x0001;
3687 params->p.cw_max = 0x03FF;
3688 break;
3689 default:
3690 B43_WARN_ON(1);
3691 }
e6f5b934
MB		 3692 }
3693}
3694
3695/* Initialize the core's QOS capabilities */
3696static void b43_qos_init(struct b43_wldev *dev)
3697{
b0544eb6
MB		 3698 if (!dev->qos_enabled) {
3699 /* Disable QOS support. */
3700 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3701 b43_write16(dev, B43_MMIO_IFSCTL,
3702 b43_read16(dev, B43_MMIO_IFSCTL)
3703 & ~B43_MMIO_IFSCTL_USE_EDCF);
3704 b43dbg(dev->wl, "QoS disabled\n");
3705 return;
3706 }
3707
e6f5b934 3708 /* Upload the current QOS parameters. */
5a5f3b40 3709 b43_qos_upload_all(dev);
e6f5b934
MB		 3710
3711 /* Enable QOS support. */
3712 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3713 b43_write16(dev, B43_MMIO_IFSCTL,
3714 b43_read16(dev, B43_MMIO_IFSCTL)
3715 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3716 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3717}
3718
8a3a3c85
EP		 3719static int b43_op_conf_tx(struct ieee80211_hw *hw,
3720 struct ieee80211_vif *vif, u16 _queue,
40faacc4 3721 const struct ieee80211_tx_queue_params *params)
e4d6b795 3722{
e6f5b934 3723 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3724 struct b43_wldev *dev;
e6f5b934 3725 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3726 int err = -ENODEV;
e6f5b934
MB		 3727
3728 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3729 /* Queue not available or don't support setting
3730 * params on this queue. Return success to not
3731 * confuse mac80211. */
3732 return 0;
3733 }
5a5f3b40
MB		 3734 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3735 ARRAY_SIZE(wl->qos_params));
e6f5b934 3736
5a5f3b40
MB		 3737 mutex_lock(&wl->mutex);
3738 dev = wl->current_dev;
3739 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3740 goto out_unlock;
e6f5b934 3741
5a5f3b40
MB		 3742 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3743 b43_mac_suspend(dev);
3744 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3745 b43_qos_shm_offsets[queue]);
3746 b43_mac_enable(dev);
3747 err = 0;
e6f5b934 3748
5a5f3b40
MB		 3749out_unlock:
3750 mutex_unlock(&wl->mutex);
3751
3752 return err;
e4d6b795
MB		 3753}
3754
40faacc4
MB		 3755static int b43_op_get_stats(struct ieee80211_hw *hw,
3756 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3757{
3758 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3759
36dbd954 3760 mutex_lock(&wl->mutex);
e4d6b795 3761 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3762 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3763
3764 return 0;
3765}
3766
37a41b4a 3767static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
08e87a83
AF		 3768{
3769 struct b43_wl *wl = hw_to_b43_wl(hw);
3770 struct b43_wldev *dev;
3771 u64 tsf;
3772
3773 mutex_lock(&wl->mutex);
08e87a83
AF		 3774 dev = wl->current_dev;
3775
3776 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3777 b43_tsf_read(dev, &tsf);
3778 else
3779 tsf = 0;
3780
08e87a83
AF		 3781 mutex_unlock(&wl->mutex);
3782
3783 return tsf;
3784}
3785
37a41b4a
EP		 3786static void b43_op_set_tsf(struct ieee80211_hw *hw,
3787 struct ieee80211_vif *vif, u64 tsf)
08e87a83
AF		 3788{
3789 struct b43_wl *wl = hw_to_b43_wl(hw);
3790 struct b43_wldev *dev;
3791
3792 mutex_lock(&wl->mutex);
08e87a83
AF		 3793 dev = wl->current_dev;
3794
3795 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3796 b43_tsf_write(dev, tsf);
3797
08e87a83
AF		 3798 mutex_unlock(&wl->mutex);
3799}
3800
99da185a 3801static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3802{
3803 switch (band) {
3804 case IEEE80211_BAND_5GHZ:
3805 return "5";
3806 case IEEE80211_BAND_2GHZ:
3807 return "2.4";
3808 default:
3809 break;
3810 }
3811 B43_WARN_ON(1);
3812 return "";
3813}
3814
e4d6b795 3815/* Expects wl->mutex locked */
7a8af8cf
RM		 3816static int b43_switch_band(struct b43_wldev *dev,
3817 struct ieee80211_channel *chan)
e4d6b795 3818{
7a8af8cf
RM		 3819 struct b43_phy *phy = &dev->phy;
3820 bool gmode;
3821 u32 tmp;
e4d6b795 3822
644aa4d6
RM		 3823 switch (chan->band) {
3824 case IEEE80211_BAND_5GHZ:
7a8af8cf 3825 gmode = false;
644aa4d6
RM		 3826 break;
3827 case IEEE80211_BAND_2GHZ:
7a8af8cf 3828 gmode = true;
644aa4d6
RM		 3829 break;
3830 default:
3831 B43_WARN_ON(1);
3832 return -EINVAL;
bb1eeff1 3833 }
644aa4d6 3834
7a8af8cf
RM		 3835 if (!((gmode && phy->supports_2ghz) ||
3836 (!gmode && phy->supports_5ghz))) {
3837 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
bb1eeff1
MB		 3838 band_to_string(chan->band));
3839 return -ENODEV;
e4d6b795 3840 }
7a8af8cf
RM		 3841
3842 if (!!phy->gmode == !!gmode) {
e4d6b795
MB		 3843 /* This device is already running. */
3844 return 0;
3845 }
7a8af8cf
RM		 3846
3847 b43dbg(dev->wl, "Switching to %s GHz band\n",
bb1eeff1 3848 band_to_string(chan->band));
7a8af8cf 3849
6fe55143
RM		 3850 /* Some new devices don't need disabling radio for band switching */
3851 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3852 b43_software_rfkill(dev, true);
7a8af8cf
RM		 3853
3854 phy->gmode = gmode;
3855 b43_phy_put_into_reset(dev);
3856 switch (dev->dev->bus_type) {
3857#ifdef CONFIG_B43_BCMA
3858 case B43_BUS_BCMA:
3859 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3860 if (gmode)
3861 tmp |= B43_BCMA_IOCTL_GMODE;
3862 else
3863 tmp &= ~B43_BCMA_IOCTL_GMODE;
3864 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3865 break;
3866#endif
3867#ifdef CONFIG_B43_SSB
3868 case B43_BUS_SSB:
3869 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3870 if (gmode)
3871 tmp |= B43_TMSLOW_GMODE;
3872 else
3873 tmp &= ~B43_TMSLOW_GMODE;
3874 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3875 break;
3876#endif
e4d6b795 3877 }
7a8af8cf 3878 b43_phy_take_out_of_reset(dev);
e4d6b795 3879
7a8af8cf
RM		 3880 b43_upload_initvals_band(dev);
3881
3882 b43_phy_init(dev);
e4d6b795
MB		 3883
3884 return 0;
e4d6b795
MB		 3885}
3886
9124b077
JB		 3887/* Write the short and long frame retry limit values. */
3888static void b43_set_retry_limits(struct b43_wldev *dev,
3889 unsigned int short_retry,
3890 unsigned int long_retry)
3891{
3892 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3893 * the chip-internal counter. */
3894 short_retry = min(short_retry, (unsigned int)0xF);
3895 long_retry = min(long_retry, (unsigned int)0xF);
3896
3897 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3898 short_retry);
3899 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3900 long_retry);
3901}
3902
e8975581 3903static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3904{
3905 struct b43_wl *wl = hw_to_b43_wl(hw);
53256511
RM		 3906 struct b43_wldev *dev = wl->current_dev;
3907 struct b43_phy *phy = &dev->phy;
e8975581 3908 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3909 int antenna;
e4d6b795 3910 int err = 0;
e4d6b795 3911
e4d6b795 3912 mutex_lock(&wl->mutex);
7a8af8cf
RM		 3913 b43_mac_suspend(dev);
3914
8c79e5ee 3915 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
ea42e71c 3916 phy->chandef = &conf->chandef;
f9471e99 3917 phy->channel = conf->chandef.chan->hw_value;
2a190322 3918
8c79e5ee
RM		 3919 /* Switch the band (if necessary). */
3920 err = b43_switch_band(dev, conf->chandef.chan);
3921 if (err)
3922 goto out_mac_enable;
3923
3924 /* Switch to the requested channel.
3925 * The firmware takes care of races with the TX handler.
3926 */
f9471e99 3927 b43_switch_channel(dev, phy->channel);
8c79e5ee 3928 }
aa4c7b2a 3929
9124b077
JB		 3930 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3931 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3932 conf->long_frame_max_tx_count);
3933 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3934 if (!changed)
d10d0e57 3935 goto out_mac_enable;
e4d6b795 3936
0869aea0 3937 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3938
e4d6b795
MB		 3939 /* Adjust the desired TX power level. */
3940 if (conf->power_level != 0) {
18c8adeb
MB		 3941 if (conf->power_level != phy->desired_txpower) {
3942 phy->desired_txpower = conf->power_level;
3943 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3944 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3945 }
3946 }
3947
3948 /* Antennas for RX and management frame TX. */
0f4ac38b 3949 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3950 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3951 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3952 if (phy->ops->set_rx_antenna)
3953 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3954
fd4973c5
LF		 3955 if (wl->radio_enabled != phy->radio_on) {
3956 if (wl->radio_enabled) {
19d337df 3957 b43_software_rfkill(dev, false);
fda9abcf
MB		 3958 b43info(dev->wl, "Radio turned on by software\n");
3959 if (!dev->radio_hw_enable) {
3960 b43info(dev->wl, "The hardware RF-kill button "
3961 "still turns the radio physically off. "
3962 "Press the button to turn it on.\n");
3963 }
3964 } else {
19d337df 3965 b43_software_rfkill(dev, true);
fda9abcf
MB		 3966 b43info(dev->wl, "Radio turned off by software\n");
3967 }
3968 }
3969
d10d0e57
MB		 3970out_mac_enable:
3971 b43_mac_enable(dev);
e4d6b795
MB		 3972 mutex_unlock(&wl->mutex);
3973
3974 return err;
3975}
3976
881d948c 3977static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3978{
3979 struct ieee80211_supported_band *sband =
3980 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3981 struct ieee80211_rate *rate;
3982 int i;
3983 u16 basic, direct, offset, basic_offset, rateptr;
3984
3985 for (i = 0; i < sband->n_bitrates; i++) {
3986 rate = &sband->bitrates[i];
3987
3988 if (b43_is_cck_rate(rate->hw_value)) {
3989 direct = B43_SHM_SH_CCKDIRECT;
3990 basic = B43_SHM_SH_CCKBASIC;
3991 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3992 offset &= 0xF;
3993 } else {
3994 direct = B43_SHM_SH_OFDMDIRECT;
3995 basic = B43_SHM_SH_OFDMBASIC;
3996 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3997 offset &= 0xF;
3998 }
3999
4000 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
4001
4002 if (b43_is_cck_rate(rate->hw_value)) {
4003 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4004 basic_offset &= 0xF;
4005 } else {
4006 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4007 basic_offset &= 0xF;
4008 }
4009
4010 /*
4011 * Get the pointer that we need to point to
4012 * from the direct map
4013 */
4014 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
4015 direct + 2 * basic_offset);
4016 /* and write it to the basic map */
4017 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
4018 rateptr);
4019 }
4020}
4021
4022static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
4023 struct ieee80211_vif *vif,
4024 struct ieee80211_bss_conf *conf,
4025 u32 changed)
4026{
4027 struct b43_wl *wl = hw_to_b43_wl(hw);
4028 struct b43_wldev *dev;
c7ab5ef9
JB		 4029
4030 mutex_lock(&wl->mutex);
4031
4032 dev = wl->current_dev;
d10d0e57 4033 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 4034 goto out_unlock_mutex;
2d0ddec5
JB		 4035
4036 B43_WARN_ON(wl->vif != vif);
4037
4038 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 4039 if (conf->bssid)
4040 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
4041 else
4042 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 4043 }
2d0ddec5 4044
3f0d843b
JB		 4045 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
4046 if (changed & BSS_CHANGED_BEACON &&
4047 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4048 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4049 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
4050 b43_update_templates(wl);
4051
4052 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 4053 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 4054 }
4055
c7ab5ef9
JB		 4056 b43_mac_suspend(dev);
4057
57c4d7b4
JB		 4058 /* Update templates for AP/mesh mode. */
4059 if (changed & BSS_CHANGED_BEACON_INT &&
4060 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4061 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 4062 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4063 conf->beacon_int)
57c4d7b4
JB		 4064 b43_set_beacon_int(dev, conf->beacon_int);
4065
c7ab5ef9
JB		 4066 if (changed & BSS_CHANGED_BASIC_RATES)
4067 b43_update_basic_rates(dev, conf->basic_rates);
4068
4069 if (changed & BSS_CHANGED_ERP_SLOT) {
4070 if (conf->use_short_slot)
4071 b43_short_slot_timing_enable(dev);
4072 else
4073 b43_short_slot_timing_disable(dev);
4074 }
4075
4076 b43_mac_enable(dev);
d10d0e57 4077out_unlock_mutex:
c7ab5ef9 4078 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 4079}
4080
40faacc4 4081static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 4082 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4083 struct ieee80211_key_conf *key)
e4d6b795
MB		 4084{
4085 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 4086 struct b43_wldev *dev;
e4d6b795
MB		 4087 u8 algorithm;
4088 u8 index;
c6dfc9a8 4089 int err;
060210f9 4090 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 4091
4092 if (modparam_nohwcrypt)
4093 return -ENOSPC; /* User disabled HW-crypto */
4094
78f9c850
AQ		 4095 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4096 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4097 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4098 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4099 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4100 /*
4101 * For now, disable hw crypto for the RSN IBSS group keys. This
4102 * could be optimized in the future, but until that gets
4103 * implemented, use of software crypto for group addressed
4104 * frames is a acceptable to allow RSN IBSS to be used.
4105 */
4106 return -EOPNOTSUPP;
4107 }
4108
c6dfc9a8 4109 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 4110
4111 dev = wl->current_dev;
4112 err = -ENODEV;
4113 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4114 goto out_unlock;
4115
403a3a13 4116 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 4117 /* We don't have firmware for the crypto engine.
4118 * Must use software-crypto. */
4119 err = -EOPNOTSUPP;
4120 goto out_unlock;
4121 }
4122
c6dfc9a8 4123 err = -EINVAL;
97359d12
JB		 4124 switch (key->cipher) {
4125 case WLAN_CIPHER_SUITE_WEP40:
4126 algorithm = B43_SEC_ALGO_WEP40;
4127 break;
4128 case WLAN_CIPHER_SUITE_WEP104:
4129 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4130 break;
97359d12 4131 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4132 algorithm = B43_SEC_ALGO_TKIP;
4133 break;
97359d12 4134 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4135 algorithm = B43_SEC_ALGO_AES;
4136 break;
4137 default:
4138 B43_WARN_ON(1);
c6dfc9a8 4139 goto out_unlock;
e4d6b795 4140 }
e4d6b795
MB		 4141 index = (u8) (key->keyidx);
4142 if (index > 3)
e4d6b795 4143 goto out_unlock;
e4d6b795
MB		 4144
4145 switch (cmd) {
4146 case SET_KEY:
035d0243 4147 if (algorithm == B43_SEC_ALGO_TKIP &&
4148 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4149 !modparam_hwtkip)) {
4150 /* We support only pairwise key */
e4d6b795
MB		 4151 err = -EOPNOTSUPP;
4152 goto out_unlock;
4153 }
4154
e808e586 4155 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4156 if (WARN_ON(!sta)) {
4157 err = -EOPNOTSUPP;
4158 goto out_unlock;
4159 }
e808e586 4160 /* Pairwise key with an assigned MAC address. */
e4d6b795 4161 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4162 key->key, key->keylen,
4163 sta->addr, key);
e808e586
MB		 4164 } else {
4165 /* Group key */
4166 err = b43_key_write(dev, index, algorithm,
4167 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4168 }
4169 if (err)
4170 goto out_unlock;
4171
4172 if (algorithm == B43_SEC_ALGO_WEP40 ||
4173 algorithm == B43_SEC_ALGO_WEP104) {
4174 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4175 } else {
4176 b43_hf_write(dev,
4177 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4178 }
4179 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4180 if (algorithm == B43_SEC_ALGO_TKIP)
4181 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4182 break;
4183 case DISABLE_KEY: {
4184 err = b43_key_clear(dev, key->hw_key_idx);
4185 if (err)
4186 goto out_unlock;
4187 break;
4188 }
4189 default:
4190 B43_WARN_ON(1);
4191 }
9cf7f247 4192
e4d6b795 4193out_unlock:
e4d6b795
MB		 4194 if (!err) {
4195 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4196 "mac: %pM\n",
e4d6b795 4197 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4198 sta ? sta->addr : bcast_addr);
9cf7f247 4199 b43_dump_keymemory(dev);
e4d6b795 4200 }
9cf7f247
MB		 4201 mutex_unlock(&wl->mutex);
4202
e4d6b795
MB		 4203 return err;
4204}
4205
40faacc4
MB		 4206static void b43_op_configure_filter(struct ieee80211_hw *hw,
4207 unsigned int changed, unsigned int *fflags,
3ac64bee 4208 u64 multicast)
e4d6b795
MB		 4209{
4210 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4211 struct b43_wldev *dev;
e4d6b795 4212
36dbd954
MB		 4213 mutex_lock(&wl->mutex);
4214 dev = wl->current_dev;
4150c572
JB		 4215 if (!dev) {
4216 *fflags = 0;
36dbd954 4217 goto out_unlock;
e4d6b795 4218 }
4150c572 4219
4150c572
JB		 4220 *fflags &= FIF_PROMISC_IN_BSS |
4221 FIF_ALLMULTI |
4222 FIF_FCSFAIL |
4223 FIF_PLCPFAIL |
4224 FIF_CONTROL |
4225 FIF_OTHER_BSS |
4226 FIF_BCN_PRBRESP_PROMISC;
4227
4228 changed &= FIF_PROMISC_IN_BSS |
4229 FIF_ALLMULTI |
4230 FIF_FCSFAIL |
4231 FIF_PLCPFAIL |
4232 FIF_CONTROL |
4233 FIF_OTHER_BSS |
4234 FIF_BCN_PRBRESP_PROMISC;
4235
4236 wl->filter_flags = *fflags;
4237
4238 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4239 b43_adjust_opmode(dev);
36dbd954
MB		 4240
4241out_unlock:
4242 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4243}
4244
36dbd954
MB		 4245/* Locking: wl->mutex
4246 * Returns the current dev. This might be different from the passed in dev,
4247 * because the core might be gone away while we unlocked the mutex. */
4248static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795 4249{
9a53bf54 4250 struct b43_wl *wl;
36dbd954 4251 struct b43_wldev *orig_dev;
49d965c8 4252 u32 mask;
bad69194 4253 int queue_num;
e4d6b795 4254
9a53bf54
LF		 4255 if (!dev)
4256 return NULL;
4257 wl = dev->wl;
36dbd954
MB		 4258redo:
4259 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4260 return dev;
a19d12d7 4261
f5d40eed 4262 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4263 mutex_unlock(&wl->mutex);
4264 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4265 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 4266 mutex_lock(&wl->mutex);
4267 dev = wl->current_dev;
4268 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4269 /* Whoops, aliens ate up the device while we were unlocked. */
4270 return dev;
4271 }
a19d12d7 4272
36dbd954 4273 /* Disable interrupts on the device. */
e4d6b795 4274 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4275 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4276 /* wl->mutex is locked. That is enough. */
4277 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4278 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4279 } else {
4280 spin_lock_irq(&wl->hardirq_lock);
4281 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4282 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4283 spin_unlock_irq(&wl->hardirq_lock);
4284 }
176e9f6a 4285 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4286 orig_dev = dev;
e4d6b795 4287 mutex_unlock(&wl->mutex);
505fb019 4288 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4289 b43_sdio_free_irq(dev);
4290 } else {
a18c715e
RM		 4291 synchronize_irq(dev->dev->irq);
4292 free_irq(dev->dev->irq, dev);
176e9f6a 4293 }
e4d6b795 4294 mutex_lock(&wl->mutex);
36dbd954
MB		 4295 dev = wl->current_dev;
4296 if (!dev)
4297 return dev;
4298 if (dev != orig_dev) {
4299 if (b43_status(dev) >= B43_STAT_STARTED)
4300 goto redo;
4301 return dev;
4302 }
49d965c8
MB		 4303 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4304 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4305
bad69194 4306 /* Drain all TX queues. */
4307 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
78f18df4
FF		 4308 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4309 struct sk_buff *skb;
4310
4311 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4312 ieee80211_free_txskb(wl->hw, skb);
4313 }
bad69194 4314 }
f5d40eed 4315
e4d6b795 4316 b43_mac_suspend(dev);
a78b3bb2 4317 b43_leds_exit(dev);
e4d6b795 4318 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4319
4320 return dev;
e4d6b795
MB		 4321}
4322
4323/* Locking: wl->mutex */
4324static int b43_wireless_core_start(struct b43_wldev *dev)
4325{
4326 int err;
4327
4328 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4329
4330 drain_txstatus_queue(dev);
505fb019 4331 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4332 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4333 if (err) {
4334 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4335 goto out;
4336 }
4337 } else {
a18c715e 4338 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4339 b43_interrupt_thread_handler,
4340 IRQF_SHARED, KBUILD_MODNAME, dev);
4341 if (err) {
dedb1eb9 4342 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4343 dev->dev->irq);
3dbba8e2
AH		 4344 goto out;
4345 }
e4d6b795
MB		 4346 }
4347
4348 /* We are ready to run. */
0866b03c 4349 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4350 b43_set_status(dev, B43_STAT_STARTED);
4351
4352 /* Start data flow (TX/RX). */
4353 b43_mac_enable(dev);
13790728 4354 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4355
25985edc 4356 /* Start maintenance work */
e4d6b795
MB		 4357 b43_periodic_tasks_setup(dev);
4358
a78b3bb2
MB		 4359 b43_leds_init(dev);
4360
e4d6b795 4361 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4362out:
e4d6b795
MB		 4363 return err;
4364}
4365
2fdf8c54
RM		 4366static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4367{
4368 switch (phy_type) {
4369 case B43_PHYTYPE_A:
4370 return "A";
4371 case B43_PHYTYPE_B:
4372 return "B";
4373 case B43_PHYTYPE_G:
4374 return "G";
4375 case B43_PHYTYPE_N:
4376 return "N";
4377 case B43_PHYTYPE_LP:
4378 return "LP";
4379 case B43_PHYTYPE_SSLPN:
4380 return "SSLPN";
4381 case B43_PHYTYPE_HT:
4382 return "HT";
4383 case B43_PHYTYPE_LCN:
4384 return "LCN";
4385 case B43_PHYTYPE_LCNXN:
4386 return "LCNXN";
4387 case B43_PHYTYPE_LCN40:
4388 return "LCN40";
4389 case B43_PHYTYPE_AC:
4390 return "AC";
4391 }
4392 return "UNKNOWN";
4393}
4394
e4d6b795
MB		 4395/* Get PHY and RADIO versioning numbers */
4396static int b43_phy_versioning(struct b43_wldev *dev)
4397{
4398 struct b43_phy *phy = &dev->phy;
fe5e499f 4399 const u8 core_rev = dev->dev->core_rev;
e4d6b795
MB		 4400 u32 tmp;
4401 u8 analog_type;
4402 u8 phy_type;
4403 u8 phy_rev;
4404 u16 radio_manuf;
16e75453 4405 u16 radio_id;
e4d6b795 4406 u16 radio_rev;
16e75453 4407 u8 radio_ver;
e4d6b795
MB		 4408 int unsupported = 0;
4409
4410 /* Get PHY versioning */
4411 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4412 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4413 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4414 phy_rev = (tmp & B43_PHYVER_VERSION);
b49c3caf
RM		 4415
4416 /* LCNXN is continuation of N which run out of revisions */
4417 if (phy_type == B43_PHYTYPE_LCNXN) {
4418 phy_type = B43_PHYTYPE_N;
4419 phy_rev += 16;
4420 }
4421
e4d6b795 4422 switch (phy_type) {
418378fe 4423#ifdef CONFIG_B43_PHY_G
e4d6b795 4424 case B43_PHYTYPE_G:
013978b6 4425 if (phy_rev > 9)
e4d6b795
MB		 4426 unsupported = 1;
4427 break;
418378fe 4428#endif
692d2c0f 4429#ifdef CONFIG_B43_PHY_N
d5c71e46 4430 case B43_PHYTYPE_N:
40c68f20 4431 if (phy_rev >= 19)
d5c71e46
MB		 4432 unsupported = 1;
4433 break;
6b1c7c67
MB		 4434#endif
4435#ifdef CONFIG_B43_PHY_LP
4436 case B43_PHYTYPE_LP:
9d86a2d5 4437 if (phy_rev > 2)
6b1c7c67
MB		 4438 unsupported = 1;
4439 break;
d7520b1d
RM		 4440#endif
4441#ifdef CONFIG_B43_PHY_HT
4442 case B43_PHYTYPE_HT:
4443 if (phy_rev > 1)
4444 unsupported = 1;
4445 break;
1d738e64
RM		 4446#endif
4447#ifdef CONFIG_B43_PHY_LCN
4448 case B43_PHYTYPE_LCN:
4449 if (phy_rev > 1)
4450 unsupported = 1;
4451 break;
d5c71e46 4452#endif
e4d6b795
MB		 4453 default:
4454 unsupported = 1;
6403eab1 4455 }
e4d6b795 4456 if (unsupported) {
2fdf8c54
RM		 4457 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4458 analog_type, phy_type, b43_phy_name(dev, phy_type),
4459 phy_rev);
e4d6b795
MB		 4460 return -EOPNOTSUPP;
4461 }
2fdf8c54
RM		 4462 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4463 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
e4d6b795
MB		 4464
4465 /* Get RADIO versioning */
fe5e499f
RM		 4466 if (core_rev == 40 || core_rev == 42) {
4467 radio_manuf = 0x17F;
4468
25c15566 4469 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0);
fe5e499f
RM		 4470 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4471
25c15566 4472 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1);
16e75453
RM		 4473 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4474
4475 radio_ver = 0; /* Is there version somewhere? */
fe5e499f 4476 } else if (core_rev >= 24) {
544e5d8b
RM		 4477 u16 radio24[3];
4478
4479 for (tmp = 0; tmp < 3; tmp++) {
25c15566 4480 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp);
544e5d8b
RM		 4481 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4482 }
4483
544e5d8b 4484 radio_manuf = 0x17F;
16e75453 4485 radio_id = (radio24[2] << 8) | radio24[1];
544e5d8b 4486 radio_rev = (radio24[0] & 0xF);
16e75453 4487 radio_ver = (radio24[0] & 0xF0) >> 4;
e4d6b795 4488 } else {
3fd48508
RM		 4489 if (dev->dev->chip_id == 0x4317) {
4490 if (dev->dev->chip_rev == 0)
4491 tmp = 0x3205017F;
4492 else if (dev->dev->chip_rev == 1)
4493 tmp = 0x4205017F;
4494 else
4495 tmp = 0x5205017F;
4496 } else {
25c15566
RM		 4497 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4498 B43_RADIOCTL_ID);
3fd48508 4499 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
25c15566
RM		 4500 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4501 B43_RADIOCTL_ID);
4502 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3fd48508
RM		 4503 }
4504 radio_manuf = (tmp & 0x00000FFF);
16e75453 4505 radio_id = (tmp & 0x0FFFF000) >> 12;
3fd48508 4506 radio_rev = (tmp & 0xF0000000) >> 28;
16e75453 4507 radio_ver = 0; /* Probably not available on old hw */
e4d6b795 4508 }
3fd48508 4509
96c755a3
MB		 4510 if (radio_manuf != 0x17F /* Broadcom */)
4511 unsupported = 1;
e4d6b795
MB		 4512 switch (phy_type) {
4513 case B43_PHYTYPE_A:
16e75453 4514 if (radio_id != 0x2060)
e4d6b795
MB		 4515 unsupported = 1;
4516 if (radio_rev != 1)
4517 unsupported = 1;
4518 if (radio_manuf != 0x17F)
4519 unsupported = 1;
4520 break;
4521 case B43_PHYTYPE_B:
16e75453 4522 if ((radio_id & 0xFFF0) != 0x2050)
e4d6b795
MB		 4523 unsupported = 1;
4524 break;
4525 case B43_PHYTYPE_G:
16e75453 4526 if (radio_id != 0x2050)
e4d6b795
MB		 4527 unsupported = 1;
4528 break;
96c755a3 4529 case B43_PHYTYPE_N:
16e75453
RM		 4530 if (radio_id != 0x2055 && radio_id != 0x2056 &&
4531 radio_id != 0x2057)
3695b932 4532 unsupported = 1;
16e75453 4533 if (radio_id == 0x2057 &&
c11082f0 4534 !(radio_rev == 9 || radio_rev == 14))
96c755a3
MB		 4535 unsupported = 1;
4536 break;
6b1c7c67 4537 case B43_PHYTYPE_LP:
16e75453 4538 if (radio_id != 0x2062 && radio_id != 0x2063)
6b1c7c67
MB		 4539 unsupported = 1;
4540 break;
d7520b1d 4541 case B43_PHYTYPE_HT:
16e75453 4542 if (radio_id != 0x2059)
d7520b1d
RM		 4543 unsupported = 1;
4544 break;
1d738e64 4545 case B43_PHYTYPE_LCN:
16e75453 4546 if (radio_id != 0x2064)
1d738e64
RM		 4547 unsupported = 1;
4548 break;
e4d6b795
MB		 4549 default:
4550 B43_WARN_ON(1);
4551 }
4552 if (unsupported) {
88d825bf 4553 b43err(dev->wl,
16e75453
RM		 4554 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n",
4555 radio_manuf, radio_id, radio_rev, radio_ver);
e4d6b795
MB		 4556 return -EOPNOTSUPP;
4557 }
16e75453
RM		 4558 b43info(dev->wl,
4559 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n",
4560 radio_manuf, radio_id, radio_rev, radio_ver);
e4d6b795 4561
16e75453 4562 /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */
e4d6b795 4563 phy->radio_manuf = radio_manuf;
16e75453 4564 phy->radio_ver = radio_id;
e4d6b795
MB		 4565 phy->radio_rev = radio_rev;
4566
4567 phy->analog = analog_type;
4568 phy->type = phy_type;
4569 phy->rev = phy_rev;
4570
4571 return 0;
4572}
4573
4574static void setup_struct_phy_for_init(struct b43_wldev *dev,
4575 struct b43_phy *phy)
4576{
e4d6b795 4577 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4578 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4579 /* PHY TX errors counter. */
4580 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4581
4582#if B43_DEBUG
3db1cd5c
RR		 4583 phy->phy_locked = false;
4584 phy->radio_locked = false;
591f3dc2 4585#endif
e4d6b795
MB		 4586}
4587
4588static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4589{
3db1cd5c 4590 dev->dfq_valid = false;
aa6c7ae2 4591
6a724d68
MB		 4592 /* Assume the radio is enabled. If it's not enabled, the state will
4593 * immediately get fixed on the first periodic work run. */
3db1cd5c 4594 dev->radio_hw_enable = true;
e4d6b795
MB		 4595
4596 /* Stats */
4597 memset(&dev->stats, 0, sizeof(dev->stats));
4598
4599 setup_struct_phy_for_init(dev, &dev->phy);
4600
4601 /* IRQ related flags */
4602 dev->irq_reason = 0;
4603 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4604 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4605 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4606 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4607
4608 dev->mac_suspended = 1;
4609
4610 /* Noise calculation context */
4611 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4612}
4613
4614static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4615{
0581483a 4616 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4617 u64 hf;
e4d6b795 4618
1855ba78
MB		 4619 if (!modparam_btcoex)
4620 return;
95de2841 4621 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4622 return;
4623 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4624 return;
4625
4626 hf = b43_hf_read(dev);
95de2841 4627 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4628 hf |= B43_HF_BTCOEXALT;
4629 else
4630 hf |= B43_HF_BTCOEX;
4631 b43_hf_write(dev, hf);
e4d6b795
MB		 4632}
4633
4634static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4635{
4636 if (!modparam_btcoex)
4637 return;
4638 //TODO
e4d6b795
MB		 4639}
4640
4641static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4642{
d48ae5c8 4643 struct ssb_bus *bus;
e4d6b795
MB		 4644 u32 tmp;
4645
bd7c8a59 4646#ifdef CONFIG_B43_SSB
d48ae5c8
RM		 4647 if (dev->dev->bus_type != B43_BUS_SSB)
4648 return;
bd7c8a59
RM		 4649#else
4650 return;
4651#endif
d48ae5c8
RM		 4652
4653 bus = dev->dev->sdev->bus;
4654
0fd82eaf
RM		 4655 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4656 (bus->chip_id == 0x4312)) {
d48ae5c8 4657 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4658 tmp &= ~SSB_IMCFGLO_REQTO;
4659 tmp &= ~SSB_IMCFGLO_SERTO;
4660 tmp |= 0x3;
d48ae5c8 4661 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4662 ssb_commit_settings(bus);
e4d6b795 4663 }
e4d6b795
MB		 4664}
4665
d59f720d
MB		 4666static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4667{
4668 u16 pu_delay;
4669
4670 /* The time value is in microseconds. */
4671 if (dev->phy.type == B43_PHYTYPE_A)
4672 pu_delay = 3700;
4673 else
4674 pu_delay = 1050;
05c914fe 4675 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4676 pu_delay = 500;
4677 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4678 pu_delay = max(pu_delay, (u16)2400);
4679
4680 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4681}
4682
4683/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4684static void b43_set_pretbtt(struct b43_wldev *dev)
4685{
4686 u16 pretbtt;
4687
4688 /* The time value is in microseconds. */
05c914fe 4689 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4690 pretbtt = 2;
4691 } else {
4692 if (dev->phy.type == B43_PHYTYPE_A)
4693 pretbtt = 120;
4694 else
4695 pretbtt = 250;
4696 }
4697 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4698 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4699}
4700
e4d6b795
MB		 4701/* Shutdown a wireless core */
4702/* Locking: wl->mutex */
4703static void b43_wireless_core_exit(struct b43_wldev *dev)
4704{
36dbd954
MB		 4705 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4706 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4707 return;
84c164a3 4708
e4d6b795
MB		 4709 b43_set_status(dev, B43_STAT_UNINIT);
4710
1f7d87b0 4711 /* Stop the microcode PSM. */
5056635c
RM		 4712 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4713 B43_MACCTL_PSM_JMP0);
1f7d87b0 4714
50023008
HM		 4715 switch (dev->dev->bus_type) {
4716#ifdef CONFIG_B43_BCMA
4717 case B43_BUS_BCMA:
4718 bcma_core_pci_down(dev->dev->bdev->bus);
4719 break;
4720#endif
4721#ifdef CONFIG_B43_SSB
4722 case B43_BUS_SSB:
4723 /* TODO */
4724 break;
4725#endif
4726 }
4727
e4d6b795 4728 b43_dma_free(dev);
5100d5ac 4729 b43_pio_free(dev);
e4d6b795 4730 b43_chip_exit(dev);
cb24f57f 4731 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4732 if (dev->wl->current_beacon) {
4733 dev_kfree_skb_any(dev->wl->current_beacon);
4734 dev->wl->current_beacon = NULL;
4735 }
4736
24ca39d6
RM		 4737 b43_device_disable(dev, 0);
4738 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4739}
4740
4741/* Initialize a wireless core */
4742static int b43_wireless_core_init(struct b43_wldev *dev)
4743{
0581483a 4744 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4745 struct b43_phy *phy = &dev->phy;
4746 int err;
a259d6a4 4747 u64 hf;
e4d6b795
MB		 4748
4749 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4750
24ca39d6 4751 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4752 if (err)
4753 goto out;
4da909e7
RM		 4754 if (!b43_device_is_enabled(dev))
4755 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4756
fb11137a 4757 /* Reset all data structures. */
e4d6b795 4758 setup_struct_wldev_for_init(dev);
fb11137a 4759 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4760
4761 /* Enable IRQ routing to this device. */
6cbab0d9 4762 switch (dev->dev->bus_type) {
42c9a458
RM		 4763#ifdef CONFIG_B43_BCMA
4764 case B43_BUS_BCMA:
dfae7143 4765 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
42c9a458 4766 dev->dev->bdev, true);
50023008 4767 bcma_core_pci_up(dev->dev->bdev->bus);
42c9a458
RM		 4768 break;
4769#endif
6cbab0d9
RM		 4770#ifdef CONFIG_B43_SSB
4771 case B43_BUS_SSB:
4772 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4773 dev->dev->sdev);
4774 break;
4775#endif
4776 }
e4d6b795
MB		 4777
4778 b43_imcfglo_timeouts_workaround(dev);
4779 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4780 if (phy->ops->prepare_hardware) {
4781 err = phy->ops->prepare_hardware(dev);
ef1a628d 4782 if (err)
fb11137a 4783 goto err_busdown;
ef1a628d 4784 }
e4d6b795
MB		 4785 err = b43_chip_init(dev);
4786 if (err)
fb11137a 4787 goto err_busdown;
e4d6b795 4788 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4789 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4790 hf = b43_hf_read(dev);
4791 if (phy->type == B43_PHYTYPE_G) {
4792 hf |= B43_HF_SYMW;
4793 if (phy->rev == 1)
4794 hf |= B43_HF_GDCW;
95de2841 4795 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4796 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4797 }
4798 if (phy->radio_ver == 0x2050) {
4799 if (phy->radio_rev == 6)
4800 hf |= B43_HF_4318TSSI;
4801 if (phy->radio_rev < 6)
4802 hf |= B43_HF_VCORECALC;
e4d6b795 4803 }
1cc8f476
MB		 4804 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4805 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
bd7c8a59 4806#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
6cbab0d9
RM		 4807 if (dev->dev->bus_type == B43_BUS_SSB &&
4808 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4809 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4810 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4811#endif
25d3ef59 4812 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4813 b43_hf_write(dev, hf);
4814
74cfdba7
MB		 4815 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4816 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4817 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4818 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4819
4820 /* Disable sending probe responses from firmware.
4821 * Setting the MaxTime to one usec will always trigger
4822 * a timeout, so we never send any probe resp.
4823 * A timeout of zero is infinite. */
4824 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4825
4826 b43_rate_memory_init(dev);
5042c507 4827 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4828
4829 /* Minimum Contention Window */
c5a079f4 4830 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4831 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4832 else
e4d6b795 4833 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4834 /* Maximum Contention Window */
4835 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4836
505fb019 4837 if (b43_bus_host_is_pcmcia(dev->dev) ||
cbe1e82a 4838 b43_bus_host_is_sdio(dev->dev)) {
3db1cd5c 4839 dev->__using_pio_transfers = true;
cbe1e82a
RM		 4840 err = b43_pio_init(dev);
4841 } else if (dev->use_pio) {
4842 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4843 "This should not be needed and will result in lower "
4844 "performance.\n");
3db1cd5c 4845 dev->__using_pio_transfers = true;
5100d5ac
MB		 4846 err = b43_pio_init(dev);
4847 } else {
3db1cd5c 4848 dev->__using_pio_transfers = false;
5100d5ac
MB		 4849 err = b43_dma_init(dev);
4850 }
e4d6b795
MB		 4851 if (err)
4852 goto err_chip_exit;
03b29773 4853 b43_qos_init(dev);
d59f720d 4854 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4855 b43_bluetooth_coext_enable(dev);
4856
24ca39d6 4857 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4858 b43_upload_card_macaddress(dev);
e4d6b795 4859 b43_security_init(dev);
e4d6b795 4860
5ab9549a 4861 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4862
4863 b43_set_status(dev, B43_STAT_INITIALIZED);
4864
1a8d1227 4865out:
e4d6b795
MB		 4866 return err;
4867
ef1a628d 4868err_chip_exit:
e4d6b795 4869 b43_chip_exit(dev);
ef1a628d 4870err_busdown:
24ca39d6 4871 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4872 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4873 return err;
4874}
4875
40faacc4 4876static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4877 struct ieee80211_vif *vif)
e4d6b795
MB		 4878{
4879 struct b43_wl *wl = hw_to_b43_wl(hw);
4880 struct b43_wldev *dev;
e4d6b795 4881 int err = -EOPNOTSUPP;
4150c572
JB		 4882
4883 /* TODO: allow WDS/AP devices to coexist */
4884
1ed32e4f
JB		 4885 if (vif->type != NL80211_IFTYPE_AP &&
4886 vif->type != NL80211_IFTYPE_MESH_POINT &&
4887 vif->type != NL80211_IFTYPE_STATION &&
4888 vif->type != NL80211_IFTYPE_WDS &&
4889 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4890 return -EOPNOTSUPP;
e4d6b795
MB		 4891
4892 mutex_lock(&wl->mutex);
4150c572 4893 if (wl->operating)
e4d6b795
MB		 4894 goto out_mutex_unlock;
4895
1ed32e4f 4896 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4897
4898 dev = wl->current_dev;
3db1cd5c 4899 wl->operating = true;
1ed32e4f
JB		 4900 wl->vif = vif;
4901 wl->if_type = vif->type;
4902 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4903
4150c572 4904 b43_adjust_opmode(dev);
d59f720d
MB		 4905 b43_set_pretbtt(dev);
4906 b43_set_synth_pu_delay(dev, 0);
4150c572 4907 b43_upload_card_macaddress(dev);
4150c572
JB		 4908
4909 err = 0;
4910 out_mutex_unlock:
4911 mutex_unlock(&wl->mutex);
4912
2a190322
FF		 4913 if (err == 0)
4914 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4915
4150c572
JB		 4916 return err;
4917}
4918
40faacc4 4919static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4920 struct ieee80211_vif *vif)
4150c572
JB		 4921{
4922 struct b43_wl *wl = hw_to_b43_wl(hw);
4923 struct b43_wldev *dev = wl->current_dev;
4150c572 4924
1ed32e4f 4925 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4926
4927 mutex_lock(&wl->mutex);
4928
4929 B43_WARN_ON(!wl->operating);
1ed32e4f 4930 B43_WARN_ON(wl->vif != vif);
32bfd35d 4931 wl->vif = NULL;
4150c572 4932
3db1cd5c 4933 wl->operating = false;
4150c572 4934
4150c572
JB		 4935 b43_adjust_opmode(dev);
4936 memset(wl->mac_addr, 0, ETH_ALEN);
4937 b43_upload_card_macaddress(dev);
4150c572
JB		 4938
4939 mutex_unlock(&wl->mutex);
4940}
4941
40faacc4 4942static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4943{
4944 struct b43_wl *wl = hw_to_b43_wl(hw);
4945 struct b43_wldev *dev = wl->current_dev;
4946 int did_init = 0;
923403b8 4947 int err = 0;
4150c572 4948
7be1bb6b
MB		 4949 /* Kill all old instance specific information to make sure
4950 * the card won't use it in the short timeframe between start
4951 * and mac80211 reconfiguring it. */
4952 memset(wl->bssid, 0, ETH_ALEN);
4953 memset(wl->mac_addr, 0, ETH_ALEN);
4954 wl->filter_flags = 0;
3db1cd5c 4955 wl->radiotap_enabled = false;
e6f5b934 4956 b43_qos_clear(wl);
3db1cd5c
RR		 4957 wl->beacon0_uploaded = false;
4958 wl->beacon1_uploaded = false;
4959 wl->beacon_templates_virgin = true;
4960 wl->radio_enabled = true;
7be1bb6b 4961
4150c572
JB		 4962 mutex_lock(&wl->mutex);
4963
e4d6b795
MB		 4964 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4965 err = b43_wireless_core_init(dev);
f41f3f37 4966 if (err)
e4d6b795
MB		 4967 goto out_mutex_unlock;
4968 did_init = 1;
4969 }
4150c572 4970
e4d6b795
MB		 4971 if (b43_status(dev) < B43_STAT_STARTED) {
4972 err = b43_wireless_core_start(dev);
4973 if (err) {
4974 if (did_init)
4975 b43_wireless_core_exit(dev);
4976 goto out_mutex_unlock;
4977 }
4978 }
4979
f41f3f37
JB		 4980 /* XXX: only do if device doesn't support rfkill irq */
4981 wiphy_rfkill_start_polling(hw->wiphy);
4982
4150c572 4983 out_mutex_unlock:
e4d6b795
MB		 4984 mutex_unlock(&wl->mutex);
4985
dbdedbdf
SF		 4986 /*
4987 * Configuration may have been overwritten during initialization.
4988 * Reload the configuration, but only if initialization was
4989 * successful. Reloading the configuration after a failed init
4990 * may hang the system.
4991 */
4992 if (!err)
4993 b43_op_config(hw, ~0);
2a190322 4994
e4d6b795
MB		 4995 return err;
4996}
4997
40faacc4 4998static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4999{
5000 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 5001 struct b43_wldev *dev = wl->current_dev;
e4d6b795 5002
a82d9922 5003 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 5004
ccde8a45
GL		 5005 if (!dev)
5006 goto out;
5007
e4d6b795 5008 mutex_lock(&wl->mutex);
36dbd954
MB		 5009 if (b43_status(dev) >= B43_STAT_STARTED) {
5010 dev = b43_wireless_core_stop(dev);
5011 if (!dev)
5012 goto out_unlock;
5013 }
4150c572 5014 b43_wireless_core_exit(dev);
3db1cd5c 5015 wl->radio_enabled = false;
36dbd954
MB		 5016
5017out_unlock:
e4d6b795 5018 mutex_unlock(&wl->mutex);
ccde8a45 5019out:
18c8adeb 5020 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 5021}
5022
17741cdc
JB		 5023static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
5024 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 5025{
5026 struct b43_wl *wl = hw_to_b43_wl(hw);
5027
8f611288 5028 /* FIXME: add locking */
9d139c81 5029 b43_update_templates(wl);
e66fee6a
MB		 5030
5031 return 0;
5032}
5033
38968d09
JB		 5034static void b43_op_sta_notify(struct ieee80211_hw *hw,
5035 struct ieee80211_vif *vif,
5036 enum sta_notify_cmd notify_cmd,
17741cdc 5037 struct ieee80211_sta *sta)
38968d09
JB		 5038{
5039 struct b43_wl *wl = hw_to_b43_wl(hw);
5040
5041 B43_WARN_ON(!vif || wl->vif != vif);
5042}
5043
25d3ef59
MB		 5044static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
5045{
5046 struct b43_wl *wl = hw_to_b43_wl(hw);
5047 struct b43_wldev *dev;
5048
5049 mutex_lock(&wl->mutex);
5050 dev = wl->current_dev;
5051 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5052 /* Disable CFP update during scan on other channels. */
5053 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
5054 }
5055 mutex_unlock(&wl->mutex);
5056}
5057
5058static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
5059{
5060 struct b43_wl *wl = hw_to_b43_wl(hw);
5061 struct b43_wldev *dev;
5062
5063 mutex_lock(&wl->mutex);
5064 dev = wl->current_dev;
5065 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5066 /* Re-enable CFP update. */
5067 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
5068 }
5069 mutex_unlock(&wl->mutex);
5070}
5071
354b4f04
JL		 5072static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5073 struct survey_info *survey)
5074{
5075 struct b43_wl *wl = hw_to_b43_wl(hw);
5076 struct b43_wldev *dev = wl->current_dev;
5077 struct ieee80211_conf *conf = &hw->conf;
5078
5079 if (idx != 0)
5080 return -ENOENT;
5081
675a0b04 5082 survey->channel = conf->chandef.chan;
354b4f04
JL		 5083 survey->filled = SURVEY_INFO_NOISE_DBM;
5084 survey->noise = dev->stats.link_noise;
5085
5086 return 0;
5087}
5088
e4d6b795 5089static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 5090 .tx = b43_op_tx,
5091 .conf_tx = b43_op_conf_tx,
5092 .add_interface = b43_op_add_interface,
5093 .remove_interface = b43_op_remove_interface,
5094 .config = b43_op_config,
c7ab5ef9 5095 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 5096 .configure_filter = b43_op_configure_filter,
5097 .set_key = b43_op_set_key,
035d0243 5098 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 5099 .get_stats = b43_op_get_stats,
08e87a83
AF		 5100 .get_tsf = b43_op_get_tsf,
5101 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 5102 .start = b43_op_start,
5103 .stop = b43_op_stop,
e66fee6a 5104 .set_tim = b43_op_beacon_set_tim,
38968d09 5105 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 5106 .sw_scan_start = b43_op_sw_scan_start_notifier,
5107 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 5108 .get_survey = b43_op_get_survey,
f41f3f37 5109 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 5110};
5111
5112/* Hard-reset the chip. Do not call this directly.
5113 * Use b43_controller_restart()
5114 */
5115static void b43_chip_reset(struct work_struct *work)
5116{
5117 struct b43_wldev *dev =
5118 container_of(work, struct b43_wldev, restart_work);
5119 struct b43_wl *wl = dev->wl;
5120 int err = 0;
5121 int prev_status;
5122
5123 mutex_lock(&wl->mutex);
5124
5125 prev_status = b43_status(dev);
5126 /* Bring the device down... */
36dbd954
MB		 5127 if (prev_status >= B43_STAT_STARTED) {
5128 dev = b43_wireless_core_stop(dev);
5129 if (!dev) {
5130 err = -ENODEV;
5131 goto out;
5132 }
5133 }
e4d6b795
MB		 5134 if (prev_status >= B43_STAT_INITIALIZED)
5135 b43_wireless_core_exit(dev);
5136
5137 /* ...and up again. */
5138 if (prev_status >= B43_STAT_INITIALIZED) {
5139 err = b43_wireless_core_init(dev);
5140 if (err)
5141 goto out;
5142 }
5143 if (prev_status >= B43_STAT_STARTED) {
5144 err = b43_wireless_core_start(dev);
5145 if (err) {
5146 b43_wireless_core_exit(dev);
5147 goto out;
5148 }
5149 }
3bf0a32e
MB		 5150out:
5151 if (err)
5152 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 5153 mutex_unlock(&wl->mutex);
2a190322
FF		 5154
5155 if (err) {
e4d6b795 5156 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 5157 return;
5158 }
5159
5160 /* reload configuration */
5161 b43_op_config(wl->hw, ~0);
5162 if (wl->vif)
5163 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5164
5165 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 5166}
5167
bb1eeff1 5168static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 5169 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 5170{
5171 struct ieee80211_hw *hw = dev->wl->hw;
3695b932
RM		 5172 struct b43_phy *phy = &dev->phy;
5173 bool limited_2g;
b453fda6 5174 bool limited_5g;
3695b932
RM		 5175
5176 /* We don't support all 2 GHz channels on some devices */
c11082f0
RM		 5177 limited_2g = phy->radio_ver == 0x2057 &&
5178 (phy->radio_rev == 9 || phy->radio_rev == 14);
b453fda6
RM		 5179 limited_5g = phy->radio_ver == 0x2057 &&
5180 phy->radio_rev == 9;
e4d6b795 5181
bb1eeff1 5182 if (have_2ghz_phy)
3695b932
RM		 5183 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ?
5184 &b43_band_2ghz_limited : &b43_band_2GHz;
bb1eeff1
MB		 5185 if (dev->phy.type == B43_PHYTYPE_N) {
5186 if (have_5ghz_phy)
b453fda6
RM		 5187 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = limited_5g ?
5188 &b43_band_5GHz_nphy_limited :
5189 &b43_band_5GHz_nphy;
bb1eeff1
MB		 5190 } else {
5191 if (have_5ghz_phy)
5192 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5193 }
96c755a3 5194
bb1eeff1
MB		 5195 dev->phy.supports_2ghz = have_2ghz_phy;
5196 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 5197
5198 return 0;
5199}
5200
5201static void b43_wireless_core_detach(struct b43_wldev *dev)
5202{
5203 /* We release firmware that late to not be required to re-request
5204 * is all the time when we reinit the core. */
5205 b43_release_firmware(dev);
fb11137a 5206 b43_phy_free(dev);
e4d6b795
MB		 5207}
5208
075ca604
RM		 5209static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5210 bool *have_5ghz_phy)
5211{
5212 u16 dev_id = 0;
5213
773cfc50
RM		 5214#ifdef CONFIG_B43_BCMA
5215 if (dev->dev->bus_type == B43_BUS_BCMA &&
5216 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5217 dev_id = dev->dev->bdev->bus->host_pci->device;
5218#endif
075ca604
RM		 5219#ifdef CONFIG_B43_SSB
5220 if (dev->dev->bus_type == B43_BUS_SSB &&
5221 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5222 dev_id = dev->dev->sdev->bus->host_pci->device;
5223#endif
773cfc50
RM		 5224 /* Override with SPROM value if available */
5225 if (dev->dev->bus_sprom->dev_id)
5226 dev_id = dev->dev->bus_sprom->dev_id;
075ca604
RM		 5227
5228 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5229 switch (dev_id) {
5230 case 0x4324: /* BCM4306 */
5231 case 0x4312: /* BCM4311 */
5232 case 0x4319: /* BCM4318 */
773cfc50
RM		 5233 case 0x4328: /* BCM4321 */
5234 case 0x432b: /* BCM4322 */
5235 case 0x4350: /* BCM43222 */
5236 case 0x4353: /* BCM43224 */
5237 case 0x0576: /* BCM43224 */
5238 case 0x435f: /* BCM6362 */
5239 case 0x4331: /* BCM4331 */
5240 case 0x4359: /* BCM43228 */
5241 case 0x43a0: /* BCM4360 */
5242 case 0x43b1: /* BCM4352 */
075ca604
RM		 5243 /* Dual band devices */
5244 *have_2ghz_phy = true;
5245 *have_5ghz_phy = true;
5246 return;
773cfc50
RM		 5247 case 0x4321: /* BCM4306 */
5248 case 0x4313: /* BCM4311 */
5249 case 0x431a: /* BCM4318 */
5250 case 0x432a: /* BCM4321 */
5251 case 0x432d: /* BCM4322 */
5252 case 0x4352: /* BCM43222 */
5253 case 0x4333: /* BCM4331 */
5254 case 0x43a2: /* BCM4360 */
5255 case 0x43b3: /* BCM4352 */
5256 /* 5 GHz only devices */
5257 *have_2ghz_phy = false;
5258 *have_5ghz_phy = true;
5259 return;
075ca604
RM		 5260 }
5261
5262 /* As a fallback, try to guess using PHY type */
5263 switch (dev->phy.type) {
5264 case B43_PHYTYPE_A:
5265 *have_2ghz_phy = false;
5266 *have_5ghz_phy = true;
5267 return;
5268 case B43_PHYTYPE_G:
5269 case B43_PHYTYPE_N:
5270 case B43_PHYTYPE_LP:
5271 case B43_PHYTYPE_HT:
5272 case B43_PHYTYPE_LCN:
5273 *have_2ghz_phy = true;
5274 *have_5ghz_phy = false;
5275 return;
5276 }
5277
5278 B43_WARN_ON(1);
5279}
5280
e4d6b795
MB		 5281static int b43_wireless_core_attach(struct b43_wldev *dev)
5282{
5283 struct b43_wl *wl = dev->wl;
09951ad4 5284 struct b43_phy *phy = &dev->phy;
e4d6b795 5285 int err;
40c62269 5286 u32 tmp;
3db1cd5c 5287 bool have_2ghz_phy = false, have_5ghz_phy = false;
e4d6b795
MB		 5288
5289 /* Do NOT do any device initialization here.
5290 * Do it in wireless_core_init() instead.
5291 * This function is for gathering basic information about the HW, only.
5292 * Also some structs may be set up here. But most likely you want to have
5293 * that in core_init(), too.
5294 */
5295
24ca39d6 5296 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5297 if (err) {
5298 b43err(wl, "Bus powerup failed\n");
5299 goto out;
5300 }
e4d6b795 5301
09951ad4
RM		 5302 phy->do_full_init = true;
5303
075ca604 5304 /* Try to guess supported bands for the first init needs */
6cbab0d9 5305 switch (dev->dev->bus_type) {
42c9a458
RM		 5306#ifdef CONFIG_B43_BCMA
5307 case B43_BUS_BCMA:
40c62269
RM		 5308 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5309 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5310 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5311 break;
5312#endif
6cbab0d9
RM		 5313#ifdef CONFIG_B43_SSB
5314 case B43_BUS_SSB:
5315 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5316 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5317 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5318 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5319 } else
5320 B43_WARN_ON(1);
5321 break;
5322#endif
5323 }
e4d6b795 5324
96c755a3 5325 dev->phy.gmode = have_2ghz_phy;
4da909e7 5326 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795 5327
075ca604 5328 /* Get the PHY type. */
e4d6b795
MB		 5329 err = b43_phy_versioning(dev);
5330 if (err)
21954c36 5331 goto err_powerdown;
075ca604
RM		 5332
5333 /* Get real info about supported bands */
5334 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5335
5336 /* We don't support 5 GHz on some PHYs yet */
72fcd3d1
RM		 5337 if (have_5ghz_phy) {
5338 switch (dev->phy.type) {
5339 case B43_PHYTYPE_A:
5340 case B43_PHYTYPE_G:
72fcd3d1
RM		 5341 case B43_PHYTYPE_LP:
5342 case B43_PHYTYPE_HT:
5343 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
5344 have_5ghz_phy = false;
5345 }
e4d6b795 5346 }
075ca604
RM		 5347
5348 if (!have_2ghz_phy && !have_5ghz_phy) {
5349 b43err(wl, "b43 can't support any band on this device\n");
96c755a3
MB		 5350 err = -EOPNOTSUPP;
5351 goto err_powerdown;
5352 }
2e35af14 5353
fb11137a
MB		 5354 err = b43_phy_allocate(dev);
5355 if (err)
5356 goto err_powerdown;
5357
96c755a3 5358 dev->phy.gmode = have_2ghz_phy;
4da909e7 5359 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5360
5361 err = b43_validate_chipaccess(dev);
5362 if (err)
fb11137a 5363 goto err_phy_free;
bb1eeff1 5364 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5365 if (err)
fb11137a 5366 goto err_phy_free;
e4d6b795
MB		 5367
5368 /* Now set some default "current_dev" */
5369 if (!wl->current_dev)
5370 wl->current_dev = dev;
5371 INIT_WORK(&dev->restart_work, b43_chip_reset);
5372
cb24f57f 5373 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5374 b43_device_disable(dev, 0);
5375 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5376
5377out:
5378 return err;
5379
fb11137a
MB		 5380err_phy_free:
5381 b43_phy_free(dev);
e4d6b795 5382err_powerdown:
24ca39d6 5383 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5384 return err;
5385}
5386
482f0538 5387static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5388{
5389 struct b43_wldev *wldev;
5390 struct b43_wl *wl;
5391
3bf0a32e
MB		 5392 /* Do not cancel ieee80211-workqueue based work here.
5393 * See comment in b43_remove(). */
5394
74abacb6 5395 wldev = b43_bus_get_wldev(dev);
e4d6b795 5396 wl = wldev->wl;
e4d6b795
MB		 5397 b43_debugfs_remove_device(wldev);
5398 b43_wireless_core_detach(wldev);
5399 list_del(&wldev->list);
74abacb6 5400 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5401 kfree(wldev);
5402}
5403
482f0538 5404static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5405{
5406 struct b43_wldev *wldev;
e4d6b795
MB		 5407 int err = -ENOMEM;
5408
e4d6b795
MB		 5409 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5410 if (!wldev)
5411 goto out;
5412
9e3bd919 5413 wldev->use_pio = b43_modparam_pio;
482f0538 5414 wldev->dev = dev;
e4d6b795
MB		 5415 wldev->wl = wl;
5416 b43_set_status(wldev, B43_STAT_UNINIT);
5417 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5418 INIT_LIST_HEAD(&wldev->list);
5419
5420 err = b43_wireless_core_attach(wldev);
5421 if (err)
5422 goto err_kfree_wldev;
5423
74abacb6 5424 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5425 b43_debugfs_add_device(wldev);
5426
5427 out:
5428 return err;
5429
5430 err_kfree_wldev:
5431 kfree(wldev);
5432 return err;
5433}
5434
9fc38458
MB		 5435#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5436 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5437 (pdev->device == _device) && \
5438 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5439 (pdev->subsystem_device == _subdevice) )
5440
bd7c8a59 5441#ifdef CONFIG_B43_SSB
e4d6b795
MB		 5442static void b43_sprom_fixup(struct ssb_bus *bus)
5443{
1855ba78
MB		 5444 struct pci_dev *pdev;
5445
e4d6b795
MB		 5446 /* boardflags workarounds */
5447 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5a20ef3d 5448 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
95de2841 5449 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795 5450 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5a20ef3d 5451 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
95de2841 5452 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5453 if (bus->bustype == SSB_BUSTYPE_PCI) {
5454 pdev = bus->host_pci;
9fc38458 5455 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5456 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5457 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5458 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5459 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5460 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5461 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5462 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5463 }
e4d6b795
MB		 5464}
5465
482f0538 5466static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5467{
5468 struct ieee80211_hw *hw = wl->hw;
5469
482f0538 5470 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5471 ieee80211_free_hw(hw);
5472}
bd7c8a59 5473#endif
e4d6b795 5474
d1507051 5475static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5476{
d1507051 5477 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5478 struct ieee80211_hw *hw;
5479 struct b43_wl *wl;
2729df25 5480 char chip_name[6];
bad69194 5481 int queue_num;
e4d6b795
MB		 5482
5483 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5484 if (!hw) {
5485 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5486 return ERR_PTR(-ENOMEM);
e4d6b795 5487 }
403a3a13 5488 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5489
5490 /* fill hw info */
605a0bd6 5491 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5492 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5493
f59ac048
LR		 5494 hw->wiphy->interface_modes =
5495 BIT(NL80211_IFTYPE_AP) |
5496 BIT(NL80211_IFTYPE_MESH_POINT) |
5497 BIT(NL80211_IFTYPE_STATION) |
5498 BIT(NL80211_IFTYPE_WDS) |
5499 BIT(NL80211_IFTYPE_ADHOC);
5500
78f9c850
AQ		 5501 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5502
e64add27 5503 wl->hw_registred = false;
e6a9854b 5504 hw->max_rates = 2;
e4d6b795 5505 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5506 if (is_valid_ether_addr(sprom->et1mac))
5507 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5508 else
95de2841 5509 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5510
403a3a13 5511 /* Initialize struct b43_wl */
e4d6b795 5512 wl->hw = hw;
e4d6b795 5513 mutex_init(&wl->mutex);
36dbd954 5514 spin_lock_init(&wl->hardirq_lock);
a82d9922 5515 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5516 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed 5517 INIT_WORK(&wl->tx_work, b43_tx_work);
bad69194 5518
5519 /* Initialize queues and flags. */
5520 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5521 skb_queue_head_init(&wl->tx_queue[queue_num]);
5522 wl->tx_queue_stopped[queue_num] = 0;
5523 }
e4d6b795 5524
2729df25
RM		 5525 snprintf(chip_name, ARRAY_SIZE(chip_name),
5526 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5527 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5528 dev->core_rev);
0355a345 5529 return wl;
e4d6b795
MB		 5530}
5531
3c65ab62
RM		 5532#ifdef CONFIG_B43_BCMA
5533static int b43_bcma_probe(struct bcma_device *core)
5534{
397915c3 5535 struct b43_bus_dev *dev;
24aad3f4
RM		 5536 struct b43_wl *wl;
5537 int err;
397915c3 5538
8960400e
RM		 5539 if (!modparam_allhwsupport &&
5540 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5541 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5542 return -ENOTSUPP;
5543 }
5544
397915c3
RM		 5545 dev = b43_bus_dev_bcma_init(core);
5546 if (!dev)
5547 return -ENODEV;
5548
24aad3f4
RM		 5549 wl = b43_wireless_init(dev);
5550 if (IS_ERR(wl)) {
5551 err = PTR_ERR(wl);
5552 goto bcma_out;
5553 }
5554
5555 err = b43_one_core_attach(dev, wl);
5556 if (err)
5557 goto bcma_err_wireless_exit;
5558
6b6fa586
LF		 5559 /* setup and start work to load firmware */
5560 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5561 schedule_work(&wl->firmware_load);
24aad3f4
RM		 5562
5563bcma_out:
5564 return err;
5565
24aad3f4
RM		 5566bcma_err_wireless_exit:
5567 ieee80211_free_hw(wl->hw);
5568 return err;
3c65ab62
RM		 5569}
5570
5571static void b43_bcma_remove(struct bcma_device *core)
5572{
24aad3f4
RM		 5573 struct b43_wldev *wldev = bcma_get_drvdata(core);
5574 struct b43_wl *wl = wldev->wl;
5575
5576 /* We must cancel any work here before unregistering from ieee80211,
5577 * as the ieee80211 unreg will destroy the workqueue. */
5578 cancel_work_sync(&wldev->restart_work);
63a02ce1 5579 cancel_work_sync(&wl->firmware_load);
24aad3f4 5580
e64add27 5581 B43_WARN_ON(!wl);
f89ff644
LF		 5582 if (!wldev->fw.ucode.data)
5583 return; /* NULL if firmware never loaded */
e64add27 5584 if (wl->current_dev == wldev && wl->hw_registred) {
e64add27
OR		 5585 b43_leds_stop(wldev);
5586 ieee80211_unregister_hw(wl->hw);
5587 }
24aad3f4
RM		 5588
5589 b43_one_core_detach(wldev->dev);
5590
09164043
LF		 5591 /* Unregister HW RNG driver */
5592 b43_rng_exit(wl);
5593
24aad3f4
RM		 5594 b43_leds_unregister(wl);
5595
5596 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5597}
5598
5599static struct bcma_driver b43_bcma_driver = {
5600 .name = KBUILD_MODNAME,
5601 .id_table = b43_bcma_tbl,
5602 .probe = b43_bcma_probe,
5603 .remove = b43_bcma_remove,
5604};
5605#endif
5606
aec7ffdf 5607#ifdef CONFIG_B43_SSB
aa63418a
RM		 5608static
5609int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5610{
482f0538 5611 struct b43_bus_dev *dev;
e4d6b795
MB		 5612 struct b43_wl *wl;
5613 int err;
e4d6b795 5614
482f0538 5615 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5616 if (!dev)
5617 return -ENOMEM;
482f0538 5618
aa63418a 5619 wl = ssb_get_devtypedata(sdev);
8f15e287
RM		 5620 if (wl) {
5621 b43err(NULL, "Dual-core devices are not supported\n");
5622 err = -ENOTSUPP;
5623 goto err_ssb_kfree_dev;
e4d6b795 5624 }
8f15e287
RM		 5625
5626 b43_sprom_fixup(sdev->bus);
5627
5628 wl = b43_wireless_init(dev);
5629 if (IS_ERR(wl)) {
5630 err = PTR_ERR(wl);
5631 goto err_ssb_kfree_dev;
5632 }
5633 ssb_set_devtypedata(sdev, wl);
5634 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5635
e4d6b795
MB		 5636 err = b43_one_core_attach(dev, wl);
5637 if (err)
8f15e287 5638 goto err_ssb_wireless_exit;
e4d6b795 5639
6b6fa586
LF		 5640 /* setup and start work to load firmware */
5641 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5642 schedule_work(&wl->firmware_load);
e4d6b795 5643
e4d6b795
MB		 5644 return err;
5645
8f15e287
RM		 5646err_ssb_wireless_exit:
5647 b43_wireless_exit(dev, wl);
5648err_ssb_kfree_dev:
5649 kfree(dev);
e4d6b795
MB		 5650 return err;
5651}
5652
aa63418a 5653static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5654{
aa63418a
RM		 5655 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5656 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5657 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5658
3bf0a32e
MB		 5659 /* We must cancel any work here before unregistering from ieee80211,
5660 * as the ieee80211 unreg will destroy the workqueue. */
5661 cancel_work_sync(&wldev->restart_work);
63a02ce1 5662 cancel_work_sync(&wl->firmware_load);
3bf0a32e 5663
e4d6b795 5664 B43_WARN_ON(!wl);
f89ff644
LF		 5665 if (!wldev->fw.ucode.data)
5666 return; /* NULL if firmware never loaded */
e64add27 5667 if (wl->current_dev == wldev && wl->hw_registred) {
82905ace 5668 b43_leds_stop(wldev);
e4d6b795 5669 ieee80211_unregister_hw(wl->hw);
403a3a13 5670 }
e4d6b795 5671
e61b52d1 5672 b43_one_core_detach(dev);
e4d6b795 5673
09164043
LF		 5674 /* Unregister HW RNG driver */
5675 b43_rng_exit(wl);
5676
644aa4d6
RM		 5677 b43_leds_unregister(wl);
5678 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5679}
5680
aec7ffdf
RM		 5681static struct ssb_driver b43_ssb_driver = {
5682 .name = KBUILD_MODNAME,
5683 .id_table = b43_ssb_tbl,
5684 .probe = b43_ssb_probe,
5685 .remove = b43_ssb_remove,
5686};
5687#endif /* CONFIG_B43_SSB */
5688
e4d6b795
MB		 5689/* Perform a hardware reset. This can be called from any context. */
5690void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5691{
5692 /* Must avoid requeueing, if we are in shutdown. */
5693 if (b43_status(dev) < B43_STAT_INITIALIZED)
5694 return;
5695 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5696 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5697}
5698
26bc783f
MB		 5699static void b43_print_driverinfo(void)
5700{
5701 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5702 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5703
5704#ifdef CONFIG_B43_PCI_AUTOSELECT
5705 feat_pci = "P";
5706#endif
5707#ifdef CONFIG_B43_PCMCIA
5708 feat_pcmcia = "M";
5709#endif
692d2c0f 5710#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5711 feat_nphy = "N";
5712#endif
5713#ifdef CONFIG_B43_LEDS
5714 feat_leds = "L";
3dbba8e2
AH		 5715#endif
5716#ifdef CONFIG_B43_SDIO
5717 feat_sdio = "S";
26bc783f
MB		 5718#endif
5719 printk(KERN_INFO "Broadcom 43xx driver loaded "
8b0be90c 5720 "[ Features: %s%s%s%s%s ]\n",
26bc783f 5721 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5722 feat_leds, feat_sdio);
26bc783f
MB		 5723}
5724
e4d6b795
MB		 5725static int __init b43_init(void)
5726{
5727 int err;
5728
5729 b43_debugfs_init();
5730 err = b43_pcmcia_init();
5731 if (err)
5732 goto err_dfs_exit;
3dbba8e2 5733 err = b43_sdio_init();
e4d6b795
MB		 5734 if (err)
5735 goto err_pcmcia_exit;
3c65ab62
RM		 5736#ifdef CONFIG_B43_BCMA
5737 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5738 if (err)
5739 goto err_sdio_exit;
3c65ab62 5740#endif
aec7ffdf 5741#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5742 err = ssb_driver_register(&b43_ssb_driver);
5743 if (err)
5744 goto err_bcma_driver_exit;
aec7ffdf 5745#endif
26bc783f 5746 b43_print_driverinfo();
e4d6b795
MB		 5747
5748 return err;
5749
aec7ffdf 5750#ifdef CONFIG_B43_SSB
3c65ab62 5751err_bcma_driver_exit:
aec7ffdf 5752#endif
3c65ab62
RM		 5753#ifdef CONFIG_B43_BCMA
5754 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5755err_sdio_exit:
3c65ab62 5756#endif
3dbba8e2 5757 b43_sdio_exit();
e4d6b795
MB		 5758err_pcmcia_exit:
5759 b43_pcmcia_exit();
5760err_dfs_exit:
5761 b43_debugfs_exit();
5762 return err;
5763}
5764
5765static void __exit b43_exit(void)
5766{
aec7ffdf 5767#ifdef CONFIG_B43_SSB
e4d6b795 5768 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5769#endif
3c65ab62
RM		 5770#ifdef CONFIG_B43_BCMA
5771 bcma_driver_unregister(&b43_bcma_driver);
5772#endif
3dbba8e2 5773 b43_sdio_exit();
e4d6b795
MB		 5774 b43_pcmcia_exit();
5775 b43_debugfs_exit();
5776}
5777
5778module_init(b43_init)
5779module_exit(b43_exit)
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