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b43: Fixup set_key handling
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
9c7d99d6
MB		 63MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
e4d6b795
MB		 65
66static int modparam_bad_frames_preempt;
67module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
e4d6b795
MB		 71static char modparam_fwpostfix[16];
72module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
e4d6b795
MB		 75static int modparam_hwpctl;
76module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79static int modparam_nohwcrypt;
80module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
e6f5b934
MB		 83int b43_modparam_qos = 1;
84module_param_named(qos, b43_modparam_qos, int, 0444);
85MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
1855ba78
MB		 87static int modparam_btcoex = 1;
88module_param_named(btcoex, modparam_btcoex, int, 0444);
89MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
e6f5b934 91
e4d6b795
MB		 92static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
e4d6b795
MB		 100 SSB_DEVTABLE_END
101};
102
103MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
104
105/* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 110 { \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
113 .flags = (_flags), \
e4d6b795 114 }
8318d78a
JB		 115
116/*
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
119 */
e4d6b795 120static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 133};
134
135#define b43_a_ratetable (__b43_ratetable + 4)
136#define b43_a_ratetable_size 8
137#define b43_b_ratetable (__b43_ratetable + 0)
138#define b43_b_ratetable_size 4
139#define b43_g_ratetable (__b43_ratetable + 0)
140#define b43_g_ratetable_size 12
141
bb1eeff1
MB		 142#define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
146 .flags = (_flags), \
147 .max_antenna_gain = 0, \
148 .max_power = 30, \
149}
96c755a3 150static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 151 CHAN4G(1, 2412, 0),
152 CHAN4G(2, 2417, 0),
153 CHAN4G(3, 2422, 0),
154 CHAN4G(4, 2427, 0),
155 CHAN4G(5, 2432, 0),
156 CHAN4G(6, 2437, 0),
157 CHAN4G(7, 2442, 0),
158 CHAN4G(8, 2447, 0),
159 CHAN4G(9, 2452, 0),
160 CHAN4G(10, 2457, 0),
161 CHAN4G(11, 2462, 0),
162 CHAN4G(12, 2467, 0),
163 CHAN4G(13, 2472, 0),
164 CHAN4G(14, 2484, 0),
165};
166#undef CHAN4G
167
168#define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
172 .flags = (_flags), \
173 .max_antenna_gain = 0, \
174 .max_power = 30, \
175}
176static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 232};
233
bb1eeff1
MB		 234static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
253 CHAN5G(216, 0),
254};
255#undef CHAN5G
256
257static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
e4d6b795 263};
8318d78a 264
bb1eeff1
MB		 265static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
8318d78a 271};
e4d6b795 272
8318d78a 273static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 279};
280
e4d6b795
MB		 281static void b43_wireless_core_exit(struct b43_wldev *dev);
282static int b43_wireless_core_init(struct b43_wldev *dev);
283static void b43_wireless_core_stop(struct b43_wldev *dev);
284static int b43_wireless_core_start(struct b43_wldev *dev);
285
286static int b43_ratelimit(struct b43_wl *wl)
287{
288 if (!wl || !wl->current_dev)
289 return 1;
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
291 return 1;
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
295}
296
297void b43info(struct b43_wl *wl, const char *fmt, ...)
298{
299 va_list args;
300
301 if (!b43_ratelimit(wl))
302 return;
303 va_start(args, fmt);
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
306 vprintk(fmt, args);
307 va_end(args);
308}
309
310void b43err(struct b43_wl *wl, const char *fmt, ...)
311{
312 va_list args;
313
314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321}
322
323void b43warn(struct b43_wl *wl, const char *fmt, ...)
324{
325 va_list args;
326
327 if (!b43_ratelimit(wl))
328 return;
329 va_start(args, fmt);
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
332 vprintk(fmt, args);
333 va_end(args);
334}
335
336#if B43_DEBUG
337void b43dbg(struct b43_wl *wl, const char *fmt, ...)
338{
339 va_list args;
340
341 va_start(args, fmt);
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346}
347#endif /* DEBUG */
348
349static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
350{
351 u32 macctl;
352
353 B43_WARN_ON(offset % 4 != 0);
354
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
357 val = swab32(val);
358
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
360 mmiowb();
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
362}
363
280d0e16
MB		 364static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
e4d6b795
MB		 366{
367 u32 control;
368
369 /* "offset" is the WORD offset. */
e4d6b795
MB		 370 control = routing;
371 control <<= 16;
372 control |= offset;
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
374}
375
6bbc321a 376u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 377{
378 u32 ret;
379
380 if (routing == B43_SHM_SHARED) {
381 B43_WARN_ON(offset & 0x0001);
382 if (offset & 0x0003) {
383 /* Unaligned access */
384 b43_shm_control_word(dev, routing, offset >> 2);
385 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
386 ret <<= 16;
387 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
388 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
389
280d0e16 390 goto out;
e4d6b795
MB		 391 }
392 offset >>= 2;
393 }
394 b43_shm_control_word(dev, routing, offset);
395 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 396out:
e4d6b795
MB		 397 return ret;
398}
399
6bbc321a 400u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 401{
280d0e16
MB		 402 struct b43_wl *wl = dev->wl;
403 unsigned long flags;
6bbc321a 404 u32 ret;
e4d6b795 405
280d0e16 406 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 407 ret = __b43_shm_read32(dev, routing, offset);
408 spin_unlock_irqrestore(&wl->shm_lock, flags);
409
410 return ret;
411}
412
413u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
414{
415 u16 ret;
416
e4d6b795
MB		 417 if (routing == B43_SHM_SHARED) {
418 B43_WARN_ON(offset & 0x0001);
419 if (offset & 0x0003) {
420 /* Unaligned access */
421 b43_shm_control_word(dev, routing, offset >> 2);
422 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
423
280d0e16 424 goto out;
e4d6b795
MB		 425 }
426 offset >>= 2;
427 }
428 b43_shm_control_word(dev, routing, offset);
429 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 430out:
e4d6b795
MB		 431 return ret;
432}
433
6bbc321a 434u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 435{
280d0e16
MB		 436 struct b43_wl *wl = dev->wl;
437 unsigned long flags;
6bbc321a 438 u16 ret;
280d0e16
MB		 439
440 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 441 ret = __b43_shm_read16(dev, routing, offset);
442 spin_unlock_irqrestore(&wl->shm_lock, flags);
443
444 return ret;
445}
446
447void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
448{
e4d6b795
MB		 449 if (routing == B43_SHM_SHARED) {
450 B43_WARN_ON(offset & 0x0001);
451 if (offset & 0x0003) {
452 /* Unaligned access */
453 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 454 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
455 (value >> 16) & 0xffff);
e4d6b795 456 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 457 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
6bbc321a 458 return;
e4d6b795
MB		 459 }
460 offset >>= 2;
461 }
462 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 463 b43_write32(dev, B43_MMIO_SHM_DATA, value);
464}
465
6bbc321a 466void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
e4d6b795 467{
280d0e16
MB		 468 struct b43_wl *wl = dev->wl;
469 unsigned long flags;
470
471 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 472 __b43_shm_write32(dev, routing, offset, value);
473 spin_unlock_irqrestore(&wl->shm_lock, flags);
474}
475
476void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
477{
e4d6b795
MB		 478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 484 return;
e4d6b795
MB		 485 }
486 offset >>= 2;
487 }
488 b43_shm_control_word(dev, routing, offset);
e4d6b795 489 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 490}
491
492void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
493{
494 struct b43_wl *wl = dev->wl;
495 unsigned long flags;
496
497 spin_lock_irqsave(&wl->shm_lock, flags);
498 __b43_shm_write16(dev, routing, offset, value);
280d0e16 499 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 500}
501
502/* Read HostFlags */
35f0d354 503u64 b43_hf_read(struct b43_wldev * dev)
e4d6b795 504{
35f0d354 505 u64 ret;
e4d6b795
MB		 506
507 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
508 ret <<= 16;
35f0d354
MB		 509 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
510 ret <<= 16;
e4d6b795
MB		 511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
512
513 return ret;
514}
515
516/* Write HostFlags */
35f0d354 517void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 518{
35f0d354
MB		 519 u16 lo, mi, hi;
520
521 lo = (value & 0x00000000FFFFULL);
522 mi = (value & 0x0000FFFF0000ULL) >> 16;
523 hi = (value & 0xFFFF00000000ULL) >> 32;
524 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 527}
528
529void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
530{
531 /* We need to be careful. As we read the TSF from multiple
532 * registers, we should take care of register overflows.
533 * In theory, the whole tsf read process should be atomic.
534 * We try to be atomic here, by restaring the read process,
535 * if any of the high registers changed (overflew).
536 */
537 if (dev->dev->id.revision >= 3) {
538 u32 low, high, high2;
539
540 do {
541 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
542 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
543 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
544 } while (unlikely(high != high2));
545
546 *tsf = high;
547 *tsf <<= 32;
548 *tsf |= low;
549 } else {
550 u64 tmp;
551 u16 v0, v1, v2, v3;
552 u16 test1, test2, test3;
553
554 do {
555 v3 = b43_read16(dev, B43_MMIO_TSF_3);
556 v2 = b43_read16(dev, B43_MMIO_TSF_2);
557 v1 = b43_read16(dev, B43_MMIO_TSF_1);
558 v0 = b43_read16(dev, B43_MMIO_TSF_0);
559
560 test3 = b43_read16(dev, B43_MMIO_TSF_3);
561 test2 = b43_read16(dev, B43_MMIO_TSF_2);
562 test1 = b43_read16(dev, B43_MMIO_TSF_1);
563 } while (v3 != test3 || v2 != test2 || v1 != test1);
564
565 *tsf = v3;
566 *tsf <<= 48;
567 tmp = v2;
568 tmp <<= 32;
569 *tsf |= tmp;
570 tmp = v1;
571 tmp <<= 16;
572 *tsf |= tmp;
573 *tsf |= v0;
574 }
575}
576
577static void b43_time_lock(struct b43_wldev *dev)
578{
579 u32 macctl;
580
581 macctl = b43_read32(dev, B43_MMIO_MACCTL);
582 macctl |= B43_MACCTL_TBTTHOLD;
583 b43_write32(dev, B43_MMIO_MACCTL, macctl);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
586}
587
588static void b43_time_unlock(struct b43_wldev *dev)
589{
590 u32 macctl;
591
592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
593 macctl &= ~B43_MACCTL_TBTTHOLD;
594 b43_write32(dev, B43_MMIO_MACCTL, macctl);
595 /* Commit the write */
596 b43_read32(dev, B43_MMIO_MACCTL);
597}
598
599static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
600{
601 /* Be careful with the in-progress timer.
602 * First zero out the low register, so we have a full
603 * register-overflow duration to complete the operation.
604 */
605 if (dev->dev->id.revision >= 3) {
606 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
607 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
608
609 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
610 mmiowb();
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
612 mmiowb();
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
614 } else {
615 u16 v0 = (tsf & 0x000000000000FFFFULL);
616 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
617 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
618 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
619
620 b43_write16(dev, B43_MMIO_TSF_0, 0);
621 mmiowb();
622 b43_write16(dev, B43_MMIO_TSF_3, v3);
623 mmiowb();
624 b43_write16(dev, B43_MMIO_TSF_2, v2);
625 mmiowb();
626 b43_write16(dev, B43_MMIO_TSF_1, v1);
627 mmiowb();
628 b43_write16(dev, B43_MMIO_TSF_0, v0);
629 }
630}
631
632void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
633{
634 b43_time_lock(dev);
635 b43_tsf_write_locked(dev, tsf);
636 b43_time_unlock(dev);
637}
638
639static
640void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
641{
642 static const u8 zero_addr[ETH_ALEN] = { 0 };
643 u16 data;
644
645 if (!mac)
646 mac = zero_addr;
647
648 offset |= 0x0020;
649 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
650
651 data = mac[0];
652 data |= mac[1] << 8;
653 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
654 data = mac[2];
655 data |= mac[3] << 8;
656 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
657 data = mac[4];
658 data |= mac[5] << 8;
659 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
660}
661
662static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
663{
664 const u8 *mac;
665 const u8 *bssid;
666 u8 mac_bssid[ETH_ALEN * 2];
667 int i;
668 u32 tmp;
669
670 bssid = dev->wl->bssid;
671 mac = dev->wl->mac_addr;
672
673 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
674
675 memcpy(mac_bssid, mac, ETH_ALEN);
676 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
677
678 /* Write our MAC address and BSSID to template ram */
679 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
680 tmp = (u32) (mac_bssid[i + 0]);
681 tmp |= (u32) (mac_bssid[i + 1]) << 8;
682 tmp |= (u32) (mac_bssid[i + 2]) << 16;
683 tmp |= (u32) (mac_bssid[i + 3]) << 24;
684 b43_ram_write(dev, 0x20 + i, tmp);
685 }
686}
687
4150c572 688static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 689{
e4d6b795 690 b43_write_mac_bssid_templates(dev);
4150c572 691 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 692}
693
694static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
695{
696 /* slot_time is in usec. */
697 if (dev->phy.type != B43_PHYTYPE_G)
698 return;
699 b43_write16(dev, 0x684, 510 + slot_time);
700 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
701}
702
703static void b43_short_slot_timing_enable(struct b43_wldev *dev)
704{
705 b43_set_slot_time(dev, 9);
e4d6b795
MB		 706}
707
708static void b43_short_slot_timing_disable(struct b43_wldev *dev)
709{
710 b43_set_slot_time(dev, 20);
e4d6b795
MB		 711}
712
713/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
714 * Returns the _previously_ enabled IRQ mask.
715 */
716static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
717{
718 u32 old_mask;
719
720 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
721 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
722
723 return old_mask;
724}
725
726/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
727 * Returns the _previously_ enabled IRQ mask.
728 */
729static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
730{
731 u32 old_mask;
732
733 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
734 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
735
736 return old_mask;
737}
738
739/* Synchronize IRQ top- and bottom-half.
740 * IRQs must be masked before calling this.
741 * This must not be called with the irq_lock held.
742 */
743static void b43_synchronize_irq(struct b43_wldev *dev)
744{
745 synchronize_irq(dev->dev->irq);
746 tasklet_kill(&dev->isr_tasklet);
747}
748
749/* DummyTransmission function, as documented on
750 * http://bcm-specs.sipsolutions.net/DummyTransmission
751 */
752void b43_dummy_transmission(struct b43_wldev *dev)
753{
21a75d77 754 struct b43_wl *wl = dev->wl;
e4d6b795
MB		 755 struct b43_phy *phy = &dev->phy;
756 unsigned int i, max_loop;
757 u16 value;
758 u32 buffer[5] = {
759 0x00000000,
760 0x00D40000,
761 0x00000000,
762 0x01000000,
763 0x00000000,
764 };
765
766 switch (phy->type) {
767 case B43_PHYTYPE_A:
768 max_loop = 0x1E;
769 buffer[0] = 0x000201CC;
770 break;
771 case B43_PHYTYPE_B:
772 case B43_PHYTYPE_G:
773 max_loop = 0xFA;
774 buffer[0] = 0x000B846E;
775 break;
776 default:
777 B43_WARN_ON(1);
778 return;
779 }
780
21a75d77
MB		 781 spin_lock_irq(&wl->irq_lock);
782 write_lock(&wl->tx_lock);
783
e4d6b795
MB		 784 for (i = 0; i < 5; i++)
785 b43_ram_write(dev, i * 4, buffer[i]);
786
787 /* Commit writes */
788 b43_read32(dev, B43_MMIO_MACCTL);
789
790 b43_write16(dev, 0x0568, 0x0000);
791 b43_write16(dev, 0x07C0, 0x0000);
792 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
793 b43_write16(dev, 0x050C, value);
794 b43_write16(dev, 0x0508, 0x0000);
795 b43_write16(dev, 0x050A, 0x0000);
796 b43_write16(dev, 0x054C, 0x0000);
797 b43_write16(dev, 0x056A, 0x0014);
798 b43_write16(dev, 0x0568, 0x0826);
799 b43_write16(dev, 0x0500, 0x0000);
800 b43_write16(dev, 0x0502, 0x0030);
801
802 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
803 b43_radio_write16(dev, 0x0051, 0x0017);
804 for (i = 0x00; i < max_loop; i++) {
805 value = b43_read16(dev, 0x050E);
806 if (value & 0x0080)
807 break;
808 udelay(10);
809 }
810 for (i = 0x00; i < 0x0A; i++) {
811 value = b43_read16(dev, 0x050E);
812 if (value & 0x0400)
813 break;
814 udelay(10);
815 }
1d280ddc 816 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 817 value = b43_read16(dev, 0x0690);
818 if (!(value & 0x0100))
819 break;
820 udelay(10);
821 }
822 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
823 b43_radio_write16(dev, 0x0051, 0x0037);
21a75d77
MB		 824
825 write_unlock(&wl->tx_lock);
826 spin_unlock_irq(&wl->irq_lock);
e4d6b795
MB		 827}
828
829static void key_write(struct b43_wldev *dev,
830 u8 index, u8 algorithm, const u8 * key)
831{
832 unsigned int i;
833 u32 offset;
834 u16 value;
835 u16 kidx;
836
837 /* Key index/algo block */
838 kidx = b43_kidx_to_fw(dev, index);
839 value = ((kidx << 4) | algorithm);
840 b43_shm_write16(dev, B43_SHM_SHARED,
841 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
842
843 /* Write the key to the Key Table Pointer offset */
844 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
845 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
846 value = key[i];
847 value |= (u16) (key[i + 1]) << 8;
848 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
849 }
850}
851
852static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
853{
854 u32 addrtmp[2] = { 0, 0, };
855 u8 per_sta_keys_start = 8;
856
857 if (b43_new_kidx_api(dev))
858 per_sta_keys_start = 4;
859
860 B43_WARN_ON(index < per_sta_keys_start);
861 /* We have two default TX keys and possibly two default RX keys.
862 * Physical mac 0 is mapped to physical key 4 or 8, depending
863 * on the firmware version.
864 * So we must adjust the index here.
865 */
866 index -= per_sta_keys_start;
867
868 if (addr) {
869 addrtmp[0] = addr[0];
870 addrtmp[0] |= ((u32) (addr[1]) << 8);
871 addrtmp[0] |= ((u32) (addr[2]) << 16);
872 addrtmp[0] |= ((u32) (addr[3]) << 24);
873 addrtmp[1] = addr[4];
874 addrtmp[1] |= ((u32) (addr[5]) << 8);
875 }
876
877 if (dev->dev->id.revision >= 5) {
878 /* Receive match transmitter address mechanism */
879 b43_shm_write32(dev, B43_SHM_RCMTA,
880 (index * 2) + 0, addrtmp[0]);
881 b43_shm_write16(dev, B43_SHM_RCMTA,
882 (index * 2) + 1, addrtmp[1]);
883 } else {
884 /* RXE (Receive Engine) and
885 * PSM (Programmable State Machine) mechanism
886 */
887 if (index < 8) {
888 /* TODO write to RCM 16, 19, 22 and 25 */
889 } else {
890 b43_shm_write32(dev, B43_SHM_SHARED,
891 B43_SHM_SH_PSM + (index * 6) + 0,
892 addrtmp[0]);
893 b43_shm_write16(dev, B43_SHM_SHARED,
894 B43_SHM_SH_PSM + (index * 6) + 4,
895 addrtmp[1]);
896 }
897 }
898}
899
900static void do_key_write(struct b43_wldev *dev,
901 u8 index, u8 algorithm,
902 const u8 * key, size_t key_len, const u8 * mac_addr)
903{
904 u8 buf[B43_SEC_KEYSIZE] = { 0, };
905 u8 per_sta_keys_start = 8;
906
907 if (b43_new_kidx_api(dev))
908 per_sta_keys_start = 4;
909
910 B43_WARN_ON(index >= dev->max_nr_keys);
911 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
912
913 if (index >= per_sta_keys_start)
914 keymac_write(dev, index, NULL); /* First zero out mac. */
915 if (key)
916 memcpy(buf, key, key_len);
917 key_write(dev, index, algorithm, buf);
918 if (index >= per_sta_keys_start)
919 keymac_write(dev, index, mac_addr);
920
921 dev->key[index].algorithm = algorithm;
922}
923
924static int b43_key_write(struct b43_wldev *dev,
925 int index, u8 algorithm,
926 const u8 * key, size_t key_len,
927 const u8 * mac_addr,
928 struct ieee80211_key_conf *keyconf)
929{
930 int i;
931 int sta_keys_start;
932
933 if (key_len > B43_SEC_KEYSIZE)
934 return -EINVAL;
935 for (i = 0; i < dev->max_nr_keys; i++) {
936 /* Check that we don't already have this key. */
937 B43_WARN_ON(dev->key[i].keyconf == keyconf);
938 }
939 if (index < 0) {
e808e586 940 /* Pairwise key. Get an empty slot for the key. */
e4d6b795
MB		 941 if (b43_new_kidx_api(dev))
942 sta_keys_start = 4;
943 else
944 sta_keys_start = 8;
945 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
946 if (!dev->key[i].keyconf) {
947 /* found empty */
948 index = i;
949 break;
950 }
951 }
952 if (index < 0) {
e808e586 953 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 954 return -ENOSPC;
955 }
956 } else
957 B43_WARN_ON(index > 3);
958
959 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
960 if ((index <= 3) && !b43_new_kidx_api(dev)) {
961 /* Default RX key */
962 B43_WARN_ON(mac_addr);
963 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
964 }
965 keyconf->hw_key_idx = index;
966 dev->key[index].keyconf = keyconf;
967
968 return 0;
969}
970
971static int b43_key_clear(struct b43_wldev *dev, int index)
972{
973 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
974 return -EINVAL;
975 do_key_write(dev, index, B43_SEC_ALGO_NONE,
976 NULL, B43_SEC_KEYSIZE, NULL);
977 if ((index <= 3) && !b43_new_kidx_api(dev)) {
978 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
979 NULL, B43_SEC_KEYSIZE, NULL);
980 }
981 dev->key[index].keyconf = NULL;
982
983 return 0;
984}
985
986static void b43_clear_keys(struct b43_wldev *dev)
987{
988 int i;
989
990 for (i = 0; i < dev->max_nr_keys; i++)
991 b43_key_clear(dev, i);
992}
993
9cf7f247
MB		 994static void b43_dump_keymemory(struct b43_wldev *dev)
995{
996 unsigned int i, index, offset;
997 DECLARE_MAC_BUF(macbuf);
998 u8 mac[ETH_ALEN];
999 u16 algo;
1000 u32 rcmta0;
1001 u16 rcmta1;
1002 u64 hf;
1003 struct b43_key *key;
1004
1005 if (!b43_debug(dev, B43_DBG_KEYS))
1006 return;
1007
1008 hf = b43_hf_read(dev);
1009 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1010 !!(hf & B43_HF_USEDEFKEYS));
1011 for (index = 0; index < dev->max_nr_keys; index++) {
1012 key = &(dev->key[index]);
1013 printk(KERN_DEBUG "Key slot %02u: %s",
1014 index, (key->keyconf == NULL) ? " " : "*");
1015 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1016 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1017 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1018 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1019 }
1020
1021 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1022 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1023 printk(" Algo: %04X/%02X", algo, key->algorithm);
1024
1025 if (index >= 4) {
1026 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1027 ((index - 4) * 2) + 0);
1028 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1029 ((index - 4) * 2) + 1);
1030 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1031 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1032 printk(" MAC: %s",
1033 print_mac(macbuf, mac));
1034 } else
1035 printk(" DEFAULT KEY");
1036 printk("\n");
1037 }
1038}
1039
e4d6b795
MB		 1040void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1041{
1042 u32 macctl;
1043 u16 ucstat;
1044 bool hwps;
1045 bool awake;
1046 int i;
1047
1048 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1049 (ps_flags & B43_PS_DISABLED));
1050 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1051
1052 if (ps_flags & B43_PS_ENABLED) {
1053 hwps = 1;
1054 } else if (ps_flags & B43_PS_DISABLED) {
1055 hwps = 0;
1056 } else {
1057 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1058 // and thus is not an AP and we are associated, set bit 25
1059 }
1060 if (ps_flags & B43_PS_AWAKE) {
1061 awake = 1;
1062 } else if (ps_flags & B43_PS_ASLEEP) {
1063 awake = 0;
1064 } else {
1065 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1066 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1067 // successful, set bit26
1068 }
1069
1070/* FIXME: For now we force awake-on and hwps-off */
1071 hwps = 0;
1072 awake = 1;
1073
1074 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1075 if (hwps)
1076 macctl |= B43_MACCTL_HWPS;
1077 else
1078 macctl &= ~B43_MACCTL_HWPS;
1079 if (awake)
1080 macctl |= B43_MACCTL_AWAKE;
1081 else
1082 macctl &= ~B43_MACCTL_AWAKE;
1083 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1084 /* Commit write */
1085 b43_read32(dev, B43_MMIO_MACCTL);
1086 if (awake && dev->dev->id.revision >= 5) {
1087 /* Wait for the microcode to wake up. */
1088 for (i = 0; i < 100; i++) {
1089 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1090 B43_SHM_SH_UCODESTAT);
1091 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1092 break;
1093 udelay(10);
1094 }
1095 }
1096}
1097
e4d6b795
MB		 1098void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1099{
1100 u32 tmslow;
1101 u32 macctl;
1102
1103 flags |= B43_TMSLOW_PHYCLKEN;
1104 flags |= B43_TMSLOW_PHYRESET;
1105 ssb_device_enable(dev->dev, flags);
1106 msleep(2); /* Wait for the PLL to turn on. */
1107
1108 /* Now take the PHY out of Reset again */
1109 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1110 tmslow |= SSB_TMSLOW_FGC;
1111 tmslow &= ~B43_TMSLOW_PHYRESET;
1112 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1113 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1114 msleep(1);
1115 tmslow &= ~SSB_TMSLOW_FGC;
1116 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1117 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1118 msleep(1);
1119
fb11137a
MB		 1120 /* Turn Analog ON, but only if we already know the PHY-type.
1121 * This protects against very early setup where we don't know the
1122 * PHY-type, yet. wireless_core_reset will be called once again later,
1123 * when we know the PHY-type. */
1124 if (dev->phy.ops)
cb24f57f 1125 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1126
1127 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1128 macctl &= ~B43_MACCTL_GMODE;
1129 if (flags & B43_TMSLOW_GMODE)
1130 macctl |= B43_MACCTL_GMODE;
1131 macctl |= B43_MACCTL_IHR_ENABLED;
1132 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1133}
1134
1135static void handle_irq_transmit_status(struct b43_wldev *dev)
1136{
1137 u32 v0, v1;
1138 u16 tmp;
1139 struct b43_txstatus stat;
1140
1141 while (1) {
1142 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1143 if (!(v0 & 0x00000001))
1144 break;
1145 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1146
1147 stat.cookie = (v0 >> 16);
1148 stat.seq = (v1 & 0x0000FFFF);
1149 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1150 tmp = (v0 & 0x0000FFFF);
1151 stat.frame_count = ((tmp & 0xF000) >> 12);
1152 stat.rts_count = ((tmp & 0x0F00) >> 8);
1153 stat.supp_reason = ((tmp & 0x001C) >> 2);
1154 stat.pm_indicated = !!(tmp & 0x0080);
1155 stat.intermediate = !!(tmp & 0x0040);
1156 stat.for_ampdu = !!(tmp & 0x0020);
1157 stat.acked = !!(tmp & 0x0002);
1158
1159 b43_handle_txstatus(dev, &stat);
1160 }
1161}
1162
1163static void drain_txstatus_queue(struct b43_wldev *dev)
1164{
1165 u32 dummy;
1166
1167 if (dev->dev->id.revision < 5)
1168 return;
1169 /* Read all entries from the microcode TXstatus FIFO
1170 * and throw them away.
1171 */
1172 while (1) {
1173 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1174 if (!(dummy & 0x00000001))
1175 break;
1176 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1177 }
1178}
1179
1180static u32 b43_jssi_read(struct b43_wldev *dev)
1181{
1182 u32 val = 0;
1183
1184 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1185 val <<= 16;
1186 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1187
1188 return val;
1189}
1190
1191static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1192{
1193 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1194 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1195}
1196
1197static void b43_generate_noise_sample(struct b43_wldev *dev)
1198{
1199 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1200 b43_write32(dev, B43_MMIO_MACCMD,
1201 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1202}
1203
1204static void b43_calculate_link_quality(struct b43_wldev *dev)
1205{
1206 /* Top half of Link Quality calculation. */
1207
ef1a628d
MB		 1208 if (dev->phy.type != B43_PHYTYPE_G)
1209 return;
e4d6b795
MB		 1210 if (dev->noisecalc.calculation_running)
1211 return;
e4d6b795
MB		 1212 dev->noisecalc.calculation_running = 1;
1213 dev->noisecalc.nr_samples = 0;
1214
1215 b43_generate_noise_sample(dev);
1216}
1217
1218static void handle_irq_noise(struct b43_wldev *dev)
1219{
ef1a628d 1220 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1221 u16 tmp;
1222 u8 noise[4];
1223 u8 i, j;
1224 s32 average;
1225
1226 /* Bottom half of Link Quality calculation. */
1227
ef1a628d
MB		 1228 if (dev->phy.type != B43_PHYTYPE_G)
1229 return;
1230
98a3b2fe
MB		 1231 /* Possible race condition: It might be possible that the user
1232 * changed to a different channel in the meantime since we
1233 * started the calculation. We ignore that fact, since it's
1234 * not really that much of a problem. The background noise is
1235 * an estimation only anyway. Slightly wrong results will get damped
1236 * by the averaging of the 8 sample rounds. Additionally the
1237 * value is shortlived. So it will be replaced by the next noise
1238 * calculation round soon. */
1239
e4d6b795 1240 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1241 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1242 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1243 noise[2] == 0x7F || noise[3] == 0x7F)
1244 goto generate_new;
1245
1246 /* Get the noise samples. */
1247 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1248 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1249 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1250 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1251 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1252 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1253 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1254 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1255 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1256 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1257 dev->noisecalc.nr_samples++;
1258 if (dev->noisecalc.nr_samples == 8) {
1259 /* Calculate the Link Quality by the noise samples. */
1260 average = 0;
1261 for (i = 0; i < 8; i++) {
1262 for (j = 0; j < 4; j++)
1263 average += dev->noisecalc.samples[i][j];
1264 }
1265 average /= (8 * 4);
1266 average *= 125;
1267 average += 64;
1268 average /= 128;
1269 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1270 tmp = (tmp / 128) & 0x1F;
1271 if (tmp >= 8)
1272 average += 2;
1273 else
1274 average -= 25;
1275 if (tmp == 8)
1276 average -= 72;
1277 else
1278 average -= 48;
1279
1280 dev->stats.link_noise = average;
e4d6b795
MB		 1281 dev->noisecalc.calculation_running = 0;
1282 return;
1283 }
98a3b2fe 1284generate_new:
e4d6b795
MB		 1285 b43_generate_noise_sample(dev);
1286}
1287
1288static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1289{
05c914fe 1290 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1291 ///TODO: PS TBTT
1292 } else {
1293 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1294 b43_power_saving_ctl_bits(dev, 0);
1295 }
05c914fe 1296 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1297 dev->dfq_valid = 1;
e4d6b795
MB		 1298}
1299
1300static void handle_irq_atim_end(struct b43_wldev *dev)
1301{
aa6c7ae2
MB		 1302 if (dev->dfq_valid) {
1303 b43_write32(dev, B43_MMIO_MACCMD,
1304 b43_read32(dev, B43_MMIO_MACCMD)
1305 | B43_MACCMD_DFQ_VALID);
1306 dev->dfq_valid = 0;
1307 }
e4d6b795
MB		 1308}
1309
1310static void handle_irq_pmq(struct b43_wldev *dev)
1311{
1312 u32 tmp;
1313
1314 //TODO: AP mode.
1315
1316 while (1) {
1317 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1318 if (!(tmp & 0x00000008))
1319 break;
1320 }
1321 /* 16bit write is odd, but correct. */
1322 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1323}
1324
1325static void b43_write_template_common(struct b43_wldev *dev,
1326 const u8 * data, u16 size,
1327 u16 ram_offset,
1328 u16 shm_size_offset, u8 rate)
1329{
1330 u32 i, tmp;
1331 struct b43_plcp_hdr4 plcp;
1332
1333 plcp.data = 0;
1334 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1335 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1336 ram_offset += sizeof(u32);
1337 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1338 * So leave the first two bytes of the next write blank.
1339 */
1340 tmp = (u32) (data[0]) << 16;
1341 tmp |= (u32) (data[1]) << 24;
1342 b43_ram_write(dev, ram_offset, tmp);
1343 ram_offset += sizeof(u32);
1344 for (i = 2; i < size; i += sizeof(u32)) {
1345 tmp = (u32) (data[i + 0]);
1346 if (i + 1 < size)
1347 tmp |= (u32) (data[i + 1]) << 8;
1348 if (i + 2 < size)
1349 tmp |= (u32) (data[i + 2]) << 16;
1350 if (i + 3 < size)
1351 tmp |= (u32) (data[i + 3]) << 24;
1352 b43_ram_write(dev, ram_offset + i - 2, tmp);
1353 }
1354 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1355 size + sizeof(struct b43_plcp_hdr6));
1356}
1357
5042c507
MB		 1358/* Check if the use of the antenna that ieee80211 told us to
1359 * use is possible. This will fall back to DEFAULT.
1360 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1361u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1362 u8 antenna_nr)
1363{
1364 u8 antenna_mask;
1365
1366 if (antenna_nr == 0) {
1367 /* Zero means "use default antenna". That's always OK. */
1368 return 0;
1369 }
1370
1371 /* Get the mask of available antennas. */
1372 if (dev->phy.gmode)
1373 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1374 else
1375 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1376
1377 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1378 /* This antenna is not available. Fall back to default. */
1379 return 0;
1380 }
1381
1382 return antenna_nr;
1383}
1384
5042c507
MB		 1385/* Convert a b43 antenna number value to the PHY TX control value. */
1386static u16 b43_antenna_to_phyctl(int antenna)
1387{
1388 switch (antenna) {
1389 case B43_ANTENNA0:
1390 return B43_TXH_PHY_ANT0;
1391 case B43_ANTENNA1:
1392 return B43_TXH_PHY_ANT1;
1393 case B43_ANTENNA2:
1394 return B43_TXH_PHY_ANT2;
1395 case B43_ANTENNA3:
1396 return B43_TXH_PHY_ANT3;
1397 case B43_ANTENNA_AUTO:
1398 return B43_TXH_PHY_ANT01AUTO;
1399 }
1400 B43_WARN_ON(1);
1401 return 0;
1402}
1403
e4d6b795
MB		 1404static void b43_write_beacon_template(struct b43_wldev *dev,
1405 u16 ram_offset,
5042c507 1406 u16 shm_size_offset)
e4d6b795 1407{
47f76ca3 1408 unsigned int i, len, variable_len;
e66fee6a
MB		 1409 const struct ieee80211_mgmt *bcn;
1410 const u8 *ie;
1411 bool tim_found = 0;
5042c507
MB		 1412 unsigned int rate;
1413 u16 ctl;
1414 int antenna;
e039fa4a 1415 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1416
e66fee6a
MB		 1417 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1418 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1419 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1420 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1421
1422 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1423 len, ram_offset, shm_size_offset, rate);
e66fee6a 1424
5042c507 1425 /* Write the PHY TX control parameters. */
0f4ac38b 1426 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1427 antenna = b43_antenna_to_phyctl(antenna);
1428 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1429 /* We can't send beacons with short preamble. Would get PHY errors. */
1430 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1431 ctl &= ~B43_TXH_PHY_ANT;
1432 ctl &= ~B43_TXH_PHY_ENC;
1433 ctl |= antenna;
1434 if (b43_is_cck_rate(rate))
1435 ctl |= B43_TXH_PHY_ENC_CCK;
1436 else
1437 ctl |= B43_TXH_PHY_ENC_OFDM;
1438 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1439
e66fee6a
MB		 1440 /* Find the position of the TIM and the DTIM_period value
1441 * and write them to SHM. */
1442 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1443 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1444 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1445 uint8_t ie_id, ie_len;
1446
1447 ie_id = ie[i];
1448 ie_len = ie[i + 1];
1449 if (ie_id == 5) {
1450 u16 tim_position;
1451 u16 dtim_period;
1452 /* This is the TIM Information Element */
1453
1454 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1455 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1456 break;
1457 /* A valid TIM is at least 4 bytes long. */
1458 if (ie_len < 4)
1459 break;
1460 tim_found = 1;
1461
1462 tim_position = sizeof(struct b43_plcp_hdr6);
1463 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1464 tim_position += i;
1465
1466 dtim_period = ie[i + 3];
1467
1468 b43_shm_write16(dev, B43_SHM_SHARED,
1469 B43_SHM_SH_TIMBPOS, tim_position);
1470 b43_shm_write16(dev, B43_SHM_SHARED,
1471 B43_SHM_SH_DTIMPER, dtim_period);
1472 break;
1473 }
1474 i += ie_len + 2;
1475 }
1476 if (!tim_found) {
04dea136
JB		 1477 /*
1478 * If ucode wants to modify TIM do it behind the beacon, this
1479 * will happen, for example, when doing mesh networking.
1480 */
1481 b43_shm_write16(dev, B43_SHM_SHARED,
1482 B43_SHM_SH_TIMBPOS,
1483 len + sizeof(struct b43_plcp_hdr6));
1484 b43_shm_write16(dev, B43_SHM_SHARED,
1485 B43_SHM_SH_DTIMPER, 0);
1486 }
1487 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1488}
1489
1490static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
8318d78a
JB		 1491 u16 shm_offset, u16 size,
1492 struct ieee80211_rate *rate)
e4d6b795
MB		 1493{
1494 struct b43_plcp_hdr4 plcp;
1495 u32 tmp;
1496 __le16 dur;
1497
1498 plcp.data = 0;
8318d78a 1499 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
e4d6b795 1500 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1501 dev->wl->vif, size,
8318d78a 1502 rate);
e4d6b795
MB		 1503 /* Write PLCP in two parts and timing for packet transfer */
1504 tmp = le32_to_cpu(plcp.data);
1505 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1506 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1507 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1508}
1509
1510/* Instead of using custom probe response template, this function
1511 * just patches custom beacon template by:
1512 * 1) Changing packet type
1513 * 2) Patching duration field
1514 * 3) Stripping TIM
1515 */
e66fee6a 1516static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
8318d78a
JB		 1517 u16 *dest_size,
1518 struct ieee80211_rate *rate)
e4d6b795
MB		 1519{
1520 const u8 *src_data;
1521 u8 *dest_data;
1522 u16 src_size, elem_size, src_pos, dest_pos;
1523 __le16 dur;
1524 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1525 size_t ie_start;
1526
1527 src_size = dev->wl->current_beacon->len;
1528 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1529
e66fee6a
MB		 1530 /* Get the start offset of the variable IEs in the packet. */
1531 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1532 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1533
e66fee6a 1534 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1535 return NULL;
e4d6b795
MB		 1536
1537 dest_data = kmalloc(src_size, GFP_ATOMIC);
1538 if (unlikely(!dest_data))
1539 return NULL;
1540
e66fee6a
MB		 1541 /* Copy the static data and all Information Elements, except the TIM. */
1542 memcpy(dest_data, src_data, ie_start);
1543 src_pos = ie_start;
1544 dest_pos = ie_start;
1545 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1546 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1547 if (src_data[src_pos] == 5) {
1548 /* This is the TIM. */
1549 continue;
e4d6b795 1550 }
e66fee6a
MB		 1551 memcpy(dest_data + dest_pos, src_data + src_pos,
1552 elem_size);
1553 dest_pos += elem_size;
e4d6b795
MB		 1554 }
1555 *dest_size = dest_pos;
1556 hdr = (struct ieee80211_hdr *)dest_data;
1557
1558 /* Set the frame control. */
1559 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1560 IEEE80211_STYPE_PROBE_RESP);
1561 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1562 dev->wl->vif, *dest_size,
8318d78a 1563 rate);
e4d6b795
MB		 1564 hdr->duration_id = dur;
1565
1566 return dest_data;
1567}
1568
1569static void b43_write_probe_resp_template(struct b43_wldev *dev,
1570 u16 ram_offset,
8318d78a
JB		 1571 u16 shm_size_offset,
1572 struct ieee80211_rate *rate)
e4d6b795 1573{
e66fee6a 1574 const u8 *probe_resp_data;
e4d6b795
MB		 1575 u16 size;
1576
e66fee6a 1577 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1578 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1579 if (unlikely(!probe_resp_data))
1580 return;
1581
1582 /* Looks like PLCP headers plus packet timings are stored for
1583 * all possible basic rates
1584 */
8318d78a
JB		 1585 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1586 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1587 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1588 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
e4d6b795
MB		 1589
1590 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1591 b43_write_template_common(dev, probe_resp_data,
8318d78a
JB		 1592 size, ram_offset, shm_size_offset,
1593 rate->hw_value);
e4d6b795
MB		 1594 kfree(probe_resp_data);
1595}
1596
6b4bec01
MB		 1597static void b43_upload_beacon0(struct b43_wldev *dev)
1598{
1599 struct b43_wl *wl = dev->wl;
1600
1601 if (wl->beacon0_uploaded)
1602 return;
1603 b43_write_beacon_template(dev, 0x68, 0x18);
1604 /* FIXME: Probe resp upload doesn't really belong here,
1605 * but we don't use that feature anyway. */
1606 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1607 &__b43_ratetable[3]);
1608 wl->beacon0_uploaded = 1;
1609}
1610
1611static void b43_upload_beacon1(struct b43_wldev *dev)
1612{
1613 struct b43_wl *wl = dev->wl;
1614
1615 if (wl->beacon1_uploaded)
1616 return;
1617 b43_write_beacon_template(dev, 0x468, 0x1A);
1618 wl->beacon1_uploaded = 1;
1619}
1620
c97a4ccc
MB		 1621static void handle_irq_beacon(struct b43_wldev *dev)
1622{
1623 struct b43_wl *wl = dev->wl;
1624 u32 cmd, beacon0_valid, beacon1_valid;
1625
05c914fe
JB		 1626 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1627 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1628 return;
1629
1630 /* This is the bottom half of the asynchronous beacon update. */
1631
1632 /* Ignore interrupt in the future. */
1633 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1634
1635 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1636 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1637 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1638
1639 /* Schedule interrupt manually, if busy. */
1640 if (beacon0_valid && beacon1_valid) {
1641 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1642 dev->irq_savedstate |= B43_IRQ_BEACON;
1643 return;
1644 }
1645
6b4bec01
MB		 1646 if (unlikely(wl->beacon_templates_virgin)) {
1647 /* We never uploaded a beacon before.
1648 * Upload both templates now, but only mark one valid. */
1649 wl->beacon_templates_virgin = 0;
1650 b43_upload_beacon0(dev);
1651 b43_upload_beacon1(dev);
c97a4ccc
MB		 1652 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1653 cmd |= B43_MACCMD_BEACON0_VALID;
1654 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1655 } else {
1656 if (!beacon0_valid) {
1657 b43_upload_beacon0(dev);
1658 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1659 cmd |= B43_MACCMD_BEACON0_VALID;
1660 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1661 } else if (!beacon1_valid) {
1662 b43_upload_beacon1(dev);
1663 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1664 cmd |= B43_MACCMD_BEACON1_VALID;
1665 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1666 }
c97a4ccc
MB		 1667 }
1668}
1669
a82d9922
MB		 1670static void b43_beacon_update_trigger_work(struct work_struct *work)
1671{
1672 struct b43_wl *wl = container_of(work, struct b43_wl,
1673 beacon_update_trigger);
1674 struct b43_wldev *dev;
1675
1676 mutex_lock(&wl->mutex);
1677 dev = wl->current_dev;
1678 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1679 spin_lock_irq(&wl->irq_lock);
c97a4ccc
MB		 1680 /* update beacon right away or defer to irq */
1681 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1682 handle_irq_beacon(dev);
1683 /* The handler might have updated the IRQ mask. */
1684 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1685 dev->irq_savedstate);
1686 mmiowb();
a82d9922
MB		 1687 spin_unlock_irq(&wl->irq_lock);
1688 }
1689 mutex_unlock(&wl->mutex);
1690}
1691
d4df6f1a
MB		 1692/* Asynchronously update the packet templates in template RAM.
1693 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1694static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1695{
9d139c81
JB		 1696 struct sk_buff *beacon;
1697
e66fee6a
MB		 1698 /* This is the top half of the ansynchronous beacon update.
1699 * The bottom half is the beacon IRQ.
1700 * Beacon update must be asynchronous to avoid sending an
1701 * invalid beacon. This can happen for example, if the firmware
1702 * transmits a beacon while we are updating it. */
e4d6b795 1703
9d139c81
JB		 1704 /* We could modify the existing beacon and set the aid bit in
1705 * the TIM field, but that would probably require resizing and
1706 * moving of data within the beacon template.
1707 * Simply request a new beacon and let mac80211 do the hard work. */
1708 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1709 if (unlikely(!beacon))
1710 return;
1711
e66fee6a
MB		 1712 if (wl->current_beacon)
1713 dev_kfree_skb_any(wl->current_beacon);
1714 wl->current_beacon = beacon;
1715 wl->beacon0_uploaded = 0;
1716 wl->beacon1_uploaded = 0;
a82d9922 1717 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
e4d6b795
MB		 1718}
1719
e4d6b795
MB		 1720static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1721{
1722 b43_time_lock(dev);
1723 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1724 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1725 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1726 } else {
1727 b43_write16(dev, 0x606, (beacon_int >> 6));
1728 b43_write16(dev, 0x610, beacon_int);
1729 }
1730 b43_time_unlock(dev);
a82d9922 1731 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1732}
1733
afa83e23
MB		 1734static void b43_handle_firmware_panic(struct b43_wldev *dev)
1735{
1736 u16 reason;
1737
1738 /* Read the register that contains the reason code for the panic. */
1739 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1740 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1741
1742 switch (reason) {
1743 default:
1744 b43dbg(dev->wl, "The panic reason is unknown.\n");
1745 /* fallthrough */
1746 case B43_FWPANIC_DIE:
1747 /* Do not restart the controller or firmware.
1748 * The device is nonfunctional from now on.
1749 * Restarting would result in this panic to trigger again,
1750 * so we avoid that recursion. */
1751 break;
1752 case B43_FWPANIC_RESTART:
1753 b43_controller_restart(dev, "Microcode panic");
1754 break;
1755 }
1756}
1757
e4d6b795
MB		 1758static void handle_irq_ucode_debug(struct b43_wldev *dev)
1759{
e48b0eeb 1760 unsigned int i, cnt;
53c06856 1761 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1762 __le16 *buf;
1763
1764 /* The proprietary firmware doesn't have this IRQ. */
1765 if (!dev->fw.opensource)
1766 return;
1767
afa83e23
MB		 1768 /* Read the register that contains the reason code for this IRQ. */
1769 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1770
e48b0eeb
MB		 1771 switch (reason) {
1772 case B43_DEBUGIRQ_PANIC:
afa83e23 1773 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1774 break;
1775 case B43_DEBUGIRQ_DUMP_SHM:
1776 if (!B43_DEBUG)
1777 break; /* Only with driver debugging enabled. */
1778 buf = kmalloc(4096, GFP_ATOMIC);
1779 if (!buf) {
1780 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1781 goto out;
1782 }
1783 for (i = 0; i < 4096; i += 2) {
1784 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1785 buf[i / 2] = cpu_to_le16(tmp);
1786 }
1787 b43info(dev->wl, "Shared memory dump:\n");
1788 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1789 16, 2, buf, 4096, 1);
1790 kfree(buf);
1791 break;
1792 case B43_DEBUGIRQ_DUMP_REGS:
1793 if (!B43_DEBUG)
1794 break; /* Only with driver debugging enabled. */
1795 b43info(dev->wl, "Microcode register dump:\n");
1796 for (i = 0, cnt = 0; i < 64; i++) {
1797 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1798 if (cnt == 0)
1799 printk(KERN_INFO);
1800 printk("r%02u: 0x%04X ", i, tmp);
1801 cnt++;
1802 if (cnt == 6) {
1803 printk("\n");
1804 cnt = 0;
1805 }
1806 }
1807 printk("\n");
1808 break;
53c06856
MB		 1809 case B43_DEBUGIRQ_MARKER:
1810 if (!B43_DEBUG)
1811 break; /* Only with driver debugging enabled. */
1812 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1813 B43_MARKER_ID_REG);
1814 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1815 B43_MARKER_LINE_REG);
1816 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1817 "at line number %u\n",
1818 marker_id, marker_line);
1819 break;
e48b0eeb
MB		 1820 default:
1821 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1822 reason);
1823 }
1824out:
afa83e23
MB		 1825 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1826 b43_shm_write16(dev, B43_SHM_SCRATCH,
1827 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1828}
1829
1830/* Interrupt handler bottom-half */
1831static void b43_interrupt_tasklet(struct b43_wldev *dev)
1832{
1833 u32 reason;
1834 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1835 u32 merged_dma_reason = 0;
21954c36 1836 int i;
e4d6b795
MB		 1837 unsigned long flags;
1838
1839 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1840
1841 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1842
1843 reason = dev->irq_reason;
1844 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1845 dma_reason[i] = dev->dma_reason[i];
1846 merged_dma_reason |= dma_reason[i];
1847 }
1848
1849 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1850 b43err(dev->wl, "MAC transmission error\n");
1851
00e0b8cb 1852 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1853 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1854 rmb();
1855 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1856 atomic_set(&dev->phy.txerr_cnt,
1857 B43_PHY_TX_BADNESS_LIMIT);
1858 b43err(dev->wl, "Too many PHY TX errors, "
1859 "restarting the controller\n");
1860 b43_controller_restart(dev, "PHY TX errors");
1861 }
1862 }
e4d6b795
MB		 1863
1864 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1865 B43_DMAIRQ_NONFATALMASK))) {
1866 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1867 b43err(dev->wl, "Fatal DMA error: "
1868 "0x%08X, 0x%08X, 0x%08X, "
1869 "0x%08X, 0x%08X, 0x%08X\n",
1870 dma_reason[0], dma_reason[1],
1871 dma_reason[2], dma_reason[3],
1872 dma_reason[4], dma_reason[5]);
1873 b43_controller_restart(dev, "DMA error");
1874 mmiowb();
1875 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1876 return;
1877 }
1878 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1879 b43err(dev->wl, "DMA error: "
1880 "0x%08X, 0x%08X, 0x%08X, "
1881 "0x%08X, 0x%08X, 0x%08X\n",
1882 dma_reason[0], dma_reason[1],
1883 dma_reason[2], dma_reason[3],
1884 dma_reason[4], dma_reason[5]);
1885 }
1886 }
1887
1888 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1889 handle_irq_ucode_debug(dev);
1890 if (reason & B43_IRQ_TBTT_INDI)
1891 handle_irq_tbtt_indication(dev);
1892 if (reason & B43_IRQ_ATIM_END)
1893 handle_irq_atim_end(dev);
1894 if (reason & B43_IRQ_BEACON)
1895 handle_irq_beacon(dev);
1896 if (reason & B43_IRQ_PMQ)
1897 handle_irq_pmq(dev);
21954c36
MB		 1898 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1899 ;/* TODO */
1900 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1901 handle_irq_noise(dev);
1902
1903 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1904 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1905 if (b43_using_pio_transfers(dev))
1906 b43_pio_rx(dev->pio.rx_queue);
1907 else
1908 b43_dma_rx(dev->dma.rx_ring);
1909 }
e4d6b795
MB		 1910 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1911 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1912 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1913 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1914 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1915
21954c36 1916 if (reason & B43_IRQ_TX_OK)
e4d6b795 1917 handle_irq_transmit_status(dev);
e4d6b795 1918
e4d6b795
MB		 1919 b43_interrupt_enable(dev, dev->irq_savedstate);
1920 mmiowb();
1921 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1922}
1923
e4d6b795
MB		 1924static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1925{
e4d6b795
MB		 1926 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1927
1928 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1929 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1930 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1931 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1932 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1933 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1934}
1935
1936/* Interrupt handler top-half */
1937static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1938{
1939 irqreturn_t ret = IRQ_NONE;
1940 struct b43_wldev *dev = dev_id;
1941 u32 reason;
1942
1943 if (!dev)
1944 return IRQ_NONE;
1945
1946 spin_lock(&dev->wl->irq_lock);
1947
1948 if (b43_status(dev) < B43_STAT_STARTED)
1949 goto out;
1950 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1951 if (reason == 0xffffffff) /* shared IRQ */
1952 goto out;
1953 ret = IRQ_HANDLED;
1954 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1955 if (!reason)
1956 goto out;
1957
1958 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1959 & 0x0001DC00;
1960 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1961 & 0x0000DC00;
1962 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1963 & 0x0000DC00;
1964 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1965 & 0x0001DC00;
1966 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1967 & 0x0000DC00;
1968 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1969 & 0x0000DC00;
1970
1971 b43_interrupt_ack(dev, reason);
1972 /* disable all IRQs. They are enabled again in the bottom half. */
1973 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1974 /* save the reason code and call our bottom half. */
1975 dev->irq_reason = reason;
1976 tasklet_schedule(&dev->isr_tasklet);
1977 out:
1978 mmiowb();
1979 spin_unlock(&dev->wl->irq_lock);
1980
1981 return ret;
1982}
1983
61cb5dd6
MB		 1984static void do_release_fw(struct b43_firmware_file *fw)
1985{
1986 release_firmware(fw->data);
1987 fw->data = NULL;
1988 fw->filename = NULL;
1989}
1990
e4d6b795
MB		 1991static void b43_release_firmware(struct b43_wldev *dev)
1992{
61cb5dd6
MB		 1993 do_release_fw(&dev->fw.ucode);
1994 do_release_fw(&dev->fw.pcm);
1995 do_release_fw(&dev->fw.initvals);
1996 do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1997}
1998
eb189d8b 1999static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2000{
eb189d8b
MB		 2001 const char *text;
2002
2003 text = "You must go to "
354807e0 2004 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
eb189d8b
MB		 2005 "and download the latest firmware (version 4).\n";
2006 if (error)
2007 b43err(wl, text);
2008 else
2009 b43warn(wl, text);
e4d6b795
MB		 2010}
2011
2012static int do_request_fw(struct b43_wldev *dev,
2013 const char *name,
68217832
MB		 2014 struct b43_firmware_file *fw,
2015 bool silent)
e4d6b795 2016{
1a09404a 2017 char path[sizeof(modparam_fwpostfix) + 32];
61cb5dd6 2018 const struct firmware *blob;
e4d6b795
MB		 2019 struct b43_fw_header *hdr;
2020 u32 size;
2021 int err;
2022
61cb5dd6
MB		 2023 if (!name) {
2024 /* Don't fetch anything. Free possibly cached firmware. */
2025 do_release_fw(fw);
e4d6b795 2026 return 0;
61cb5dd6
MB		 2027 }
2028 if (fw->filename) {
2029 if (strcmp(fw->filename, name) == 0)
2030 return 0; /* Already have this fw. */
2031 /* Free the cached firmware first. */
2032 do_release_fw(fw);
2033 }
e4d6b795
MB		 2034
2035 snprintf(path, ARRAY_SIZE(path),
2036 "b43%s/%s.fw",
2037 modparam_fwpostfix, name);
61cb5dd6 2038 err = request_firmware(&blob, path, dev->dev->dev);
68217832
MB		 2039 if (err == -ENOENT) {
2040 if (!silent) {
2041 b43err(dev->wl, "Firmware file \"%s\" not found\n",
2042 path);
2043 }
2044 return err;
2045 } else if (err) {
2046 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2047 path, err);
e4d6b795
MB		 2048 return err;
2049 }
61cb5dd6 2050 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2051 goto err_format;
61cb5dd6 2052 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2053 switch (hdr->type) {
2054 case B43_FW_TYPE_UCODE:
2055 case B43_FW_TYPE_PCM:
2056 size = be32_to_cpu(hdr->size);
61cb5dd6 2057 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2058 goto err_format;
2059 /* fallthrough */
2060 case B43_FW_TYPE_IV:
2061 if (hdr->ver != 1)
2062 goto err_format;
2063 break;
2064 default:
2065 goto err_format;
2066 }
2067
61cb5dd6
MB		 2068 fw->data = blob;
2069 fw->filename = name;
2070
2071 return 0;
e4d6b795
MB		 2072
2073err_format:
2074 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
61cb5dd6
MB		 2075 release_firmware(blob);
2076
e4d6b795
MB		 2077 return -EPROTO;
2078}
2079
2080static int b43_request_firmware(struct b43_wldev *dev)
2081{
2082 struct b43_firmware *fw = &dev->fw;
2083 const u8 rev = dev->dev->id.revision;
2084 const char *filename;
2085 u32 tmshigh;
2086 int err;
2087
61cb5dd6 2088 /* Get microcode */
e4d6b795 2089 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2090 if ((rev >= 5) && (rev <= 10))
2091 filename = "ucode5";
2092 else if ((rev >= 11) && (rev <= 12))
2093 filename = "ucode11";
2094 else if (rev >= 13)
2095 filename = "ucode13";
2096 else
2097 goto err_no_ucode;
68217832 2098 err = do_request_fw(dev, filename, &fw->ucode, 0);
61cb5dd6
MB		 2099 if (err)
2100 goto err_load;
2101
2102 /* Get PCM code */
2103 if ((rev >= 5) && (rev <= 10))
2104 filename = "pcm5";
2105 else if (rev >= 11)
2106 filename = NULL;
2107 else
2108 goto err_no_pcm;
68217832
MB		 2109 fw->pcm_request_failed = 0;
2110 err = do_request_fw(dev, filename, &fw->pcm, 1);
2111 if (err == -ENOENT) {
2112 /* We did not find a PCM file? Not fatal, but
2113 * core rev <= 10 must do without hwcrypto then. */
2114 fw->pcm_request_failed = 1;
2115 } else if (err)
61cb5dd6
MB		 2116 goto err_load;
2117
2118 /* Get initvals */
2119 switch (dev->phy.type) {
2120 case B43_PHYTYPE_A:
2121 if ((rev >= 5) && (rev <= 10)) {
2122 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2123 filename = "a0g1initvals5";
2124 else
2125 filename = "a0g0initvals5";
2126 } else
2127 goto err_no_initvals;
2128 break;
2129 case B43_PHYTYPE_G:
e4d6b795 2130 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2131 filename = "b0g0initvals5";
e4d6b795 2132 else if (rev >= 13)
e9304882 2133 filename = "b0g0initvals13";
e4d6b795 2134 else
61cb5dd6
MB		 2135 goto err_no_initvals;
2136 break;
2137 case B43_PHYTYPE_N:
2138 if ((rev >= 11) && (rev <= 12))
2139 filename = "n0initvals11";
2140 else
2141 goto err_no_initvals;
2142 break;
2143 default:
2144 goto err_no_initvals;
e4d6b795 2145 }
68217832 2146 err = do_request_fw(dev, filename, &fw->initvals, 0);
61cb5dd6
MB		 2147 if (err)
2148 goto err_load;
2149
2150 /* Get bandswitch initvals */
2151 switch (dev->phy.type) {
2152 case B43_PHYTYPE_A:
2153 if ((rev >= 5) && (rev <= 10)) {
2154 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2155 filename = "a0g1bsinitvals5";
2156 else
2157 filename = "a0g0bsinitvals5";
2158 } else if (rev >= 11)
2159 filename = NULL;
2160 else
2161 goto err_no_initvals;
2162 break;
2163 case B43_PHYTYPE_G:
e4d6b795 2164 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2165 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2166 else if (rev >= 11)
2167 filename = NULL;
2168 else
e4d6b795 2169 goto err_no_initvals;
61cb5dd6
MB		 2170 break;
2171 case B43_PHYTYPE_N:
2172 if ((rev >= 11) && (rev <= 12))
2173 filename = "n0bsinitvals11";
2174 else
e4d6b795 2175 goto err_no_initvals;
61cb5dd6
MB		 2176 break;
2177 default:
2178 goto err_no_initvals;
e4d6b795 2179 }
68217832 2180 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
61cb5dd6
MB		 2181 if (err)
2182 goto err_load;
e4d6b795
MB		 2183
2184 return 0;
2185
2186err_load:
eb189d8b 2187 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2188 goto error;
2189
2190err_no_ucode:
2191 err = -ENODEV;
2192 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2193 goto error;
2194
2195err_no_pcm:
2196 err = -ENODEV;
2197 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2198 goto error;
2199
2200err_no_initvals:
2201 err = -ENODEV;
2202 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2203 "core rev %u\n", dev->phy.type, rev);
2204 goto error;
2205
2206error:
2207 b43_release_firmware(dev);
2208 return err;
2209}
2210
2211static int b43_upload_microcode(struct b43_wldev *dev)
2212{
2213 const size_t hdr_len = sizeof(struct b43_fw_header);
2214 const __be32 *data;
2215 unsigned int i, len;
2216 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2217 u32 tmp, macctl;
e4d6b795
MB		 2218 int err = 0;
2219
1f7d87b0
MB		 2220 /* Jump the microcode PSM to offset 0 */
2221 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2222 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2223 macctl |= B43_MACCTL_PSM_JMP0;
2224 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2225 /* Zero out all microcode PSM registers and shared memory. */
2226 for (i = 0; i < 64; i++)
2227 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2228 for (i = 0; i < 4096; i += 2)
2229 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2230
e4d6b795 2231 /* Upload Microcode. */
61cb5dd6
MB		 2232 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2233 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2234 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2235 for (i = 0; i < len; i++) {
2236 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2237 udelay(10);
2238 }
2239
61cb5dd6 2240 if (dev->fw.pcm.data) {
e4d6b795 2241 /* Upload PCM data. */
61cb5dd6
MB		 2242 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2243 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2244 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2245 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2246 /* No need for autoinc bit in SHM_HW */
2247 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2248 for (i = 0; i < len; i++) {
2249 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2250 udelay(10);
2251 }
2252 }
2253
2254 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2255
2256 /* Start the microcode PSM */
2257 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2258 macctl &= ~B43_MACCTL_PSM_JMP0;
2259 macctl |= B43_MACCTL_PSM_RUN;
2260 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2261
2262 /* Wait for the microcode to load and respond */
2263 i = 0;
2264 while (1) {
2265 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2266 if (tmp == B43_IRQ_MAC_SUSPENDED)
2267 break;
2268 i++;
1f7d87b0 2269 if (i >= 20) {
e4d6b795 2270 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2271 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2272 err = -ENODEV;
1f7d87b0
MB		 2273 goto error;
2274 }
2275 msleep_interruptible(50);
2276 if (signal_pending(current)) {
2277 err = -EINTR;
2278 goto error;
e4d6b795 2279 }
e4d6b795
MB		 2280 }
2281 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2282
2283 /* Get and check the revisions. */
2284 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2285 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2286 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2287 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2288
2289 if (fwrev <= 0x128) {
2290 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2291 "binary drivers older than version 4.x is unsupported. "
2292 "You must upgrade your firmware files.\n");
eb189d8b 2293 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2294 err = -EOPNOTSUPP;
1f7d87b0 2295 goto error;
e4d6b795 2296 }
e4d6b795
MB		 2297 dev->fw.rev = fwrev;
2298 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2299 dev->fw.opensource = (fwdate == 0xFFFF);
2300
2301 if (dev->fw.opensource) {
2302 /* Patchlevel info is encoded in the "time" field. */
2303 dev->fw.patch = fwtime;
68217832
MB		 2304 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2305 dev->fw.rev, dev->fw.patch,
2306 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
e48b0eeb
MB		 2307 } else {
2308 b43info(dev->wl, "Loading firmware version %u.%u "
2309 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2310 fwrev, fwpatch,
2311 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2312 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2313 if (dev->fw.pcm_request_failed) {
2314 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2315 "Hardware accelerated cryptography is disabled.\n");
2316 b43_print_fw_helptext(dev->wl, 0);
2317 }
e48b0eeb 2318 }
e4d6b795 2319
eb189d8b
MB		 2320 if (b43_is_old_txhdr_format(dev)) {
2321 b43warn(dev->wl, "You are using an old firmware image. "
2322 "Support for old firmware will be removed in July 2008.\n");
2323 b43_print_fw_helptext(dev->wl, 0);
2324 }
2325
1f7d87b0
MB		 2326 return 0;
2327
2328error:
2329 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2330 macctl &= ~B43_MACCTL_PSM_RUN;
2331 macctl |= B43_MACCTL_PSM_JMP0;
2332 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2333
e4d6b795
MB		 2334 return err;
2335}
2336
2337static int b43_write_initvals(struct b43_wldev *dev,
2338 const struct b43_iv *ivals,
2339 size_t count,
2340 size_t array_size)
2341{
2342 const struct b43_iv *iv;
2343 u16 offset;
2344 size_t i;
2345 bool bit32;
2346
2347 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2348 iv = ivals;
2349 for (i = 0; i < count; i++) {
2350 if (array_size < sizeof(iv->offset_size))
2351 goto err_format;
2352 array_size -= sizeof(iv->offset_size);
2353 offset = be16_to_cpu(iv->offset_size);
2354 bit32 = !!(offset & B43_IV_32BIT);
2355 offset &= B43_IV_OFFSET_MASK;
2356 if (offset >= 0x1000)
2357 goto err_format;
2358 if (bit32) {
2359 u32 value;
2360
2361 if (array_size < sizeof(iv->data.d32))
2362 goto err_format;
2363 array_size -= sizeof(iv->data.d32);
2364
533dd1b0 2365 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2366 b43_write32(dev, offset, value);
2367
2368 iv = (const struct b43_iv *)((const uint8_t *)iv +
2369 sizeof(__be16) +
2370 sizeof(__be32));
2371 } else {
2372 u16 value;
2373
2374 if (array_size < sizeof(iv->data.d16))
2375 goto err_format;
2376 array_size -= sizeof(iv->data.d16);
2377
2378 value = be16_to_cpu(iv->data.d16);
2379 b43_write16(dev, offset, value);
2380
2381 iv = (const struct b43_iv *)((const uint8_t *)iv +
2382 sizeof(__be16) +
2383 sizeof(__be16));
2384 }
2385 }
2386 if (array_size)
2387 goto err_format;
2388
2389 return 0;
2390
2391err_format:
2392 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2393 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2394
2395 return -EPROTO;
2396}
2397
2398static int b43_upload_initvals(struct b43_wldev *dev)
2399{
2400 const size_t hdr_len = sizeof(struct b43_fw_header);
2401 const struct b43_fw_header *hdr;
2402 struct b43_firmware *fw = &dev->fw;
2403 const struct b43_iv *ivals;
2404 size_t count;
2405 int err;
2406
61cb5dd6
MB		 2407 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2408 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2409 count = be32_to_cpu(hdr->size);
2410 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2411 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2412 if (err)
2413 goto out;
61cb5dd6
MB		 2414 if (fw->initvals_band.data) {
2415 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2416 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2417 count = be32_to_cpu(hdr->size);
2418 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2419 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2420 if (err)
2421 goto out;
2422 }
2423out:
2424
2425 return err;
2426}
2427
2428/* Initialize the GPIOs
2429 * http://bcm-specs.sipsolutions.net/GPIO
2430 */
2431static int b43_gpio_init(struct b43_wldev *dev)
2432{
2433 struct ssb_bus *bus = dev->dev->bus;
2434 struct ssb_device *gpiodev, *pcidev = NULL;
2435 u32 mask, set;
2436
2437 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2438 & ~B43_MACCTL_GPOUTSMSK);
2439
e4d6b795
MB		 2440 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2441 | 0x000F);
2442
2443 mask = 0x0000001F;
2444 set = 0x0000000F;
2445 if (dev->dev->bus->chip_id == 0x4301) {
2446 mask |= 0x0060;
2447 set |= 0x0060;
2448 }
2449 if (0 /* FIXME: conditional unknown */ ) {
2450 b43_write16(dev, B43_MMIO_GPIO_MASK,
2451 b43_read16(dev, B43_MMIO_GPIO_MASK)
2452 | 0x0100);
2453 mask |= 0x0180;
2454 set |= 0x0180;
2455 }
95de2841 2456 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2457 b43_write16(dev, B43_MMIO_GPIO_MASK,
2458 b43_read16(dev, B43_MMIO_GPIO_MASK)
2459 | 0x0200);
2460 mask |= 0x0200;
2461 set |= 0x0200;
2462 }
2463 if (dev->dev->id.revision >= 2)
2464 mask |= 0x0010; /* FIXME: This is redundant. */
2465
2466#ifdef CONFIG_SSB_DRIVER_PCICORE
2467 pcidev = bus->pcicore.dev;
2468#endif
2469 gpiodev = bus->chipco.dev ? : pcidev;
2470 if (!gpiodev)
2471 return 0;
2472 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2473 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2474 & mask) | set);
2475
2476 return 0;
2477}
2478
2479/* Turn off all GPIO stuff. Call this on module unload, for example. */
2480static void b43_gpio_cleanup(struct b43_wldev *dev)
2481{
2482 struct ssb_bus *bus = dev->dev->bus;
2483 struct ssb_device *gpiodev, *pcidev = NULL;
2484
2485#ifdef CONFIG_SSB_DRIVER_PCICORE
2486 pcidev = bus->pcicore.dev;
2487#endif
2488 gpiodev = bus->chipco.dev ? : pcidev;
2489 if (!gpiodev)
2490 return;
2491 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2492}
2493
2494/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2495void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2496{
923fd703
MB		 2497 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2498 u16 fwstate;
2499
2500 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2501 B43_SHM_SH_UCODESTAT);
2502 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2503 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2504 b43err(dev->wl, "b43_mac_enable(): The firmware "
2505 "should be suspended, but current state is %u\n",
2506 fwstate);
2507 }
2508 }
2509
e4d6b795
MB		 2510 dev->mac_suspended--;
2511 B43_WARN_ON(dev->mac_suspended < 0);
2512 if (dev->mac_suspended == 0) {
2513 b43_write32(dev, B43_MMIO_MACCTL,
2514 b43_read32(dev, B43_MMIO_MACCTL)
2515 | B43_MACCTL_ENABLED);
2516 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2517 B43_IRQ_MAC_SUSPENDED);
2518 /* Commit writes */
2519 b43_read32(dev, B43_MMIO_MACCTL);
2520 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2521 b43_power_saving_ctl_bits(dev, 0);
2522 }
2523}
2524
2525/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2526void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2527{
2528 int i;
2529 u32 tmp;
2530
05b64b36 2531 might_sleep();
e4d6b795 2532 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2533
e4d6b795
MB		 2534 if (dev->mac_suspended == 0) {
2535 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2536 b43_write32(dev, B43_MMIO_MACCTL,
2537 b43_read32(dev, B43_MMIO_MACCTL)
2538 & ~B43_MACCTL_ENABLED);
2539 /* force pci to flush the write */
2540 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2541 for (i = 35; i; i--) {
2542 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2543 if (tmp & B43_IRQ_MAC_SUSPENDED)
2544 goto out;
2545 udelay(10);
2546 }
2547 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2548 for (i = 40; i; i--) {
e4d6b795
MB		 2549 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2550 if (tmp & B43_IRQ_MAC_SUSPENDED)
2551 goto out;
05b64b36 2552 msleep(1);
e4d6b795
MB		 2553 }
2554 b43err(dev->wl, "MAC suspend failed\n");
2555 }
05b64b36 2556out:
e4d6b795
MB		 2557 dev->mac_suspended++;
2558}
2559
2560static void b43_adjust_opmode(struct b43_wldev *dev)
2561{
2562 struct b43_wl *wl = dev->wl;
2563 u32 ctl;
2564 u16 cfp_pretbtt;
2565
2566 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2567 /* Reset status to STA infrastructure mode. */
2568 ctl &= ~B43_MACCTL_AP;
2569 ctl &= ~B43_MACCTL_KEEP_CTL;
2570 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2571 ctl &= ~B43_MACCTL_KEEP_BAD;
2572 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2573 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2574 ctl |= B43_MACCTL_INFRA;
2575
05c914fe
JB		 2576 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2577 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2578 ctl |= B43_MACCTL_AP;
05c914fe 2579 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2580 ctl &= ~B43_MACCTL_INFRA;
2581
2582 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2583 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2584 if (wl->filter_flags & FIF_FCSFAIL)
2585 ctl |= B43_MACCTL_KEEP_BAD;
2586 if (wl->filter_flags & FIF_PLCPFAIL)
2587 ctl |= B43_MACCTL_KEEP_BADPLCP;
2588 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2589 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2590 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2591 ctl |= B43_MACCTL_BEACPROMISC;
2592
e4d6b795
MB		 2593 /* Workaround: On old hardware the HW-MAC-address-filter
2594 * doesn't work properly, so always run promisc in filter
2595 * it in software. */
2596 if (dev->dev->id.revision <= 4)
2597 ctl |= B43_MACCTL_PROMISC;
2598
2599 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2600
2601 cfp_pretbtt = 2;
2602 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2603 if (dev->dev->bus->chip_id == 0x4306 &&
2604 dev->dev->bus->chip_rev == 3)
2605 cfp_pretbtt = 100;
2606 else
2607 cfp_pretbtt = 50;
2608 }
2609 b43_write16(dev, 0x612, cfp_pretbtt);
2610}
2611
2612static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2613{
2614 u16 offset;
2615
2616 if (is_ofdm) {
2617 offset = 0x480;
2618 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2619 } else {
2620 offset = 0x4C0;
2621 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2622 }
2623 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2624 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2625}
2626
2627static void b43_rate_memory_init(struct b43_wldev *dev)
2628{
2629 switch (dev->phy.type) {
2630 case B43_PHYTYPE_A:
2631 case B43_PHYTYPE_G:
53a6e234 2632 case B43_PHYTYPE_N:
e4d6b795
MB		 2633 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2634 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2635 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2636 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2637 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2638 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2639 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2640 if (dev->phy.type == B43_PHYTYPE_A)
2641 break;
2642 /* fallthrough */
2643 case B43_PHYTYPE_B:
2644 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2645 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2646 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2647 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2648 break;
2649 default:
2650 B43_WARN_ON(1);
2651 }
2652}
2653
5042c507
MB		 2654/* Set the default values for the PHY TX Control Words. */
2655static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2656{
2657 u16 ctl = 0;
2658
2659 ctl |= B43_TXH_PHY_ENC_CCK;
2660 ctl |= B43_TXH_PHY_ANT01AUTO;
2661 ctl |= B43_TXH_PHY_TXPWR;
2662
2663 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2664 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2665 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2666}
2667
e4d6b795
MB		 2668/* Set the TX-Antenna for management frames sent by firmware. */
2669static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2670{
5042c507 2671 u16 ant;
e4d6b795
MB		 2672 u16 tmp;
2673
5042c507 2674 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2675
e4d6b795
MB		 2676 /* For ACK/CTS */
2677 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2678 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2679 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2680 /* For Probe Resposes */
2681 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2682 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2683 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2684}
2685
2686/* This is the opposite of b43_chip_init() */
2687static void b43_chip_exit(struct b43_wldev *dev)
2688{
fb11137a 2689 b43_phy_exit(dev);
e4d6b795
MB		 2690 b43_gpio_cleanup(dev);
2691 /* firmware is released later */
2692}
2693
2694/* Initialize the chip
2695 * http://bcm-specs.sipsolutions.net/ChipInit
2696 */
2697static int b43_chip_init(struct b43_wldev *dev)
2698{
2699 struct b43_phy *phy = &dev->phy;
ef1a628d 2700 int err;
1f7d87b0 2701 u32 value32, macctl;
e4d6b795
MB		 2702 u16 value16;
2703
1f7d87b0
MB		 2704 /* Initialize the MAC control */
2705 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2706 if (dev->phy.gmode)
2707 macctl |= B43_MACCTL_GMODE;
2708 macctl |= B43_MACCTL_INFRA;
2709 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2710
2711 err = b43_request_firmware(dev);
2712 if (err)
2713 goto out;
2714 err = b43_upload_microcode(dev);
2715 if (err)
2716 goto out; /* firmware is released later */
2717
2718 err = b43_gpio_init(dev);
2719 if (err)
2720 goto out; /* firmware is released later */
21954c36 2721
e4d6b795
MB		 2722 err = b43_upload_initvals(dev);
2723 if (err)
1a8d1227 2724 goto err_gpio_clean;
e4d6b795 2725
0b7dcd96
MB		 2726 /* Turn the Analog on and initialize the PHY. */
2727 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2728 err = b43_phy_init(dev);
2729 if (err)
ef1a628d 2730 goto err_gpio_clean;
e4d6b795 2731
ef1a628d
MB		 2732 /* Disable Interference Mitigation. */
2733 if (phy->ops->interf_mitigation)
2734 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2735
ef1a628d
MB		 2736 /* Select the antennae */
2737 if (phy->ops->set_rx_antenna)
2738 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2739 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2740
2741 if (phy->type == B43_PHYTYPE_B) {
2742 value16 = b43_read16(dev, 0x005E);
2743 value16 |= 0x0004;
2744 b43_write16(dev, 0x005E, value16);
2745 }
2746 b43_write32(dev, 0x0100, 0x01000000);
2747 if (dev->dev->id.revision < 5)
2748 b43_write32(dev, 0x010C, 0x01000000);
2749
2750 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2751 & ~B43_MACCTL_INFRA);
2752 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2753 | B43_MACCTL_INFRA);
e4d6b795 2754
e4d6b795
MB		 2755 /* Probe Response Timeout value */
2756 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2757 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2758
2759 /* Initially set the wireless operation mode. */
2760 b43_adjust_opmode(dev);
2761
2762 if (dev->dev->id.revision < 3) {
2763 b43_write16(dev, 0x060E, 0x0000);
2764 b43_write16(dev, 0x0610, 0x8000);
2765 b43_write16(dev, 0x0604, 0x0000);
2766 b43_write16(dev, 0x0606, 0x0200);
2767 } else {
2768 b43_write32(dev, 0x0188, 0x80000000);
2769 b43_write32(dev, 0x018C, 0x02000000);
2770 }
2771 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2772 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2773 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2774 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2775 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2776 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2777 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2778
2779 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2780 value32 |= 0x00100000;
2781 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2782
2783 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2784 dev->dev->bus->chipco.fast_pwrup_delay);
2785
2786 err = 0;
2787 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2788out:
e4d6b795
MB		 2789 return err;
2790
1a8d1227 2791err_gpio_clean:
e4d6b795 2792 b43_gpio_cleanup(dev);
21954c36 2793 return err;
e4d6b795
MB		 2794}
2795
e4d6b795
MB		 2796static void b43_periodic_every60sec(struct b43_wldev *dev)
2797{
ef1a628d 2798 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2799
ef1a628d
MB		 2800 if (ops->pwork_60sec)
2801 ops->pwork_60sec(dev);
18c8adeb
MB		 2802
2803 /* Force check the TX power emission now. */
2804 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2805}
2806
2807static void b43_periodic_every30sec(struct b43_wldev *dev)
2808{
2809 /* Update device statistics. */
2810 b43_calculate_link_quality(dev);
2811}
2812
2813static void b43_periodic_every15sec(struct b43_wldev *dev)
2814{
2815 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2816 u16 wdr;
2817
2818 if (dev->fw.opensource) {
2819 /* Check if the firmware is still alive.
2820 * It will reset the watchdog counter to 0 in its idle loop. */
2821 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2822 if (unlikely(wdr)) {
2823 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2824 b43_controller_restart(dev, "Firmware watchdog");
2825 return;
2826 } else {
2827 b43_shm_write16(dev, B43_SHM_SCRATCH,
2828 B43_WATCHDOG_REG, 1);
2829 }
2830 }
e4d6b795 2831
ef1a628d
MB		 2832 if (phy->ops->pwork_15sec)
2833 phy->ops->pwork_15sec(dev);
2834
00e0b8cb
SB		 2835 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2836 wmb();
e4d6b795
MB		 2837}
2838
e4d6b795
MB		 2839static void do_periodic_work(struct b43_wldev *dev)
2840{
2841 unsigned int state;
2842
2843 state = dev->periodic_state;
42bb4cd5 2844 if (state % 4 == 0)
e4d6b795 2845 b43_periodic_every60sec(dev);
42bb4cd5 2846 if (state % 2 == 0)
e4d6b795 2847 b43_periodic_every30sec(dev);
42bb4cd5 2848 b43_periodic_every15sec(dev);
e4d6b795
MB		 2849}
2850
05b64b36
MB		 2851/* Periodic work locking policy:
2852 * The whole periodic work handler is protected by
2853 * wl->mutex. If another lock is needed somewhere in the
2854 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2855 */
e4d6b795
MB		 2856static void b43_periodic_work_handler(struct work_struct *work)
2857{
05b64b36
MB		 2858 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2859 periodic_work.work);
2860 struct b43_wl *wl = dev->wl;
2861 unsigned long delay;
e4d6b795 2862
05b64b36 2863 mutex_lock(&wl->mutex);
e4d6b795
MB		 2864
2865 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2866 goto out;
2867 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2868 goto out_requeue;
2869
05b64b36 2870 do_periodic_work(dev);
e4d6b795 2871
e4d6b795 2872 dev->periodic_state++;
42bb4cd5 2873out_requeue:
e4d6b795
MB		 2874 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2875 delay = msecs_to_jiffies(50);
2876 else
82cd682d 2877 delay = round_jiffies_relative(HZ * 15);
05b64b36 2878 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2879out:
05b64b36 2880 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2881}
2882
2883static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2884{
2885 struct delayed_work *work = &dev->periodic_work;
2886
2887 dev->periodic_state = 0;
2888 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2889 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2890}
2891
f3dd3fcc 2892/* Check if communication with the device works correctly. */
e4d6b795
MB		 2893static int b43_validate_chipaccess(struct b43_wldev *dev)
2894{
f3dd3fcc 2895 u32 v, backup;
e4d6b795 2896
f3dd3fcc
MB		 2897 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2898
2899 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2900 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2901 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2902 goto error;
f3dd3fcc
MB		 2903 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2904 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2905 goto error;
2906
f3dd3fcc
MB		 2907 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2908
2909 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2910 /* The 32bit register shadows the two 16bit registers
2911 * with update sideeffects. Validate this. */
2912 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2913 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2914 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2915 goto error;
2916 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2917 goto error;
2918 }
2919 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2920
2921 v = b43_read32(dev, B43_MMIO_MACCTL);
2922 v |= B43_MACCTL_GMODE;
2923 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2924 goto error;
2925
2926 return 0;
f3dd3fcc 2927error:
e4d6b795
MB		 2928 b43err(dev->wl, "Failed to validate the chipaccess\n");
2929 return -ENODEV;
2930}
2931
2932static void b43_security_init(struct b43_wldev *dev)
2933{
2934 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2935 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2936 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2937 /* KTP is a word address, but we address SHM bytewise.
2938 * So multiply by two.
2939 */
2940 dev->ktp *= 2;
2941 if (dev->dev->id.revision >= 5) {
2942 /* Number of RCMTA address slots */
2943 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2944 }
2945 b43_clear_keys(dev);
2946}
2947
2948static int b43_rng_read(struct hwrng *rng, u32 * data)
2949{
2950 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2951 unsigned long flags;
2952
2953 /* Don't take wl->mutex here, as it could deadlock with
2954 * hwrng internal locking. It's not needed to take
2955 * wl->mutex here, anyway. */
2956
2957 spin_lock_irqsave(&wl->irq_lock, flags);
2958 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2959 spin_unlock_irqrestore(&wl->irq_lock, flags);
2960
2961 return (sizeof(u16));
2962}
2963
b844eba2 2964static void b43_rng_exit(struct b43_wl *wl)
e4d6b795
MB		 2965{
2966 if (wl->rng_initialized)
b844eba2 2967 hwrng_unregister(&wl->rng);
e4d6b795
MB		 2968}
2969
2970static int b43_rng_init(struct b43_wl *wl)
2971{
2972 int err;
2973
2974 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2975 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2976 wl->rng.name = wl->rng_name;
2977 wl->rng.data_read = b43_rng_read;
2978 wl->rng.priv = (unsigned long)wl;
2979 wl->rng_initialized = 1;
2980 err = hwrng_register(&wl->rng);
2981 if (err) {
2982 wl->rng_initialized = 0;
2983 b43err(wl, "Failed to register the random "
2984 "number generator (%d)\n", err);
2985 }
2986
2987 return err;
2988}
2989
40faacc4 2990static int b43_op_tx(struct ieee80211_hw *hw,
e039fa4a 2991 struct sk_buff *skb)
e4d6b795
MB		 2992{
2993 struct b43_wl *wl = hw_to_b43_wl(hw);
2994 struct b43_wldev *dev = wl->current_dev;
21a75d77
MB		 2995 unsigned long flags;
2996 int err;
e4d6b795 2997
5100d5ac
MB		 2998 if (unlikely(skb->len < 2 + 2 + 6)) {
2999 /* Too short, this can't be a valid frame. */
c9e8eae0 3000 goto drop_packet;
5100d5ac
MB		 3001 }
3002 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
e4d6b795 3003 if (unlikely(!dev))
c9e8eae0 3004 goto drop_packet;
21a75d77
MB		 3005
3006 /* Transmissions on seperate queues can run concurrently. */
3007 read_lock_irqsave(&wl->tx_lock, flags);
3008
3009 err = -ENODEV;
3010 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3011 if (b43_using_pio_transfers(dev))
e039fa4a 3012 err = b43_pio_tx(dev, skb);
21a75d77 3013 else
e039fa4a 3014 err = b43_dma_tx(dev, skb);
21a75d77
MB		 3015 }
3016
3017 read_unlock_irqrestore(&wl->tx_lock, flags);
3018
e4d6b795 3019 if (unlikely(err))
c9e8eae0
MB		 3020 goto drop_packet;
3021 return NETDEV_TX_OK;
3022
3023drop_packet:
3024 /* We can not transmit this packet. Drop it. */
3025 dev_kfree_skb_any(skb);
e4d6b795
MB		 3026 return NETDEV_TX_OK;
3027}
3028
e6f5b934
MB		 3029/* Locking: wl->irq_lock */
3030static void b43_qos_params_upload(struct b43_wldev *dev,
3031 const struct ieee80211_tx_queue_params *p,
3032 u16 shm_offset)
3033{
3034 u16 params[B43_NR_QOSPARAMS];
0b57664c 3035 int bslots, tmp;
e6f5b934
MB		 3036 unsigned int i;
3037
0b57664c 3038 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3039
3040 memset(&params, 0, sizeof(params));
3041
3042 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3043 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3044 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3045 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3046 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3047 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3048 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3049
3050 for (i = 0; i < ARRAY_SIZE(params); i++) {
3051 if (i == B43_QOSPARAM_STATUS) {
3052 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3053 shm_offset + (i * 2));
3054 /* Mark the parameters as updated. */
3055 tmp |= 0x100;
3056 b43_shm_write16(dev, B43_SHM_SHARED,
3057 shm_offset + (i * 2),
3058 tmp);
3059 } else {
3060 b43_shm_write16(dev, B43_SHM_SHARED,
3061 shm_offset + (i * 2),
3062 params[i]);
3063 }
3064 }
3065}
3066
c40c1129
MB		 3067/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3068static const u16 b43_qos_shm_offsets[] = {
3069 /* [mac80211-queue-nr] = SHM_OFFSET, */
3070 [0] = B43_QOS_VOICE,
3071 [1] = B43_QOS_VIDEO,
3072 [2] = B43_QOS_BESTEFFORT,
3073 [3] = B43_QOS_BACKGROUND,
3074};
3075
5a5f3b40
MB		 3076/* Update all QOS parameters in hardware. */
3077static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3078{
3079 struct b43_wl *wl = dev->wl;
3080 struct b43_qos_params *params;
e6f5b934
MB		 3081 unsigned int i;
3082
c40c1129
MB		 3083 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3084 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3085
3086 b43_mac_suspend(dev);
e6f5b934
MB		 3087 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3088 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3089 b43_qos_params_upload(dev, &(params->p),
3090 b43_qos_shm_offsets[i]);
e6f5b934 3091 }
e6f5b934
MB		 3092 b43_mac_enable(dev);
3093}
3094
3095static void b43_qos_clear(struct b43_wl *wl)
3096{
3097 struct b43_qos_params *params;
3098 unsigned int i;
3099
c40c1129
MB		 3100 /* Initialize QoS parameters to sane defaults. */
3101
3102 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3103 ARRAY_SIZE(wl->qos_params));
3104
e6f5b934
MB		 3105 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3106 params = &(wl->qos_params[i]);
3107
c40c1129
MB		 3108 switch (b43_qos_shm_offsets[i]) {
3109 case B43_QOS_VOICE:
3110 params->p.txop = 0;
3111 params->p.aifs = 2;
3112 params->p.cw_min = 0x0001;
3113 params->p.cw_max = 0x0001;
3114 break;
3115 case B43_QOS_VIDEO:
3116 params->p.txop = 0;
3117 params->p.aifs = 2;
3118 params->p.cw_min = 0x0001;
3119 params->p.cw_max = 0x0001;
3120 break;
3121 case B43_QOS_BESTEFFORT:
3122 params->p.txop = 0;
3123 params->p.aifs = 3;
3124 params->p.cw_min = 0x0001;
3125 params->p.cw_max = 0x03FF;
3126 break;
3127 case B43_QOS_BACKGROUND:
3128 params->p.txop = 0;
3129 params->p.aifs = 7;
3130 params->p.cw_min = 0x0001;
3131 params->p.cw_max = 0x03FF;
3132 break;
3133 default:
3134 B43_WARN_ON(1);
3135 }
e6f5b934
MB		 3136 }
3137}
3138
3139/* Initialize the core's QOS capabilities */
3140static void b43_qos_init(struct b43_wldev *dev)
3141{
e6f5b934 3142 /* Upload the current QOS parameters. */
5a5f3b40 3143 b43_qos_upload_all(dev);
e6f5b934
MB		 3144
3145 /* Enable QOS support. */
3146 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3147 b43_write16(dev, B43_MMIO_IFSCTL,
3148 b43_read16(dev, B43_MMIO_IFSCTL)
3149 | B43_MMIO_IFSCTL_USE_EDCF);
3150}
3151
e100bb64 3152static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3153 const struct ieee80211_tx_queue_params *params)
e4d6b795 3154{
e6f5b934 3155 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3156 struct b43_wldev *dev;
e6f5b934 3157 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3158 int err = -ENODEV;
e6f5b934
MB		 3159
3160 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3161 /* Queue not available or don't support setting
3162 * params on this queue. Return success to not
3163 * confuse mac80211. */
3164 return 0;
3165 }
5a5f3b40
MB		 3166 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3167 ARRAY_SIZE(wl->qos_params));
e6f5b934 3168
5a5f3b40
MB		 3169 mutex_lock(&wl->mutex);
3170 dev = wl->current_dev;
3171 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3172 goto out_unlock;
e6f5b934 3173
5a5f3b40
MB		 3174 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3175 b43_mac_suspend(dev);
3176 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3177 b43_qos_shm_offsets[queue]);
3178 b43_mac_enable(dev);
3179 err = 0;
e6f5b934 3180
5a5f3b40
MB		 3181out_unlock:
3182 mutex_unlock(&wl->mutex);
3183
3184 return err;
e4d6b795
MB		 3185}
3186
40faacc4
MB		 3187static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3188 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3189{
3190 struct b43_wl *wl = hw_to_b43_wl(hw);
3191 struct b43_wldev *dev = wl->current_dev;
3192 unsigned long flags;
3193 int err = -ENODEV;
3194
3195 if (!dev)
3196 goto out;
3197 spin_lock_irqsave(&wl->irq_lock, flags);
3198 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3199 if (b43_using_pio_transfers(dev))
3200 b43_pio_get_tx_stats(dev, stats);
3201 else
3202 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3203 err = 0;
3204 }
3205 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3206out:
e4d6b795
MB		 3207 return err;
3208}
3209
40faacc4
MB		 3210static int b43_op_get_stats(struct ieee80211_hw *hw,
3211 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3212{
3213 struct b43_wl *wl = hw_to_b43_wl(hw);
3214 unsigned long flags;
3215
3216 spin_lock_irqsave(&wl->irq_lock, flags);
3217 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3218 spin_unlock_irqrestore(&wl->irq_lock, flags);
3219
3220 return 0;
3221}
3222
e4d6b795
MB		 3223static void b43_put_phy_into_reset(struct b43_wldev *dev)
3224{
3225 struct ssb_device *sdev = dev->dev;
3226 u32 tmslow;
3227
3228 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3229 tmslow &= ~B43_TMSLOW_GMODE;
3230 tmslow |= B43_TMSLOW_PHYRESET;
3231 tmslow |= SSB_TMSLOW_FGC;
3232 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3233 msleep(1);
3234
3235 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3236 tmslow &= ~SSB_TMSLOW_FGC;
3237 tmslow |= B43_TMSLOW_PHYRESET;
3238 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3239 msleep(1);
3240}
3241
bb1eeff1
MB		 3242static const char * band_to_string(enum ieee80211_band band)
3243{
3244 switch (band) {
3245 case IEEE80211_BAND_5GHZ:
3246 return "5";
3247 case IEEE80211_BAND_2GHZ:
3248 return "2.4";
3249 default:
3250 break;
3251 }
3252 B43_WARN_ON(1);
3253 return "";
3254}
3255
e4d6b795 3256/* Expects wl->mutex locked */
bb1eeff1 3257static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3258{
bb1eeff1 3259 struct b43_wldev *up_dev = NULL;
e4d6b795 3260 struct b43_wldev *down_dev;
bb1eeff1 3261 struct b43_wldev *d;
e4d6b795 3262 int err;
922d8a0b 3263 bool uninitialized_var(gmode);
e4d6b795
MB		 3264 int prev_status;
3265
bb1eeff1
MB		 3266 /* Find a device and PHY which supports the band. */
3267 list_for_each_entry(d, &wl->devlist, list) {
3268 switch (chan->band) {
3269 case IEEE80211_BAND_5GHZ:
3270 if (d->phy.supports_5ghz) {
3271 up_dev = d;
3272 gmode = 0;
3273 }
3274 break;
3275 case IEEE80211_BAND_2GHZ:
3276 if (d->phy.supports_2ghz) {
3277 up_dev = d;
3278 gmode = 1;
3279 }
3280 break;
3281 default:
3282 B43_WARN_ON(1);
3283 return -EINVAL;
3284 }
3285 if (up_dev)
3286 break;
3287 }
3288 if (!up_dev) {
3289 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3290 band_to_string(chan->band));
3291 return -ENODEV;
e4d6b795
MB		 3292 }
3293 if ((up_dev == wl->current_dev) &&
3294 (!!wl->current_dev->phy.gmode == !!gmode)) {
3295 /* This device is already running. */
3296 return 0;
3297 }
bb1eeff1
MB		 3298 b43dbg(wl, "Switching to %s-GHz band\n",
3299 band_to_string(chan->band));
e4d6b795
MB		 3300 down_dev = wl->current_dev;
3301
3302 prev_status = b43_status(down_dev);
3303 /* Shutdown the currently running core. */
3304 if (prev_status >= B43_STAT_STARTED)
3305 b43_wireless_core_stop(down_dev);
3306 if (prev_status >= B43_STAT_INITIALIZED)
3307 b43_wireless_core_exit(down_dev);
3308
3309 if (down_dev != up_dev) {
3310 /* We switch to a different core, so we put PHY into
3311 * RESET on the old core. */
3312 b43_put_phy_into_reset(down_dev);
3313 }
3314
3315 /* Now start the new core. */
3316 up_dev->phy.gmode = gmode;
3317 if (prev_status >= B43_STAT_INITIALIZED) {
3318 err = b43_wireless_core_init(up_dev);
3319 if (err) {
3320 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3321 "selected %s-GHz band\n",
3322 band_to_string(chan->band));
e4d6b795
MB		 3323 goto init_failure;
3324 }
3325 }
3326 if (prev_status >= B43_STAT_STARTED) {
3327 err = b43_wireless_core_start(up_dev);
3328 if (err) {
3329 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3330 "selected %s-GHz band\n",
3331 band_to_string(chan->band));
e4d6b795
MB		 3332 b43_wireless_core_exit(up_dev);
3333 goto init_failure;
3334 }
3335 }
3336 B43_WARN_ON(b43_status(up_dev) != prev_status);
3337
3338 wl->current_dev = up_dev;
3339
3340 return 0;
bb1eeff1 3341init_failure:
e4d6b795
MB		 3342 /* Whoops, failed to init the new core. No core is operating now. */
3343 wl->current_dev = NULL;
3344 return err;
3345}
3346
9124b077
JB		 3347/* Write the short and long frame retry limit values. */
3348static void b43_set_retry_limits(struct b43_wldev *dev,
3349 unsigned int short_retry,
3350 unsigned int long_retry)
3351{
3352 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3353 * the chip-internal counter. */
3354 short_retry = min(short_retry, (unsigned int)0xF);
3355 long_retry = min(long_retry, (unsigned int)0xF);
3356
3357 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3358 short_retry);
3359 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3360 long_retry);
3361}
3362
e8975581 3363static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3364{
3365 struct b43_wl *wl = hw_to_b43_wl(hw);
3366 struct b43_wldev *dev;
3367 struct b43_phy *phy;
e8975581 3368 struct ieee80211_conf *conf = &hw->conf;
e4d6b795 3369 unsigned long flags;
9db1f6d7 3370 int antenna;
e4d6b795 3371 int err = 0;
e4d6b795 3372
e4d6b795
MB		 3373 mutex_lock(&wl->mutex);
3374
bb1eeff1
MB		 3375 /* Switch the band (if necessary). This might change the active core. */
3376 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3377 if (err)
3378 goto out_unlock_mutex;
3379 dev = wl->current_dev;
3380 phy = &dev->phy;
3381
d10d0e57
MB		 3382 b43_mac_suspend(dev);
3383
9124b077
JB		 3384 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3385 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3386 conf->long_frame_max_tx_count);
3387 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3388 if (!changed)
d10d0e57 3389 goto out_mac_enable;
e4d6b795
MB		 3390
3391 /* Switch to the requested channel.
3392 * The firmware takes care of races with the TX handler. */
8318d78a 3393 if (conf->channel->hw_value != phy->channel)
ef1a628d 3394 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3395
d42ce84a
JB		 3396 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3397
e4d6b795
MB		 3398 /* Adjust the desired TX power level. */
3399 if (conf->power_level != 0) {
18c8adeb
MB		 3400 spin_lock_irqsave(&wl->irq_lock, flags);
3401 if (conf->power_level != phy->desired_txpower) {
3402 phy->desired_txpower = conf->power_level;
3403 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3404 B43_TXPWR_IGNORE_TSSI);
e4d6b795 3405 }
18c8adeb 3406 spin_unlock_irqrestore(&wl->irq_lock, flags);
e4d6b795
MB		 3407 }
3408
3409 /* Antennas for RX and management frame TX. */
0f4ac38b 3410 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3411 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3412 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3413 if (phy->ops->set_rx_antenna)
3414 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3415
04dea136 3416 /* Update templates for AP/mesh mode. */
05c914fe
JB		 3417 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3418 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
e4d6b795
MB		 3419 b43_set_beacon_int(dev, conf->beacon_int);
3420
fda9abcf
MB		 3421 if (!!conf->radio_enabled != phy->radio_on) {
3422 if (conf->radio_enabled) {
ef1a628d 3423 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
fda9abcf
MB		 3424 b43info(dev->wl, "Radio turned on by software\n");
3425 if (!dev->radio_hw_enable) {
3426 b43info(dev->wl, "The hardware RF-kill button "
3427 "still turns the radio physically off. "
3428 "Press the button to turn it on.\n");
3429 }
3430 } else {
ef1a628d 3431 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
fda9abcf
MB		 3432 b43info(dev->wl, "Radio turned off by software\n");
3433 }
3434 }
3435
d10d0e57
MB		 3436out_mac_enable:
3437 b43_mac_enable(dev);
3438out_unlock_mutex:
e4d6b795
MB		 3439 mutex_unlock(&wl->mutex);
3440
3441 return err;
3442}
3443
c7ab5ef9
JB		 3444static void b43_update_basic_rates(struct b43_wldev *dev, u64 brates)
3445{
3446 struct ieee80211_supported_band *sband =
3447 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3448 struct ieee80211_rate *rate;
3449 int i;
3450 u16 basic, direct, offset, basic_offset, rateptr;
3451
3452 for (i = 0; i < sband->n_bitrates; i++) {
3453 rate = &sband->bitrates[i];
3454
3455 if (b43_is_cck_rate(rate->hw_value)) {
3456 direct = B43_SHM_SH_CCKDIRECT;
3457 basic = B43_SHM_SH_CCKBASIC;
3458 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3459 offset &= 0xF;
3460 } else {
3461 direct = B43_SHM_SH_OFDMDIRECT;
3462 basic = B43_SHM_SH_OFDMBASIC;
3463 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3464 offset &= 0xF;
3465 }
3466
3467 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3468
3469 if (b43_is_cck_rate(rate->hw_value)) {
3470 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3471 basic_offset &= 0xF;
3472 } else {
3473 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3474 basic_offset &= 0xF;
3475 }
3476
3477 /*
3478 * Get the pointer that we need to point to
3479 * from the direct map
3480 */
3481 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3482 direct + 2 * basic_offset);
3483 /* and write it to the basic map */
3484 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3485 rateptr);
3486 }
3487}
3488
3489static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3490 struct ieee80211_vif *vif,
3491 struct ieee80211_bss_conf *conf,
3492 u32 changed)
3493{
3494 struct b43_wl *wl = hw_to_b43_wl(hw);
3495 struct b43_wldev *dev;
c7ab5ef9
JB		 3496
3497 mutex_lock(&wl->mutex);
3498
3499 dev = wl->current_dev;
d10d0e57 3500 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3501 goto out_unlock_mutex;
c7ab5ef9
JB		 3502 b43_mac_suspend(dev);
3503
3504 if (changed & BSS_CHANGED_BASIC_RATES)
3505 b43_update_basic_rates(dev, conf->basic_rates);
3506
3507 if (changed & BSS_CHANGED_ERP_SLOT) {
3508 if (conf->use_short_slot)
3509 b43_short_slot_timing_enable(dev);
3510 else
3511 b43_short_slot_timing_disable(dev);
3512 }
3513
3514 b43_mac_enable(dev);
d10d0e57 3515out_unlock_mutex:
c7ab5ef9
JB		 3516 mutex_unlock(&wl->mutex);
3517
3518 return;
3519}
3520
40faacc4 3521static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4150c572
JB		 3522 const u8 *local_addr, const u8 *addr,
3523 struct ieee80211_key_conf *key)
e4d6b795
MB		 3524{
3525 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3526 struct b43_wldev *dev;
e4d6b795
MB		 3527 u8 algorithm;
3528 u8 index;
c6dfc9a8 3529 int err;
e4d6b795
MB		 3530
3531 if (modparam_nohwcrypt)
3532 return -ENOSPC; /* User disabled HW-crypto */
3533
c6dfc9a8 3534 mutex_lock(&wl->mutex);
e808e586
MB		 3535 spin_lock_irq(&wl->irq_lock);
3536 write_lock(&wl->tx_lock);
3537 /* Why do we need all this locking here?
3538 * mutex -> Every config operation must take it.
3539 * irq_lock -> We modify the dev->key array, which is accessed
3540 * in the IRQ handlers.
3541 * tx_lock -> We modify the dev->key array, which is accessed
3542 * in the TX handler.
3543 */
c6dfc9a8
MB		 3544
3545 dev = wl->current_dev;
3546 err = -ENODEV;
3547 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3548 goto out_unlock;
3549
68217832
MB		 3550 if (dev->fw.pcm_request_failed) {
3551 /* We don't have firmware for the crypto engine.
3552 * Must use software-crypto. */
3553 err = -EOPNOTSUPP;
3554 goto out_unlock;
3555 }
3556
c6dfc9a8 3557 err = -EINVAL;
e4d6b795 3558 switch (key->alg) {
e4d6b795 3559 case ALG_WEP:
e808e586 3560 if (key->keylen == LEN_WEP40)
e4d6b795
MB		 3561 algorithm = B43_SEC_ALGO_WEP40;
3562 else
3563 algorithm = B43_SEC_ALGO_WEP104;
3564 break;
3565 case ALG_TKIP:
3566 algorithm = B43_SEC_ALGO_TKIP;
3567 break;
3568 case ALG_CCMP:
3569 algorithm = B43_SEC_ALGO_AES;
3570 break;
3571 default:
3572 B43_WARN_ON(1);
c6dfc9a8 3573 goto out_unlock;
e4d6b795 3574 }
e4d6b795
MB		 3575 index = (u8) (key->keyidx);
3576 if (index > 3)
e4d6b795 3577 goto out_unlock;
e4d6b795
MB		 3578
3579 switch (cmd) {
3580 case SET_KEY:
3581 if (algorithm == B43_SEC_ALGO_TKIP) {
3582 /* FIXME: No TKIP hardware encryption for now. */
3583 err = -EOPNOTSUPP;
3584 goto out_unlock;
3585 }
3586
e808e586
MB		 3587 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3588 /* Pairwise key with an assigned MAC address. */
e4d6b795
MB		 3589 err = b43_key_write(dev, -1, algorithm,
3590 key->key, key->keylen, addr, key);
e808e586
MB		 3591 } else {
3592 /* Group key */
3593 err = b43_key_write(dev, index, algorithm,
3594 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3595 }
3596 if (err)
3597 goto out_unlock;
3598
3599 if (algorithm == B43_SEC_ALGO_WEP40 ||
3600 algorithm == B43_SEC_ALGO_WEP104) {
3601 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3602 } else {
3603 b43_hf_write(dev,
3604 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3605 }
3606 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3607 break;
3608 case DISABLE_KEY: {
3609 err = b43_key_clear(dev, key->hw_key_idx);
3610 if (err)
3611 goto out_unlock;
3612 break;
3613 }
3614 default:
3615 B43_WARN_ON(1);
3616 }
9cf7f247 3617
e4d6b795 3618out_unlock:
e4d6b795
MB		 3619 if (!err) {
3620 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3621 "mac: %pM\n",
e4d6b795 3622 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
e174961c 3623 addr);
9cf7f247 3624 b43_dump_keymemory(dev);
e4d6b795 3625 }
e808e586
MB		 3626 write_unlock(&wl->tx_lock);
3627 spin_unlock_irq(&wl->irq_lock);
9cf7f247
MB		 3628 mutex_unlock(&wl->mutex);
3629
e4d6b795
MB		 3630 return err;
3631}
3632
40faacc4
MB		 3633static void b43_op_configure_filter(struct ieee80211_hw *hw,
3634 unsigned int changed, unsigned int *fflags,
3635 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 3636{
3637 struct b43_wl *wl = hw_to_b43_wl(hw);
3638 struct b43_wldev *dev = wl->current_dev;
3639 unsigned long flags;
3640
4150c572
JB		 3641 if (!dev) {
3642 *fflags = 0;
e4d6b795 3643 return;
e4d6b795 3644 }
4150c572
JB		 3645
3646 spin_lock_irqsave(&wl->irq_lock, flags);
3647 *fflags &= FIF_PROMISC_IN_BSS |
3648 FIF_ALLMULTI |
3649 FIF_FCSFAIL |
3650 FIF_PLCPFAIL |
3651 FIF_CONTROL |
3652 FIF_OTHER_BSS |
3653 FIF_BCN_PRBRESP_PROMISC;
3654
3655 changed &= FIF_PROMISC_IN_BSS |
3656 FIF_ALLMULTI |
3657 FIF_FCSFAIL |
3658 FIF_PLCPFAIL |
3659 FIF_CONTROL |
3660 FIF_OTHER_BSS |
3661 FIF_BCN_PRBRESP_PROMISC;
3662
3663 wl->filter_flags = *fflags;
3664
3665 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3666 b43_adjust_opmode(dev);
e4d6b795
MB		 3667 spin_unlock_irqrestore(&wl->irq_lock, flags);
3668}
3669
40faacc4 3670static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 3671 struct ieee80211_vif *vif,
40faacc4 3672 struct ieee80211_if_conf *conf)
e4d6b795
MB		 3673{
3674 struct b43_wl *wl = hw_to_b43_wl(hw);
3675 struct b43_wldev *dev = wl->current_dev;
3676 unsigned long flags;
3677
3678 if (!dev)
3679 return -ENODEV;
3680 mutex_lock(&wl->mutex);
3681 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 3682 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 3683 if (conf->bssid)
3684 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3685 else
3686 memset(wl->bssid, 0, ETH_ALEN);
3687 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
05c914fe
JB		 3688 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3689 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
9d139c81 3690 B43_WARN_ON(vif->type != wl->if_type);
9d139c81
JB		 3691 if (conf->changed & IEEE80211_IFCC_BEACON)
3692 b43_update_templates(wl);
05c914fe 3693 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
9d139c81
JB		 3694 if (conf->changed & IEEE80211_IFCC_BEACON)
3695 b43_update_templates(wl);
e4d6b795 3696 }
4150c572 3697 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3698 }
3699 spin_unlock_irqrestore(&wl->irq_lock, flags);
3700 mutex_unlock(&wl->mutex);
3701
3702 return 0;
3703}
3704
3705/* Locking: wl->mutex */
3706static void b43_wireless_core_stop(struct b43_wldev *dev)
3707{
3708 struct b43_wl *wl = dev->wl;
3709 unsigned long flags;
3710
3711 if (b43_status(dev) < B43_STAT_STARTED)
3712 return;
a19d12d7
SB		 3713
3714 /* Disable and sync interrupts. We must do this before than
3715 * setting the status to INITIALIZED, as the interrupt handler
3716 * won't care about IRQs then. */
3717 spin_lock_irqsave(&wl->irq_lock, flags);
3718 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3719 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3720 spin_unlock_irqrestore(&wl->irq_lock, flags);
3721 b43_synchronize_irq(dev);
3722
21a75d77 3723 write_lock_irqsave(&wl->tx_lock, flags);
e4d6b795 3724 b43_set_status(dev, B43_STAT_INITIALIZED);
21a75d77 3725 write_unlock_irqrestore(&wl->tx_lock, flags);
e4d6b795 3726
5100d5ac 3727 b43_pio_stop(dev);
e4d6b795
MB		 3728 mutex_unlock(&wl->mutex);
3729 /* Must unlock as it would otherwise deadlock. No races here.
3730 * Cancel the possibly running self-rearming periodic work. */
3731 cancel_delayed_work_sync(&dev->periodic_work);
3732 mutex_lock(&wl->mutex);
3733
e4d6b795
MB		 3734 b43_mac_suspend(dev);
3735 free_irq(dev->dev->irq, dev);
3736 b43dbg(wl, "Wireless interface stopped\n");
3737}
3738
3739/* Locking: wl->mutex */
3740static int b43_wireless_core_start(struct b43_wldev *dev)
3741{
3742 int err;
3743
3744 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3745
3746 drain_txstatus_queue(dev);
3747 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3748 IRQF_SHARED, KBUILD_MODNAME, dev);
3749 if (err) {
3750 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3751 goto out;
3752 }
3753
3754 /* We are ready to run. */
3755 b43_set_status(dev, B43_STAT_STARTED);
3756
3757 /* Start data flow (TX/RX). */
3758 b43_mac_enable(dev);
3759 b43_interrupt_enable(dev, dev->irq_savedstate);
e4d6b795
MB		 3760
3761 /* Start maintainance work */
3762 b43_periodic_tasks_setup(dev);
3763
3764 b43dbg(dev->wl, "Wireless interface started\n");
3765 out:
3766 return err;
3767}
3768
3769/* Get PHY and RADIO versioning numbers */
3770static int b43_phy_versioning(struct b43_wldev *dev)
3771{
3772 struct b43_phy *phy = &dev->phy;
3773 u32 tmp;
3774 u8 analog_type;
3775 u8 phy_type;
3776 u8 phy_rev;
3777 u16 radio_manuf;
3778 u16 radio_ver;
3779 u16 radio_rev;
3780 int unsupported = 0;
3781
3782 /* Get PHY versioning */
3783 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3784 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3785 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3786 phy_rev = (tmp & B43_PHYVER_VERSION);
3787 switch (phy_type) {
3788 case B43_PHYTYPE_A:
3789 if (phy_rev >= 4)
3790 unsupported = 1;
3791 break;
3792 case B43_PHYTYPE_B:
3793 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3794 && phy_rev != 7)
3795 unsupported = 1;
3796 break;
3797 case B43_PHYTYPE_G:
013978b6 3798 if (phy_rev > 9)
e4d6b795
MB		 3799 unsupported = 1;
3800 break;
d5c71e46
MB		 3801#ifdef CONFIG_B43_NPHY
3802 case B43_PHYTYPE_N:
3803 if (phy_rev > 1)
3804 unsupported = 1;
3805 break;
3806#endif
e4d6b795
MB		 3807 default:
3808 unsupported = 1;
3809 };
3810 if (unsupported) {
3811 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3812 "(Analog %u, Type %u, Revision %u)\n",
3813 analog_type, phy_type, phy_rev);
3814 return -EOPNOTSUPP;
3815 }
3816 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3817 analog_type, phy_type, phy_rev);
3818
3819 /* Get RADIO versioning */
3820 if (dev->dev->bus->chip_id == 0x4317) {
3821 if (dev->dev->bus->chip_rev == 0)
3822 tmp = 0x3205017F;
3823 else if (dev->dev->bus->chip_rev == 1)
3824 tmp = 0x4205017F;
3825 else
3826 tmp = 0x5205017F;
3827 } else {
3828 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3829 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3830 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3831 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3832 }
3833 radio_manuf = (tmp & 0x00000FFF);
3834 radio_ver = (tmp & 0x0FFFF000) >> 12;
3835 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3836 if (radio_manuf != 0x17F /* Broadcom */)
3837 unsupported = 1;
e4d6b795
MB		 3838 switch (phy_type) {
3839 case B43_PHYTYPE_A:
3840 if (radio_ver != 0x2060)
3841 unsupported = 1;
3842 if (radio_rev != 1)
3843 unsupported = 1;
3844 if (radio_manuf != 0x17F)
3845 unsupported = 1;
3846 break;
3847 case B43_PHYTYPE_B:
3848 if ((radio_ver & 0xFFF0) != 0x2050)
3849 unsupported = 1;
3850 break;
3851 case B43_PHYTYPE_G:
3852 if (radio_ver != 0x2050)
3853 unsupported = 1;
3854 break;
96c755a3 3855 case B43_PHYTYPE_N:
243dcfcc 3856 if (radio_ver != 0x2055)
96c755a3
MB		 3857 unsupported = 1;
3858 break;
e4d6b795
MB		 3859 default:
3860 B43_WARN_ON(1);
3861 }
3862 if (unsupported) {
3863 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3864 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3865 radio_manuf, radio_ver, radio_rev);
3866 return -EOPNOTSUPP;
3867 }
3868 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3869 radio_manuf, radio_ver, radio_rev);
3870
3871 phy->radio_manuf = radio_manuf;
3872 phy->radio_ver = radio_ver;
3873 phy->radio_rev = radio_rev;
3874
3875 phy->analog = analog_type;
3876 phy->type = phy_type;
3877 phy->rev = phy_rev;
3878
3879 return 0;
3880}
3881
3882static void setup_struct_phy_for_init(struct b43_wldev *dev,
3883 struct b43_phy *phy)
3884{
e4d6b795 3885 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 3886 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 3887 /* PHY TX errors counter. */
3888 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
e4d6b795
MB		 3889}
3890
3891static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3892{
aa6c7ae2
MB		 3893 dev->dfq_valid = 0;
3894
6a724d68
MB		 3895 /* Assume the radio is enabled. If it's not enabled, the state will
3896 * immediately get fixed on the first periodic work run. */
3897 dev->radio_hw_enable = 1;
e4d6b795
MB		 3898
3899 /* Stats */
3900 memset(&dev->stats, 0, sizeof(dev->stats));
3901
3902 setup_struct_phy_for_init(dev, &dev->phy);
3903
3904 /* IRQ related flags */
3905 dev->irq_reason = 0;
3906 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3907 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3908
3909 dev->mac_suspended = 1;
3910
3911 /* Noise calculation context */
3912 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3913}
3914
3915static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3916{
3917 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 3918 u64 hf;
e4d6b795 3919
1855ba78
MB		 3920 if (!modparam_btcoex)
3921 return;
95de2841 3922 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 3923 return;
3924 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3925 return;
3926
3927 hf = b43_hf_read(dev);
95de2841 3928 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 3929 hf |= B43_HF_BTCOEXALT;
3930 else
3931 hf |= B43_HF_BTCOEX;
3932 b43_hf_write(dev, hf);
e4d6b795
MB		 3933}
3934
3935static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 3936{
3937 if (!modparam_btcoex)
3938 return;
3939 //TODO
e4d6b795
MB		 3940}
3941
3942static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3943{
3944#ifdef CONFIG_SSB_DRIVER_PCICORE
3945 struct ssb_bus *bus = dev->dev->bus;
3946 u32 tmp;
3947
3948 if (bus->pcicore.dev &&
3949 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3950 bus->pcicore.dev->id.revision <= 5) {
3951 /* IMCFGLO timeouts workaround. */
3952 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3953 tmp &= ~SSB_IMCFGLO_REQTO;
3954 tmp &= ~SSB_IMCFGLO_SERTO;
3955 switch (bus->bustype) {
3956 case SSB_BUSTYPE_PCI:
3957 case SSB_BUSTYPE_PCMCIA:
3958 tmp |= 0x32;
3959 break;
3960 case SSB_BUSTYPE_SSB:
3961 tmp |= 0x53;
3962 break;
3963 }
3964 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3965 }
3966#endif /* CONFIG_SSB_DRIVER_PCICORE */
3967}
3968
d59f720d
MB		 3969static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3970{
3971 u16 pu_delay;
3972
3973 /* The time value is in microseconds. */
3974 if (dev->phy.type == B43_PHYTYPE_A)
3975 pu_delay = 3700;
3976 else
3977 pu_delay = 1050;
05c914fe 3978 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 3979 pu_delay = 500;
3980 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3981 pu_delay = max(pu_delay, (u16)2400);
3982
3983 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3984}
3985
3986/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3987static void b43_set_pretbtt(struct b43_wldev *dev)
3988{
3989 u16 pretbtt;
3990
3991 /* The time value is in microseconds. */
05c914fe 3992 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 3993 pretbtt = 2;
3994 } else {
3995 if (dev->phy.type == B43_PHYTYPE_A)
3996 pretbtt = 120;
3997 else
3998 pretbtt = 250;
3999 }
4000 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4001 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4002}
4003
e4d6b795
MB		 4004/* Shutdown a wireless core */
4005/* Locking: wl->mutex */
4006static void b43_wireless_core_exit(struct b43_wldev *dev)
4007{
1f7d87b0 4008 u32 macctl;
e4d6b795
MB		 4009
4010 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
4011 if (b43_status(dev) != B43_STAT_INITIALIZED)
4012 return;
4013 b43_set_status(dev, B43_STAT_UNINIT);
4014
1f7d87b0
MB		 4015 /* Stop the microcode PSM. */
4016 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4017 macctl &= ~B43_MACCTL_PSM_RUN;
4018 macctl |= B43_MACCTL_PSM_JMP0;
4019 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4020
3506e0c4
RW		 4021 if (!dev->suspend_in_progress) {
4022 b43_leds_exit(dev);
b844eba2 4023 b43_rng_exit(dev->wl);
3506e0c4 4024 }
e4d6b795 4025 b43_dma_free(dev);
5100d5ac 4026 b43_pio_free(dev);
e4d6b795 4027 b43_chip_exit(dev);
cb24f57f 4028 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4029 if (dev->wl->current_beacon) {
4030 dev_kfree_skb_any(dev->wl->current_beacon);
4031 dev->wl->current_beacon = NULL;
4032 }
4033
e4d6b795
MB		 4034 ssb_device_disable(dev->dev, 0);
4035 ssb_bus_may_powerdown(dev->dev->bus);
4036}
4037
4038/* Initialize a wireless core */
4039static int b43_wireless_core_init(struct b43_wldev *dev)
4040{
4041 struct b43_wl *wl = dev->wl;
4042 struct ssb_bus *bus = dev->dev->bus;
4043 struct ssb_sprom *sprom = &bus->sprom;
4044 struct b43_phy *phy = &dev->phy;
4045 int err;
a259d6a4
MB		 4046 u64 hf;
4047 u32 tmp;
e4d6b795
MB		 4048
4049 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4050
4051 err = ssb_bus_powerup(bus, 0);
4052 if (err)
4053 goto out;
4054 if (!ssb_device_is_enabled(dev->dev)) {
4055 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4056 b43_wireless_core_reset(dev, tmp);
4057 }
4058
fb11137a 4059 /* Reset all data structures. */
e4d6b795 4060 setup_struct_wldev_for_init(dev);
fb11137a 4061 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4062
4063 /* Enable IRQ routing to this device. */
4064 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4065
4066 b43_imcfglo_timeouts_workaround(dev);
4067 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4068 if (phy->ops->prepare_hardware) {
4069 err = phy->ops->prepare_hardware(dev);
ef1a628d 4070 if (err)
fb11137a 4071 goto err_busdown;
ef1a628d 4072 }
e4d6b795
MB		 4073 err = b43_chip_init(dev);
4074 if (err)
fb11137a 4075 goto err_busdown;
e4d6b795
MB		 4076 b43_shm_write16(dev, B43_SHM_SHARED,
4077 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4078 hf = b43_hf_read(dev);
4079 if (phy->type == B43_PHYTYPE_G) {
4080 hf |= B43_HF_SYMW;
4081 if (phy->rev == 1)
4082 hf |= B43_HF_GDCW;
95de2841 4083 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 4084 hf |= B43_HF_OFDMPABOOST;
4085 } else if (phy->type == B43_PHYTYPE_B) {
4086 hf |= B43_HF_SYMW;
4087 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4088 hf &= ~B43_HF_GDCW;
4089 }
4090 b43_hf_write(dev, hf);
4091
74cfdba7
MB		 4092 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4093 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4094 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4095 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4096
4097 /* Disable sending probe responses from firmware.
4098 * Setting the MaxTime to one usec will always trigger
4099 * a timeout, so we never send any probe resp.
4100 * A timeout of zero is infinite. */
4101 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4102
4103 b43_rate_memory_init(dev);
5042c507 4104 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4105
4106 /* Minimum Contention Window */
4107 if (phy->type == B43_PHYTYPE_B) {
4108 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4109 } else {
4110 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4111 }
4112 /* Maximum Contention Window */
4113 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4114
5100d5ac
MB		 4115 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4116 dev->__using_pio_transfers = 1;
4117 err = b43_pio_init(dev);
4118 } else {
4119 dev->__using_pio_transfers = 0;
4120 err = b43_dma_init(dev);
4121 }
e4d6b795
MB		 4122 if (err)
4123 goto err_chip_exit;
03b29773 4124 b43_qos_init(dev);
d59f720d 4125 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4126 b43_bluetooth_coext_enable(dev);
4127
4128 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 4129 b43_upload_card_macaddress(dev);
e4d6b795 4130 b43_security_init(dev);
3506e0c4
RW		 4131 if (!dev->suspend_in_progress)
4132 b43_rng_init(wl);
e4d6b795
MB		 4133
4134 b43_set_status(dev, B43_STAT_INITIALIZED);
4135
3506e0c4
RW		 4136 if (!dev->suspend_in_progress)
4137 b43_leds_init(dev);
1a8d1227 4138out:
e4d6b795
MB		 4139 return err;
4140
ef1a628d 4141err_chip_exit:
e4d6b795 4142 b43_chip_exit(dev);
ef1a628d 4143err_busdown:
e4d6b795
MB		 4144 ssb_bus_may_powerdown(bus);
4145 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4146 return err;
4147}
4148
40faacc4
MB		 4149static int b43_op_add_interface(struct ieee80211_hw *hw,
4150 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4151{
4152 struct b43_wl *wl = hw_to_b43_wl(hw);
4153 struct b43_wldev *dev;
4154 unsigned long flags;
4155 int err = -EOPNOTSUPP;
4150c572
JB		 4156
4157 /* TODO: allow WDS/AP devices to coexist */
4158
05c914fe
JB		 4159 if (conf->type != NL80211_IFTYPE_AP &&
4160 conf->type != NL80211_IFTYPE_MESH_POINT &&
4161 conf->type != NL80211_IFTYPE_STATION &&
4162 conf->type != NL80211_IFTYPE_WDS &&
4163 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4164 return -EOPNOTSUPP;
e4d6b795
MB		 4165
4166 mutex_lock(&wl->mutex);
4150c572 4167 if (wl->operating)
e4d6b795
MB		 4168 goto out_mutex_unlock;
4169
4170 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4171
4172 dev = wl->current_dev;
4150c572 4173 wl->operating = 1;
32bfd35d 4174 wl->vif = conf->vif;
4150c572
JB		 4175 wl->if_type = conf->type;
4176 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4177
4178 spin_lock_irqsave(&wl->irq_lock, flags);
4179 b43_adjust_opmode(dev);
d59f720d
MB		 4180 b43_set_pretbtt(dev);
4181 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 4182 b43_upload_card_macaddress(dev);
4183 spin_unlock_irqrestore(&wl->irq_lock, flags);
4184
4185 err = 0;
4186 out_mutex_unlock:
4187 mutex_unlock(&wl->mutex);
4188
4189 return err;
4190}
4191
40faacc4
MB		 4192static void b43_op_remove_interface(struct ieee80211_hw *hw,
4193 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4194{
4195 struct b43_wl *wl = hw_to_b43_wl(hw);
4196 struct b43_wldev *dev = wl->current_dev;
4197 unsigned long flags;
4198
4199 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4200
4201 mutex_lock(&wl->mutex);
4202
4203 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4204 B43_WARN_ON(wl->vif != conf->vif);
4205 wl->vif = NULL;
4150c572
JB		 4206
4207 wl->operating = 0;
4208
4209 spin_lock_irqsave(&wl->irq_lock, flags);
4210 b43_adjust_opmode(dev);
4211 memset(wl->mac_addr, 0, ETH_ALEN);
4212 b43_upload_card_macaddress(dev);
4213 spin_unlock_irqrestore(&wl->irq_lock, flags);
4214
4215 mutex_unlock(&wl->mutex);
4216}
4217
40faacc4 4218static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4219{
4220 struct b43_wl *wl = hw_to_b43_wl(hw);
4221 struct b43_wldev *dev = wl->current_dev;
4222 int did_init = 0;
923403b8 4223 int err = 0;
1946a2c3 4224 bool do_rfkill_exit = 0;
4150c572 4225
7be1bb6b
MB		 4226 /* Kill all old instance specific information to make sure
4227 * the card won't use it in the short timeframe between start
4228 * and mac80211 reconfiguring it. */
4229 memset(wl->bssid, 0, ETH_ALEN);
4230 memset(wl->mac_addr, 0, ETH_ALEN);
4231 wl->filter_flags = 0;
4232 wl->radiotap_enabled = 0;
e6f5b934 4233 b43_qos_clear(wl);
6b4bec01
MB		 4234 wl->beacon0_uploaded = 0;
4235 wl->beacon1_uploaded = 0;
4236 wl->beacon_templates_virgin = 1;
7be1bb6b 4237
1a8d1227
LF		 4238 /* First register RFkill.
4239 * LEDs that are registered later depend on it. */
4240 b43_rfkill_init(dev);
4241
4150c572
JB		 4242 mutex_lock(&wl->mutex);
4243
e4d6b795
MB		 4244 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4245 err = b43_wireless_core_init(dev);
1946a2c3
MB		 4246 if (err) {
4247 do_rfkill_exit = 1;
e4d6b795 4248 goto out_mutex_unlock;
1946a2c3 4249 }
e4d6b795
MB		 4250 did_init = 1;
4251 }
4150c572 4252
e4d6b795
MB		 4253 if (b43_status(dev) < B43_STAT_STARTED) {
4254 err = b43_wireless_core_start(dev);
4255 if (err) {
4256 if (did_init)
4257 b43_wireless_core_exit(dev);
1946a2c3 4258 do_rfkill_exit = 1;
e4d6b795
MB		 4259 goto out_mutex_unlock;
4260 }
4261 }
4262
4150c572 4263 out_mutex_unlock:
e4d6b795
MB		 4264 mutex_unlock(&wl->mutex);
4265
1946a2c3
MB		 4266 if (do_rfkill_exit)
4267 b43_rfkill_exit(dev);
4268
e4d6b795
MB		 4269 return err;
4270}
4271
40faacc4 4272static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4273{
4274 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4275 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4276
1a8d1227 4277 b43_rfkill_exit(dev);
a82d9922 4278 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4279
e4d6b795 4280 mutex_lock(&wl->mutex);
4150c572
JB		 4281 if (b43_status(dev) >= B43_STAT_STARTED)
4282 b43_wireless_core_stop(dev);
4283 b43_wireless_core_exit(dev);
e4d6b795 4284 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4285
4286 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4287}
4288
17741cdc
JB		 4289static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4290 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4291{
4292 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4293 unsigned long flags;
e66fee6a 4294
d4df6f1a 4295 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 4296 b43_update_templates(wl);
d4df6f1a 4297 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4298
4299 return 0;
4300}
4301
38968d09
JB		 4302static void b43_op_sta_notify(struct ieee80211_hw *hw,
4303 struct ieee80211_vif *vif,
4304 enum sta_notify_cmd notify_cmd,
17741cdc 4305 struct ieee80211_sta *sta)
38968d09
JB		 4306{
4307 struct b43_wl *wl = hw_to_b43_wl(hw);
4308
4309 B43_WARN_ON(!vif || wl->vif != vif);
4310}
4311
e4d6b795 4312static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4313 .tx = b43_op_tx,
4314 .conf_tx = b43_op_conf_tx,
4315 .add_interface = b43_op_add_interface,
4316 .remove_interface = b43_op_remove_interface,
4317 .config = b43_op_config,
c7ab5ef9 4318 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4319 .config_interface = b43_op_config_interface,
4320 .configure_filter = b43_op_configure_filter,
4321 .set_key = b43_op_set_key,
4322 .get_stats = b43_op_get_stats,
4323 .get_tx_stats = b43_op_get_tx_stats,
4324 .start = b43_op_start,
4325 .stop = b43_op_stop,
e66fee6a 4326 .set_tim = b43_op_beacon_set_tim,
38968d09 4327 .sta_notify = b43_op_sta_notify,
e4d6b795
MB		 4328};
4329
4330/* Hard-reset the chip. Do not call this directly.
4331 * Use b43_controller_restart()
4332 */
4333static void b43_chip_reset(struct work_struct *work)
4334{
4335 struct b43_wldev *dev =
4336 container_of(work, struct b43_wldev, restart_work);
4337 struct b43_wl *wl = dev->wl;
4338 int err = 0;
4339 int prev_status;
4340
4341 mutex_lock(&wl->mutex);
4342
4343 prev_status = b43_status(dev);
4344 /* Bring the device down... */
4345 if (prev_status >= B43_STAT_STARTED)
4346 b43_wireless_core_stop(dev);
4347 if (prev_status >= B43_STAT_INITIALIZED)
4348 b43_wireless_core_exit(dev);
4349
4350 /* ...and up again. */
4351 if (prev_status >= B43_STAT_INITIALIZED) {
4352 err = b43_wireless_core_init(dev);
4353 if (err)
4354 goto out;
4355 }
4356 if (prev_status >= B43_STAT_STARTED) {
4357 err = b43_wireless_core_start(dev);
4358 if (err) {
4359 b43_wireless_core_exit(dev);
4360 goto out;
4361 }
4362 }
3bf0a32e
MB		 4363out:
4364 if (err)
4365 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4366 mutex_unlock(&wl->mutex);
4367 if (err)
4368 b43err(wl, "Controller restart FAILED\n");
4369 else
4370 b43info(wl, "Controller restarted\n");
4371}
4372
bb1eeff1 4373static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4374 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4375{
4376 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4377
bb1eeff1
MB		 4378 if (have_2ghz_phy)
4379 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4380 if (dev->phy.type == B43_PHYTYPE_N) {
4381 if (have_5ghz_phy)
4382 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4383 } else {
4384 if (have_5ghz_phy)
4385 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4386 }
96c755a3 4387
bb1eeff1
MB		 4388 dev->phy.supports_2ghz = have_2ghz_phy;
4389 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4390
4391 return 0;
4392}
4393
4394static void b43_wireless_core_detach(struct b43_wldev *dev)
4395{
4396 /* We release firmware that late to not be required to re-request
4397 * is all the time when we reinit the core. */
4398 b43_release_firmware(dev);
fb11137a 4399 b43_phy_free(dev);
e4d6b795
MB		 4400}
4401
4402static int b43_wireless_core_attach(struct b43_wldev *dev)
4403{
4404 struct b43_wl *wl = dev->wl;
4405 struct ssb_bus *bus = dev->dev->bus;
4406 struct pci_dev *pdev = bus->host_pci;
4407 int err;
96c755a3 4408 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4409 u32 tmp;
4410
4411 /* Do NOT do any device initialization here.
4412 * Do it in wireless_core_init() instead.
4413 * This function is for gathering basic information about the HW, only.
4414 * Also some structs may be set up here. But most likely you want to have
4415 * that in core_init(), too.
4416 */
4417
4418 err = ssb_bus_powerup(bus, 0);
4419 if (err) {
4420 b43err(wl, "Bus powerup failed\n");
4421 goto out;
4422 }
4423 /* Get the PHY type. */
4424 if (dev->dev->id.revision >= 5) {
4425 u32 tmshigh;
4426
4427 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4428 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4429 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4430 } else
96c755a3 4431 B43_WARN_ON(1);
e4d6b795 4432
96c755a3 4433 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4434 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4435 b43_wireless_core_reset(dev, tmp);
4436
4437 err = b43_phy_versioning(dev);
4438 if (err)
21954c36 4439 goto err_powerdown;
e4d6b795
MB		 4440 /* Check if this device supports multiband. */
4441 if (!pdev ||
4442 (pdev->device != 0x4312 &&
4443 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4444 /* No multiband support. */
96c755a3
MB		 4445 have_2ghz_phy = 0;
4446 have_5ghz_phy = 0;
e4d6b795
MB		 4447 switch (dev->phy.type) {
4448 case B43_PHYTYPE_A:
96c755a3 4449 have_5ghz_phy = 1;
e4d6b795
MB		 4450 break;
4451 case B43_PHYTYPE_G:
96c755a3
MB		 4452 case B43_PHYTYPE_N:
4453 have_2ghz_phy = 1;
e4d6b795
MB		 4454 break;
4455 default:
4456 B43_WARN_ON(1);
4457 }
4458 }
96c755a3
MB		 4459 if (dev->phy.type == B43_PHYTYPE_A) {
4460 /* FIXME */
4461 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4462 err = -EOPNOTSUPP;
4463 goto err_powerdown;
4464 }
2e35af14
MB		 4465 if (1 /* disable A-PHY */) {
4466 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4467 if (dev->phy.type != B43_PHYTYPE_N) {
4468 have_2ghz_phy = 1;
4469 have_5ghz_phy = 0;
4470 }
4471 }
4472
fb11137a
MB		 4473 err = b43_phy_allocate(dev);
4474 if (err)
4475 goto err_powerdown;
4476
96c755a3 4477 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4478 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4479 b43_wireless_core_reset(dev, tmp);
4480
4481 err = b43_validate_chipaccess(dev);
4482 if (err)
fb11137a 4483 goto err_phy_free;
bb1eeff1 4484 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4485 if (err)
fb11137a 4486 goto err_phy_free;
e4d6b795
MB		 4487
4488 /* Now set some default "current_dev" */
4489 if (!wl->current_dev)
4490 wl->current_dev = dev;
4491 INIT_WORK(&dev->restart_work, b43_chip_reset);
4492
cb24f57f 4493 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4494 ssb_device_disable(dev->dev, 0);
4495 ssb_bus_may_powerdown(bus);
4496
4497out:
4498 return err;
4499
fb11137a
MB		 4500err_phy_free:
4501 b43_phy_free(dev);
e4d6b795
MB		 4502err_powerdown:
4503 ssb_bus_may_powerdown(bus);
4504 return err;
4505}
4506
4507static void b43_one_core_detach(struct ssb_device *dev)
4508{
4509 struct b43_wldev *wldev;
4510 struct b43_wl *wl;
4511
3bf0a32e
MB		 4512 /* Do not cancel ieee80211-workqueue based work here.
4513 * See comment in b43_remove(). */
4514
e4d6b795
MB		 4515 wldev = ssb_get_drvdata(dev);
4516 wl = wldev->wl;
e4d6b795
MB		 4517 b43_debugfs_remove_device(wldev);
4518 b43_wireless_core_detach(wldev);
4519 list_del(&wldev->list);
4520 wl->nr_devs--;
4521 ssb_set_drvdata(dev, NULL);
4522 kfree(wldev);
4523}
4524
4525static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4526{
4527 struct b43_wldev *wldev;
4528 struct pci_dev *pdev;
4529 int err = -ENOMEM;
4530
4531 if (!list_empty(&wl->devlist)) {
4532 /* We are not the first core on this chip. */
4533 pdev = dev->bus->host_pci;
4534 /* Only special chips support more than one wireless
4535 * core, although some of the other chips have more than
4536 * one wireless core as well. Check for this and
4537 * bail out early.
4538 */
4539 if (!pdev ||
4540 ((pdev->device != 0x4321) &&
4541 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4542 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4543 return -ENODEV;
4544 }
4545 }
4546
4547 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4548 if (!wldev)
4549 goto out;
4550
4551 wldev->dev = dev;
4552 wldev->wl = wl;
4553 b43_set_status(wldev, B43_STAT_UNINIT);
4554 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4555 tasklet_init(&wldev->isr_tasklet,
4556 (void (*)(unsigned long))b43_interrupt_tasklet,
4557 (unsigned long)wldev);
e4d6b795
MB		 4558 INIT_LIST_HEAD(&wldev->list);
4559
4560 err = b43_wireless_core_attach(wldev);
4561 if (err)
4562 goto err_kfree_wldev;
4563
4564 list_add(&wldev->list, &wl->devlist);
4565 wl->nr_devs++;
4566 ssb_set_drvdata(dev, wldev);
4567 b43_debugfs_add_device(wldev);
4568
4569 out:
4570 return err;
4571
4572 err_kfree_wldev:
4573 kfree(wldev);
4574 return err;
4575}
4576
9fc38458
MB		 4577#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4578 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4579 (pdev->device == _device) && \
4580 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4581 (pdev->subsystem_device == _subdevice) )
4582
e4d6b795
MB		 4583static void b43_sprom_fixup(struct ssb_bus *bus)
4584{
1855ba78
MB		 4585 struct pci_dev *pdev;
4586
e4d6b795
MB		 4587 /* boardflags workarounds */
4588 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4589 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4590 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4591 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4592 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4593 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4594 if (bus->bustype == SSB_BUSTYPE_PCI) {
4595 pdev = bus->host_pci;
9fc38458 4596 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4597 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4598 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4599 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4600 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4601 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4602 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4603 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4604 }
e4d6b795
MB		 4605}
4606
4607static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4608{
4609 struct ieee80211_hw *hw = wl->hw;
4610
4611 ssb_set_devtypedata(dev, NULL);
4612 ieee80211_free_hw(hw);
4613}
4614
4615static int b43_wireless_init(struct ssb_device *dev)
4616{
4617 struct ssb_sprom *sprom = &dev->bus->sprom;
4618 struct ieee80211_hw *hw;
4619 struct b43_wl *wl;
4620 int err = -ENOMEM;
4621
4622 b43_sprom_fixup(dev->bus);
4623
4624 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4625 if (!hw) {
4626 b43err(NULL, "Could not allocate ieee80211 device\n");
4627 goto out;
4628 }
4629
4630 /* fill hw info */
605a0bd6 4631 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4632 IEEE80211_HW_SIGNAL_DBM |
4633 IEEE80211_HW_NOISE_DBM;
4634
f59ac048
LR		 4635 hw->wiphy->interface_modes =
4636 BIT(NL80211_IFTYPE_AP) |
4637 BIT(NL80211_IFTYPE_MESH_POINT) |
4638 BIT(NL80211_IFTYPE_STATION) |
4639 BIT(NL80211_IFTYPE_WDS) |
4640 BIT(NL80211_IFTYPE_ADHOC);
4641
e6f5b934 4642 hw->queues = b43_modparam_qos ? 4 : 1;
e6a9854b 4643 hw->max_rates = 2;
e4d6b795 4644 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4645 if (is_valid_ether_addr(sprom->et1mac))
4646 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4647 else
95de2841 4648 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 4649
4650 /* Get and initialize struct b43_wl */
4651 wl = hw_to_b43_wl(hw);
4652 memset(wl, 0, sizeof(*wl));
4653 wl->hw = hw;
4654 spin_lock_init(&wl->irq_lock);
21a75d77 4655 rwlock_init(&wl->tx_lock);
e4d6b795 4656 spin_lock_init(&wl->leds_lock);
280d0e16 4657 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4658 mutex_init(&wl->mutex);
4659 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4660 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4661 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
e4d6b795
MB		 4662
4663 ssb_set_devtypedata(dev, wl);
4664 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4665 err = 0;
4666 out:
4667 return err;
4668}
4669
4670static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4671{
4672 struct b43_wl *wl;
4673 int err;
4674 int first = 0;
4675
4676 wl = ssb_get_devtypedata(dev);
4677 if (!wl) {
4678 /* Probing the first core. Must setup common struct b43_wl */
4679 first = 1;
4680 err = b43_wireless_init(dev);
4681 if (err)
4682 goto out;
4683 wl = ssb_get_devtypedata(dev);
4684 B43_WARN_ON(!wl);
4685 }
4686 err = b43_one_core_attach(dev, wl);
4687 if (err)
4688 goto err_wireless_exit;
4689
4690 if (first) {
4691 err = ieee80211_register_hw(wl->hw);
4692 if (err)
4693 goto err_one_core_detach;
4694 }
4695
4696 out:
4697 return err;
4698
4699 err_one_core_detach:
4700 b43_one_core_detach(dev);
4701 err_wireless_exit:
4702 if (first)
4703 b43_wireless_exit(dev, wl);
4704 return err;
4705}
4706
4707static void b43_remove(struct ssb_device *dev)
4708{
4709 struct b43_wl *wl = ssb_get_devtypedata(dev);
4710 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4711
3bf0a32e
MB		 4712 /* We must cancel any work here before unregistering from ieee80211,
4713 * as the ieee80211 unreg will destroy the workqueue. */
4714 cancel_work_sync(&wldev->restart_work);
4715
e4d6b795
MB		 4716 B43_WARN_ON(!wl);
4717 if (wl->current_dev == wldev)
4718 ieee80211_unregister_hw(wl->hw);
4719
4720 b43_one_core_detach(dev);
4721
4722 if (list_empty(&wl->devlist)) {
4723 /* Last core on the chip unregistered.
4724 * We can destroy common struct b43_wl.
4725 */
4726 b43_wireless_exit(dev, wl);
4727 }
4728}
4729
4730/* Perform a hardware reset. This can be called from any context. */
4731void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4732{
4733 /* Must avoid requeueing, if we are in shutdown. */
4734 if (b43_status(dev) < B43_STAT_INITIALIZED)
4735 return;
4736 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4737 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4738}
4739
4740#ifdef CONFIG_PM
4741
4742static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4743{
4744 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4745 struct b43_wl *wl = wldev->wl;
4746
4747 b43dbg(wl, "Suspending...\n");
4748
4749 mutex_lock(&wl->mutex);
3506e0c4 4750 wldev->suspend_in_progress = true;
e4d6b795
MB		 4751 wldev->suspend_init_status = b43_status(wldev);
4752 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4753 b43_wireless_core_stop(wldev);
4754 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4755 b43_wireless_core_exit(wldev);
4756 mutex_unlock(&wl->mutex);
4757
4758 b43dbg(wl, "Device suspended.\n");
4759
4760 return 0;
4761}
4762
4763static int b43_resume(struct ssb_device *dev)
4764{
4765 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4766 struct b43_wl *wl = wldev->wl;
4767 int err = 0;
4768
4769 b43dbg(wl, "Resuming...\n");
4770
4771 mutex_lock(&wl->mutex);
4772 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4773 err = b43_wireless_core_init(wldev);
4774 if (err) {
4775 b43err(wl, "Resume failed at core init\n");
4776 goto out;
4777 }
4778 }
4779 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4780 err = b43_wireless_core_start(wldev);
4781 if (err) {
3506e0c4 4782 b43_leds_exit(wldev);
b844eba2 4783 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4784 b43_wireless_core_exit(wldev);
4785 b43err(wl, "Resume failed at core start\n");
4786 goto out;
4787 }
4788 }
e4d6b795 4789 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4790 out:
4791 wldev->suspend_in_progress = false;
4792 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4793 return err;
4794}
4795
4796#else /* CONFIG_PM */
4797# define b43_suspend NULL
4798# define b43_resume NULL
4799#endif /* CONFIG_PM */
4800
4801static struct ssb_driver b43_ssb_driver = {
4802 .name = KBUILD_MODNAME,
4803 .id_table = b43_ssb_tbl,
4804 .probe = b43_probe,
4805 .remove = b43_remove,
4806 .suspend = b43_suspend,
4807 .resume = b43_resume,
4808};
4809
26bc783f
MB		 4810static void b43_print_driverinfo(void)
4811{
4812 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4813 *feat_leds = "", *feat_rfkill = "";
4814
4815#ifdef CONFIG_B43_PCI_AUTOSELECT
4816 feat_pci = "P";
4817#endif
4818#ifdef CONFIG_B43_PCMCIA
4819 feat_pcmcia = "M";
4820#endif
4821#ifdef CONFIG_B43_NPHY
4822 feat_nphy = "N";
4823#endif
4824#ifdef CONFIG_B43_LEDS
4825 feat_leds = "L";
4826#endif
4827#ifdef CONFIG_B43_RFKILL
4828 feat_rfkill = "R";
4829#endif
4830 printk(KERN_INFO "Broadcom 43xx driver loaded "
4831 "[ Features: %s%s%s%s%s, Firmware-ID: "
4832 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4833 feat_pci, feat_pcmcia, feat_nphy,
4834 feat_leds, feat_rfkill);
4835}
4836
e4d6b795
MB		 4837static int __init b43_init(void)
4838{
4839 int err;
4840
4841 b43_debugfs_init();
4842 err = b43_pcmcia_init();
4843 if (err)
4844 goto err_dfs_exit;
4845 err = ssb_driver_register(&b43_ssb_driver);
4846 if (err)
4847 goto err_pcmcia_exit;
26bc783f 4848 b43_print_driverinfo();
e4d6b795
MB		 4849
4850 return err;
4851
4852err_pcmcia_exit:
4853 b43_pcmcia_exit();
4854err_dfs_exit:
4855 b43_debugfs_exit();
4856 return err;
4857}
4858
4859static void __exit b43_exit(void)
4860{
4861 ssb_driver_unregister(&b43_ssb_driver);
4862 b43_pcmcia_exit();
4863 b43_debugfs_exit();
4864}
4865
4866module_init(b43_init)
4867module_exit(b43_exit)
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