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b43: use enum for firmware header format
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
3dbba8e2
AH		 11 SDIO support
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
e4d6b795
MB		 14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
21
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
26
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
31
32*/
33
34#include <linux/delay.h>
35#include <linux/init.h>
36#include <linux/moduleparam.h>
37#include <linux/if_arp.h>
38#include <linux/etherdevice.h>
e4d6b795 39#include <linux/firmware.h>
e4d6b795
MB		 40#include <linux/workqueue.h>
41#include <linux/skbuff.h>
96cf49a2 42#include <linux/io.h>
e4d6b795 43#include <linux/dma-mapping.h>
5a0e3ad6 44#include <linux/slab.h>
e4d6b795
MB		 45#include <asm/unaligned.h>
46
47#include "b43.h"
48#include "main.h"
49#include "debugfs.h"
ef1a628d
MB		 50#include "phy_common.h"
51#include "phy_g.h"
3d0da751 52#include "phy_n.h"
e4d6b795 53#include "dma.h"
5100d5ac 54#include "pio.h"
e4d6b795
MB		 55#include "sysfs.h"
56#include "xmit.h"
e4d6b795
MB		 57#include "lo.h"
58#include "pcmcia.h"
3dbba8e2
AH		 59#include "sdio.h"
60#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 61
62MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63MODULE_AUTHOR("Martin Langer");
64MODULE_AUTHOR("Stefano Brivio");
65MODULE_AUTHOR("Michael Buesch");
0136e51e 66MODULE_AUTHOR("Gábor Stefanik");
e4d6b795
MB		 67MODULE_LICENSE("GPL");
68
9c7d99d6 69MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
6021e08d
TG		 70MODULE_FIRMWARE("b43/ucode11.fw");
71MODULE_FIRMWARE("b43/ucode13.fw");
72MODULE_FIRMWARE("b43/ucode14.fw");
73MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 74MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 75MODULE_FIRMWARE("b43/ucode5.fw");
76MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 77
78static int modparam_bad_frames_preempt;
79module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80MODULE_PARM_DESC(bad_frames_preempt,
81 "enable(1) / disable(0) Bad Frames Preemption");
82
e4d6b795
MB		 83static char modparam_fwpostfix[16];
84module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
85MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
86
e4d6b795
MB		 87static int modparam_hwpctl;
88module_param_named(hwpctl, modparam_hwpctl, int, 0444);
89MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
90
91static int modparam_nohwcrypt;
92module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
93MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
94
035d0243 95static int modparam_hwtkip;
96module_param_named(hwtkip, modparam_hwtkip, int, 0444);
97MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
98
403a3a13
MB		 99static int modparam_qos = 1;
100module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 101MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
102
1855ba78
MB		 103static int modparam_btcoex = 1;
104module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 105MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 106
060210f9
MB		 107int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
108module_param_named(verbose, b43_modparam_verbose, int, 0644);
109MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
110
41950bdf 111static int b43_modparam_pio = B43_PIO_DEFAULT;
9e3bd919
LT		 112module_param_named(pio, b43_modparam_pio, int, 0644);
113MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 114
3c65ab62
RM		 115#ifdef CONFIG_B43_BCMA
116static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 117 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
3c65ab62
RM		 118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
121 BCMA_CORETABLE_END
122};
123MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
124#endif
125
aec7ffdf 126#ifdef CONFIG_B43_SSB
e4d6b795
MB		 127static const struct ssb_device_id b43_ssb_tbl[] = {
128 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 138 SSB_DEVTABLE_END
139};
e4d6b795 140MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 141#endif
e4d6b795
MB		 142
143/* Channel and ratetables are shared for all devices.
144 * They can't be const, because ieee80211 puts some precalculated
145 * data in there. This data is the same for all devices, so we don't
146 * get concurrency issues */
147#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 148 { \
149 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
150 .hw_value = (_rateid), \
151 .flags = (_flags), \
e4d6b795 152 }
8318d78a
JB		 153
154/*
155 * NOTE: When changing this, sync with xmit.c's
156 * b43_plcp_get_bitrate_idx_* functions!
157 */
e4d6b795 158static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 159 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
160 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
161 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
162 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
163 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
164 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
165 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
166 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 171};
172
173#define b43_a_ratetable (__b43_ratetable + 4)
174#define b43_a_ratetable_size 8
175#define b43_b_ratetable (__b43_ratetable + 0)
176#define b43_b_ratetable_size 4
177#define b43_g_ratetable (__b43_ratetable + 0)
178#define b43_g_ratetable_size 12
179
bb1eeff1
MB		 180#define CHAN4G(_channel, _freq, _flags) { \
181 .band = IEEE80211_BAND_2GHZ, \
182 .center_freq = (_freq), \
183 .hw_value = (_channel), \
184 .flags = (_flags), \
185 .max_antenna_gain = 0, \
186 .max_power = 30, \
187}
96c755a3 188static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 189 CHAN4G(1, 2412, 0),
190 CHAN4G(2, 2417, 0),
191 CHAN4G(3, 2422, 0),
192 CHAN4G(4, 2427, 0),
193 CHAN4G(5, 2432, 0),
194 CHAN4G(6, 2437, 0),
195 CHAN4G(7, 2442, 0),
196 CHAN4G(8, 2447, 0),
197 CHAN4G(9, 2452, 0),
198 CHAN4G(10, 2457, 0),
199 CHAN4G(11, 2462, 0),
200 CHAN4G(12, 2467, 0),
201 CHAN4G(13, 2472, 0),
202 CHAN4G(14, 2484, 0),
203};
204#undef CHAN4G
205
206#define CHAN5G(_channel, _flags) { \
207 .band = IEEE80211_BAND_5GHZ, \
208 .center_freq = 5000 + (5 * (_channel)), \
209 .hw_value = (_channel), \
210 .flags = (_flags), \
211 .max_antenna_gain = 0, \
212 .max_power = 30, \
213}
214static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
215 CHAN5G(32, 0), CHAN5G(34, 0),
216 CHAN5G(36, 0), CHAN5G(38, 0),
217 CHAN5G(40, 0), CHAN5G(42, 0),
218 CHAN5G(44, 0), CHAN5G(46, 0),
219 CHAN5G(48, 0), CHAN5G(50, 0),
220 CHAN5G(52, 0), CHAN5G(54, 0),
221 CHAN5G(56, 0), CHAN5G(58, 0),
222 CHAN5G(60, 0), CHAN5G(62, 0),
223 CHAN5G(64, 0), CHAN5G(66, 0),
224 CHAN5G(68, 0), CHAN5G(70, 0),
225 CHAN5G(72, 0), CHAN5G(74, 0),
226 CHAN5G(76, 0), CHAN5G(78, 0),
227 CHAN5G(80, 0), CHAN5G(82, 0),
228 CHAN5G(84, 0), CHAN5G(86, 0),
229 CHAN5G(88, 0), CHAN5G(90, 0),
230 CHAN5G(92, 0), CHAN5G(94, 0),
231 CHAN5G(96, 0), CHAN5G(98, 0),
232 CHAN5G(100, 0), CHAN5G(102, 0),
233 CHAN5G(104, 0), CHAN5G(106, 0),
234 CHAN5G(108, 0), CHAN5G(110, 0),
235 CHAN5G(112, 0), CHAN5G(114, 0),
236 CHAN5G(116, 0), CHAN5G(118, 0),
237 CHAN5G(120, 0), CHAN5G(122, 0),
238 CHAN5G(124, 0), CHAN5G(126, 0),
239 CHAN5G(128, 0), CHAN5G(130, 0),
240 CHAN5G(132, 0), CHAN5G(134, 0),
241 CHAN5G(136, 0), CHAN5G(138, 0),
242 CHAN5G(140, 0), CHAN5G(142, 0),
243 CHAN5G(144, 0), CHAN5G(145, 0),
244 CHAN5G(146, 0), CHAN5G(147, 0),
245 CHAN5G(148, 0), CHAN5G(149, 0),
246 CHAN5G(150, 0), CHAN5G(151, 0),
247 CHAN5G(152, 0), CHAN5G(153, 0),
248 CHAN5G(154, 0), CHAN5G(155, 0),
249 CHAN5G(156, 0), CHAN5G(157, 0),
250 CHAN5G(158, 0), CHAN5G(159, 0),
251 CHAN5G(160, 0), CHAN5G(161, 0),
252 CHAN5G(162, 0), CHAN5G(163, 0),
253 CHAN5G(164, 0), CHAN5G(165, 0),
254 CHAN5G(166, 0), CHAN5G(168, 0),
255 CHAN5G(170, 0), CHAN5G(172, 0),
256 CHAN5G(174, 0), CHAN5G(176, 0),
257 CHAN5G(178, 0), CHAN5G(180, 0),
258 CHAN5G(182, 0), CHAN5G(184, 0),
259 CHAN5G(186, 0), CHAN5G(188, 0),
260 CHAN5G(190, 0), CHAN5G(192, 0),
261 CHAN5G(194, 0), CHAN5G(196, 0),
262 CHAN5G(198, 0), CHAN5G(200, 0),
263 CHAN5G(202, 0), CHAN5G(204, 0),
264 CHAN5G(206, 0), CHAN5G(208, 0),
265 CHAN5G(210, 0), CHAN5G(212, 0),
266 CHAN5G(214, 0), CHAN5G(216, 0),
267 CHAN5G(218, 0), CHAN5G(220, 0),
268 CHAN5G(222, 0), CHAN5G(224, 0),
269 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 270};
271
bb1eeff1
MB		 272static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
273 CHAN5G(34, 0), CHAN5G(36, 0),
274 CHAN5G(38, 0), CHAN5G(40, 0),
275 CHAN5G(42, 0), CHAN5G(44, 0),
276 CHAN5G(46, 0), CHAN5G(48, 0),
277 CHAN5G(52, 0), CHAN5G(56, 0),
278 CHAN5G(60, 0), CHAN5G(64, 0),
279 CHAN5G(100, 0), CHAN5G(104, 0),
280 CHAN5G(108, 0), CHAN5G(112, 0),
281 CHAN5G(116, 0), CHAN5G(120, 0),
282 CHAN5G(124, 0), CHAN5G(128, 0),
283 CHAN5G(132, 0), CHAN5G(136, 0),
284 CHAN5G(140, 0), CHAN5G(149, 0),
285 CHAN5G(153, 0), CHAN5G(157, 0),
286 CHAN5G(161, 0), CHAN5G(165, 0),
287 CHAN5G(184, 0), CHAN5G(188, 0),
288 CHAN5G(192, 0), CHAN5G(196, 0),
289 CHAN5G(200, 0), CHAN5G(204, 0),
290 CHAN5G(208, 0), CHAN5G(212, 0),
291 CHAN5G(216, 0),
292};
293#undef CHAN5G
294
295static struct ieee80211_supported_band b43_band_5GHz_nphy = {
296 .band = IEEE80211_BAND_5GHZ,
297 .channels = b43_5ghz_nphy_chantable,
298 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
299 .bitrates = b43_a_ratetable,
300 .n_bitrates = b43_a_ratetable_size,
e4d6b795 301};
8318d78a 302
bb1eeff1
MB		 303static struct ieee80211_supported_band b43_band_5GHz_aphy = {
304 .band = IEEE80211_BAND_5GHZ,
305 .channels = b43_5ghz_aphy_chantable,
306 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
307 .bitrates = b43_a_ratetable,
308 .n_bitrates = b43_a_ratetable_size,
8318d78a 309};
e4d6b795 310
8318d78a 311static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 312 .band = IEEE80211_BAND_2GHZ,
313 .channels = b43_2ghz_chantable,
314 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
315 .bitrates = b43_g_ratetable,
316 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 317};
318
e4d6b795
MB		 319static void b43_wireless_core_exit(struct b43_wldev *dev);
320static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 321static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 322static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 323static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
324 struct ieee80211_vif *vif,
325 struct ieee80211_bss_conf *conf,
326 u32 changed);
e4d6b795
MB		 327
328static int b43_ratelimit(struct b43_wl *wl)
329{
330 if (!wl || !wl->current_dev)
331 return 1;
332 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
333 return 1;
334 /* We are up and running.
335 * Ratelimit the messages to avoid DoS over the net. */
336 return net_ratelimit();
337}
338
339void b43info(struct b43_wl *wl, const char *fmt, ...)
340{
5b736d42 341 struct va_format vaf;
e4d6b795
MB		 342 va_list args;
343
060210f9
MB		 344 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
345 return;
e4d6b795
MB		 346 if (!b43_ratelimit(wl))
347 return;
5b736d42 348
e4d6b795 349 va_start(args, fmt);
5b736d42
JP		 350
351 vaf.fmt = fmt;
352 vaf.va = &args;
353
354 printk(KERN_INFO "b43-%s: %pV",
355 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
356
e4d6b795
MB		 357 va_end(args);
358}
359
360void b43err(struct b43_wl *wl, const char *fmt, ...)
361{
5b736d42 362 struct va_format vaf;
e4d6b795
MB		 363 va_list args;
364
060210f9
MB		 365 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
366 return;
e4d6b795
MB		 367 if (!b43_ratelimit(wl))
368 return;
5b736d42 369
e4d6b795 370 va_start(args, fmt);
5b736d42
JP		 371
372 vaf.fmt = fmt;
373 vaf.va = &args;
374
375 printk(KERN_ERR "b43-%s ERROR: %pV",
376 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
377
e4d6b795
MB		 378 va_end(args);
379}
380
381void b43warn(struct b43_wl *wl, const char *fmt, ...)
382{
5b736d42 383 struct va_format vaf;
e4d6b795
MB		 384 va_list args;
385
060210f9
MB		 386 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
387 return;
e4d6b795
MB		 388 if (!b43_ratelimit(wl))
389 return;
5b736d42 390
e4d6b795 391 va_start(args, fmt);
5b736d42
JP		 392
393 vaf.fmt = fmt;
394 vaf.va = &args;
395
396 printk(KERN_WARNING "b43-%s warning: %pV",
397 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
398
e4d6b795
MB		 399 va_end(args);
400}
401
e4d6b795
MB		 402void b43dbg(struct b43_wl *wl, const char *fmt, ...)
403{
5b736d42 404 struct va_format vaf;
e4d6b795
MB		 405 va_list args;
406
060210f9
MB		 407 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
408 return;
5b736d42 409
e4d6b795 410 va_start(args, fmt);
5b736d42
JP		 411
412 vaf.fmt = fmt;
413 vaf.va = &args;
414
415 printk(KERN_DEBUG "b43-%s debug: %pV",
416 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
417
e4d6b795
MB		 418 va_end(args);
419}
e4d6b795
MB		 420
421static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
422{
423 u32 macctl;
424
425 B43_WARN_ON(offset % 4 != 0);
426
427 macctl = b43_read32(dev, B43_MMIO_MACCTL);
428 if (macctl & B43_MACCTL_BE)
429 val = swab32(val);
430
431 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
432 mmiowb();
433 b43_write32(dev, B43_MMIO_RAM_DATA, val);
434}
435
280d0e16
MB		 436static inline void b43_shm_control_word(struct b43_wldev *dev,
437 u16 routing, u16 offset)
e4d6b795
MB		 438{
439 u32 control;
440
441 /* "offset" is the WORD offset. */
e4d6b795
MB		 442 control = routing;
443 control <<= 16;
444 control |= offset;
445 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
446}
447
69eddc8a 448u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 449{
450 u32 ret;
451
452 if (routing == B43_SHM_SHARED) {
453 B43_WARN_ON(offset & 0x0001);
454 if (offset & 0x0003) {
455 /* Unaligned access */
456 b43_shm_control_word(dev, routing, offset >> 2);
457 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 458 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 459 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 460
280d0e16 461 goto out;
e4d6b795
MB		 462 }
463 offset >>= 2;
464 }
465 b43_shm_control_word(dev, routing, offset);
466 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 467out:
e4d6b795
MB		 468 return ret;
469}
470
69eddc8a 471u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 472{
473 u16 ret;
474
e4d6b795
MB		 475 if (routing == B43_SHM_SHARED) {
476 B43_WARN_ON(offset & 0x0001);
477 if (offset & 0x0003) {
478 /* Unaligned access */
479 b43_shm_control_word(dev, routing, offset >> 2);
480 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
481
280d0e16 482 goto out;
e4d6b795
MB		 483 }
484 offset >>= 2;
485 }
486 b43_shm_control_word(dev, routing, offset);
487 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 488out:
e4d6b795
MB		 489 return ret;
490}
491
69eddc8a 492void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 493{
e4d6b795
MB		 494 if (routing == B43_SHM_SHARED) {
495 B43_WARN_ON(offset & 0x0001);
496 if (offset & 0x0003) {
497 /* Unaligned access */
498 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 499 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 500 value & 0xFFFF);
e4d6b795 501 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 502 b43_write16(dev, B43_MMIO_SHM_DATA,
503 (value >> 16) & 0xFFFF);
6bbc321a 504 return;
e4d6b795
MB		 505 }
506 offset >>= 2;
507 }
508 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 509 b43_write32(dev, B43_MMIO_SHM_DATA, value);
510}
511
69eddc8a 512void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 513{
e4d6b795
MB		 514 if (routing == B43_SHM_SHARED) {
515 B43_WARN_ON(offset & 0x0001);
516 if (offset & 0x0003) {
517 /* Unaligned access */
518 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 519 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 520 return;
e4d6b795
MB		 521 }
522 offset >>= 2;
523 }
524 b43_shm_control_word(dev, routing, offset);
e4d6b795 525 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 526}
527
e4d6b795 528/* Read HostFlags */
99da185a 529u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 530{
35f0d354 531 u64 ret;
e4d6b795
MB		 532
533 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
534 ret <<= 16;
35f0d354
MB		 535 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
536 ret <<= 16;
e4d6b795
MB		 537 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
538
539 return ret;
540}
541
542/* Write HostFlags */
35f0d354 543void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 544{
35f0d354
MB		 545 u16 lo, mi, hi;
546
547 lo = (value & 0x00000000FFFFULL);
548 mi = (value & 0x0000FFFF0000ULL) >> 16;
549 hi = (value & 0xFFFF00000000ULL) >> 32;
550 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
551 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
552 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 553}
554
403a3a13
MB		 555/* Read the firmware capabilities bitmask (Opensource firmware only) */
556static u16 b43_fwcapa_read(struct b43_wldev *dev)
557{
558 B43_WARN_ON(!dev->fw.opensource);
559 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
560}
561
3ebbbb56 562void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 563{
3ebbbb56
MB		 564 u32 low, high;
565
21d889d4 566 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 567
568 /* The hardware guarantees us an atomic read, if we
569 * read the low register first. */
570 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
571 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
572
573 *tsf = high;
574 *tsf <<= 32;
575 *tsf |= low;
e4d6b795
MB		 576}
577
578static void b43_time_lock(struct b43_wldev *dev)
579{
580 u32 macctl;
581
582 macctl = b43_read32(dev, B43_MMIO_MACCTL);
583 macctl |= B43_MACCTL_TBTTHOLD;
584 b43_write32(dev, B43_MMIO_MACCTL, macctl);
585 /* Commit the write */
586 b43_read32(dev, B43_MMIO_MACCTL);
587}
588
589static void b43_time_unlock(struct b43_wldev *dev)
590{
591 u32 macctl;
592
593 macctl = b43_read32(dev, B43_MMIO_MACCTL);
594 macctl &= ~B43_MACCTL_TBTTHOLD;
595 b43_write32(dev, B43_MMIO_MACCTL, macctl);
596 /* Commit the write */
597 b43_read32(dev, B43_MMIO_MACCTL);
598}
599
600static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
601{
3ebbbb56
MB		 602 u32 low, high;
603
21d889d4 604 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 605
606 low = tsf;
607 high = (tsf >> 32);
608 /* The hardware guarantees us an atomic write, if we
609 * write the low register first. */
610 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
611 mmiowb();
612 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
613 mmiowb();
e4d6b795
MB		 614}
615
616void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
617{
618 b43_time_lock(dev);
619 b43_tsf_write_locked(dev, tsf);
620 b43_time_unlock(dev);
621}
622
623static
99da185a 624void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 625{
626 static const u8 zero_addr[ETH_ALEN] = { 0 };
627 u16 data;
628
629 if (!mac)
630 mac = zero_addr;
631
632 offset |= 0x0020;
633 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
634
635 data = mac[0];
636 data |= mac[1] << 8;
637 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
638 data = mac[2];
639 data |= mac[3] << 8;
640 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
641 data = mac[4];
642 data |= mac[5] << 8;
643 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
644}
645
646static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
647{
648 const u8 *mac;
649 const u8 *bssid;
650 u8 mac_bssid[ETH_ALEN * 2];
651 int i;
652 u32 tmp;
653
654 bssid = dev->wl->bssid;
655 mac = dev->wl->mac_addr;
656
657 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
658
659 memcpy(mac_bssid, mac, ETH_ALEN);
660 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
661
662 /* Write our MAC address and BSSID to template ram */
663 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
664 tmp = (u32) (mac_bssid[i + 0]);
665 tmp |= (u32) (mac_bssid[i + 1]) << 8;
666 tmp |= (u32) (mac_bssid[i + 2]) << 16;
667 tmp |= (u32) (mac_bssid[i + 3]) << 24;
668 b43_ram_write(dev, 0x20 + i, tmp);
669 }
670}
671
4150c572 672static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 673{
e4d6b795 674 b43_write_mac_bssid_templates(dev);
4150c572 675 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 676}
677
678static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
679{
680 /* slot_time is in usec. */
b6c3f5be
LF		 681 /* This test used to exit for all but a G PHY. */
682 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 683 return;
b6c3f5be
LF		 684 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
685 /* Shared memory location 0x0010 is the slot time and should be
686 * set to slot_time; however, this register is initially 0 and changing
687 * the value adversely affects the transmit rate for BCM4311
688 * devices. Until this behavior is unterstood, delete this step
689 *
690 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
691 */
e4d6b795
MB		 692}
693
694static void b43_short_slot_timing_enable(struct b43_wldev *dev)
695{
696 b43_set_slot_time(dev, 9);
e4d6b795
MB		 697}
698
699static void b43_short_slot_timing_disable(struct b43_wldev *dev)
700{
701 b43_set_slot_time(dev, 20);
e4d6b795
MB		 702}
703
e4d6b795 704/* DummyTransmission function, as documented on
2f19c287 705 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 706 */
2f19c287 707void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 708{
709 struct b43_phy *phy = &dev->phy;
710 unsigned int i, max_loop;
711 u16 value;
712 u32 buffer[5] = {
713 0x00000000,
714 0x00D40000,
715 0x00000000,
716 0x01000000,
717 0x00000000,
718 };
719
2f19c287 720 if (ofdm) {
e4d6b795
MB		 721 max_loop = 0x1E;
722 buffer[0] = 0x000201CC;
2f19c287 723 } else {
e4d6b795
MB		 724 max_loop = 0xFA;
725 buffer[0] = 0x000B846E;
e4d6b795
MB		 726 }
727
728 for (i = 0; i < 5; i++)
729 b43_ram_write(dev, i * 4, buffer[i]);
730
e4d6b795 731 b43_write16(dev, 0x0568, 0x0000);
21d889d4 732 if (dev->dev->core_rev < 11)
2f19c287
GS		 733 b43_write16(dev, 0x07C0, 0x0000);
734 else
735 b43_write16(dev, 0x07C0, 0x0100);
736 value = (ofdm ? 0x41 : 0x40);
e4d6b795 737 b43_write16(dev, 0x050C, value);
2f19c287
GS		 738 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
739 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 740 b43_write16(dev, 0x0508, 0x0000);
741 b43_write16(dev, 0x050A, 0x0000);
742 b43_write16(dev, 0x054C, 0x0000);
743 b43_write16(dev, 0x056A, 0x0014);
744 b43_write16(dev, 0x0568, 0x0826);
745 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 746 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
747 //SPEC TODO
748 }
749
750 switch (phy->type) {
751 case B43_PHYTYPE_N:
752 b43_write16(dev, 0x0502, 0x00D0);
753 break;
754 case B43_PHYTYPE_LP:
755 b43_write16(dev, 0x0502, 0x0050);
756 break;
757 default:
758 b43_write16(dev, 0x0502, 0x0030);
759 }
e4d6b795
MB		 760
761 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
762 b43_radio_write16(dev, 0x0051, 0x0017);
763 for (i = 0x00; i < max_loop; i++) {
764 value = b43_read16(dev, 0x050E);
765 if (value & 0x0080)
766 break;
767 udelay(10);
768 }
769 for (i = 0x00; i < 0x0A; i++) {
770 value = b43_read16(dev, 0x050E);
771 if (value & 0x0400)
772 break;
773 udelay(10);
774 }
1d280ddc 775 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 776 value = b43_read16(dev, 0x0690);
777 if (!(value & 0x0100))
778 break;
779 udelay(10);
780 }
781 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
782 b43_radio_write16(dev, 0x0051, 0x0037);
783}
784
785static void key_write(struct b43_wldev *dev,
99da185a 786 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 787{
788 unsigned int i;
789 u32 offset;
790 u16 value;
791 u16 kidx;
792
793 /* Key index/algo block */
794 kidx = b43_kidx_to_fw(dev, index);
795 value = ((kidx << 4) | algorithm);
796 b43_shm_write16(dev, B43_SHM_SHARED,
797 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
798
799 /* Write the key to the Key Table Pointer offset */
800 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
801 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
802 value = key[i];
803 value |= (u16) (key[i + 1]) << 8;
804 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
805 }
806}
807
99da185a 808static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 809{
810 u32 addrtmp[2] = { 0, 0, };
66d2d089 811 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 812
813 if (b43_new_kidx_api(dev))
66d2d089 814 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 815
66d2d089
MB		 816 B43_WARN_ON(index < pairwise_keys_start);
817 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 818 * Physical mac 0 is mapped to physical key 4 or 8, depending
819 * on the firmware version.
820 * So we must adjust the index here.
821 */
66d2d089
MB		 822 index -= pairwise_keys_start;
823 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 824
825 if (addr) {
826 addrtmp[0] = addr[0];
827 addrtmp[0] |= ((u32) (addr[1]) << 8);
828 addrtmp[0] |= ((u32) (addr[2]) << 16);
829 addrtmp[0] |= ((u32) (addr[3]) << 24);
830 addrtmp[1] = addr[4];
831 addrtmp[1] |= ((u32) (addr[5]) << 8);
832 }
833
66d2d089
MB		 834 /* Receive match transmitter address (RCMTA) mechanism */
835 b43_shm_write32(dev, B43_SHM_RCMTA,
836 (index * 2) + 0, addrtmp[0]);
837 b43_shm_write16(dev, B43_SHM_RCMTA,
838 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 839}
840
035d0243 841/* The ucode will use phase1 key with TEK key to decrypt rx packets.
842 * When a packet is received, the iv32 is checked.
843 * - if it doesn't the packet is returned without modification (and software
844 * decryption can be done). That's what happen when iv16 wrap.
845 * - if it does, the rc4 key is computed, and decryption is tried.
846 * Either it will success and B43_RX_MAC_DEC is returned,
847 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
848 * and the packet is not usable (it got modified by the ucode).
849 * So in order to never have B43_RX_MAC_DECERR, we should provide
850 * a iv32 and phase1key that match. Because we drop packets in case of
851 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
852 * packets will be lost without higher layer knowing (ie no resync possible
853 * until next wrap).
854 *
855 * NOTE : this should support 50 key like RCMTA because
856 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
857 */
858static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
859 u16 *phase1key)
860{
861 unsigned int i;
862 u32 offset;
863 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
864
865 if (!modparam_hwtkip)
866 return;
867
868 if (b43_new_kidx_api(dev))
869 pairwise_keys_start = B43_NR_GROUP_KEYS;
870
871 B43_WARN_ON(index < pairwise_keys_start);
872 /* We have four default TX keys and possibly four default RX keys.
873 * Physical mac 0 is mapped to physical key 4 or 8, depending
874 * on the firmware version.
875 * So we must adjust the index here.
876 */
877 index -= pairwise_keys_start;
878 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
879
880 if (b43_debug(dev, B43_DBG_KEYS)) {
881 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
882 index, iv32);
883 }
884 /* Write the key to the RX tkip shared mem */
885 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
886 for (i = 0; i < 10; i += 2) {
887 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
888 phase1key ? phase1key[i / 2] : 0);
889 }
890 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
892}
893
894static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 895 struct ieee80211_vif *vif,
896 struct ieee80211_key_conf *keyconf,
897 struct ieee80211_sta *sta,
898 u32 iv32, u16 *phase1key)
035d0243 899{
900 struct b43_wl *wl = hw_to_b43_wl(hw);
901 struct b43_wldev *dev;
902 int index = keyconf->hw_key_idx;
903
904 if (B43_WARN_ON(!modparam_hwtkip))
905 return;
906
96869a39
MB		 907 /* This is only called from the RX path through mac80211, where
908 * our mutex is already locked. */
909 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 910 dev = wl->current_dev;
96869a39 911 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 912
913 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
914
915 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 916 /* only pairwise TKIP keys are supported right now */
917 if (WARN_ON(!sta))
96869a39 918 return;
b3fbdcf4 919 keymac_write(dev, index, sta->addr);
035d0243 920}
921
e4d6b795
MB		 922static void do_key_write(struct b43_wldev *dev,
923 u8 index, u8 algorithm,
99da185a 924 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 925{
926 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 927 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 928
929 if (b43_new_kidx_api(dev))
66d2d089 930 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 931
66d2d089 932 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 933 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
934
66d2d089 935 if (index >= pairwise_keys_start)
e4d6b795 936 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 937 if (algorithm == B43_SEC_ALGO_TKIP) {
938 /*
939 * We should provide an initial iv32, phase1key pair.
940 * We could start with iv32=0 and compute the corresponding
941 * phase1key, but this means calling ieee80211_get_tkip_key
942 * with a fake skb (or export other tkip function).
943 * Because we are lazy we hope iv32 won't start with
944 * 0xffffffff and let's b43_op_update_tkip_key provide a
945 * correct pair.
946 */
947 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
948 } else if (index >= pairwise_keys_start) /* clear it */
949 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 950 if (key)
951 memcpy(buf, key, key_len);
952 key_write(dev, index, algorithm, buf);
66d2d089 953 if (index >= pairwise_keys_start)
e4d6b795
MB		 954 keymac_write(dev, index, mac_addr);
955
956 dev->key[index].algorithm = algorithm;
957}
958
959static int b43_key_write(struct b43_wldev *dev,
960 int index, u8 algorithm,
99da185a
JD		 961 const u8 *key, size_t key_len,
962 const u8 *mac_addr,
e4d6b795
MB		 963 struct ieee80211_key_conf *keyconf)
964{
965 int i;
66d2d089 966 int pairwise_keys_start;
e4d6b795 967
035d0243 968 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
969 * - Temporal Encryption Key (128 bits)
970 * - Temporal Authenticator Tx MIC Key (64 bits)
971 * - Temporal Authenticator Rx MIC Key (64 bits)
972 *
973 * Hardware only store TEK
974 */
975 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
976 key_len = 16;
e4d6b795
MB		 977 if (key_len > B43_SEC_KEYSIZE)
978 return -EINVAL;
66d2d089 979 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 980 /* Check that we don't already have this key. */
981 B43_WARN_ON(dev->key[i].keyconf == keyconf);
982 }
983 if (index < 0) {
e808e586 984 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 985 if (b43_new_kidx_api(dev))
66d2d089 986 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 987 else
66d2d089
MB		 988 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
989 for (i = pairwise_keys_start;
990 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
991 i++) {
992 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 993 if (!dev->key[i].keyconf) {
994 /* found empty */
995 index = i;
996 break;
997 }
998 }
999 if (index < 0) {
e808e586 1000 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1001 return -ENOSPC;
1002 }
1003 } else
1004 B43_WARN_ON(index > 3);
1005
1006 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1007 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1008 /* Default RX key */
1009 B43_WARN_ON(mac_addr);
1010 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1011 }
1012 keyconf->hw_key_idx = index;
1013 dev->key[index].keyconf = keyconf;
1014
1015 return 0;
1016}
1017
1018static int b43_key_clear(struct b43_wldev *dev, int index)
1019{
66d2d089 1020 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1021 return -EINVAL;
1022 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1023 NULL, B43_SEC_KEYSIZE, NULL);
1024 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1025 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1026 NULL, B43_SEC_KEYSIZE, NULL);
1027 }
1028 dev->key[index].keyconf = NULL;
1029
1030 return 0;
1031}
1032
1033static void b43_clear_keys(struct b43_wldev *dev)
1034{
66d2d089 1035 int i, count;
e4d6b795 1036
66d2d089
MB		 1037 if (b43_new_kidx_api(dev))
1038 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1039 else
1040 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1041 for (i = 0; i < count; i++)
e4d6b795
MB		 1042 b43_key_clear(dev, i);
1043}
1044
9cf7f247
MB		 1045static void b43_dump_keymemory(struct b43_wldev *dev)
1046{
66d2d089 1047 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1048 u8 mac[ETH_ALEN];
1049 u16 algo;
1050 u32 rcmta0;
1051 u16 rcmta1;
1052 u64 hf;
1053 struct b43_key *key;
1054
1055 if (!b43_debug(dev, B43_DBG_KEYS))
1056 return;
1057
1058 hf = b43_hf_read(dev);
1059 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1060 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1061 if (b43_new_kidx_api(dev)) {
1062 pairwise_keys_start = B43_NR_GROUP_KEYS;
1063 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1064 } else {
1065 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1066 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1067 }
1068 for (index = 0; index < count; index++) {
9cf7f247
MB		 1069 key = &(dev->key[index]);
1070 printk(KERN_DEBUG "Key slot %02u: %s",
1071 index, (key->keyconf == NULL) ? " " : "*");
1072 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1073 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1074 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1075 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1076 }
1077
1078 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1079 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1080 printk(" Algo: %04X/%02X", algo, key->algorithm);
1081
66d2d089 1082 if (index >= pairwise_keys_start) {
035d0243 1083 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1084 printk(" TKIP: ");
1085 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1086 for (i = 0; i < 14; i += 2) {
1087 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1088 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1089 }
1090 }
9cf7f247 1091 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1092 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1093 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1094 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1095 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1096 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1097 printk(" MAC: %pM", mac);
9cf7f247
MB		 1098 } else
1099 printk(" DEFAULT KEY");
1100 printk("\n");
1101 }
1102}
1103
e4d6b795
MB		 1104void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1105{
1106 u32 macctl;
1107 u16 ucstat;
1108 bool hwps;
1109 bool awake;
1110 int i;
1111
1112 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1113 (ps_flags & B43_PS_DISABLED));
1114 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1115
1116 if (ps_flags & B43_PS_ENABLED) {
1117 hwps = 1;
1118 } else if (ps_flags & B43_PS_DISABLED) {
1119 hwps = 0;
1120 } else {
1121 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1122 // and thus is not an AP and we are associated, set bit 25
1123 }
1124 if (ps_flags & B43_PS_AWAKE) {
1125 awake = 1;
1126 } else if (ps_flags & B43_PS_ASLEEP) {
1127 awake = 0;
1128 } else {
1129 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1130 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1131 // successful, set bit26
1132 }
1133
1134/* FIXME: For now we force awake-on and hwps-off */
1135 hwps = 0;
1136 awake = 1;
1137
1138 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1139 if (hwps)
1140 macctl |= B43_MACCTL_HWPS;
1141 else
1142 macctl &= ~B43_MACCTL_HWPS;
1143 if (awake)
1144 macctl |= B43_MACCTL_AWAKE;
1145 else
1146 macctl &= ~B43_MACCTL_AWAKE;
1147 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1148 /* Commit write */
1149 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1150 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1151 /* Wait for the microcode to wake up. */
1152 for (i = 0; i < 100; i++) {
1153 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1154 B43_SHM_SH_UCODESTAT);
1155 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1156 break;
1157 udelay(10);
1158 }
1159 }
1160}
1161
42c9a458 1162#ifdef CONFIG_B43_BCMA
49173592 1163static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1164{
49173592 1165 u32 flags;
42c9a458 1166
49173592
RM		 1167 /* Put PHY into reset */
1168 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1169 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1170 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1171 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1172 udelay(2);
1173
1174 /* Take PHY out of reset */
1175 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1176 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1177 flags |= BCMA_IOCTL_FGC;
1178 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1179 udelay(1);
1180
1181 /* Do not force clock anymore */
1182 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1183 flags &= ~BCMA_IOCTL_FGC;
1184 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1185 udelay(1);
1186}
42c9a458 1187
49173592
RM		 1188static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1189{
1190 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1191 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1192 b43_bcma_phy_reset(dev);
1193 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
42c9a458
RM		 1194}
1195#endif
1196
4da909e7 1197static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1198{
d48ae5c8 1199 struct ssb_device *sdev = dev->dev->sdev;
e4d6b795 1200 u32 tmslow;
4da909e7 1201 u32 flags = 0;
e4d6b795 1202
4da909e7
RM		 1203 if (gmode)
1204 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1205 flags |= B43_TMSLOW_PHYCLKEN;
1206 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1207 if (dev->phy.type == B43_PHYTYPE_N)
1208 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1209 b43_device_enable(dev, flags);
e4d6b795
MB		 1210 msleep(2); /* Wait for the PLL to turn on. */
1211
1212 /* Now take the PHY out of Reset again */
d48ae5c8 1213 tmslow = ssb_read32(sdev, SSB_TMSLOW);
e4d6b795
MB		 1214 tmslow |= SSB_TMSLOW_FGC;
1215 tmslow &= ~B43_TMSLOW_PHYRESET;
d48ae5c8
RM		 1216 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1217 ssb_read32(sdev, SSB_TMSLOW); /* flush */
e4d6b795
MB		 1218 msleep(1);
1219 tmslow &= ~SSB_TMSLOW_FGC;
d48ae5c8
RM		 1220 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1221 ssb_read32(sdev, SSB_TMSLOW); /* flush */
e4d6b795 1222 msleep(1);
1495298d
RM		 1223}
1224
4da909e7 1225void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1226{
1227 u32 macctl;
1228
6cbab0d9 1229 switch (dev->dev->bus_type) {
42c9a458
RM		 1230#ifdef CONFIG_B43_BCMA
1231 case B43_BUS_BCMA:
1232 b43_bcma_wireless_core_reset(dev, gmode);
1233 break;
1234#endif
6cbab0d9
RM		 1235#ifdef CONFIG_B43_SSB
1236 case B43_BUS_SSB:
1237 b43_ssb_wireless_core_reset(dev, gmode);
1238 break;
1239#endif
1240 }
e4d6b795 1241
fb11137a
MB		 1242 /* Turn Analog ON, but only if we already know the PHY-type.
1243 * This protects against very early setup where we don't know the
1244 * PHY-type, yet. wireless_core_reset will be called once again later,
1245 * when we know the PHY-type. */
1246 if (dev->phy.ops)
cb24f57f 1247 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1248
1249 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1250 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1251 if (gmode)
e4d6b795
MB		 1252 macctl |= B43_MACCTL_GMODE;
1253 macctl |= B43_MACCTL_IHR_ENABLED;
1254 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1255}
1256
1257static void handle_irq_transmit_status(struct b43_wldev *dev)
1258{
1259 u32 v0, v1;
1260 u16 tmp;
1261 struct b43_txstatus stat;
1262
1263 while (1) {
1264 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1265 if (!(v0 & 0x00000001))
1266 break;
1267 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1268
1269 stat.cookie = (v0 >> 16);
1270 stat.seq = (v1 & 0x0000FFFF);
1271 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1272 tmp = (v0 & 0x0000FFFF);
1273 stat.frame_count = ((tmp & 0xF000) >> 12);
1274 stat.rts_count = ((tmp & 0x0F00) >> 8);
1275 stat.supp_reason = ((tmp & 0x001C) >> 2);
1276 stat.pm_indicated = !!(tmp & 0x0080);
1277 stat.intermediate = !!(tmp & 0x0040);
1278 stat.for_ampdu = !!(tmp & 0x0020);
1279 stat.acked = !!(tmp & 0x0002);
1280
1281 b43_handle_txstatus(dev, &stat);
1282 }
1283}
1284
1285static void drain_txstatus_queue(struct b43_wldev *dev)
1286{
1287 u32 dummy;
1288
21d889d4 1289 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1290 return;
1291 /* Read all entries from the microcode TXstatus FIFO
1292 * and throw them away.
1293 */
1294 while (1) {
1295 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1296 if (!(dummy & 0x00000001))
1297 break;
1298 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1299 }
1300}
1301
1302static u32 b43_jssi_read(struct b43_wldev *dev)
1303{
1304 u32 val = 0;
1305
1306 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1307 val <<= 16;
1308 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1309
1310 return val;
1311}
1312
1313static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1314{
1315 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1316 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1317}
1318
1319static void b43_generate_noise_sample(struct b43_wldev *dev)
1320{
1321 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1322 b43_write32(dev, B43_MMIO_MACCMD,
1323 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1324}
1325
1326static void b43_calculate_link_quality(struct b43_wldev *dev)
1327{
1328 /* Top half of Link Quality calculation. */
1329
ef1a628d
MB		 1330 if (dev->phy.type != B43_PHYTYPE_G)
1331 return;
e4d6b795
MB		 1332 if (dev->noisecalc.calculation_running)
1333 return;
e4d6b795
MB		 1334 dev->noisecalc.calculation_running = 1;
1335 dev->noisecalc.nr_samples = 0;
1336
1337 b43_generate_noise_sample(dev);
1338}
1339
1340static void handle_irq_noise(struct b43_wldev *dev)
1341{
ef1a628d 1342 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1343 u16 tmp;
1344 u8 noise[4];
1345 u8 i, j;
1346 s32 average;
1347
1348 /* Bottom half of Link Quality calculation. */
1349
ef1a628d
MB		 1350 if (dev->phy.type != B43_PHYTYPE_G)
1351 return;
1352
98a3b2fe
MB		 1353 /* Possible race condition: It might be possible that the user
1354 * changed to a different channel in the meantime since we
1355 * started the calculation. We ignore that fact, since it's
1356 * not really that much of a problem. The background noise is
1357 * an estimation only anyway. Slightly wrong results will get damped
1358 * by the averaging of the 8 sample rounds. Additionally the
1359 * value is shortlived. So it will be replaced by the next noise
1360 * calculation round soon. */
1361
e4d6b795 1362 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1363 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1364 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1365 noise[2] == 0x7F || noise[3] == 0x7F)
1366 goto generate_new;
1367
1368 /* Get the noise samples. */
1369 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1370 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1371 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1372 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1373 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1375 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1376 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1377 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1378 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1379 dev->noisecalc.nr_samples++;
1380 if (dev->noisecalc.nr_samples == 8) {
1381 /* Calculate the Link Quality by the noise samples. */
1382 average = 0;
1383 for (i = 0; i < 8; i++) {
1384 for (j = 0; j < 4; j++)
1385 average += dev->noisecalc.samples[i][j];
1386 }
1387 average /= (8 * 4);
1388 average *= 125;
1389 average += 64;
1390 average /= 128;
1391 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1392 tmp = (tmp / 128) & 0x1F;
1393 if (tmp >= 8)
1394 average += 2;
1395 else
1396 average -= 25;
1397 if (tmp == 8)
1398 average -= 72;
1399 else
1400 average -= 48;
1401
1402 dev->stats.link_noise = average;
e4d6b795
MB		 1403 dev->noisecalc.calculation_running = 0;
1404 return;
1405 }
98a3b2fe 1406generate_new:
e4d6b795
MB		 1407 b43_generate_noise_sample(dev);
1408}
1409
1410static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1411{
05c914fe 1412 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1413 ///TODO: PS TBTT
1414 } else {
1415 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1416 b43_power_saving_ctl_bits(dev, 0);
1417 }
05c914fe 1418 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1419 dev->dfq_valid = 1;
e4d6b795
MB		 1420}
1421
1422static void handle_irq_atim_end(struct b43_wldev *dev)
1423{
aa6c7ae2
MB		 1424 if (dev->dfq_valid) {
1425 b43_write32(dev, B43_MMIO_MACCMD,
1426 b43_read32(dev, B43_MMIO_MACCMD)
1427 | B43_MACCMD_DFQ_VALID);
1428 dev->dfq_valid = 0;
1429 }
e4d6b795
MB		 1430}
1431
1432static void handle_irq_pmq(struct b43_wldev *dev)
1433{
1434 u32 tmp;
1435
1436 //TODO: AP mode.
1437
1438 while (1) {
1439 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1440 if (!(tmp & 0x00000008))
1441 break;
1442 }
1443 /* 16bit write is odd, but correct. */
1444 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1445}
1446
1447static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1448 const u8 *data, u16 size,
e4d6b795
MB		 1449 u16 ram_offset,
1450 u16 shm_size_offset, u8 rate)
1451{
1452 u32 i, tmp;
1453 struct b43_plcp_hdr4 plcp;
1454
1455 plcp.data = 0;
1456 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1457 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1458 ram_offset += sizeof(u32);
1459 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1460 * So leave the first two bytes of the next write blank.
1461 */
1462 tmp = (u32) (data[0]) << 16;
1463 tmp |= (u32) (data[1]) << 24;
1464 b43_ram_write(dev, ram_offset, tmp);
1465 ram_offset += sizeof(u32);
1466 for (i = 2; i < size; i += sizeof(u32)) {
1467 tmp = (u32) (data[i + 0]);
1468 if (i + 1 < size)
1469 tmp |= (u32) (data[i + 1]) << 8;
1470 if (i + 2 < size)
1471 tmp |= (u32) (data[i + 2]) << 16;
1472 if (i + 3 < size)
1473 tmp |= (u32) (data[i + 3]) << 24;
1474 b43_ram_write(dev, ram_offset + i - 2, tmp);
1475 }
1476 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1477 size + sizeof(struct b43_plcp_hdr6));
1478}
1479
5042c507
MB		 1480/* Check if the use of the antenna that ieee80211 told us to
1481 * use is possible. This will fall back to DEFAULT.
1482 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1483u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1484 u8 antenna_nr)
1485{
1486 u8 antenna_mask;
1487
1488 if (antenna_nr == 0) {
1489 /* Zero means "use default antenna". That's always OK. */
1490 return 0;
1491 }
1492
1493 /* Get the mask of available antennas. */
1494 if (dev->phy.gmode)
0581483a 1495 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1496 else
0581483a 1497 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1498
1499 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1500 /* This antenna is not available. Fall back to default. */
1501 return 0;
1502 }
1503
1504 return antenna_nr;
1505}
1506
5042c507
MB		 1507/* Convert a b43 antenna number value to the PHY TX control value. */
1508static u16 b43_antenna_to_phyctl(int antenna)
1509{
1510 switch (antenna) {
1511 case B43_ANTENNA0:
1512 return B43_TXH_PHY_ANT0;
1513 case B43_ANTENNA1:
1514 return B43_TXH_PHY_ANT1;
1515 case B43_ANTENNA2:
1516 return B43_TXH_PHY_ANT2;
1517 case B43_ANTENNA3:
1518 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1519 case B43_ANTENNA_AUTO0:
1520 case B43_ANTENNA_AUTO1:
5042c507
MB		 1521 return B43_TXH_PHY_ANT01AUTO;
1522 }
1523 B43_WARN_ON(1);
1524 return 0;
1525}
1526
e4d6b795
MB		 1527static void b43_write_beacon_template(struct b43_wldev *dev,
1528 u16 ram_offset,
5042c507 1529 u16 shm_size_offset)
e4d6b795 1530{
47f76ca3 1531 unsigned int i, len, variable_len;
e66fee6a
MB		 1532 const struct ieee80211_mgmt *bcn;
1533 const u8 *ie;
1534 bool tim_found = 0;
5042c507
MB		 1535 unsigned int rate;
1536 u16 ctl;
1537 int antenna;
e039fa4a 1538 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1539
e66fee6a
MB		 1540 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1541 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1542 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1543 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1544
1545 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1546 len, ram_offset, shm_size_offset, rate);
e66fee6a 1547
5042c507 1548 /* Write the PHY TX control parameters. */
0f4ac38b 1549 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1550 antenna = b43_antenna_to_phyctl(antenna);
1551 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1552 /* We can't send beacons with short preamble. Would get PHY errors. */
1553 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1554 ctl &= ~B43_TXH_PHY_ANT;
1555 ctl &= ~B43_TXH_PHY_ENC;
1556 ctl |= antenna;
1557 if (b43_is_cck_rate(rate))
1558 ctl |= B43_TXH_PHY_ENC_CCK;
1559 else
1560 ctl |= B43_TXH_PHY_ENC_OFDM;
1561 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1562
e66fee6a
MB		 1563 /* Find the position of the TIM and the DTIM_period value
1564 * and write them to SHM. */
1565 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1566 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1567 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1568 uint8_t ie_id, ie_len;
1569
1570 ie_id = ie[i];
1571 ie_len = ie[i + 1];
1572 if (ie_id == 5) {
1573 u16 tim_position;
1574 u16 dtim_period;
1575 /* This is the TIM Information Element */
1576
1577 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1578 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1579 break;
1580 /* A valid TIM is at least 4 bytes long. */
1581 if (ie_len < 4)
1582 break;
1583 tim_found = 1;
1584
1585 tim_position = sizeof(struct b43_plcp_hdr6);
1586 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1587 tim_position += i;
1588
1589 dtim_period = ie[i + 3];
1590
1591 b43_shm_write16(dev, B43_SHM_SHARED,
1592 B43_SHM_SH_TIMBPOS, tim_position);
1593 b43_shm_write16(dev, B43_SHM_SHARED,
1594 B43_SHM_SH_DTIMPER, dtim_period);
1595 break;
1596 }
1597 i += ie_len + 2;
1598 }
1599 if (!tim_found) {
04dea136
JB		 1600 /*
1601 * If ucode wants to modify TIM do it behind the beacon, this
1602 * will happen, for example, when doing mesh networking.
1603 */
1604 b43_shm_write16(dev, B43_SHM_SHARED,
1605 B43_SHM_SH_TIMBPOS,
1606 len + sizeof(struct b43_plcp_hdr6));
1607 b43_shm_write16(dev, B43_SHM_SHARED,
1608 B43_SHM_SH_DTIMPER, 0);
1609 }
1610 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1611}
1612
6b4bec01
MB		 1613static void b43_upload_beacon0(struct b43_wldev *dev)
1614{
1615 struct b43_wl *wl = dev->wl;
1616
1617 if (wl->beacon0_uploaded)
1618 return;
1619 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1620 wl->beacon0_uploaded = 1;
1621}
1622
1623static void b43_upload_beacon1(struct b43_wldev *dev)
1624{
1625 struct b43_wl *wl = dev->wl;
1626
1627 if (wl->beacon1_uploaded)
1628 return;
1629 b43_write_beacon_template(dev, 0x468, 0x1A);
1630 wl->beacon1_uploaded = 1;
1631}
1632
c97a4ccc
MB		 1633static void handle_irq_beacon(struct b43_wldev *dev)
1634{
1635 struct b43_wl *wl = dev->wl;
1636 u32 cmd, beacon0_valid, beacon1_valid;
1637
05c914fe
JB		 1638 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1639 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1640 return;
1641
1642 /* This is the bottom half of the asynchronous beacon update. */
1643
1644 /* Ignore interrupt in the future. */
13790728 1645 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1646
1647 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1648 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1649 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1650
1651 /* Schedule interrupt manually, if busy. */
1652 if (beacon0_valid && beacon1_valid) {
1653 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1654 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1655 return;
1656 }
1657
6b4bec01
MB		 1658 if (unlikely(wl->beacon_templates_virgin)) {
1659 /* We never uploaded a beacon before.
1660 * Upload both templates now, but only mark one valid. */
1661 wl->beacon_templates_virgin = 0;
1662 b43_upload_beacon0(dev);
1663 b43_upload_beacon1(dev);
c97a4ccc
MB		 1664 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1665 cmd |= B43_MACCMD_BEACON0_VALID;
1666 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1667 } else {
1668 if (!beacon0_valid) {
1669 b43_upload_beacon0(dev);
1670 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1671 cmd |= B43_MACCMD_BEACON0_VALID;
1672 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1673 } else if (!beacon1_valid) {
1674 b43_upload_beacon1(dev);
1675 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1676 cmd |= B43_MACCMD_BEACON1_VALID;
1677 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1678 }
c97a4ccc
MB		 1679 }
1680}
1681
36dbd954
MB		 1682static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1683{
1684 u32 old_irq_mask = dev->irq_mask;
1685
1686 /* update beacon right away or defer to irq */
1687 handle_irq_beacon(dev);
1688 if (old_irq_mask != dev->irq_mask) {
1689 /* The handler updated the IRQ mask. */
1690 B43_WARN_ON(!dev->irq_mask);
1691 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1692 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1693 } else {
1694 /* Device interrupts are currently disabled. That means
1695 * we just ran the hardirq handler and scheduled the
1696 * IRQ thread. The thread will write the IRQ mask when
1697 * it finished, so there's nothing to do here. Writing
1698 * the mask _here_ would incorrectly re-enable IRQs. */
1699 }
1700 }
1701}
1702
a82d9922
MB		 1703static void b43_beacon_update_trigger_work(struct work_struct *work)
1704{
1705 struct b43_wl *wl = container_of(work, struct b43_wl,
1706 beacon_update_trigger);
1707 struct b43_wldev *dev;
1708
1709 mutex_lock(&wl->mutex);
1710 dev = wl->current_dev;
1711 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1712 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1713 /* wl->mutex is enough. */
1714 b43_do_beacon_update_trigger_work(dev);
1715 mmiowb();
1716 } else {
1717 spin_lock_irq(&wl->hardirq_lock);
1718 b43_do_beacon_update_trigger_work(dev);
1719 mmiowb();
1720 spin_unlock_irq(&wl->hardirq_lock);
1721 }
a82d9922
MB		 1722 }
1723 mutex_unlock(&wl->mutex);
1724}
1725
d4df6f1a 1726/* Asynchronously update the packet templates in template RAM.
36dbd954 1727 * Locking: Requires wl->mutex to be locked. */
9d139c81 1728static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1729{
9d139c81
JB		 1730 struct sk_buff *beacon;
1731
e66fee6a
MB		 1732 /* This is the top half of the ansynchronous beacon update.
1733 * The bottom half is the beacon IRQ.
1734 * Beacon update must be asynchronous to avoid sending an
1735 * invalid beacon. This can happen for example, if the firmware
1736 * transmits a beacon while we are updating it. */
e4d6b795 1737
9d139c81
JB		 1738 /* We could modify the existing beacon and set the aid bit in
1739 * the TIM field, but that would probably require resizing and
1740 * moving of data within the beacon template.
1741 * Simply request a new beacon and let mac80211 do the hard work. */
1742 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1743 if (unlikely(!beacon))
1744 return;
1745
e66fee6a
MB		 1746 if (wl->current_beacon)
1747 dev_kfree_skb_any(wl->current_beacon);
1748 wl->current_beacon = beacon;
1749 wl->beacon0_uploaded = 0;
1750 wl->beacon1_uploaded = 0;
42935eca 1751 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1752}
1753
e4d6b795
MB		 1754static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1755{
1756 b43_time_lock(dev);
21d889d4 1757 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1758 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1759 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1760 } else {
1761 b43_write16(dev, 0x606, (beacon_int >> 6));
1762 b43_write16(dev, 0x610, beacon_int);
1763 }
1764 b43_time_unlock(dev);
a82d9922 1765 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1766}
1767
afa83e23
MB		 1768static void b43_handle_firmware_panic(struct b43_wldev *dev)
1769{
1770 u16 reason;
1771
1772 /* Read the register that contains the reason code for the panic. */
1773 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1774 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1775
1776 switch (reason) {
1777 default:
1778 b43dbg(dev->wl, "The panic reason is unknown.\n");
1779 /* fallthrough */
1780 case B43_FWPANIC_DIE:
1781 /* Do not restart the controller or firmware.
1782 * The device is nonfunctional from now on.
1783 * Restarting would result in this panic to trigger again,
1784 * so we avoid that recursion. */
1785 break;
1786 case B43_FWPANIC_RESTART:
1787 b43_controller_restart(dev, "Microcode panic");
1788 break;
1789 }
1790}
1791
e4d6b795
MB		 1792static void handle_irq_ucode_debug(struct b43_wldev *dev)
1793{
e48b0eeb 1794 unsigned int i, cnt;
53c06856 1795 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1796 __le16 *buf;
1797
1798 /* The proprietary firmware doesn't have this IRQ. */
1799 if (!dev->fw.opensource)
1800 return;
1801
afa83e23
MB		 1802 /* Read the register that contains the reason code for this IRQ. */
1803 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1804
e48b0eeb
MB		 1805 switch (reason) {
1806 case B43_DEBUGIRQ_PANIC:
afa83e23 1807 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1808 break;
1809 case B43_DEBUGIRQ_DUMP_SHM:
1810 if (!B43_DEBUG)
1811 break; /* Only with driver debugging enabled. */
1812 buf = kmalloc(4096, GFP_ATOMIC);
1813 if (!buf) {
1814 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1815 goto out;
1816 }
1817 for (i = 0; i < 4096; i += 2) {
1818 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1819 buf[i / 2] = cpu_to_le16(tmp);
1820 }
1821 b43info(dev->wl, "Shared memory dump:\n");
1822 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1823 16, 2, buf, 4096, 1);
1824 kfree(buf);
1825 break;
1826 case B43_DEBUGIRQ_DUMP_REGS:
1827 if (!B43_DEBUG)
1828 break; /* Only with driver debugging enabled. */
1829 b43info(dev->wl, "Microcode register dump:\n");
1830 for (i = 0, cnt = 0; i < 64; i++) {
1831 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1832 if (cnt == 0)
1833 printk(KERN_INFO);
1834 printk("r%02u: 0x%04X ", i, tmp);
1835 cnt++;
1836 if (cnt == 6) {
1837 printk("\n");
1838 cnt = 0;
1839 }
1840 }
1841 printk("\n");
1842 break;
53c06856
MB		 1843 case B43_DEBUGIRQ_MARKER:
1844 if (!B43_DEBUG)
1845 break; /* Only with driver debugging enabled. */
1846 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1847 B43_MARKER_ID_REG);
1848 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1849 B43_MARKER_LINE_REG);
1850 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1851 "at line number %u\n",
1852 marker_id, marker_line);
1853 break;
e48b0eeb
MB		 1854 default:
1855 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1856 reason);
1857 }
1858out:
afa83e23
MB		 1859 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1860 b43_shm_write16(dev, B43_SHM_SCRATCH,
1861 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1862}
1863
36dbd954 1864static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1865{
1866 u32 reason;
1867 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1868 u32 merged_dma_reason = 0;
21954c36 1869 int i;
e4d6b795 1870
36dbd954
MB		 1871 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1872 return;
e4d6b795
MB		 1873
1874 reason = dev->irq_reason;
1875 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1876 dma_reason[i] = dev->dma_reason[i];
1877 merged_dma_reason |= dma_reason[i];
1878 }
1879
1880 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1881 b43err(dev->wl, "MAC transmission error\n");
1882
00e0b8cb 1883 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1884 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1885 rmb();
1886 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1887 atomic_set(&dev->phy.txerr_cnt,
1888 B43_PHY_TX_BADNESS_LIMIT);
1889 b43err(dev->wl, "Too many PHY TX errors, "
1890 "restarting the controller\n");
1891 b43_controller_restart(dev, "PHY TX errors");
1892 }
1893 }
e4d6b795
MB		 1894
1895 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1896 B43_DMAIRQ_NONFATALMASK))) {
1897 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1898 b43err(dev->wl, "Fatal DMA error: "
1899 "0x%08X, 0x%08X, 0x%08X, "
1900 "0x%08X, 0x%08X, 0x%08X\n",
1901 dma_reason[0], dma_reason[1],
1902 dma_reason[2], dma_reason[3],
1903 dma_reason[4], dma_reason[5]);
214ac9a4 1904 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1905 "on your system. It will now be switched to PIO.\n");
9e3bd919
LT		 1906 /* Fall back to PIO transfers if we get fatal DMA errors! */
1907 dev->use_pio = 1;
1908 b43_controller_restart(dev, "DMA error");
e4d6b795
MB		 1909 return;
1910 }
1911 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1912 b43err(dev->wl, "DMA error: "
1913 "0x%08X, 0x%08X, 0x%08X, "
1914 "0x%08X, 0x%08X, 0x%08X\n",
1915 dma_reason[0], dma_reason[1],
1916 dma_reason[2], dma_reason[3],
1917 dma_reason[4], dma_reason[5]);
1918 }
1919 }
1920
1921 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1922 handle_irq_ucode_debug(dev);
1923 if (reason & B43_IRQ_TBTT_INDI)
1924 handle_irq_tbtt_indication(dev);
1925 if (reason & B43_IRQ_ATIM_END)
1926 handle_irq_atim_end(dev);
1927 if (reason & B43_IRQ_BEACON)
1928 handle_irq_beacon(dev);
1929 if (reason & B43_IRQ_PMQ)
1930 handle_irq_pmq(dev);
21954c36
MB		 1931 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1932 ;/* TODO */
1933 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1934 handle_irq_noise(dev);
1935
1936 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1937 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1938 if (b43_using_pio_transfers(dev))
1939 b43_pio_rx(dev->pio.rx_queue);
1940 else
1941 b43_dma_rx(dev->dma.rx_ring);
1942 }
e4d6b795
MB		 1943 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1944 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1945 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1946 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1947 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1948
21954c36 1949 if (reason & B43_IRQ_TX_OK)
e4d6b795 1950 handle_irq_transmit_status(dev);
e4d6b795 1951
36dbd954 1952 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1953 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1954
1955#if B43_DEBUG
1956 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1957 dev->irq_count++;
1958 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1959 if (reason & (1 << i))
1960 dev->irq_bit_count[i]++;
1961 }
1962 }
1963#endif
e4d6b795
MB		 1964}
1965
36dbd954
MB		 1966/* Interrupt thread handler. Handles device interrupts in thread context. */
1967static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1968{
36dbd954 1969 struct b43_wldev *dev = dev_id;
e4d6b795 1970
36dbd954
MB		 1971 mutex_lock(&dev->wl->mutex);
1972 b43_do_interrupt_thread(dev);
1973 mmiowb();
1974 mutex_unlock(&dev->wl->mutex);
1975
1976 return IRQ_HANDLED;
e4d6b795
MB		 1977}
1978
36dbd954 1979static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1980{
e4d6b795
MB		 1981 u32 reason;
1982
36dbd954
MB		 1983 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1984 * On SDIO, this runs under wl->mutex. */
e4d6b795 1985
e4d6b795
MB		 1986 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1987 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1988 return IRQ_NONE;
13790728 1989 reason &= dev->irq_mask;
e4d6b795 1990 if (!reason)
cae56147 1991 return IRQ_NONE;
e4d6b795
MB		 1992
1993 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1994 & 0x0001DC00;
1995 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1996 & 0x0000DC00;
1997 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1998 & 0x0000DC00;
1999 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2000 & 0x0001DC00;
2001 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2002 & 0x0000DC00;
13790728 2003/* Unused ring
e4d6b795
MB		 2004 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2005 & 0x0000DC00;
13790728 2006*/
e4d6b795 2007
36dbd954
MB		 2008 /* ACK the interrupt. */
2009 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2010 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2011 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2012 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2013 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2014 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2015/* Unused ring
2016 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2017*/
2018
2019 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2020 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2021 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2022 dev->irq_reason = reason;
36dbd954
MB		 2023
2024 return IRQ_WAKE_THREAD;
2025}
2026
2027/* Interrupt handler top-half. This runs with interrupts disabled. */
2028static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2029{
2030 struct b43_wldev *dev = dev_id;
2031 irqreturn_t ret;
2032
2033 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2034 return IRQ_NONE;
2035
2036 spin_lock(&dev->wl->hardirq_lock);
2037 ret = b43_do_interrupt(dev);
e4d6b795 2038 mmiowb();
36dbd954 2039 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2040
2041 return ret;
2042}
2043
3dbba8e2
AH		 2044/* SDIO interrupt handler. This runs in process context. */
2045static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2046{
2047 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2048 irqreturn_t ret;
2049
3dbba8e2 2050 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2051
2052 ret = b43_do_interrupt(dev);
2053 if (ret == IRQ_WAKE_THREAD)
2054 b43_do_interrupt_thread(dev);
2055
3dbba8e2
AH		 2056 mutex_unlock(&wl->mutex);
2057}
2058
1a9f5093 2059void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2060{
2061 release_firmware(fw->data);
2062 fw->data = NULL;
2063 fw->filename = NULL;
2064}
2065
e4d6b795
MB		 2066static void b43_release_firmware(struct b43_wldev *dev)
2067{
1a9f5093
MB		 2068 b43_do_release_fw(&dev->fw.ucode);
2069 b43_do_release_fw(&dev->fw.pcm);
2070 b43_do_release_fw(&dev->fw.initvals);
2071 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2072}
2073
eb189d8b 2074static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2075{
fc68ed4f
HE		 2076 const char text[] =
2077 "You must go to " \
2078 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2079 "and download the correct firmware for this driver version. " \
2080 "Please carefully read all instructions on this website.\n";
eb189d8b 2081
eb189d8b
MB		 2082 if (error)
2083 b43err(wl, text);
2084 else
2085 b43warn(wl, text);
e4d6b795
MB		 2086}
2087
1a9f5093
MB		 2088int b43_do_request_fw(struct b43_request_fw_context *ctx,
2089 const char *name,
2090 struct b43_firmware_file *fw)
e4d6b795 2091{
61cb5dd6 2092 const struct firmware *blob;
e4d6b795
MB		 2093 struct b43_fw_header *hdr;
2094 u32 size;
2095 int err;
2096
61cb5dd6
MB		 2097 if (!name) {
2098 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2099 /* FIXME: We should probably keep it anyway, to save some headache
2100 * on suspend/resume with multiband devices. */
2101 b43_do_release_fw(fw);
e4d6b795 2102 return 0;
61cb5dd6
MB		 2103 }
2104 if (fw->filename) {
1a9f5093
MB		 2105 if ((fw->type == ctx->req_type) &&
2106 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2107 return 0; /* Already have this fw. */
2108 /* Free the cached firmware first. */
1a9f5093
MB		 2109 /* FIXME: We should probably do this later after we successfully
2110 * got the new fw. This could reduce headache with multiband devices.
2111 * We could also redesign this to cache the firmware for all possible
2112 * bands all the time. */
2113 b43_do_release_fw(fw);
61cb5dd6 2114 }
e4d6b795 2115
1a9f5093
MB		 2116 switch (ctx->req_type) {
2117 case B43_FWTYPE_PROPRIETARY:
2118 snprintf(ctx->fwname, sizeof(ctx->fwname),
2119 "b43%s/%s.fw",
2120 modparam_fwpostfix, name);
2121 break;
2122 case B43_FWTYPE_OPENSOURCE:
2123 snprintf(ctx->fwname, sizeof(ctx->fwname),
2124 "b43-open%s/%s.fw",
2125 modparam_fwpostfix, name);
2126 break;
2127 default:
2128 B43_WARN_ON(1);
2129 return -ENOSYS;
2130 }
a18c715e 2131 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2132 if (err == -ENOENT) {
1a9f5093
MB		 2133 snprintf(ctx->errors[ctx->req_type],
2134 sizeof(ctx->errors[ctx->req_type]),
2135 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2136 return err;
2137 } else if (err) {
1a9f5093
MB		 2138 snprintf(ctx->errors[ctx->req_type],
2139 sizeof(ctx->errors[ctx->req_type]),
2140 "Firmware file \"%s\" request failed (err=%d)\n",
2141 ctx->fwname, err);
e4d6b795
MB		 2142 return err;
2143 }
61cb5dd6 2144 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2145 goto err_format;
61cb5dd6 2146 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2147 switch (hdr->type) {
2148 case B43_FW_TYPE_UCODE:
2149 case B43_FW_TYPE_PCM:
2150 size = be32_to_cpu(hdr->size);
61cb5dd6 2151 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2152 goto err_format;
2153 /* fallthrough */
2154 case B43_FW_TYPE_IV:
2155 if (hdr->ver != 1)
2156 goto err_format;
2157 break;
2158 default:
2159 goto err_format;
2160 }
2161
61cb5dd6
MB		 2162 fw->data = blob;
2163 fw->filename = name;
1a9f5093 2164 fw->type = ctx->req_type;
61cb5dd6
MB		 2165
2166 return 0;
e4d6b795
MB		 2167
2168err_format:
1a9f5093
MB		 2169 snprintf(ctx->errors[ctx->req_type],
2170 sizeof(ctx->errors[ctx->req_type]),
2171 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2172 release_firmware(blob);
2173
e4d6b795
MB		 2174 return -EPROTO;
2175}
2176
1a9f5093 2177static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2178{
1a9f5093
MB		 2179 struct b43_wldev *dev = ctx->dev;
2180 struct b43_firmware *fw = &ctx->dev->fw;
21d889d4 2181 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795
MB		 2182 const char *filename;
2183 u32 tmshigh;
2184 int err;
2185
8b9bda75
RM		 2186 /* Files for HT and LCN were found by trying one by one */
2187
61cb5dd6 2188 /* Get microcode */
6ff1e5cf 2189 if ((rev >= 5) && (rev <= 10)) {
61cb5dd6 2190 filename = "ucode5";
6ff1e5cf 2191 } else if ((rev >= 11) && (rev <= 12)) {
61cb5dd6 2192 filename = "ucode11";
6ff1e5cf 2193 } else if (rev == 13) {
61cb5dd6 2194 filename = "ucode13";
6ff1e5cf 2195 } else if (rev == 14) {
759b973b 2196 filename = "ucode14";
6ff1e5cf 2197 } else if (rev == 15) {
759b973b 2198 filename = "ucode15";
6ff1e5cf
RM		 2199 } else {
2200 switch (dev->phy.type) {
2201 case B43_PHYTYPE_N:
2202 if (rev >= 16)
2203 filename = "ucode16_mimo";
2204 else
2205 goto err_no_ucode;
2206 break;
8b9bda75
RM		 2207 case B43_PHYTYPE_HT:
2208 if (rev == 29)
2209 filename = "ucode29_mimo";
2210 else
2211 goto err_no_ucode;
2212 break;
2213 case B43_PHYTYPE_LCN:
2214 if (rev == 24)
2215 filename = "ucode24_mimo";
2216 else
2217 goto err_no_ucode;
2218 break;
6ff1e5cf
RM		 2219 default:
2220 goto err_no_ucode;
2221 }
2222 }
1a9f5093 2223 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2224 if (err)
2225 goto err_load;
2226
2227 /* Get PCM code */
2228 if ((rev >= 5) && (rev <= 10))
2229 filename = "pcm5";
2230 else if (rev >= 11)
2231 filename = NULL;
2232 else
2233 goto err_no_pcm;
68217832 2234 fw->pcm_request_failed = 0;
1a9f5093 2235 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2236 if (err == -ENOENT) {
2237 /* We did not find a PCM file? Not fatal, but
2238 * core rev <= 10 must do without hwcrypto then. */
2239 fw->pcm_request_failed = 1;
2240 } else if (err)
61cb5dd6
MB		 2241 goto err_load;
2242
2243 /* Get initvals */
2244 switch (dev->phy.type) {
2245 case B43_PHYTYPE_A:
2246 if ((rev >= 5) && (rev <= 10)) {
d48ae5c8 2247 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
61cb5dd6
MB		 2248 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2249 filename = "a0g1initvals5";
2250 else
2251 filename = "a0g0initvals5";
2252 } else
2253 goto err_no_initvals;
2254 break;
2255 case B43_PHYTYPE_G:
e4d6b795 2256 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2257 filename = "b0g0initvals5";
e4d6b795 2258 else if (rev >= 13)
e9304882 2259 filename = "b0g0initvals13";
e4d6b795 2260 else
61cb5dd6
MB		 2261 goto err_no_initvals;
2262 break;
2263 case B43_PHYTYPE_N:
e41596a1
RM		 2264 if (rev >= 16)
2265 filename = "n0initvals16";
2266 else if ((rev >= 11) && (rev <= 12))
61cb5dd6
MB		 2267 filename = "n0initvals11";
2268 else
2269 goto err_no_initvals;
2270 break;
759b973b
GS		 2271 case B43_PHYTYPE_LP:
2272 if (rev == 13)
2273 filename = "lp0initvals13";
2274 else if (rev == 14)
2275 filename = "lp0initvals14";
2276 else if (rev >= 15)
2277 filename = "lp0initvals15";
2278 else
2279 goto err_no_initvals;
2280 break;
8b9bda75
RM		 2281 case B43_PHYTYPE_HT:
2282 if (rev == 29)
2283 filename = "ht0initvals29";
2284 else
2285 goto err_no_initvals;
2286 break;
2287 case B43_PHYTYPE_LCN:
2288 if (rev == 24)
2289 filename = "lcn0initvals24";
2290 else
2291 goto err_no_initvals;
2292 break;
61cb5dd6
MB		 2293 default:
2294 goto err_no_initvals;
e4d6b795 2295 }
1a9f5093 2296 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2297 if (err)
2298 goto err_load;
2299
2300 /* Get bandswitch initvals */
2301 switch (dev->phy.type) {
2302 case B43_PHYTYPE_A:
2303 if ((rev >= 5) && (rev <= 10)) {
d48ae5c8 2304 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
61cb5dd6
MB		 2305 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2306 filename = "a0g1bsinitvals5";
2307 else
2308 filename = "a0g0bsinitvals5";
2309 } else if (rev >= 11)
2310 filename = NULL;
2311 else
2312 goto err_no_initvals;
2313 break;
2314 case B43_PHYTYPE_G:
e4d6b795 2315 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2316 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2317 else if (rev >= 11)
2318 filename = NULL;
2319 else
e4d6b795 2320 goto err_no_initvals;
61cb5dd6
MB		 2321 break;
2322 case B43_PHYTYPE_N:
e41596a1
RM		 2323 if (rev >= 16)
2324 filename = "n0bsinitvals16";
2325 else if ((rev >= 11) && (rev <= 12))
61cb5dd6
MB		 2326 filename = "n0bsinitvals11";
2327 else
e4d6b795 2328 goto err_no_initvals;
61cb5dd6 2329 break;
759b973b
GS		 2330 case B43_PHYTYPE_LP:
2331 if (rev == 13)
2332 filename = "lp0bsinitvals13";
2333 else if (rev == 14)
2334 filename = "lp0bsinitvals14";
2335 else if (rev >= 15)
2336 filename = "lp0bsinitvals15";
2337 else
2338 goto err_no_initvals;
2339 break;
8b9bda75
RM		 2340 case B43_PHYTYPE_HT:
2341 if (rev == 29)
2342 filename = "ht0bsinitvals29";
2343 else
2344 goto err_no_initvals;
2345 break;
2346 case B43_PHYTYPE_LCN:
2347 if (rev == 24)
2348 filename = "lcn0bsinitvals24";
2349 else
2350 goto err_no_initvals;
2351 break;
61cb5dd6
MB		 2352 default:
2353 goto err_no_initvals;
e4d6b795 2354 }
1a9f5093 2355 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2356 if (err)
2357 goto err_load;
e4d6b795
MB		 2358
2359 return 0;
2360
e4d6b795 2361err_no_ucode:
1a9f5093
MB		 2362 err = ctx->fatal_failure = -EOPNOTSUPP;
2363 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2364 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2365 goto error;
2366
2367err_no_pcm:
1a9f5093
MB		 2368 err = ctx->fatal_failure = -EOPNOTSUPP;
2369 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2370 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2371 goto error;
2372
2373err_no_initvals:
1a9f5093
MB		 2374 err = ctx->fatal_failure = -EOPNOTSUPP;
2375 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2376 "is required for your device (wl-core rev %u)\n", rev);
2377 goto error;
2378
2379err_load:
2380 /* We failed to load this firmware image. The error message
2381 * already is in ctx->errors. Return and let our caller decide
2382 * what to do. */
e4d6b795
MB		 2383 goto error;
2384
2385error:
2386 b43_release_firmware(dev);
2387 return err;
2388}
2389
1a9f5093
MB		 2390static int b43_request_firmware(struct b43_wldev *dev)
2391{
2392 struct b43_request_fw_context *ctx;
2393 unsigned int i;
2394 int err;
2395 const char *errmsg;
2396
2397 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2398 if (!ctx)
2399 return -ENOMEM;
2400 ctx->dev = dev;
2401
2402 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2403 err = b43_try_request_fw(ctx);
2404 if (!err)
2405 goto out; /* Successfully loaded it. */
2406 err = ctx->fatal_failure;
2407 if (err)
2408 goto out;
2409
2410 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2411 err = b43_try_request_fw(ctx);
2412 if (!err)
2413 goto out; /* Successfully loaded it. */
2414 err = ctx->fatal_failure;
2415 if (err)
2416 goto out;
2417
2418 /* Could not find a usable firmware. Print the errors. */
2419 for (i = 0; i < B43_NR_FWTYPES; i++) {
2420 errmsg = ctx->errors[i];
2421 if (strlen(errmsg))
2422 b43err(dev->wl, errmsg);
2423 }
2424 b43_print_fw_helptext(dev->wl, 1);
2425 err = -ENOENT;
2426
2427out:
2428 kfree(ctx);
2429 return err;
2430}
2431
e4d6b795
MB		 2432static int b43_upload_microcode(struct b43_wldev *dev)
2433{
652caa5b 2434 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2435 const size_t hdr_len = sizeof(struct b43_fw_header);
2436 const __be32 *data;
2437 unsigned int i, len;
2438 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2439 u32 tmp, macctl;
e4d6b795
MB		 2440 int err = 0;
2441
1f7d87b0
MB		 2442 /* Jump the microcode PSM to offset 0 */
2443 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2444 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2445 macctl |= B43_MACCTL_PSM_JMP0;
2446 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2447 /* Zero out all microcode PSM registers and shared memory. */
2448 for (i = 0; i < 64; i++)
2449 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2450 for (i = 0; i < 4096; i += 2)
2451 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2452
e4d6b795 2453 /* Upload Microcode. */
61cb5dd6
MB		 2454 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2455 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2456 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2457 for (i = 0; i < len; i++) {
2458 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2459 udelay(10);
2460 }
2461
61cb5dd6 2462 if (dev->fw.pcm.data) {
e4d6b795 2463 /* Upload PCM data. */
61cb5dd6
MB		 2464 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2465 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2466 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2467 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2468 /* No need for autoinc bit in SHM_HW */
2469 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2470 for (i = 0; i < len; i++) {
2471 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2472 udelay(10);
2473 }
2474 }
2475
2476 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2477
2478 /* Start the microcode PSM */
2479 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2480 macctl &= ~B43_MACCTL_PSM_JMP0;
2481 macctl |= B43_MACCTL_PSM_RUN;
2482 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2483
2484 /* Wait for the microcode to load and respond */
2485 i = 0;
2486 while (1) {
2487 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2488 if (tmp == B43_IRQ_MAC_SUSPENDED)
2489 break;
2490 i++;
1f7d87b0 2491 if (i >= 20) {
e4d6b795 2492 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2493 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2494 err = -ENODEV;
1f7d87b0
MB		 2495 goto error;
2496 }
e175e996 2497 msleep(50);
e4d6b795
MB		 2498 }
2499 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2500
2501 /* Get and check the revisions. */
2502 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2503 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2504 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2505 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2506
2507 if (fwrev <= 0x128) {
2508 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2509 "binary drivers older than version 4.x is unsupported. "
2510 "You must upgrade your firmware files.\n");
eb189d8b 2511 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2512 err = -EOPNOTSUPP;
1f7d87b0 2513 goto error;
e4d6b795 2514 }
e4d6b795
MB		 2515 dev->fw.rev = fwrev;
2516 dev->fw.patch = fwpatch;
efe0249b
RM		 2517 if (dev->fw.rev >= 410)
2518 dev->fw.hdr_format = B43_FW_HDR_410;
2519 else
2520 dev->fw.hdr_format = B43_FW_HDR_351;
e48b0eeb
MB		 2521 dev->fw.opensource = (fwdate == 0xFFFF);
2522
403a3a13
MB		 2523 /* Default to use-all-queues. */
2524 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2525 dev->qos_enabled = !!modparam_qos;
2526 /* Default to firmware/hardware crypto acceleration. */
2527 dev->hwcrypto_enabled = 1;
2528
e48b0eeb 2529 if (dev->fw.opensource) {
403a3a13
MB		 2530 u16 fwcapa;
2531
e48b0eeb
MB		 2532 /* Patchlevel info is encoded in the "time" field. */
2533 dev->fw.patch = fwtime;
403a3a13
MB		 2534 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2535 dev->fw.rev, dev->fw.patch);
2536
2537 fwcapa = b43_fwcapa_read(dev);
2538 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2539 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2540 /* Disable hardware crypto and fall back to software crypto. */
2541 dev->hwcrypto_enabled = 0;
2542 }
2543 if (!(fwcapa & B43_FWCAPA_QOS)) {
2544 b43info(dev->wl, "QoS not supported by firmware\n");
2545 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2546 * ieee80211_unregister to make sure the networking core can
2547 * properly free possible resources. */
2548 dev->wl->hw->queues = 1;
2549 dev->qos_enabled = 0;
2550 }
e48b0eeb
MB		 2551 } else {
2552 b43info(dev->wl, "Loading firmware version %u.%u "
2553 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2554 fwrev, fwpatch,
2555 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2556 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2557 if (dev->fw.pcm_request_failed) {
2558 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2559 "Hardware accelerated cryptography is disabled.\n");
2560 b43_print_fw_helptext(dev->wl, 0);
2561 }
e48b0eeb 2562 }
e4d6b795 2563
652caa5b
JL		 2564 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2565 dev->fw.rev, dev->fw.patch);
21d889d4 2566 wiphy->hw_version = dev->dev->core_id;
652caa5b 2567
efe0249b 2568 if (dev->fw.hdr_format == B43_FW_HDR_351) {
c557289c
MB		 2569 /* We're over the deadline, but we keep support for old fw
2570 * until it turns out to be in major conflict with something new. */
eb189d8b 2571 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2572 "Support for old firmware will be removed soon "
2573 "(official deadline was July 2008).\n");
eb189d8b
MB		 2574 b43_print_fw_helptext(dev->wl, 0);
2575 }
2576
1f7d87b0
MB		 2577 return 0;
2578
2579error:
2580 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2581 macctl &= ~B43_MACCTL_PSM_RUN;
2582 macctl |= B43_MACCTL_PSM_JMP0;
2583 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2584
e4d6b795
MB		 2585 return err;
2586}
2587
2588static int b43_write_initvals(struct b43_wldev *dev,
2589 const struct b43_iv *ivals,
2590 size_t count,
2591 size_t array_size)
2592{
2593 const struct b43_iv *iv;
2594 u16 offset;
2595 size_t i;
2596 bool bit32;
2597
2598 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2599 iv = ivals;
2600 for (i = 0; i < count; i++) {
2601 if (array_size < sizeof(iv->offset_size))
2602 goto err_format;
2603 array_size -= sizeof(iv->offset_size);
2604 offset = be16_to_cpu(iv->offset_size);
2605 bit32 = !!(offset & B43_IV_32BIT);
2606 offset &= B43_IV_OFFSET_MASK;
2607 if (offset >= 0x1000)
2608 goto err_format;
2609 if (bit32) {
2610 u32 value;
2611
2612 if (array_size < sizeof(iv->data.d32))
2613 goto err_format;
2614 array_size -= sizeof(iv->data.d32);
2615
533dd1b0 2616 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2617 b43_write32(dev, offset, value);
2618
2619 iv = (const struct b43_iv *)((const uint8_t *)iv +
2620 sizeof(__be16) +
2621 sizeof(__be32));
2622 } else {
2623 u16 value;
2624
2625 if (array_size < sizeof(iv->data.d16))
2626 goto err_format;
2627 array_size -= sizeof(iv->data.d16);
2628
2629 value = be16_to_cpu(iv->data.d16);
2630 b43_write16(dev, offset, value);
2631
2632 iv = (const struct b43_iv *)((const uint8_t *)iv +
2633 sizeof(__be16) +
2634 sizeof(__be16));
2635 }
2636 }
2637 if (array_size)
2638 goto err_format;
2639
2640 return 0;
2641
2642err_format:
2643 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2644 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2645
2646 return -EPROTO;
2647}
2648
2649static int b43_upload_initvals(struct b43_wldev *dev)
2650{
2651 const size_t hdr_len = sizeof(struct b43_fw_header);
2652 const struct b43_fw_header *hdr;
2653 struct b43_firmware *fw = &dev->fw;
2654 const struct b43_iv *ivals;
2655 size_t count;
2656 int err;
2657
61cb5dd6
MB		 2658 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2659 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2660 count = be32_to_cpu(hdr->size);
2661 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2662 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2663 if (err)
2664 goto out;
61cb5dd6
MB		 2665 if (fw->initvals_band.data) {
2666 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2667 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2668 count = be32_to_cpu(hdr->size);
2669 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2670 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2671 if (err)
2672 goto out;
2673 }
2674out:
2675
2676 return err;
2677}
2678
2679/* Initialize the GPIOs
2680 * http://bcm-specs.sipsolutions.net/GPIO
2681 */
c4a2a081 2682static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2683{
d48ae5c8 2684 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2685
2686#ifdef CONFIG_SSB_DRIVER_PCICORE
2687 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2688#else
2689 return bus->chipco.dev;
2690#endif
2691}
2692
e4d6b795
MB		 2693static int b43_gpio_init(struct b43_wldev *dev)
2694{
c4a2a081 2695 struct ssb_device *gpiodev;
e4d6b795
MB		 2696 u32 mask, set;
2697
2698 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2699 & ~B43_MACCTL_GPOUTSMSK);
2700
e4d6b795
MB		 2701 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2702 | 0x000F);
2703
2704 mask = 0x0000001F;
2705 set = 0x0000000F;
c244e08c 2706 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2707 mask |= 0x0060;
2708 set |= 0x0060;
2709 }
2710 if (0 /* FIXME: conditional unknown */ ) {
2711 b43_write16(dev, B43_MMIO_GPIO_MASK,
2712 b43_read16(dev, B43_MMIO_GPIO_MASK)
2713 | 0x0100);
2714 mask |= 0x0180;
2715 set |= 0x0180;
2716 }
0581483a 2717 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2718 b43_write16(dev, B43_MMIO_GPIO_MASK,
2719 b43_read16(dev, B43_MMIO_GPIO_MASK)
2720 | 0x0200);
2721 mask |= 0x0200;
2722 set |= 0x0200;
2723 }
21d889d4 2724 if (dev->dev->core_rev >= 2)
e4d6b795
MB		 2725 mask |= 0x0010; /* FIXME: This is redundant. */
2726
6cbab0d9 2727 switch (dev->dev->bus_type) {
42c9a458
RM		 2728#ifdef CONFIG_B43_BCMA
2729 case B43_BUS_BCMA:
2730 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2731 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2732 BCMA_CC_GPIOCTL) & mask) | set);
2733 break;
2734#endif
6cbab0d9
RM		 2735#ifdef CONFIG_B43_SSB
2736 case B43_BUS_SSB:
2737 gpiodev = b43_ssb_gpio_dev(dev);
2738 if (gpiodev)
2739 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2740 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2741 & mask) | set);
2742 break;
2743#endif
2744 }
e4d6b795
MB		 2745
2746 return 0;
2747}
2748
2749/* Turn off all GPIO stuff. Call this on module unload, for example. */
2750static void b43_gpio_cleanup(struct b43_wldev *dev)
2751{
c4a2a081 2752 struct ssb_device *gpiodev;
e4d6b795 2753
6cbab0d9 2754 switch (dev->dev->bus_type) {
42c9a458
RM		 2755#ifdef CONFIG_B43_BCMA
2756 case B43_BUS_BCMA:
2757 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2758 0);
2759 break;
2760#endif
6cbab0d9
RM		 2761#ifdef CONFIG_B43_SSB
2762 case B43_BUS_SSB:
2763 gpiodev = b43_ssb_gpio_dev(dev);
2764 if (gpiodev)
2765 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2766 break;
2767#endif
2768 }
e4d6b795
MB		 2769}
2770
2771/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2772void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2773{
923fd703
MB		 2774 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2775 u16 fwstate;
2776
2777 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2778 B43_SHM_SH_UCODESTAT);
2779 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2780 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2781 b43err(dev->wl, "b43_mac_enable(): The firmware "
2782 "should be suspended, but current state is %u\n",
2783 fwstate);
2784 }
2785 }
2786
e4d6b795
MB		 2787 dev->mac_suspended--;
2788 B43_WARN_ON(dev->mac_suspended < 0);
2789 if (dev->mac_suspended == 0) {
2790 b43_write32(dev, B43_MMIO_MACCTL,
2791 b43_read32(dev, B43_MMIO_MACCTL)
2792 | B43_MACCTL_ENABLED);
2793 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2794 B43_IRQ_MAC_SUSPENDED);
2795 /* Commit writes */
2796 b43_read32(dev, B43_MMIO_MACCTL);
2797 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2798 b43_power_saving_ctl_bits(dev, 0);
2799 }
2800}
2801
2802/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2803void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2804{
2805 int i;
2806 u32 tmp;
2807
05b64b36 2808 might_sleep();
e4d6b795 2809 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2810
e4d6b795
MB		 2811 if (dev->mac_suspended == 0) {
2812 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2813 b43_write32(dev, B43_MMIO_MACCTL,
2814 b43_read32(dev, B43_MMIO_MACCTL)
2815 & ~B43_MACCTL_ENABLED);
2816 /* force pci to flush the write */
2817 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2818 for (i = 35; i; i--) {
2819 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2820 if (tmp & B43_IRQ_MAC_SUSPENDED)
2821 goto out;
2822 udelay(10);
2823 }
2824 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2825 for (i = 40; i; i--) {
e4d6b795
MB		 2826 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2827 if (tmp & B43_IRQ_MAC_SUSPENDED)
2828 goto out;
05b64b36 2829 msleep(1);
e4d6b795
MB		 2830 }
2831 b43err(dev->wl, "MAC suspend failed\n");
2832 }
05b64b36 2833out:
e4d6b795
MB		 2834 dev->mac_suspended++;
2835}
2836
858a1652
RM		 2837/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2838void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2839{
6cbab0d9
RM		 2840 u32 tmp;
2841
2842 switch (dev->dev->bus_type) {
42c9a458
RM		 2843#ifdef CONFIG_B43_BCMA
2844 case B43_BUS_BCMA:
36677874 2845 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2846 if (on)
2847 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2848 else
2849 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2850 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2851 break;
2852#endif
6cbab0d9
RM		 2853#ifdef CONFIG_B43_SSB
2854 case B43_BUS_SSB:
2855 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2856 if (on)
2857 tmp |= B43_TMSLOW_MACPHYCLKEN;
2858 else
2859 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2860 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2861 break;
2862#endif
2863 }
858a1652
RM		 2864}
2865
e4d6b795
MB		 2866static void b43_adjust_opmode(struct b43_wldev *dev)
2867{
2868 struct b43_wl *wl = dev->wl;
2869 u32 ctl;
2870 u16 cfp_pretbtt;
2871
2872 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2873 /* Reset status to STA infrastructure mode. */
2874 ctl &= ~B43_MACCTL_AP;
2875 ctl &= ~B43_MACCTL_KEEP_CTL;
2876 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2877 ctl &= ~B43_MACCTL_KEEP_BAD;
2878 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2879 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2880 ctl |= B43_MACCTL_INFRA;
2881
05c914fe
JB		 2882 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2883 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2884 ctl |= B43_MACCTL_AP;
05c914fe 2885 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2886 ctl &= ~B43_MACCTL_INFRA;
2887
2888 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2889 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2890 if (wl->filter_flags & FIF_FCSFAIL)
2891 ctl |= B43_MACCTL_KEEP_BAD;
2892 if (wl->filter_flags & FIF_PLCPFAIL)
2893 ctl |= B43_MACCTL_KEEP_BADPLCP;
2894 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2895 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2896 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2897 ctl |= B43_MACCTL_BEACPROMISC;
2898
e4d6b795
MB		 2899 /* Workaround: On old hardware the HW-MAC-address-filter
2900 * doesn't work properly, so always run promisc in filter
2901 * it in software. */
21d889d4 2902 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 2903 ctl |= B43_MACCTL_PROMISC;
2904
2905 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2906
2907 cfp_pretbtt = 2;
2908 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 2909 if (dev->dev->chip_id == 0x4306 &&
2910 dev->dev->chip_rev == 3)
e4d6b795
MB		 2911 cfp_pretbtt = 100;
2912 else
2913 cfp_pretbtt = 50;
2914 }
2915 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 2916
2917 /* FIXME: We don't currently implement the PMQ mechanism,
2918 * so always disable it. If we want to implement PMQ,
2919 * we need to enable it here (clear DISCPMQ) in AP mode.
2920 */
2921 if (0 /* ctl & B43_MACCTL_AP */) {
2922 b43_write32(dev, B43_MMIO_MACCTL,
2923 b43_read32(dev, B43_MMIO_MACCTL)
2924 & ~B43_MACCTL_DISCPMQ);
2925 } else {
2926 b43_write32(dev, B43_MMIO_MACCTL,
2927 b43_read32(dev, B43_MMIO_MACCTL)
2928 | B43_MACCTL_DISCPMQ);
2929 }
e4d6b795
MB		 2930}
2931
2932static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2933{
2934 u16 offset;
2935
2936 if (is_ofdm) {
2937 offset = 0x480;
2938 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2939 } else {
2940 offset = 0x4C0;
2941 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2942 }
2943 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2944 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2945}
2946
2947static void b43_rate_memory_init(struct b43_wldev *dev)
2948{
2949 switch (dev->phy.type) {
2950 case B43_PHYTYPE_A:
2951 case B43_PHYTYPE_G:
53a6e234 2952 case B43_PHYTYPE_N:
9d86a2d5 2953 case B43_PHYTYPE_LP:
e4d6b795
MB		 2954 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2955 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2956 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2957 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2958 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2959 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2960 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2961 if (dev->phy.type == B43_PHYTYPE_A)
2962 break;
2963 /* fallthrough */
2964 case B43_PHYTYPE_B:
2965 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2966 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2967 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2968 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2969 break;
2970 default:
2971 B43_WARN_ON(1);
2972 }
2973}
2974
5042c507
MB		 2975/* Set the default values for the PHY TX Control Words. */
2976static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2977{
2978 u16 ctl = 0;
2979
2980 ctl |= B43_TXH_PHY_ENC_CCK;
2981 ctl |= B43_TXH_PHY_ANT01AUTO;
2982 ctl |= B43_TXH_PHY_TXPWR;
2983
2984 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2985 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2986 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2987}
2988
e4d6b795
MB		 2989/* Set the TX-Antenna for management frames sent by firmware. */
2990static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2991{
5042c507 2992 u16 ant;
e4d6b795
MB		 2993 u16 tmp;
2994
5042c507 2995 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2996
e4d6b795
MB		 2997 /* For ACK/CTS */
2998 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2999 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3000 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3001 /* For Probe Resposes */
3002 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 3003 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3004 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3005}
3006
3007/* This is the opposite of b43_chip_init() */
3008static void b43_chip_exit(struct b43_wldev *dev)
3009{
fb11137a 3010 b43_phy_exit(dev);
e4d6b795
MB		 3011 b43_gpio_cleanup(dev);
3012 /* firmware is released later */
3013}
3014
3015/* Initialize the chip
3016 * http://bcm-specs.sipsolutions.net/ChipInit
3017 */
3018static int b43_chip_init(struct b43_wldev *dev)
3019{
3020 struct b43_phy *phy = &dev->phy;
ef1a628d 3021 int err;
858a1652 3022 u32 macctl;
e4d6b795
MB		 3023 u16 value16;
3024
1f7d87b0
MB		 3025 /* Initialize the MAC control */
3026 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3027 if (dev->phy.gmode)
3028 macctl |= B43_MACCTL_GMODE;
3029 macctl |= B43_MACCTL_INFRA;
3030 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 3031
3032 err = b43_request_firmware(dev);
3033 if (err)
3034 goto out;
3035 err = b43_upload_microcode(dev);
3036 if (err)
3037 goto out; /* firmware is released later */
3038
3039 err = b43_gpio_init(dev);
3040 if (err)
3041 goto out; /* firmware is released later */
21954c36 3042
e4d6b795
MB		 3043 err = b43_upload_initvals(dev);
3044 if (err)
1a8d1227 3045 goto err_gpio_clean;
e4d6b795 3046
0b7dcd96
MB		 3047 /* Turn the Analog on and initialize the PHY. */
3048 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3049 err = b43_phy_init(dev);
3050 if (err)
ef1a628d 3051 goto err_gpio_clean;
e4d6b795 3052
ef1a628d
MB		 3053 /* Disable Interference Mitigation. */
3054 if (phy->ops->interf_mitigation)
3055 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3056
ef1a628d
MB		 3057 /* Select the antennae */
3058 if (phy->ops->set_rx_antenna)
3059 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3060 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3061
3062 if (phy->type == B43_PHYTYPE_B) {
3063 value16 = b43_read16(dev, 0x005E);
3064 value16 |= 0x0004;
3065 b43_write16(dev, 0x005E, value16);
3066 }
3067 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3068 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3069 b43_write32(dev, 0x010C, 0x01000000);
3070
3071 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3072 & ~B43_MACCTL_INFRA);
3073 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3074 | B43_MACCTL_INFRA);
e4d6b795 3075
e4d6b795
MB		 3076 /* Probe Response Timeout value */
3077 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3078 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3079
3080 /* Initially set the wireless operation mode. */
3081 b43_adjust_opmode(dev);
3082
21d889d4 3083 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3084 b43_write16(dev, 0x060E, 0x0000);
3085 b43_write16(dev, 0x0610, 0x8000);
3086 b43_write16(dev, 0x0604, 0x0000);
3087 b43_write16(dev, 0x0606, 0x0200);
3088 } else {
3089 b43_write32(dev, 0x0188, 0x80000000);
3090 b43_write32(dev, 0x018C, 0x02000000);
3091 }
3092 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3093 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3094 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3095 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3096 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3097 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3098 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3099
858a1652 3100 b43_mac_phy_clock_set(dev, true);
e4d6b795 3101
6cbab0d9 3102 switch (dev->dev->bus_type) {
42c9a458
RM		 3103#ifdef CONFIG_B43_BCMA
3104 case B43_BUS_BCMA:
3105 /* FIXME: 0xE74 is quite common, but should be read from CC */
3106 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3107 break;
3108#endif
6cbab0d9
RM		 3109#ifdef CONFIG_B43_SSB
3110 case B43_BUS_SSB:
3111 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3112 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3113 break;
3114#endif
3115 }
e4d6b795
MB		 3116
3117 err = 0;
3118 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3119out:
e4d6b795
MB		 3120 return err;
3121
1a8d1227 3122err_gpio_clean:
e4d6b795 3123 b43_gpio_cleanup(dev);
21954c36 3124 return err;
e4d6b795
MB		 3125}
3126
e4d6b795
MB		 3127static void b43_periodic_every60sec(struct b43_wldev *dev)
3128{
ef1a628d 3129 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3130
ef1a628d
MB		 3131 if (ops->pwork_60sec)
3132 ops->pwork_60sec(dev);
18c8adeb
MB		 3133
3134 /* Force check the TX power emission now. */
3135 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3136}
3137
3138static void b43_periodic_every30sec(struct b43_wldev *dev)
3139{
3140 /* Update device statistics. */
3141 b43_calculate_link_quality(dev);
3142}
3143
3144static void b43_periodic_every15sec(struct b43_wldev *dev)
3145{
3146 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3147 u16 wdr;
3148
3149 if (dev->fw.opensource) {
3150 /* Check if the firmware is still alive.
3151 * It will reset the watchdog counter to 0 in its idle loop. */
3152 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3153 if (unlikely(wdr)) {
3154 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3155 b43_controller_restart(dev, "Firmware watchdog");
3156 return;
3157 } else {
3158 b43_shm_write16(dev, B43_SHM_SCRATCH,
3159 B43_WATCHDOG_REG, 1);
3160 }
3161 }
e4d6b795 3162
ef1a628d
MB		 3163 if (phy->ops->pwork_15sec)
3164 phy->ops->pwork_15sec(dev);
3165
00e0b8cb
SB		 3166 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3167 wmb();
990b86f4
MB		 3168
3169#if B43_DEBUG
3170 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3171 unsigned int i;
3172
3173 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3174 dev->irq_count / 15,
3175 dev->tx_count / 15,
3176 dev->rx_count / 15);
3177 dev->irq_count = 0;
3178 dev->tx_count = 0;
3179 dev->rx_count = 0;
3180 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3181 if (dev->irq_bit_count[i]) {
3182 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3183 dev->irq_bit_count[i] / 15, i, (1 << i));
3184 dev->irq_bit_count[i] = 0;
3185 }
3186 }
3187 }
3188#endif
e4d6b795
MB		 3189}
3190
e4d6b795
MB		 3191static void do_periodic_work(struct b43_wldev *dev)
3192{
3193 unsigned int state;
3194
3195 state = dev->periodic_state;
42bb4cd5 3196 if (state % 4 == 0)
e4d6b795 3197 b43_periodic_every60sec(dev);
42bb4cd5 3198 if (state % 2 == 0)
e4d6b795 3199 b43_periodic_every30sec(dev);
42bb4cd5 3200 b43_periodic_every15sec(dev);
e4d6b795
MB		 3201}
3202
05b64b36
MB		 3203/* Periodic work locking policy:
3204 * The whole periodic work handler is protected by
3205 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3206 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3207 */
e4d6b795
MB		 3208static void b43_periodic_work_handler(struct work_struct *work)
3209{
05b64b36
MB		 3210 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3211 periodic_work.work);
3212 struct b43_wl *wl = dev->wl;
3213 unsigned long delay;
e4d6b795 3214
05b64b36 3215 mutex_lock(&wl->mutex);
e4d6b795
MB		 3216
3217 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3218 goto out;
3219 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3220 goto out_requeue;
3221
05b64b36 3222 do_periodic_work(dev);
e4d6b795 3223
e4d6b795 3224 dev->periodic_state++;
42bb4cd5 3225out_requeue:
e4d6b795
MB		 3226 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3227 delay = msecs_to_jiffies(50);
3228 else
82cd682d 3229 delay = round_jiffies_relative(HZ * 15);
42935eca 3230 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3231out:
05b64b36 3232 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3233}
3234
3235static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3236{
3237 struct delayed_work *work = &dev->periodic_work;
3238
3239 dev->periodic_state = 0;
3240 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3241 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3242}
3243
f3dd3fcc 3244/* Check if communication with the device works correctly. */
e4d6b795
MB		 3245static int b43_validate_chipaccess(struct b43_wldev *dev)
3246{
f62ae6cd 3247 u32 v, backup0, backup4;
e4d6b795 3248
f62ae6cd
MB		 3249 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3250 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3251
3252 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3253 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3254 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3255 goto error;
f3dd3fcc
MB		 3256 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3257 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3258 goto error;
3259
f62ae6cd
MB		 3260 /* Check if unaligned 32bit SHM_SHARED access works properly.
3261 * However, don't bail out on failure, because it's noncritical. */
3262 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3263 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3264 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3265 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3266 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3267 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3268 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3269 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3270 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3271 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3272 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3273 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3274
3275 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3276 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3277
21d889d4 3278 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3279 /* The 32bit register shadows the two 16bit registers
3280 * with update sideeffects. Validate this. */
3281 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3282 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3283 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3284 goto error;
3285 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3286 goto error;
3287 }
3288 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3289
3290 v = b43_read32(dev, B43_MMIO_MACCTL);
3291 v |= B43_MACCTL_GMODE;
3292 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3293 goto error;
3294
3295 return 0;
f3dd3fcc 3296error:
e4d6b795
MB		 3297 b43err(dev->wl, "Failed to validate the chipaccess\n");
3298 return -ENODEV;
3299}
3300
3301static void b43_security_init(struct b43_wldev *dev)
3302{
e4d6b795
MB		 3303 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3304 /* KTP is a word address, but we address SHM bytewise.
3305 * So multiply by two.
3306 */
3307 dev->ktp *= 2;
66d2d089
MB		 3308 /* Number of RCMTA address slots */
3309 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3310 /* Clear the key memory. */
e4d6b795
MB		 3311 b43_clear_keys(dev);
3312}
3313
616de35d 3314#ifdef CONFIG_B43_HWRNG
99da185a 3315static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3316{
3317 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3318 struct b43_wldev *dev;
3319 int count = -ENODEV;
e4d6b795 3320
a78b3bb2
MB		 3321 mutex_lock(&wl->mutex);
3322 dev = wl->current_dev;
3323 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3324 *data = b43_read16(dev, B43_MMIO_RNG);
3325 count = sizeof(u16);
3326 }
3327 mutex_unlock(&wl->mutex);
e4d6b795 3328
a78b3bb2 3329 return count;
e4d6b795 3330}
616de35d 3331#endif /* CONFIG_B43_HWRNG */
e4d6b795 3332
b844eba2 3333static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3334{
616de35d 3335#ifdef CONFIG_B43_HWRNG
e4d6b795 3336 if (wl->rng_initialized)
b844eba2 3337 hwrng_unregister(&wl->rng);
616de35d 3338#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3339}
3340
3341static int b43_rng_init(struct b43_wl *wl)
3342{
616de35d 3343 int err = 0;
e4d6b795 3344
616de35d 3345#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3346 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3347 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3348 wl->rng.name = wl->rng_name;
3349 wl->rng.data_read = b43_rng_read;
3350 wl->rng.priv = (unsigned long)wl;
3351 wl->rng_initialized = 1;
3352 err = hwrng_register(&wl->rng);
3353 if (err) {
3354 wl->rng_initialized = 0;
3355 b43err(wl, "Failed to register the random "
3356 "number generator (%d)\n", err);
3357 }
616de35d 3358#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3359
3360 return err;
3361}
3362
f5d40eed 3363static void b43_tx_work(struct work_struct *work)
e4d6b795 3364{
f5d40eed
MB		 3365 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3366 struct b43_wldev *dev;
3367 struct sk_buff *skb;
3368 int err = 0;
e4d6b795 3369
f5d40eed
MB		 3370 mutex_lock(&wl->mutex);
3371 dev = wl->current_dev;
3372 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3373 mutex_unlock(&wl->mutex);
3374 return;
5100d5ac 3375 }
21a75d77 3376
f5d40eed
MB		 3377 while (skb_queue_len(&wl->tx_queue)) {
3378 skb = skb_dequeue(&wl->tx_queue);
21a75d77 3379
21a75d77 3380 if (b43_using_pio_transfers(dev))
e039fa4a 3381 err = b43_pio_tx(dev, skb);
21a75d77 3382 else
e039fa4a 3383 err = b43_dma_tx(dev, skb);
f5d40eed
MB		 3384 if (unlikely(err))
3385 dev_kfree_skb(skb); /* Drop it */
21a75d77
MB		 3386 }
3387
990b86f4
MB		 3388#if B43_DEBUG
3389 dev->tx_count++;
3390#endif
f5d40eed
MB		 3391 mutex_unlock(&wl->mutex);
3392}
21a75d77 3393
7bb45683 3394static void b43_op_tx(struct ieee80211_hw *hw,
f5d40eed
MB		 3395 struct sk_buff *skb)
3396{
3397 struct b43_wl *wl = hw_to_b43_wl(hw);
3398
3399 if (unlikely(skb->len < 2 + 2 + 6)) {
3400 /* Too short, this can't be a valid frame. */
3401 dev_kfree_skb_any(skb);
7bb45683 3402 return;
f5d40eed
MB		 3403 }
3404 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3405
3406 skb_queue_tail(&wl->tx_queue, skb);
3407 ieee80211_queue_work(wl->hw, &wl->tx_work);
e4d6b795
MB		 3408}
3409
e6f5b934
MB		 3410static void b43_qos_params_upload(struct b43_wldev *dev,
3411 const struct ieee80211_tx_queue_params *p,
3412 u16 shm_offset)
3413{
3414 u16 params[B43_NR_QOSPARAMS];
0b57664c 3415 int bslots, tmp;
e6f5b934
MB		 3416 unsigned int i;
3417
b0544eb6
MB		 3418 if (!dev->qos_enabled)
3419 return;
3420
0b57664c 3421 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3422
3423 memset(&params, 0, sizeof(params));
3424
3425 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3426 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3427 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3428 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3429 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3430 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3431 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3432
3433 for (i = 0; i < ARRAY_SIZE(params); i++) {
3434 if (i == B43_QOSPARAM_STATUS) {
3435 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3436 shm_offset + (i * 2));
3437 /* Mark the parameters as updated. */
3438 tmp |= 0x100;
3439 b43_shm_write16(dev, B43_SHM_SHARED,
3440 shm_offset + (i * 2),
3441 tmp);
3442 } else {
3443 b43_shm_write16(dev, B43_SHM_SHARED,
3444 shm_offset + (i * 2),
3445 params[i]);
3446 }
3447 }
3448}
3449
c40c1129
MB		 3450/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3451static const u16 b43_qos_shm_offsets[] = {
3452 /* [mac80211-queue-nr] = SHM_OFFSET, */
3453 [0] = B43_QOS_VOICE,
3454 [1] = B43_QOS_VIDEO,
3455 [2] = B43_QOS_BESTEFFORT,
3456 [3] = B43_QOS_BACKGROUND,
3457};
3458
5a5f3b40
MB		 3459/* Update all QOS parameters in hardware. */
3460static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3461{
3462 struct b43_wl *wl = dev->wl;
3463 struct b43_qos_params *params;
e6f5b934
MB		 3464 unsigned int i;
3465
b0544eb6
MB		 3466 if (!dev->qos_enabled)
3467 return;
3468
c40c1129
MB		 3469 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3470 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3471
3472 b43_mac_suspend(dev);
e6f5b934
MB		 3473 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3474 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3475 b43_qos_params_upload(dev, &(params->p),
3476 b43_qos_shm_offsets[i]);
e6f5b934 3477 }
e6f5b934
MB		 3478 b43_mac_enable(dev);
3479}
3480
3481static void b43_qos_clear(struct b43_wl *wl)
3482{
3483 struct b43_qos_params *params;
3484 unsigned int i;
3485
c40c1129
MB		 3486 /* Initialize QoS parameters to sane defaults. */
3487
3488 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3489 ARRAY_SIZE(wl->qos_params));
3490
e6f5b934
MB		 3491 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3492 params = &(wl->qos_params[i]);
3493
c40c1129
MB		 3494 switch (b43_qos_shm_offsets[i]) {
3495 case B43_QOS_VOICE:
3496 params->p.txop = 0;
3497 params->p.aifs = 2;
3498 params->p.cw_min = 0x0001;
3499 params->p.cw_max = 0x0001;
3500 break;
3501 case B43_QOS_VIDEO:
3502 params->p.txop = 0;
3503 params->p.aifs = 2;
3504 params->p.cw_min = 0x0001;
3505 params->p.cw_max = 0x0001;
3506 break;
3507 case B43_QOS_BESTEFFORT:
3508 params->p.txop = 0;
3509 params->p.aifs = 3;
3510 params->p.cw_min = 0x0001;
3511 params->p.cw_max = 0x03FF;
3512 break;
3513 case B43_QOS_BACKGROUND:
3514 params->p.txop = 0;
3515 params->p.aifs = 7;
3516 params->p.cw_min = 0x0001;
3517 params->p.cw_max = 0x03FF;
3518 break;
3519 default:
3520 B43_WARN_ON(1);
3521 }
e6f5b934
MB		 3522 }
3523}
3524
3525/* Initialize the core's QOS capabilities */
3526static void b43_qos_init(struct b43_wldev *dev)
3527{
b0544eb6
MB		 3528 if (!dev->qos_enabled) {
3529 /* Disable QOS support. */
3530 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3531 b43_write16(dev, B43_MMIO_IFSCTL,
3532 b43_read16(dev, B43_MMIO_IFSCTL)
3533 & ~B43_MMIO_IFSCTL_USE_EDCF);
3534 b43dbg(dev->wl, "QoS disabled\n");
3535 return;
3536 }
3537
e6f5b934 3538 /* Upload the current QOS parameters. */
5a5f3b40 3539 b43_qos_upload_all(dev);
e6f5b934
MB		 3540
3541 /* Enable QOS support. */
3542 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3543 b43_write16(dev, B43_MMIO_IFSCTL,
3544 b43_read16(dev, B43_MMIO_IFSCTL)
3545 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3546 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3547}
3548
e100bb64 3549static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3550 const struct ieee80211_tx_queue_params *params)
e4d6b795 3551{
e6f5b934 3552 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3553 struct b43_wldev *dev;
e6f5b934 3554 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3555 int err = -ENODEV;
e6f5b934
MB		 3556
3557 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3558 /* Queue not available or don't support setting
3559 * params on this queue. Return success to not
3560 * confuse mac80211. */
3561 return 0;
3562 }
5a5f3b40
MB		 3563 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3564 ARRAY_SIZE(wl->qos_params));
e6f5b934 3565
5a5f3b40
MB		 3566 mutex_lock(&wl->mutex);
3567 dev = wl->current_dev;
3568 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3569 goto out_unlock;
e6f5b934 3570
5a5f3b40
MB		 3571 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3572 b43_mac_suspend(dev);
3573 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3574 b43_qos_shm_offsets[queue]);
3575 b43_mac_enable(dev);
3576 err = 0;
e6f5b934 3577
5a5f3b40
MB		 3578out_unlock:
3579 mutex_unlock(&wl->mutex);
3580
3581 return err;
e4d6b795
MB		 3582}
3583
40faacc4
MB		 3584static int b43_op_get_stats(struct ieee80211_hw *hw,
3585 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3586{
3587 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3588
36dbd954 3589 mutex_lock(&wl->mutex);
e4d6b795 3590 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3591 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3592
3593 return 0;
3594}
3595
08e87a83
AF		 3596static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3597{
3598 struct b43_wl *wl = hw_to_b43_wl(hw);
3599 struct b43_wldev *dev;
3600 u64 tsf;
3601
3602 mutex_lock(&wl->mutex);
08e87a83
AF		 3603 dev = wl->current_dev;
3604
3605 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3606 b43_tsf_read(dev, &tsf);
3607 else
3608 tsf = 0;
3609
08e87a83
AF		 3610 mutex_unlock(&wl->mutex);
3611
3612 return tsf;
3613}
3614
3615static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3616{
3617 struct b43_wl *wl = hw_to_b43_wl(hw);
3618 struct b43_wldev *dev;
3619
3620 mutex_lock(&wl->mutex);
08e87a83
AF		 3621 dev = wl->current_dev;
3622
3623 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3624 b43_tsf_write(dev, tsf);
3625
08e87a83
AF		 3626 mutex_unlock(&wl->mutex);
3627}
3628
e4d6b795
MB		 3629static void b43_put_phy_into_reset(struct b43_wldev *dev)
3630{
6cbab0d9 3631 u32 tmp;
e4d6b795 3632
6cbab0d9 3633 switch (dev->dev->bus_type) {
42c9a458
RM		 3634#ifdef CONFIG_B43_BCMA
3635 case B43_BUS_BCMA:
3636 b43err(dev->wl,
3637 "Putting PHY into reset not supported on BCMA\n");
3638 break;
3639#endif
6cbab0d9
RM		 3640#ifdef CONFIG_B43_SSB
3641 case B43_BUS_SSB:
3642 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3643 tmp &= ~B43_TMSLOW_GMODE;
3644 tmp |= B43_TMSLOW_PHYRESET;
3645 tmp |= SSB_TMSLOW_FGC;
3646 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3647 msleep(1);
3648
3649 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3650 tmp &= ~SSB_TMSLOW_FGC;
3651 tmp |= B43_TMSLOW_PHYRESET;
3652 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3653 msleep(1);
e4d6b795 3654
6cbab0d9
RM		 3655 break;
3656#endif
3657 }
e4d6b795
MB		 3658}
3659
99da185a 3660static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3661{
3662 switch (band) {
3663 case IEEE80211_BAND_5GHZ:
3664 return "5";
3665 case IEEE80211_BAND_2GHZ:
3666 return "2.4";
3667 default:
3668 break;
3669 }
3670 B43_WARN_ON(1);
3671 return "";
3672}
3673
e4d6b795 3674/* Expects wl->mutex locked */
bb1eeff1 3675static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3676{
bb1eeff1 3677 struct b43_wldev *up_dev = NULL;
e4d6b795 3678 struct b43_wldev *down_dev;
bb1eeff1 3679 struct b43_wldev *d;
e4d6b795 3680 int err;
922d8a0b 3681 bool uninitialized_var(gmode);
e4d6b795
MB		 3682 int prev_status;
3683
bb1eeff1
MB		 3684 /* Find a device and PHY which supports the band. */
3685 list_for_each_entry(d, &wl->devlist, list) {
3686 switch (chan->band) {
3687 case IEEE80211_BAND_5GHZ:
3688 if (d->phy.supports_5ghz) {
3689 up_dev = d;
3690 gmode = 0;
3691 }
3692 break;
3693 case IEEE80211_BAND_2GHZ:
3694 if (d->phy.supports_2ghz) {
3695 up_dev = d;
3696 gmode = 1;
3697 }
3698 break;
3699 default:
3700 B43_WARN_ON(1);
3701 return -EINVAL;
3702 }
3703 if (up_dev)
3704 break;
3705 }
3706 if (!up_dev) {
3707 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3708 band_to_string(chan->band));
3709 return -ENODEV;
e4d6b795
MB		 3710 }
3711 if ((up_dev == wl->current_dev) &&
3712 (!!wl->current_dev->phy.gmode == !!gmode)) {
3713 /* This device is already running. */
3714 return 0;
3715 }
bb1eeff1
MB		 3716 b43dbg(wl, "Switching to %s-GHz band\n",
3717 band_to_string(chan->band));
e4d6b795
MB		 3718 down_dev = wl->current_dev;
3719
3720 prev_status = b43_status(down_dev);
3721 /* Shutdown the currently running core. */
3722 if (prev_status >= B43_STAT_STARTED)
36dbd954 3723 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3724 if (prev_status >= B43_STAT_INITIALIZED)
3725 b43_wireless_core_exit(down_dev);
3726
3727 if (down_dev != up_dev) {
3728 /* We switch to a different core, so we put PHY into
3729 * RESET on the old core. */
3730 b43_put_phy_into_reset(down_dev);
3731 }
3732
3733 /* Now start the new core. */
3734 up_dev->phy.gmode = gmode;
3735 if (prev_status >= B43_STAT_INITIALIZED) {
3736 err = b43_wireless_core_init(up_dev);
3737 if (err) {
3738 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3739 "selected %s-GHz band\n",
3740 band_to_string(chan->band));
e4d6b795
MB		 3741 goto init_failure;
3742 }
3743 }
3744 if (prev_status >= B43_STAT_STARTED) {
3745 err = b43_wireless_core_start(up_dev);
3746 if (err) {
3747 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3748 "selected %s-GHz band\n",
3749 band_to_string(chan->band));
e4d6b795
MB		 3750 b43_wireless_core_exit(up_dev);
3751 goto init_failure;
3752 }
3753 }
3754 B43_WARN_ON(b43_status(up_dev) != prev_status);
3755
3756 wl->current_dev = up_dev;
3757
3758 return 0;
bb1eeff1 3759init_failure:
e4d6b795
MB		 3760 /* Whoops, failed to init the new core. No core is operating now. */
3761 wl->current_dev = NULL;
3762 return err;
3763}
3764
9124b077
JB		 3765/* Write the short and long frame retry limit values. */
3766static void b43_set_retry_limits(struct b43_wldev *dev,
3767 unsigned int short_retry,
3768 unsigned int long_retry)
3769{
3770 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3771 * the chip-internal counter. */
3772 short_retry = min(short_retry, (unsigned int)0xF);
3773 long_retry = min(long_retry, (unsigned int)0xF);
3774
3775 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3776 short_retry);
3777 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3778 long_retry);
3779}
3780
e8975581 3781static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3782{
3783 struct b43_wl *wl = hw_to_b43_wl(hw);
3784 struct b43_wldev *dev;
3785 struct b43_phy *phy;
e8975581 3786 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3787 int antenna;
e4d6b795 3788 int err = 0;
2a190322 3789 bool reload_bss = false;
e4d6b795 3790
e4d6b795
MB		 3791 mutex_lock(&wl->mutex);
3792
2a190322
FF		 3793 dev = wl->current_dev;
3794
bb1eeff1
MB		 3795 /* Switch the band (if necessary). This might change the active core. */
3796 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3797 if (err)
3798 goto out_unlock_mutex;
2a190322
FF		 3799
3800 /* Need to reload all settings if the core changed */
3801 if (dev != wl->current_dev) {
3802 dev = wl->current_dev;
3803 changed = ~0;
3804 reload_bss = true;
3805 }
3806
e4d6b795
MB		 3807 phy = &dev->phy;
3808
aa4c7b2a
RM		 3809 if (conf_is_ht(conf))
3810 phy->is_40mhz =
3811 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3812 else
3813 phy->is_40mhz = false;
3814
d10d0e57
MB		 3815 b43_mac_suspend(dev);
3816
9124b077
JB		 3817 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3818 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3819 conf->long_frame_max_tx_count);
3820 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3821 if (!changed)
d10d0e57 3822 goto out_mac_enable;
e4d6b795
MB		 3823
3824 /* Switch to the requested channel.
3825 * The firmware takes care of races with the TX handler. */
8318d78a 3826 if (conf->channel->hw_value != phy->channel)
ef1a628d 3827 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3828
0869aea0 3829 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3830
e4d6b795
MB		 3831 /* Adjust the desired TX power level. */
3832 if (conf->power_level != 0) {
18c8adeb
MB		 3833 if (conf->power_level != phy->desired_txpower) {
3834 phy->desired_txpower = conf->power_level;
3835 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3836 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3837 }
3838 }
3839
3840 /* Antennas for RX and management frame TX. */
0f4ac38b 3841 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3842 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3843 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3844 if (phy->ops->set_rx_antenna)
3845 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3846
fd4973c5
LF		 3847 if (wl->radio_enabled != phy->radio_on) {
3848 if (wl->radio_enabled) {
19d337df 3849 b43_software_rfkill(dev, false);
fda9abcf
MB		 3850 b43info(dev->wl, "Radio turned on by software\n");
3851 if (!dev->radio_hw_enable) {
3852 b43info(dev->wl, "The hardware RF-kill button "
3853 "still turns the radio physically off. "
3854 "Press the button to turn it on.\n");
3855 }
3856 } else {
19d337df 3857 b43_software_rfkill(dev, true);
fda9abcf
MB		 3858 b43info(dev->wl, "Radio turned off by software\n");
3859 }
3860 }
3861
d10d0e57
MB		 3862out_mac_enable:
3863 b43_mac_enable(dev);
3864out_unlock_mutex:
e4d6b795
MB		 3865 mutex_unlock(&wl->mutex);
3866
2a190322
FF		 3867 if (wl->vif && reload_bss)
3868 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3869
e4d6b795
MB		 3870 return err;
3871}
3872
881d948c 3873static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3874{
3875 struct ieee80211_supported_band *sband =
3876 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3877 struct ieee80211_rate *rate;
3878 int i;
3879 u16 basic, direct, offset, basic_offset, rateptr;
3880
3881 for (i = 0; i < sband->n_bitrates; i++) {
3882 rate = &sband->bitrates[i];
3883
3884 if (b43_is_cck_rate(rate->hw_value)) {
3885 direct = B43_SHM_SH_CCKDIRECT;
3886 basic = B43_SHM_SH_CCKBASIC;
3887 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3888 offset &= 0xF;
3889 } else {
3890 direct = B43_SHM_SH_OFDMDIRECT;
3891 basic = B43_SHM_SH_OFDMBASIC;
3892 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3893 offset &= 0xF;
3894 }
3895
3896 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3897
3898 if (b43_is_cck_rate(rate->hw_value)) {
3899 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3900 basic_offset &= 0xF;
3901 } else {
3902 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3903 basic_offset &= 0xF;
3904 }
3905
3906 /*
3907 * Get the pointer that we need to point to
3908 * from the direct map
3909 */
3910 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3911 direct + 2 * basic_offset);
3912 /* and write it to the basic map */
3913 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3914 rateptr);
3915 }
3916}
3917
3918static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3919 struct ieee80211_vif *vif,
3920 struct ieee80211_bss_conf *conf,
3921 u32 changed)
3922{
3923 struct b43_wl *wl = hw_to_b43_wl(hw);
3924 struct b43_wldev *dev;
c7ab5ef9
JB		 3925
3926 mutex_lock(&wl->mutex);
3927
3928 dev = wl->current_dev;
d10d0e57 3929 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3930 goto out_unlock_mutex;
2d0ddec5
JB		 3931
3932 B43_WARN_ON(wl->vif != vif);
3933
3934 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3935 if (conf->bssid)
3936 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3937 else
3938 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3939 }
2d0ddec5 3940
3f0d843b
JB		 3941 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3942 if (changed & BSS_CHANGED_BEACON &&
3943 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3944 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3945 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3946 b43_update_templates(wl);
3947
3948 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3949 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3950 }
3951
c7ab5ef9
JB		 3952 b43_mac_suspend(dev);
3953
57c4d7b4
JB		 3954 /* Update templates for AP/mesh mode. */
3955 if (changed & BSS_CHANGED_BEACON_INT &&
3956 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3957 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 3958 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3959 conf->beacon_int)
57c4d7b4
JB		 3960 b43_set_beacon_int(dev, conf->beacon_int);
3961
c7ab5ef9
JB		 3962 if (changed & BSS_CHANGED_BASIC_RATES)
3963 b43_update_basic_rates(dev, conf->basic_rates);
3964
3965 if (changed & BSS_CHANGED_ERP_SLOT) {
3966 if (conf->use_short_slot)
3967 b43_short_slot_timing_enable(dev);
3968 else
3969 b43_short_slot_timing_disable(dev);
3970 }
3971
3972 b43_mac_enable(dev);
d10d0e57 3973out_unlock_mutex:
c7ab5ef9 3974 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3975}
3976
40faacc4 3977static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3978 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3979 struct ieee80211_key_conf *key)
e4d6b795
MB		 3980{
3981 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3982 struct b43_wldev *dev;
e4d6b795
MB		 3983 u8 algorithm;
3984 u8 index;
c6dfc9a8 3985 int err;
060210f9 3986 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3987
3988 if (modparam_nohwcrypt)
3989 return -ENOSPC; /* User disabled HW-crypto */
3990
c6dfc9a8 3991 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 3992
3993 dev = wl->current_dev;
3994 err = -ENODEV;
3995 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3996 goto out_unlock;
3997
403a3a13 3998 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3999 /* We don't have firmware for the crypto engine.
4000 * Must use software-crypto. */
4001 err = -EOPNOTSUPP;
4002 goto out_unlock;
4003 }
4004
c6dfc9a8 4005 err = -EINVAL;
97359d12
JB		 4006 switch (key->cipher) {
4007 case WLAN_CIPHER_SUITE_WEP40:
4008 algorithm = B43_SEC_ALGO_WEP40;
4009 break;
4010 case WLAN_CIPHER_SUITE_WEP104:
4011 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4012 break;
97359d12 4013 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4014 algorithm = B43_SEC_ALGO_TKIP;
4015 break;
97359d12 4016 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4017 algorithm = B43_SEC_ALGO_AES;
4018 break;
4019 default:
4020 B43_WARN_ON(1);
c6dfc9a8 4021 goto out_unlock;
e4d6b795 4022 }
e4d6b795
MB		 4023 index = (u8) (key->keyidx);
4024 if (index > 3)
e4d6b795 4025 goto out_unlock;
e4d6b795
MB		 4026
4027 switch (cmd) {
4028 case SET_KEY:
035d0243 4029 if (algorithm == B43_SEC_ALGO_TKIP &&
4030 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4031 !modparam_hwtkip)) {
4032 /* We support only pairwise key */
e4d6b795
MB		 4033 err = -EOPNOTSUPP;
4034 goto out_unlock;
4035 }
4036
e808e586 4037 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4038 if (WARN_ON(!sta)) {
4039 err = -EOPNOTSUPP;
4040 goto out_unlock;
4041 }
e808e586 4042 /* Pairwise key with an assigned MAC address. */
e4d6b795 4043 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4044 key->key, key->keylen,
4045 sta->addr, key);
e808e586
MB		 4046 } else {
4047 /* Group key */
4048 err = b43_key_write(dev, index, algorithm,
4049 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4050 }
4051 if (err)
4052 goto out_unlock;
4053
4054 if (algorithm == B43_SEC_ALGO_WEP40 ||
4055 algorithm == B43_SEC_ALGO_WEP104) {
4056 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4057 } else {
4058 b43_hf_write(dev,
4059 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4060 }
4061 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4062 if (algorithm == B43_SEC_ALGO_TKIP)
4063 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4064 break;
4065 case DISABLE_KEY: {
4066 err = b43_key_clear(dev, key->hw_key_idx);
4067 if (err)
4068 goto out_unlock;
4069 break;
4070 }
4071 default:
4072 B43_WARN_ON(1);
4073 }
9cf7f247 4074
e4d6b795 4075out_unlock:
e4d6b795
MB		 4076 if (!err) {
4077 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4078 "mac: %pM\n",
e4d6b795 4079 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4080 sta ? sta->addr : bcast_addr);
9cf7f247 4081 b43_dump_keymemory(dev);
e4d6b795 4082 }
9cf7f247
MB		 4083 mutex_unlock(&wl->mutex);
4084
e4d6b795
MB		 4085 return err;
4086}
4087
40faacc4
MB		 4088static void b43_op_configure_filter(struct ieee80211_hw *hw,
4089 unsigned int changed, unsigned int *fflags,
3ac64bee 4090 u64 multicast)
e4d6b795
MB		 4091{
4092 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4093 struct b43_wldev *dev;
e4d6b795 4094
36dbd954
MB		 4095 mutex_lock(&wl->mutex);
4096 dev = wl->current_dev;
4150c572
JB		 4097 if (!dev) {
4098 *fflags = 0;
36dbd954 4099 goto out_unlock;
e4d6b795 4100 }
4150c572 4101
4150c572
JB		 4102 *fflags &= FIF_PROMISC_IN_BSS |
4103 FIF_ALLMULTI |
4104 FIF_FCSFAIL |
4105 FIF_PLCPFAIL |
4106 FIF_CONTROL |
4107 FIF_OTHER_BSS |
4108 FIF_BCN_PRBRESP_PROMISC;
4109
4110 changed &= FIF_PROMISC_IN_BSS |
4111 FIF_ALLMULTI |
4112 FIF_FCSFAIL |
4113 FIF_PLCPFAIL |
4114 FIF_CONTROL |
4115 FIF_OTHER_BSS |
4116 FIF_BCN_PRBRESP_PROMISC;
4117
4118 wl->filter_flags = *fflags;
4119
4120 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4121 b43_adjust_opmode(dev);
36dbd954
MB		 4122
4123out_unlock:
4124 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4125}
4126
36dbd954
MB		 4127/* Locking: wl->mutex
4128 * Returns the current dev. This might be different from the passed in dev,
4129 * because the core might be gone away while we unlocked the mutex. */
4130static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795
MB		 4131{
4132 struct b43_wl *wl = dev->wl;
36dbd954 4133 struct b43_wldev *orig_dev;
49d965c8 4134 u32 mask;
e4d6b795 4135
36dbd954
MB		 4136redo:
4137 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4138 return dev;
a19d12d7 4139
f5d40eed 4140 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4141 mutex_unlock(&wl->mutex);
4142 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4143 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 4144 mutex_lock(&wl->mutex);
4145 dev = wl->current_dev;
4146 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4147 /* Whoops, aliens ate up the device while we were unlocked. */
4148 return dev;
4149 }
a19d12d7 4150
36dbd954 4151 /* Disable interrupts on the device. */
e4d6b795 4152 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4153 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4154 /* wl->mutex is locked. That is enough. */
4155 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4156 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4157 } else {
4158 spin_lock_irq(&wl->hardirq_lock);
4159 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4160 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4161 spin_unlock_irq(&wl->hardirq_lock);
4162 }
176e9f6a 4163 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4164 orig_dev = dev;
e4d6b795 4165 mutex_unlock(&wl->mutex);
505fb019 4166 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4167 b43_sdio_free_irq(dev);
4168 } else {
a18c715e
RM		 4169 synchronize_irq(dev->dev->irq);
4170 free_irq(dev->dev->irq, dev);
176e9f6a 4171 }
e4d6b795 4172 mutex_lock(&wl->mutex);
36dbd954
MB		 4173 dev = wl->current_dev;
4174 if (!dev)
4175 return dev;
4176 if (dev != orig_dev) {
4177 if (b43_status(dev) >= B43_STAT_STARTED)
4178 goto redo;
4179 return dev;
4180 }
49d965c8
MB		 4181 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4182 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4183
f5d40eed
MB		 4184 /* Drain the TX queue */
4185 while (skb_queue_len(&wl->tx_queue))
4186 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
4187
e4d6b795 4188 b43_mac_suspend(dev);
a78b3bb2 4189 b43_leds_exit(dev);
e4d6b795 4190 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4191
4192 return dev;
e4d6b795
MB		 4193}
4194
4195/* Locking: wl->mutex */
4196static int b43_wireless_core_start(struct b43_wldev *dev)
4197{
4198 int err;
4199
4200 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4201
4202 drain_txstatus_queue(dev);
505fb019 4203 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4204 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4205 if (err) {
4206 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4207 goto out;
4208 }
4209 } else {
a18c715e 4210 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4211 b43_interrupt_thread_handler,
4212 IRQF_SHARED, KBUILD_MODNAME, dev);
4213 if (err) {
dedb1eb9 4214 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4215 dev->dev->irq);
3dbba8e2
AH		 4216 goto out;
4217 }
e4d6b795
MB		 4218 }
4219
4220 /* We are ready to run. */
0866b03c 4221 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4222 b43_set_status(dev, B43_STAT_STARTED);
4223
4224 /* Start data flow (TX/RX). */
4225 b43_mac_enable(dev);
13790728 4226 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4227
25985edc 4228 /* Start maintenance work */
e4d6b795
MB		 4229 b43_periodic_tasks_setup(dev);
4230
a78b3bb2
MB		 4231 b43_leds_init(dev);
4232
e4d6b795 4233 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4234out:
e4d6b795
MB		 4235 return err;
4236}
4237
4238/* Get PHY and RADIO versioning numbers */
4239static int b43_phy_versioning(struct b43_wldev *dev)
4240{
4241 struct b43_phy *phy = &dev->phy;
4242 u32 tmp;
4243 u8 analog_type;
4244 u8 phy_type;
4245 u8 phy_rev;
4246 u16 radio_manuf;
4247 u16 radio_ver;
4248 u16 radio_rev;
4249 int unsupported = 0;
4250
4251 /* Get PHY versioning */
4252 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4253 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4254 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4255 phy_rev = (tmp & B43_PHYVER_VERSION);
4256 switch (phy_type) {
4257 case B43_PHYTYPE_A:
4258 if (phy_rev >= 4)
4259 unsupported = 1;
4260 break;
4261 case B43_PHYTYPE_B:
4262 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4263 && phy_rev != 7)
4264 unsupported = 1;
4265 break;
4266 case B43_PHYTYPE_G:
013978b6 4267 if (phy_rev > 9)
e4d6b795
MB		 4268 unsupported = 1;
4269 break;
692d2c0f 4270#ifdef CONFIG_B43_PHY_N
d5c71e46 4271 case B43_PHYTYPE_N:
ab72efdf 4272 if (phy_rev > 9)
d5c71e46
MB		 4273 unsupported = 1;
4274 break;
6b1c7c67
MB		 4275#endif
4276#ifdef CONFIG_B43_PHY_LP
4277 case B43_PHYTYPE_LP:
9d86a2d5 4278 if (phy_rev > 2)
6b1c7c67
MB		 4279 unsupported = 1;
4280 break;
d7520b1d
RM		 4281#endif
4282#ifdef CONFIG_B43_PHY_HT
4283 case B43_PHYTYPE_HT:
4284 if (phy_rev > 1)
4285 unsupported = 1;
4286 break;
1d738e64
RM		 4287#endif
4288#ifdef CONFIG_B43_PHY_LCN
4289 case B43_PHYTYPE_LCN:
4290 if (phy_rev > 1)
4291 unsupported = 1;
4292 break;
d5c71e46 4293#endif
e4d6b795
MB		 4294 default:
4295 unsupported = 1;
6403eab1 4296 }
e4d6b795
MB		 4297 if (unsupported) {
4298 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4299 "(Analog %u, Type %u, Revision %u)\n",
4300 analog_type, phy_type, phy_rev);
4301 return -EOPNOTSUPP;
4302 }
4303 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4304 analog_type, phy_type, phy_rev);
4305
4306 /* Get RADIO versioning */
3fd48508 4307 if (dev->dev->core_rev >= 24) {
544e5d8b
RM		 4308 u16 radio24[3];
4309
4310 for (tmp = 0; tmp < 3; tmp++) {
4311 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4312 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4313 }
4314
4315 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4316 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4317
4318 radio_manuf = 0x17F;
4319 radio_ver = (radio24[2] << 8) | radio24[1];
4320 radio_rev = (radio24[0] & 0xF);
e4d6b795 4321 } else {
3fd48508
RM		 4322 if (dev->dev->chip_id == 0x4317) {
4323 if (dev->dev->chip_rev == 0)
4324 tmp = 0x3205017F;
4325 else if (dev->dev->chip_rev == 1)
4326 tmp = 0x4205017F;
4327 else
4328 tmp = 0x5205017F;
4329 } else {
4330 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4331 B43_RADIOCTL_ID);
4332 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4333 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4334 B43_RADIOCTL_ID);
4335 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4336 << 16;
4337 }
4338 radio_manuf = (tmp & 0x00000FFF);
4339 radio_ver = (tmp & 0x0FFFF000) >> 12;
4340 radio_rev = (tmp & 0xF0000000) >> 28;
e4d6b795 4341 }
3fd48508 4342
96c755a3
MB		 4343 if (radio_manuf != 0x17F /* Broadcom */)
4344 unsupported = 1;
e4d6b795
MB		 4345 switch (phy_type) {
4346 case B43_PHYTYPE_A:
4347 if (radio_ver != 0x2060)
4348 unsupported = 1;
4349 if (radio_rev != 1)
4350 unsupported = 1;
4351 if (radio_manuf != 0x17F)
4352 unsupported = 1;
4353 break;
4354 case B43_PHYTYPE_B:
4355 if ((radio_ver & 0xFFF0) != 0x2050)
4356 unsupported = 1;
4357 break;
4358 case B43_PHYTYPE_G:
4359 if (radio_ver != 0x2050)
4360 unsupported = 1;
4361 break;
96c755a3 4362 case B43_PHYTYPE_N:
bb519bee 4363 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4364 unsupported = 1;
4365 break;
6b1c7c67 4366 case B43_PHYTYPE_LP:
9d86a2d5 4367 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4368 unsupported = 1;
4369 break;
d7520b1d
RM		 4370 case B43_PHYTYPE_HT:
4371 if (radio_ver != 0x2059)
4372 unsupported = 1;
4373 break;
1d738e64
RM		 4374 case B43_PHYTYPE_LCN:
4375 if (radio_ver != 0x2064)
4376 unsupported = 1;
4377 break;
e4d6b795
MB		 4378 default:
4379 B43_WARN_ON(1);
4380 }
4381 if (unsupported) {
4382 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4383 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4384 radio_manuf, radio_ver, radio_rev);
4385 return -EOPNOTSUPP;
4386 }
4387 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4388 radio_manuf, radio_ver, radio_rev);
4389
4390 phy->radio_manuf = radio_manuf;
4391 phy->radio_ver = radio_ver;
4392 phy->radio_rev = radio_rev;
4393
4394 phy->analog = analog_type;
4395 phy->type = phy_type;
4396 phy->rev = phy_rev;
4397
4398 return 0;
4399}
4400
4401static void setup_struct_phy_for_init(struct b43_wldev *dev,
4402 struct b43_phy *phy)
4403{
e4d6b795 4404 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4405 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4406 /* PHY TX errors counter. */
4407 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4408
4409#if B43_DEBUG
4410 phy->phy_locked = 0;
4411 phy->radio_locked = 0;
4412#endif
e4d6b795
MB		 4413}
4414
4415static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4416{
aa6c7ae2
MB		 4417 dev->dfq_valid = 0;
4418
6a724d68
MB		 4419 /* Assume the radio is enabled. If it's not enabled, the state will
4420 * immediately get fixed on the first periodic work run. */
4421 dev->radio_hw_enable = 1;
e4d6b795
MB		 4422
4423 /* Stats */
4424 memset(&dev->stats, 0, sizeof(dev->stats));
4425
4426 setup_struct_phy_for_init(dev, &dev->phy);
4427
4428 /* IRQ related flags */
4429 dev->irq_reason = 0;
4430 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4431 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4432 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4433 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4434
4435 dev->mac_suspended = 1;
4436
4437 /* Noise calculation context */
4438 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4439}
4440
4441static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4442{
0581483a 4443 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4444 u64 hf;
e4d6b795 4445
1855ba78
MB		 4446 if (!modparam_btcoex)
4447 return;
95de2841 4448 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4449 return;
4450 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4451 return;
4452
4453 hf = b43_hf_read(dev);
95de2841 4454 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4455 hf |= B43_HF_BTCOEXALT;
4456 else
4457 hf |= B43_HF_BTCOEX;
4458 b43_hf_write(dev, hf);
e4d6b795
MB		 4459}
4460
4461static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4462{
4463 if (!modparam_btcoex)
4464 return;
4465 //TODO
e4d6b795
MB		 4466}
4467
4468static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4469{
d48ae5c8 4470 struct ssb_bus *bus;
e4d6b795
MB		 4471 u32 tmp;
4472
d48ae5c8
RM		 4473 if (dev->dev->bus_type != B43_BUS_SSB)
4474 return;
4475
4476 bus = dev->dev->sdev->bus;
4477
0fd82eaf
RM		 4478 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4479 (bus->chip_id == 0x4312)) {
d48ae5c8 4480 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4481 tmp &= ~SSB_IMCFGLO_REQTO;
4482 tmp &= ~SSB_IMCFGLO_SERTO;
4483 tmp |= 0x3;
d48ae5c8 4484 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4485 ssb_commit_settings(bus);
e4d6b795 4486 }
e4d6b795
MB		 4487}
4488
d59f720d
MB		 4489static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4490{
4491 u16 pu_delay;
4492
4493 /* The time value is in microseconds. */
4494 if (dev->phy.type == B43_PHYTYPE_A)
4495 pu_delay = 3700;
4496 else
4497 pu_delay = 1050;
05c914fe 4498 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4499 pu_delay = 500;
4500 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4501 pu_delay = max(pu_delay, (u16)2400);
4502
4503 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4504}
4505
4506/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4507static void b43_set_pretbtt(struct b43_wldev *dev)
4508{
4509 u16 pretbtt;
4510
4511 /* The time value is in microseconds. */
05c914fe 4512 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4513 pretbtt = 2;
4514 } else {
4515 if (dev->phy.type == B43_PHYTYPE_A)
4516 pretbtt = 120;
4517 else
4518 pretbtt = 250;
4519 }
4520 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4521 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4522}
4523
e4d6b795
MB		 4524/* Shutdown a wireless core */
4525/* Locking: wl->mutex */
4526static void b43_wireless_core_exit(struct b43_wldev *dev)
4527{
1f7d87b0 4528 u32 macctl;
e4d6b795 4529
36dbd954
MB		 4530 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4531 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4532 return;
84c164a3
JL		 4533
4534 /* Unregister HW RNG driver */
4535 b43_rng_exit(dev->wl);
4536
e4d6b795
MB		 4537 b43_set_status(dev, B43_STAT_UNINIT);
4538
1f7d87b0
MB		 4539 /* Stop the microcode PSM. */
4540 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4541 macctl &= ~B43_MACCTL_PSM_RUN;
4542 macctl |= B43_MACCTL_PSM_JMP0;
4543 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4544
e4d6b795 4545 b43_dma_free(dev);
5100d5ac 4546 b43_pio_free(dev);
e4d6b795 4547 b43_chip_exit(dev);
cb24f57f 4548 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4549 if (dev->wl->current_beacon) {
4550 dev_kfree_skb_any(dev->wl->current_beacon);
4551 dev->wl->current_beacon = NULL;
4552 }
4553
24ca39d6
RM		 4554 b43_device_disable(dev, 0);
4555 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4556}
4557
4558/* Initialize a wireless core */
4559static int b43_wireless_core_init(struct b43_wldev *dev)
4560{
0581483a 4561 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4562 struct b43_phy *phy = &dev->phy;
4563 int err;
a259d6a4 4564 u64 hf;
e4d6b795
MB		 4565
4566 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4567
24ca39d6 4568 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4569 if (err)
4570 goto out;
4da909e7
RM		 4571 if (!b43_device_is_enabled(dev))
4572 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4573
fb11137a 4574 /* Reset all data structures. */
e4d6b795 4575 setup_struct_wldev_for_init(dev);
fb11137a 4576 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4577
4578 /* Enable IRQ routing to this device. */
6cbab0d9 4579 switch (dev->dev->bus_type) {
42c9a458
RM		 4580#ifdef CONFIG_B43_BCMA
4581 case B43_BUS_BCMA:
4582 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4583 dev->dev->bdev, true);
4584 break;
4585#endif
6cbab0d9
RM		 4586#ifdef CONFIG_B43_SSB
4587 case B43_BUS_SSB:
4588 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4589 dev->dev->sdev);
4590 break;
4591#endif
4592 }
e4d6b795
MB		 4593
4594 b43_imcfglo_timeouts_workaround(dev);
4595 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4596 if (phy->ops->prepare_hardware) {
4597 err = phy->ops->prepare_hardware(dev);
ef1a628d 4598 if (err)
fb11137a 4599 goto err_busdown;
ef1a628d 4600 }
e4d6b795
MB		 4601 err = b43_chip_init(dev);
4602 if (err)
fb11137a 4603 goto err_busdown;
e4d6b795 4604 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4605 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4606 hf = b43_hf_read(dev);
4607 if (phy->type == B43_PHYTYPE_G) {
4608 hf |= B43_HF_SYMW;
4609 if (phy->rev == 1)
4610 hf |= B43_HF_GDCW;
95de2841 4611 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4612 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4613 }
4614 if (phy->radio_ver == 0x2050) {
4615 if (phy->radio_rev == 6)
4616 hf |= B43_HF_4318TSSI;
4617 if (phy->radio_rev < 6)
4618 hf |= B43_HF_VCORECALC;
e4d6b795 4619 }
1cc8f476
MB		 4620 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4621 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4622#ifdef CONFIG_SSB_DRIVER_PCICORE
6cbab0d9
RM		 4623 if (dev->dev->bus_type == B43_BUS_SSB &&
4624 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4625 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4626 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4627#endif
25d3ef59 4628 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4629 b43_hf_write(dev, hf);
4630
74cfdba7
MB		 4631 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4632 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4633 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4634 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4635
4636 /* Disable sending probe responses from firmware.
4637 * Setting the MaxTime to one usec will always trigger
4638 * a timeout, so we never send any probe resp.
4639 * A timeout of zero is infinite. */
4640 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4641
4642 b43_rate_memory_init(dev);
5042c507 4643 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4644
4645 /* Minimum Contention Window */
c5a079f4 4646 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4647 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4648 else
e4d6b795 4649 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4650 /* Maximum Contention Window */
4651 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4652
505fb019
RM		 4653 if (b43_bus_host_is_pcmcia(dev->dev) ||
4654 b43_bus_host_is_sdio(dev->dev) ||
9e3bd919 4655 dev->use_pio) {
5100d5ac
MB		 4656 dev->__using_pio_transfers = 1;
4657 err = b43_pio_init(dev);
4658 } else {
4659 dev->__using_pio_transfers = 0;
4660 err = b43_dma_init(dev);
4661 }
e4d6b795
MB		 4662 if (err)
4663 goto err_chip_exit;
03b29773 4664 b43_qos_init(dev);
d59f720d 4665 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4666 b43_bluetooth_coext_enable(dev);
4667
24ca39d6 4668 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4669 b43_upload_card_macaddress(dev);
e4d6b795 4670 b43_security_init(dev);
e4d6b795 4671
5ab9549a 4672 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4673
4674 b43_set_status(dev, B43_STAT_INITIALIZED);
4675
84c164a3
JL		 4676 /* Register HW RNG driver */
4677 b43_rng_init(dev->wl);
4678
1a8d1227 4679out:
e4d6b795
MB		 4680 return err;
4681
ef1a628d 4682err_chip_exit:
e4d6b795 4683 b43_chip_exit(dev);
ef1a628d 4684err_busdown:
24ca39d6 4685 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4686 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4687 return err;
4688}
4689
40faacc4 4690static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4691 struct ieee80211_vif *vif)
e4d6b795
MB		 4692{
4693 struct b43_wl *wl = hw_to_b43_wl(hw);
4694 struct b43_wldev *dev;
e4d6b795 4695 int err = -EOPNOTSUPP;
4150c572
JB		 4696
4697 /* TODO: allow WDS/AP devices to coexist */
4698
1ed32e4f
JB		 4699 if (vif->type != NL80211_IFTYPE_AP &&
4700 vif->type != NL80211_IFTYPE_MESH_POINT &&
4701 vif->type != NL80211_IFTYPE_STATION &&
4702 vif->type != NL80211_IFTYPE_WDS &&
4703 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4704 return -EOPNOTSUPP;
e4d6b795
MB		 4705
4706 mutex_lock(&wl->mutex);
4150c572 4707 if (wl->operating)
e4d6b795
MB		 4708 goto out_mutex_unlock;
4709
1ed32e4f 4710 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4711
4712 dev = wl->current_dev;
4150c572 4713 wl->operating = 1;
1ed32e4f
JB		 4714 wl->vif = vif;
4715 wl->if_type = vif->type;
4716 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4717
4150c572 4718 b43_adjust_opmode(dev);
d59f720d
MB		 4719 b43_set_pretbtt(dev);
4720 b43_set_synth_pu_delay(dev, 0);
4150c572 4721 b43_upload_card_macaddress(dev);
4150c572
JB		 4722
4723 err = 0;
4724 out_mutex_unlock:
4725 mutex_unlock(&wl->mutex);
4726
2a190322
FF		 4727 if (err == 0)
4728 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4729
4150c572
JB		 4730 return err;
4731}
4732
40faacc4 4733static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4734 struct ieee80211_vif *vif)
4150c572
JB		 4735{
4736 struct b43_wl *wl = hw_to_b43_wl(hw);
4737 struct b43_wldev *dev = wl->current_dev;
4150c572 4738
1ed32e4f 4739 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4740
4741 mutex_lock(&wl->mutex);
4742
4743 B43_WARN_ON(!wl->operating);
1ed32e4f 4744 B43_WARN_ON(wl->vif != vif);
32bfd35d 4745 wl->vif = NULL;
4150c572
JB		 4746
4747 wl->operating = 0;
4748
4150c572
JB		 4749 b43_adjust_opmode(dev);
4750 memset(wl->mac_addr, 0, ETH_ALEN);
4751 b43_upload_card_macaddress(dev);
4150c572
JB		 4752
4753 mutex_unlock(&wl->mutex);
4754}
4755
40faacc4 4756static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4757{
4758 struct b43_wl *wl = hw_to_b43_wl(hw);
4759 struct b43_wldev *dev = wl->current_dev;
4760 int did_init = 0;
923403b8 4761 int err = 0;
4150c572 4762
7be1bb6b
MB		 4763 /* Kill all old instance specific information to make sure
4764 * the card won't use it in the short timeframe between start
4765 * and mac80211 reconfiguring it. */
4766 memset(wl->bssid, 0, ETH_ALEN);
4767 memset(wl->mac_addr, 0, ETH_ALEN);
4768 wl->filter_flags = 0;
4769 wl->radiotap_enabled = 0;
e6f5b934 4770 b43_qos_clear(wl);
6b4bec01
MB		 4771 wl->beacon0_uploaded = 0;
4772 wl->beacon1_uploaded = 0;
4773 wl->beacon_templates_virgin = 1;
fd4973c5 4774 wl->radio_enabled = 1;
7be1bb6b 4775
4150c572
JB		 4776 mutex_lock(&wl->mutex);
4777
e4d6b795
MB		 4778 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4779 err = b43_wireless_core_init(dev);
f41f3f37 4780 if (err)
e4d6b795
MB		 4781 goto out_mutex_unlock;
4782 did_init = 1;
4783 }
4150c572 4784
e4d6b795
MB		 4785 if (b43_status(dev) < B43_STAT_STARTED) {
4786 err = b43_wireless_core_start(dev);
4787 if (err) {
4788 if (did_init)
4789 b43_wireless_core_exit(dev);
4790 goto out_mutex_unlock;
4791 }
4792 }
4793
f41f3f37
JB		 4794 /* XXX: only do if device doesn't support rfkill irq */
4795 wiphy_rfkill_start_polling(hw->wiphy);
4796
4150c572 4797 out_mutex_unlock:
e4d6b795
MB		 4798 mutex_unlock(&wl->mutex);
4799
2a190322
FF		 4800 /* reload configuration */
4801 b43_op_config(hw, ~0);
4802
e4d6b795
MB		 4803 return err;
4804}
4805
40faacc4 4806static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4807{
4808 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4809 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4810
a82d9922 4811 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4812
e4d6b795 4813 mutex_lock(&wl->mutex);
36dbd954
MB		 4814 if (b43_status(dev) >= B43_STAT_STARTED) {
4815 dev = b43_wireless_core_stop(dev);
4816 if (!dev)
4817 goto out_unlock;
4818 }
4150c572 4819 b43_wireless_core_exit(dev);
fd4973c5 4820 wl->radio_enabled = 0;
36dbd954
MB		 4821
4822out_unlock:
e4d6b795 4823 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4824
4825 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4826}
4827
17741cdc
JB		 4828static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4829 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4830{
4831 struct b43_wl *wl = hw_to_b43_wl(hw);
4832
8f611288 4833 /* FIXME: add locking */
9d139c81 4834 b43_update_templates(wl);
e66fee6a
MB		 4835
4836 return 0;
4837}
4838
38968d09
JB		 4839static void b43_op_sta_notify(struct ieee80211_hw *hw,
4840 struct ieee80211_vif *vif,
4841 enum sta_notify_cmd notify_cmd,
17741cdc 4842 struct ieee80211_sta *sta)
38968d09
JB		 4843{
4844 struct b43_wl *wl = hw_to_b43_wl(hw);
4845
4846 B43_WARN_ON(!vif || wl->vif != vif);
4847}
4848
25d3ef59
MB		 4849static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4850{
4851 struct b43_wl *wl = hw_to_b43_wl(hw);
4852 struct b43_wldev *dev;
4853
4854 mutex_lock(&wl->mutex);
4855 dev = wl->current_dev;
4856 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4857 /* Disable CFP update during scan on other channels. */
4858 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4859 }
4860 mutex_unlock(&wl->mutex);
4861}
4862
4863static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4864{
4865 struct b43_wl *wl = hw_to_b43_wl(hw);
4866 struct b43_wldev *dev;
4867
4868 mutex_lock(&wl->mutex);
4869 dev = wl->current_dev;
4870 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4871 /* Re-enable CFP update. */
4872 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4873 }
4874 mutex_unlock(&wl->mutex);
4875}
4876
354b4f04
JL		 4877static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4878 struct survey_info *survey)
4879{
4880 struct b43_wl *wl = hw_to_b43_wl(hw);
4881 struct b43_wldev *dev = wl->current_dev;
4882 struct ieee80211_conf *conf = &hw->conf;
4883
4884 if (idx != 0)
4885 return -ENOENT;
4886
4887 survey->channel = conf->channel;
4888 survey->filled = SURVEY_INFO_NOISE_DBM;
4889 survey->noise = dev->stats.link_noise;
4890
4891 return 0;
4892}
4893
e4d6b795 4894static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4895 .tx = b43_op_tx,
4896 .conf_tx = b43_op_conf_tx,
4897 .add_interface = b43_op_add_interface,
4898 .remove_interface = b43_op_remove_interface,
4899 .config = b43_op_config,
c7ab5ef9 4900 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4901 .configure_filter = b43_op_configure_filter,
4902 .set_key = b43_op_set_key,
035d0243 4903 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 4904 .get_stats = b43_op_get_stats,
08e87a83
AF		 4905 .get_tsf = b43_op_get_tsf,
4906 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4907 .start = b43_op_start,
4908 .stop = b43_op_stop,
e66fee6a 4909 .set_tim = b43_op_beacon_set_tim,
38968d09 4910 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4911 .sw_scan_start = b43_op_sw_scan_start_notifier,
4912 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 4913 .get_survey = b43_op_get_survey,
f41f3f37 4914 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4915};
4916
4917/* Hard-reset the chip. Do not call this directly.
4918 * Use b43_controller_restart()
4919 */
4920static void b43_chip_reset(struct work_struct *work)
4921{
4922 struct b43_wldev *dev =
4923 container_of(work, struct b43_wldev, restart_work);
4924 struct b43_wl *wl = dev->wl;
4925 int err = 0;
4926 int prev_status;
4927
4928 mutex_lock(&wl->mutex);
4929
4930 prev_status = b43_status(dev);
4931 /* Bring the device down... */
36dbd954
MB		 4932 if (prev_status >= B43_STAT_STARTED) {
4933 dev = b43_wireless_core_stop(dev);
4934 if (!dev) {
4935 err = -ENODEV;
4936 goto out;
4937 }
4938 }
e4d6b795
MB		 4939 if (prev_status >= B43_STAT_INITIALIZED)
4940 b43_wireless_core_exit(dev);
4941
4942 /* ...and up again. */
4943 if (prev_status >= B43_STAT_INITIALIZED) {
4944 err = b43_wireless_core_init(dev);
4945 if (err)
4946 goto out;
4947 }
4948 if (prev_status >= B43_STAT_STARTED) {
4949 err = b43_wireless_core_start(dev);
4950 if (err) {
4951 b43_wireless_core_exit(dev);
4952 goto out;
4953 }
4954 }
3bf0a32e
MB		 4955out:
4956 if (err)
4957 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 4958 mutex_unlock(&wl->mutex);
2a190322
FF		 4959
4960 if (err) {
e4d6b795 4961 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 4962 return;
4963 }
4964
4965 /* reload configuration */
4966 b43_op_config(wl->hw, ~0);
4967 if (wl->vif)
4968 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
4969
4970 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 4971}
4972
bb1eeff1 4973static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4974 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4975{
4976 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4977
bb1eeff1
MB		 4978 if (have_2ghz_phy)
4979 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4980 if (dev->phy.type == B43_PHYTYPE_N) {
4981 if (have_5ghz_phy)
4982 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4983 } else {
4984 if (have_5ghz_phy)
4985 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4986 }
96c755a3 4987
bb1eeff1
MB		 4988 dev->phy.supports_2ghz = have_2ghz_phy;
4989 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4990
4991 return 0;
4992}
4993
4994static void b43_wireless_core_detach(struct b43_wldev *dev)
4995{
4996 /* We release firmware that late to not be required to re-request
4997 * is all the time when we reinit the core. */
4998 b43_release_firmware(dev);
fb11137a 4999 b43_phy_free(dev);
e4d6b795
MB		 5000}
5001
5002static int b43_wireless_core_attach(struct b43_wldev *dev)
5003{
5004 struct b43_wl *wl = dev->wl;
6cbab0d9 5005 struct pci_dev *pdev = NULL;
e4d6b795 5006 int err;
40c62269 5007 u32 tmp;
96c755a3 5008 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 5009
5010 /* Do NOT do any device initialization here.
5011 * Do it in wireless_core_init() instead.
5012 * This function is for gathering basic information about the HW, only.
5013 * Also some structs may be set up here. But most likely you want to have
5014 * that in core_init(), too.
5015 */
5016
6cbab0d9
RM		 5017#ifdef CONFIG_B43_SSB
5018 if (dev->dev->bus_type == B43_BUS_SSB &&
5019 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5020 pdev = dev->dev->sdev->bus->host_pci;
5021#endif
5022
24ca39d6 5023 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5024 if (err) {
5025 b43err(wl, "Bus powerup failed\n");
5026 goto out;
5027 }
e4d6b795 5028
6cbab0d9
RM		 5029 /* Get the PHY type. */
5030 switch (dev->dev->bus_type) {
42c9a458
RM		 5031#ifdef CONFIG_B43_BCMA
5032 case B43_BUS_BCMA:
40c62269
RM		 5033 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5034 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5035 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5036 break;
5037#endif
6cbab0d9
RM		 5038#ifdef CONFIG_B43_SSB
5039 case B43_BUS_SSB:
5040 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5041 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5042 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5043 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5044 } else
5045 B43_WARN_ON(1);
5046 break;
5047#endif
5048 }
e4d6b795 5049
96c755a3 5050 dev->phy.gmode = have_2ghz_phy;
fd4973c5 5051 dev->phy.radio_on = 1;
4da909e7 5052 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5053
5054 err = b43_phy_versioning(dev);
5055 if (err)
21954c36 5056 goto err_powerdown;
e4d6b795
MB		 5057 /* Check if this device supports multiband. */
5058 if (!pdev ||
5059 (pdev->device != 0x4312 &&
5060 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5061 /* No multiband support. */
96c755a3
MB		 5062 have_2ghz_phy = 0;
5063 have_5ghz_phy = 0;
e4d6b795
MB		 5064 switch (dev->phy.type) {
5065 case B43_PHYTYPE_A:
96c755a3 5066 have_5ghz_phy = 1;
e4d6b795 5067 break;
9d86a2d5 5068 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 5069#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 5070 have_5ghz_phy = 1;
86b2892a 5071#endif
e4d6b795 5072 case B43_PHYTYPE_G:
96c755a3 5073 case B43_PHYTYPE_N:
8b9bda75
RM		 5074 case B43_PHYTYPE_HT:
5075 case B43_PHYTYPE_LCN:
96c755a3 5076 have_2ghz_phy = 1;
e4d6b795
MB		 5077 break;
5078 default:
5079 B43_WARN_ON(1);
5080 }
5081 }
96c755a3
MB		 5082 if (dev->phy.type == B43_PHYTYPE_A) {
5083 /* FIXME */
5084 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5085 err = -EOPNOTSUPP;
5086 goto err_powerdown;
5087 }
2e35af14
MB		 5088 if (1 /* disable A-PHY */) {
5089 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 5090 if (dev->phy.type != B43_PHYTYPE_N &&
5091 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 5092 have_2ghz_phy = 1;
5093 have_5ghz_phy = 0;
5094 }
5095 }
5096
fb11137a
MB		 5097 err = b43_phy_allocate(dev);
5098 if (err)
5099 goto err_powerdown;
5100
96c755a3 5101 dev->phy.gmode = have_2ghz_phy;
4da909e7 5102 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5103
5104 err = b43_validate_chipaccess(dev);
5105 if (err)
fb11137a 5106 goto err_phy_free;
bb1eeff1 5107 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5108 if (err)
fb11137a 5109 goto err_phy_free;
e4d6b795
MB		 5110
5111 /* Now set some default "current_dev" */
5112 if (!wl->current_dev)
5113 wl->current_dev = dev;
5114 INIT_WORK(&dev->restart_work, b43_chip_reset);
5115
cb24f57f 5116 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5117 b43_device_disable(dev, 0);
5118 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5119
5120out:
5121 return err;
5122
fb11137a
MB		 5123err_phy_free:
5124 b43_phy_free(dev);
e4d6b795 5125err_powerdown:
24ca39d6 5126 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5127 return err;
5128}
5129
482f0538 5130static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5131{
5132 struct b43_wldev *wldev;
5133 struct b43_wl *wl;
5134
3bf0a32e
MB		 5135 /* Do not cancel ieee80211-workqueue based work here.
5136 * See comment in b43_remove(). */
5137
74abacb6 5138 wldev = b43_bus_get_wldev(dev);
e4d6b795 5139 wl = wldev->wl;
e4d6b795
MB		 5140 b43_debugfs_remove_device(wldev);
5141 b43_wireless_core_detach(wldev);
5142 list_del(&wldev->list);
5143 wl->nr_devs--;
74abacb6 5144 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5145 kfree(wldev);
5146}
5147
482f0538 5148static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5149{
5150 struct b43_wldev *wldev;
e4d6b795
MB		 5151 int err = -ENOMEM;
5152
e4d6b795
MB		 5153 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5154 if (!wldev)
5155 goto out;
5156
9e3bd919 5157 wldev->use_pio = b43_modparam_pio;
482f0538 5158 wldev->dev = dev;
e4d6b795
MB		 5159 wldev->wl = wl;
5160 b43_set_status(wldev, B43_STAT_UNINIT);
5161 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5162 INIT_LIST_HEAD(&wldev->list);
5163
5164 err = b43_wireless_core_attach(wldev);
5165 if (err)
5166 goto err_kfree_wldev;
5167
5168 list_add(&wldev->list, &wl->devlist);
5169 wl->nr_devs++;
74abacb6 5170 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5171 b43_debugfs_add_device(wldev);
5172
5173 out:
5174 return err;
5175
5176 err_kfree_wldev:
5177 kfree(wldev);
5178 return err;
5179}
5180
9fc38458
MB		 5181#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5182 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5183 (pdev->device == _device) && \
5184 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5185 (pdev->subsystem_device == _subdevice) )
5186
e4d6b795
MB		 5187static void b43_sprom_fixup(struct ssb_bus *bus)
5188{
1855ba78
MB		 5189 struct pci_dev *pdev;
5190
e4d6b795
MB		 5191 /* boardflags workarounds */
5192 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5193 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 5194 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 5195 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5196 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 5197 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5198 if (bus->bustype == SSB_BUSTYPE_PCI) {
5199 pdev = bus->host_pci;
9fc38458 5200 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5201 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5202 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5203 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5204 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5205 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5206 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5207 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5208 }
e4d6b795
MB		 5209}
5210
482f0538 5211static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5212{
5213 struct ieee80211_hw *hw = wl->hw;
5214
482f0538 5215 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5216 ieee80211_free_hw(hw);
5217}
5218
d1507051 5219static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5220{
d1507051 5221 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5222 struct ieee80211_hw *hw;
5223 struct b43_wl *wl;
2729df25 5224 char chip_name[6];
e4d6b795
MB		 5225
5226 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5227 if (!hw) {
5228 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5229 return ERR_PTR(-ENOMEM);
e4d6b795 5230 }
403a3a13 5231 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5232
5233 /* fill hw info */
605a0bd6 5234 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5235 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5236
f59ac048
LR		 5237 hw->wiphy->interface_modes =
5238 BIT(NL80211_IFTYPE_AP) |
5239 BIT(NL80211_IFTYPE_MESH_POINT) |
5240 BIT(NL80211_IFTYPE_STATION) |
5241 BIT(NL80211_IFTYPE_WDS) |
5242 BIT(NL80211_IFTYPE_ADHOC);
5243
403a3a13
MB		 5244 hw->queues = modparam_qos ? 4 : 1;
5245 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 5246 hw->max_rates = 2;
e4d6b795 5247 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5248 if (is_valid_ether_addr(sprom->et1mac))
5249 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5250 else
95de2841 5251 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5252
403a3a13 5253 /* Initialize struct b43_wl */
e4d6b795 5254 wl->hw = hw;
e4d6b795 5255 mutex_init(&wl->mutex);
36dbd954 5256 spin_lock_init(&wl->hardirq_lock);
e4d6b795 5257 INIT_LIST_HEAD(&wl->devlist);
a82d9922 5258 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5259 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed
MB		 5260 INIT_WORK(&wl->tx_work, b43_tx_work);
5261 skb_queue_head_init(&wl->tx_queue);
e4d6b795 5262
2729df25
RM		 5263 snprintf(chip_name, ARRAY_SIZE(chip_name),
5264 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5265 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5266 dev->core_rev);
0355a345 5267 return wl;
e4d6b795
MB		 5268}
5269
3c65ab62
RM		 5270#ifdef CONFIG_B43_BCMA
5271static int b43_bcma_probe(struct bcma_device *core)
5272{
397915c3 5273 struct b43_bus_dev *dev;
24aad3f4
RM		 5274 struct b43_wl *wl;
5275 int err;
397915c3
RM		 5276
5277 dev = b43_bus_dev_bcma_init(core);
5278 if (!dev)
5279 return -ENODEV;
5280
24aad3f4
RM		 5281 wl = b43_wireless_init(dev);
5282 if (IS_ERR(wl)) {
5283 err = PTR_ERR(wl);
5284 goto bcma_out;
5285 }
5286
5287 err = b43_one_core_attach(dev, wl);
5288 if (err)
5289 goto bcma_err_wireless_exit;
5290
5291 err = ieee80211_register_hw(wl->hw);
5292 if (err)
5293 goto bcma_err_one_core_detach;
5294 b43_leds_register(wl->current_dev);
5295
5296bcma_out:
5297 return err;
5298
5299bcma_err_one_core_detach:
5300 b43_one_core_detach(dev);
5301bcma_err_wireless_exit:
5302 ieee80211_free_hw(wl->hw);
5303 return err;
3c65ab62
RM		 5304}
5305
5306static void b43_bcma_remove(struct bcma_device *core)
5307{
24aad3f4
RM		 5308 struct b43_wldev *wldev = bcma_get_drvdata(core);
5309 struct b43_wl *wl = wldev->wl;
5310
5311 /* We must cancel any work here before unregistering from ieee80211,
5312 * as the ieee80211 unreg will destroy the workqueue. */
5313 cancel_work_sync(&wldev->restart_work);
5314
5315 /* Restore the queues count before unregistering, because firmware detect
5316 * might have modified it. Restoring is important, so the networking
5317 * stack can properly free resources. */
5318 wl->hw->queues = wl->mac80211_initially_registered_queues;
5319 b43_leds_stop(wldev);
5320 ieee80211_unregister_hw(wl->hw);
5321
5322 b43_one_core_detach(wldev->dev);
5323
5324 b43_leds_unregister(wl);
5325
5326 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5327}
5328
5329static struct bcma_driver b43_bcma_driver = {
5330 .name = KBUILD_MODNAME,
5331 .id_table = b43_bcma_tbl,
5332 .probe = b43_bcma_probe,
5333 .remove = b43_bcma_remove,
5334};
5335#endif
5336
aec7ffdf 5337#ifdef CONFIG_B43_SSB
aa63418a
RM		 5338static
5339int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5340{
482f0538 5341 struct b43_bus_dev *dev;
e4d6b795
MB		 5342 struct b43_wl *wl;
5343 int err;
5344 int first = 0;
5345
482f0538 5346 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5347 if (!dev)
5348 return -ENOMEM;
482f0538 5349
aa63418a 5350 wl = ssb_get_devtypedata(sdev);
e4d6b795
MB		 5351 if (!wl) {
5352 /* Probing the first core. Must setup common struct b43_wl */
5353 first = 1;
aa63418a 5354 b43_sprom_fixup(sdev->bus);
d1507051 5355 wl = b43_wireless_init(dev);
0355a345
RM		 5356 if (IS_ERR(wl)) {
5357 err = PTR_ERR(wl);
e4d6b795 5358 goto out;
0355a345 5359 }
aa63418a
RM		 5360 ssb_set_devtypedata(sdev, wl);
5361 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
e4d6b795
MB		 5362 }
5363 err = b43_one_core_attach(dev, wl);
5364 if (err)
5365 goto err_wireless_exit;
5366
5367 if (first) {
5368 err = ieee80211_register_hw(wl->hw);
5369 if (err)
5370 goto err_one_core_detach;
a78b3bb2 5371 b43_leds_register(wl->current_dev);
e4d6b795
MB		 5372 }
5373
5374 out:
5375 return err;
5376
5377 err_one_core_detach:
5378 b43_one_core_detach(dev);
5379 err_wireless_exit:
5380 if (first)
5381 b43_wireless_exit(dev, wl);
5382 return err;
5383}
5384
aa63418a 5385static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5386{
aa63418a
RM		 5387 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5388 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5389 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5390
3bf0a32e
MB		 5391 /* We must cancel any work here before unregistering from ieee80211,
5392 * as the ieee80211 unreg will destroy the workqueue. */
5393 cancel_work_sync(&wldev->restart_work);
5394
e4d6b795 5395 B43_WARN_ON(!wl);
403a3a13
MB		 5396 if (wl->current_dev == wldev) {
5397 /* Restore the queues count before unregistering, because firmware detect
5398 * might have modified it. Restoring is important, so the networking
5399 * stack can properly free resources. */
5400 wl->hw->queues = wl->mac80211_initially_registered_queues;
82905ace 5401 b43_leds_stop(wldev);
e4d6b795 5402 ieee80211_unregister_hw(wl->hw);
403a3a13 5403 }
e4d6b795 5404
e61b52d1 5405 b43_one_core_detach(dev);
e4d6b795
MB		 5406
5407 if (list_empty(&wl->devlist)) {
727c9885 5408 b43_leds_unregister(wl);
e4d6b795
MB		 5409 /* Last core on the chip unregistered.
5410 * We can destroy common struct b43_wl.
5411 */
e61b52d1 5412 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5413 }
5414}
5415
aec7ffdf
RM		 5416static struct ssb_driver b43_ssb_driver = {
5417 .name = KBUILD_MODNAME,
5418 .id_table = b43_ssb_tbl,
5419 .probe = b43_ssb_probe,
5420 .remove = b43_ssb_remove,
5421};
5422#endif /* CONFIG_B43_SSB */
5423
e4d6b795
MB		 5424/* Perform a hardware reset. This can be called from any context. */
5425void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5426{
5427 /* Must avoid requeueing, if we are in shutdown. */
5428 if (b43_status(dev) < B43_STAT_INITIALIZED)
5429 return;
5430 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5431 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5432}
5433
26bc783f
MB		 5434static void b43_print_driverinfo(void)
5435{
5436 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5437 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5438
5439#ifdef CONFIG_B43_PCI_AUTOSELECT
5440 feat_pci = "P";
5441#endif
5442#ifdef CONFIG_B43_PCMCIA
5443 feat_pcmcia = "M";
5444#endif
692d2c0f 5445#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5446 feat_nphy = "N";
5447#endif
5448#ifdef CONFIG_B43_LEDS
5449 feat_leds = "L";
3dbba8e2
AH		 5450#endif
5451#ifdef CONFIG_B43_SDIO
5452 feat_sdio = "S";
26bc783f
MB		 5453#endif
5454 printk(KERN_INFO "Broadcom 43xx driver loaded "
3dbba8e2 5455 "[ Features: %s%s%s%s%s, Firmware-ID: "
26bc783f
MB		 5456 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5457 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5458 feat_leds, feat_sdio);
26bc783f
MB		 5459}
5460
e4d6b795
MB		 5461static int __init b43_init(void)
5462{
5463 int err;
5464
5465 b43_debugfs_init();
5466 err = b43_pcmcia_init();
5467 if (err)
5468 goto err_dfs_exit;
3dbba8e2 5469 err = b43_sdio_init();
e4d6b795
MB		 5470 if (err)
5471 goto err_pcmcia_exit;
3c65ab62
RM		 5472#ifdef CONFIG_B43_BCMA
5473 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5474 if (err)
5475 goto err_sdio_exit;
3c65ab62 5476#endif
aec7ffdf 5477#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5478 err = ssb_driver_register(&b43_ssb_driver);
5479 if (err)
5480 goto err_bcma_driver_exit;
aec7ffdf 5481#endif
26bc783f 5482 b43_print_driverinfo();
e4d6b795
MB		 5483
5484 return err;
5485
aec7ffdf 5486#ifdef CONFIG_B43_SSB
3c65ab62 5487err_bcma_driver_exit:
aec7ffdf 5488#endif
3c65ab62
RM		 5489#ifdef CONFIG_B43_BCMA
5490 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5491err_sdio_exit:
3c65ab62 5492#endif
3dbba8e2 5493 b43_sdio_exit();
e4d6b795
MB		 5494err_pcmcia_exit:
5495 b43_pcmcia_exit();
5496err_dfs_exit:
5497 b43_debugfs_exit();
5498 return err;
5499}
5500
5501static void __exit b43_exit(void)
5502{
aec7ffdf 5503#ifdef CONFIG_B43_SSB
e4d6b795 5504 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5505#endif
3c65ab62
RM		 5506#ifdef CONFIG_B43_BCMA
5507 bcma_driver_unregister(&b43_bcma_driver);
5508#endif
3dbba8e2 5509 b43_sdio_exit();
e4d6b795
MB		 5510 b43_pcmcia_exit();
5511 b43_debugfs_exit();
5512}
5513
5514module_init(b43_init)
5515module_exit(b43_exit)
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