]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/net/wireless/b43/main.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add rtl8180 wireless driver
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
47#include "phy.h"
48#include "dma.h"
e4d6b795
MB		 49#include "sysfs.h"
50#include "xmit.h"
e4d6b795
MB		 51#include "lo.h"
52#include "pcmcia.h"
53
54MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55MODULE_AUTHOR("Martin Langer");
56MODULE_AUTHOR("Stefano Brivio");
57MODULE_AUTHOR("Michael Buesch");
58MODULE_LICENSE("GPL");
59
e4d6b795
MB		 60
61static int modparam_bad_frames_preempt;
62module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
63MODULE_PARM_DESC(bad_frames_preempt,
64 "enable(1) / disable(0) Bad Frames Preemption");
65
e4d6b795
MB		 66static char modparam_fwpostfix[16];
67module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
68MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
69
e4d6b795
MB		 70static int modparam_hwpctl;
71module_param_named(hwpctl, modparam_hwpctl, int, 0444);
72MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
73
74static int modparam_nohwcrypt;
75module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
76MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
77
78static const struct ssb_device_id b43_ssb_tbl[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
e4d6b795
MB		 86 SSB_DEVTABLE_END
87};
88
89MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
90
91/* Channel and ratetables are shared for all devices.
92 * They can't be const, because ieee80211 puts some precalculated
93 * data in there. This data is the same for all devices, so we don't
94 * get concurrency issues */
95#define RATETAB_ENT(_rateid, _flags) \
96 { \
97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
98 .val = (_rateid), \
99 .val2 = (_rateid), \
100 .flags = (_flags), \
101 }
102static struct ieee80211_rate __b43_ratetable[] = {
103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
115};
116
117#define b43_a_ratetable (__b43_ratetable + 4)
118#define b43_a_ratetable_size 8
119#define b43_b_ratetable (__b43_ratetable + 0)
120#define b43_b_ratetable_size 4
121#define b43_g_ratetable (__b43_ratetable + 0)
122#define b43_g_ratetable_size 12
123
124#define CHANTAB_ENT(_chanid, _freq) \
125 { \
126 .chan = (_chanid), \
127 .freq = (_freq), \
128 .val = (_chanid), \
129 .flag = IEEE80211_CHAN_W_SCAN | \
130 IEEE80211_CHAN_W_ACTIVE_SCAN | \
131 IEEE80211_CHAN_W_IBSS, \
132 .power_level = 0xFF, \
133 .antenna_max = 0xFF, \
134 }
96c755a3 135static struct ieee80211_channel b43_2ghz_chantable[] = {
e4d6b795
MB		 136 CHANTAB_ENT(1, 2412),
137 CHANTAB_ENT(2, 2417),
138 CHANTAB_ENT(3, 2422),
139 CHANTAB_ENT(4, 2427),
140 CHANTAB_ENT(5, 2432),
141 CHANTAB_ENT(6, 2437),
142 CHANTAB_ENT(7, 2442),
143 CHANTAB_ENT(8, 2447),
144 CHANTAB_ENT(9, 2452),
145 CHANTAB_ENT(10, 2457),
146 CHANTAB_ENT(11, 2462),
147 CHANTAB_ENT(12, 2467),
148 CHANTAB_ENT(13, 2472),
149 CHANTAB_ENT(14, 2484),
150};
96c755a3 151#define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
e4d6b795 152
96c755a3
MB		 153#if 0
154static struct ieee80211_channel b43_5ghz_chantable[] = {
e4d6b795
MB		 155 CHANTAB_ENT(36, 5180),
156 CHANTAB_ENT(40, 5200),
157 CHANTAB_ENT(44, 5220),
158 CHANTAB_ENT(48, 5240),
159 CHANTAB_ENT(52, 5260),
160 CHANTAB_ENT(56, 5280),
161 CHANTAB_ENT(60, 5300),
162 CHANTAB_ENT(64, 5320),
163 CHANTAB_ENT(149, 5745),
164 CHANTAB_ENT(153, 5765),
165 CHANTAB_ENT(157, 5785),
166 CHANTAB_ENT(161, 5805),
167 CHANTAB_ENT(165, 5825),
168};
96c755a3
MB		 169#define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
170#endif
e4d6b795
MB		 171
172static void b43_wireless_core_exit(struct b43_wldev *dev);
173static int b43_wireless_core_init(struct b43_wldev *dev);
174static void b43_wireless_core_stop(struct b43_wldev *dev);
175static int b43_wireless_core_start(struct b43_wldev *dev);
176
177static int b43_ratelimit(struct b43_wl *wl)
178{
179 if (!wl || !wl->current_dev)
180 return 1;
181 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
182 return 1;
183 /* We are up and running.
184 * Ratelimit the messages to avoid DoS over the net. */
185 return net_ratelimit();
186}
187
188void b43info(struct b43_wl *wl, const char *fmt, ...)
189{
190 va_list args;
191
192 if (!b43_ratelimit(wl))
193 return;
194 va_start(args, fmt);
195 printk(KERN_INFO "b43-%s: ",
196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
197 vprintk(fmt, args);
198 va_end(args);
199}
200
201void b43err(struct b43_wl *wl, const char *fmt, ...)
202{
203 va_list args;
204
205 if (!b43_ratelimit(wl))
206 return;
207 va_start(args, fmt);
208 printk(KERN_ERR "b43-%s ERROR: ",
209 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
210 vprintk(fmt, args);
211 va_end(args);
212}
213
214void b43warn(struct b43_wl *wl, const char *fmt, ...)
215{
216 va_list args;
217
218 if (!b43_ratelimit(wl))
219 return;
220 va_start(args, fmt);
221 printk(KERN_WARNING "b43-%s warning: ",
222 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
223 vprintk(fmt, args);
224 va_end(args);
225}
226
227#if B43_DEBUG
228void b43dbg(struct b43_wl *wl, const char *fmt, ...)
229{
230 va_list args;
231
232 va_start(args, fmt);
233 printk(KERN_DEBUG "b43-%s debug: ",
234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
235 vprintk(fmt, args);
236 va_end(args);
237}
238#endif /* DEBUG */
239
240static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
241{
242 u32 macctl;
243
244 B43_WARN_ON(offset % 4 != 0);
245
246 macctl = b43_read32(dev, B43_MMIO_MACCTL);
247 if (macctl & B43_MACCTL_BE)
248 val = swab32(val);
249
250 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
251 mmiowb();
252 b43_write32(dev, B43_MMIO_RAM_DATA, val);
253}
254
255static inline
256 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
257{
258 u32 control;
259
260 /* "offset" is the WORD offset. */
261
262 control = routing;
263 control <<= 16;
264 control |= offset;
265 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
266}
267
268u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
269{
270 u32 ret;
271
272 if (routing == B43_SHM_SHARED) {
273 B43_WARN_ON(offset & 0x0001);
274 if (offset & 0x0003) {
275 /* Unaligned access */
276 b43_shm_control_word(dev, routing, offset >> 2);
277 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
278 ret <<= 16;
279 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
280 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
281
282 return ret;
283 }
284 offset >>= 2;
285 }
286 b43_shm_control_word(dev, routing, offset);
287 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
288
289 return ret;
290}
291
292u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
293{
294 u16 ret;
295
296 if (routing == B43_SHM_SHARED) {
297 B43_WARN_ON(offset & 0x0001);
298 if (offset & 0x0003) {
299 /* Unaligned access */
300 b43_shm_control_word(dev, routing, offset >> 2);
301 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
302
303 return ret;
304 }
305 offset >>= 2;
306 }
307 b43_shm_control_word(dev, routing, offset);
308 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
309
310 return ret;
311}
312
313void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
314{
315 if (routing == B43_SHM_SHARED) {
316 B43_WARN_ON(offset & 0x0001);
317 if (offset & 0x0003) {
318 /* Unaligned access */
319 b43_shm_control_word(dev, routing, offset >> 2);
320 mmiowb();
321 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
322 (value >> 16) & 0xffff);
323 mmiowb();
324 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
325 mmiowb();
326 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
327 return;
328 }
329 offset >>= 2;
330 }
331 b43_shm_control_word(dev, routing, offset);
332 mmiowb();
333 b43_write32(dev, B43_MMIO_SHM_DATA, value);
334}
335
336void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
337{
338 if (routing == B43_SHM_SHARED) {
339 B43_WARN_ON(offset & 0x0001);
340 if (offset & 0x0003) {
341 /* Unaligned access */
342 b43_shm_control_word(dev, routing, offset >> 2);
343 mmiowb();
344 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
345 return;
346 }
347 offset >>= 2;
348 }
349 b43_shm_control_word(dev, routing, offset);
350 mmiowb();
351 b43_write16(dev, B43_MMIO_SHM_DATA, value);
352}
353
354/* Read HostFlags */
355u32 b43_hf_read(struct b43_wldev * dev)
356{
357 u32 ret;
358
359 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
360 ret <<= 16;
361 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
362
363 return ret;
364}
365
366/* Write HostFlags */
367void b43_hf_write(struct b43_wldev *dev, u32 value)
368{
369 b43_shm_write16(dev, B43_SHM_SHARED,
370 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
371 b43_shm_write16(dev, B43_SHM_SHARED,
372 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
373}
374
375void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
376{
377 /* We need to be careful. As we read the TSF from multiple
378 * registers, we should take care of register overflows.
379 * In theory, the whole tsf read process should be atomic.
380 * We try to be atomic here, by restaring the read process,
381 * if any of the high registers changed (overflew).
382 */
383 if (dev->dev->id.revision >= 3) {
384 u32 low, high, high2;
385
386 do {
387 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
388 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
389 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
390 } while (unlikely(high != high2));
391
392 *tsf = high;
393 *tsf <<= 32;
394 *tsf |= low;
395 } else {
396 u64 tmp;
397 u16 v0, v1, v2, v3;
398 u16 test1, test2, test3;
399
400 do {
401 v3 = b43_read16(dev, B43_MMIO_TSF_3);
402 v2 = b43_read16(dev, B43_MMIO_TSF_2);
403 v1 = b43_read16(dev, B43_MMIO_TSF_1);
404 v0 = b43_read16(dev, B43_MMIO_TSF_0);
405
406 test3 = b43_read16(dev, B43_MMIO_TSF_3);
407 test2 = b43_read16(dev, B43_MMIO_TSF_2);
408 test1 = b43_read16(dev, B43_MMIO_TSF_1);
409 } while (v3 != test3 || v2 != test2 || v1 != test1);
410
411 *tsf = v3;
412 *tsf <<= 48;
413 tmp = v2;
414 tmp <<= 32;
415 *tsf |= tmp;
416 tmp = v1;
417 tmp <<= 16;
418 *tsf |= tmp;
419 *tsf |= v0;
420 }
421}
422
423static void b43_time_lock(struct b43_wldev *dev)
424{
425 u32 macctl;
426
427 macctl = b43_read32(dev, B43_MMIO_MACCTL);
428 macctl |= B43_MACCTL_TBTTHOLD;
429 b43_write32(dev, B43_MMIO_MACCTL, macctl);
430 /* Commit the write */
431 b43_read32(dev, B43_MMIO_MACCTL);
432}
433
434static void b43_time_unlock(struct b43_wldev *dev)
435{
436 u32 macctl;
437
438 macctl = b43_read32(dev, B43_MMIO_MACCTL);
439 macctl &= ~B43_MACCTL_TBTTHOLD;
440 b43_write32(dev, B43_MMIO_MACCTL, macctl);
441 /* Commit the write */
442 b43_read32(dev, B43_MMIO_MACCTL);
443}
444
445static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
446{
447 /* Be careful with the in-progress timer.
448 * First zero out the low register, so we have a full
449 * register-overflow duration to complete the operation.
450 */
451 if (dev->dev->id.revision >= 3) {
452 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
453 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
454
455 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
456 mmiowb();
457 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
458 mmiowb();
459 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
460 } else {
461 u16 v0 = (tsf & 0x000000000000FFFFULL);
462 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
463 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
464 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
465
466 b43_write16(dev, B43_MMIO_TSF_0, 0);
467 mmiowb();
468 b43_write16(dev, B43_MMIO_TSF_3, v3);
469 mmiowb();
470 b43_write16(dev, B43_MMIO_TSF_2, v2);
471 mmiowb();
472 b43_write16(dev, B43_MMIO_TSF_1, v1);
473 mmiowb();
474 b43_write16(dev, B43_MMIO_TSF_0, v0);
475 }
476}
477
478void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
479{
480 b43_time_lock(dev);
481 b43_tsf_write_locked(dev, tsf);
482 b43_time_unlock(dev);
483}
484
485static
486void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
487{
488 static const u8 zero_addr[ETH_ALEN] = { 0 };
489 u16 data;
490
491 if (!mac)
492 mac = zero_addr;
493
494 offset |= 0x0020;
495 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
496
497 data = mac[0];
498 data |= mac[1] << 8;
499 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
500 data = mac[2];
501 data |= mac[3] << 8;
502 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
503 data = mac[4];
504 data |= mac[5] << 8;
505 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
506}
507
508static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
509{
510 const u8 *mac;
511 const u8 *bssid;
512 u8 mac_bssid[ETH_ALEN * 2];
513 int i;
514 u32 tmp;
515
516 bssid = dev->wl->bssid;
517 mac = dev->wl->mac_addr;
518
519 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
520
521 memcpy(mac_bssid, mac, ETH_ALEN);
522 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
523
524 /* Write our MAC address and BSSID to template ram */
525 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
526 tmp = (u32) (mac_bssid[i + 0]);
527 tmp |= (u32) (mac_bssid[i + 1]) << 8;
528 tmp |= (u32) (mac_bssid[i + 2]) << 16;
529 tmp |= (u32) (mac_bssid[i + 3]) << 24;
530 b43_ram_write(dev, 0x20 + i, tmp);
531 }
532}
533
4150c572 534static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 535{
e4d6b795 536 b43_write_mac_bssid_templates(dev);
4150c572 537 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 538}
539
540static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
541{
542 /* slot_time is in usec. */
543 if (dev->phy.type != B43_PHYTYPE_G)
544 return;
545 b43_write16(dev, 0x684, 510 + slot_time);
546 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
547}
548
549static void b43_short_slot_timing_enable(struct b43_wldev *dev)
550{
551 b43_set_slot_time(dev, 9);
552 dev->short_slot = 1;
553}
554
555static void b43_short_slot_timing_disable(struct b43_wldev *dev)
556{
557 b43_set_slot_time(dev, 20);
558 dev->short_slot = 0;
559}
560
561/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
562 * Returns the _previously_ enabled IRQ mask.
563 */
564static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
565{
566 u32 old_mask;
567
568 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
569 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
570
571 return old_mask;
572}
573
574/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
575 * Returns the _previously_ enabled IRQ mask.
576 */
577static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
578{
579 u32 old_mask;
580
581 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
582 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
583
584 return old_mask;
585}
586
587/* Synchronize IRQ top- and bottom-half.
588 * IRQs must be masked before calling this.
589 * This must not be called with the irq_lock held.
590 */
591static void b43_synchronize_irq(struct b43_wldev *dev)
592{
593 synchronize_irq(dev->dev->irq);
594 tasklet_kill(&dev->isr_tasklet);
595}
596
597/* DummyTransmission function, as documented on
598 * http://bcm-specs.sipsolutions.net/DummyTransmission
599 */
600void b43_dummy_transmission(struct b43_wldev *dev)
601{
602 struct b43_phy *phy = &dev->phy;
603 unsigned int i, max_loop;
604 u16 value;
605 u32 buffer[5] = {
606 0x00000000,
607 0x00D40000,
608 0x00000000,
609 0x01000000,
610 0x00000000,
611 };
612
613 switch (phy->type) {
614 case B43_PHYTYPE_A:
615 max_loop = 0x1E;
616 buffer[0] = 0x000201CC;
617 break;
618 case B43_PHYTYPE_B:
619 case B43_PHYTYPE_G:
620 max_loop = 0xFA;
621 buffer[0] = 0x000B846E;
622 break;
623 default:
624 B43_WARN_ON(1);
625 return;
626 }
627
628 for (i = 0; i < 5; i++)
629 b43_ram_write(dev, i * 4, buffer[i]);
630
631 /* Commit writes */
632 b43_read32(dev, B43_MMIO_MACCTL);
633
634 b43_write16(dev, 0x0568, 0x0000);
635 b43_write16(dev, 0x07C0, 0x0000);
636 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
637 b43_write16(dev, 0x050C, value);
638 b43_write16(dev, 0x0508, 0x0000);
639 b43_write16(dev, 0x050A, 0x0000);
640 b43_write16(dev, 0x054C, 0x0000);
641 b43_write16(dev, 0x056A, 0x0014);
642 b43_write16(dev, 0x0568, 0x0826);
643 b43_write16(dev, 0x0500, 0x0000);
644 b43_write16(dev, 0x0502, 0x0030);
645
646 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
647 b43_radio_write16(dev, 0x0051, 0x0017);
648 for (i = 0x00; i < max_loop; i++) {
649 value = b43_read16(dev, 0x050E);
650 if (value & 0x0080)
651 break;
652 udelay(10);
653 }
654 for (i = 0x00; i < 0x0A; i++) {
655 value = b43_read16(dev, 0x050E);
656 if (value & 0x0400)
657 break;
658 udelay(10);
659 }
660 for (i = 0x00; i < 0x0A; i++) {
661 value = b43_read16(dev, 0x0690);
662 if (!(value & 0x0100))
663 break;
664 udelay(10);
665 }
666 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
667 b43_radio_write16(dev, 0x0051, 0x0037);
668}
669
670static void key_write(struct b43_wldev *dev,
671 u8 index, u8 algorithm, const u8 * key)
672{
673 unsigned int i;
674 u32 offset;
675 u16 value;
676 u16 kidx;
677
678 /* Key index/algo block */
679 kidx = b43_kidx_to_fw(dev, index);
680 value = ((kidx << 4) | algorithm);
681 b43_shm_write16(dev, B43_SHM_SHARED,
682 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
683
684 /* Write the key to the Key Table Pointer offset */
685 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
686 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
687 value = key[i];
688 value |= (u16) (key[i + 1]) << 8;
689 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
690 }
691}
692
693static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
694{
695 u32 addrtmp[2] = { 0, 0, };
696 u8 per_sta_keys_start = 8;
697
698 if (b43_new_kidx_api(dev))
699 per_sta_keys_start = 4;
700
701 B43_WARN_ON(index < per_sta_keys_start);
702 /* We have two default TX keys and possibly two default RX keys.
703 * Physical mac 0 is mapped to physical key 4 or 8, depending
704 * on the firmware version.
705 * So we must adjust the index here.
706 */
707 index -= per_sta_keys_start;
708
709 if (addr) {
710 addrtmp[0] = addr[0];
711 addrtmp[0] |= ((u32) (addr[1]) << 8);
712 addrtmp[0] |= ((u32) (addr[2]) << 16);
713 addrtmp[0] |= ((u32) (addr[3]) << 24);
714 addrtmp[1] = addr[4];
715 addrtmp[1] |= ((u32) (addr[5]) << 8);
716 }
717
718 if (dev->dev->id.revision >= 5) {
719 /* Receive match transmitter address mechanism */
720 b43_shm_write32(dev, B43_SHM_RCMTA,
721 (index * 2) + 0, addrtmp[0]);
722 b43_shm_write16(dev, B43_SHM_RCMTA,
723 (index * 2) + 1, addrtmp[1]);
724 } else {
725 /* RXE (Receive Engine) and
726 * PSM (Programmable State Machine) mechanism
727 */
728 if (index < 8) {
729 /* TODO write to RCM 16, 19, 22 and 25 */
730 } else {
731 b43_shm_write32(dev, B43_SHM_SHARED,
732 B43_SHM_SH_PSM + (index * 6) + 0,
733 addrtmp[0]);
734 b43_shm_write16(dev, B43_SHM_SHARED,
735 B43_SHM_SH_PSM + (index * 6) + 4,
736 addrtmp[1]);
737 }
738 }
739}
740
741static void do_key_write(struct b43_wldev *dev,
742 u8 index, u8 algorithm,
743 const u8 * key, size_t key_len, const u8 * mac_addr)
744{
745 u8 buf[B43_SEC_KEYSIZE] = { 0, };
746 u8 per_sta_keys_start = 8;
747
748 if (b43_new_kidx_api(dev))
749 per_sta_keys_start = 4;
750
751 B43_WARN_ON(index >= dev->max_nr_keys);
752 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
753
754 if (index >= per_sta_keys_start)
755 keymac_write(dev, index, NULL); /* First zero out mac. */
756 if (key)
757 memcpy(buf, key, key_len);
758 key_write(dev, index, algorithm, buf);
759 if (index >= per_sta_keys_start)
760 keymac_write(dev, index, mac_addr);
761
762 dev->key[index].algorithm = algorithm;
763}
764
765static int b43_key_write(struct b43_wldev *dev,
766 int index, u8 algorithm,
767 const u8 * key, size_t key_len,
768 const u8 * mac_addr,
769 struct ieee80211_key_conf *keyconf)
770{
771 int i;
772 int sta_keys_start;
773
774 if (key_len > B43_SEC_KEYSIZE)
775 return -EINVAL;
776 for (i = 0; i < dev->max_nr_keys; i++) {
777 /* Check that we don't already have this key. */
778 B43_WARN_ON(dev->key[i].keyconf == keyconf);
779 }
780 if (index < 0) {
781 /* Either pairwise key or address is 00:00:00:00:00:00
782 * for transmit-only keys. Search the index. */
783 if (b43_new_kidx_api(dev))
784 sta_keys_start = 4;
785 else
786 sta_keys_start = 8;
787 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
788 if (!dev->key[i].keyconf) {
789 /* found empty */
790 index = i;
791 break;
792 }
793 }
794 if (index < 0) {
795 b43err(dev->wl, "Out of hardware key memory\n");
796 return -ENOSPC;
797 }
798 } else
799 B43_WARN_ON(index > 3);
800
801 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
802 if ((index <= 3) && !b43_new_kidx_api(dev)) {
803 /* Default RX key */
804 B43_WARN_ON(mac_addr);
805 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
806 }
807 keyconf->hw_key_idx = index;
808 dev->key[index].keyconf = keyconf;
809
810 return 0;
811}
812
813static int b43_key_clear(struct b43_wldev *dev, int index)
814{
815 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
816 return -EINVAL;
817 do_key_write(dev, index, B43_SEC_ALGO_NONE,
818 NULL, B43_SEC_KEYSIZE, NULL);
819 if ((index <= 3) && !b43_new_kidx_api(dev)) {
820 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
821 NULL, B43_SEC_KEYSIZE, NULL);
822 }
823 dev->key[index].keyconf = NULL;
824
825 return 0;
826}
827
828static void b43_clear_keys(struct b43_wldev *dev)
829{
830 int i;
831
832 for (i = 0; i < dev->max_nr_keys; i++)
833 b43_key_clear(dev, i);
834}
835
836void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
837{
838 u32 macctl;
839 u16 ucstat;
840 bool hwps;
841 bool awake;
842 int i;
843
844 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
845 (ps_flags & B43_PS_DISABLED));
846 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
847
848 if (ps_flags & B43_PS_ENABLED) {
849 hwps = 1;
850 } else if (ps_flags & B43_PS_DISABLED) {
851 hwps = 0;
852 } else {
853 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
854 // and thus is not an AP and we are associated, set bit 25
855 }
856 if (ps_flags & B43_PS_AWAKE) {
857 awake = 1;
858 } else if (ps_flags & B43_PS_ASLEEP) {
859 awake = 0;
860 } else {
861 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
862 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
863 // successful, set bit26
864 }
865
866/* FIXME: For now we force awake-on and hwps-off */
867 hwps = 0;
868 awake = 1;
869
870 macctl = b43_read32(dev, B43_MMIO_MACCTL);
871 if (hwps)
872 macctl |= B43_MACCTL_HWPS;
873 else
874 macctl &= ~B43_MACCTL_HWPS;
875 if (awake)
876 macctl |= B43_MACCTL_AWAKE;
877 else
878 macctl &= ~B43_MACCTL_AWAKE;
879 b43_write32(dev, B43_MMIO_MACCTL, macctl);
880 /* Commit write */
881 b43_read32(dev, B43_MMIO_MACCTL);
882 if (awake && dev->dev->id.revision >= 5) {
883 /* Wait for the microcode to wake up. */
884 for (i = 0; i < 100; i++) {
885 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
886 B43_SHM_SH_UCODESTAT);
887 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
888 break;
889 udelay(10);
890 }
891 }
892}
893
894/* Turn the Analog ON/OFF */
895static void b43_switch_analog(struct b43_wldev *dev, int on)
896{
897 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
898}
899
900void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
901{
902 u32 tmslow;
903 u32 macctl;
904
905 flags |= B43_TMSLOW_PHYCLKEN;
906 flags |= B43_TMSLOW_PHYRESET;
907 ssb_device_enable(dev->dev, flags);
908 msleep(2); /* Wait for the PLL to turn on. */
909
910 /* Now take the PHY out of Reset again */
911 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
912 tmslow |= SSB_TMSLOW_FGC;
913 tmslow &= ~B43_TMSLOW_PHYRESET;
914 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
915 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
916 msleep(1);
917 tmslow &= ~SSB_TMSLOW_FGC;
918 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
919 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
920 msleep(1);
921
922 /* Turn Analog ON */
923 b43_switch_analog(dev, 1);
924
925 macctl = b43_read32(dev, B43_MMIO_MACCTL);
926 macctl &= ~B43_MACCTL_GMODE;
927 if (flags & B43_TMSLOW_GMODE)
928 macctl |= B43_MACCTL_GMODE;
929 macctl |= B43_MACCTL_IHR_ENABLED;
930 b43_write32(dev, B43_MMIO_MACCTL, macctl);
931}
932
933static void handle_irq_transmit_status(struct b43_wldev *dev)
934{
935 u32 v0, v1;
936 u16 tmp;
937 struct b43_txstatus stat;
938
939 while (1) {
940 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
941 if (!(v0 & 0x00000001))
942 break;
943 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
944
945 stat.cookie = (v0 >> 16);
946 stat.seq = (v1 & 0x0000FFFF);
947 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
948 tmp = (v0 & 0x0000FFFF);
949 stat.frame_count = ((tmp & 0xF000) >> 12);
950 stat.rts_count = ((tmp & 0x0F00) >> 8);
951 stat.supp_reason = ((tmp & 0x001C) >> 2);
952 stat.pm_indicated = !!(tmp & 0x0080);
953 stat.intermediate = !!(tmp & 0x0040);
954 stat.for_ampdu = !!(tmp & 0x0020);
955 stat.acked = !!(tmp & 0x0002);
956
957 b43_handle_txstatus(dev, &stat);
958 }
959}
960
961static void drain_txstatus_queue(struct b43_wldev *dev)
962{
963 u32 dummy;
964
965 if (dev->dev->id.revision < 5)
966 return;
967 /* Read all entries from the microcode TXstatus FIFO
968 * and throw them away.
969 */
970 while (1) {
971 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
972 if (!(dummy & 0x00000001))
973 break;
974 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
975 }
976}
977
978static u32 b43_jssi_read(struct b43_wldev *dev)
979{
980 u32 val = 0;
981
982 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
983 val <<= 16;
984 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
985
986 return val;
987}
988
989static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
990{
991 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
992 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
993}
994
995static void b43_generate_noise_sample(struct b43_wldev *dev)
996{
997 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 998 b43_write32(dev, B43_MMIO_MACCMD,
999 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1000 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1001}
1002
1003static void b43_calculate_link_quality(struct b43_wldev *dev)
1004{
1005 /* Top half of Link Quality calculation. */
1006
1007 if (dev->noisecalc.calculation_running)
1008 return;
1009 dev->noisecalc.channel_at_start = dev->phy.channel;
1010 dev->noisecalc.calculation_running = 1;
1011 dev->noisecalc.nr_samples = 0;
1012
1013 b43_generate_noise_sample(dev);
1014}
1015
1016static void handle_irq_noise(struct b43_wldev *dev)
1017{
1018 struct b43_phy *phy = &dev->phy;
1019 u16 tmp;
1020 u8 noise[4];
1021 u8 i, j;
1022 s32 average;
1023
1024 /* Bottom half of Link Quality calculation. */
1025
1026 B43_WARN_ON(!dev->noisecalc.calculation_running);
1027 if (dev->noisecalc.channel_at_start != phy->channel)
1028 goto drop_calculation;
1a09404a 1029 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1030 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1031 noise[2] == 0x7F || noise[3] == 0x7F)
1032 goto generate_new;
1033
1034 /* Get the noise samples. */
1035 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1036 i = dev->noisecalc.nr_samples;
1037 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1038 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1039 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1040 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1041 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1042 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1043 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1044 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1045 dev->noisecalc.nr_samples++;
1046 if (dev->noisecalc.nr_samples == 8) {
1047 /* Calculate the Link Quality by the noise samples. */
1048 average = 0;
1049 for (i = 0; i < 8; i++) {
1050 for (j = 0; j < 4; j++)
1051 average += dev->noisecalc.samples[i][j];
1052 }
1053 average /= (8 * 4);
1054 average *= 125;
1055 average += 64;
1056 average /= 128;
1057 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1058 tmp = (tmp / 128) & 0x1F;
1059 if (tmp >= 8)
1060 average += 2;
1061 else
1062 average -= 25;
1063 if (tmp == 8)
1064 average -= 72;
1065 else
1066 average -= 48;
1067
1068 dev->stats.link_noise = average;
1069 drop_calculation:
1070 dev->noisecalc.calculation_running = 0;
1071 return;
1072 }
1073 generate_new:
1074 b43_generate_noise_sample(dev);
1075}
1076
1077static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1078{
1079 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1080 ///TODO: PS TBTT
1081 } else {
1082 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1083 b43_power_saving_ctl_bits(dev, 0);
1084 }
e4d6b795 1085 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
aa6c7ae2 1086 dev->dfq_valid = 1;
e4d6b795
MB		 1087}
1088
1089static void handle_irq_atim_end(struct b43_wldev *dev)
1090{
aa6c7ae2
MB		 1091 if (dev->dfq_valid) {
1092 b43_write32(dev, B43_MMIO_MACCMD,
1093 b43_read32(dev, B43_MMIO_MACCMD)
1094 | B43_MACCMD_DFQ_VALID);
1095 dev->dfq_valid = 0;
1096 }
e4d6b795
MB		 1097}
1098
1099static void handle_irq_pmq(struct b43_wldev *dev)
1100{
1101 u32 tmp;
1102
1103 //TODO: AP mode.
1104
1105 while (1) {
1106 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1107 if (!(tmp & 0x00000008))
1108 break;
1109 }
1110 /* 16bit write is odd, but correct. */
1111 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1112}
1113
1114static void b43_write_template_common(struct b43_wldev *dev,
1115 const u8 * data, u16 size,
1116 u16 ram_offset,
1117 u16 shm_size_offset, u8 rate)
1118{
1119 u32 i, tmp;
1120 struct b43_plcp_hdr4 plcp;
1121
1122 plcp.data = 0;
1123 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1124 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1125 ram_offset += sizeof(u32);
1126 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1127 * So leave the first two bytes of the next write blank.
1128 */
1129 tmp = (u32) (data[0]) << 16;
1130 tmp |= (u32) (data[1]) << 24;
1131 b43_ram_write(dev, ram_offset, tmp);
1132 ram_offset += sizeof(u32);
1133 for (i = 2; i < size; i += sizeof(u32)) {
1134 tmp = (u32) (data[i + 0]);
1135 if (i + 1 < size)
1136 tmp |= (u32) (data[i + 1]) << 8;
1137 if (i + 2 < size)
1138 tmp |= (u32) (data[i + 2]) << 16;
1139 if (i + 3 < size)
1140 tmp |= (u32) (data[i + 3]) << 24;
1141 b43_ram_write(dev, ram_offset + i - 2, tmp);
1142 }
1143 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1144 size + sizeof(struct b43_plcp_hdr6));
1145}
1146
1147static void b43_write_beacon_template(struct b43_wldev *dev,
1148 u16 ram_offset,
1149 u16 shm_size_offset, u8 rate)
1150{
1151 int len;
1152 const u8 *data;
1153
1154 B43_WARN_ON(!dev->cached_beacon);
1155 len = min((size_t) dev->cached_beacon->len,
1156 0x200 - sizeof(struct b43_plcp_hdr6));
1157 data = (const u8 *)(dev->cached_beacon->data);
1158 b43_write_template_common(dev, data,
1159 len, ram_offset, shm_size_offset, rate);
1160}
1161
1162static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1163 u16 shm_offset, u16 size, u8 rate)
1164{
1165 struct b43_plcp_hdr4 plcp;
1166 u32 tmp;
1167 __le16 dur;
1168
1169 plcp.data = 0;
1170 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1171 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1172 dev->wl->if_id, size,
1173 B43_RATE_TO_BASE100KBPS(rate));
1174 /* Write PLCP in two parts and timing for packet transfer */
1175 tmp = le32_to_cpu(plcp.data);
1176 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1177 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1178 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1179}
1180
1181/* Instead of using custom probe response template, this function
1182 * just patches custom beacon template by:
1183 * 1) Changing packet type
1184 * 2) Patching duration field
1185 * 3) Stripping TIM
1186 */
1187static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1188 u16 * dest_size, u8 rate)
1189{
1190 const u8 *src_data;
1191 u8 *dest_data;
1192 u16 src_size, elem_size, src_pos, dest_pos;
1193 __le16 dur;
1194 struct ieee80211_hdr *hdr;
1195
1196 B43_WARN_ON(!dev->cached_beacon);
1197 src_size = dev->cached_beacon->len;
1198 src_data = (const u8 *)dev->cached_beacon->data;
1199
1200 if (unlikely(src_size < 0x24)) {
1201 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1202 return NULL;
1203 }
1204
1205 dest_data = kmalloc(src_size, GFP_ATOMIC);
1206 if (unlikely(!dest_data))
1207 return NULL;
1208
1209 /* 0x24 is offset of first variable-len Information-Element
1210 * in beacon frame.
1211 */
1212 memcpy(dest_data, src_data, 0x24);
1213 src_pos = dest_pos = 0x24;
1214 for (; src_pos < src_size - 2; src_pos += elem_size) {
1215 elem_size = src_data[src_pos + 1] + 2;
1216 if (src_data[src_pos] != 0x05) { /* TIM */
1217 memcpy(dest_data + dest_pos, src_data + src_pos,
1218 elem_size);
1219 dest_pos += elem_size;
1220 }
1221 }
1222 *dest_size = dest_pos;
1223 hdr = (struct ieee80211_hdr *)dest_data;
1224
1225 /* Set the frame control. */
1226 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1227 IEEE80211_STYPE_PROBE_RESP);
1228 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1229 dev->wl->if_id, *dest_size,
1230 B43_RATE_TO_BASE100KBPS(rate));
1231 hdr->duration_id = dur;
1232
1233 return dest_data;
1234}
1235
1236static void b43_write_probe_resp_template(struct b43_wldev *dev,
1237 u16 ram_offset,
1238 u16 shm_size_offset, u8 rate)
1239{
1240 u8 *probe_resp_data;
1241 u16 size;
1242
1243 B43_WARN_ON(!dev->cached_beacon);
1244 size = dev->cached_beacon->len;
1245 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1246 if (unlikely(!probe_resp_data))
1247 return;
1248
1249 /* Looks like PLCP headers plus packet timings are stored for
1250 * all possible basic rates
1251 */
1252 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1253 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1254 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1255 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1256
1257 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1258 b43_write_template_common(dev, probe_resp_data,
1259 size, ram_offset, shm_size_offset, rate);
1260 kfree(probe_resp_data);
1261}
1262
1263static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1264 struct sk_buff *beacon)
1265{
1266 if (dev->cached_beacon)
1267 kfree_skb(dev->cached_beacon);
1268 dev->cached_beacon = beacon;
1269
1270 return 0;
1271}
1272
1273static void b43_update_templates(struct b43_wldev *dev)
1274{
aa6c7ae2 1275 u32 cmd;
e4d6b795
MB		 1276
1277 B43_WARN_ON(!dev->cached_beacon);
1278
1279 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1280 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1281 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1282
aa6c7ae2
MB		 1283 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1284 cmd |= B43_MACCMD_BEACON0_VALID | B43_MACCMD_BEACON1_VALID;
1285 b43_write32(dev, B43_MMIO_MACCMD, cmd);
e4d6b795
MB		 1286}
1287
1288static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1289{
1290 int err;
1291
1292 err = b43_refresh_cached_beacon(dev, beacon);
1293 if (unlikely(err))
1294 return;
1295 b43_update_templates(dev);
1296}
1297
1298static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1299{
1300 u32 tmp;
1301 u16 i, len;
1302
1303 len = min((u16) ssid_len, (u16) 0x100);
1304 for (i = 0; i < len; i += sizeof(u32)) {
1305 tmp = (u32) (ssid[i + 0]);
1306 if (i + 1 < len)
1307 tmp |= (u32) (ssid[i + 1]) << 8;
1308 if (i + 2 < len)
1309 tmp |= (u32) (ssid[i + 2]) << 16;
1310 if (i + 3 < len)
1311 tmp |= (u32) (ssid[i + 3]) << 24;
1312 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1313 }
1314 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1315}
1316
1317static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1318{
1319 b43_time_lock(dev);
1320 if (dev->dev->id.revision >= 3) {
1321 b43_write32(dev, 0x188, (beacon_int << 16));
1322 } else {
1323 b43_write16(dev, 0x606, (beacon_int >> 6));
1324 b43_write16(dev, 0x610, beacon_int);
1325 }
1326 b43_time_unlock(dev);
1327}
1328
1329static void handle_irq_beacon(struct b43_wldev *dev)
1330{
1331 u32 status;
1332
1333 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1334 return;
1335
1336 dev->irq_savedstate &= ~B43_IRQ_BEACON;
aa6c7ae2 1337 status = b43_read32(dev, B43_MMIO_MACCMD);
e4d6b795
MB		 1338
1339 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1340 /* ACK beacon IRQ. */
1341 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1342 dev->irq_savedstate |= B43_IRQ_BEACON;
1343 if (dev->cached_beacon)
1344 kfree_skb(dev->cached_beacon);
1345 dev->cached_beacon = NULL;
1346 return;
1347 }
1348 if (!(status & 0x1)) {
1349 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1350 status |= 0x1;
aa6c7ae2 1351 b43_write32(dev, B43_MMIO_MACCMD, status);
e4d6b795
MB		 1352 }
1353 if (!(status & 0x2)) {
1354 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1355 status |= 0x2;
aa6c7ae2 1356 b43_write32(dev, B43_MMIO_MACCMD, status);
e4d6b795
MB		 1357 }
1358}
1359
1360static void handle_irq_ucode_debug(struct b43_wldev *dev)
1361{
1362 //TODO
1363}
1364
1365/* Interrupt handler bottom-half */
1366static void b43_interrupt_tasklet(struct b43_wldev *dev)
1367{
1368 u32 reason;
1369 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1370 u32 merged_dma_reason = 0;
21954c36 1371 int i;
e4d6b795
MB		 1372 unsigned long flags;
1373
1374 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1375
1376 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1377
1378 reason = dev->irq_reason;
1379 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1380 dma_reason[i] = dev->dma_reason[i];
1381 merged_dma_reason |= dma_reason[i];
1382 }
1383
1384 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1385 b43err(dev->wl, "MAC transmission error\n");
1386
00e0b8cb 1387 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1388 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1389 rmb();
1390 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1391 atomic_set(&dev->phy.txerr_cnt,
1392 B43_PHY_TX_BADNESS_LIMIT);
1393 b43err(dev->wl, "Too many PHY TX errors, "
1394 "restarting the controller\n");
1395 b43_controller_restart(dev, "PHY TX errors");
1396 }
1397 }
e4d6b795
MB		 1398
1399 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1400 B43_DMAIRQ_NONFATALMASK))) {
1401 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1402 b43err(dev->wl, "Fatal DMA error: "
1403 "0x%08X, 0x%08X, 0x%08X, "
1404 "0x%08X, 0x%08X, 0x%08X\n",
1405 dma_reason[0], dma_reason[1],
1406 dma_reason[2], dma_reason[3],
1407 dma_reason[4], dma_reason[5]);
1408 b43_controller_restart(dev, "DMA error");
1409 mmiowb();
1410 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1411 return;
1412 }
1413 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1414 b43err(dev->wl, "DMA error: "
1415 "0x%08X, 0x%08X, 0x%08X, "
1416 "0x%08X, 0x%08X, 0x%08X\n",
1417 dma_reason[0], dma_reason[1],
1418 dma_reason[2], dma_reason[3],
1419 dma_reason[4], dma_reason[5]);
1420 }
1421 }
1422
1423 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1424 handle_irq_ucode_debug(dev);
1425 if (reason & B43_IRQ_TBTT_INDI)
1426 handle_irq_tbtt_indication(dev);
1427 if (reason & B43_IRQ_ATIM_END)
1428 handle_irq_atim_end(dev);
1429 if (reason & B43_IRQ_BEACON)
1430 handle_irq_beacon(dev);
1431 if (reason & B43_IRQ_PMQ)
1432 handle_irq_pmq(dev);
21954c36
MB		 1433 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1434 ;/* TODO */
1435 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1436 handle_irq_noise(dev);
1437
1438 /* Check the DMA reason registers for received data. */
03b29773
MB		 1439 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1440 b43_dma_rx(dev->dma.rx_ring0);
1441 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1442 b43_dma_rx(dev->dma.rx_ring3);
e4d6b795
MB		 1443 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1444 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1445 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1446 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1447
21954c36 1448 if (reason & B43_IRQ_TX_OK)
e4d6b795 1449 handle_irq_transmit_status(dev);
e4d6b795 1450
e4d6b795
MB		 1451 b43_interrupt_enable(dev, dev->irq_savedstate);
1452 mmiowb();
1453 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1454}
1455
e4d6b795
MB		 1456static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1457{
e4d6b795
MB		 1458 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1459
1460 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1461 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1462 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1463 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1464 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1465 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1466}
1467
1468/* Interrupt handler top-half */
1469static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1470{
1471 irqreturn_t ret = IRQ_NONE;
1472 struct b43_wldev *dev = dev_id;
1473 u32 reason;
1474
1475 if (!dev)
1476 return IRQ_NONE;
1477
1478 spin_lock(&dev->wl->irq_lock);
1479
1480 if (b43_status(dev) < B43_STAT_STARTED)
1481 goto out;
1482 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1483 if (reason == 0xffffffff) /* shared IRQ */
1484 goto out;
1485 ret = IRQ_HANDLED;
1486 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1487 if (!reason)
1488 goto out;
1489
1490 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1491 & 0x0001DC00;
1492 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1493 & 0x0000DC00;
1494 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1495 & 0x0000DC00;
1496 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1497 & 0x0001DC00;
1498 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1499 & 0x0000DC00;
1500 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1501 & 0x0000DC00;
1502
1503 b43_interrupt_ack(dev, reason);
1504 /* disable all IRQs. They are enabled again in the bottom half. */
1505 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1506 /* save the reason code and call our bottom half. */
1507 dev->irq_reason = reason;
1508 tasklet_schedule(&dev->isr_tasklet);
1509 out:
1510 mmiowb();
1511 spin_unlock(&dev->wl->irq_lock);
1512
1513 return ret;
1514}
1515
1516static void b43_release_firmware(struct b43_wldev *dev)
1517{
1518 release_firmware(dev->fw.ucode);
1519 dev->fw.ucode = NULL;
1520 release_firmware(dev->fw.pcm);
1521 dev->fw.pcm = NULL;
1522 release_firmware(dev->fw.initvals);
1523 dev->fw.initvals = NULL;
1524 release_firmware(dev->fw.initvals_band);
1525 dev->fw.initvals_band = NULL;
1526}
1527
1528static void b43_print_fw_helptext(struct b43_wl *wl)
1529{
1530 b43err(wl, "You must go to "
354807e0 1531 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
e4d6b795
MB		 1532 "and download the correct firmware (version 4).\n");
1533}
1534
1535static int do_request_fw(struct b43_wldev *dev,
1536 const char *name,
1537 const struct firmware **fw)
1538{
1a09404a 1539 char path[sizeof(modparam_fwpostfix) + 32];
e4d6b795
MB		 1540 struct b43_fw_header *hdr;
1541 u32 size;
1542 int err;
1543
1544 if (!name)
1545 return 0;
1546
1547 snprintf(path, ARRAY_SIZE(path),
1548 "b43%s/%s.fw",
1549 modparam_fwpostfix, name);
1550 err = request_firmware(fw, path, dev->dev->dev);
1551 if (err) {
1552 b43err(dev->wl, "Firmware file \"%s\" not found "
1553 "or load failed.\n", path);
1554 return err;
1555 }
1556 if ((*fw)->size < sizeof(struct b43_fw_header))
1557 goto err_format;
1558 hdr = (struct b43_fw_header *)((*fw)->data);
1559 switch (hdr->type) {
1560 case B43_FW_TYPE_UCODE:
1561 case B43_FW_TYPE_PCM:
1562 size = be32_to_cpu(hdr->size);
1563 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1564 goto err_format;
1565 /* fallthrough */
1566 case B43_FW_TYPE_IV:
1567 if (hdr->ver != 1)
1568 goto err_format;
1569 break;
1570 default:
1571 goto err_format;
1572 }
1573
1574 return err;
1575
1576err_format:
1577 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1578 return -EPROTO;
1579}
1580
1581static int b43_request_firmware(struct b43_wldev *dev)
1582{
1583 struct b43_firmware *fw = &dev->fw;
1584 const u8 rev = dev->dev->id.revision;
1585 const char *filename;
1586 u32 tmshigh;
1587 int err;
1588
1589 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1590 if (!fw->ucode) {
1591 if ((rev >= 5) && (rev <= 10))
1592 filename = "ucode5";
1593 else if ((rev >= 11) && (rev <= 12))
1594 filename = "ucode11";
1595 else if (rev >= 13)
1596 filename = "ucode13";
1597 else
1598 goto err_no_ucode;
1599 err = do_request_fw(dev, filename, &fw->ucode);
1600 if (err)
1601 goto err_load;
1602 }
1603 if (!fw->pcm) {
1604 if ((rev >= 5) && (rev <= 10))
1605 filename = "pcm5";
1606 else if (rev >= 11)
1607 filename = NULL;
1608 else
1609 goto err_no_pcm;
1610 err = do_request_fw(dev, filename, &fw->pcm);
1611 if (err)
1612 goto err_load;
1613 }
1614 if (!fw->initvals) {
1615 switch (dev->phy.type) {
1616 case B43_PHYTYPE_A:
1617 if ((rev >= 5) && (rev <= 10)) {
96c755a3 1618 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
e4d6b795
MB		 1619 filename = "a0g1initvals5";
1620 else
1621 filename = "a0g0initvals5";
1622 } else
1623 goto err_no_initvals;
1624 break;
1625 case B43_PHYTYPE_G:
1626 if ((rev >= 5) && (rev <= 10))
1627 filename = "b0g0initvals5";
1628 else if (rev >= 13)
1629 filename = "lp0initvals13";
1630 else
1631 goto err_no_initvals;
1632 break;
1633 default:
1634 goto err_no_initvals;
1635 }
1636 err = do_request_fw(dev, filename, &fw->initvals);
1637 if (err)
1638 goto err_load;
1639 }
1640 if (!fw->initvals_band) {
1641 switch (dev->phy.type) {
1642 case B43_PHYTYPE_A:
1643 if ((rev >= 5) && (rev <= 10)) {
96c755a3 1644 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
e4d6b795
MB		 1645 filename = "a0g1bsinitvals5";
1646 else
1647 filename = "a0g0bsinitvals5";
1648 } else if (rev >= 11)
1649 filename = NULL;
1650 else
1651 goto err_no_initvals;
1652 break;
1653 case B43_PHYTYPE_G:
1654 if ((rev >= 5) && (rev <= 10))
1655 filename = "b0g0bsinitvals5";
1656 else if (rev >= 11)
1657 filename = NULL;
1658 else
1659 goto err_no_initvals;
1660 break;
1661 default:
1662 goto err_no_initvals;
1663 }
1664 err = do_request_fw(dev, filename, &fw->initvals_band);
1665 if (err)
1666 goto err_load;
1667 }
1668
1669 return 0;
1670
1671err_load:
1672 b43_print_fw_helptext(dev->wl);
1673 goto error;
1674
1675err_no_ucode:
1676 err = -ENODEV;
1677 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1678 goto error;
1679
1680err_no_pcm:
1681 err = -ENODEV;
1682 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1683 goto error;
1684
1685err_no_initvals:
1686 err = -ENODEV;
1687 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1688 "core rev %u\n", dev->phy.type, rev);
1689 goto error;
1690
1691error:
1692 b43_release_firmware(dev);
1693 return err;
1694}
1695
1696static int b43_upload_microcode(struct b43_wldev *dev)
1697{
1698 const size_t hdr_len = sizeof(struct b43_fw_header);
1699 const __be32 *data;
1700 unsigned int i, len;
1701 u16 fwrev, fwpatch, fwdate, fwtime;
1702 u32 tmp;
1703 int err = 0;
1704
1705 /* Upload Microcode. */
1706 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1707 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1708 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1709 for (i = 0; i < len; i++) {
1710 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1711 udelay(10);
1712 }
1713
1714 if (dev->fw.pcm) {
1715 /* Upload PCM data. */
1716 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1717 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1718 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1719 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1720 /* No need for autoinc bit in SHM_HW */
1721 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1722 for (i = 0; i < len; i++) {
1723 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1724 udelay(10);
1725 }
1726 }
1727
1728 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1729 b43_write32(dev, B43_MMIO_MACCTL,
1730 B43_MACCTL_PSM_RUN |
1731 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1732
1733 /* Wait for the microcode to load and respond */
1734 i = 0;
1735 while (1) {
1736 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1737 if (tmp == B43_IRQ_MAC_SUSPENDED)
1738 break;
1739 i++;
1740 if (i >= 50) {
1741 b43err(dev->wl, "Microcode not responding\n");
1742 b43_print_fw_helptext(dev->wl);
1743 err = -ENODEV;
1744 goto out;
1745 }
1746 udelay(10);
1747 }
1748 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1749
1750 /* Get and check the revisions. */
1751 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1752 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1753 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1754 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1755
1756 if (fwrev <= 0x128) {
1757 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1758 "binary drivers older than version 4.x is unsupported. "
1759 "You must upgrade your firmware files.\n");
1760 b43_print_fw_helptext(dev->wl);
1761 b43_write32(dev, B43_MMIO_MACCTL, 0);
1762 err = -EOPNOTSUPP;
1763 goto out;
1764 }
1765 b43dbg(dev->wl, "Loading firmware version %u.%u "
1766 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1767 fwrev, fwpatch,
1768 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1769 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1770
1771 dev->fw.rev = fwrev;
1772 dev->fw.patch = fwpatch;
1773
1774 out:
1775 return err;
1776}
1777
1778static int b43_write_initvals(struct b43_wldev *dev,
1779 const struct b43_iv *ivals,
1780 size_t count,
1781 size_t array_size)
1782{
1783 const struct b43_iv *iv;
1784 u16 offset;
1785 size_t i;
1786 bool bit32;
1787
1788 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1789 iv = ivals;
1790 for (i = 0; i < count; i++) {
1791 if (array_size < sizeof(iv->offset_size))
1792 goto err_format;
1793 array_size -= sizeof(iv->offset_size);
1794 offset = be16_to_cpu(iv->offset_size);
1795 bit32 = !!(offset & B43_IV_32BIT);
1796 offset &= B43_IV_OFFSET_MASK;
1797 if (offset >= 0x1000)
1798 goto err_format;
1799 if (bit32) {
1800 u32 value;
1801
1802 if (array_size < sizeof(iv->data.d32))
1803 goto err_format;
1804 array_size -= sizeof(iv->data.d32);
1805
1806 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1807 b43_write32(dev, offset, value);
1808
1809 iv = (const struct b43_iv *)((const uint8_t *)iv +
1810 sizeof(__be16) +
1811 sizeof(__be32));
1812 } else {
1813 u16 value;
1814
1815 if (array_size < sizeof(iv->data.d16))
1816 goto err_format;
1817 array_size -= sizeof(iv->data.d16);
1818
1819 value = be16_to_cpu(iv->data.d16);
1820 b43_write16(dev, offset, value);
1821
1822 iv = (const struct b43_iv *)((const uint8_t *)iv +
1823 sizeof(__be16) +
1824 sizeof(__be16));
1825 }
1826 }
1827 if (array_size)
1828 goto err_format;
1829
1830 return 0;
1831
1832err_format:
1833 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1834 b43_print_fw_helptext(dev->wl);
1835
1836 return -EPROTO;
1837}
1838
1839static int b43_upload_initvals(struct b43_wldev *dev)
1840{
1841 const size_t hdr_len = sizeof(struct b43_fw_header);
1842 const struct b43_fw_header *hdr;
1843 struct b43_firmware *fw = &dev->fw;
1844 const struct b43_iv *ivals;
1845 size_t count;
1846 int err;
1847
1848 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1849 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1850 count = be32_to_cpu(hdr->size);
1851 err = b43_write_initvals(dev, ivals, count,
1852 fw->initvals->size - hdr_len);
1853 if (err)
1854 goto out;
1855 if (fw->initvals_band) {
1856 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1857 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1858 count = be32_to_cpu(hdr->size);
1859 err = b43_write_initvals(dev, ivals, count,
1860 fw->initvals_band->size - hdr_len);
1861 if (err)
1862 goto out;
1863 }
1864out:
1865
1866 return err;
1867}
1868
1869/* Initialize the GPIOs
1870 * http://bcm-specs.sipsolutions.net/GPIO
1871 */
1872static int b43_gpio_init(struct b43_wldev *dev)
1873{
1874 struct ssb_bus *bus = dev->dev->bus;
1875 struct ssb_device *gpiodev, *pcidev = NULL;
1876 u32 mask, set;
1877
1878 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1879 & ~B43_MACCTL_GPOUTSMSK);
1880
e4d6b795
MB		 1881 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1882 | 0x000F);
1883
1884 mask = 0x0000001F;
1885 set = 0x0000000F;
1886 if (dev->dev->bus->chip_id == 0x4301) {
1887 mask |= 0x0060;
1888 set |= 0x0060;
1889 }
1890 if (0 /* FIXME: conditional unknown */ ) {
1891 b43_write16(dev, B43_MMIO_GPIO_MASK,
1892 b43_read16(dev, B43_MMIO_GPIO_MASK)
1893 | 0x0100);
1894 mask |= 0x0180;
1895 set |= 0x0180;
1896 }
95de2841 1897 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 1898 b43_write16(dev, B43_MMIO_GPIO_MASK,
1899 b43_read16(dev, B43_MMIO_GPIO_MASK)
1900 | 0x0200);
1901 mask |= 0x0200;
1902 set |= 0x0200;
1903 }
1904 if (dev->dev->id.revision >= 2)
1905 mask |= 0x0010; /* FIXME: This is redundant. */
1906
1907#ifdef CONFIG_SSB_DRIVER_PCICORE
1908 pcidev = bus->pcicore.dev;
1909#endif
1910 gpiodev = bus->chipco.dev ? : pcidev;
1911 if (!gpiodev)
1912 return 0;
1913 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1914 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1915 & mask) | set);
1916
1917 return 0;
1918}
1919
1920/* Turn off all GPIO stuff. Call this on module unload, for example. */
1921static void b43_gpio_cleanup(struct b43_wldev *dev)
1922{
1923 struct ssb_bus *bus = dev->dev->bus;
1924 struct ssb_device *gpiodev, *pcidev = NULL;
1925
1926#ifdef CONFIG_SSB_DRIVER_PCICORE
1927 pcidev = bus->pcicore.dev;
1928#endif
1929 gpiodev = bus->chipco.dev ? : pcidev;
1930 if (!gpiodev)
1931 return;
1932 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1933}
1934
1935/* http://bcm-specs.sipsolutions.net/EnableMac */
1936void b43_mac_enable(struct b43_wldev *dev)
1937{
1938 dev->mac_suspended--;
1939 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 1940 B43_WARN_ON(irqs_disabled());
e4d6b795
MB		 1941 if (dev->mac_suspended == 0) {
1942 b43_write32(dev, B43_MMIO_MACCTL,
1943 b43_read32(dev, B43_MMIO_MACCTL)
1944 | B43_MACCTL_ENABLED);
1945 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1946 B43_IRQ_MAC_SUSPENDED);
1947 /* Commit writes */
1948 b43_read32(dev, B43_MMIO_MACCTL);
1949 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1950 b43_power_saving_ctl_bits(dev, 0);
05b64b36
MB		 1951
1952 /* Re-enable IRQs. */
1953 spin_lock_irq(&dev->wl->irq_lock);
1954 b43_interrupt_enable(dev, dev->irq_savedstate);
1955 spin_unlock_irq(&dev->wl->irq_lock);
e4d6b795
MB		 1956 }
1957}
1958
1959/* http://bcm-specs.sipsolutions.net/SuspendMAC */
1960void b43_mac_suspend(struct b43_wldev *dev)
1961{
1962 int i;
1963 u32 tmp;
1964
05b64b36
MB		 1965 might_sleep();
1966 B43_WARN_ON(irqs_disabled());
e4d6b795 1967 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 1968
e4d6b795 1969 if (dev->mac_suspended == 0) {
05b64b36
MB		 1970 /* Mask IRQs before suspending MAC. Otherwise
1971 * the MAC stays busy and won't suspend. */
1972 spin_lock_irq(&dev->wl->irq_lock);
1973 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
1974 spin_unlock_irq(&dev->wl->irq_lock);
1975 b43_synchronize_irq(dev);
1976 dev->irq_savedstate = tmp;
1977
e4d6b795
MB		 1978 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1979 b43_write32(dev, B43_MMIO_MACCTL,
1980 b43_read32(dev, B43_MMIO_MACCTL)
1981 & ~B43_MACCTL_ENABLED);
1982 /* force pci to flush the write */
1983 b43_read32(dev, B43_MMIO_MACCTL);
05b64b36 1984 for (i = 40; i; i--) {
e4d6b795
MB		 1985 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1986 if (tmp & B43_IRQ_MAC_SUSPENDED)
1987 goto out;
05b64b36 1988 msleep(1);
e4d6b795
MB		 1989 }
1990 b43err(dev->wl, "MAC suspend failed\n");
1991 }
05b64b36 1992out:
e4d6b795
MB		 1993 dev->mac_suspended++;
1994}
1995
1996static void b43_adjust_opmode(struct b43_wldev *dev)
1997{
1998 struct b43_wl *wl = dev->wl;
1999 u32 ctl;
2000 u16 cfp_pretbtt;
2001
2002 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2003 /* Reset status to STA infrastructure mode. */
2004 ctl &= ~B43_MACCTL_AP;
2005 ctl &= ~B43_MACCTL_KEEP_CTL;
2006 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2007 ctl &= ~B43_MACCTL_KEEP_BAD;
2008 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2009 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2010 ctl |= B43_MACCTL_INFRA;
2011
4150c572
JB		 2012 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2013 ctl |= B43_MACCTL_AP;
2014 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2015 ctl &= ~B43_MACCTL_INFRA;
2016
2017 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2018 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2019 if (wl->filter_flags & FIF_FCSFAIL)
2020 ctl |= B43_MACCTL_KEEP_BAD;
2021 if (wl->filter_flags & FIF_PLCPFAIL)
2022 ctl |= B43_MACCTL_KEEP_BADPLCP;
2023 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2024 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2025 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2026 ctl |= B43_MACCTL_BEACPROMISC;
2027
e4d6b795
MB		 2028 /* Workaround: On old hardware the HW-MAC-address-filter
2029 * doesn't work properly, so always run promisc in filter
2030 * it in software. */
2031 if (dev->dev->id.revision <= 4)
2032 ctl |= B43_MACCTL_PROMISC;
2033
2034 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2035
2036 cfp_pretbtt = 2;
2037 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2038 if (dev->dev->bus->chip_id == 0x4306 &&
2039 dev->dev->bus->chip_rev == 3)
2040 cfp_pretbtt = 100;
2041 else
2042 cfp_pretbtt = 50;
2043 }
2044 b43_write16(dev, 0x612, cfp_pretbtt);
2045}
2046
2047static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2048{
2049 u16 offset;
2050
2051 if (is_ofdm) {
2052 offset = 0x480;
2053 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2054 } else {
2055 offset = 0x4C0;
2056 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2057 }
2058 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2059 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2060}
2061
2062static void b43_rate_memory_init(struct b43_wldev *dev)
2063{
2064 switch (dev->phy.type) {
2065 case B43_PHYTYPE_A:
2066 case B43_PHYTYPE_G:
2067 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2068 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2069 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2070 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2071 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2072 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2073 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2074 if (dev->phy.type == B43_PHYTYPE_A)
2075 break;
2076 /* fallthrough */
2077 case B43_PHYTYPE_B:
2078 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2079 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2080 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2081 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2082 break;
2083 default:
2084 B43_WARN_ON(1);
2085 }
2086}
2087
2088/* Set the TX-Antenna for management frames sent by firmware. */
2089static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2090{
2091 u16 ant = 0;
2092 u16 tmp;
2093
2094 switch (antenna) {
2095 case B43_ANTENNA0:
2096 ant |= B43_TX4_PHY_ANT0;
2097 break;
2098 case B43_ANTENNA1:
2099 ant |= B43_TX4_PHY_ANT1;
2100 break;
2101 case B43_ANTENNA_AUTO:
2102 ant |= B43_TX4_PHY_ANTLAST;
2103 break;
2104 default:
2105 B43_WARN_ON(1);
2106 }
2107
2108 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2109
2110 /* For Beacons */
2111 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2112 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2113 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2114 /* For ACK/CTS */
2115 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2116 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2117 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2118 /* For Probe Resposes */
2119 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2120 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2121 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2122}
2123
2124/* This is the opposite of b43_chip_init() */
2125static void b43_chip_exit(struct b43_wldev *dev)
2126{
8e9f7529 2127 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 2128 b43_gpio_cleanup(dev);
2129 /* firmware is released later */
2130}
2131
2132/* Initialize the chip
2133 * http://bcm-specs.sipsolutions.net/ChipInit
2134 */
2135static int b43_chip_init(struct b43_wldev *dev)
2136{
2137 struct b43_phy *phy = &dev->phy;
2138 int err, tmp;
2139 u32 value32;
2140 u16 value16;
2141
2142 b43_write32(dev, B43_MMIO_MACCTL,
2143 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2144
2145 err = b43_request_firmware(dev);
2146 if (err)
2147 goto out;
2148 err = b43_upload_microcode(dev);
2149 if (err)
2150 goto out; /* firmware is released later */
2151
2152 err = b43_gpio_init(dev);
2153 if (err)
2154 goto out; /* firmware is released later */
21954c36 2155
e4d6b795
MB		 2156 err = b43_upload_initvals(dev);
2157 if (err)
1a8d1227 2158 goto err_gpio_clean;
e4d6b795 2159 b43_radio_turn_on(dev);
e4d6b795
MB		 2160
2161 b43_write16(dev, 0x03E6, 0x0000);
2162 err = b43_phy_init(dev);
2163 if (err)
2164 goto err_radio_off;
2165
2166 /* Select initial Interference Mitigation. */
2167 tmp = phy->interfmode;
2168 phy->interfmode = B43_INTERFMODE_NONE;
2169 b43_radio_set_interference_mitigation(dev, tmp);
2170
2171 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2172 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2173
2174 if (phy->type == B43_PHYTYPE_B) {
2175 value16 = b43_read16(dev, 0x005E);
2176 value16 |= 0x0004;
2177 b43_write16(dev, 0x005E, value16);
2178 }
2179 b43_write32(dev, 0x0100, 0x01000000);
2180 if (dev->dev->id.revision < 5)
2181 b43_write32(dev, 0x010C, 0x01000000);
2182
2183 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2184 & ~B43_MACCTL_INFRA);
2185 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2186 | B43_MACCTL_INFRA);
e4d6b795 2187
e4d6b795
MB		 2188 /* Probe Response Timeout value */
2189 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2190 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2191
2192 /* Initially set the wireless operation mode. */
2193 b43_adjust_opmode(dev);
2194
2195 if (dev->dev->id.revision < 3) {
2196 b43_write16(dev, 0x060E, 0x0000);
2197 b43_write16(dev, 0x0610, 0x8000);
2198 b43_write16(dev, 0x0604, 0x0000);
2199 b43_write16(dev, 0x0606, 0x0200);
2200 } else {
2201 b43_write32(dev, 0x0188, 0x80000000);
2202 b43_write32(dev, 0x018C, 0x02000000);
2203 }
2204 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2205 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2206 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2207 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2208 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2209 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2210 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2211
2212 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2213 value32 |= 0x00100000;
2214 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2215
2216 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2217 dev->dev->bus->chipco.fast_pwrup_delay);
2218
2219 err = 0;
2220 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2221out:
e4d6b795
MB		 2222 return err;
2223
21954c36 2224err_radio_off:
8e9f7529 2225 b43_radio_turn_off(dev, 1);
1a8d1227 2226err_gpio_clean:
e4d6b795 2227 b43_gpio_cleanup(dev);
21954c36 2228 return err;
e4d6b795
MB		 2229}
2230
2231static void b43_periodic_every120sec(struct b43_wldev *dev)
2232{
2233 struct b43_phy *phy = &dev->phy;
2234
2235 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2236 return;
2237
2238 b43_mac_suspend(dev);
2239 b43_lo_g_measure(dev);
2240 b43_mac_enable(dev);
2241 if (b43_has_hardware_pctl(phy))
2242 b43_lo_g_ctl_mark_all_unused(dev);
2243}
2244
2245static void b43_periodic_every60sec(struct b43_wldev *dev)
2246{
2247 struct b43_phy *phy = &dev->phy;
2248
2249 if (!b43_has_hardware_pctl(phy))
2250 b43_lo_g_ctl_mark_all_unused(dev);
95de2841 2251 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
e4d6b795
MB		 2252 b43_mac_suspend(dev);
2253 b43_calc_nrssi_slope(dev);
2254 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2255 u8 old_chan = phy->channel;
2256
2257 /* VCO Calibration */
2258 if (old_chan >= 8)
2259 b43_radio_selectchannel(dev, 1, 0);
2260 else
2261 b43_radio_selectchannel(dev, 13, 0);
2262 b43_radio_selectchannel(dev, old_chan, 0);
2263 }
2264 b43_mac_enable(dev);
2265 }
2266}
2267
2268static void b43_periodic_every30sec(struct b43_wldev *dev)
2269{
2270 /* Update device statistics. */
2271 b43_calculate_link_quality(dev);
2272}
2273
2274static void b43_periodic_every15sec(struct b43_wldev *dev)
2275{
2276 struct b43_phy *phy = &dev->phy;
2277
2278 if (phy->type == B43_PHYTYPE_G) {
2279 //TODO: update_aci_moving_average
2280 if (phy->aci_enable && phy->aci_wlan_automatic) {
2281 b43_mac_suspend(dev);
2282 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2283 if (0 /*TODO: bunch of conditions */ ) {
2284 b43_radio_set_interference_mitigation
2285 (dev, B43_INTERFMODE_MANUALWLAN);
2286 }
2287 } else if (1 /*TODO*/) {
2288 /*
2289 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2290 b43_radio_set_interference_mitigation(dev,
2291 B43_INTERFMODE_NONE);
2292 }
2293 */
2294 }
2295 b43_mac_enable(dev);
2296 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2297 phy->rev == 1) {
2298 //TODO: implement rev1 workaround
2299 }
2300 }
2301 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2302 //TODO for APHY (temperature?)
00e0b8cb
SB		 2303
2304 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2305 wmb();
e4d6b795
MB		 2306}
2307
e4d6b795
MB		 2308static void do_periodic_work(struct b43_wldev *dev)
2309{
2310 unsigned int state;
2311
2312 state = dev->periodic_state;
42bb4cd5 2313 if (state % 8 == 0)
e4d6b795 2314 b43_periodic_every120sec(dev);
42bb4cd5 2315 if (state % 4 == 0)
e4d6b795 2316 b43_periodic_every60sec(dev);
42bb4cd5 2317 if (state % 2 == 0)
e4d6b795 2318 b43_periodic_every30sec(dev);
42bb4cd5 2319 b43_periodic_every15sec(dev);
e4d6b795
MB		 2320}
2321
05b64b36
MB		 2322/* Periodic work locking policy:
2323 * The whole periodic work handler is protected by
2324 * wl->mutex. If another lock is needed somewhere in the
2325 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2326 */
e4d6b795
MB		 2327static void b43_periodic_work_handler(struct work_struct *work)
2328{
05b64b36
MB		 2329 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2330 periodic_work.work);
2331 struct b43_wl *wl = dev->wl;
2332 unsigned long delay;
e4d6b795 2333
05b64b36 2334 mutex_lock(&wl->mutex);
e4d6b795
MB		 2335
2336 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2337 goto out;
2338 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2339 goto out_requeue;
2340
05b64b36 2341 do_periodic_work(dev);
e4d6b795 2342
e4d6b795 2343 dev->periodic_state++;
42bb4cd5 2344out_requeue:
e4d6b795
MB		 2345 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2346 delay = msecs_to_jiffies(50);
2347 else
82cd682d 2348 delay = round_jiffies_relative(HZ * 15);
05b64b36 2349 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2350out:
05b64b36 2351 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2352}
2353
2354static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2355{
2356 struct delayed_work *work = &dev->periodic_work;
2357
2358 dev->periodic_state = 0;
2359 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2360 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2361}
2362
f3dd3fcc 2363/* Check if communication with the device works correctly. */
e4d6b795
MB		 2364static int b43_validate_chipaccess(struct b43_wldev *dev)
2365{
f3dd3fcc 2366 u32 v, backup;
e4d6b795 2367
f3dd3fcc
MB		 2368 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2369
2370 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2371 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2372 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2373 goto error;
f3dd3fcc
MB		 2374 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2375 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2376 goto error;
2377
f3dd3fcc
MB		 2378 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2379
2380 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2381 /* The 32bit register shadows the two 16bit registers
2382 * with update sideeffects. Validate this. */
2383 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2384 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2385 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2386 goto error;
2387 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2388 goto error;
2389 }
2390 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2391
2392 v = b43_read32(dev, B43_MMIO_MACCTL);
2393 v |= B43_MACCTL_GMODE;
2394 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2395 goto error;
2396
2397 return 0;
f3dd3fcc 2398error:
e4d6b795
MB		 2399 b43err(dev->wl, "Failed to validate the chipaccess\n");
2400 return -ENODEV;
2401}
2402
2403static void b43_security_init(struct b43_wldev *dev)
2404{
2405 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2406 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2407 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2408 /* KTP is a word address, but we address SHM bytewise.
2409 * So multiply by two.
2410 */
2411 dev->ktp *= 2;
2412 if (dev->dev->id.revision >= 5) {
2413 /* Number of RCMTA address slots */
2414 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2415 }
2416 b43_clear_keys(dev);
2417}
2418
2419static int b43_rng_read(struct hwrng *rng, u32 * data)
2420{
2421 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2422 unsigned long flags;
2423
2424 /* Don't take wl->mutex here, as it could deadlock with
2425 * hwrng internal locking. It's not needed to take
2426 * wl->mutex here, anyway. */
2427
2428 spin_lock_irqsave(&wl->irq_lock, flags);
2429 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2430 spin_unlock_irqrestore(&wl->irq_lock, flags);
2431
2432 return (sizeof(u16));
2433}
2434
2435static void b43_rng_exit(struct b43_wl *wl)
2436{
2437 if (wl->rng_initialized)
2438 hwrng_unregister(&wl->rng);
2439}
2440
2441static int b43_rng_init(struct b43_wl *wl)
2442{
2443 int err;
2444
2445 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2446 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2447 wl->rng.name = wl->rng_name;
2448 wl->rng.data_read = b43_rng_read;
2449 wl->rng.priv = (unsigned long)wl;
2450 wl->rng_initialized = 1;
2451 err = hwrng_register(&wl->rng);
2452 if (err) {
2453 wl->rng_initialized = 0;
2454 b43err(wl, "Failed to register the random "
2455 "number generator (%d)\n", err);
2456 }
2457
2458 return err;
2459}
2460
40faacc4
MB		 2461static int b43_op_tx(struct ieee80211_hw *hw,
2462 struct sk_buff *skb,
2463 struct ieee80211_tx_control *ctl)
e4d6b795
MB		 2464{
2465 struct b43_wl *wl = hw_to_b43_wl(hw);
2466 struct b43_wldev *dev = wl->current_dev;
2467 int err = -ENODEV;
e4d6b795
MB		 2468
2469 if (unlikely(!dev))
2470 goto out;
2471 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2472 goto out;
2473 /* DMA-TX is done without a global lock. */
03b29773 2474 err = b43_dma_tx(dev, skb, ctl);
40faacc4 2475out:
e4d6b795
MB		 2476 if (unlikely(err))
2477 return NETDEV_TX_BUSY;
2478 return NETDEV_TX_OK;
2479}
2480
40faacc4
MB		 2481static int b43_op_conf_tx(struct ieee80211_hw *hw,
2482 int queue,
2483 const struct ieee80211_tx_queue_params *params)
e4d6b795
MB		 2484{
2485 return 0;
2486}
2487
40faacc4
MB		 2488static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2489 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 2490{
2491 struct b43_wl *wl = hw_to_b43_wl(hw);
2492 struct b43_wldev *dev = wl->current_dev;
2493 unsigned long flags;
2494 int err = -ENODEV;
2495
2496 if (!dev)
2497 goto out;
2498 spin_lock_irqsave(&wl->irq_lock, flags);
2499 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
03b29773 2500 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 2501 err = 0;
2502 }
2503 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 2504out:
e4d6b795
MB		 2505 return err;
2506}
2507
40faacc4
MB		 2508static int b43_op_get_stats(struct ieee80211_hw *hw,
2509 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 2510{
2511 struct b43_wl *wl = hw_to_b43_wl(hw);
2512 unsigned long flags;
2513
2514 spin_lock_irqsave(&wl->irq_lock, flags);
2515 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2516 spin_unlock_irqrestore(&wl->irq_lock, flags);
2517
2518 return 0;
2519}
2520
2521static const char *phymode_to_string(unsigned int phymode)
2522{
2523 switch (phymode) {
2524 case B43_PHYMODE_A:
2525 return "A";
2526 case B43_PHYMODE_B:
2527 return "B";
2528 case B43_PHYMODE_G:
2529 return "G";
2530 default:
2531 B43_WARN_ON(1);
2532 }
2533 return "";
2534}
2535
2536static int find_wldev_for_phymode(struct b43_wl *wl,
2537 unsigned int phymode,
2538 struct b43_wldev **dev, bool * gmode)
2539{
2540 struct b43_wldev *d;
2541
2542 list_for_each_entry(d, &wl->devlist, list) {
2543 if (d->phy.possible_phymodes & phymode) {
2544 /* Ok, this device supports the PHY-mode.
2545 * Now figure out how the gmode bit has to be
2546 * set to support it. */
2547 if (phymode == B43_PHYMODE_A)
2548 *gmode = 0;
2549 else
2550 *gmode = 1;
2551 *dev = d;
2552
2553 return 0;
2554 }
2555 }
2556
2557 return -ESRCH;
2558}
2559
2560static void b43_put_phy_into_reset(struct b43_wldev *dev)
2561{
2562 struct ssb_device *sdev = dev->dev;
2563 u32 tmslow;
2564
2565 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2566 tmslow &= ~B43_TMSLOW_GMODE;
2567 tmslow |= B43_TMSLOW_PHYRESET;
2568 tmslow |= SSB_TMSLOW_FGC;
2569 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2570 msleep(1);
2571
2572 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2573 tmslow &= ~SSB_TMSLOW_FGC;
2574 tmslow |= B43_TMSLOW_PHYRESET;
2575 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2576 msleep(1);
2577}
2578
2579/* Expects wl->mutex locked */
2580static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2581{
2582 struct b43_wldev *up_dev;
2583 struct b43_wldev *down_dev;
2584 int err;
2585 bool gmode = 0;
2586 int prev_status;
2587
2588 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2589 if (err) {
2590 b43err(wl, "Could not find a device for %s-PHY mode\n",
2591 phymode_to_string(new_mode));
2592 return err;
2593 }
2594 if ((up_dev == wl->current_dev) &&
2595 (!!wl->current_dev->phy.gmode == !!gmode)) {
2596 /* This device is already running. */
2597 return 0;
2598 }
2599 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2600 phymode_to_string(new_mode));
2601 down_dev = wl->current_dev;
2602
2603 prev_status = b43_status(down_dev);
2604 /* Shutdown the currently running core. */
2605 if (prev_status >= B43_STAT_STARTED)
2606 b43_wireless_core_stop(down_dev);
2607 if (prev_status >= B43_STAT_INITIALIZED)
2608 b43_wireless_core_exit(down_dev);
2609
2610 if (down_dev != up_dev) {
2611 /* We switch to a different core, so we put PHY into
2612 * RESET on the old core. */
2613 b43_put_phy_into_reset(down_dev);
2614 }
2615
2616 /* Now start the new core. */
2617 up_dev->phy.gmode = gmode;
2618 if (prev_status >= B43_STAT_INITIALIZED) {
2619 err = b43_wireless_core_init(up_dev);
2620 if (err) {
2621 b43err(wl, "Fatal: Could not initialize device for "
2622 "newly selected %s-PHY mode\n",
2623 phymode_to_string(new_mode));
2624 goto init_failure;
2625 }
2626 }
2627 if (prev_status >= B43_STAT_STARTED) {
2628 err = b43_wireless_core_start(up_dev);
2629 if (err) {
2630 b43err(wl, "Fatal: Coult not start device for "
2631 "newly selected %s-PHY mode\n",
2632 phymode_to_string(new_mode));
2633 b43_wireless_core_exit(up_dev);
2634 goto init_failure;
2635 }
2636 }
2637 B43_WARN_ON(b43_status(up_dev) != prev_status);
2638
2639 wl->current_dev = up_dev;
2640
2641 return 0;
2642 init_failure:
2643 /* Whoops, failed to init the new core. No core is operating now. */
2644 wl->current_dev = NULL;
2645 return err;
2646}
2647
9db1f6d7
MB		 2648/* Check if the use of the antenna that ieee80211 told us to
2649 * use is possible. This will fall back to DEFAULT.
2650 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2651u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2652 u8 antenna_nr)
e4d6b795 2653{
9db1f6d7
MB		 2654 u8 antenna_mask;
2655
2656 if (antenna_nr == 0) {
2657 /* Zero means "use default antenna". That's always OK. */
2658 return 0;
2659 }
2660
2661 /* Get the mask of available antennas. */
2662 if (dev->phy.gmode)
2663 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2664 else
2665 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2666
2667 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2668 /* This antenna is not available. Fall back to default. */
2669 return 0;
2670 }
2671
2672 return antenna_nr;
2673}
2674
2675static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2676{
2677 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
e4d6b795
MB		 2678 switch (antenna) {
2679 case 0: /* default/diversity */
2680 return B43_ANTENNA_DEFAULT;
2681 case 1: /* Antenna 0 */
2682 return B43_ANTENNA0;
2683 case 2: /* Antenna 1 */
2684 return B43_ANTENNA1;
2685 default:
2686 return B43_ANTENNA_DEFAULT;
2687 }
2688}
2689
40faacc4 2690static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
e4d6b795
MB		 2691{
2692 struct b43_wl *wl = hw_to_b43_wl(hw);
2693 struct b43_wldev *dev;
2694 struct b43_phy *phy;
2695 unsigned long flags;
2696 unsigned int new_phymode = 0xFFFF;
9db1f6d7 2697 int antenna;
e4d6b795
MB		 2698 int err = 0;
2699 u32 savedirqs;
2700
e4d6b795
MB		 2701 mutex_lock(&wl->mutex);
2702
2703 /* Switch the PHY mode (if necessary). */
2704 switch (conf->phymode) {
2705 case MODE_IEEE80211A:
2706 new_phymode = B43_PHYMODE_A;
2707 break;
2708 case MODE_IEEE80211B:
2709 new_phymode = B43_PHYMODE_B;
2710 break;
2711 case MODE_IEEE80211G:
2712 new_phymode = B43_PHYMODE_G;
2713 break;
2714 default:
2715 B43_WARN_ON(1);
2716 }
2717 err = b43_switch_phymode(wl, new_phymode);
2718 if (err)
2719 goto out_unlock_mutex;
2720 dev = wl->current_dev;
2721 phy = &dev->phy;
2722
2723 /* Disable IRQs while reconfiguring the device.
2724 * This makes it possible to drop the spinlock throughout
2725 * the reconfiguration process. */
2726 spin_lock_irqsave(&wl->irq_lock, flags);
2727 if (b43_status(dev) < B43_STAT_STARTED) {
2728 spin_unlock_irqrestore(&wl->irq_lock, flags);
2729 goto out_unlock_mutex;
2730 }
2731 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2732 spin_unlock_irqrestore(&wl->irq_lock, flags);
2733 b43_synchronize_irq(dev);
2734
2735 /* Switch to the requested channel.
2736 * The firmware takes care of races with the TX handler. */
2737 if (conf->channel_val != phy->channel)
2738 b43_radio_selectchannel(dev, conf->channel_val, 0);
2739
2740 /* Enable/Disable ShortSlot timing. */
2741 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2742 dev->short_slot) {
2743 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2744 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2745 b43_short_slot_timing_enable(dev);
2746 else
2747 b43_short_slot_timing_disable(dev);
2748 }
2749
d42ce84a
JB		 2750 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2751
e4d6b795
MB		 2752 /* Adjust the desired TX power level. */
2753 if (conf->power_level != 0) {
2754 if (conf->power_level != phy->power_level) {
2755 phy->power_level = conf->power_level;
2756 b43_phy_xmitpower(dev);
2757 }
2758 }
2759
2760 /* Antennas for RX and management frame TX. */
9db1f6d7
MB		 2761 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2762 b43_mgmtframe_txantenna(dev, antenna);
2763 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2764 b43_set_rx_antenna(dev, antenna);
e4d6b795
MB		 2765
2766 /* Update templates for AP mode. */
2767 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2768 b43_set_beacon_int(dev, conf->beacon_int);
2769
fda9abcf
MB		 2770 if (!!conf->radio_enabled != phy->radio_on) {
2771 if (conf->radio_enabled) {
2772 b43_radio_turn_on(dev);
2773 b43info(dev->wl, "Radio turned on by software\n");
2774 if (!dev->radio_hw_enable) {
2775 b43info(dev->wl, "The hardware RF-kill button "
2776 "still turns the radio physically off. "
2777 "Press the button to turn it on.\n");
2778 }
2779 } else {
8e9f7529 2780 b43_radio_turn_off(dev, 0);
fda9abcf
MB		 2781 b43info(dev->wl, "Radio turned off by software\n");
2782 }
2783 }
2784
e4d6b795
MB		 2785 spin_lock_irqsave(&wl->irq_lock, flags);
2786 b43_interrupt_enable(dev, savedirqs);
2787 mmiowb();
2788 spin_unlock_irqrestore(&wl->irq_lock, flags);
2789 out_unlock_mutex:
2790 mutex_unlock(&wl->mutex);
2791
2792 return err;
2793}
2794
40faacc4 2795static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4150c572
JB		 2796 const u8 *local_addr, const u8 *addr,
2797 struct ieee80211_key_conf *key)
e4d6b795
MB		 2798{
2799 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 2800 struct b43_wldev *dev;
e4d6b795
MB		 2801 unsigned long flags;
2802 u8 algorithm;
2803 u8 index;
c6dfc9a8 2804 int err;
0795af57 2805 DECLARE_MAC_BUF(mac);
e4d6b795
MB		 2806
2807 if (modparam_nohwcrypt)
2808 return -ENOSPC; /* User disabled HW-crypto */
2809
c6dfc9a8
MB		 2810 mutex_lock(&wl->mutex);
2811 spin_lock_irqsave(&wl->irq_lock, flags);
2812
2813 dev = wl->current_dev;
2814 err = -ENODEV;
2815 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2816 goto out_unlock;
2817
2818 err = -EINVAL;
e4d6b795 2819 switch (key->alg) {
e4d6b795
MB		 2820 case ALG_WEP:
2821 if (key->keylen == 5)
2822 algorithm = B43_SEC_ALGO_WEP40;
2823 else
2824 algorithm = B43_SEC_ALGO_WEP104;
2825 break;
2826 case ALG_TKIP:
2827 algorithm = B43_SEC_ALGO_TKIP;
2828 break;
2829 case ALG_CCMP:
2830 algorithm = B43_SEC_ALGO_AES;
2831 break;
2832 default:
2833 B43_WARN_ON(1);
c6dfc9a8 2834 goto out_unlock;
e4d6b795 2835 }
e4d6b795
MB		 2836 index = (u8) (key->keyidx);
2837 if (index > 3)
e4d6b795 2838 goto out_unlock;
e4d6b795
MB		 2839
2840 switch (cmd) {
2841 case SET_KEY:
2842 if (algorithm == B43_SEC_ALGO_TKIP) {
2843 /* FIXME: No TKIP hardware encryption for now. */
2844 err = -EOPNOTSUPP;
2845 goto out_unlock;
2846 }
2847
2848 if (is_broadcast_ether_addr(addr)) {
2849 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2850 err = b43_key_write(dev, index, algorithm,
2851 key->key, key->keylen, NULL, key);
2852 } else {
2853 /*
2854 * either pairwise key or address is 00:00:00:00:00:00
2855 * for transmit-only keys
2856 */
2857 err = b43_key_write(dev, -1, algorithm,
2858 key->key, key->keylen, addr, key);
2859 }
2860 if (err)
2861 goto out_unlock;
2862
2863 if (algorithm == B43_SEC_ALGO_WEP40 ||
2864 algorithm == B43_SEC_ALGO_WEP104) {
2865 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2866 } else {
2867 b43_hf_write(dev,
2868 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2869 }
2870 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2871 break;
2872 case DISABLE_KEY: {
2873 err = b43_key_clear(dev, key->hw_key_idx);
2874 if (err)
2875 goto out_unlock;
2876 break;
2877 }
2878 default:
2879 B43_WARN_ON(1);
2880 }
2881out_unlock:
2882 spin_unlock_irqrestore(&wl->irq_lock, flags);
2883 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2884 if (!err) {
2885 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
0795af57 2886 "mac: %s\n",
e4d6b795 2887 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
0795af57 2888 print_mac(mac, addr));
e4d6b795
MB		 2889 }
2890 return err;
2891}
2892
40faacc4
MB		 2893static void b43_op_configure_filter(struct ieee80211_hw *hw,
2894 unsigned int changed, unsigned int *fflags,
2895 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 2896{
2897 struct b43_wl *wl = hw_to_b43_wl(hw);
2898 struct b43_wldev *dev = wl->current_dev;
2899 unsigned long flags;
2900
4150c572
JB		 2901 if (!dev) {
2902 *fflags = 0;
e4d6b795 2903 return;
e4d6b795 2904 }
4150c572
JB		 2905
2906 spin_lock_irqsave(&wl->irq_lock, flags);
2907 *fflags &= FIF_PROMISC_IN_BSS |
2908 FIF_ALLMULTI |
2909 FIF_FCSFAIL |
2910 FIF_PLCPFAIL |
2911 FIF_CONTROL |
2912 FIF_OTHER_BSS |
2913 FIF_BCN_PRBRESP_PROMISC;
2914
2915 changed &= FIF_PROMISC_IN_BSS |
2916 FIF_ALLMULTI |
2917 FIF_FCSFAIL |
2918 FIF_PLCPFAIL |
2919 FIF_CONTROL |
2920 FIF_OTHER_BSS |
2921 FIF_BCN_PRBRESP_PROMISC;
2922
2923 wl->filter_flags = *fflags;
2924
2925 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2926 b43_adjust_opmode(dev);
e4d6b795
MB		 2927 spin_unlock_irqrestore(&wl->irq_lock, flags);
2928}
2929
40faacc4
MB		 2930static int b43_op_config_interface(struct ieee80211_hw *hw,
2931 int if_id,
2932 struct ieee80211_if_conf *conf)
e4d6b795
MB		 2933{
2934 struct b43_wl *wl = hw_to_b43_wl(hw);
2935 struct b43_wldev *dev = wl->current_dev;
2936 unsigned long flags;
2937
2938 if (!dev)
2939 return -ENODEV;
2940 mutex_lock(&wl->mutex);
2941 spin_lock_irqsave(&wl->irq_lock, flags);
4150c572
JB		 2942 B43_WARN_ON(wl->if_id != if_id);
2943 if (conf->bssid)
2944 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2945 else
2946 memset(wl->bssid, 0, ETH_ALEN);
2947 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2948 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2949 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2950 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2951 if (conf->beacon)
2952 b43_refresh_templates(dev, conf->beacon);
e4d6b795 2953 }
4150c572 2954 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 2955 }
2956 spin_unlock_irqrestore(&wl->irq_lock, flags);
2957 mutex_unlock(&wl->mutex);
2958
2959 return 0;
2960}
2961
2962/* Locking: wl->mutex */
2963static void b43_wireless_core_stop(struct b43_wldev *dev)
2964{
2965 struct b43_wl *wl = dev->wl;
2966 unsigned long flags;
2967
2968 if (b43_status(dev) < B43_STAT_STARTED)
2969 return;
a19d12d7
SB		 2970
2971 /* Disable and sync interrupts. We must do this before than
2972 * setting the status to INITIALIZED, as the interrupt handler
2973 * won't care about IRQs then. */
2974 spin_lock_irqsave(&wl->irq_lock, flags);
2975 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
2976 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
2977 spin_unlock_irqrestore(&wl->irq_lock, flags);
2978 b43_synchronize_irq(dev);
2979
e4d6b795
MB		 2980 b43_set_status(dev, B43_STAT_INITIALIZED);
2981
2982 mutex_unlock(&wl->mutex);
2983 /* Must unlock as it would otherwise deadlock. No races here.
2984 * Cancel the possibly running self-rearming periodic work. */
2985 cancel_delayed_work_sync(&dev->periodic_work);
2986 mutex_lock(&wl->mutex);
2987
2988 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
2989
e4d6b795
MB		 2990 b43_mac_suspend(dev);
2991 free_irq(dev->dev->irq, dev);
2992 b43dbg(wl, "Wireless interface stopped\n");
2993}
2994
2995/* Locking: wl->mutex */
2996static int b43_wireless_core_start(struct b43_wldev *dev)
2997{
2998 int err;
2999
3000 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3001
3002 drain_txstatus_queue(dev);
3003 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3004 IRQF_SHARED, KBUILD_MODNAME, dev);
3005 if (err) {
3006 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3007 goto out;
3008 }
3009
3010 /* We are ready to run. */
3011 b43_set_status(dev, B43_STAT_STARTED);
3012
3013 /* Start data flow (TX/RX). */
3014 b43_mac_enable(dev);
3015 b43_interrupt_enable(dev, dev->irq_savedstate);
3016 ieee80211_start_queues(dev->wl->hw);
3017
3018 /* Start maintainance work */
3019 b43_periodic_tasks_setup(dev);
3020
3021 b43dbg(dev->wl, "Wireless interface started\n");
3022 out:
3023 return err;
3024}
3025
3026/* Get PHY and RADIO versioning numbers */
3027static int b43_phy_versioning(struct b43_wldev *dev)
3028{
3029 struct b43_phy *phy = &dev->phy;
3030 u32 tmp;
3031 u8 analog_type;
3032 u8 phy_type;
3033 u8 phy_rev;
3034 u16 radio_manuf;
3035 u16 radio_ver;
3036 u16 radio_rev;
3037 int unsupported = 0;
3038
3039 /* Get PHY versioning */
3040 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3041 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3042 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3043 phy_rev = (tmp & B43_PHYVER_VERSION);
3044 switch (phy_type) {
3045 case B43_PHYTYPE_A:
3046 if (phy_rev >= 4)
3047 unsupported = 1;
3048 break;
3049 case B43_PHYTYPE_B:
3050 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3051 && phy_rev != 7)
3052 unsupported = 1;
3053 break;
3054 case B43_PHYTYPE_G:
013978b6 3055 if (phy_rev > 9)
e4d6b795
MB		 3056 unsupported = 1;
3057 break;
d5c71e46
MB		 3058#ifdef CONFIG_B43_NPHY
3059 case B43_PHYTYPE_N:
3060 if (phy_rev > 1)
3061 unsupported = 1;
3062 break;
3063#endif
e4d6b795
MB		 3064 default:
3065 unsupported = 1;
3066 };
3067 if (unsupported) {
3068 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3069 "(Analog %u, Type %u, Revision %u)\n",
3070 analog_type, phy_type, phy_rev);
3071 return -EOPNOTSUPP;
3072 }
3073 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3074 analog_type, phy_type, phy_rev);
3075
3076 /* Get RADIO versioning */
3077 if (dev->dev->bus->chip_id == 0x4317) {
3078 if (dev->dev->bus->chip_rev == 0)
3079 tmp = 0x3205017F;
3080 else if (dev->dev->bus->chip_rev == 1)
3081 tmp = 0x4205017F;
3082 else
3083 tmp = 0x5205017F;
3084 } else {
3085 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3086 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3087 tmp <<= 16;
3088 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3089 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3090 }
3091 radio_manuf = (tmp & 0x00000FFF);
3092 radio_ver = (tmp & 0x0FFFF000) >> 12;
3093 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3094 if (radio_manuf != 0x17F /* Broadcom */)
3095 unsupported = 1;
e4d6b795
MB		 3096 switch (phy_type) {
3097 case B43_PHYTYPE_A:
3098 if (radio_ver != 0x2060)
3099 unsupported = 1;
3100 if (radio_rev != 1)
3101 unsupported = 1;
3102 if (radio_manuf != 0x17F)
3103 unsupported = 1;
3104 break;
3105 case B43_PHYTYPE_B:
3106 if ((radio_ver & 0xFFF0) != 0x2050)
3107 unsupported = 1;
3108 break;
3109 case B43_PHYTYPE_G:
3110 if (radio_ver != 0x2050)
3111 unsupported = 1;
3112 break;
96c755a3
MB		 3113 case B43_PHYTYPE_N:
3114 if (radio_ver != 5)
3115 unsupported = 1;
3116 break;
e4d6b795
MB		 3117 default:
3118 B43_WARN_ON(1);
3119 }
3120 if (unsupported) {
3121 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3122 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3123 radio_manuf, radio_ver, radio_rev);
3124 return -EOPNOTSUPP;
3125 }
3126 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3127 radio_manuf, radio_ver, radio_rev);
3128
3129 phy->radio_manuf = radio_manuf;
3130 phy->radio_ver = radio_ver;
3131 phy->radio_rev = radio_rev;
3132
3133 phy->analog = analog_type;
3134 phy->type = phy_type;
3135 phy->rev = phy_rev;
3136
3137 return 0;
3138}
3139
3140static void setup_struct_phy_for_init(struct b43_wldev *dev,
3141 struct b43_phy *phy)
3142{
3143 struct b43_txpower_lo_control *lo;
3144 int i;
3145
3146 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3147 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3148
e4d6b795
MB		 3149 phy->aci_enable = 0;
3150 phy->aci_wlan_automatic = 0;
3151 phy->aci_hw_rssi = 0;
3152
fda9abcf
MB		 3153 phy->radio_off_context.valid = 0;
3154
e4d6b795
MB		 3155 lo = phy->lo_control;
3156 if (lo) {
3157 memset(lo, 0, sizeof(*(phy->lo_control)));
3158 lo->rebuild = 1;
3159 lo->tx_bias = 0xFF;
3160 }
3161 phy->max_lb_gain = 0;
3162 phy->trsw_rx_gain = 0;
3163 phy->txpwr_offset = 0;
3164
3165 /* NRSSI */
3166 phy->nrssislope = 0;
3167 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3168 phy->nrssi[i] = -1000;
3169 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3170 phy->nrssi_lt[i] = i;
3171
3172 phy->lofcal = 0xFFFF;
3173 phy->initval = 0xFFFF;
3174
e4d6b795
MB		 3175 phy->interfmode = B43_INTERFMODE_NONE;
3176 phy->channel = 0xFF;
3177
3178 phy->hardware_power_control = !!modparam_hwpctl;
8ed7fc48
MB		 3179
3180 /* PHY TX errors counter. */
3181 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3182
3183 /* OFDM-table address caching. */
3184 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
e4d6b795
MB		 3185}
3186
3187static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3188{
aa6c7ae2
MB		 3189 dev->dfq_valid = 0;
3190
6a724d68
MB		 3191 /* Assume the radio is enabled. If it's not enabled, the state will
3192 * immediately get fixed on the first periodic work run. */
3193 dev->radio_hw_enable = 1;
e4d6b795
MB		 3194
3195 /* Stats */
3196 memset(&dev->stats, 0, sizeof(dev->stats));
3197
3198 setup_struct_phy_for_init(dev, &dev->phy);
3199
3200 /* IRQ related flags */
3201 dev->irq_reason = 0;
3202 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3203 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3204
3205 dev->mac_suspended = 1;
3206
3207 /* Noise calculation context */
3208 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3209}
3210
3211static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3212{
3213 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3214 u32 hf;
3215
95de2841 3216 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 3217 return;
3218 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3219 return;
3220
3221 hf = b43_hf_read(dev);
95de2841 3222 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 3223 hf |= B43_HF_BTCOEXALT;
3224 else
3225 hf |= B43_HF_BTCOEX;
3226 b43_hf_write(dev, hf);
3227 //TODO
3228}
3229
3230static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3231{ //TODO
3232}
3233
3234static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3235{
3236#ifdef CONFIG_SSB_DRIVER_PCICORE
3237 struct ssb_bus *bus = dev->dev->bus;
3238 u32 tmp;
3239
3240 if (bus->pcicore.dev &&
3241 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3242 bus->pcicore.dev->id.revision <= 5) {
3243 /* IMCFGLO timeouts workaround. */
3244 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3245 tmp &= ~SSB_IMCFGLO_REQTO;
3246 tmp &= ~SSB_IMCFGLO_SERTO;
3247 switch (bus->bustype) {
3248 case SSB_BUSTYPE_PCI:
3249 case SSB_BUSTYPE_PCMCIA:
3250 tmp |= 0x32;
3251 break;
3252 case SSB_BUSTYPE_SSB:
3253 tmp |= 0x53;
3254 break;
3255 }
3256 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3257 }
3258#endif /* CONFIG_SSB_DRIVER_PCICORE */
3259}
3260
74cfdba7
MB		 3261/* Write the short and long frame retry limit values. */
3262static void b43_set_retry_limits(struct b43_wldev *dev,
3263 unsigned int short_retry,
3264 unsigned int long_retry)
3265{
3266 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3267 * the chip-internal counter. */
3268 short_retry = min(short_retry, (unsigned int)0xF);
3269 long_retry = min(long_retry, (unsigned int)0xF);
3270
3271 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3272 short_retry);
3273 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3274 long_retry);
3275}
3276
e4d6b795
MB		 3277/* Shutdown a wireless core */
3278/* Locking: wl->mutex */
3279static void b43_wireless_core_exit(struct b43_wldev *dev)
3280{
3281 struct b43_phy *phy = &dev->phy;
3282
3283 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3284 if (b43_status(dev) != B43_STAT_INITIALIZED)
3285 return;
3286 b43_set_status(dev, B43_STAT_UNINIT);
3287
1a8d1227 3288 b43_leds_exit(dev);
e4d6b795 3289 b43_rng_exit(dev->wl);
e4d6b795
MB		 3290 b43_dma_free(dev);
3291 b43_chip_exit(dev);
8e9f7529 3292 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3293 b43_switch_analog(dev, 0);
3294 if (phy->dyn_tssi_tbl)
3295 kfree(phy->tssi2dbm);
3296 kfree(phy->lo_control);
3297 phy->lo_control = NULL;
3298 ssb_device_disable(dev->dev, 0);
3299 ssb_bus_may_powerdown(dev->dev->bus);
3300}
3301
3302/* Initialize a wireless core */
3303static int b43_wireless_core_init(struct b43_wldev *dev)
3304{
3305 struct b43_wl *wl = dev->wl;
3306 struct ssb_bus *bus = dev->dev->bus;
3307 struct ssb_sprom *sprom = &bus->sprom;
3308 struct b43_phy *phy = &dev->phy;
3309 int err;
3310 u32 hf, tmp;
3311
3312 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3313
3314 err = ssb_bus_powerup(bus, 0);
3315 if (err)
3316 goto out;
3317 if (!ssb_device_is_enabled(dev->dev)) {
3318 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3319 b43_wireless_core_reset(dev, tmp);
3320 }
3321
3322 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3323 phy->lo_control =
3324 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3325 if (!phy->lo_control) {
3326 err = -ENOMEM;
3327 goto err_busdown;
3328 }
3329 }
3330 setup_struct_wldev_for_init(dev);
3331
3332 err = b43_phy_init_tssi2dbm_table(dev);
3333 if (err)
3334 goto err_kfree_lo_control;
3335
3336 /* Enable IRQ routing to this device. */
3337 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3338
3339 b43_imcfglo_timeouts_workaround(dev);
3340 b43_bluetooth_coext_disable(dev);
3341 b43_phy_early_init(dev);
3342 err = b43_chip_init(dev);
3343 if (err)
3344 goto err_kfree_tssitbl;
3345 b43_shm_write16(dev, B43_SHM_SHARED,
3346 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3347 hf = b43_hf_read(dev);
3348 if (phy->type == B43_PHYTYPE_G) {
3349 hf |= B43_HF_SYMW;
3350 if (phy->rev == 1)
3351 hf |= B43_HF_GDCW;
95de2841 3352 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 3353 hf |= B43_HF_OFDMPABOOST;
3354 } else if (phy->type == B43_PHYTYPE_B) {
3355 hf |= B43_HF_SYMW;
3356 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3357 hf &= ~B43_HF_GDCW;
3358 }
3359 b43_hf_write(dev, hf);
3360
74cfdba7
MB		 3361 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3362 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 3363 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3364 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3365
3366 /* Disable sending probe responses from firmware.
3367 * Setting the MaxTime to one usec will always trigger
3368 * a timeout, so we never send any probe resp.
3369 * A timeout of zero is infinite. */
3370 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3371
3372 b43_rate_memory_init(dev);
3373
3374 /* Minimum Contention Window */
3375 if (phy->type == B43_PHYTYPE_B) {
3376 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3377 } else {
3378 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3379 }
3380 /* Maximum Contention Window */
3381 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3382
03b29773 3383 err = b43_dma_init(dev);
e4d6b795
MB		 3384 if (err)
3385 goto err_chip_exit;
03b29773 3386 b43_qos_init(dev);
e4d6b795
MB		 3387
3388//FIXME
3389#if 1
3390 b43_write16(dev, 0x0612, 0x0050);
3391 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3392 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3393#endif
3394
3395 b43_bluetooth_coext_enable(dev);
3396
3397 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3398 memset(wl->bssid, 0, ETH_ALEN);
4150c572
JB		 3399 memset(wl->mac_addr, 0, ETH_ALEN);
3400 b43_upload_card_macaddress(dev);
e4d6b795
MB		 3401 b43_security_init(dev);
3402 b43_rng_init(wl);
3403
3404 b43_set_status(dev, B43_STAT_INITIALIZED);
3405
1a8d1227
LF		 3406 b43_leds_init(dev);
3407out:
e4d6b795
MB		 3408 return err;
3409
3410 err_chip_exit:
3411 b43_chip_exit(dev);
3412 err_kfree_tssitbl:
3413 if (phy->dyn_tssi_tbl)
3414 kfree(phy->tssi2dbm);
3415 err_kfree_lo_control:
3416 kfree(phy->lo_control);
3417 phy->lo_control = NULL;
3418 err_busdown:
3419 ssb_bus_may_powerdown(bus);
3420 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3421 return err;
3422}
3423
40faacc4
MB		 3424static int b43_op_add_interface(struct ieee80211_hw *hw,
3425 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 3426{
3427 struct b43_wl *wl = hw_to_b43_wl(hw);
3428 struct b43_wldev *dev;
3429 unsigned long flags;
3430 int err = -EOPNOTSUPP;
4150c572
JB		 3431
3432 /* TODO: allow WDS/AP devices to coexist */
3433
3434 if (conf->type != IEEE80211_IF_TYPE_AP &&
3435 conf->type != IEEE80211_IF_TYPE_STA &&
3436 conf->type != IEEE80211_IF_TYPE_WDS &&
3437 conf->type != IEEE80211_IF_TYPE_IBSS)
3438 return -EOPNOTSUPP;
e4d6b795
MB		 3439
3440 mutex_lock(&wl->mutex);
4150c572 3441 if (wl->operating)
e4d6b795
MB		 3442 goto out_mutex_unlock;
3443
3444 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3445
3446 dev = wl->current_dev;
4150c572
JB		 3447 wl->operating = 1;
3448 wl->if_id = conf->if_id;
3449 wl->if_type = conf->type;
3450 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3451
3452 spin_lock_irqsave(&wl->irq_lock, flags);
3453 b43_adjust_opmode(dev);
3454 b43_upload_card_macaddress(dev);
3455 spin_unlock_irqrestore(&wl->irq_lock, flags);
3456
3457 err = 0;
3458 out_mutex_unlock:
3459 mutex_unlock(&wl->mutex);
3460
3461 return err;
3462}
3463
40faacc4
MB		 3464static void b43_op_remove_interface(struct ieee80211_hw *hw,
3465 struct ieee80211_if_init_conf *conf)
4150c572
JB		 3466{
3467 struct b43_wl *wl = hw_to_b43_wl(hw);
3468 struct b43_wldev *dev = wl->current_dev;
3469 unsigned long flags;
3470
3471 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3472
3473 mutex_lock(&wl->mutex);
3474
3475 B43_WARN_ON(!wl->operating);
3476 B43_WARN_ON(wl->if_id != conf->if_id);
3477
3478 wl->operating = 0;
3479
3480 spin_lock_irqsave(&wl->irq_lock, flags);
3481 b43_adjust_opmode(dev);
3482 memset(wl->mac_addr, 0, ETH_ALEN);
3483 b43_upload_card_macaddress(dev);
3484 spin_unlock_irqrestore(&wl->irq_lock, flags);
3485
3486 mutex_unlock(&wl->mutex);
3487}
3488
40faacc4 3489static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 3490{
3491 struct b43_wl *wl = hw_to_b43_wl(hw);
3492 struct b43_wldev *dev = wl->current_dev;
3493 int did_init = 0;
923403b8 3494 int err = 0;
4150c572 3495
1a8d1227
LF		 3496 /* First register RFkill.
3497 * LEDs that are registered later depend on it. */
3498 b43_rfkill_init(dev);
3499
4150c572
JB		 3500 mutex_lock(&wl->mutex);
3501
e4d6b795
MB		 3502 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3503 err = b43_wireless_core_init(dev);
3504 if (err)
3505 goto out_mutex_unlock;
3506 did_init = 1;
3507 }
4150c572 3508
e4d6b795
MB		 3509 if (b43_status(dev) < B43_STAT_STARTED) {
3510 err = b43_wireless_core_start(dev);
3511 if (err) {
3512 if (did_init)
3513 b43_wireless_core_exit(dev);
3514 goto out_mutex_unlock;
3515 }
3516 }
3517
4150c572 3518 out_mutex_unlock:
e4d6b795
MB		 3519 mutex_unlock(&wl->mutex);
3520
3521 return err;
3522}
3523
40faacc4 3524static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 3525{
3526 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 3527 struct b43_wldev *dev = wl->current_dev;
e4d6b795 3528
1a8d1227
LF		 3529 b43_rfkill_exit(dev);
3530
e4d6b795 3531 mutex_lock(&wl->mutex);
4150c572
JB		 3532 if (b43_status(dev) >= B43_STAT_STARTED)
3533 b43_wireless_core_stop(dev);
3534 b43_wireless_core_exit(dev);
e4d6b795
MB		 3535 mutex_unlock(&wl->mutex);
3536}
3537
74cfdba7
MB		 3538static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3539 u32 short_retry_limit, u32 long_retry_limit)
3540{
3541 struct b43_wl *wl = hw_to_b43_wl(hw);
3542 struct b43_wldev *dev;
3543 int err = 0;
3544
3545 mutex_lock(&wl->mutex);
3546 dev = wl->current_dev;
3547 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3548 err = -ENODEV;
3549 goto out_unlock;
3550 }
3551 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3552out_unlock:
3553 mutex_unlock(&wl->mutex);
3554
3555 return err;
3556}
3557
e4d6b795 3558static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 3559 .tx = b43_op_tx,
3560 .conf_tx = b43_op_conf_tx,
3561 .add_interface = b43_op_add_interface,
3562 .remove_interface = b43_op_remove_interface,
3563 .config = b43_op_config,
3564 .config_interface = b43_op_config_interface,
3565 .configure_filter = b43_op_configure_filter,
3566 .set_key = b43_op_set_key,
3567 .get_stats = b43_op_get_stats,
3568 .get_tx_stats = b43_op_get_tx_stats,
3569 .start = b43_op_start,
3570 .stop = b43_op_stop,
74cfdba7 3571 .set_retry_limit = b43_op_set_retry_limit,
e4d6b795
MB		 3572};
3573
3574/* Hard-reset the chip. Do not call this directly.
3575 * Use b43_controller_restart()
3576 */
3577static void b43_chip_reset(struct work_struct *work)
3578{
3579 struct b43_wldev *dev =
3580 container_of(work, struct b43_wldev, restart_work);
3581 struct b43_wl *wl = dev->wl;
3582 int err = 0;
3583 int prev_status;
3584
3585 mutex_lock(&wl->mutex);
3586
3587 prev_status = b43_status(dev);
3588 /* Bring the device down... */
3589 if (prev_status >= B43_STAT_STARTED)
3590 b43_wireless_core_stop(dev);
3591 if (prev_status >= B43_STAT_INITIALIZED)
3592 b43_wireless_core_exit(dev);
3593
3594 /* ...and up again. */
3595 if (prev_status >= B43_STAT_INITIALIZED) {
3596 err = b43_wireless_core_init(dev);
3597 if (err)
3598 goto out;
3599 }
3600 if (prev_status >= B43_STAT_STARTED) {
3601 err = b43_wireless_core_start(dev);
3602 if (err) {
3603 b43_wireless_core_exit(dev);
3604 goto out;
3605 }
3606 }
3607 out:
3608 mutex_unlock(&wl->mutex);
3609 if (err)
3610 b43err(wl, "Controller restart FAILED\n");
3611 else
3612 b43info(wl, "Controller restarted\n");
3613}
3614
3615static int b43_setup_modes(struct b43_wldev *dev,
96c755a3 3616 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 3617{
3618 struct ieee80211_hw *hw = dev->wl->hw;
3619 struct ieee80211_hw_mode *mode;
3620 struct b43_phy *phy = &dev->phy;
e4d6b795
MB		 3621 int err;
3622
96c755a3
MB		 3623 /* XXX: This function will go away soon, when mac80211
3624 * band stuff is rewritten. So this is just a hack.
3625 * For now we always claim GPHY mode, as there is no
3626 * support for NPHY and APHY in the device, yet.
3627 * This assumption is OK, as any B, N or A PHY will already
3628 * have died a horrible sanity check death earlier. */
3629
3630 mode = &phy->hwmodes[0];
3631 mode->mode = MODE_IEEE80211G;
3632 mode->num_channels = b43_2ghz_chantable_size;
3633 mode->channels = b43_2ghz_chantable;
3634 mode->num_rates = b43_g_ratetable_size;
3635 mode->rates = b43_g_ratetable;
3636 err = ieee80211_register_hwmode(hw, mode);
3637 if (err)
3638 return err;
3639 phy->possible_phymodes |= B43_PHYMODE_G;
e4d6b795
MB		 3640
3641 return 0;
3642}
3643
3644static void b43_wireless_core_detach(struct b43_wldev *dev)
3645{
3646 /* We release firmware that late to not be required to re-request
3647 * is all the time when we reinit the core. */
3648 b43_release_firmware(dev);
3649}
3650
3651static int b43_wireless_core_attach(struct b43_wldev *dev)
3652{
3653 struct b43_wl *wl = dev->wl;
3654 struct ssb_bus *bus = dev->dev->bus;
3655 struct pci_dev *pdev = bus->host_pci;
3656 int err;
96c755a3 3657 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 3658 u32 tmp;
3659
3660 /* Do NOT do any device initialization here.
3661 * Do it in wireless_core_init() instead.
3662 * This function is for gathering basic information about the HW, only.
3663 * Also some structs may be set up here. But most likely you want to have
3664 * that in core_init(), too.
3665 */
3666
3667 err = ssb_bus_powerup(bus, 0);
3668 if (err) {
3669 b43err(wl, "Bus powerup failed\n");
3670 goto out;
3671 }
3672 /* Get the PHY type. */
3673 if (dev->dev->id.revision >= 5) {
3674 u32 tmshigh;
3675
3676 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 3677 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3678 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 3679 } else
96c755a3 3680 B43_WARN_ON(1);
e4d6b795 3681
96c755a3 3682 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 3683 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3684 b43_wireless_core_reset(dev, tmp);
3685
3686 err = b43_phy_versioning(dev);
3687 if (err)
21954c36 3688 goto err_powerdown;
e4d6b795
MB		 3689 /* Check if this device supports multiband. */
3690 if (!pdev ||
3691 (pdev->device != 0x4312 &&
3692 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3693 /* No multiband support. */
96c755a3
MB		 3694 have_2ghz_phy = 0;
3695 have_5ghz_phy = 0;
e4d6b795
MB		 3696 switch (dev->phy.type) {
3697 case B43_PHYTYPE_A:
96c755a3 3698 have_5ghz_phy = 1;
e4d6b795
MB		 3699 break;
3700 case B43_PHYTYPE_G:
96c755a3
MB		 3701 case B43_PHYTYPE_N:
3702 have_2ghz_phy = 1;
e4d6b795
MB		 3703 break;
3704 default:
3705 B43_WARN_ON(1);
3706 }
3707 }
96c755a3
MB		 3708 if (dev->phy.type == B43_PHYTYPE_A) {
3709 /* FIXME */
3710 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3711 err = -EOPNOTSUPP;
3712 goto err_powerdown;
3713 }
3714 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 3715 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3716 b43_wireless_core_reset(dev, tmp);
3717
3718 err = b43_validate_chipaccess(dev);
3719 if (err)
21954c36 3720 goto err_powerdown;
96c755a3 3721 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 3722 if (err)
21954c36 3723 goto err_powerdown;
e4d6b795
MB		 3724
3725 /* Now set some default "current_dev" */
3726 if (!wl->current_dev)
3727 wl->current_dev = dev;
3728 INIT_WORK(&dev->restart_work, b43_chip_reset);
3729
8e9f7529 3730 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3731 b43_switch_analog(dev, 0);
3732 ssb_device_disable(dev->dev, 0);
3733 ssb_bus_may_powerdown(bus);
3734
3735out:
3736 return err;
3737
e4d6b795
MB		 3738err_powerdown:
3739 ssb_bus_may_powerdown(bus);
3740 return err;
3741}
3742
3743static void b43_one_core_detach(struct ssb_device *dev)
3744{
3745 struct b43_wldev *wldev;
3746 struct b43_wl *wl;
3747
3748 wldev = ssb_get_drvdata(dev);
3749 wl = wldev->wl;
3750 cancel_work_sync(&wldev->restart_work);
3751 b43_debugfs_remove_device(wldev);
3752 b43_wireless_core_detach(wldev);
3753 list_del(&wldev->list);
3754 wl->nr_devs--;
3755 ssb_set_drvdata(dev, NULL);
3756 kfree(wldev);
3757}
3758
3759static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3760{
3761 struct b43_wldev *wldev;
3762 struct pci_dev *pdev;
3763 int err = -ENOMEM;
3764
3765 if (!list_empty(&wl->devlist)) {
3766 /* We are not the first core on this chip. */
3767 pdev = dev->bus->host_pci;
3768 /* Only special chips support more than one wireless
3769 * core, although some of the other chips have more than
3770 * one wireless core as well. Check for this and
3771 * bail out early.
3772 */
3773 if (!pdev ||
3774 ((pdev->device != 0x4321) &&
3775 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3776 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3777 return -ENODEV;
3778 }
3779 }
3780
3781 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3782 if (!wldev)
3783 goto out;
3784
3785 wldev->dev = dev;
3786 wldev->wl = wl;
3787 b43_set_status(wldev, B43_STAT_UNINIT);
3788 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3789 tasklet_init(&wldev->isr_tasklet,
3790 (void (*)(unsigned long))b43_interrupt_tasklet,
3791 (unsigned long)wldev);
e4d6b795
MB		 3792 INIT_LIST_HEAD(&wldev->list);
3793
3794 err = b43_wireless_core_attach(wldev);
3795 if (err)
3796 goto err_kfree_wldev;
3797
3798 list_add(&wldev->list, &wl->devlist);
3799 wl->nr_devs++;
3800 ssb_set_drvdata(dev, wldev);
3801 b43_debugfs_add_device(wldev);
3802
3803 out:
3804 return err;
3805
3806 err_kfree_wldev:
3807 kfree(wldev);
3808 return err;
3809}
3810
3811static void b43_sprom_fixup(struct ssb_bus *bus)
3812{
3813 /* boardflags workarounds */
3814 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3815 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 3816 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 3817 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3818 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 3819 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
e4d6b795
MB		 3820}
3821
3822static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3823{
3824 struct ieee80211_hw *hw = wl->hw;
3825
3826 ssb_set_devtypedata(dev, NULL);
3827 ieee80211_free_hw(hw);
3828}
3829
3830static int b43_wireless_init(struct ssb_device *dev)
3831{
3832 struct ssb_sprom *sprom = &dev->bus->sprom;
3833 struct ieee80211_hw *hw;
3834 struct b43_wl *wl;
3835 int err = -ENOMEM;
3836
3837 b43_sprom_fixup(dev->bus);
3838
3839 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3840 if (!hw) {
3841 b43err(NULL, "Could not allocate ieee80211 device\n");
3842 goto out;
3843 }
3844
3845 /* fill hw info */
d8be11ee
JB		 3846 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3847 IEEE80211_HW_RX_INCLUDES_FCS;
e4d6b795
MB		 3848 hw->max_signal = 100;
3849 hw->max_rssi = -110;
3850 hw->max_noise = -110;
3851 hw->queues = 1; /* FIXME: hardware has more queues */
3852 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 3853 if (is_valid_ether_addr(sprom->et1mac))
3854 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 3855 else
95de2841 3856 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 3857
3858 /* Get and initialize struct b43_wl */
3859 wl = hw_to_b43_wl(hw);
3860 memset(wl, 0, sizeof(*wl));
3861 wl->hw = hw;
3862 spin_lock_init(&wl->irq_lock);
3863 spin_lock_init(&wl->leds_lock);
3864 mutex_init(&wl->mutex);
3865 INIT_LIST_HEAD(&wl->devlist);
3866
3867 ssb_set_devtypedata(dev, wl);
3868 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3869 err = 0;
3870 out:
3871 return err;
3872}
3873
3874static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3875{
3876 struct b43_wl *wl;
3877 int err;
3878 int first = 0;
3879
3880 wl = ssb_get_devtypedata(dev);
3881 if (!wl) {
3882 /* Probing the first core. Must setup common struct b43_wl */
3883 first = 1;
3884 err = b43_wireless_init(dev);
3885 if (err)
3886 goto out;
3887 wl = ssb_get_devtypedata(dev);
3888 B43_WARN_ON(!wl);
3889 }
3890 err = b43_one_core_attach(dev, wl);
3891 if (err)
3892 goto err_wireless_exit;
3893
3894 if (first) {
3895 err = ieee80211_register_hw(wl->hw);
3896 if (err)
3897 goto err_one_core_detach;
3898 }
3899
3900 out:
3901 return err;
3902
3903 err_one_core_detach:
3904 b43_one_core_detach(dev);
3905 err_wireless_exit:
3906 if (first)
3907 b43_wireless_exit(dev, wl);
3908 return err;
3909}
3910
3911static void b43_remove(struct ssb_device *dev)
3912{
3913 struct b43_wl *wl = ssb_get_devtypedata(dev);
3914 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3915
3916 B43_WARN_ON(!wl);
3917 if (wl->current_dev == wldev)
3918 ieee80211_unregister_hw(wl->hw);
3919
3920 b43_one_core_detach(dev);
3921
3922 if (list_empty(&wl->devlist)) {
3923 /* Last core on the chip unregistered.
3924 * We can destroy common struct b43_wl.
3925 */
3926 b43_wireless_exit(dev, wl);
3927 }
3928}
3929
3930/* Perform a hardware reset. This can be called from any context. */
3931void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3932{
3933 /* Must avoid requeueing, if we are in shutdown. */
3934 if (b43_status(dev) < B43_STAT_INITIALIZED)
3935 return;
3936 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3937 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3938}
3939
3940#ifdef CONFIG_PM
3941
3942static int b43_suspend(struct ssb_device *dev, pm_message_t state)
3943{
3944 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3945 struct b43_wl *wl = wldev->wl;
3946
3947 b43dbg(wl, "Suspending...\n");
3948
3949 mutex_lock(&wl->mutex);
3950 wldev->suspend_init_status = b43_status(wldev);
3951 if (wldev->suspend_init_status >= B43_STAT_STARTED)
3952 b43_wireless_core_stop(wldev);
3953 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
3954 b43_wireless_core_exit(wldev);
3955 mutex_unlock(&wl->mutex);
3956
3957 b43dbg(wl, "Device suspended.\n");
3958
3959 return 0;
3960}
3961
3962static int b43_resume(struct ssb_device *dev)
3963{
3964 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3965 struct b43_wl *wl = wldev->wl;
3966 int err = 0;
3967
3968 b43dbg(wl, "Resuming...\n");
3969
3970 mutex_lock(&wl->mutex);
3971 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
3972 err = b43_wireless_core_init(wldev);
3973 if (err) {
3974 b43err(wl, "Resume failed at core init\n");
3975 goto out;
3976 }
3977 }
3978 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
3979 err = b43_wireless_core_start(wldev);
3980 if (err) {
3981 b43_wireless_core_exit(wldev);
3982 b43err(wl, "Resume failed at core start\n");
3983 goto out;
3984 }
3985 }
3986 mutex_unlock(&wl->mutex);
3987
3988 b43dbg(wl, "Device resumed.\n");
3989 out:
3990 return err;
3991}
3992
3993#else /* CONFIG_PM */
3994# define b43_suspend NULL
3995# define b43_resume NULL
3996#endif /* CONFIG_PM */
3997
3998static struct ssb_driver b43_ssb_driver = {
3999 .name = KBUILD_MODNAME,
4000 .id_table = b43_ssb_tbl,
4001 .probe = b43_probe,
4002 .remove = b43_remove,
4003 .suspend = b43_suspend,
4004 .resume = b43_resume,
4005};
4006
4007static int __init b43_init(void)
4008{
4009 int err;
4010
4011 b43_debugfs_init();
4012 err = b43_pcmcia_init();
4013 if (err)
4014 goto err_dfs_exit;
4015 err = ssb_driver_register(&b43_ssb_driver);
4016 if (err)
4017 goto err_pcmcia_exit;
4018
4019 return err;
4020
4021err_pcmcia_exit:
4022 b43_pcmcia_exit();
4023err_dfs_exit:
4024 b43_debugfs_exit();
4025 return err;
4026}
4027
4028static void __exit b43_exit(void)
4029{
4030 ssb_driver_unregister(&b43_ssb_driver);
4031 b43_pcmcia_exit();
4032 b43_debugfs_exit();
4033}
4034
4035module_init(b43_init)
4036module_exit(b43_exit)
ubuntu-zesty-kernel mirror