[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / b43 / nphy.c

/*

  Broadcom B43 wireless driver
  IEEE 802.11n PHY support

  Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

#include <linux/delay.h>
#include <linux/types.h>

#include "b43.h"
#include "nphy.h"
#include "tables_nphy.h"


void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
{//TODO
}

void b43_nphy_xmitpower(struct b43_wldev *dev)
{//TODO
}

static void b43_chantab_radio_upload(struct b43_wldev *dev,
				     const struct b43_nphy_channeltab_entry *e)
{
	b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
	b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
	b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
	b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
	b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
	b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
	b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
	b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
	b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
	b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
	b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
	b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
	b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
	b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
	b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
	b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
	b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
	b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
	b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
	b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
	b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
	b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
}

static void b43_chantab_phy_upload(struct b43_wldev *dev,
				   const struct b43_nphy_channeltab_entry *e)
{
	b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
	b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
	b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
	b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
	b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
	b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
}

static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
{
	//TODO
}

/* Tune the hardware to a new channel. */
static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
{
	const struct b43_nphy_channeltab_entry *tabent;

	tabent = b43_nphy_get_chantabent(dev, channel);
	if (!tabent)
		return -ESRCH;

	//FIXME enable/disable band select upper20 in RXCTL
	if (0 /*FIXME 5Ghz*/)
		b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
	else
		b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
	b43_chantab_radio_upload(dev, tabent);
	udelay(50);
	b43_radio_write16(dev, B2055_VCO_CAL10, 5);
	b43_radio_write16(dev, B2055_VCO_CAL10, 45);
	b43_radio_write16(dev, B2055_VCO_CAL10, 65);
	udelay(300);
	if (0 /*FIXME 5Ghz*/)
		b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
	else
		b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
	b43_chantab_phy_upload(dev, tabent);
	b43_nphy_tx_power_fix(dev);

	return 0;
}

static void b43_radio_init2055_pre(struct b43_wldev *dev)
{
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
		     ~B43_NPHY_RFCTL_CMD_PORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
		    B43_NPHY_RFCTL_CMD_CHIP0PU |
		    B43_NPHY_RFCTL_CMD_OEPORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
		    B43_NPHY_RFCTL_CMD_PORFORCE);
}

static void b43_radio_init2055_post(struct b43_wldev *dev)
{
	struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
	struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
	int i;
	u16 val;

	b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
	msleep(1);
	if ((sprom->revision != 4) || !(sprom->boardflags_hi & 0x0002)) {
		if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
		    (binfo->type != 0x46D) ||
		    (binfo->rev < 0x41)) {
			b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
			b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
			msleep(1);
		}
	}
	b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
	msleep(1);
	b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
	msleep(1);
	b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
	msleep(1);
	b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
	msleep(1);
	b43_radio_set(dev, B2055_CAL_MISC, 0x1);
	msleep(1);
	b43_radio_set(dev, B2055_CAL_MISC, 0x40);
	msleep(1);
	for (i = 0; i < 100; i++) {
		val = b43_radio_read16(dev, B2055_CAL_COUT2);
		if (val & 0x80)
			break;
		udelay(10);
	}
	msleep(1);
	b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
	msleep(1);
	nphy_channel_switch(dev, dev->phy.channel);
	b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
	b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
	b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
	b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
}

/* Initialize a Broadcom 2055 N-radio */
static void b43_radio_init2055(struct b43_wldev *dev)
{
	b43_radio_init2055_pre(dev);
	if (b43_status(dev) < B43_STAT_INITIALIZED)
		b2055_upload_inittab(dev, 0, 1);
	else
		b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
	b43_radio_init2055_post(dev);
}

void b43_nphy_radio_turn_on(struct b43_wldev *dev)
{
	b43_radio_init2055(dev);
}

void b43_nphy_radio_turn_off(struct b43_wldev *dev)
{
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
		     ~B43_NPHY_RFCTL_CMD_EN);
}

#define ntab_upload(dev, offset, data) do { \
		unsigned int i;						\
		for (i = 0; i < (offset##_SIZE); i++)			\
			b43_ntab_write(dev, (offset) + i, (data)[i]);	\
	} while (0)

/* Upload the N-PHY tables. */
static void b43_nphy_tables_init(struct b43_wldev *dev)
{
	/* Static tables */
	ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
	ntab_upload(dev, B43_NTAB_FRAMELT, b43_ntab_framelookup);
	ntab_upload(dev, B43_NTAB_TMAP, b43_ntab_tmap);
	ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn);
	ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel);
	ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot);
	ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
	ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0);
	ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1);
	ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0);
	ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1);
	ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
	ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest);
	ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs);

	/* Volatile tables */
	ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10);
	ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11);
	ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0);
	ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1);
	ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0);
	ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1);
	ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
	ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
	ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0);
	ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1);
	ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0);
	ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
}

static void b43_nphy_workarounds(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	unsigned int i;

	b43_phy_set(dev, B43_NPHY_IQFLIP,
		    B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
	if (1 /* FIXME band is 2.4GHz */) {
		b43_phy_set(dev, B43_NPHY_CLASSCTL,
			    B43_NPHY_CLASSCTL_CCKEN);
	} else {
		b43_phy_mask(dev, B43_NPHY_CLASSCTL,
			     ~B43_NPHY_CLASSCTL_CCKEN);
	}
	b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
	b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);

	/* Fixup some tables */
	b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
	b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
	b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
	b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
	b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
	b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
	b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
	b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
	b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
	b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);

	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);

	//TODO set RF sequence

	/* Set narrowband clip threshold */
	b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
	b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);

	/* Set wideband clip 2 threshold */
	b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
			~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
			21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
	b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
			~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
			21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);

	/* Set Clip 2 detect */
	b43_phy_set(dev, B43_NPHY_C1_CGAINI,
		    B43_NPHY_C1_CGAINI_CL2DETECT);
	b43_phy_set(dev, B43_NPHY_C2_CGAINI,
		    B43_NPHY_C2_CGAINI_CL2DETECT);

	if (0 /*FIXME*/) {
		/* Set dwell lengths */
		b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
		b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
		b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
		b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);

		/* Set gain backoff */
		b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
				~B43_NPHY_C1_CGAINI_GAINBKOFF,
				1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
		b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
				~B43_NPHY_C2_CGAINI_GAINBKOFF,
				1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);

		/* Set HPVGA2 index */
		b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
				~B43_NPHY_C1_INITGAIN_HPVGA2,
				6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
		b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
				~B43_NPHY_C2_INITGAIN_HPVGA2,
				6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);

		//FIXME verify that the specs really mean to use autoinc here.
		for (i = 0; i < 3; i++)
			b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
	}

	/* Set minimum gain value */
	b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
			~B43_NPHY_C1_MINGAIN,
			23 << B43_NPHY_C1_MINGAIN_SHIFT);
	b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
			~B43_NPHY_C2_MINGAIN,
			23 << B43_NPHY_C2_MINGAIN_SHIFT);

	if (phy->rev < 2) {
		b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
			     ~B43_NPHY_SCRAM_SIGCTL_SCM);
	}

	/* Set phase track alpha and beta */
	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
}

static void b43_nphy_reset_cca(struct b43_wldev *dev)
{
	u16 bbcfg;

	ssb_write32(dev->dev, SSB_TMSLOW,
		    ssb_read32(dev->dev, SSB_TMSLOW) | SSB_TMSLOW_FGC);
	bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
	b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
	b43_phy_write(dev, B43_NPHY_BBCFG,
		      bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
	ssb_write32(dev->dev, SSB_TMSLOW,
		    ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
}

enum b43_nphy_rf_sequence {
	B43_RFSEQ_RX2TX,
	B43_RFSEQ_TX2RX,
	B43_RFSEQ_RESET2RX,
	B43_RFSEQ_UPDATE_GAINH,
	B43_RFSEQ_UPDATE_GAINL,
	B43_RFSEQ_UPDATE_GAINU,
};

static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
				       enum b43_nphy_rf_sequence seq)
{
	static const u16 trigger[] = {
		[B43_RFSEQ_RX2TX]		= B43_NPHY_RFSEQTR_RX2TX,
		[B43_RFSEQ_TX2RX]		= B43_NPHY_RFSEQTR_TX2RX,
		[B43_RFSEQ_RESET2RX]		= B43_NPHY_RFSEQTR_RST2RX,
		[B43_RFSEQ_UPDATE_GAINH]	= B43_NPHY_RFSEQTR_UPGH,
		[B43_RFSEQ_UPDATE_GAINL]	= B43_NPHY_RFSEQTR_UPGL,
		[B43_RFSEQ_UPDATE_GAINU]	= B43_NPHY_RFSEQTR_UPGU,
	};
	int i;

	B43_WARN_ON(seq >= ARRAY_SIZE(trigger));

	b43_phy_set(dev, B43_NPHY_RFSEQMODE,
		    B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
	b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
	for (i = 0; i < 200; i++) {
		if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
			goto ok;
		msleep(1);
	}
	b43err(dev->wl, "RF sequence status timeout\n");
ok:
	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
		     ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
}

static void b43_nphy_bphy_init(struct b43_wldev *dev)
{
	unsigned int i;
	u16 val;

	val = 0x1E1F;
	for (i = 0; i < 14; i++) {
		b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
		val -= 0x202;
	}
	val = 0x3E3F;
	for (i = 0; i < 16; i++) {
		b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
		val -= 0x202;
	}
	b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
}

/* RSSI Calibration */
static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
{
	//TODO
}

int b43_phy_initn(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	u16 tmp;

	//TODO: Spectral management
	b43_nphy_tables_init(dev);

	/* Clear all overrides */
	b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
		     ~(B43_NPHY_RFSEQMODE_CAOVER |
		       B43_NPHY_RFSEQMODE_TROVER));
	b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);

	tmp = (phy->rev < 2) ? 64 : 59;
	b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
			~B43_NPHY_BPHY_CTL3_SCALE,
			tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);

	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);

	b43_phy_write(dev, B43_NPHY_TXREALFD, 184);
	b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 200);
	b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 80);
	b43_phy_write(dev, B43_NPHY_C2_BCLIPBKOFF, 511);

	//TODO MIMO-Config
	//TODO Update TX/RX chain

	if (phy->rev < 2) {
		b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
		b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
	}
	b43_nphy_workarounds(dev);
	b43_nphy_reset_cca(dev);

	ssb_write32(dev->dev, SSB_TMSLOW,
		    ssb_read32(dev->dev, SSB_TMSLOW) | B43_TMSLOW_MACPHYCLKEN);
	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);

	b43_phy_read(dev, B43_NPHY_CLASSCTL); /* dummy read */
	//TODO read core1/2 clip1 thres regs

	if (1 /* FIXME Band is 2.4GHz */)
		b43_nphy_bphy_init(dev);
	//TODO disable TX power control
	//TODO Fix the TX power settings
	//TODO Init periodic calibration with reason 3
	b43_nphy_rssi_cal(dev, 2);
	b43_nphy_rssi_cal(dev, 0);
	b43_nphy_rssi_cal(dev, 1);
	//TODO get TX gain
	//TODO init superswitch
	//TODO calibrate LO
	//TODO idle TSSI TX pctl
	//TODO TX power control power setup
	//TODO table writes
	//TODO TX power control coefficients
	//TODO enable TX power control
	//TODO control antenna selection
	//TODO init radar detection
	//TODO reset channel if changed

	b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
	return 0;
}

static int b43_nphy_op_allocate(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy;

	nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
	if (!nphy)
		return -ENOMEM;
	dev->phy.n = nphy;

	//TODO init struct b43_phy_n

	return 0;
}

static int b43_nphy_op_init(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;
	int err;

	err = b43_phy_initn(dev);
	if (err)
		return err;
	nphy->initialised = 1;

	return 0;
}

static void b43_nphy_op_exit(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy = dev->phy.n;

	if (nphy->initialised) {
		//TODO
		nphy->initialised = 0;
	}
	//TODO
	kfree(nphy);
	dev->phy.n = NULL;
}

static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
{
#if B43_DEBUG
	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
		/* OFDM registers are onnly available on A/G-PHYs */
		b43err(dev->wl, "Invalid OFDM PHY access at "
		       "0x%04X on N-PHY\n", offset);
		dump_stack();
	}
	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
		/* Ext-G registers are only available on G-PHYs */
		b43err(dev->wl, "Invalid EXT-G PHY access at "
		       "0x%04X on N-PHY\n", offset);
		dump_stack();
	}
#endif /* B43_DEBUG */
}

static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
{
	check_phyreg(dev, reg);
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_PHY_DATA);
}

static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	check_phyreg(dev, reg);
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	b43_write16(dev, B43_MMIO_PHY_DATA, value);
}

static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
{
	/* Register 1 is a 32-bit register. */
	B43_WARN_ON(reg == 1);
	/* N-PHY needs 0x100 for read access */
	reg |= 0x100;

	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
}

static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	/* Register 1 is a 32-bit register. */
	B43_WARN_ON(reg == 1);

	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
	b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
}

static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
					enum rfkill_state state)
{//TODO
}

static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
				      unsigned int new_channel)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		if ((new_channel < 1) || (new_channel > 14))
			return -EINVAL;
	} else {
		if (new_channel > 200)
			return -EINVAL;
	}

	return nphy_channel_switch(dev, new_channel);
}

static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
		return 1;
	return 36;
}

static void b43_nphy_op_xmitpower(struct b43_wldev *dev)
{//TODO
}

const struct b43_phy_operations b43_phyops_n = {
	.allocate		= b43_nphy_op_allocate,
	.init			= b43_nphy_op_init,
	.exit			= b43_nphy_op_exit,
	.phy_read		= b43_nphy_op_read,
	.phy_write		= b43_nphy_op_write,
	.radio_read		= b43_nphy_op_radio_read,
	.radio_write		= b43_nphy_op_radio_write,
	.software_rfkill	= b43_nphy_op_software_rfkill,
	.switch_channel		= b43_nphy_op_switch_channel,
	.get_default_chan	= b43_nphy_op_get_default_chan,
	.xmitpower		= b43_nphy_op_xmitpower,
};
Commit	Line	Data
424047e6 MB	1	/*
	2
	3	Broadcom B43 wireless driver
	4	IEEE 802.11n PHY support
	5
	6	Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; see the file COPYING. If not, write to
	20	the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
	21	Boston, MA 02110-1301, USA.
	22
	23	*/
	24
819d772b JL	25	#include <linux/delay.h>
	26	#include <linux/types.h>
	27
424047e6 MB	28	#include "b43.h"
424047e6 MB	29	#include "nphy.h"
53a6e234	30	#include "tables_nphy.h"
424047e6 MB	31
424047e6 MB	32
53a6e234 MB	33	void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
	34	{//TODO
	35	}
	36
	37	void b43_nphy_xmitpower(struct b43_wldev *dev)
	38	{//TODO
	39	}
	40
d1591314 MB	41	static void b43_chantab_radio_upload(struct b43_wldev *dev,
	42	const struct b43_nphy_channeltab_entry *e)
	43	{
	44	b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
	45	b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
	46	b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
	47	b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
	48	b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
	49	b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
	50	b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
	51	b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
	52	b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
	53	b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
	54	b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
	55	b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
	56	b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
	57	b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
	58	b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
	59	b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
	60	b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
	61	b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
	62	b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
	63	b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
	64	b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
	65	b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
	66	}
	67
	68	static void b43_chantab_phy_upload(struct b43_wldev *dev,
	69	const struct b43_nphy_channeltab_entry *e)
	70	{
	71	b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
	72	b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
	73	b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
	74	b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
	75	b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
	76	b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
	77	}
	78
	79	static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
	80	{
	81	//TODO
	82	}
	83
ef1a628d MB	84	/* Tune the hardware to a new channel. */
ef1a628d MB	85	static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234	86	{
d1591314 MB	87	const struct b43_nphy_channeltab_entry *tabent;
	88
	89	tabent = b43_nphy_get_chantabent(dev, channel);
	90	if (!tabent)
	91	return -ESRCH;
	92
	93	//FIXME enable/disable band select upper20 in RXCTL
	94	if (0 /FIXME 5Ghz/)
	95	b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
	96	else
	97	b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
	98	b43_chantab_radio_upload(dev, tabent);
	99	udelay(50);
	100	b43_radio_write16(dev, B2055_VCO_CAL10, 5);
	101	b43_radio_write16(dev, B2055_VCO_CAL10, 45);
	102	b43_radio_write16(dev, B2055_VCO_CAL10, 65);
	103	udelay(300);
	104	if (0 /FIXME 5Ghz/)
	105	b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
	106	else
	107	b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
	108	b43_chantab_phy_upload(dev, tabent);
	109	b43_nphy_tx_power_fix(dev);
53a6e234	110
d1591314	111	return 0;
53a6e234 MB	112	}
	113
	114	static void b43_radio_init2055_pre(struct b43_wldev *dev)
	115	{
	116	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
	117	~B43_NPHY_RFCTL_CMD_PORFORCE);
	118	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
	119	B43_NPHY_RFCTL_CMD_CHIP0PU \|
	120	B43_NPHY_RFCTL_CMD_OEPORFORCE);
	121	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
	122	B43_NPHY_RFCTL_CMD_PORFORCE);
	123	}
	124
	125	static void b43_radio_init2055_post(struct b43_wldev *dev)
	126	{
	127	struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
	128	struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
	129	int i;
	130	u16 val;
	131
	132	b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
	133	msleep(1);
	134	if ((sprom->revision != 4) \|\| !(sprom->boardflags_hi & 0x0002)) {
	135	if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) \|\|
	136	(binfo->type != 0x46D) \|\|
	137	(binfo->rev < 0x41)) {
	138	b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
	139	b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
	140	msleep(1);
	141	}
	142	}
	143	b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
	144	msleep(1);
	145	b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
	146	msleep(1);
	147	b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
	148	msleep(1);
	149	b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
	150	msleep(1);
	151	b43_radio_set(dev, B2055_CAL_MISC, 0x1);
	152	msleep(1);
	153	b43_radio_set(dev, B2055_CAL_MISC, 0x40);
	154	msleep(1);
	155	for (i = 0; i < 100; i++) {
	156	val = b43_radio_read16(dev, B2055_CAL_COUT2);
	157	if (val & 0x80)
	158	break;
	159	udelay(10);
	160	}
	161	msleep(1);
	162	b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
	163	msleep(1);
ef1a628d	164	nphy_channel_switch(dev, dev->phy.channel);
53a6e234 MB	165	b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
	166	b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
	167	b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
	168	b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
	169	}
	170
	171	/* Initialize a Broadcom 2055 N-radio */
	172	static void b43_radio_init2055(struct b43_wldev *dev)
	173	{
	174	b43_radio_init2055_pre(dev);
	175	if (b43_status(dev) < B43_STAT_INITIALIZED)
	176	b2055_upload_inittab(dev, 0, 1);
	177	else
	178	b2055_upload_inittab(dev, 0/FIXME on 5ghz band/, 0);
	179	b43_radio_init2055_post(dev);
	180	}
	181
	182	void b43_nphy_radio_turn_on(struct b43_wldev *dev)
	183	{
	184	b43_radio_init2055(dev);
	185	}
	186
	187	void b43_nphy_radio_turn_off(struct b43_wldev *dev)
	188	{
	189	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
	190	~B43_NPHY_RFCTL_CMD_EN);
	191	}
	192
95b66bad MB	193	#define ntab_upload(dev, offset, data) do { \
	194	unsigned int i; \
	195	for (i = 0; i < (offset##_SIZE); i++) \
	196	b43_ntab_write(dev, (offset) + i, (data)[i]); \
	197	} while (0)
	198
	199	/* Upload the N-PHY tables. */
	200	static void b43_nphy_tables_init(struct b43_wldev *dev)
	201	{
	202	/* Static tables */
	203	ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
	204	ntab_upload(dev, B43_NTAB_FRAMELT, b43_ntab_framelookup);
	205	ntab_upload(dev, B43_NTAB_TMAP, b43_ntab_tmap);
	206	ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn);
	207	ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel);
	208	ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot);
	209	ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
	210	ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0);
	211	ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1);
	212	ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0);
	213	ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1);
	214	ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
	215	ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest);
	216	ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs);
	217
	218	/* Volatile tables */
	219	ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10);
	220	ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11);
	221	ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0);
	222	ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1);
	223	ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0);
	224	ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1);
	225	ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
	226	ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
	227	ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0);
	228	ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1);
	229	ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0);
	230	ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
	231	}
	232
	233	static void b43_nphy_workarounds(struct b43_wldev *dev)
	234	{
	235	struct b43_phy *phy = &dev->phy;
	236	unsigned int i;
	237
	238	b43_phy_set(dev, B43_NPHY_IQFLIP,
	239	B43_NPHY_IQFLIP_ADC1 \| B43_NPHY_IQFLIP_ADC2);
95b66bad MB	240	if (1 /* FIXME band is 2.4GHz */) {
	241	b43_phy_set(dev, B43_NPHY_CLASSCTL,
	242	B43_NPHY_CLASSCTL_CCKEN);
	243	} else {
	244	b43_phy_mask(dev, B43_NPHY_CLASSCTL,
	245	~B43_NPHY_CLASSCTL_CCKEN);
	246	}
	247	b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
	248	b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
	249
	250	/* Fixup some tables */
	251	b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
	252	b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
	253	b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
	254	b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
	255	b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
	256	b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
	257	b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
	258	b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
	259	b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
	260	b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
	261
	262	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
	263	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
	264	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
	265	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
	266
	267	//TODO set RF sequence
	268
	269	/* Set narrowband clip threshold */
	270	b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
	271	b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
	272
	273	/* Set wideband clip 2 threshold */
	274	b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
	275	~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
	276	21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
	277	b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
	278	~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
	279	21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
	280
	281	/* Set Clip 2 detect */
	282	b43_phy_set(dev, B43_NPHY_C1_CGAINI,
	283	B43_NPHY_C1_CGAINI_CL2DETECT);
	284	b43_phy_set(dev, B43_NPHY_C2_CGAINI,
	285	B43_NPHY_C2_CGAINI_CL2DETECT);
	286
	287	if (0 /FIXME/) {
	288	/* Set dwell lengths */
	289	b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
	290	b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
	291	b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
	292	b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
	293
	294	/* Set gain backoff */
	295	b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
	296	~B43_NPHY_C1_CGAINI_GAINBKOFF,
	297	1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
	298	b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
	299	~B43_NPHY_C2_CGAINI_GAINBKOFF,
	300	1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
	301
	302	/* Set HPVGA2 index */
	303	b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
304	~B43_NPHY_C1_INITGAIN_HPVGA2,
305	6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
306	b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
307	~B43_NPHY_C2_INITGAIN_HPVGA2,
308	6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
309
310	//FIXME verify that the specs really mean to use autoinc here.
311	for (i = 0; i < 3; i++)
312	b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
313	}
314
315	/* Set minimum gain value */
316	b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
317	~B43_NPHY_C1_MINGAIN,
318	23 << B43_NPHY_C1_MINGAIN_SHIFT);
319	b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
320	~B43_NPHY_C2_MINGAIN,
321	23 << B43_NPHY_C2_MINGAIN_SHIFT);
322
323	if (phy->rev < 2) {
324	b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
325	~B43_NPHY_SCRAM_SIGCTL_SCM);
326	}
327
328	/* Set phase track alpha and beta */
329	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
330	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
331	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
332	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
333	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
334	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
335	}
336
337	static void b43_nphy_reset_cca(struct b43_wldev *dev)
338	{
339	u16 bbcfg;
340
341	ssb_write32(dev->dev, SSB_TMSLOW,
342	ssb_read32(dev->dev, SSB_TMSLOW) \| SSB_TMSLOW_FGC);
343	bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
344	b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
345	b43_phy_write(dev, B43_NPHY_BBCFG,
346	bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
347	ssb_write32(dev->dev, SSB_TMSLOW,
348	ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
349	}
350
351	enum b43_nphy_rf_sequence {
352	B43_RFSEQ_RX2TX,
353	B43_RFSEQ_TX2RX,
354	B43_RFSEQ_RESET2RX,
355	B43_RFSEQ_UPDATE_GAINH,
356	B43_RFSEQ_UPDATE_GAINL,
357	B43_RFSEQ_UPDATE_GAINU,
358	};
359
360	static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
361	enum b43_nphy_rf_sequence seq)
362	{
363	static const u16 trigger[] = {
364	[B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
365	[B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
366	[B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
367	[B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
368	[B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
369	[B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
370	};
371	int i;
372
373	B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
374
375	b43_phy_set(dev, B43_NPHY_RFSEQMODE,
376	B43_NPHY_RFSEQMODE_CAOVER \| B43_NPHY_RFSEQMODE_TROVER);
377	b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
378	for (i = 0; i < 200; i++) {
379	if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
380	goto ok;
381	msleep(1);
382	}
383	b43err(dev->wl, "RF sequence status timeout\n");
384	ok:
385	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
386	~(B43_NPHY_RFSEQMODE_CAOVER \| B43_NPHY_RFSEQMODE_TROVER));
387	}
388
389	static void b43_nphy_bphy_init(struct b43_wldev *dev)
390	{
391	unsigned int i;
392	u16 val;
393
394	val = 0x1E1F;
395	for (i = 0; i < 14; i++) {
396	b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
397	val -= 0x202;
398	}
399	val = 0x3E3F;
400	for (i = 0; i < 16; i++) {
401	b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
402	val -= 0x202;
403	}
404	b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
405	}
406
407	/* RSSI Calibration */
408	static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
409	{
410	//TODO
411	}
412
424047e6 MB	413	int b43_phy_initn(struct b43_wldev *dev)
424047e6 MB	414	{
95b66bad MB	415	struct b43_phy *phy = &dev->phy;
	416	u16 tmp;
	417
	418	//TODO: Spectral management
	419	b43_nphy_tables_init(dev);
	420
	421	/* Clear all overrides */
	422	b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
	423	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
	424	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
	425	b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
	426	b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
	427	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
	428	~(B43_NPHY_RFSEQMODE_CAOVER \|
	429	B43_NPHY_RFSEQMODE_TROVER));
	430	b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
	431
	432	tmp = (phy->rev < 2) ? 64 : 59;
	433	b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
	434	~B43_NPHY_BPHY_CTL3_SCALE,
	435	tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
	436
	437	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
	438	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
	439
	440	b43_phy_write(dev, B43_NPHY_TXREALFD, 184);
	441	b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 200);
	442	b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 80);
	443	b43_phy_write(dev, B43_NPHY_C2_BCLIPBKOFF, 511);
424047e6	444
95b66bad MB	445	//TODO MIMO-Config
	446	//TODO Update TX/RX chain
	447
	448	if (phy->rev < 2) {
	449	b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
	450	b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
	451	}
	452	b43_nphy_workarounds(dev);
	453	b43_nphy_reset_cca(dev);
	454
	455	ssb_write32(dev->dev, SSB_TMSLOW,
	456	ssb_read32(dev->dev, SSB_TMSLOW) \| B43_TMSLOW_MACPHYCLKEN);
	457	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
	458	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
	459
	460	b43_phy_read(dev, B43_NPHY_CLASSCTL); /* dummy read */
	461	//TODO read core1/2 clip1 thres regs
	462
	463	if (1 /* FIXME Band is 2.4GHz */)
	464	b43_nphy_bphy_init(dev);
	465	//TODO disable TX power control
	466	//TODO Fix the TX power settings
	467	//TODO Init periodic calibration with reason 3
	468	b43_nphy_rssi_cal(dev, 2);
	469	b43_nphy_rssi_cal(dev, 0);
	470	b43_nphy_rssi_cal(dev, 1);
	471	//TODO get TX gain
	472	//TODO init superswitch
	473	//TODO calibrate LO
	474	//TODO idle TSSI TX pctl
	475	//TODO TX power control power setup
	476	//TODO table writes
	477	//TODO TX power control coefficients
	478	//TODO enable TX power control
	479	//TODO control antenna selection
	480	//TODO init radar detection
	481	//TODO reset channel if changed
	482
	483	b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234	484	return 0;
424047e6	485	}
ef1a628d MB	486
	487	static int b43_nphy_op_allocate(struct b43_wldev *dev)
	488	{
	489	struct b43_phy_n *nphy;
	490
	491	nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
	492	if (!nphy)
	493	return -ENOMEM;
	494	dev->phy.n = nphy;
	495
	496	//TODO init struct b43_phy_n
	497
	498	return 0;
	499	}
	500
	501	static int b43_nphy_op_init(struct b43_wldev *dev)
	502	{
	503	struct b43_phy_n *nphy = dev->phy.n;
	504	int err;
	505
	506	err = b43_phy_initn(dev);
	507	if (err)
	508	return err;
	509	nphy->initialised = 1;
	510
	511	return 0;
	512	}
	513
	514	static void b43_nphy_op_exit(struct b43_wldev *dev)
	515	{
	516	struct b43_phy_n *nphy = dev->phy.n;
	517
	518	if (nphy->initialised) {
	519	//TODO
	520	nphy->initialised = 0;
	521	}
	522	//TODO
	523	kfree(nphy);
	524	dev->phy.n = NULL;
	525	}
	526
	527	static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
	528	{
	529	#if B43_DEBUG
	530	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
	531	/* OFDM registers are onnly available on A/G-PHYs */
	532	b43err(dev->wl, "Invalid OFDM PHY access at "
	533	"0x%04X on N-PHY\n", offset);
	534	dump_stack();
	535	}
	536	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
	537	/* Ext-G registers are only available on G-PHYs */
	538	b43err(dev->wl, "Invalid EXT-G PHY access at "
	539	"0x%04X on N-PHY\n", offset);
	540	dump_stack();
	541	}
	542	#endif /* B43_DEBUG */
	543	}
	544
	545	static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
	546	{
	547	check_phyreg(dev, reg);
	548	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	549	return b43_read16(dev, B43_MMIO_PHY_DATA);
550	}
551
552	static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
553	{
554	check_phyreg(dev, reg);
555	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
556	b43_write16(dev, B43_MMIO_PHY_DATA, value);
557	}
558
559	static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
560	{
561	/* Register 1 is a 32-bit register. */
562	B43_WARN_ON(reg == 1);
563	/* N-PHY needs 0x100 for read access */
564	reg \|= 0x100;
565
566	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
567	return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
568	}
569
570	static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
571	{
572	/* Register 1 is a 32-bit register. */
573	B43_WARN_ON(reg == 1);
574
575	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
576	b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
577	}
578
579	static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
580	enum rfkill_state state)
581	{//TODO
582	}
583
584	static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
585	unsigned int new_channel)
586	{
587	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
588	if ((new_channel < 1) \|\| (new_channel > 14))
589	return -EINVAL;
590	} else {
591	if (new_channel > 200)
592	return -EINVAL;
593	}
594
595	return nphy_channel_switch(dev, new_channel);
596	}
597
598	static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
599	{
600	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
601	return 1;
602	return 36;
603	}
604
605	static void b43_nphy_op_xmitpower(struct b43_wldev *dev)
606	{//TODO
607	}
608
609	const struct b43_phy_operations b43_phyops_n = {
610	.allocate = b43_nphy_op_allocate,
611	.init = b43_nphy_op_init,
612	.exit = b43_nphy_op_exit,
613	.phy_read = b43_nphy_op_read,
614	.phy_write = b43_nphy_op_write,
615	.radio_read = b43_nphy_op_radio_read,
616	.radio_write = b43_nphy_op_radio_write,
617	.software_rfkill = b43_nphy_op_software_rfkill,
618	.switch_channel = b43_nphy_op_switch_channel,
619	.get_default_chan = b43_nphy_op_get_default_chan,
620	.xmitpower = b43_nphy_op_xmitpower,
621	};