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d7520b1d RM |
1 | #ifndef B43_PHY_HT_H_ |
2 | #define B43_PHY_HT_H_ | |
3 | ||
4 | #include "phy_common.h" | |
5 | ||
6 | ||
19240f36 RM |
7 | #define B43_PHY_HT_BBCFG 0x001 /* BB config */ |
8 | #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ | |
9 | #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ | |
bdb2dfb2 | 10 | #define B43_PHY_HT_BANDCTL 0x009 /* Band control */ |
19240f36 | 11 | #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ |
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12 | #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ |
13 | #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ | |
14 | #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ | |
b372afae RM |
15 | #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */ |
16 | #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */ | |
17 | #define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */ | |
18 | #define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */ | |
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19 | #define B43_PHY_HT_IQLOCAL_CMDGCTL 0x0C2 /* I/Q LO cal command G control */ |
20 | #define B43_PHY_HT_SAMP_CMD 0x0C3 /* Sample command */ | |
21 | #define B43_PHY_HT_SAMP_CMD_STOP 0x0002 /* Stop */ | |
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22 | #define B43_PHY_HT_SAMP_LOOP_CNT 0x0C4 /* Sample loop count */ |
23 | #define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */ | |
24 | #define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */ | |
371ec465 | 25 | #define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */ |
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26 | #define B43_PHY_HT_BW1 0x1CE |
27 | #define B43_PHY_HT_BW2 0x1CF | |
28 | #define B43_PHY_HT_BW3 0x1D0 | |
29 | #define B43_PHY_HT_BW4 0x1D1 | |
30 | #define B43_PHY_HT_BW5 0x1D2 | |
31 | #define B43_PHY_HT_BW6 0x1D3 | |
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32 | #define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */ |
33 | #define B43_PHY_HT_TXPCTL_CMD_C1_INIT 0x007F /* Init */ | |
34 | #define B43_PHY_HT_TXPCTL_CMD_C1_COEFF 0x2000 /* Power control coefficients */ | |
35 | #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */ | |
36 | #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */ | |
37 | #define B43_PHY_HT_TXPCTL_CMD_C2 0x222 | |
38 | #define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F | |
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39 | #define B43_PHY_HT_RSSI_C1 0x219 |
40 | #define B43_PHY_HT_RSSI_C2 0x21A | |
41 | #define B43_PHY_HT_RSSI_C3 0x21B | |
d7520b1d | 42 | |
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43 | #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) |
44 | #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) | |
45 | #define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E) | |
46 | ||
c750f795 | 47 | #define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000) |
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48 | #define B43_PHY_HT_RF_SEQ_MODE_CA_OVER 0x0001 /* Core active override */ |
49 | #define B43_PHY_HT_RF_SEQ_MODE_TR_OVER 0x0002 /* Trigger override */ | |
c750f795 RM |
50 | #define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003) |
51 | #define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ | |
52 | #define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ | |
53 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */ | |
54 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */ | |
55 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */ | |
56 | #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ | |
57 | #define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004) | |
58 | /* Values for the status are the same as for the trigger */ | |
59 | ||
e7c62552 RM |
60 | #define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010) |
61 | ||
a51ab258 RM |
62 | #define B43_PHY_HT_RF_CTL_INT_C1 B43_PHY_EXTG(0x04c) |
63 | #define B43_PHY_HT_RF_CTL_INT_C2 B43_PHY_EXTG(0x06c) | |
64 | #define B43_PHY_HT_RF_CTL_INT_C3 B43_PHY_EXTG(0x08c) | |
65 | ||
47606922 RM |
66 | #define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110) |
67 | #define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111) | |
68 | #define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114) | |
69 | #define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115) | |
70 | #define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118) | |
71 | #define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119) | |
a8e82749 | 72 | |
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73 | #define B43_PHY_HT_TXPCTL_CMD_C3 B43_PHY_EXTG(0x164) |
74 | #define B43_PHY_HT_TXPCTL_CMD_C3_INIT 0x007F | |
75 | ||
b372afae RM |
76 | #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) |
77 | ||
d7520b1d | 78 | |
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79 | /* Values for PHY registers used on channel switching */ |
80 | struct b43_phy_ht_channeltab_e_phy { | |
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81 | u16 bw1; |
82 | u16 bw2; | |
83 | u16 bw3; | |
84 | u16 bw4; | |
85 | u16 bw5; | |
86 | u16 bw6; | |
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87 | }; |
88 | ||
89 | ||
d7520b1d | 90 | struct b43_phy_ht { |
a51ab258 | 91 | u16 rf_ctl_int_save[3]; |
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92 | |
93 | bool tx_pwr_ctl; | |
94 | u8 tx_pwr_idx[3]; | |
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95 | |
96 | s32 bb_mult_save[3]; | |
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97 | |
98 | u8 idle_tssi[3]; | |
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99 | }; |
100 | ||
101 | ||
102 | struct b43_phy_operations; | |
103 | extern const struct b43_phy_operations b43_phyops_ht; | |
104 | ||
105 | #endif /* B43_PHY_HT_H_ */ |