[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / b43 / xmit.h

#ifndef B43_XMIT_H_
#define B43_XMIT_H_

#include "main.h"
#include <net/mac80211.h>


#define _b43_declare_plcp_hdr(size) \
	struct b43_plcp_hdr##size {		\
		union {				\
			__le32 data;		\
			__u8 raw[size];		\
		} __packed;	\
	} __packed

/* struct b43_plcp_hdr4 */
_b43_declare_plcp_hdr(4);
/* struct b43_plcp_hdr6 */
_b43_declare_plcp_hdr(6);

#undef _b43_declare_plcp_hdr

/* TX header for v4 firmware */
struct b43_txhdr {
	__le32 mac_ctl;			/* MAC TX control */
	__le16 mac_frame_ctl;		/* Copy of the FrameControl field */
	__le16 tx_fes_time_norm;	/* TX FES Time Normal */
	__le16 phy_ctl;			/* PHY TX control */
	__le16 phy_ctl1;		/* PHY TX control word 1 */
	__le16 phy_ctl1_fb;		/* PHY TX control word 1 for fallback rates */
	__le16 phy_ctl1_rts;		/* PHY TX control word 1 RTS */
	__le16 phy_ctl1_rts_fb;		/* PHY TX control word 1 RTS for fallback rates */
	__u8 phy_rate;			/* PHY rate */
	__u8 phy_rate_rts;		/* PHY rate for RTS/CTS */
	__u8 extra_ft;			/* Extra Frame Types */
	__u8 chan_radio_code;		/* Channel Radio Code */
	__u8 iv[16];			/* Encryption IV */
	__u8 tx_receiver[6];		/* TX Frame Receiver address */
	__le16 tx_fes_time_fb;		/* TX FES Time Fallback */
	struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */
	__le16 rts_dur_fb;		/* RTS fallback duration */
	struct b43_plcp_hdr6 plcp_fb;	/* Fallback PLCP header */
	__le16 dur_fb;			/* Fallback duration */
	__le16 mimo_modelen;		/* MIMO mode length */
	__le16 mimo_ratelen_fb;		/* MIMO fallback rate length */
	__le32 timeout;			/* Timeout */

	union {
		/* The new r410 format. */
		struct {
			__le16 mimo_antenna;		/* MIMO antenna select */
			__le16 preload_size;		/* Preload size */
			PAD_BYTES(2);
			__le16 cookie;			/* TX frame cookie */
			__le16 tx_status;		/* TX status */
			struct b43_plcp_hdr6 rts_plcp;	/* RTS PLCP header */
			__u8 rts_frame[16];		/* The RTS frame (if used) */
			PAD_BYTES(2);
			struct b43_plcp_hdr6 plcp;	/* Main PLCP header */
		} new_format __packed;

		/* The old r351 format. */
		struct {
			PAD_BYTES(2);
			__le16 cookie;			/* TX frame cookie */
			__le16 tx_status;		/* TX status */
			struct b43_plcp_hdr6 rts_plcp;	/* RTS PLCP header */
			__u8 rts_frame[16];		/* The RTS frame (if used) */
			PAD_BYTES(2);
			struct b43_plcp_hdr6 plcp;	/* Main PLCP header */
		} old_format __packed;

	} __packed;
} __packed;

struct b43_tx_legacy_rate_phy_ctl_entry {
	u8 bitrate;
	u16 coding_rate;
	u16 modulation;
};

/* MAC TX control */
#define B43_TXH_MAC_USEFBR		0x10000000 /* Use fallback rate for this AMPDU */
#define B43_TXH_MAC_KEYIDX		0x0FF00000 /* Security key index */
#define B43_TXH_MAC_KEYIDX_SHIFT	20
#define B43_TXH_MAC_KEYALG		0x00070000 /* Security key algorithm */
#define B43_TXH_MAC_KEYALG_SHIFT	16
#define B43_TXH_MAC_AMIC		0x00008000 /* AMIC */
#define B43_TXH_MAC_RIFS		0x00004000 /* Use RIFS */
#define B43_TXH_MAC_LIFETIME		0x00002000 /* Lifetime */
#define B43_TXH_MAC_FRAMEBURST		0x00001000 /* Frameburst */
#define B43_TXH_MAC_SENDCTS		0x00000800 /* Send CTS-to-self */
#define B43_TXH_MAC_AMPDU		0x00000600 /* AMPDU status */
#define  B43_TXH_MAC_AMPDU_MPDU		0x00000000 /* Regular MPDU, not an AMPDU */
#define  B43_TXH_MAC_AMPDU_FIRST	0x00000200 /* First MPDU or AMPDU */
#define  B43_TXH_MAC_AMPDU_INTER	0x00000400 /* Intermediate MPDU or AMPDU */
#define  B43_TXH_MAC_AMPDU_LAST		0x00000600 /* Last (or only) MPDU of AMPDU */
#define B43_TXH_MAC_40MHZ		0x00000100 /* Use 40 MHz bandwidth */
#define B43_TXH_MAC_5GHZ		0x00000080 /* 5GHz band */
#define B43_TXH_MAC_DFCS		0x00000040 /* DFCS */
#define B43_TXH_MAC_IGNPMQ		0x00000020 /* Ignore PMQ */
#define B43_TXH_MAC_HWSEQ		0x00000010 /* Use Hardware Sequence Number */
#define B43_TXH_MAC_STMSDU		0x00000008 /* Start MSDU */
#define B43_TXH_MAC_SENDRTS		0x00000004 /* Send RTS */
#define B43_TXH_MAC_LONGFRAME		0x00000002 /* Long frame */
#define B43_TXH_MAC_ACK			0x00000001 /* Immediate ACK */

/* Extra Frame Types */
#define B43_TXH_EFT_FB			0x03 /* Data frame fallback encoding */
#define  B43_TXH_EFT_FB_CCK		0x00 /* CCK */
#define  B43_TXH_EFT_FB_OFDM		0x01 /* OFDM */
#define  B43_TXH_EFT_FB_EWC		0x02 /* EWC */
#define  B43_TXH_EFT_FB_N		0x03 /* N */
#define B43_TXH_EFT_RTS			0x0C /* RTS/CTS encoding */
#define  B43_TXH_EFT_RTS_CCK		0x00 /* CCK */
#define  B43_TXH_EFT_RTS_OFDM		0x04 /* OFDM */
#define  B43_TXH_EFT_RTS_EWC		0x08 /* EWC */
#define  B43_TXH_EFT_RTS_N		0x0C /* N */
#define B43_TXH_EFT_RTSFB		0x30 /* RTS/CTS fallback encoding */
#define  B43_TXH_EFT_RTSFB_CCK		0x00 /* CCK */
#define  B43_TXH_EFT_RTSFB_OFDM		0x10 /* OFDM */
#define  B43_TXH_EFT_RTSFB_EWC		0x20 /* EWC */
#define  B43_TXH_EFT_RTSFB_N		0x30 /* N */

/* PHY TX control word */
#define B43_TXH_PHY_ENC			0x0003 /* Data frame encoding */
#define  B43_TXH_PHY_ENC_CCK		0x0000 /* CCK */
#define  B43_TXH_PHY_ENC_OFDM		0x0001 /* OFDM */
#define  B43_TXH_PHY_ENC_EWC		0x0002 /* EWC */
#define  B43_TXH_PHY_ENC_N		0x0003 /* N */
#define B43_TXH_PHY_SHORTPRMBL		0x0010 /* Use short preamble */
#define B43_TXH_PHY_ANT			0x03C0 /* Antenna selection */
#define  B43_TXH_PHY_ANT0		0x0000 /* Use antenna 0 */
#define  B43_TXH_PHY_ANT1		0x0040 /* Use antenna 1 */
#define  B43_TXH_PHY_ANT01AUTO		0x00C0 /* Use antenna 0/1 auto */
#define  B43_TXH_PHY_ANT2		0x0100 /* Use antenna 2 */
#define  B43_TXH_PHY_ANT3		0x0200 /* Use antenna 3 */
#define B43_TXH_PHY_TXPWR		0xFC00 /* TX power */
#define B43_TXH_PHY_TXPWR_SHIFT		10

/* PHY TX control word 1 */
#define B43_TXH_PHY1_BW			0x0007 /* Bandwidth */
#define  B43_TXH_PHY1_BW_10		0x0000 /* 10 MHz */
#define  B43_TXH_PHY1_BW_10U		0x0001 /* 10 MHz upper */
#define  B43_TXH_PHY1_BW_20		0x0002 /* 20 MHz */
#define  B43_TXH_PHY1_BW_20U		0x0003 /* 20 MHz upper */
#define  B43_TXH_PHY1_BW_40		0x0004 /* 40 MHz */
#define  B43_TXH_PHY1_BW_40DUP		0x0005 /* 50 MHz duplicate */
#define B43_TXH_PHY1_MODE		0x0038 /* Mode */
#define  B43_TXH_PHY1_MODE_SISO		0x0000 /* SISO */
#define  B43_TXH_PHY1_MODE_CDD		0x0008 /* CDD */
#define  B43_TXH_PHY1_MODE_STBC		0x0010 /* STBC */
#define  B43_TXH_PHY1_MODE_SDM		0x0018 /* SDM */
#define B43_TXH_PHY1_CRATE		0x0700 /* Coding rate */
#define  B43_TXH_PHY1_CRATE_1_2		0x0000 /* 1/2 */
#define  B43_TXH_PHY1_CRATE_2_3		0x0100 /* 2/3 */
#define  B43_TXH_PHY1_CRATE_3_4		0x0200 /* 3/4 */
#define  B43_TXH_PHY1_CRATE_4_5		0x0300 /* 4/5 */
#define  B43_TXH_PHY1_CRATE_5_6		0x0400 /* 5/6 */
#define  B43_TXH_PHY1_CRATE_7_8		0x0600 /* 7/8 */
#define B43_TXH_PHY1_MODUL		0x3800 /* Modulation scheme */
#define  B43_TXH_PHY1_MODUL_BPSK	0x0000 /* BPSK */
#define  B43_TXH_PHY1_MODUL_QPSK	0x0800 /* QPSK */
#define  B43_TXH_PHY1_MODUL_QAM16	0x1000 /* QAM16 */
#define  B43_TXH_PHY1_MODUL_QAM64	0x1800 /* QAM64 */
#define  B43_TXH_PHY1_MODUL_QAM256	0x2000 /* QAM256 */


/* r351 firmware compatibility stuff. */
static inline
bool b43_is_old_txhdr_format(struct b43_wldev *dev)
{
	return (dev->fw.rev <= 351);
}

static inline
size_t b43_txhdr_size(struct b43_wldev *dev)
{
	if (b43_is_old_txhdr_format(dev))
		return 100 + sizeof(struct b43_plcp_hdr6);
	return 104 + sizeof(struct b43_plcp_hdr6);
}


int b43_generate_txhdr(struct b43_wldev *dev,
		       u8 * txhdr,
		       struct sk_buff *skb_frag,
		       struct ieee80211_tx_info *txctl, u16 cookie);

/* Transmit Status */
struct b43_txstatus {
	u16 cookie;		/* The cookie from the txhdr */
	u16 seq;		/* Sequence number */
	u8 phy_stat;		/* PHY TX status */
	u8 frame_count;		/* Frame transmit count */
	u8 rts_count;		/* RTS transmit count */
	u8 supp_reason;		/* Suppression reason */
	/* flags */
	u8 pm_indicated;	/* PM mode indicated to AP */
	u8 intermediate;	/* Intermediate status notification (not final) */
	u8 for_ampdu;		/* Status is for an AMPDU (afterburner) */
	u8 acked;		/* Wireless ACK received */
};

/* txstatus supp_reason values */
enum {
	B43_TXST_SUPP_NONE,	/* Not suppressed */
	B43_TXST_SUPP_PMQ,	/* Suppressed due to PMQ entry */
	B43_TXST_SUPP_FLUSH,	/* Suppressed due to flush request */
	B43_TXST_SUPP_PREV,	/* Previous fragment failed */
	B43_TXST_SUPP_CHAN,	/* Channel mismatch */
	B43_TXST_SUPP_LIFE,	/* Lifetime expired */
	B43_TXST_SUPP_UNDER,	/* Buffer underflow */
	B43_TXST_SUPP_ABNACK,	/* Afterburner NACK */
};

/* Receive header for v4 firmware. */
struct b43_rxhdr_fw4 {
	__le16 frame_len;	/* Frame length */
	 PAD_BYTES(2);
	__le16 phy_status0;	/* PHY RX Status 0 */
	union {
		/* RSSI for A/B/G-PHYs */
		struct {
			__u8 jssi;	/* PHY RX Status 1: JSSI */
			__u8 sig_qual;	/* PHY RX Status 1: Signal Quality */
		} __packed;

		/* RSSI for N-PHYs */
		struct {
			__s8 power0;	/* PHY RX Status 1: Power 0 */
			__s8 power1;	/* PHY RX Status 1: Power 1 */
		} __packed;
	} __packed;
	__le16 phy_status2;	/* PHY RX Status 2 */
	__le16 phy_status3;	/* PHY RX Status 3 */
	__le32 mac_status;	/* MAC RX status */
	__le16 mac_time;
	__le16 channel;
} __packed;

/* PHY RX Status 0 */
#define B43_RX_PHYST0_GAINCTL		0x4000 /* Gain Control */
#define B43_RX_PHYST0_PLCPHCF		0x0200
#define B43_RX_PHYST0_PLCPFV		0x0100
#define B43_RX_PHYST0_SHORTPRMBL	0x0080 /* Received with Short Preamble */
#define B43_RX_PHYST0_LCRS		0x0040
#define B43_RX_PHYST0_ANT		0x0020 /* Antenna */
#define B43_RX_PHYST0_UNSRATE		0x0010
#define B43_RX_PHYST0_CLIP		0x000C
#define B43_RX_PHYST0_CLIP_SHIFT	2
#define B43_RX_PHYST0_FTYPE		0x0003 /* Frame type */
#define  B43_RX_PHYST0_CCK		0x0000 /* Frame type: CCK */
#define  B43_RX_PHYST0_OFDM		0x0001 /* Frame type: OFDM */
#define  B43_RX_PHYST0_PRE_N		0x0002 /* Pre-standard N-PHY frame */
#define  B43_RX_PHYST0_STD_N		0x0003 /* Standard N-PHY frame */

/* PHY RX Status 2 */
#define B43_RX_PHYST2_LNAG		0xC000 /* LNA Gain */
#define B43_RX_PHYST2_LNAG_SHIFT	14
#define B43_RX_PHYST2_PNAG		0x3C00 /* PNA Gain */
#define B43_RX_PHYST2_PNAG_SHIFT	10
#define B43_RX_PHYST2_FOFF		0x03FF /* F offset */

/* PHY RX Status 3 */
#define B43_RX_PHYST3_DIGG		0x1800 /* DIG Gain */
#define B43_RX_PHYST3_DIGG_SHIFT	11
#define B43_RX_PHYST3_TRSTATE		0x0400 /* TR state */

/* MAC RX Status */
#define B43_RX_MAC_RXST_VALID		0x01000000 /* PHY RXST valid */
#define B43_RX_MAC_TKIP_MICERR		0x00100000 /* TKIP MIC error */
#define B43_RX_MAC_TKIP_MICATT		0x00080000 /* TKIP MIC attempted */
#define B43_RX_MAC_AGGTYPE		0x00060000 /* Aggregation type */
#define B43_RX_MAC_AGGTYPE_SHIFT	17
#define B43_RX_MAC_AMSDU		0x00010000 /* A-MSDU mask */
#define B43_RX_MAC_BEACONSENT		0x00008000 /* Beacon sent flag */
#define B43_RX_MAC_KEYIDX		0x000007E0 /* Key index */
#define B43_RX_MAC_KEYIDX_SHIFT		5
#define B43_RX_MAC_DECERR		0x00000010 /* Decrypt error */
#define B43_RX_MAC_DEC			0x00000008 /* Decryption attempted */
#define B43_RX_MAC_PADDING		0x00000004 /* Pad bytes present */
#define B43_RX_MAC_RESP			0x00000002 /* Response frame transmitted */
#define B43_RX_MAC_FCSERR		0x00000001 /* FCS error */

/* RX channel */
#define B43_RX_CHAN_40MHZ		0x1000 /* 40 Mhz channel width */
#define B43_RX_CHAN_5GHZ		0x0800 /* 5 Ghz band */
#define B43_RX_CHAN_ID			0x07F8 /* Channel ID */
#define B43_RX_CHAN_ID_SHIFT		3
#define B43_RX_CHAN_PHYTYPE		0x0007 /* PHY type */


u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);

void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
			   const u16 octets, const u8 bitrate);

void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);

void b43_handle_txstatus(struct b43_wldev *dev,
			 const struct b43_txstatus *status);
bool b43_fill_txstatus_report(struct b43_wldev *dev,
			      struct ieee80211_tx_info *report,
			      const struct b43_txstatus *status);

void b43_tx_suspend(struct b43_wldev *dev);
void b43_tx_resume(struct b43_wldev *dev);


/* Helper functions for converting the key-table index from "firmware-format"
 * to "raw-format" and back. The firmware API changed for this at some revision.
 * We need to account for that here. */
static inline int b43_new_kidx_api(struct b43_wldev *dev)
{
	/* FIXME: Not sure the change was at rev 351 */
	return (dev->fw.rev >= 351);
}
static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
{
	u8 firmware_kidx;
	if (b43_new_kidx_api(dev)) {
		firmware_kidx = raw_kidx;
	} else {
		if (raw_kidx >= 4)	/* Is per STA key? */
			firmware_kidx = raw_kidx - 4;
		else
			firmware_kidx = raw_kidx;	/* TX default key */
	}
	return firmware_kidx;
}
static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
{
	u8 raw_kidx;
	if (b43_new_kidx_api(dev))
		raw_kidx = firmware_kidx;
	else
		raw_kidx = firmware_kidx + 4;	/* RX default keys or per STA keys */
	return raw_kidx;
}

/* struct b43_private_tx_info - TX info private to b43.
 * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data
 *
 * @bouncebuffer: DMA Bouncebuffer (if used)
 */
struct b43_private_tx_info {
	void *bouncebuffer;
};

static inline struct b43_private_tx_info *
b43_get_priv_tx_info(struct ieee80211_tx_info *info)
{
	BUILD_BUG_ON(sizeof(struct b43_private_tx_info) >
		     sizeof(info->rate_driver_data));
	return (struct b43_private_tx_info *)info->rate_driver_data;
}

#endif /* B43_XMIT_H_ */
Commit	Line	Data
e4d6b795 MB	1	#ifndef B43_XMIT_H_
	2	#define B43_XMIT_H_
	3
	4	#include "main.h"
f54a5202 MB	5	#include <net/mac80211.h>
f54a5202 MB	6
e4d6b795 MB	7
	8	#define _b43_declare_plcp_hdr(size) \
	9	struct b43_plcp_hdr##size { \
	10	union { \
	11	__le32 data; \
	12	__u8 raw[size]; \
ba2d3587 ED	13	} __packed; \
ba2d3587 ED	14	} __packed
e4d6b795 MB	15
	16	/* struct b43_plcp_hdr4 */
	17	_b43_declare_plcp_hdr(4);
	18	/* struct b43_plcp_hdr6 */
	19	_b43_declare_plcp_hdr(6);
	20
	21	#undef _b43_declare_plcp_hdr
	22
	23	/* TX header for v4 firmware */
eb189d8b MB	24	struct b43_txhdr {
	25	__le32 mac_ctl; /* MAC TX control */
	26	__le16 mac_frame_ctl; /* Copy of the FrameControl field */
e4d6b795	27	__le16 tx_fes_time_norm; /* TX FES Time Normal */
eb189d8b MB	28	__le16 phy_ctl; /* PHY TX control */
	29	__le16 phy_ctl1; /* PHY TX control word 1 */
	30	__le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */
	31	__le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */
	32	__le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */
	33	__u8 phy_rate; /* PHY rate */
	34	__u8 phy_rate_rts; /* PHY rate for RTS/CTS */
	35	__u8 extra_ft; /* Extra Frame Types */
	36	__u8 chan_radio_code; /* Channel Radio Code */
	37	__u8 iv[16]; /* Encryption IV */
	38	__u8 tx_receiver[6]; /* TX Frame Receiver address */
	39	__le16 tx_fes_time_fb; /* TX FES Time Fallback */
	40	struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */
	41	__le16 rts_dur_fb; /* RTS fallback duration */
	42	struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */
	43	__le16 dur_fb; /* Fallback duration */
	44	__le16 mimo_modelen; /* MIMO mode length */
	45	__le16 mimo_ratelen_fb; /* MIMO fallback rate length */
	46	__le32 timeout; /* Timeout */
	47
	48	union {
	49	/* The new r410 format. */
	50	struct {
	51	__le16 mimo_antenna; /* MIMO antenna select */
	52	__le16 preload_size; /* Preload size */
	53	PAD_BYTES(2);
	54	__le16 cookie; /* TX frame cookie */
	55	__le16 tx_status; /* TX status */
	56	struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
	57	__u8 rts_frame[16]; /* The RTS frame (if used) */
	58	PAD_BYTES(2);
	59	struct b43_plcp_hdr6 plcp; /* Main PLCP header */
ba2d3587	60	} new_format __packed;
eb189d8b MB	61
	62	/* The old r351 format. */
	63	struct {
	64	PAD_BYTES(2);
	65	__le16 cookie; /* TX frame cookie */
	66	__le16 tx_status; /* TX status */
	67	struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
	68	__u8 rts_frame[16]; /* The RTS frame (if used) */
	69	PAD_BYTES(2);
	70	struct b43_plcp_hdr6 plcp; /* Main PLCP header */
ba2d3587	71	} old_format __packed;
eb189d8b	72
ba2d3587 ED	73	} __packed;
ba2d3587 ED	74	} __packed;
e4d6b795	75
3311abbb RM	76	struct b43_tx_legacy_rate_phy_ctl_entry {
	77	u8 bitrate;
	78	u16 coding_rate;
	79	u16 modulation;
	80	};
	81
e4d6b795	82	/* MAC TX control */
eb189d8b MB	83	#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
	84	#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
	85	#define B43_TXH_MAC_KEYIDX_SHIFT 20
	86	#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
	87	#define B43_TXH_MAC_KEYALG_SHIFT 16
	88	#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
	89	#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
	90	#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
	91	#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */
	92	#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */
	93	#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */
	94	#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */
	95	#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */
	96	#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */
	97	#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */
	98	#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
	99	#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */
	100	#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */
	101	#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */
	102	#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
	103	#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */
	104	#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */
	105	#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */
	106	#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */
e4d6b795 MB	107
e4d6b795 MB	108	/* Extra Frame Types */
eb189d8b MB	109	#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */
	110	#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */
	111	#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */
	112	#define B43_TXH_EFT_FB_EWC 0x02 /* EWC */
	113	#define B43_TXH_EFT_FB_N 0x03 /* N */
	114	#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */
	115	#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */
	116	#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */
	117	#define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */
	118	#define B43_TXH_EFT_RTS_N 0x0C /* N */
	119	#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */
	120	#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */
	121	#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */
	122	#define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */
	123	#define B43_TXH_EFT_RTSFB_N 0x30 /* N */
e4d6b795 MB	124
e4d6b795 MB	125	/* PHY TX control word */
eb189d8b MB	126	#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */
	127	#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */
	128	#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */
	129	#define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */
	130	#define B43_TXH_PHY_ENC_N 0x0003 /* N */
	131	#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
	132	#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */
	133	#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */
	134	#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */
	135	#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */
	136	#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */
	137	#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */
	138	#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */
	139	#define B43_TXH_PHY_TXPWR_SHIFT 10
	140
	141	/* PHY TX control word 1 */
	142	#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */
	143	#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
	144	#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
	145	#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
	146	#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
	147	#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
	148	#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */
	149	#define B43_TXH_PHY1_MODE 0x0038 /* Mode */
	150	#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
	151	#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
	152	#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
	153	#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
	154	#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */
	155	#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
	156	#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
	157	#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
	158	#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
	159	#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
	160	#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
	161	#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
	162	#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
	163	#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
	164	#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
	165	#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
	166	#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
	167
	168
	169	/* r351 firmware compatibility stuff. */
	170	static inline
	171	bool b43_is_old_txhdr_format(struct b43_wldev *dev)
	172	{
	173	return (dev->fw.rev <= 351);
	174	}
	175
	176	static inline
	177	size_t b43_txhdr_size(struct b43_wldev *dev)
	178	{
	179	if (b43_is_old_txhdr_format(dev))
	180	return 100 + sizeof(struct b43_plcp_hdr6);
	181	return 104 + sizeof(struct b43_plcp_hdr6);
	182	}
	183
e4d6b795	184
09552ccd MB	185	int b43_generate_txhdr(struct b43_wldev *dev,
09552ccd MB	186	u8 * txhdr,
035d0243	187	struct sk_buff *skb_frag,
e6a9854b	188	struct ieee80211_tx_info *txctl, u16 cookie);
e4d6b795 MB	189
	190	/* Transmit Status */
	191	struct b43_txstatus {
	192	u16 cookie; /* The cookie from the txhdr */
	193	u16 seq; /* Sequence number */
	194	u8 phy_stat; /* PHY TX status */
	195	u8 frame_count; /* Frame transmit count */
	196	u8 rts_count; /* RTS transmit count */
	197	u8 supp_reason; /* Suppression reason */
	198	/* flags */
	199	u8 pm_indicated; /* PM mode indicated to AP */
	200	u8 intermediate; /* Intermediate status notification (not final) */
	201	u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
	202	u8 acked; /* Wireless ACK received */
	203	};
	204
	205	/* txstatus supp_reason values */
	206	enum {
	207	B43_TXST_SUPP_NONE, /* Not suppressed */
	208	B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
	209	B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
	210	B43_TXST_SUPP_PREV, /* Previous fragment failed */
	211	B43_TXST_SUPP_CHAN, /* Channel mismatch */
	212	B43_TXST_SUPP_LIFE, /* Lifetime expired */
	213	B43_TXST_SUPP_UNDER, /* Buffer underflow */
	214	B43_TXST_SUPP_ABNACK, /* Afterburner NACK */
	215	};
	216
e4d6b795 MB	217	/* Receive header for v4 firmware. */
	218	struct b43_rxhdr_fw4 {
	219	__le16 frame_len; /* Frame length */
	220	PAD_BYTES(2);
	221	__le16 phy_status0; /* PHY RX Status 0 */
7b584163 MB	222	union {
	223	/* RSSI for A/B/G-PHYs */
	224	struct {
	225	__u8 jssi; /* PHY RX Status 1: JSSI */
	226	__u8 sig_qual; /* PHY RX Status 1: Signal Quality */
ba2d3587	227	} __packed;
7b584163 MB	228
	229	/* RSSI for N-PHYs */
	230	struct {
	231	__s8 power0; /* PHY RX Status 1: Power 0 */
	232	__s8 power1; /* PHY RX Status 1: Power 1 */
ba2d3587 ED	233	} __packed;
ba2d3587 ED	234	} __packed;
e4d6b795 MB	235	__le16 phy_status2; /* PHY RX Status 2 */
	236	__le16 phy_status3; /* PHY RX Status 3 */
	237	__le32 mac_status; /* MAC RX status */
	238	__le16 mac_time;
	239	__le16 channel;
ba2d3587	240	} __packed;
e4d6b795 MB	241
e4d6b795 MB	242	/* PHY RX Status 0 */
d987160b MB	243	#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
	244	#define B43_RX_PHYST0_PLCPHCF 0x0200
	245	#define B43_RX_PHYST0_PLCPFV 0x0100
	246	#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
e4d6b795	247	#define B43_RX_PHYST0_LCRS 0x0040
d987160b MB	248	#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */
d987160b MB	249	#define B43_RX_PHYST0_UNSRATE 0x0010
e4d6b795 MB	250	#define B43_RX_PHYST0_CLIP 0x000C
e4d6b795 MB	251	#define B43_RX_PHYST0_CLIP_SHIFT 2
d987160b MB	252	#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */
	253	#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
	254	#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
	255	#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
	256	#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
e4d6b795 MB	257
e4d6b795 MB	258	/* PHY RX Status 2 */
d987160b	259	#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
e4d6b795	260	#define B43_RX_PHYST2_LNAG_SHIFT 14
d987160b	261	#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
e4d6b795	262	#define B43_RX_PHYST2_PNAG_SHIFT 10
d987160b	263	#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */
e4d6b795 MB	264
e4d6b795 MB	265	/* PHY RX Status 3 */
d987160b	266	#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
e4d6b795	267	#define B43_RX_PHYST3_DIGG_SHIFT 11
d987160b	268	#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */
e4d6b795 MB	269
e4d6b795 MB	270	/* MAC RX Status */
d987160b MB	271	#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */
	272	#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */
	273	#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */
	274	#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */
	275	#define B43_RX_MAC_AGGTYPE_SHIFT 17
	276	#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */
	277	#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */
	278	#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */
	279	#define B43_RX_MAC_KEYIDX_SHIFT 5
	280	#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */
	281	#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */
	282	#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
	283	#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
	284	#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */
e4d6b795 MB	285
e4d6b795 MB	286	/* RX channel */
d987160b MB	287	#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */
	288	#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */
	289	#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */
	290	#define B43_RX_CHAN_ID_SHIFT 3
	291	#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */
	292
e4d6b795 MB	293
	294	u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
	295	u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
	296
	297	void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
	298	const u16 octets, const u8 bitrate);
	299
	300	void b43_rx(struct b43_wldev dev, struct sk_buff skb, const void *_rxhdr);
	301
	302	void b43_handle_txstatus(struct b43_wldev *dev,
	303	const struct b43_txstatus *status);
e6a9854b JB	304	bool b43_fill_txstatus_report(struct b43_wldev *dev,
e6a9854b JB	305	struct ieee80211_tx_info *report,
5100d5ac	306	const struct b43_txstatus *status);
e4d6b795 MB	307
	308	void b43_tx_suspend(struct b43_wldev *dev);
	309	void b43_tx_resume(struct b43_wldev *dev);
	310
e4d6b795 MB	311
	312	/* Helper functions for converting the key-table index from "firmware-format"
	313	* to "raw-format" and back. The firmware API changed for this at some revision.
	314	* We need to account for that here. */
	315	static inline int b43_new_kidx_api(struct b43_wldev *dev)
	316	{
	317	/* FIXME: Not sure the change was at rev 351 */
	318	return (dev->fw.rev >= 351);
	319	}
	320	static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
	321	{
	322	u8 firmware_kidx;
	323	if (b43_new_kidx_api(dev)) {
	324	firmware_kidx = raw_kidx;
	325	} else {
	326	if (raw_kidx >= 4) /* Is per STA key? */
	327	firmware_kidx = raw_kidx - 4;
	328	else
	329	firmware_kidx = raw_kidx; /* TX default key */
	330	}
	331	return firmware_kidx;
	332	}
	333	static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
	334	{
	335	u8 raw_kidx;
	336	if (b43_new_kidx_api(dev))
	337	raw_kidx = firmware_kidx;
	338	else
	339	raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */
	340	return raw_kidx;
	341	}
	342
f54a5202 MB	343	/* struct b43_private_tx_info - TX info private to b43.
	344	* The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data
	345	*
	346	* @bouncebuffer: DMA Bouncebuffer (if used)
	347	*/
	348	struct b43_private_tx_info {
	349	void *bouncebuffer;
	350	};
	351
	352	static inline struct b43_private_tx_info *
	353	b43_get_priv_tx_info(struct ieee80211_tx_info *info)
	354	{
	355	BUILD_BUG_ON(sizeof(struct b43_private_tx_info) >
	356	sizeof(info->rate_driver_data));
	357	return (struct b43_private_tx_info *)info->rate_driver_data;
	358	}
	359
e4d6b795	360	#endif /* B43_XMIT_H_ */