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[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / b43legacy / main.c
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75388acd
LF		 1/*
2 *
3 * Broadcom B43legacy wireless driver
4 *
5 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6fff1c64 6 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 * Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
75388acd
LF		 8 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11 *
12 * Some parts of the code in this file are derived from the ipw2200
13 * driver Copyright(c) 2003 - 2004 Intel Corporation.
14
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING. If not, write to
27 * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28 * Boston, MA 02110-1301, USA.
29 *
30 */
31
32#include <linux/delay.h>
33#include <linux/init.h>
34#include <linux/moduleparam.h>
35#include <linux/if_arp.h>
36#include <linux/etherdevice.h>
75388acd
LF		 37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
d43c36dc 40#include <linux/sched.h>
75388acd
LF		 41#include <linux/skbuff.h>
42#include <linux/dma-mapping.h>
5a0e3ad6 43#include <linux/slab.h>
75388acd
LF		 44#include <net/dst.h>
45#include <asm/unaligned.h>
46
47#include "b43legacy.h"
48#include "main.h"
49#include "debugfs.h"
50#include "phy.h"
51#include "dma.h"
52#include "pio.h"
53#include "sysfs.h"
54#include "xmit.h"
55#include "radio.h"
56
57
58MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
59MODULE_AUTHOR("Martin Langer");
60MODULE_AUTHOR("Stefano Brivio");
61MODULE_AUTHOR("Michael Buesch");
62MODULE_LICENSE("GPL");
63
1a1c360d 64MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
c2f4f527
TG		 65MODULE_FIRMWARE("b43legacy/ucode2.fw");
66MODULE_FIRMWARE("b43legacy/ucode4.fw");
1a1c360d 67
75388acd
LF		 68#if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
69static int modparam_pio;
70module_param_named(pio, modparam_pio, int, 0444);
71MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
72#elif defined(CONFIG_B43LEGACY_DMA)
73# define modparam_pio 0
74#elif defined(CONFIG_B43LEGACY_PIO)
75# define modparam_pio 1
76#endif
77
78static int modparam_bad_frames_preempt;
79module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
81 " Preemption");
82
75388acd
LF		 83static char modparam_fwpostfix[16];
84module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
85MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
86
75388acd
LF		 87/* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
88static const struct ssb_device_id b43legacy_ssb_tbl[] = {
89 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
90 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
91 SSB_DEVTABLE_END
92};
93MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
94
95
96/* Channel and ratetables are shared for all devices.
97 * They can't be const, because ieee80211 puts some precalculated
98 * data in there. This data is the same for all devices, so we don't
99 * get concurrency issues */
100#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 101 { \
102 .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
103 .hw_value = (_rateid), \
104 .flags = (_flags), \
75388acd 105 }
8318d78a
JB		 106/*
107 * NOTE: When changing this, sync with xmit.c's
108 * b43legacy_plcp_get_bitrate_idx_* functions!
109 */
75388acd 110static struct ieee80211_rate __b43legacy_ratetable[] = {
8318d78a
JB		 111 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
112 RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
113 RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
114 RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
115 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
116 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
117 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
118 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
119 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
120 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
121 RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
122 RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
75388acd 123};
75388acd
LF		 124#define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
125#define b43legacy_b_ratetable_size 4
126#define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
127#define b43legacy_g_ratetable_size 12
128
129#define CHANTAB_ENT(_chanid, _freq) \
130 { \
8318d78a
JB		 131 .center_freq = (_freq), \
132 .hw_value = (_chanid), \
75388acd
LF		 133 }
134static struct ieee80211_channel b43legacy_bg_chantable[] = {
135 CHANTAB_ENT(1, 2412),
136 CHANTAB_ENT(2, 2417),
137 CHANTAB_ENT(3, 2422),
138 CHANTAB_ENT(4, 2427),
139 CHANTAB_ENT(5, 2432),
140 CHANTAB_ENT(6, 2437),
141 CHANTAB_ENT(7, 2442),
142 CHANTAB_ENT(8, 2447),
143 CHANTAB_ENT(9, 2452),
144 CHANTAB_ENT(10, 2457),
145 CHANTAB_ENT(11, 2462),
146 CHANTAB_ENT(12, 2467),
147 CHANTAB_ENT(13, 2472),
148 CHANTAB_ENT(14, 2484),
149};
8318d78a
JB		 150
151static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
152 .channels = b43legacy_bg_chantable,
153 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
154 .bitrates = b43legacy_b_ratetable,
155 .n_bitrates = b43legacy_b_ratetable_size,
156};
157
158static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
159 .channels = b43legacy_bg_chantable,
160 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
161 .bitrates = b43legacy_g_ratetable,
162 .n_bitrates = b43legacy_g_ratetable_size,
163};
75388acd
LF		 164
165static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
166static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
167static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
168static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
169
170
171static int b43legacy_ratelimit(struct b43legacy_wl *wl)
172{
173 if (!wl || !wl->current_dev)
174 return 1;
175 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
176 return 1;
177 /* We are up and running.
178 * Ratelimit the messages to avoid DoS over the net. */
179 return net_ratelimit();
180}
181
182void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
183{
0e67d6cb 184 struct va_format vaf;
75388acd
LF		 185 va_list args;
186
187 if (!b43legacy_ratelimit(wl))
188 return;
0e67d6cb 189
75388acd 190 va_start(args, fmt);
0e67d6cb
JP		 191
192 vaf.fmt = fmt;
193 vaf.va = &args;
194
195 printk(KERN_INFO "b43legacy-%s: %pV",
196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
197
75388acd
LF		 198 va_end(args);
199}
200
201void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
202{
0e67d6cb 203 struct va_format vaf;
75388acd
LF		 204 va_list args;
205
206 if (!b43legacy_ratelimit(wl))
207 return;
0e67d6cb 208
75388acd 209 va_start(args, fmt);
0e67d6cb
JP		 210
211 vaf.fmt = fmt;
212 vaf.va = &args;
213
214 printk(KERN_ERR "b43legacy-%s ERROR: %pV",
215 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
216
75388acd
LF		 217 va_end(args);
218}
219
220void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
221{
0e67d6cb 222 struct va_format vaf;
75388acd
LF		 223 va_list args;
224
225 if (!b43legacy_ratelimit(wl))
226 return;
0e67d6cb 227
75388acd 228 va_start(args, fmt);
0e67d6cb
JP		 229
230 vaf.fmt = fmt;
231 vaf.va = &args;
232
233 printk(KERN_WARNING "b43legacy-%s warning: %pV",
234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
235
75388acd
LF		 236 va_end(args);
237}
238
239#if B43legacy_DEBUG
240void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
241{
0e67d6cb 242 struct va_format vaf;
75388acd
LF		 243 va_list args;
244
245 va_start(args, fmt);
0e67d6cb
JP		 246
247 vaf.fmt = fmt;
248 vaf.va = &args;
249
250 printk(KERN_DEBUG "b43legacy-%s debug: %pV",
251 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
252
75388acd
LF		 253 va_end(args);
254}
255#endif /* DEBUG */
256
257static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
258 u32 val)
259{
260 u32 status;
261
262 B43legacy_WARN_ON(offset % 4 != 0);
263
e78c9d28
SB		 264 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
265 if (status & B43legacy_MACCTL_BE)
75388acd
LF		 266 val = swab32(val);
267
268 b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
269 mmiowb();
270 b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
271}
272
273static inline
274void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
275 u16 routing, u16 offset)
276{
277 u32 control;
278
279 /* "offset" is the WORD offset. */
280
281 control = routing;
282 control <<= 16;
283 control |= offset;
284 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
285}
286
287u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
288 u16 routing, u16 offset)
289{
290 u32 ret;
291
292 if (routing == B43legacy_SHM_SHARED) {
293 B43legacy_WARN_ON((offset & 0x0001) != 0);
294 if (offset & 0x0003) {
295 /* Unaligned access */
296 b43legacy_shm_control_word(dev, routing, offset >> 2);
297 ret = b43legacy_read16(dev,
298 B43legacy_MMIO_SHM_DATA_UNALIGNED);
299 ret <<= 16;
300 b43legacy_shm_control_word(dev, routing,
301 (offset >> 2) + 1);
302 ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
303
304 return ret;
305 }
306 offset >>= 2;
307 }
308 b43legacy_shm_control_word(dev, routing, offset);
309 ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
310
311 return ret;
312}
313
314u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
315 u16 routing, u16 offset)
316{
317 u16 ret;
318
319 if (routing == B43legacy_SHM_SHARED) {
320 B43legacy_WARN_ON((offset & 0x0001) != 0);
321 if (offset & 0x0003) {
322 /* Unaligned access */
323 b43legacy_shm_control_word(dev, routing, offset >> 2);
324 ret = b43legacy_read16(dev,
325 B43legacy_MMIO_SHM_DATA_UNALIGNED);
326
327 return ret;
328 }
329 offset >>= 2;
330 }
331 b43legacy_shm_control_word(dev, routing, offset);
332 ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
333
334 return ret;
335}
336
337void b43legacy_shm_write32(struct b43legacy_wldev *dev,
338 u16 routing, u16 offset,
339 u32 value)
340{
341 if (routing == B43legacy_SHM_SHARED) {
342 B43legacy_WARN_ON((offset & 0x0001) != 0);
343 if (offset & 0x0003) {
344 /* Unaligned access */
345 b43legacy_shm_control_word(dev, routing, offset >> 2);
346 mmiowb();
347 b43legacy_write16(dev,
348 B43legacy_MMIO_SHM_DATA_UNALIGNED,
349 (value >> 16) & 0xffff);
350 mmiowb();
351 b43legacy_shm_control_word(dev, routing,
352 (offset >> 2) + 1);
353 mmiowb();
354 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
355 value & 0xffff);
356 return;
357 }
358 offset >>= 2;
359 }
360 b43legacy_shm_control_word(dev, routing, offset);
361 mmiowb();
362 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
363}
364
365void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
366 u16 value)
367{
368 if (routing == B43legacy_SHM_SHARED) {
369 B43legacy_WARN_ON((offset & 0x0001) != 0);
370 if (offset & 0x0003) {
371 /* Unaligned access */
372 b43legacy_shm_control_word(dev, routing, offset >> 2);
373 mmiowb();
374 b43legacy_write16(dev,
375 B43legacy_MMIO_SHM_DATA_UNALIGNED,
376 value);
377 return;
378 }
379 offset >>= 2;
380 }
381 b43legacy_shm_control_word(dev, routing, offset);
382 mmiowb();
383 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
384}
385
386/* Read HostFlags */
387u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
388{
389 u32 ret;
390
391 ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
392 B43legacy_SHM_SH_HOSTFHI);
393 ret <<= 16;
394 ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
395 B43legacy_SHM_SH_HOSTFLO);
396
397 return ret;
398}
399
400/* Write HostFlags */
401void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
402{
403 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
404 B43legacy_SHM_SH_HOSTFLO,
405 (value & 0x0000FFFF));
406 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
407 B43legacy_SHM_SH_HOSTFHI,
408 ((value & 0xFFFF0000) >> 16));
409}
410
411void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
412{
413 /* We need to be careful. As we read the TSF from multiple
414 * registers, we should take care of register overflows.
415 * In theory, the whole tsf read process should be atomic.
416 * We try to be atomic here, by restaring the read process,
417 * if any of the high registers changed (overflew).
418 */
419 if (dev->dev->id.revision >= 3) {
420 u32 low;
421 u32 high;
422 u32 high2;
423
424 do {
425 high = b43legacy_read32(dev,
426 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
427 low = b43legacy_read32(dev,
428 B43legacy_MMIO_REV3PLUS_TSF_LOW);
429 high2 = b43legacy_read32(dev,
430 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
431 } while (unlikely(high != high2));
432
433 *tsf = high;
434 *tsf <<= 32;
435 *tsf |= low;
436 } else {
437 u64 tmp;
438 u16 v0;
439 u16 v1;
440 u16 v2;
441 u16 v3;
442 u16 test1;
443 u16 test2;
444 u16 test3;
445
446 do {
447 v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
448 v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
449 v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
450 v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
451
452 test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
453 test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
454 test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
455 } while (v3 != test3 || v2 != test2 || v1 != test1);
456
457 *tsf = v3;
458 *tsf <<= 48;
459 tmp = v2;
460 tmp <<= 32;
461 *tsf |= tmp;
462 tmp = v1;
463 tmp <<= 16;
464 *tsf |= tmp;
465 *tsf |= v0;
466 }
467}
468
469static void b43legacy_time_lock(struct b43legacy_wldev *dev)
470{
471 u32 status;
472
e78c9d28
SB		 473 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
474 status |= B43legacy_MACCTL_TBTTHOLD;
475 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 476 mmiowb();
477}
478
479static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
480{
481 u32 status;
482
e78c9d28
SB		 483 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
484 status &= ~B43legacy_MACCTL_TBTTHOLD;
485 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 486}
487
488static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
489{
490 /* Be careful with the in-progress timer.
491 * First zero out the low register, so we have a full
492 * register-overflow duration to complete the operation.
493 */
494 if (dev->dev->id.revision >= 3) {
495 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
496 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
497
498 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
499 mmiowb();
500 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
501 hi);
502 mmiowb();
503 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
504 lo);
505 } else {
506 u16 v0 = (tsf & 0x000000000000FFFFULL);
507 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
508 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
509 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
510
511 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
512 mmiowb();
513 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
514 mmiowb();
515 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
516 mmiowb();
517 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
518 mmiowb();
519 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
520 }
521}
522
523void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
524{
525 b43legacy_time_lock(dev);
526 b43legacy_tsf_write_locked(dev, tsf);
527 b43legacy_time_unlock(dev);
528}
529
530static
531void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
532 u16 offset, const u8 *mac)
533{
534 static const u8 zero_addr[ETH_ALEN] = { 0 };
535 u16 data;
536
537 if (!mac)
538 mac = zero_addr;
539
540 offset |= 0x0020;
541 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
542
543 data = mac[0];
544 data |= mac[1] << 8;
545 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
546 data = mac[2];
547 data |= mac[3] << 8;
548 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
549 data = mac[4];
550 data |= mac[5] << 8;
551 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
552}
553
554static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
555{
556 static const u8 zero_addr[ETH_ALEN] = { 0 };
557 const u8 *mac = dev->wl->mac_addr;
558 const u8 *bssid = dev->wl->bssid;
559 u8 mac_bssid[ETH_ALEN * 2];
560 int i;
561 u32 tmp;
562
563 if (!bssid)
564 bssid = zero_addr;
565 if (!mac)
566 mac = zero_addr;
567
568 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
569
570 memcpy(mac_bssid, mac, ETH_ALEN);
571 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
572
573 /* Write our MAC address and BSSID to template ram */
574 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
575 tmp = (u32)(mac_bssid[i + 0]);
576 tmp |= (u32)(mac_bssid[i + 1]) << 8;
577 tmp |= (u32)(mac_bssid[i + 2]) << 16;
578 tmp |= (u32)(mac_bssid[i + 3]) << 24;
579 b43legacy_ram_write(dev, 0x20 + i, tmp);
580 b43legacy_ram_write(dev, 0x78 + i, tmp);
581 b43legacy_ram_write(dev, 0x478 + i, tmp);
582 }
583}
584
4150c572 585static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
75388acd 586{
75388acd 587 b43legacy_write_mac_bssid_templates(dev);
4150c572
JB		 588 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
589 dev->wl->mac_addr);
75388acd
LF		 590}
591
592static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
593 u16 slot_time)
594{
595 /* slot_time is in usec. */
596 if (dev->phy.type != B43legacy_PHYTYPE_G)
597 return;
598 b43legacy_write16(dev, 0x684, 510 + slot_time);
599 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
600 slot_time);
601}
602
603static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
604{
605 b43legacy_set_slot_time(dev, 9);
75388acd
LF		 606}
607
608static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
609{
610 b43legacy_set_slot_time(dev, 20);
75388acd
LF		 611}
612
75388acd
LF		 613/* Synchronize IRQ top- and bottom-half.
614 * IRQs must be masked before calling this.
615 * This must not be called with the irq_lock held.
616 */
617static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
618{
619 synchronize_irq(dev->dev->irq);
620 tasklet_kill(&dev->isr_tasklet);
621}
622
623/* DummyTransmission function, as documented on
624 * http://bcm-specs.sipsolutions.net/DummyTransmission
625 */
626void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
627{
628 struct b43legacy_phy *phy = &dev->phy;
629 unsigned int i;
630 unsigned int max_loop;
631 u16 value;
632 u32 buffer[5] = {
633 0x00000000,
634 0x00D40000,
635 0x00000000,
636 0x01000000,
637 0x00000000,
638 };
639
640 switch (phy->type) {
641 case B43legacy_PHYTYPE_B:
642 case B43legacy_PHYTYPE_G:
643 max_loop = 0xFA;
644 buffer[0] = 0x000B846E;
645 break;
646 default:
647 B43legacy_BUG_ON(1);
648 return;
649 }
650
651 for (i = 0; i < 5; i++)
652 b43legacy_ram_write(dev, i * 4, buffer[i]);
653
654 /* dummy read follows */
e78c9d28 655 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 656
657 b43legacy_write16(dev, 0x0568, 0x0000);
658 b43legacy_write16(dev, 0x07C0, 0x0000);
659 b43legacy_write16(dev, 0x050C, 0x0000);
660 b43legacy_write16(dev, 0x0508, 0x0000);
661 b43legacy_write16(dev, 0x050A, 0x0000);
662 b43legacy_write16(dev, 0x054C, 0x0000);
663 b43legacy_write16(dev, 0x056A, 0x0014);
664 b43legacy_write16(dev, 0x0568, 0x0826);
665 b43legacy_write16(dev, 0x0500, 0x0000);
666 b43legacy_write16(dev, 0x0502, 0x0030);
667
668 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
669 b43legacy_radio_write16(dev, 0x0051, 0x0017);
670 for (i = 0x00; i < max_loop; i++) {
671 value = b43legacy_read16(dev, 0x050E);
672 if (value & 0x0080)
673 break;
674 udelay(10);
675 }
676 for (i = 0x00; i < 0x0A; i++) {
677 value = b43legacy_read16(dev, 0x050E);
678 if (value & 0x0400)
679 break;
680 udelay(10);
681 }
682 for (i = 0x00; i < 0x0A; i++) {
683 value = b43legacy_read16(dev, 0x0690);
684 if (!(value & 0x0100))
685 break;
686 udelay(10);
687 }
688 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
689 b43legacy_radio_write16(dev, 0x0051, 0x0037);
690}
691
692/* Turn the Analog ON/OFF */
693static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
694{
695 b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
696}
697
698void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
699{
700 u32 tmslow;
701 u32 macctl;
702
703 flags |= B43legacy_TMSLOW_PHYCLKEN;
704 flags |= B43legacy_TMSLOW_PHYRESET;
705 ssb_device_enable(dev->dev, flags);
706 msleep(2); /* Wait for the PLL to turn on. */
707
708 /* Now take the PHY out of Reset again */
709 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
710 tmslow |= SSB_TMSLOW_FGC;
711 tmslow &= ~B43legacy_TMSLOW_PHYRESET;
712 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
713 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
714 msleep(1);
715 tmslow &= ~SSB_TMSLOW_FGC;
716 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
717 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
718 msleep(1);
719
720 /* Turn Analog ON */
721 b43legacy_switch_analog(dev, 1);
722
723 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
724 macctl &= ~B43legacy_MACCTL_GMODE;
725 if (flags & B43legacy_TMSLOW_GMODE) {
726 macctl |= B43legacy_MACCTL_GMODE;
727 dev->phy.gmode = 1;
728 } else
729 dev->phy.gmode = 0;
730 macctl |= B43legacy_MACCTL_IHR_ENABLED;
731 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
732}
733
734static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
735{
736 u32 v0;
737 u32 v1;
738 u16 tmp;
739 struct b43legacy_txstatus stat;
740
741 while (1) {
742 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
743 if (!(v0 & 0x00000001))
744 break;
745 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
746
747 stat.cookie = (v0 >> 16);
748 stat.seq = (v1 & 0x0000FFFF);
749 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
750 tmp = (v0 & 0x0000FFFF);
751 stat.frame_count = ((tmp & 0xF000) >> 12);
752 stat.rts_count = ((tmp & 0x0F00) >> 8);
753 stat.supp_reason = ((tmp & 0x001C) >> 2);
754 stat.pm_indicated = !!(tmp & 0x0080);
755 stat.intermediate = !!(tmp & 0x0040);
756 stat.for_ampdu = !!(tmp & 0x0020);
757 stat.acked = !!(tmp & 0x0002);
758
759 b43legacy_handle_txstatus(dev, &stat);
760 }
761}
762
763static void drain_txstatus_queue(struct b43legacy_wldev *dev)
764{
765 u32 dummy;
766
767 if (dev->dev->id.revision < 5)
768 return;
769 /* Read all entries from the microcode TXstatus FIFO
770 * and throw them away.
771 */
772 while (1) {
773 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
774 if (!(dummy & 0x00000001))
775 break;
776 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
777 }
778}
779
780static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
781{
782 u32 val = 0;
783
784 val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
785 val <<= 16;
786 val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
787
788 return val;
789}
790
791static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
792{
793 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
794 (jssi & 0x0000FFFF));
795 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
796 (jssi & 0xFFFF0000) >> 16);
797}
798
799static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
800{
801 b43legacy_jssi_write(dev, 0x7F7F7F7F);
e78c9d28 802 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
eed0fd21
SB		 803 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
804 | B43legacy_MACCMD_BGNOISE);
75388acd
LF		 805 B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
806 dev->phy.channel);
807}
808
809static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
810{
811 /* Top half of Link Quality calculation. */
812
813 if (dev->noisecalc.calculation_running)
814 return;
815 dev->noisecalc.channel_at_start = dev->phy.channel;
816 dev->noisecalc.calculation_running = 1;
817 dev->noisecalc.nr_samples = 0;
818
819 b43legacy_generate_noise_sample(dev);
820}
821
822static void handle_irq_noise(struct b43legacy_wldev *dev)
823{
824 struct b43legacy_phy *phy = &dev->phy;
825 u16 tmp;
826 u8 noise[4];
827 u8 i;
828 u8 j;
829 s32 average;
830
831 /* Bottom half of Link Quality calculation. */
832
833 B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
834 if (dev->noisecalc.channel_at_start != phy->channel)
835 goto drop_calculation;
836 *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
837 if (noise[0] == 0x7F || noise[1] == 0x7F ||
838 noise[2] == 0x7F || noise[3] == 0x7F)
839 goto generate_new;
840
841 /* Get the noise samples. */
842 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
843 i = dev->noisecalc.nr_samples;
ca21614d
HH		 844 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
845 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
846 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
847 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
75388acd
LF		 848 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
849 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
850 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
851 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
852 dev->noisecalc.nr_samples++;
853 if (dev->noisecalc.nr_samples == 8) {
854 /* Calculate the Link Quality by the noise samples. */
855 average = 0;
856 for (i = 0; i < 8; i++) {
857 for (j = 0; j < 4; j++)
858 average += dev->noisecalc.samples[i][j];
859 }
860 average /= (8 * 4);
861 average *= 125;
862 average += 64;
863 average /= 128;
864 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
865 0x40C);
866 tmp = (tmp / 128) & 0x1F;
867 if (tmp >= 8)
868 average += 2;
869 else
870 average -= 25;
871 if (tmp == 8)
872 average -= 72;
873 else
874 average -= 48;
875
876 dev->stats.link_noise = average;
877drop_calculation:
878 dev->noisecalc.calculation_running = 0;
879 return;
880 }
881generate_new:
882 b43legacy_generate_noise_sample(dev);
883}
884
885static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
886{
05c914fe 887 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
75388acd
LF		 888 /* TODO: PS TBTT */
889 } else {
890 if (1/*FIXME: the last PSpoll frame was sent successfully */)
891 b43legacy_power_saving_ctl_bits(dev, -1, -1);
892 }
05c914fe 893 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
eed0fd21 894 dev->dfq_valid = 1;
75388acd
LF		 895}
896
897static void handle_irq_atim_end(struct b43legacy_wldev *dev)
898{
eed0fd21
SB		 899 if (dev->dfq_valid) {
900 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
901 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
902 | B43legacy_MACCMD_DFQ_VALID);
903 dev->dfq_valid = 0;
904 }
75388acd
LF		 905}
906
907static void handle_irq_pmq(struct b43legacy_wldev *dev)
908{
909 u32 tmp;
910
911 /* TODO: AP mode. */
912
913 while (1) {
914 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
915 if (!(tmp & 0x00000008))
916 break;
917 }
918 /* 16bit write is odd, but correct. */
919 b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
920}
921
922static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
923 const u8 *data, u16 size,
924 u16 ram_offset,
925 u16 shm_size_offset, u8 rate)
926{
927 u32 i;
928 u32 tmp;
929 struct b43legacy_plcp_hdr4 plcp;
930
931 plcp.data = 0;
932 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
933 b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
934 ram_offset += sizeof(u32);
935 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
936 * So leave the first two bytes of the next write blank.
937 */
938 tmp = (u32)(data[0]) << 16;
939 tmp |= (u32)(data[1]) << 24;
940 b43legacy_ram_write(dev, ram_offset, tmp);
941 ram_offset += sizeof(u32);
942 for (i = 2; i < size; i += sizeof(u32)) {
943 tmp = (u32)(data[i + 0]);
944 if (i + 1 < size)
945 tmp |= (u32)(data[i + 1]) << 8;
946 if (i + 2 < size)
947 tmp |= (u32)(data[i + 2]) << 16;
948 if (i + 3 < size)
949 tmp |= (u32)(data[i + 3]) << 24;
950 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
951 }
952 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
953 size + sizeof(struct b43legacy_plcp_hdr6));
954}
955
2d1f96dd
LF		 956/* Convert a b43legacy antenna number value to the PHY TX control value. */
957static u16 b43legacy_antenna_to_phyctl(int antenna)
958{
959 switch (antenna) {
960 case B43legacy_ANTENNA0:
961 return B43legacy_TX4_PHY_ANT0;
962 case B43legacy_ANTENNA1:
963 return B43legacy_TX4_PHY_ANT1;
964 }
965 return B43legacy_TX4_PHY_ANTLAST;
966}
967
75388acd
LF		 968static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
969 u16 ram_offset,
2d1f96dd 970 u16 shm_size_offset)
75388acd 971{
75388acd 972
a297170d
SB		 973 unsigned int i, len, variable_len;
974 const struct ieee80211_mgmt *bcn;
975 const u8 *ie;
976 bool tim_found = 0;
2d1f96dd
LF		 977 unsigned int rate;
978 u16 ctl;
979 int antenna;
980 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
a297170d
SB		 981
982 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
983 len = min((size_t)dev->wl->current_beacon->len,
75388acd 984 0x200 - sizeof(struct b43legacy_plcp_hdr6));
2d1f96dd 985 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
a297170d
SB		 986
987 b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
75388acd 988 shm_size_offset, rate);
a297170d 989
2d1f96dd
LF		 990 /* Write the PHY TX control parameters. */
991 antenna = B43legacy_ANTENNA_DEFAULT;
992 antenna = b43legacy_antenna_to_phyctl(antenna);
993 ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
994 B43legacy_SHM_SH_BEACPHYCTL);
995 /* We can't send beacons with short preamble. Would get PHY errors. */
996 ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
997 ctl &= ~B43legacy_TX4_PHY_ANT;
998 ctl &= ~B43legacy_TX4_PHY_ENC;
999 ctl |= antenna;
1000 ctl |= B43legacy_TX4_PHY_ENC_CCK;
1001 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1002 B43legacy_SHM_SH_BEACPHYCTL, ctl);
1003
a297170d
SB		 1004 /* Find the position of the TIM and the DTIM_period value
1005 * and write them to SHM. */
1006 ie = bcn->u.beacon.variable;
1007 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1008 for (i = 0; i < variable_len - 2; ) {
1009 uint8_t ie_id, ie_len;
1010
1011 ie_id = ie[i];
1012 ie_len = ie[i + 1];
1013 if (ie_id == 5) {
1014 u16 tim_position;
1015 u16 dtim_period;
1016 /* This is the TIM Information Element */
1017
1018 /* Check whether the ie_len is in the beacon data range. */
1019 if (variable_len < ie_len + 2 + i)
1020 break;
1021 /* A valid TIM is at least 4 bytes long. */
1022 if (ie_len < 4)
1023 break;
1024 tim_found = 1;
1025
1026 tim_position = sizeof(struct b43legacy_plcp_hdr6);
1027 tim_position += offsetof(struct ieee80211_mgmt,
1028 u.beacon.variable);
1029 tim_position += i;
1030
1031 dtim_period = ie[i + 3];
1032
1033 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1034 B43legacy_SHM_SH_TIMPOS, tim_position);
1035 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1036 B43legacy_SHM_SH_DTIMP, dtim_period);
1037 break;
1038 }
1039 i += ie_len + 2;
1040 }
1041 if (!tim_found) {
1042 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1043 "beacon template packet. AP or IBSS operation "
1044 "may be broken.\n");
7858e07b
LF		 1045 } else
1046 b43legacydbg(dev->wl, "Updated beacon template\n");
75388acd
LF		 1047}
1048
1049static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1050 u16 shm_offset, u16 size,
8318d78a 1051 struct ieee80211_rate *rate)
75388acd
LF		 1052{
1053 struct b43legacy_plcp_hdr4 plcp;
1054 u32 tmp;
1055 __le16 dur;
1056
1057 plcp.data = 0;
2d1f96dd 1058 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
75388acd 1059 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1060 dev->wl->vif,
75388acd 1061 size,
8318d78a 1062 rate);
75388acd
LF		 1063 /* Write PLCP in two parts and timing for packet transfer */
1064 tmp = le32_to_cpu(plcp.data);
1065 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1066 tmp & 0xFFFF);
1067 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1068 tmp >> 16);
1069 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1070 le16_to_cpu(dur));
1071}
1072
1073/* Instead of using custom probe response template, this function
1074 * just patches custom beacon template by:
1075 * 1) Changing packet type
1076 * 2) Patching duration field
1077 * 3) Stripping TIM
1078 */
a297170d
SB		 1079static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1080 u16 *dest_size,
1081 struct ieee80211_rate *rate)
75388acd
LF		 1082{
1083 const u8 *src_data;
1084 u8 *dest_data;
a297170d 1085 u16 src_size, elem_size, src_pos, dest_pos;
75388acd
LF		 1086 __le16 dur;
1087 struct ieee80211_hdr *hdr;
a297170d
SB		 1088 size_t ie_start;
1089
1090 src_size = dev->wl->current_beacon->len;
1091 src_data = (const u8 *)dev->wl->current_beacon->data;
75388acd 1092
a297170d
SB		 1093 /* Get the start offset of the variable IEs in the packet. */
1094 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1095 B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1096 u.beacon.variable));
75388acd 1097
4688be30 1098 if (B43legacy_WARN_ON(src_size < ie_start))
75388acd 1099 return NULL;
75388acd
LF		 1100
1101 dest_data = kmalloc(src_size, GFP_ATOMIC);
1102 if (unlikely(!dest_data))
1103 return NULL;
1104
a297170d
SB		 1105 /* Copy the static data and all Information Elements, except the TIM. */
1106 memcpy(dest_data, src_data, ie_start);
1107 src_pos = ie_start;
1108 dest_pos = ie_start;
1109 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
75388acd 1110 elem_size = src_data[src_pos + 1] + 2;
a297170d
SB		 1111 if (src_data[src_pos] == 5) {
1112 /* This is the TIM. */
1113 continue;
75388acd 1114 }
a297170d
SB		 1115 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1116 dest_pos += elem_size;
75388acd
LF		 1117 }
1118 *dest_size = dest_pos;
1119 hdr = (struct ieee80211_hdr *)dest_data;
1120
1121 /* Set the frame control. */
1122 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1123 IEEE80211_STYPE_PROBE_RESP);
1124 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1125 dev->wl->vif,
75388acd 1126 *dest_size,
8318d78a 1127 rate);
75388acd
LF		 1128 hdr->duration_id = dur;
1129
1130 return dest_data;
1131}
1132
1133static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1134 u16 ram_offset,
8318d78a
JB		 1135 u16 shm_size_offset,
1136 struct ieee80211_rate *rate)
75388acd 1137{
a297170d 1138 const u8 *probe_resp_data;
75388acd
LF		 1139 u16 size;
1140
a297170d 1141 size = dev->wl->current_beacon->len;
75388acd
LF		 1142 probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1143 if (unlikely(!probe_resp_data))
1144 return;
1145
1146 /* Looks like PLCP headers plus packet timings are stored for
1147 * all possible basic rates
1148 */
1149 b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
8318d78a 1150 &b43legacy_b_ratetable[0]);
75388acd 1151 b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
8318d78a 1152 &b43legacy_b_ratetable[1]);
75388acd 1153 b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
8318d78a 1154 &b43legacy_b_ratetable[2]);
75388acd 1155 b43legacy_write_probe_resp_plcp(dev, 0x350, size,
8318d78a 1156 &b43legacy_b_ratetable[3]);
75388acd
LF		 1157
1158 size = min((size_t)size,
1159 0x200 - sizeof(struct b43legacy_plcp_hdr6));
1160 b43legacy_write_template_common(dev, probe_resp_data,
1161 size, ram_offset,
2d1f96dd 1162 shm_size_offset, rate->hw_value);
75388acd
LF		 1163 kfree(probe_resp_data);
1164}
1165
2d1f96dd
LF		 1166static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1167{
1168 struct b43legacy_wl *wl = dev->wl;
1169
1170 if (wl->beacon0_uploaded)
1171 return;
1172 b43legacy_write_beacon_template(dev, 0x68, 0x18);
1173 /* FIXME: Probe resp upload doesn't really belong here,
1174 * but we don't use that feature anyway. */
1175 b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1176 &__b43legacy_ratetable[3]);
1177 wl->beacon0_uploaded = 1;
1178}
1179
1180static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1181{
1182 struct b43legacy_wl *wl = dev->wl;
1183
1184 if (wl->beacon1_uploaded)
1185 return;
1186 b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1187 wl->beacon1_uploaded = 1;
1188}
1189
1190static void handle_irq_beacon(struct b43legacy_wldev *dev)
1191{
1192 struct b43legacy_wl *wl = dev->wl;
1193 u32 cmd, beacon0_valid, beacon1_valid;
1194
1195 if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1196 return;
1197
1198 /* This is the bottom half of the asynchronous beacon update. */
1199
1200 /* Ignore interrupt in the future. */
44710bbc 1201 dev->irq_mask &= ~B43legacy_IRQ_BEACON;
2d1f96dd
LF		 1202
1203 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1204 beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1205 beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1206
1207 /* Schedule interrupt manually, if busy. */
1208 if (beacon0_valid && beacon1_valid) {
1209 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
44710bbc 1210 dev->irq_mask |= B43legacy_IRQ_BEACON;
2d1f96dd
LF		 1211 return;
1212 }
1213
1214 if (unlikely(wl->beacon_templates_virgin)) {
1215 /* We never uploaded a beacon before.
1216 * Upload both templates now, but only mark one valid. */
1217 wl->beacon_templates_virgin = 0;
1218 b43legacy_upload_beacon0(dev);
1219 b43legacy_upload_beacon1(dev);
1220 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1221 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1222 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1223 } else {
1224 if (!beacon0_valid) {
1225 b43legacy_upload_beacon0(dev);
1226 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1227 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1228 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1229 } else if (!beacon1_valid) {
1230 b43legacy_upload_beacon1(dev);
1231 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1232 cmd |= B43legacy_MACCMD_BEACON1_VALID;
1233 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1234 }
1235 }
1236}
1237
7858e07b
LF		 1238static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1239{
1240 struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1241 beacon_update_trigger);
1242 struct b43legacy_wldev *dev;
1243
1244 mutex_lock(&wl->mutex);
1245 dev = wl->current_dev;
1246 if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
7858e07b 1247 spin_lock_irq(&wl->irq_lock);
44710bbc 1248 /* Update beacon right away or defer to IRQ. */
2d1f96dd
LF		 1249 handle_irq_beacon(dev);
1250 /* The handler might have updated the IRQ mask. */
1251 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
44710bbc 1252 dev->irq_mask);
2d1f96dd 1253 mmiowb();
7858e07b
LF		 1254 spin_unlock_irq(&wl->irq_lock);
1255 }
1256 mutex_unlock(&wl->mutex);
1257}
1258
a297170d
SB		 1259/* Asynchronously update the packet templates in template RAM.
1260 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1261static void b43legacy_update_templates(struct b43legacy_wl *wl)
75388acd 1262{
9d139c81 1263 struct sk_buff *beacon;
a297170d
SB		 1264 /* This is the top half of the ansynchronous beacon update. The bottom
1265 * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1266 * sending an invalid beacon. This can happen for example, if the
1267 * firmware transmits a beacon while we are updating it. */
75388acd 1268
9d139c81
JB		 1269 /* We could modify the existing beacon and set the aid bit in the TIM
1270 * field, but that would probably require resizing and moving of data
1271 * within the beacon template. Simply request a new beacon and let
1272 * mac80211 do the hard work. */
1273 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1274 if (unlikely(!beacon))
1275 return;
1276
a297170d
SB		 1277 if (wl->current_beacon)
1278 dev_kfree_skb_any(wl->current_beacon);
1279 wl->current_beacon = beacon;
1280 wl->beacon0_uploaded = 0;
1281 wl->beacon1_uploaded = 0;
42935eca 1282 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
75388acd
LF		 1283}
1284
75388acd
LF		 1285static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1286 u16 beacon_int)
1287{
1288 b43legacy_time_lock(dev);
7858e07b
LF		 1289 if (dev->dev->id.revision >= 3) {
1290 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1291 (beacon_int << 16));
1292 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1293 (beacon_int << 10));
1294 } else {
75388acd
LF		 1295 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1296 b43legacy_write16(dev, 0x610, beacon_int);
1297 }
1298 b43legacy_time_unlock(dev);
7858e07b 1299 b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
75388acd
LF		 1300}
1301
75388acd
LF		 1302static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1303{
1304}
1305
1306/* Interrupt handler bottom-half */
1307static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1308{
1309 u32 reason;
1310 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1311 u32 merged_dma_reason = 0;
1312 int i;
75388acd
LF		 1313 unsigned long flags;
1314
1315 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1316
1317 B43legacy_WARN_ON(b43legacy_status(dev) <
1318 B43legacy_STAT_INITIALIZED);
1319
1320 reason = dev->irq_reason;
1321 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1322 dma_reason[i] = dev->dma_reason[i];
1323 merged_dma_reason |= dma_reason[i];
1324 }
1325
1326 if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1327 b43legacyerr(dev->wl, "MAC transmission error\n");
1328
a293ee99 1329 if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
75388acd 1330 b43legacyerr(dev->wl, "PHY transmission error\n");
a293ee99
SB		 1331 rmb();
1332 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1333 b43legacyerr(dev->wl, "Too many PHY TX errors, "
1334 "restarting the controller\n");
1335 b43legacy_controller_restart(dev, "PHY TX errors");
1336 }
1337 }
75388acd
LF		 1338
1339 if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1340 B43legacy_DMAIRQ_NONFATALMASK))) {
1341 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1342 b43legacyerr(dev->wl, "Fatal DMA error: "
1343 "0x%08X, 0x%08X, 0x%08X, "
1344 "0x%08X, 0x%08X, 0x%08X\n",
1345 dma_reason[0], dma_reason[1],
1346 dma_reason[2], dma_reason[3],
1347 dma_reason[4], dma_reason[5]);
1348 b43legacy_controller_restart(dev, "DMA error");
1349 mmiowb();
1350 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1351 return;
1352 }
1353 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1354 b43legacyerr(dev->wl, "DMA error: "
1355 "0x%08X, 0x%08X, 0x%08X, "
1356 "0x%08X, 0x%08X, 0x%08X\n",
1357 dma_reason[0], dma_reason[1],
1358 dma_reason[2], dma_reason[3],
1359 dma_reason[4], dma_reason[5]);
1360 }
1361
1362 if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1363 handle_irq_ucode_debug(dev);
1364 if (reason & B43legacy_IRQ_TBTT_INDI)
1365 handle_irq_tbtt_indication(dev);
1366 if (reason & B43legacy_IRQ_ATIM_END)
1367 handle_irq_atim_end(dev);
1368 if (reason & B43legacy_IRQ_BEACON)
1369 handle_irq_beacon(dev);
1370 if (reason & B43legacy_IRQ_PMQ)
1371 handle_irq_pmq(dev);
1372 if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1373 ;/*TODO*/
1374 if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1375 handle_irq_noise(dev);
1376
1377 /* Check the DMA reason registers for received data. */
1378 if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1379 if (b43legacy_using_pio(dev))
1380 b43legacy_pio_rx(dev->pio.queue0);
1381 else
1382 b43legacy_dma_rx(dev->dma.rx_ring0);
75388acd
LF		 1383 }
1384 B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1385 B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1386 if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1387 if (b43legacy_using_pio(dev))
1388 b43legacy_pio_rx(dev->pio.queue3);
1389 else
1390 b43legacy_dma_rx(dev->dma.rx_ring3);
75388acd
LF		 1391 }
1392 B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1393 B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1394
ba48f7bb 1395 if (reason & B43legacy_IRQ_TX_OK)
75388acd 1396 handle_irq_transmit_status(dev);
75388acd 1397
44710bbc 1398 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
75388acd
LF		 1399 mmiowb();
1400 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1401}
1402
1403static void pio_irq_workaround(struct b43legacy_wldev *dev,
1404 u16 base, int queueidx)
1405{
1406 u16 rxctl;
1407
1408 rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1409 if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1410 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1411 else
1412 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1413}
1414
1415static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1416{
1417 if (b43legacy_using_pio(dev) &&
1418 (dev->dev->id.revision < 3) &&
1419 (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1420 /* Apply a PIO specific workaround to the dma_reasons */
1421 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1422 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1423 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1424 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1425 }
1426
1427 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1428
1429 b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1430 dev->dma_reason[0]);
1431 b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1432 dev->dma_reason[1]);
1433 b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1434 dev->dma_reason[2]);
1435 b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1436 dev->dma_reason[3]);
1437 b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1438 dev->dma_reason[4]);
1439 b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1440 dev->dma_reason[5]);
1441}
1442
1443/* Interrupt handler top-half */
1444static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1445{
1446 irqreturn_t ret = IRQ_NONE;
1447 struct b43legacy_wldev *dev = dev_id;
1448 u32 reason;
1449
44710bbc 1450 B43legacy_WARN_ON(!dev);
75388acd
LF		 1451
1452 spin_lock(&dev->wl->irq_lock);
1453
44710bbc
SB		 1454 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1455 /* This can only happen on shared IRQ lines. */
75388acd
LF		 1456 goto out;
1457 reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1458 if (reason == 0xffffffff) /* shared IRQ */
1459 goto out;
1460 ret = IRQ_HANDLED;
44710bbc 1461 reason &= dev->irq_mask;
75388acd
LF		 1462 if (!reason)
1463 goto out;
1464
1465 dev->dma_reason[0] = b43legacy_read32(dev,
1466 B43legacy_MMIO_DMA0_REASON)
1467 & 0x0001DC00;
1468 dev->dma_reason[1] = b43legacy_read32(dev,
1469 B43legacy_MMIO_DMA1_REASON)
1470 & 0x0000DC00;
1471 dev->dma_reason[2] = b43legacy_read32(dev,
1472 B43legacy_MMIO_DMA2_REASON)
1473 & 0x0000DC00;
1474 dev->dma_reason[3] = b43legacy_read32(dev,
1475 B43legacy_MMIO_DMA3_REASON)
1476 & 0x0001DC00;
1477 dev->dma_reason[4] = b43legacy_read32(dev,
1478 B43legacy_MMIO_DMA4_REASON)
1479 & 0x0000DC00;
1480 dev->dma_reason[5] = b43legacy_read32(dev,
1481 B43legacy_MMIO_DMA5_REASON)
1482 & 0x0000DC00;
1483
1484 b43legacy_interrupt_ack(dev, reason);
44710bbc
SB		 1485 /* Disable all IRQs. They are enabled again in the bottom half. */
1486 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1487 /* Save the reason code and call our bottom half. */
75388acd
LF		 1488 dev->irq_reason = reason;
1489 tasklet_schedule(&dev->isr_tasklet);
1490out:
1491 mmiowb();
1492 spin_unlock(&dev->wl->irq_lock);
1493
1494 return ret;
1495}
1496
1497static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1498{
1499 release_firmware(dev->fw.ucode);
1500 dev->fw.ucode = NULL;
1501 release_firmware(dev->fw.pcm);
1502 dev->fw.pcm = NULL;
1503 release_firmware(dev->fw.initvals);
1504 dev->fw.initvals = NULL;
1505 release_firmware(dev->fw.initvals_band);
1506 dev->fw.initvals_band = NULL;
1507}
1508
1509static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1510{
1511 b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
354807e0 1512 "Drivers/b43#devicefirmware "
75388acd
LF		 1513 "and download the correct firmware (version 3).\n");
1514}
1515
1516static int do_request_fw(struct b43legacy_wldev *dev,
1517 const char *name,
1518 const struct firmware **fw)
1519{
1520 char path[sizeof(modparam_fwpostfix) + 32];
1521 struct b43legacy_fw_header *hdr;
1522 u32 size;
1523 int err;
1524
1525 if (!name)
1526 return 0;
1527
1528 snprintf(path, ARRAY_SIZE(path),
1529 "b43legacy%s/%s.fw",
1530 modparam_fwpostfix, name);
1531 err = request_firmware(fw, path, dev->dev->dev);
1532 if (err) {
1533 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1534 "or load failed.\n", path);
1535 return err;
1536 }
1537 if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1538 goto err_format;
1539 hdr = (struct b43legacy_fw_header *)((*fw)->data);
1540 switch (hdr->type) {
1541 case B43legacy_FW_TYPE_UCODE:
1542 case B43legacy_FW_TYPE_PCM:
1543 size = be32_to_cpu(hdr->size);
1544 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1545 goto err_format;
1546 /* fallthrough */
1547 case B43legacy_FW_TYPE_IV:
1548 if (hdr->ver != 1)
1549 goto err_format;
1550 break;
1551 default:
1552 goto err_format;
1553 }
1554
1555 return err;
1556
1557err_format:
1558 b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1559 return -EPROTO;
1560}
1561
1562static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1563{
1564 struct b43legacy_firmware *fw = &dev->fw;
1565 const u8 rev = dev->dev->id.revision;
1566 const char *filename;
1567 u32 tmshigh;
1568 int err;
1569
1570 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1571 if (!fw->ucode) {
1572 if (rev == 2)
1573 filename = "ucode2";
1574 else if (rev == 4)
1575 filename = "ucode4";
1576 else
1577 filename = "ucode5";
1578 err = do_request_fw(dev, filename, &fw->ucode);
1579 if (err)
1580 goto err_load;
1581 }
1582 if (!fw->pcm) {
1583 if (rev < 5)
1584 filename = "pcm4";
1585 else
1586 filename = "pcm5";
1587 err = do_request_fw(dev, filename, &fw->pcm);
1588 if (err)
1589 goto err_load;
1590 }
1591 if (!fw->initvals) {
1592 switch (dev->phy.type) {
385f848a 1593 case B43legacy_PHYTYPE_B:
75388acd
LF		 1594 case B43legacy_PHYTYPE_G:
1595 if ((rev >= 5) && (rev <= 10))
1596 filename = "b0g0initvals5";
1597 else if (rev == 2 || rev == 4)
1598 filename = "b0g0initvals2";
1599 else
1600 goto err_no_initvals;
1601 break;
1602 default:
1603 goto err_no_initvals;
1604 }
1605 err = do_request_fw(dev, filename, &fw->initvals);
1606 if (err)
1607 goto err_load;
1608 }
1609 if (!fw->initvals_band) {
1610 switch (dev->phy.type) {
385f848a 1611 case B43legacy_PHYTYPE_B:
75388acd
LF		 1612 case B43legacy_PHYTYPE_G:
1613 if ((rev >= 5) && (rev <= 10))
1614 filename = "b0g0bsinitvals5";
1615 else if (rev >= 11)
1616 filename = NULL;
1617 else if (rev == 2 || rev == 4)
1618 filename = NULL;
1619 else
1620 goto err_no_initvals;
1621 break;
1622 default:
1623 goto err_no_initvals;
1624 }
1625 err = do_request_fw(dev, filename, &fw->initvals_band);
1626 if (err)
1627 goto err_load;
1628 }
1629
1630 return 0;
1631
1632err_load:
1633 b43legacy_print_fw_helptext(dev->wl);
1634 goto error;
1635
1636err_no_initvals:
1637 err = -ENODEV;
1638 b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1639 "core rev %u\n", dev->phy.type, rev);
1640 goto error;
1641
1642error:
1643 b43legacy_release_firmware(dev);
1644 return err;
1645}
1646
1647static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1648{
bcf3c7c5 1649 struct wiphy *wiphy = dev->wl->hw->wiphy;
75388acd
LF		 1650 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1651 const __be32 *data;
1652 unsigned int i;
1653 unsigned int len;
1654 u16 fwrev;
1655 u16 fwpatch;
1656 u16 fwdate;
1657 u16 fwtime;
e78c9d28 1658 u32 tmp, macctl;
75388acd
LF		 1659 int err = 0;
1660
e78c9d28
SB		 1661 /* Jump the microcode PSM to offset 0 */
1662 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1663 B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1664 macctl |= B43legacy_MACCTL_PSM_JMP0;
1665 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1666 /* Zero out all microcode PSM registers and shared memory. */
1667 for (i = 0; i < 64; i++)
1668 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1669 for (i = 0; i < 4096; i += 2)
1670 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1671
75388acd
LF		 1672 /* Upload Microcode. */
1673 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1674 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1675 b43legacy_shm_control_word(dev,
1676 B43legacy_SHM_UCODE |
1677 B43legacy_SHM_AUTOINC_W,
1678 0x0000);
1679 for (i = 0; i < len; i++) {
1680 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1681 be32_to_cpu(data[i]));
1682 udelay(10);
1683 }
1684
1685 if (dev->fw.pcm) {
1686 /* Upload PCM data. */
1687 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1688 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1689 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1690 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1691 /* No need for autoinc bit in SHM_HW */
1692 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1693 for (i = 0; i < len; i++) {
1694 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1695 be32_to_cpu(data[i]));
1696 udelay(10);
1697 }
1698 }
1699
1700 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1701 B43legacy_IRQ_ALL);
e78c9d28
SB		 1702
1703 /* Start the microcode PSM */
1704 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1705 macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1706 macctl |= B43legacy_MACCTL_PSM_RUN;
1707 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 1708
1709 /* Wait for the microcode to load and respond */
1710 i = 0;
1711 while (1) {
1712 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1713 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1714 break;
1715 i++;
1716 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1717 b43legacyerr(dev->wl, "Microcode not responding\n");
1718 b43legacy_print_fw_helptext(dev->wl);
1719 err = -ENODEV;
e78c9d28
SB		 1720 goto error;
1721 }
1722 msleep_interruptible(50);
1723 if (signal_pending(current)) {
1724 err = -EINTR;
1725 goto error;
75388acd 1726 }
75388acd
LF		 1727 }
1728 /* dummy read follows */
1729 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1730
1731 /* Get and check the revisions. */
1732 fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1733 B43legacy_SHM_SH_UCODEREV);
1734 fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1735 B43legacy_SHM_SH_UCODEPATCH);
1736 fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1737 B43legacy_SHM_SH_UCODEDATE);
1738 fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1739 B43legacy_SHM_SH_UCODETIME);
1740
1741 if (fwrev > 0x128) {
1742 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1743 " Only firmware from binary drivers version 3.x"
1744 " is supported. You must change your firmware"
1745 " files.\n");
1746 b43legacy_print_fw_helptext(dev->wl);
75388acd 1747 err = -EOPNOTSUPP;
e78c9d28 1748 goto error;
75388acd 1749 }
cfbc35b6
SB		 1750 b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1751 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1752 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1753 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1754 fwtime & 0x1F);
75388acd
LF		 1755
1756 dev->fw.rev = fwrev;
1757 dev->fw.patch = fwpatch;
1758
bcf3c7c5
JL		 1759 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
1760 dev->fw.rev, dev->fw.patch);
1761 wiphy->hw_version = dev->dev->id.coreid;
1762
e78c9d28
SB		 1763 return 0;
1764
1765error:
1766 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1767 macctl &= ~B43legacy_MACCTL_PSM_RUN;
1768 macctl |= B43legacy_MACCTL_PSM_JMP0;
1769 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1770
75388acd
LF		 1771 return err;
1772}
1773
1774static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1775 const struct b43legacy_iv *ivals,
1776 size_t count,
1777 size_t array_size)
1778{
1779 const struct b43legacy_iv *iv;
1780 u16 offset;
1781 size_t i;
1782 bool bit32;
1783
1784 BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1785 iv = ivals;
1786 for (i = 0; i < count; i++) {
1787 if (array_size < sizeof(iv->offset_size))
1788 goto err_format;
1789 array_size -= sizeof(iv->offset_size);
1790 offset = be16_to_cpu(iv->offset_size);
1791 bit32 = !!(offset & B43legacy_IV_32BIT);
1792 offset &= B43legacy_IV_OFFSET_MASK;
1793 if (offset >= 0x1000)
1794 goto err_format;
1795 if (bit32) {
1796 u32 value;
1797
1798 if (array_size < sizeof(iv->data.d32))
1799 goto err_format;
1800 array_size -= sizeof(iv->data.d32);
1801
533dd1b0 1802 value = get_unaligned_be32(&iv->data.d32);
75388acd
LF		 1803 b43legacy_write32(dev, offset, value);
1804
1805 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1806 sizeof(__be16) +
1807 sizeof(__be32));
1808 } else {
1809 u16 value;
1810
1811 if (array_size < sizeof(iv->data.d16))
1812 goto err_format;
1813 array_size -= sizeof(iv->data.d16);
1814
1815 value = be16_to_cpu(iv->data.d16);
1816 b43legacy_write16(dev, offset, value);
1817
1818 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1819 sizeof(__be16) +
1820 sizeof(__be16));
1821 }
1822 }
1823 if (array_size)
1824 goto err_format;
1825
1826 return 0;
1827
1828err_format:
1829 b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1830 b43legacy_print_fw_helptext(dev->wl);
1831
1832 return -EPROTO;
1833}
1834
1835static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1836{
1837 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1838 const struct b43legacy_fw_header *hdr;
1839 struct b43legacy_firmware *fw = &dev->fw;
1840 const struct b43legacy_iv *ivals;
1841 size_t count;
1842 int err;
1843
1844 hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1845 ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1846 count = be32_to_cpu(hdr->size);
1847 err = b43legacy_write_initvals(dev, ivals, count,
1848 fw->initvals->size - hdr_len);
1849 if (err)
1850 goto out;
1851 if (fw->initvals_band) {
1852 hdr = (const struct b43legacy_fw_header *)
1853 (fw->initvals_band->data);
1854 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1855 + hdr_len);
1856 count = be32_to_cpu(hdr->size);
1857 err = b43legacy_write_initvals(dev, ivals, count,
1858 fw->initvals_band->size - hdr_len);
1859 if (err)
1860 goto out;
1861 }
1862out:
1863
1864 return err;
1865}
1866
1867/* Initialize the GPIOs
1868 * http://bcm-specs.sipsolutions.net/GPIO
1869 */
1870static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1871{
1872 struct ssb_bus *bus = dev->dev->bus;
1873 struct ssb_device *gpiodev, *pcidev = NULL;
1874 u32 mask;
1875 u32 set;
1876
e78c9d28 1877 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1878 b43legacy_read32(dev,
e78c9d28 1879 B43legacy_MMIO_MACCTL)
75388acd
LF		 1880 & 0xFFFF3FFF);
1881
75388acd
LF		 1882 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1883 b43legacy_read16(dev,
1884 B43legacy_MMIO_GPIO_MASK)
1885 | 0x000F);
1886
1887 mask = 0x0000001F;
1888 set = 0x0000000F;
1889 if (dev->dev->bus->chip_id == 0x4301) {
1890 mask |= 0x0060;
1891 set |= 0x0060;
1892 }
7797aa38 1893 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
75388acd
LF		 1894 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1895 b43legacy_read16(dev,
1896 B43legacy_MMIO_GPIO_MASK)
1897 | 0x0200);
1898 mask |= 0x0200;
1899 set |= 0x0200;
1900 }
1901 if (dev->dev->id.revision >= 2)
1902 mask |= 0x0010; /* FIXME: This is redundant. */
1903
1904#ifdef CONFIG_SSB_DRIVER_PCICORE
1905 pcidev = bus->pcicore.dev;
1906#endif
1907 gpiodev = bus->chipco.dev ? : pcidev;
1908 if (!gpiodev)
1909 return 0;
1910 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1911 (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1912 & mask) | set);
1913
1914 return 0;
1915}
1916
1917/* Turn off all GPIO stuff. Call this on module unload, for example. */
1918static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1919{
1920 struct ssb_bus *bus = dev->dev->bus;
1921 struct ssb_device *gpiodev, *pcidev = NULL;
1922
1923#ifdef CONFIG_SSB_DRIVER_PCICORE
1924 pcidev = bus->pcicore.dev;
1925#endif
1926 gpiodev = bus->chipco.dev ? : pcidev;
1927 if (!gpiodev)
1928 return;
1929 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1930}
1931
1932/* http://bcm-specs.sipsolutions.net/EnableMac */
1933void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1934{
1935 dev->mac_suspended--;
1936 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1937 B43legacy_WARN_ON(irqs_disabled());
75388acd 1938 if (dev->mac_suspended == 0) {
e78c9d28 1939 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1940 b43legacy_read32(dev,
e78c9d28
SB		 1941 B43legacy_MMIO_MACCTL)
1942 | B43legacy_MACCTL_ENABLED);
75388acd
LF		 1943 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1944 B43legacy_IRQ_MAC_SUSPENDED);
1945 /* the next two are dummy reads */
e78c9d28 1946 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 1947 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1948 b43legacy_power_saving_ctl_bits(dev, -1, -1);
f34eb692
LF		 1949
1950 /* Re-enable IRQs. */
1951 spin_lock_irq(&dev->wl->irq_lock);
44710bbc
SB		 1952 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1953 dev->irq_mask);
f34eb692 1954 spin_unlock_irq(&dev->wl->irq_lock);
75388acd
LF		 1955 }
1956}
1957
1958/* http://bcm-specs.sipsolutions.net/SuspendMAC */
1959void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1960{
1961 int i;
1962 u32 tmp;
1963
f34eb692
LF		 1964 might_sleep();
1965 B43legacy_WARN_ON(irqs_disabled());
75388acd 1966 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1967
75388acd 1968 if (dev->mac_suspended == 0) {
f34eb692
LF		 1969 /* Mask IRQs before suspending MAC. Otherwise
1970 * the MAC stays busy and won't suspend. */
1971 spin_lock_irq(&dev->wl->irq_lock);
44710bbc 1972 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
f34eb692
LF		 1973 spin_unlock_irq(&dev->wl->irq_lock);
1974 b43legacy_synchronize_irq(dev);
f34eb692 1975
75388acd 1976 b43legacy_power_saving_ctl_bits(dev, -1, 1);
e78c9d28 1977 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1978 b43legacy_read32(dev,
e78c9d28
SB		 1979 B43legacy_MMIO_MACCTL)
1980 & ~B43legacy_MACCTL_ENABLED);
75388acd 1981 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
f34eb692 1982 for (i = 40; i; i--) {
75388acd
LF		 1983 tmp = b43legacy_read32(dev,
1984 B43legacy_MMIO_GEN_IRQ_REASON);
1985 if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1986 goto out;
f34eb692 1987 msleep(1);
75388acd
LF		 1988 }
1989 b43legacyerr(dev->wl, "MAC suspend failed\n");
1990 }
1991out:
1992 dev->mac_suspended++;
1993}
1994
1995static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1996{
1997 struct b43legacy_wl *wl = dev->wl;
1998 u32 ctl;
1999 u16 cfp_pretbtt;
2000
2001 ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2002 /* Reset status to STA infrastructure mode. */
2003 ctl &= ~B43legacy_MACCTL_AP;
2004 ctl &= ~B43legacy_MACCTL_KEEP_CTL;
2005 ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
2006 ctl &= ~B43legacy_MACCTL_KEEP_BAD;
2007 ctl &= ~B43legacy_MACCTL_PROMISC;
4150c572 2008 ctl &= ~B43legacy_MACCTL_BEACPROMISC;
75388acd
LF		 2009 ctl |= B43legacy_MACCTL_INFRA;
2010
05c914fe 2011 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
4150c572 2012 ctl |= B43legacy_MACCTL_AP;
05c914fe 2013 else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2014 ctl &= ~B43legacy_MACCTL_INFRA;
2015
2016 if (wl->filter_flags & FIF_CONTROL)
75388acd 2017 ctl |= B43legacy_MACCTL_KEEP_CTL;
4150c572
JB		 2018 if (wl->filter_flags & FIF_FCSFAIL)
2019 ctl |= B43legacy_MACCTL_KEEP_BAD;
2020 if (wl->filter_flags & FIF_PLCPFAIL)
2021 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
2022 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
75388acd 2023 ctl |= B43legacy_MACCTL_PROMISC;
4150c572
JB		 2024 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2025 ctl |= B43legacy_MACCTL_BEACPROMISC;
2026
75388acd
LF		 2027 /* Workaround: On old hardware the HW-MAC-address-filter
2028 * doesn't work properly, so always run promisc in filter
2029 * it in software. */
2030 if (dev->dev->id.revision <= 4)
2031 ctl |= B43legacy_MACCTL_PROMISC;
2032
2033 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2034
2035 cfp_pretbtt = 2;
2036 if ((ctl & B43legacy_MACCTL_INFRA) &&
2037 !(ctl & B43legacy_MACCTL_AP)) {
2038 if (dev->dev->bus->chip_id == 0x4306 &&
2039 dev->dev->bus->chip_rev == 3)
2040 cfp_pretbtt = 100;
2041 else
2042 cfp_pretbtt = 50;
2043 }
2044 b43legacy_write16(dev, 0x612, cfp_pretbtt);
2045}
2046
2047static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2048 u16 rate,
2049 int is_ofdm)
2050{
2051 u16 offset;
2052
2053 if (is_ofdm) {
2054 offset = 0x480;
2055 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2056 } else {
2057 offset = 0x4C0;
2058 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2059 }
2060 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2061 b43legacy_shm_read16(dev,
2062 B43legacy_SHM_SHARED, offset));
2063}
2064
2065static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2066{
2067 switch (dev->phy.type) {
2068 case B43legacy_PHYTYPE_G:
2069 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2070 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2071 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2072 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2073 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2074 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2075 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2076 /* fallthrough */
2077 case B43legacy_PHYTYPE_B:
2078 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2079 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2080 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2081 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2082 break;
2083 default:
2084 B43legacy_BUG_ON(1);
2085 }
2086}
2087
2088/* Set the TX-Antenna for management frames sent by firmware. */
2089static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2090 int antenna)
2091{
2092 u16 ant = 0;
2093 u16 tmp;
2094
2095 switch (antenna) {
2096 case B43legacy_ANTENNA0:
2097 ant |= B43legacy_TX4_PHY_ANT0;
2098 break;
2099 case B43legacy_ANTENNA1:
2100 ant |= B43legacy_TX4_PHY_ANT1;
2101 break;
2102 case B43legacy_ANTENNA_AUTO:
2103 ant |= B43legacy_TX4_PHY_ANTLAST;
2104 break;
2105 default:
2106 B43legacy_BUG_ON(1);
2107 }
2108
2109 /* FIXME We also need to set the other flags of the PHY control
2110 * field somewhere. */
2111
2112 /* For Beacons */
2113 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2114 B43legacy_SHM_SH_BEACPHYCTL);
2115 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2116 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2117 B43legacy_SHM_SH_BEACPHYCTL, tmp);
2118 /* For ACK/CTS */
2119 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2120 B43legacy_SHM_SH_ACKCTSPHYCTL);
2121 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2122 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2123 B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2124 /* For Probe Resposes */
2125 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2126 B43legacy_SHM_SH_PRPHYCTL);
2127 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2128 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2129 B43legacy_SHM_SH_PRPHYCTL, tmp);
2130}
2131
2132/* This is the opposite of b43legacy_chip_init() */
2133static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2134{
93bb7f3a 2135 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 2136 b43legacy_gpio_cleanup(dev);
2137 /* firmware is released later */
2138}
2139
2140/* Initialize the chip
2141 * http://bcm-specs.sipsolutions.net/ChipInit
2142 */
2143static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2144{
2145 struct b43legacy_phy *phy = &dev->phy;
2146 int err;
2147 int tmp;
e78c9d28 2148 u32 value32, macctl;
75388acd
LF		 2149 u16 value16;
2150
e78c9d28
SB		 2151 /* Initialize the MAC control */
2152 macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2153 if (dev->phy.gmode)
2154 macctl |= B43legacy_MACCTL_GMODE;
2155 macctl |= B43legacy_MACCTL_INFRA;
2156 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 2157
2158 err = b43legacy_request_firmware(dev);
2159 if (err)
2160 goto out;
2161 err = b43legacy_upload_microcode(dev);
2162 if (err)
2163 goto out; /* firmware is released later */
2164
2165 err = b43legacy_gpio_init(dev);
2166 if (err)
2167 goto out; /* firmware is released later */
ba48f7bb 2168
75388acd
LF		 2169 err = b43legacy_upload_initvals(dev);
2170 if (err)
4ad36d78 2171 goto err_gpio_clean;
75388acd 2172 b43legacy_radio_turn_on(dev);
75388acd
LF		 2173
2174 b43legacy_write16(dev, 0x03E6, 0x0000);
2175 err = b43legacy_phy_init(dev);
2176 if (err)
2177 goto err_radio_off;
2178
2179 /* Select initial Interference Mitigation. */
2180 tmp = phy->interfmode;
2181 phy->interfmode = B43legacy_INTERFMODE_NONE;
2182 b43legacy_radio_set_interference_mitigation(dev, tmp);
2183
2184 b43legacy_phy_set_antenna_diversity(dev);
2185 b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2186
2187 if (phy->type == B43legacy_PHYTYPE_B) {
2188 value16 = b43legacy_read16(dev, 0x005E);
2189 value16 |= 0x0004;
2190 b43legacy_write16(dev, 0x005E, value16);
2191 }
2192 b43legacy_write32(dev, 0x0100, 0x01000000);
2193 if (dev->dev->id.revision < 5)
2194 b43legacy_write32(dev, 0x010C, 0x01000000);
2195
e78c9d28
SB		 2196 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2197 value32 &= ~B43legacy_MACCTL_INFRA;
2198 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2199 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2200 value32 |= B43legacy_MACCTL_INFRA;
2201 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
75388acd 2202
75388acd
LF		 2203 if (b43legacy_using_pio(dev)) {
2204 b43legacy_write32(dev, 0x0210, 0x00000100);
2205 b43legacy_write32(dev, 0x0230, 0x00000100);
2206 b43legacy_write32(dev, 0x0250, 0x00000100);
2207 b43legacy_write32(dev, 0x0270, 0x00000100);
2208 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2209 0x0000);
2210 }
2211
2212 /* Probe Response Timeout value */
2213 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2214 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2215
2216 /* Initially set the wireless operation mode. */
2217 b43legacy_adjust_opmode(dev);
2218
2219 if (dev->dev->id.revision < 3) {
2220 b43legacy_write16(dev, 0x060E, 0x0000);
2221 b43legacy_write16(dev, 0x0610, 0x8000);
2222 b43legacy_write16(dev, 0x0604, 0x0000);
2223 b43legacy_write16(dev, 0x0606, 0x0200);
2224 } else {
2225 b43legacy_write32(dev, 0x0188, 0x80000000);
2226 b43legacy_write32(dev, 0x018C, 0x02000000);
2227 }
2228 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2229 b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2230 b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2231 b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2232 b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2233 b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2234 b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2235
2236 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
a7ffab33 2237 value32 |= B43legacy_TMSLOW_MACPHYCLKEN;
75388acd
LF		 2238 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2239
2240 b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2241 dev->dev->bus->chipco.fast_pwrup_delay);
2242
a293ee99
SB		 2243 /* PHY TX errors counter. */
2244 atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2245
75388acd
LF		 2246 B43legacy_WARN_ON(err != 0);
2247 b43legacydbg(dev->wl, "Chip initialized\n");
2248out:
2249 return err;
2250
2251err_radio_off:
93bb7f3a 2252 b43legacy_radio_turn_off(dev, 1);
4ad36d78 2253err_gpio_clean:
75388acd
LF		 2254 b43legacy_gpio_cleanup(dev);
2255 goto out;
2256}
2257
2258static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2259{
2260 struct b43legacy_phy *phy = &dev->phy;
2261
2262 if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2263 return;
2264
2265 b43legacy_mac_suspend(dev);
2266 b43legacy_phy_lo_g_measure(dev);
2267 b43legacy_mac_enable(dev);
2268}
2269
2270static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2271{
2272 b43legacy_phy_lo_mark_all_unused(dev);
7797aa38 2273 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
75388acd
LF		 2274 b43legacy_mac_suspend(dev);
2275 b43legacy_calc_nrssi_slope(dev);
2276 b43legacy_mac_enable(dev);
2277 }
2278}
2279
2280static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2281{
2282 /* Update device statistics. */
2283 b43legacy_calculate_link_quality(dev);
2284}
2285
2286static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2287{
2288 b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
a293ee99
SB		 2289
2290 atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2291 wmb();
75388acd
LF		 2292}
2293
75388acd
LF		 2294static void do_periodic_work(struct b43legacy_wldev *dev)
2295{
2296 unsigned int state;
2297
2298 state = dev->periodic_state;
6be50837 2299 if (state % 8 == 0)
75388acd 2300 b43legacy_periodic_every120sec(dev);
6be50837 2301 if (state % 4 == 0)
75388acd 2302 b43legacy_periodic_every60sec(dev);
6be50837 2303 if (state % 2 == 0)
75388acd 2304 b43legacy_periodic_every30sec(dev);
6be50837 2305 b43legacy_periodic_every15sec(dev);
75388acd
LF		 2306}
2307
f34eb692
LF		 2308/* Periodic work locking policy:
2309 * The whole periodic work handler is protected by
2310 * wl->mutex. If another lock is needed somewhere in the
21ae2956 2311 * pwork callchain, it's acquired in-place, where it's needed.
75388acd 2312 */
75388acd
LF		 2313static void b43legacy_periodic_work_handler(struct work_struct *work)
2314{
f34eb692
LF		 2315 struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2316 periodic_work.work);
2317 struct b43legacy_wl *wl = dev->wl;
75388acd 2318 unsigned long delay;
75388acd 2319
f34eb692 2320 mutex_lock(&wl->mutex);
75388acd
LF		 2321
2322 if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2323 goto out;
2324 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2325 goto out_requeue;
2326
f34eb692 2327 do_periodic_work(dev);
75388acd 2328
75388acd
LF		 2329 dev->periodic_state++;
2330out_requeue:
2331 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2332 delay = msecs_to_jiffies(50);
2333 else
6be50837 2334 delay = round_jiffies_relative(HZ * 15);
42935eca 2335 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
75388acd 2336out:
f34eb692 2337 mutex_unlock(&wl->mutex);
75388acd
LF		 2338}
2339
2340static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2341{
2342 struct delayed_work *work = &dev->periodic_work;
2343
2344 dev->periodic_state = 0;
2345 INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
42935eca 2346 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
75388acd
LF		 2347}
2348
2349/* Validate access to the chip (SHM) */
2350static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2351{
2352 u32 value;
2353 u32 shm_backup;
2354
2355 shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2356 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2357 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2358 0xAA5555AA)
2359 goto error;
2360 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2361 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2362 0x55AAAA55)
2363 goto error;
2364 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2365
2366 value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2367 if ((value | B43legacy_MACCTL_GMODE) !=
2368 (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2369 goto error;
2370
2371 value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2372 if (value)
2373 goto error;
2374
2375 return 0;
2376error:
2377 b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2378 return -ENODEV;
2379}
2380
2381static void b43legacy_security_init(struct b43legacy_wldev *dev)
2382{
2383 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2384 B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2385 dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2386 0x0056);
2387 /* KTP is a word address, but we address SHM bytewise.
2388 * So multiply by two.
2389 */
2390 dev->ktp *= 2;
2391 if (dev->dev->id.revision >= 5)
2392 /* Number of RCMTA address slots */
2393 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2394 dev->max_nr_keys - 8);
2395}
2396
910cfee3 2397#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2398static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2399{
2400 struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2401 unsigned long flags;
2402
2403 /* Don't take wl->mutex here, as it could deadlock with
2404 * hwrng internal locking. It's not needed to take
2405 * wl->mutex here, anyway. */
2406
2407 spin_lock_irqsave(&wl->irq_lock, flags);
2408 *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2409 spin_unlock_irqrestore(&wl->irq_lock, flags);
2410
2411 return (sizeof(u16));
2412}
910cfee3 2413#endif
75388acd
LF		 2414
2415static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2416{
910cfee3 2417#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2418 if (wl->rng_initialized)
2419 hwrng_unregister(&wl->rng);
910cfee3 2420#endif
75388acd
LF		 2421}
2422
2423static int b43legacy_rng_init(struct b43legacy_wl *wl)
2424{
910cfee3 2425 int err = 0;
75388acd 2426
910cfee3 2427#ifdef CONFIG_B43LEGACY_HWRNG
75388acd
LF		 2428 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2429 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2430 wl->rng.name = wl->rng_name;
2431 wl->rng.data_read = b43legacy_rng_read;
2432 wl->rng.priv = (unsigned long)wl;
2433 wl->rng_initialized = 1;
2434 err = hwrng_register(&wl->rng);
2435 if (err) {
2436 wl->rng_initialized = 0;
2437 b43legacyerr(wl, "Failed to register the random "
2438 "number generator (%d)\n", err);
2439 }
2440
910cfee3 2441#endif
75388acd
LF		 2442 return err;
2443}
2444
7bb45683
JB		 2445static void b43legacy_op_tx(struct ieee80211_hw *hw,
2446 struct sk_buff *skb)
75388acd
LF		 2447{
2448 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2449 struct b43legacy_wldev *dev = wl->current_dev;
2450 int err = -ENODEV;
2451 unsigned long flags;
2452
2453 if (unlikely(!dev))
2454 goto out;
2455 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2456 goto out;
2457 /* DMA-TX is done without a global lock. */
2458 if (b43legacy_using_pio(dev)) {
2459 spin_lock_irqsave(&wl->irq_lock, flags);
e039fa4a 2460 err = b43legacy_pio_tx(dev, skb);
75388acd
LF		 2461 spin_unlock_irqrestore(&wl->irq_lock, flags);
2462 } else
e039fa4a 2463 err = b43legacy_dma_tx(dev, skb);
75388acd 2464out:
664f2006
MB		 2465 if (unlikely(err)) {
2466 /* Drop the packet. */
2467 dev_kfree_skb_any(skb);
2468 }
75388acd
LF		 2469}
2470
e100bb64 2471static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
33a3dc93 2472 const struct ieee80211_tx_queue_params *params)
75388acd
LF		 2473{
2474 return 0;
2475}
2476
33a3dc93
SB		 2477static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2478 struct ieee80211_low_level_stats *stats)
75388acd
LF		 2479{
2480 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2481 unsigned long flags;
2482
2483 spin_lock_irqsave(&wl->irq_lock, flags);
2484 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2485 spin_unlock_irqrestore(&wl->irq_lock, flags);
2486
2487 return 0;
2488}
2489
2490static const char *phymode_to_string(unsigned int phymode)
2491{
2492 switch (phymode) {
2493 case B43legacy_PHYMODE_B:
2494 return "B";
2495 case B43legacy_PHYMODE_G:
2496 return "G";
2497 default:
2498 B43legacy_BUG_ON(1);
2499 }
2500 return "";
2501}
2502
2503static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2504 unsigned int phymode,
2505 struct b43legacy_wldev **dev,
2506 bool *gmode)
2507{
2508 struct b43legacy_wldev *d;
2509
2510 list_for_each_entry(d, &wl->devlist, list) {
2511 if (d->phy.possible_phymodes & phymode) {
2512 /* Ok, this device supports the PHY-mode.
2513 * Set the gmode bit. */
2514 *gmode = 1;
2515 *dev = d;
2516
2517 return 0;
2518 }
2519 }
2520
2521 return -ESRCH;
2522}
2523
2524static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2525{
2526 struct ssb_device *sdev = dev->dev;
2527 u32 tmslow;
2528
2529 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2530 tmslow &= ~B43legacy_TMSLOW_GMODE;
2531 tmslow |= B43legacy_TMSLOW_PHYRESET;
2532 tmslow |= SSB_TMSLOW_FGC;
2533 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2534 msleep(1);
2535
2536 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2537 tmslow &= ~SSB_TMSLOW_FGC;
2538 tmslow |= B43legacy_TMSLOW_PHYRESET;
2539 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2540 msleep(1);
2541}
2542
2543/* Expects wl->mutex locked */
2544static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2545 unsigned int new_mode)
2546{
08cb7e01 2547 struct b43legacy_wldev *uninitialized_var(up_dev);
75388acd
LF		 2548 struct b43legacy_wldev *down_dev;
2549 int err;
2550 bool gmode = 0;
2551 int prev_status;
2552
2553 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2554 if (err) {
2555 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2556 phymode_to_string(new_mode));
2557 return err;
2558 }
2559 if ((up_dev == wl->current_dev) &&
2560 (!!wl->current_dev->phy.gmode == !!gmode))
2561 /* This device is already running. */
2562 return 0;
2563 b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2564 phymode_to_string(new_mode));
2565 down_dev = wl->current_dev;
2566
2567 prev_status = b43legacy_status(down_dev);
2568 /* Shutdown the currently running core. */
2569 if (prev_status >= B43legacy_STAT_STARTED)
2570 b43legacy_wireless_core_stop(down_dev);
2571 if (prev_status >= B43legacy_STAT_INITIALIZED)
2572 b43legacy_wireless_core_exit(down_dev);
2573
2574 if (down_dev != up_dev)
2575 /* We switch to a different core, so we put PHY into
2576 * RESET on the old core. */
2577 b43legacy_put_phy_into_reset(down_dev);
2578
2579 /* Now start the new core. */
2580 up_dev->phy.gmode = gmode;
2581 if (prev_status >= B43legacy_STAT_INITIALIZED) {
2582 err = b43legacy_wireless_core_init(up_dev);
2583 if (err) {
2584 b43legacyerr(wl, "Fatal: Could not initialize device"
2585 " for newly selected %s-PHY mode\n",
2586 phymode_to_string(new_mode));
2587 goto init_failure;
2588 }
2589 }
2590 if (prev_status >= B43legacy_STAT_STARTED) {
2591 err = b43legacy_wireless_core_start(up_dev);
2592 if (err) {
2593 b43legacyerr(wl, "Fatal: Coult not start device for "
2594 "newly selected %s-PHY mode\n",
2595 phymode_to_string(new_mode));
2596 b43legacy_wireless_core_exit(up_dev);
2597 goto init_failure;
2598 }
2599 }
2600 B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2601
2602 b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2603
2604 wl->current_dev = up_dev;
2605
2606 return 0;
2607init_failure:
2608 /* Whoops, failed to init the new core. No core is operating now. */
2609 wl->current_dev = NULL;
2610 return err;
2611}
2612
9124b077
JB		 2613/* Write the short and long frame retry limit values. */
2614static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2615 unsigned int short_retry,
2616 unsigned int long_retry)
2617{
2618 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2619 * the chip-internal counter. */
2620 short_retry = min(short_retry, (unsigned int)0xF);
2621 long_retry = min(long_retry, (unsigned int)0xF);
2622
2623 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2624 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2625}
2626
33a3dc93 2627static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
e8975581 2628 u32 changed)
75388acd
LF		 2629{
2630 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2631 struct b43legacy_wldev *dev;
2632 struct b43legacy_phy *phy;
e8975581 2633 struct ieee80211_conf *conf = &hw->conf;
75388acd
LF		 2634 unsigned long flags;
2635 unsigned int new_phymode = 0xFFFF;
2636 int antenna_tx;
2637 int antenna_rx;
2638 int err = 0;
75388acd 2639
0f4ac38b
JB		 2640 antenna_tx = B43legacy_ANTENNA_DEFAULT;
2641 antenna_rx = B43legacy_ANTENNA_DEFAULT;
75388acd
LF		 2642
2643 mutex_lock(&wl->mutex);
8318d78a
JB		 2644 dev = wl->current_dev;
2645 phy = &dev->phy;
75388acd 2646
9124b077
JB		 2647 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2648 b43legacy_set_retry_limits(dev,
2649 conf->short_frame_max_tx_count,
2650 conf->long_frame_max_tx_count);
2651 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2652 if (!changed)
2653 goto out_unlock_mutex;
2654
75388acd 2655 /* Switch the PHY mode (if necessary). */
8318d78a
JB		 2656 switch (conf->channel->band) {
2657 case IEEE80211_BAND_2GHZ:
2658 if (phy->type == B43legacy_PHYTYPE_B)
2659 new_phymode = B43legacy_PHYMODE_B;
2660 else
2661 new_phymode = B43legacy_PHYMODE_G;
75388acd
LF		 2662 break;
2663 default:
2664 B43legacy_WARN_ON(1);
2665 }
2666 err = b43legacy_switch_phymode(wl, new_phymode);
2667 if (err)
2668 goto out_unlock_mutex;
75388acd
LF		 2669
2670 /* Disable IRQs while reconfiguring the device.
2671 * This makes it possible to drop the spinlock throughout
2672 * the reconfiguration process. */
2673 spin_lock_irqsave(&wl->irq_lock, flags);
2674 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2675 spin_unlock_irqrestore(&wl->irq_lock, flags);
2676 goto out_unlock_mutex;
2677 }
44710bbc 2678 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
75388acd
LF		 2679 spin_unlock_irqrestore(&wl->irq_lock, flags);
2680 b43legacy_synchronize_irq(dev);
2681
2682 /* Switch to the requested channel.
2683 * The firmware takes care of races with the TX handler. */
8318d78a
JB		 2684 if (conf->channel->hw_value != phy->channel)
2685 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
75388acd 2686
0869aea0 2687 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
5be3bda8 2688
75388acd
LF		 2689 /* Adjust the desired TX power level. */
2690 if (conf->power_level != 0) {
2691 if (conf->power_level != phy->power_level) {
2692 phy->power_level = conf->power_level;
2693 b43legacy_phy_xmitpower(dev);
2694 }
2695 }
2696
2697 /* Antennas for RX and management frame TX. */
2698 b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2699
fd4973c5
LF		 2700 if (wl->radio_enabled != phy->radio_on) {
2701 if (wl->radio_enabled) {
42a9174f
LF		 2702 b43legacy_radio_turn_on(dev);
2703 b43legacyinfo(dev->wl, "Radio turned on by software\n");
2704 if (!dev->radio_hw_enable)
2705 b43legacyinfo(dev->wl, "The hardware RF-kill"
2706 " button still turns the radio"
2707 " physically off. Press the"
2708 " button to turn it on.\n");
2709 } else {
93bb7f3a 2710 b43legacy_radio_turn_off(dev, 0);
42a9174f
LF		 2711 b43legacyinfo(dev->wl, "Radio turned off by"
2712 " software\n");
2713 }
2714 }
2715
75388acd 2716 spin_lock_irqsave(&wl->irq_lock, flags);
44710bbc 2717 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
75388acd
LF		 2718 mmiowb();
2719 spin_unlock_irqrestore(&wl->irq_lock, flags);
2720out_unlock_mutex:
2721 mutex_unlock(&wl->mutex);
2722
2723 return err;
2724}
2725
881d948c 2726static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
7f3704e9
JB		 2727{
2728 struct ieee80211_supported_band *sband =
2729 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2730 struct ieee80211_rate *rate;
2731 int i;
2732 u16 basic, direct, offset, basic_offset, rateptr;
2733
2734 for (i = 0; i < sband->n_bitrates; i++) {
2735 rate = &sband->bitrates[i];
2736
2737 if (b43legacy_is_cck_rate(rate->hw_value)) {
2738 direct = B43legacy_SHM_SH_CCKDIRECT;
2739 basic = B43legacy_SHM_SH_CCKBASIC;
2740 offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2741 offset &= 0xF;
2742 } else {
2743 direct = B43legacy_SHM_SH_OFDMDIRECT;
2744 basic = B43legacy_SHM_SH_OFDMBASIC;
2745 offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2746 offset &= 0xF;
2747 }
2748
2749 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2750
2751 if (b43legacy_is_cck_rate(rate->hw_value)) {
2752 basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2753 basic_offset &= 0xF;
2754 } else {
2755 basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2756 basic_offset &= 0xF;
2757 }
2758
2759 /*
2760 * Get the pointer that we need to point to
2761 * from the direct map
2762 */
2763 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2764 direct + 2 * basic_offset);
2765 /* and write it to the basic map */
2766 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2767 basic + 2 * offset, rateptr);
2768 }
2769}
2770
2771static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2772 struct ieee80211_vif *vif,
2773 struct ieee80211_bss_conf *conf,
2774 u32 changed)
2775{
2776 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2777 struct b43legacy_wldev *dev;
2778 struct b43legacy_phy *phy;
2779 unsigned long flags;
7f3704e9
JB		 2780
2781 mutex_lock(&wl->mutex);
2d0ddec5 2782 B43legacy_WARN_ON(wl->vif != vif);
7f3704e9
JB		 2783
2784 dev = wl->current_dev;
2785 phy = &dev->phy;
2786
2787 /* Disable IRQs while reconfiguring the device.
2788 * This makes it possible to drop the spinlock throughout
2789 * the reconfiguration process. */
2790 spin_lock_irqsave(&wl->irq_lock, flags);
2791 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2792 spin_unlock_irqrestore(&wl->irq_lock, flags);
2793 goto out_unlock_mutex;
2794 }
44710bbc 2795 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2d0ddec5
JB		 2796
2797 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 2798 b43legacy_synchronize_irq(dev);
2799
2800 if (conf->bssid)
2801 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2802 else
2803 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b
JB		 2804 }
2805
2806 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2807 if (changed & BSS_CHANGED_BEACON &&
2808 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2809 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2810 b43legacy_update_templates(wl);
2d0ddec5 2811
3f0d843b 2812 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 2813 b43legacy_write_mac_bssid_templates(dev);
2d0ddec5 2814 }
3f0d843b 2815 spin_unlock_irqrestore(&wl->irq_lock, flags);
7f3704e9
JB		 2816
2817 b43legacy_mac_suspend(dev);
2818
57c4d7b4
JB		 2819 if (changed & BSS_CHANGED_BEACON_INT &&
2820 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2821 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2822 b43legacy_set_beacon_int(dev, conf->beacon_int);
2823
7f3704e9
JB		 2824 if (changed & BSS_CHANGED_BASIC_RATES)
2825 b43legacy_update_basic_rates(dev, conf->basic_rates);
2826
2827 if (changed & BSS_CHANGED_ERP_SLOT) {
2828 if (conf->use_short_slot)
2829 b43legacy_short_slot_timing_enable(dev);
2830 else
2831 b43legacy_short_slot_timing_disable(dev);
2832 }
2833
2834 b43legacy_mac_enable(dev);
2835
2836 spin_lock_irqsave(&wl->irq_lock, flags);
44710bbc 2837 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
7f3704e9
JB		 2838 /* XXX: why? */
2839 mmiowb();
2840 spin_unlock_irqrestore(&wl->irq_lock, flags);
2841 out_unlock_mutex:
2842 mutex_unlock(&wl->mutex);
7f3704e9
JB		 2843}
2844
33a3dc93
SB		 2845static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2846 unsigned int changed,
3ac64bee 2847 unsigned int *fflags,u64 multicast)
75388acd
LF		 2848{
2849 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2850 struct b43legacy_wldev *dev = wl->current_dev;
2851 unsigned long flags;
2852
4150c572
JB		 2853 if (!dev) {
2854 *fflags = 0;
75388acd 2855 return;
75388acd 2856 }
4150c572
JB		 2857
2858 spin_lock_irqsave(&wl->irq_lock, flags);
2859 *fflags &= FIF_PROMISC_IN_BSS |
2860 FIF_ALLMULTI |
2861 FIF_FCSFAIL |
2862 FIF_PLCPFAIL |
2863 FIF_CONTROL |
2864 FIF_OTHER_BSS |
2865 FIF_BCN_PRBRESP_PROMISC;
2866
2867 changed &= FIF_PROMISC_IN_BSS |
2868 FIF_ALLMULTI |
2869 FIF_FCSFAIL |
2870 FIF_PLCPFAIL |
2871 FIF_CONTROL |
2872 FIF_OTHER_BSS |
2873 FIF_BCN_PRBRESP_PROMISC;
2874
2875 wl->filter_flags = *fflags;
2876
2877 if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2878 b43legacy_adjust_opmode(dev);
75388acd
LF		 2879 spin_unlock_irqrestore(&wl->irq_lock, flags);
2880}
2881
75388acd
LF		 2882/* Locking: wl->mutex */
2883static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2884{
2885 struct b43legacy_wl *wl = dev->wl;
2886 unsigned long flags;
2887
2888 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2889 return;
440cb58a
SB		 2890
2891 /* Disable and sync interrupts. We must do this before than
2892 * setting the status to INITIALIZED, as the interrupt handler
2893 * won't care about IRQs then. */
2894 spin_lock_irqsave(&wl->irq_lock, flags);
44710bbc 2895 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
440cb58a
SB		 2896 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2897 spin_unlock_irqrestore(&wl->irq_lock, flags);
2898 b43legacy_synchronize_irq(dev);
2899
75388acd
LF		 2900 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2901
2902 mutex_unlock(&wl->mutex);
2903 /* Must unlock as it would otherwise deadlock. No races here.
2904 * Cancel the possibly running self-rearming periodic work. */
2905 cancel_delayed_work_sync(&dev->periodic_work);
2906 mutex_lock(&wl->mutex);
2907
2908 ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2909
75388acd
LF		 2910 b43legacy_mac_suspend(dev);
2911 free_irq(dev->dev->irq, dev);
2912 b43legacydbg(wl, "Wireless interface stopped\n");
2913}
2914
2915/* Locking: wl->mutex */
2916static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2917{
2918 int err;
2919
2920 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2921
2922 drain_txstatus_queue(dev);
2923 err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2924 IRQF_SHARED, KBUILD_MODNAME, dev);
2925 if (err) {
2926 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2927 dev->dev->irq);
2928 goto out;
2929 }
2930 /* We are ready to run. */
0866b03c 2931 ieee80211_wake_queues(dev->wl->hw);
75388acd
LF		 2932 b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2933
2934 /* Start data flow (TX/RX) */
2935 b43legacy_mac_enable(dev);
44710bbc 2936 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
75388acd
LF		 2937
2938 /* Start maintenance work */
2939 b43legacy_periodic_tasks_setup(dev);
2940
2941 b43legacydbg(dev->wl, "Wireless interface started\n");
2942out:
2943 return err;
2944}
2945
2946/* Get PHY and RADIO versioning numbers */
2947static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2948{
2949 struct b43legacy_phy *phy = &dev->phy;
2950 u32 tmp;
2951 u8 analog_type;
2952 u8 phy_type;
2953 u8 phy_rev;
2954 u16 radio_manuf;
2955 u16 radio_ver;
2956 u16 radio_rev;
2957 int unsupported = 0;
2958
2959 /* Get PHY versioning */
2960 tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2961 analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2962 >> B43legacy_PHYVER_ANALOG_SHIFT;
2963 phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2964 phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2965 switch (phy_type) {
2966 case B43legacy_PHYTYPE_B:
2967 if (phy_rev != 2 && phy_rev != 4
2968 && phy_rev != 6 && phy_rev != 7)
2969 unsupported = 1;
2970 break;
2971 case B43legacy_PHYTYPE_G:
2972 if (phy_rev > 8)
2973 unsupported = 1;
2974 break;
2975 default:
2976 unsupported = 1;
2977 };
2978 if (unsupported) {
2979 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2980 "(Analog %u, Type %u, Revision %u)\n",
2981 analog_type, phy_type, phy_rev);
2982 return -EOPNOTSUPP;
2983 }
2984 b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2985 analog_type, phy_type, phy_rev);
2986
2987
2988 /* Get RADIO versioning */
2989 if (dev->dev->bus->chip_id == 0x4317) {
2990 if (dev->dev->bus->chip_rev == 0)
2991 tmp = 0x3205017F;
2992 else if (dev->dev->bus->chip_rev == 1)
2993 tmp = 0x4205017F;
2994 else
2995 tmp = 0x5205017F;
2996 } else {
2997 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2998 B43legacy_RADIOCTL_ID);
2999 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
3000 tmp <<= 16;
3001 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
3002 B43legacy_RADIOCTL_ID);
3003 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
3004 }
3005 radio_manuf = (tmp & 0x00000FFF);
3006 radio_ver = (tmp & 0x0FFFF000) >> 12;
3007 radio_rev = (tmp & 0xF0000000) >> 28;
3008 switch (phy_type) {
3009 case B43legacy_PHYTYPE_B:
3010 if ((radio_ver & 0xFFF0) != 0x2050)
3011 unsupported = 1;
3012 break;
3013 case B43legacy_PHYTYPE_G:
3014 if (radio_ver != 0x2050)
3015 unsupported = 1;
3016 break;
3017 default:
3018 B43legacy_BUG_ON(1);
3019 }
3020 if (unsupported) {
3021 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3022 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3023 radio_manuf, radio_ver, radio_rev);
3024 return -EOPNOTSUPP;
3025 }
3026 b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3027 " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3028
3029
3030 phy->radio_manuf = radio_manuf;
3031 phy->radio_ver = radio_ver;
3032 phy->radio_rev = radio_rev;
3033
3034 phy->analog = analog_type;
3035 phy->type = phy_type;
3036 phy->rev = phy_rev;
3037
3038 return 0;
3039}
3040
3041static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3042 struct b43legacy_phy *phy)
3043{
3044 struct b43legacy_lopair *lo;
3045 int i;
3046
3047 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3048 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3049
1065de15
LF		 3050 /* Assume the radio is enabled. If it's not enabled, the state will
3051 * immediately get fixed on the first periodic work run. */
3052 dev->radio_hw_enable = 1;
75388acd
LF		 3053
3054 phy->savedpctlreg = 0xFFFF;
3055 phy->aci_enable = 0;
3056 phy->aci_wlan_automatic = 0;
3057 phy->aci_hw_rssi = 0;
3058
3059 lo = phy->_lo_pairs;
3060 if (lo)
3061 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3062 B43legacy_LO_COUNT);
3063 phy->max_lb_gain = 0;
3064 phy->trsw_rx_gain = 0;
3065
3066 /* Set default attenuation values. */
3067 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3068 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3069 phy->txctl1 = b43legacy_default_txctl1(dev);
3070 phy->txpwr_offset = 0;
3071
3072 /* NRSSI */
3073 phy->nrssislope = 0;
3074 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3075 phy->nrssi[i] = -1000;
3076 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3077 phy->nrssi_lt[i] = i;
3078
3079 phy->lofcal = 0xFFFF;
3080 phy->initval = 0xFFFF;
3081
75388acd
LF		 3082 phy->interfmode = B43legacy_INTERFMODE_NONE;
3083 phy->channel = 0xFF;
3084}
3085
3086static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3087{
3088 /* Flags */
eed0fd21 3089 dev->dfq_valid = 0;
75388acd
LF		 3090
3091 /* Stats */
3092 memset(&dev->stats, 0, sizeof(dev->stats));
3093
3094 setup_struct_phy_for_init(dev, &dev->phy);
3095
3096 /* IRQ related flags */
3097 dev->irq_reason = 0;
3098 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
44710bbc 3099 dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
75388acd
LF		 3100
3101 dev->mac_suspended = 1;
3102
3103 /* Noise calculation context */
3104 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3105}
3106
3e2c40ef
SB		 3107static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3108 bool idle) {
3109 u16 pu_delay = 1050;
3110
05c914fe 3111 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3e2c40ef
SB		 3112 pu_delay = 500;
3113 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3114 pu_delay = max(pu_delay, (u16)2400);
3115
3116 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3117 B43legacy_SHM_SH_SPUWKUP, pu_delay);
3118}
3119
3120/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3121static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3122{
3123 u16 pretbtt;
3124
3125 /* The time value is in microseconds. */
05c914fe 3126 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3e2c40ef
SB		 3127 pretbtt = 2;
3128 else
3129 pretbtt = 250;
3130 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3131 B43legacy_SHM_SH_PRETBTT, pretbtt);
3132 b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3133}
3134
75388acd
LF		 3135/* Shutdown a wireless core */
3136/* Locking: wl->mutex */
3137static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3138{
75388acd 3139 struct b43legacy_phy *phy = &dev->phy;
e78c9d28 3140 u32 macctl;
75388acd
LF		 3141
3142 B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3143 if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3144 return;
3145 b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3146
e78c9d28
SB		 3147 /* Stop the microcode PSM. */
3148 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3149 macctl &= ~B43legacy_MACCTL_PSM_RUN;
3150 macctl |= B43legacy_MACCTL_PSM_JMP0;
3151 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3152
4ad36d78 3153 b43legacy_leds_exit(dev);
75388acd
LF		 3154 b43legacy_rng_exit(dev->wl);
3155 b43legacy_pio_free(dev);
3156 b43legacy_dma_free(dev);
3157 b43legacy_chip_exit(dev);
93bb7f3a 3158 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3159 b43legacy_switch_analog(dev, 0);
3160 if (phy->dyn_tssi_tbl)
3161 kfree(phy->tssi2dbm);
3162 kfree(phy->lo_control);
3163 phy->lo_control = NULL;
a297170d
SB		 3164 if (dev->wl->current_beacon) {
3165 dev_kfree_skb_any(dev->wl->current_beacon);
3166 dev->wl->current_beacon = NULL;
3167 }
3168
75388acd
LF		 3169 ssb_device_disable(dev->dev, 0);
3170 ssb_bus_may_powerdown(dev->dev->bus);
3171}
3172
3173static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3174{
3175 struct b43legacy_phy *phy = &dev->phy;
3176 int i;
3177
3178 /* Set default attenuation values. */
3179 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3180 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3181 phy->txctl1 = b43legacy_default_txctl1(dev);
3182 phy->txctl2 = 0xFFFF;
3183 phy->txpwr_offset = 0;
3184
3185 /* NRSSI */
3186 phy->nrssislope = 0;
3187 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3188 phy->nrssi[i] = -1000;
3189 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3190 phy->nrssi_lt[i] = i;
3191
3192 phy->lofcal = 0xFFFF;
3193 phy->initval = 0xFFFF;
3194
3195 phy->aci_enable = 0;
3196 phy->aci_wlan_automatic = 0;
3197 phy->aci_hw_rssi = 0;
3198
3199 phy->antenna_diversity = 0xFFFF;
3200 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3201 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3202
3203 /* Flags */
3204 phy->calibrated = 0;
75388acd
LF		 3205
3206 if (phy->_lo_pairs)
3207 memset(phy->_lo_pairs, 0,
3208 sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3209 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3210}
3211
3212/* Initialize a wireless core */
3213static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3214{
3215 struct b43legacy_wl *wl = dev->wl;
3216 struct ssb_bus *bus = dev->dev->bus;
3217 struct b43legacy_phy *phy = &dev->phy;
3218 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3219 int err;
3220 u32 hf;
3221 u32 tmp;
3222
3223 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3224
3225 err = ssb_bus_powerup(bus, 0);
3226 if (err)
3227 goto out;
3228 if (!ssb_device_is_enabled(dev->dev)) {
3229 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3230 b43legacy_wireless_core_reset(dev, tmp);
3231 }
3232
3233 if ((phy->type == B43legacy_PHYTYPE_B) ||
3234 (phy->type == B43legacy_PHYTYPE_G)) {
3235 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3236 * B43legacy_LO_COUNT,
3237 GFP_KERNEL);
3238 if (!phy->_lo_pairs)
3239 return -ENOMEM;
3240 }
3241 setup_struct_wldev_for_init(dev);
3242
3243 err = b43legacy_phy_init_tssi2dbm_table(dev);
3244 if (err)
3245 goto err_kfree_lo_control;
3246
3247 /* Enable IRQ routing to this device. */
3248 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3249
75388acd
LF		 3250 prepare_phy_data_for_init(dev);
3251 b43legacy_phy_calibrate(dev);
3252 err = b43legacy_chip_init(dev);
3253 if (err)
3254 goto err_kfree_tssitbl;
3255 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3256 B43legacy_SHM_SH_WLCOREREV,
3257 dev->dev->id.revision);
3258 hf = b43legacy_hf_read(dev);
3259 if (phy->type == B43legacy_PHYTYPE_G) {
3260 hf |= B43legacy_HF_SYMW;
3261 if (phy->rev == 1)
3262 hf |= B43legacy_HF_GDCW;
7797aa38 3263 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
75388acd
LF		 3264 hf |= B43legacy_HF_OFDMPABOOST;
3265 } else if (phy->type == B43legacy_PHYTYPE_B) {
3266 hf |= B43legacy_HF_SYMW;
3267 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3268 hf &= ~B43legacy_HF_GDCW;
3269 }
3270 b43legacy_hf_write(dev, hf);
3271
0a6e1bee
SB		 3272 b43legacy_set_retry_limits(dev,
3273 B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3274 B43legacy_DEFAULT_LONG_RETRY_LIMIT);
75388acd
LF		 3275
3276 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3277 0x0044, 3);
3278 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3279 0x0046, 2);
3280
3281 /* Disable sending probe responses from firmware.
3282 * Setting the MaxTime to one usec will always trigger
3283 * a timeout, so we never send any probe resp.
3284 * A timeout of zero is infinite. */
3285 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3286 B43legacy_SHM_SH_PRMAXTIME, 1);
3287
3288 b43legacy_rate_memory_init(dev);
3289
3290 /* Minimum Contention Window */
3291 if (phy->type == B43legacy_PHYTYPE_B)
3292 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3293 0x0003, 31);
3294 else
3295 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3296 0x0003, 15);
3297 /* Maximum Contention Window */
3298 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3299 0x0004, 1023);
3300
3301 do {
3302 if (b43legacy_using_pio(dev))
3303 err = b43legacy_pio_init(dev);
3304 else {
3305 err = b43legacy_dma_init(dev);
3306 if (!err)
3307 b43legacy_qos_init(dev);
3308 }
3309 } while (err == -EAGAIN);
3310 if (err)
3311 goto err_chip_exit;
3312
3e2c40ef 3313 b43legacy_set_synth_pu_delay(dev, 1);
75388acd
LF		 3314
3315 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 3316 b43legacy_upload_card_macaddress(dev);
75388acd
LF		 3317 b43legacy_security_init(dev);
3318 b43legacy_rng_init(wl);
3319
0866b03c 3320 ieee80211_wake_queues(dev->wl->hw);
75388acd
LF		 3321 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3322
4ad36d78 3323 b43legacy_leds_init(dev);
75388acd
LF		 3324out:
3325 return err;
3326
3327err_chip_exit:
3328 b43legacy_chip_exit(dev);
3329err_kfree_tssitbl:
3330 if (phy->dyn_tssi_tbl)
3331 kfree(phy->tssi2dbm);
3332err_kfree_lo_control:
3333 kfree(phy->lo_control);
3334 phy->lo_control = NULL;
3335 ssb_bus_may_powerdown(bus);
3336 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3337 return err;
3338}
3339
33a3dc93 3340static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3341 struct ieee80211_vif *vif)
75388acd
LF		 3342{
3343 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3344 struct b43legacy_wldev *dev;
3345 unsigned long flags;
3346 int err = -EOPNOTSUPP;
4150c572
JB		 3347
3348 /* TODO: allow WDS/AP devices to coexist */
3349
1ed32e4f
JB		 3350 if (vif->type != NL80211_IFTYPE_AP &&
3351 vif->type != NL80211_IFTYPE_STATION &&
3352 vif->type != NL80211_IFTYPE_WDS &&
3353 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 3354 return -EOPNOTSUPP;
75388acd
LF		 3355
3356 mutex_lock(&wl->mutex);
4150c572 3357 if (wl->operating)
75388acd
LF		 3358 goto out_mutex_unlock;
3359
1ed32e4f 3360 b43legacydbg(wl, "Adding Interface type %d\n", vif->type);
75388acd
LF		 3361
3362 dev = wl->current_dev;
4150c572 3363 wl->operating = 1;
1ed32e4f
JB		 3364 wl->vif = vif;
3365 wl->if_type = vif->type;
3366 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572
JB		 3367
3368 spin_lock_irqsave(&wl->irq_lock, flags);
3369 b43legacy_adjust_opmode(dev);
3e2c40ef
SB		 3370 b43legacy_set_pretbtt(dev);
3371 b43legacy_set_synth_pu_delay(dev, 0);
4150c572
JB		 3372 b43legacy_upload_card_macaddress(dev);
3373 spin_unlock_irqrestore(&wl->irq_lock, flags);
3374
3375 err = 0;
3376 out_mutex_unlock:
3377 mutex_unlock(&wl->mutex);
3378
3379 return err;
3380}
3381
33a3dc93 3382static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3383 struct ieee80211_vif *vif)
4150c572
JB		 3384{
3385 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3386 struct b43legacy_wldev *dev = wl->current_dev;
3387 unsigned long flags;
3388
1ed32e4f 3389 b43legacydbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 3390
3391 mutex_lock(&wl->mutex);
3392
3393 B43legacy_WARN_ON(!wl->operating);
1ed32e4f 3394 B43legacy_WARN_ON(wl->vif != vif);
32bfd35d 3395 wl->vif = NULL;
4150c572
JB		 3396
3397 wl->operating = 0;
3398
3399 spin_lock_irqsave(&wl->irq_lock, flags);
3400 b43legacy_adjust_opmode(dev);
3401 memset(wl->mac_addr, 0, ETH_ALEN);
3402 b43legacy_upload_card_macaddress(dev);
3403 spin_unlock_irqrestore(&wl->irq_lock, flags);
3404
3405 mutex_unlock(&wl->mutex);
3406}
3407
33a3dc93 3408static int b43legacy_op_start(struct ieee80211_hw *hw)
4150c572
JB		 3409{
3410 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3411 struct b43legacy_wldev *dev = wl->current_dev;
3412 int did_init = 0;
208eec88 3413 int err = 0;
4ad36d78 3414
ada50731
SB		 3415 /* Kill all old instance specific information to make sure
3416 * the card won't use it in the short timeframe between start
3417 * and mac80211 reconfiguring it. */
3418 memset(wl->bssid, 0, ETH_ALEN);
3419 memset(wl->mac_addr, 0, ETH_ALEN);
3420 wl->filter_flags = 0;
2d1f96dd
LF		 3421 wl->beacon0_uploaded = 0;
3422 wl->beacon1_uploaded = 0;
3423 wl->beacon_templates_virgin = 1;
fd4973c5 3424 wl->radio_enabled = 1;
ada50731 3425
4150c572
JB		 3426 mutex_lock(&wl->mutex);
3427
75388acd
LF		 3428 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3429 err = b43legacy_wireless_core_init(dev);
f41f3f37 3430 if (err)
75388acd
LF		 3431 goto out_mutex_unlock;
3432 did_init = 1;
3433 }
4150c572 3434
75388acd
LF		 3435 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3436 err = b43legacy_wireless_core_start(dev);
3437 if (err) {
3438 if (did_init)
3439 b43legacy_wireless_core_exit(dev);
3440 goto out_mutex_unlock;
3441 }
3442 }
3443
f41f3f37
JB		 3444 wiphy_rfkill_start_polling(hw->wiphy);
3445
75388acd
LF		 3446out_mutex_unlock:
3447 mutex_unlock(&wl->mutex);
3448
3449 return err;
3450}
3451
33a3dc93 3452static void b43legacy_op_stop(struct ieee80211_hw *hw)
75388acd
LF		 3453{
3454 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
4150c572 3455 struct b43legacy_wldev *dev = wl->current_dev;
75388acd 3456
7858e07b 3457 cancel_work_sync(&(wl->beacon_update_trigger));
4ad36d78 3458
75388acd 3459 mutex_lock(&wl->mutex);
4150c572
JB		 3460 if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3461 b43legacy_wireless_core_stop(dev);
3462 b43legacy_wireless_core_exit(dev);
fd4973c5 3463 wl->radio_enabled = 0;
75388acd
LF		 3464 mutex_unlock(&wl->mutex);
3465}
3466
a297170d 3467static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
17741cdc 3468 struct ieee80211_sta *sta, bool set)
a297170d
SB		 3469{
3470 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3471 unsigned long flags;
3472
3473 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 3474 b43legacy_update_templates(wl);
a297170d
SB		 3475 spin_unlock_irqrestore(&wl->irq_lock, flags);
3476
3477 return 0;
3478}
3479
c7ab1a4d
JL		 3480static int b43legacy_op_get_survey(struct ieee80211_hw *hw, int idx,
3481 struct survey_info *survey)
3482{
3483 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3484 struct b43legacy_wldev *dev = wl->current_dev;
3485 struct ieee80211_conf *conf = &hw->conf;
3486
3487 if (idx != 0)
3488 return -ENOENT;
3489
3490 survey->channel = conf->channel;
3491 survey->filled = SURVEY_INFO_NOISE_DBM;
3492 survey->noise = dev->stats.link_noise;
3493
3494 return 0;
3495}
3496
75388acd 3497static const struct ieee80211_ops b43legacy_hw_ops = {
33a3dc93
SB		 3498 .tx = b43legacy_op_tx,
3499 .conf_tx = b43legacy_op_conf_tx,
3500 .add_interface = b43legacy_op_add_interface,
3501 .remove_interface = b43legacy_op_remove_interface,
3502 .config = b43legacy_op_dev_config,
7f3704e9 3503 .bss_info_changed = b43legacy_op_bss_info_changed,
33a3dc93
SB		 3504 .configure_filter = b43legacy_op_configure_filter,
3505 .get_stats = b43legacy_op_get_stats,
33a3dc93
SB		 3506 .start = b43legacy_op_start,
3507 .stop = b43legacy_op_stop,
a297170d 3508 .set_tim = b43legacy_op_beacon_set_tim,
c7ab1a4d 3509 .get_survey = b43legacy_op_get_survey,
f41f3f37 3510 .rfkill_poll = b43legacy_rfkill_poll,
75388acd
LF		 3511};
3512
3513/* Hard-reset the chip. Do not call this directly.
3514 * Use b43legacy_controller_restart()
3515 */
3516static void b43legacy_chip_reset(struct work_struct *work)
3517{
3518 struct b43legacy_wldev *dev =
3519 container_of(work, struct b43legacy_wldev, restart_work);
3520 struct b43legacy_wl *wl = dev->wl;
3521 int err = 0;
3522 int prev_status;
3523
3524 mutex_lock(&wl->mutex);
3525
3526 prev_status = b43legacy_status(dev);
3527 /* Bring the device down... */
3528 if (prev_status >= B43legacy_STAT_STARTED)
3529 b43legacy_wireless_core_stop(dev);
3530 if (prev_status >= B43legacy_STAT_INITIALIZED)
3531 b43legacy_wireless_core_exit(dev);
3532
3533 /* ...and up again. */
3534 if (prev_status >= B43legacy_STAT_INITIALIZED) {
3535 err = b43legacy_wireless_core_init(dev);
3536 if (err)
3537 goto out;
3538 }
3539 if (prev_status >= B43legacy_STAT_STARTED) {
3540 err = b43legacy_wireless_core_start(dev);
3541 if (err) {
3542 b43legacy_wireless_core_exit(dev);
3543 goto out;
3544 }
3545 }
3546out:
48e6c51b
MB		 3547 if (err)
3548 wl->current_dev = NULL; /* Failed to init the dev. */
75388acd
LF		 3549 mutex_unlock(&wl->mutex);
3550 if (err)
3551 b43legacyerr(wl, "Controller restart FAILED\n");
3552 else
3553 b43legacyinfo(wl, "Controller restarted\n");
3554}
3555
3556static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3557 int have_bphy,
3558 int have_gphy)
3559{
3560 struct ieee80211_hw *hw = dev->wl->hw;
75388acd 3561 struct b43legacy_phy *phy = &dev->phy;
75388acd
LF		 3562
3563 phy->possible_phymodes = 0;
8318d78a
JB		 3564 if (have_bphy) {
3565 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3566 &b43legacy_band_2GHz_BPHY;
3567 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3568 }
3569
3570 if (have_gphy) {
3571 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3572 &b43legacy_band_2GHz_GPHY;
3573 phy->possible_phymodes |= B43legacy_PHYMODE_G;
75388acd
LF		 3574 }
3575
3576 return 0;
3577}
3578
3579static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3580{
3581 /* We release firmware that late to not be required to re-request
3582 * is all the time when we reinit the core. */
3583 b43legacy_release_firmware(dev);
3584}
3585
3586static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3587{
3588 struct b43legacy_wl *wl = dev->wl;
3589 struct ssb_bus *bus = dev->dev->bus;
899110fe 3590 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
75388acd
LF		 3591 int err;
3592 int have_bphy = 0;
3593 int have_gphy = 0;
3594 u32 tmp;
3595
3596 /* Do NOT do any device initialization here.
3597 * Do it in wireless_core_init() instead.
3598 * This function is for gathering basic information about the HW, only.
3599 * Also some structs may be set up here. But most likely you want to
3600 * have that in core_init(), too.
3601 */
3602
3603 err = ssb_bus_powerup(bus, 0);
3604 if (err) {
3605 b43legacyerr(wl, "Bus powerup failed\n");
3606 goto out;
3607 }
3608 /* Get the PHY type. */
3609 if (dev->dev->id.revision >= 5) {
3610 u32 tmshigh;
3611
3612 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3613 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3614 if (!have_gphy)
3615 have_bphy = 1;
3616 } else if (dev->dev->id.revision == 4)
3617 have_gphy = 1;
3618 else
3619 have_bphy = 1;
3620
75388acd 3621 dev->phy.gmode = (have_gphy || have_bphy);
fd4973c5 3622 dev->phy.radio_on = 1;
75388acd
LF		 3623 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3624 b43legacy_wireless_core_reset(dev, tmp);
3625
3626 err = b43legacy_phy_versioning(dev);
3627 if (err)
ba48f7bb 3628 goto err_powerdown;
75388acd
LF		 3629 /* Check if this device supports multiband. */
3630 if (!pdev ||
3631 (pdev->device != 0x4312 &&
3632 pdev->device != 0x4319 &&
3633 pdev->device != 0x4324)) {
3634 /* No multiband support. */
3635 have_bphy = 0;
3636 have_gphy = 0;
3637 switch (dev->phy.type) {
3638 case B43legacy_PHYTYPE_B:
3639 have_bphy = 1;
3640 break;
3641 case B43legacy_PHYTYPE_G:
3642 have_gphy = 1;
3643 break;
3644 default:
3645 B43legacy_BUG_ON(1);
3646 }
3647 }
3648 dev->phy.gmode = (have_gphy || have_bphy);
3649 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3650 b43legacy_wireless_core_reset(dev, tmp);
3651
3652 err = b43legacy_validate_chipaccess(dev);
3653 if (err)
ba48f7bb 3654 goto err_powerdown;
75388acd
LF		 3655 err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3656 if (err)
ba48f7bb 3657 goto err_powerdown;
75388acd
LF		 3658
3659 /* Now set some default "current_dev" */
3660 if (!wl->current_dev)
3661 wl->current_dev = dev;
3662 INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3663
93bb7f3a 3664 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3665 b43legacy_switch_analog(dev, 0);
3666 ssb_device_disable(dev->dev, 0);
3667 ssb_bus_may_powerdown(bus);
3668
3669out:
3670 return err;
3671
75388acd
LF		 3672err_powerdown:
3673 ssb_bus_may_powerdown(bus);
3674 return err;
3675}
3676
3677static void b43legacy_one_core_detach(struct ssb_device *dev)
3678{
3679 struct b43legacy_wldev *wldev;
3680 struct b43legacy_wl *wl;
3681
48e6c51b
MB		 3682 /* Do not cancel ieee80211-workqueue based work here.
3683 * See comment in b43legacy_remove(). */
3684
75388acd
LF		 3685 wldev = ssb_get_drvdata(dev);
3686 wl = wldev->wl;
75388acd
LF		 3687 b43legacy_debugfs_remove_device(wldev);
3688 b43legacy_wireless_core_detach(wldev);
3689 list_del(&wldev->list);
3690 wl->nr_devs--;
3691 ssb_set_drvdata(dev, NULL);
3692 kfree(wldev);
3693}
3694
3695static int b43legacy_one_core_attach(struct ssb_device *dev,
3696 struct b43legacy_wl *wl)
3697{
3698 struct b43legacy_wldev *wldev;
75388acd
LF		 3699 int err = -ENOMEM;
3700
75388acd
LF		 3701 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3702 if (!wldev)
3703 goto out;
3704
3705 wldev->dev = dev;
3706 wldev->wl = wl;
3707 b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3708 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3709 tasklet_init(&wldev->isr_tasklet,
3710 (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3711 (unsigned long)wldev);
3712 if (modparam_pio)
3713 wldev->__using_pio = 1;
3714 INIT_LIST_HEAD(&wldev->list);
3715
3716 err = b43legacy_wireless_core_attach(wldev);
3717 if (err)
3718 goto err_kfree_wldev;
3719
3720 list_add(&wldev->list, &wl->devlist);
3721 wl->nr_devs++;
3722 ssb_set_drvdata(dev, wldev);
3723 b43legacy_debugfs_add_device(wldev);
3724out:
3725 return err;
3726
3727err_kfree_wldev:
3728 kfree(wldev);
3729 return err;
3730}
3731
3732static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3733{
3734 /* boardflags workarounds */
3735 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3736 bus->boardinfo.type == 0x4E &&
3737 bus->boardinfo.rev > 0x40)
7797aa38 3738 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
75388acd
LF		 3739}
3740
3741static void b43legacy_wireless_exit(struct ssb_device *dev,
3742 struct b43legacy_wl *wl)
3743{
3744 struct ieee80211_hw *hw = wl->hw;
3745
3746 ssb_set_devtypedata(dev, NULL);
3747 ieee80211_free_hw(hw);
3748}
3749
3750static int b43legacy_wireless_init(struct ssb_device *dev)
3751{
3752 struct ssb_sprom *sprom = &dev->bus->sprom;
3753 struct ieee80211_hw *hw;
3754 struct b43legacy_wl *wl;
3755 int err = -ENOMEM;
3756
3757 b43legacy_sprom_fixup(dev->bus);
3758
3759 hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3760 if (!hw) {
3761 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3762 goto out;
3763 }
3764
3765 /* fill hw info */
605a0bd6 3766 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 3767 IEEE80211_HW_SIGNAL_DBM;
f59ac048
LR		 3768 hw->wiphy->interface_modes =
3769 BIT(NL80211_IFTYPE_AP) |
3770 BIT(NL80211_IFTYPE_STATION) |
3771 BIT(NL80211_IFTYPE_WDS) |
3772 BIT(NL80211_IFTYPE_ADHOC);
75388acd 3773 hw->queues = 1; /* FIXME: hardware has more queues */
e6a9854b 3774 hw->max_rates = 2;
75388acd 3775 SET_IEEE80211_DEV(hw, dev->dev);
7797aa38
LF		 3776 if (is_valid_ether_addr(sprom->et1mac))
3777 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
75388acd 3778 else
7797aa38 3779 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
75388acd
LF		 3780
3781 /* Get and initialize struct b43legacy_wl */
3782 wl = hw_to_b43legacy_wl(hw);
3783 memset(wl, 0, sizeof(*wl));
3784 wl->hw = hw;
3785 spin_lock_init(&wl->irq_lock);
3786 spin_lock_init(&wl->leds_lock);
3787 mutex_init(&wl->mutex);
3788 INIT_LIST_HEAD(&wl->devlist);
7858e07b 3789 INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work);
75388acd
LF		 3790
3791 ssb_set_devtypedata(dev, wl);
3792 b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3793 err = 0;
3794out:
3795 return err;
3796}
3797
3798static int b43legacy_probe(struct ssb_device *dev,
3799 const struct ssb_device_id *id)
3800{
3801 struct b43legacy_wl *wl;
3802 int err;
3803 int first = 0;
3804
3805 wl = ssb_get_devtypedata(dev);
3806 if (!wl) {
3807 /* Probing the first core - setup common struct b43legacy_wl */
3808 first = 1;
3809 err = b43legacy_wireless_init(dev);
3810 if (err)
3811 goto out;
3812 wl = ssb_get_devtypedata(dev);
3813 B43legacy_WARN_ON(!wl);
3814 }
3815 err = b43legacy_one_core_attach(dev, wl);
3816 if (err)
3817 goto err_wireless_exit;
3818
3819 if (first) {
3820 err = ieee80211_register_hw(wl->hw);
3821 if (err)
3822 goto err_one_core_detach;
3823 }
3824
3825out:
3826 return err;
3827
3828err_one_core_detach:
3829 b43legacy_one_core_detach(dev);
3830err_wireless_exit:
3831 if (first)
3832 b43legacy_wireless_exit(dev, wl);
3833 return err;
3834}
3835
3836static void b43legacy_remove(struct ssb_device *dev)
3837{
3838 struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3839 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3840
48e6c51b
MB		 3841 /* We must cancel any work here before unregistering from ieee80211,
3842 * as the ieee80211 unreg will destroy the workqueue. */
3843 cancel_work_sync(&wldev->restart_work);
3844
75388acd
LF		 3845 B43legacy_WARN_ON(!wl);
3846 if (wl->current_dev == wldev)
3847 ieee80211_unregister_hw(wl->hw);
3848
3849 b43legacy_one_core_detach(dev);
3850
3851 if (list_empty(&wl->devlist))
3852 /* Last core on the chip unregistered.
3853 * We can destroy common struct b43legacy_wl.
3854 */
3855 b43legacy_wireless_exit(dev, wl);
3856}
3857
3858/* Perform a hardware reset. This can be called from any context. */
3859void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3860 const char *reason)
3861{
3862 /* Must avoid requeueing, if we are in shutdown. */
3863 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3864 return;
3865 b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 3866 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
75388acd
LF		 3867}
3868
3869#ifdef CONFIG_PM
3870
3871static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3872{
3873 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3874 struct b43legacy_wl *wl = wldev->wl;
3875
3876 b43legacydbg(wl, "Suspending...\n");
3877
3878 mutex_lock(&wl->mutex);
3879 wldev->suspend_init_status = b43legacy_status(wldev);
3880 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3881 b43legacy_wireless_core_stop(wldev);
3882 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3883 b43legacy_wireless_core_exit(wldev);
3884 mutex_unlock(&wl->mutex);
3885
3886 b43legacydbg(wl, "Device suspended.\n");
3887
3888 return 0;
3889}
3890
3891static int b43legacy_resume(struct ssb_device *dev)
3892{
3893 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3894 struct b43legacy_wl *wl = wldev->wl;
3895 int err = 0;
3896
3897 b43legacydbg(wl, "Resuming...\n");
3898
3899 mutex_lock(&wl->mutex);
3900 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3901 err = b43legacy_wireless_core_init(wldev);
3902 if (err) {
3903 b43legacyerr(wl, "Resume failed at core init\n");
3904 goto out;
3905 }
3906 }
3907 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3908 err = b43legacy_wireless_core_start(wldev);
3909 if (err) {
3910 b43legacy_wireless_core_exit(wldev);
3911 b43legacyerr(wl, "Resume failed at core start\n");
3912 goto out;
3913 }
3914 }
75388acd
LF		 3915
3916 b43legacydbg(wl, "Device resumed.\n");
3917out:
4104863f 3918 mutex_unlock(&wl->mutex);
75388acd
LF		 3919 return err;
3920}
3921
3922#else /* CONFIG_PM */
3923# define b43legacy_suspend NULL
3924# define b43legacy_resume NULL
3925#endif /* CONFIG_PM */
3926
3927static struct ssb_driver b43legacy_ssb_driver = {
3928 .name = KBUILD_MODNAME,
3929 .id_table = b43legacy_ssb_tbl,
3930 .probe = b43legacy_probe,
3931 .remove = b43legacy_remove,
3932 .suspend = b43legacy_suspend,
3933 .resume = b43legacy_resume,
3934};
3935
6fff1c64
SB		 3936static void b43legacy_print_driverinfo(void)
3937{
2f1f00fc 3938 const char *feat_pci = "", *feat_leds = "",
6fff1c64
SB		 3939 *feat_pio = "", *feat_dma = "";
3940
3941#ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3942 feat_pci = "P";
3943#endif
3944#ifdef CONFIG_B43LEGACY_LEDS
3945 feat_leds = "L";
3946#endif
6fff1c64
SB		 3947#ifdef CONFIG_B43LEGACY_PIO
3948 feat_pio = "I";
3949#endif
3950#ifdef CONFIG_B43LEGACY_DMA
3951 feat_dma = "D";
3952#endif
c256e05b 3953 printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
2f1f00fc 3954 "[ Features: %s%s%s%s, Firmware-ID: "
6fff1c64 3955 B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
2f1f00fc 3956 feat_pci, feat_leds, feat_pio, feat_dma);
6fff1c64
SB		 3957}
3958
75388acd
LF		 3959static int __init b43legacy_init(void)
3960{
3961 int err;
3962
3963 b43legacy_debugfs_init();
3964
3965 err = ssb_driver_register(&b43legacy_ssb_driver);
3966 if (err)
3967 goto err_dfs_exit;
3968
6fff1c64
SB		 3969 b43legacy_print_driverinfo();
3970
75388acd
LF		 3971 return err;
3972
3973err_dfs_exit:
3974 b43legacy_debugfs_exit();
3975 return err;
3976}
3977
3978static void __exit b43legacy_exit(void)
3979{
3980 ssb_driver_unregister(&b43legacy_ssb_driver);
3981 b43legacy_debugfs_exit();
3982}
3983
3984module_init(b43legacy_init)
3985module_exit(b43legacy_exit)
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