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b43legacy: add definitions for MAC control register
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / b43legacy / main.c
CommitLineData
75388acd
LF		 1/*
2 *
3 * Broadcom B43legacy wireless driver
4 *
5 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6fff1c64 6 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
75388acd
LF		 7 * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11 *
12 * Some parts of the code in this file are derived from the ipw2200
13 * driver Copyright(c) 2003 - 2004 Intel Corporation.
14
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING. If not, write to
27 * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28 * Boston, MA 02110-1301, USA.
29 *
30 */
31
32#include <linux/delay.h>
33#include <linux/init.h>
34#include <linux/moduleparam.h>
35#include <linux/if_arp.h>
36#include <linux/etherdevice.h>
37#include <linux/version.h>
38#include <linux/firmware.h>
39#include <linux/wireless.h>
40#include <linux/workqueue.h>
41#include <linux/skbuff.h>
42#include <linux/dma-mapping.h>
43#include <net/dst.h>
44#include <asm/unaligned.h>
45
46#include "b43legacy.h"
47#include "main.h"
48#include "debugfs.h"
49#include "phy.h"
50#include "dma.h"
51#include "pio.h"
52#include "sysfs.h"
53#include "xmit.h"
54#include "radio.h"
55
56
57MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
1a1c360d
SB		 63MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
64
75388acd
LF		 65#if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
66static int modparam_pio;
67module_param_named(pio, modparam_pio, int, 0444);
68MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
69#elif defined(CONFIG_B43LEGACY_DMA)
70# define modparam_pio 0
71#elif defined(CONFIG_B43LEGACY_PIO)
72# define modparam_pio 1
73#endif
74
75static int modparam_bad_frames_preempt;
76module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
77MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
78 " Preemption");
79
75388acd
LF		 80static char modparam_fwpostfix[16];
81module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
82MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
83
75388acd
LF		 84/* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
85static const struct ssb_device_id b43legacy_ssb_tbl[] = {
86 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
87 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
88 SSB_DEVTABLE_END
89};
90MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
91
92
93/* Channel and ratetables are shared for all devices.
94 * They can't be const, because ieee80211 puts some precalculated
95 * data in there. This data is the same for all devices, so we don't
96 * get concurrency issues */
97#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 98 { \
99 .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
100 .hw_value = (_rateid), \
101 .flags = (_flags), \
75388acd 102 }
8318d78a
JB		 103/*
104 * NOTE: When changing this, sync with xmit.c's
105 * b43legacy_plcp_get_bitrate_idx_* functions!
106 */
75388acd 107static struct ieee80211_rate __b43legacy_ratetable[] = {
8318d78a
JB		 108 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
109 RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
110 RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
111 RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
112 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
113 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
114 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
115 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
116 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
117 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
118 RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
119 RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
75388acd 120};
75388acd
LF		 121#define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
122#define b43legacy_b_ratetable_size 4
123#define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
124#define b43legacy_g_ratetable_size 12
125
126#define CHANTAB_ENT(_chanid, _freq) \
127 { \
8318d78a
JB		 128 .center_freq = (_freq), \
129 .hw_value = (_chanid), \
75388acd
LF		 130 }
131static struct ieee80211_channel b43legacy_bg_chantable[] = {
132 CHANTAB_ENT(1, 2412),
133 CHANTAB_ENT(2, 2417),
134 CHANTAB_ENT(3, 2422),
135 CHANTAB_ENT(4, 2427),
136 CHANTAB_ENT(5, 2432),
137 CHANTAB_ENT(6, 2437),
138 CHANTAB_ENT(7, 2442),
139 CHANTAB_ENT(8, 2447),
140 CHANTAB_ENT(9, 2452),
141 CHANTAB_ENT(10, 2457),
142 CHANTAB_ENT(11, 2462),
143 CHANTAB_ENT(12, 2467),
144 CHANTAB_ENT(13, 2472),
145 CHANTAB_ENT(14, 2484),
146};
8318d78a
JB		 147
148static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
149 .channels = b43legacy_bg_chantable,
150 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
151 .bitrates = b43legacy_b_ratetable,
152 .n_bitrates = b43legacy_b_ratetable_size,
153};
154
155static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
156 .channels = b43legacy_bg_chantable,
157 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
158 .bitrates = b43legacy_g_ratetable,
159 .n_bitrates = b43legacy_g_ratetable_size,
160};
75388acd
LF		 161
162static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
163static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
164static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
165static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
166
167
168static int b43legacy_ratelimit(struct b43legacy_wl *wl)
169{
170 if (!wl || !wl->current_dev)
171 return 1;
172 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
173 return 1;
174 /* We are up and running.
175 * Ratelimit the messages to avoid DoS over the net. */
176 return net_ratelimit();
177}
178
179void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
180{
181 va_list args;
182
183 if (!b43legacy_ratelimit(wl))
184 return;
185 va_start(args, fmt);
186 printk(KERN_INFO "b43legacy-%s: ",
187 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
188 vprintk(fmt, args);
189 va_end(args);
190}
191
192void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
193{
194 va_list args;
195
196 if (!b43legacy_ratelimit(wl))
197 return;
198 va_start(args, fmt);
199 printk(KERN_ERR "b43legacy-%s ERROR: ",
200 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
201 vprintk(fmt, args);
202 va_end(args);
203}
204
205void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
206{
207 va_list args;
208
209 if (!b43legacy_ratelimit(wl))
210 return;
211 va_start(args, fmt);
212 printk(KERN_WARNING "b43legacy-%s warning: ",
213 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
214 vprintk(fmt, args);
215 va_end(args);
216}
217
218#if B43legacy_DEBUG
219void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
220{
221 va_list args;
222
223 va_start(args, fmt);
224 printk(KERN_DEBUG "b43legacy-%s debug: ",
225 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
226 vprintk(fmt, args);
227 va_end(args);
228}
229#endif /* DEBUG */
230
231static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
232 u32 val)
233{
234 u32 status;
235
236 B43legacy_WARN_ON(offset % 4 != 0);
237
e78c9d28
SB		 238 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
239 if (status & B43legacy_MACCTL_BE)
75388acd
LF		 240 val = swab32(val);
241
242 b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
243 mmiowb();
244 b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
245}
246
247static inline
248void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
249 u16 routing, u16 offset)
250{
251 u32 control;
252
253 /* "offset" is the WORD offset. */
254
255 control = routing;
256 control <<= 16;
257 control |= offset;
258 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
259}
260
261u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
262 u16 routing, u16 offset)
263{
264 u32 ret;
265
266 if (routing == B43legacy_SHM_SHARED) {
267 B43legacy_WARN_ON((offset & 0x0001) != 0);
268 if (offset & 0x0003) {
269 /* Unaligned access */
270 b43legacy_shm_control_word(dev, routing, offset >> 2);
271 ret = b43legacy_read16(dev,
272 B43legacy_MMIO_SHM_DATA_UNALIGNED);
273 ret <<= 16;
274 b43legacy_shm_control_word(dev, routing,
275 (offset >> 2) + 1);
276 ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
277
278 return ret;
279 }
280 offset >>= 2;
281 }
282 b43legacy_shm_control_word(dev, routing, offset);
283 ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
284
285 return ret;
286}
287
288u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
289 u16 routing, u16 offset)
290{
291 u16 ret;
292
293 if (routing == B43legacy_SHM_SHARED) {
294 B43legacy_WARN_ON((offset & 0x0001) != 0);
295 if (offset & 0x0003) {
296 /* Unaligned access */
297 b43legacy_shm_control_word(dev, routing, offset >> 2);
298 ret = b43legacy_read16(dev,
299 B43legacy_MMIO_SHM_DATA_UNALIGNED);
300
301 return ret;
302 }
303 offset >>= 2;
304 }
305 b43legacy_shm_control_word(dev, routing, offset);
306 ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
307
308 return ret;
309}
310
311void b43legacy_shm_write32(struct b43legacy_wldev *dev,
312 u16 routing, u16 offset,
313 u32 value)
314{
315 if (routing == B43legacy_SHM_SHARED) {
316 B43legacy_WARN_ON((offset & 0x0001) != 0);
317 if (offset & 0x0003) {
318 /* Unaligned access */
319 b43legacy_shm_control_word(dev, routing, offset >> 2);
320 mmiowb();
321 b43legacy_write16(dev,
322 B43legacy_MMIO_SHM_DATA_UNALIGNED,
323 (value >> 16) & 0xffff);
324 mmiowb();
325 b43legacy_shm_control_word(dev, routing,
326 (offset >> 2) + 1);
327 mmiowb();
328 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
329 value & 0xffff);
330 return;
331 }
332 offset >>= 2;
333 }
334 b43legacy_shm_control_word(dev, routing, offset);
335 mmiowb();
336 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
337}
338
339void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
340 u16 value)
341{
342 if (routing == B43legacy_SHM_SHARED) {
343 B43legacy_WARN_ON((offset & 0x0001) != 0);
344 if (offset & 0x0003) {
345 /* Unaligned access */
346 b43legacy_shm_control_word(dev, routing, offset >> 2);
347 mmiowb();
348 b43legacy_write16(dev,
349 B43legacy_MMIO_SHM_DATA_UNALIGNED,
350 value);
351 return;
352 }
353 offset >>= 2;
354 }
355 b43legacy_shm_control_word(dev, routing, offset);
356 mmiowb();
357 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
358}
359
360/* Read HostFlags */
361u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
362{
363 u32 ret;
364
365 ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
366 B43legacy_SHM_SH_HOSTFHI);
367 ret <<= 16;
368 ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
369 B43legacy_SHM_SH_HOSTFLO);
370
371 return ret;
372}
373
374/* Write HostFlags */
375void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
376{
377 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
378 B43legacy_SHM_SH_HOSTFLO,
379 (value & 0x0000FFFF));
380 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
381 B43legacy_SHM_SH_HOSTFHI,
382 ((value & 0xFFFF0000) >> 16));
383}
384
385void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
386{
387 /* We need to be careful. As we read the TSF from multiple
388 * registers, we should take care of register overflows.
389 * In theory, the whole tsf read process should be atomic.
390 * We try to be atomic here, by restaring the read process,
391 * if any of the high registers changed (overflew).
392 */
393 if (dev->dev->id.revision >= 3) {
394 u32 low;
395 u32 high;
396 u32 high2;
397
398 do {
399 high = b43legacy_read32(dev,
400 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
401 low = b43legacy_read32(dev,
402 B43legacy_MMIO_REV3PLUS_TSF_LOW);
403 high2 = b43legacy_read32(dev,
404 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
405 } while (unlikely(high != high2));
406
407 *tsf = high;
408 *tsf <<= 32;
409 *tsf |= low;
410 } else {
411 u64 tmp;
412 u16 v0;
413 u16 v1;
414 u16 v2;
415 u16 v3;
416 u16 test1;
417 u16 test2;
418 u16 test3;
419
420 do {
421 v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
422 v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
423 v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
424 v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
425
426 test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
427 test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
428 test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
429 } while (v3 != test3 || v2 != test2 || v1 != test1);
430
431 *tsf = v3;
432 *tsf <<= 48;
433 tmp = v2;
434 tmp <<= 32;
435 *tsf |= tmp;
436 tmp = v1;
437 tmp <<= 16;
438 *tsf |= tmp;
439 *tsf |= v0;
440 }
441}
442
443static void b43legacy_time_lock(struct b43legacy_wldev *dev)
444{
445 u32 status;
446
e78c9d28
SB		 447 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
448 status |= B43legacy_MACCTL_TBTTHOLD;
449 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 450 mmiowb();
451}
452
453static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
454{
455 u32 status;
456
e78c9d28
SB		 457 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
458 status &= ~B43legacy_MACCTL_TBTTHOLD;
459 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 460}
461
462static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
463{
464 /* Be careful with the in-progress timer.
465 * First zero out the low register, so we have a full
466 * register-overflow duration to complete the operation.
467 */
468 if (dev->dev->id.revision >= 3) {
469 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
470 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
471
472 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
473 mmiowb();
474 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
475 hi);
476 mmiowb();
477 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
478 lo);
479 } else {
480 u16 v0 = (tsf & 0x000000000000FFFFULL);
481 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
482 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
483 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
484
485 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
486 mmiowb();
487 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
488 mmiowb();
489 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
490 mmiowb();
491 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
492 mmiowb();
493 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
494 }
495}
496
497void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
498{
499 b43legacy_time_lock(dev);
500 b43legacy_tsf_write_locked(dev, tsf);
501 b43legacy_time_unlock(dev);
502}
503
504static
505void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
506 u16 offset, const u8 *mac)
507{
508 static const u8 zero_addr[ETH_ALEN] = { 0 };
509 u16 data;
510
511 if (!mac)
512 mac = zero_addr;
513
514 offset |= 0x0020;
515 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
516
517 data = mac[0];
518 data |= mac[1] << 8;
519 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
520 data = mac[2];
521 data |= mac[3] << 8;
522 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
523 data = mac[4];
524 data |= mac[5] << 8;
525 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
526}
527
528static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
529{
530 static const u8 zero_addr[ETH_ALEN] = { 0 };
531 const u8 *mac = dev->wl->mac_addr;
532 const u8 *bssid = dev->wl->bssid;
533 u8 mac_bssid[ETH_ALEN * 2];
534 int i;
535 u32 tmp;
536
537 if (!bssid)
538 bssid = zero_addr;
539 if (!mac)
540 mac = zero_addr;
541
542 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
543
544 memcpy(mac_bssid, mac, ETH_ALEN);
545 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
546
547 /* Write our MAC address and BSSID to template ram */
548 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
549 tmp = (u32)(mac_bssid[i + 0]);
550 tmp |= (u32)(mac_bssid[i + 1]) << 8;
551 tmp |= (u32)(mac_bssid[i + 2]) << 16;
552 tmp |= (u32)(mac_bssid[i + 3]) << 24;
553 b43legacy_ram_write(dev, 0x20 + i, tmp);
554 b43legacy_ram_write(dev, 0x78 + i, tmp);
555 b43legacy_ram_write(dev, 0x478 + i, tmp);
556 }
557}
558
4150c572 559static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
75388acd 560{
75388acd 561 b43legacy_write_mac_bssid_templates(dev);
4150c572
JB		 562 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
563 dev->wl->mac_addr);
75388acd
LF		 564}
565
566static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
567 u16 slot_time)
568{
569 /* slot_time is in usec. */
570 if (dev->phy.type != B43legacy_PHYTYPE_G)
571 return;
572 b43legacy_write16(dev, 0x684, 510 + slot_time);
573 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
574 slot_time);
575}
576
577static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
578{
579 b43legacy_set_slot_time(dev, 9);
580 dev->short_slot = 1;
581}
582
583static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
584{
585 b43legacy_set_slot_time(dev, 20);
586 dev->short_slot = 0;
587}
588
589/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
590 * Returns the _previously_ enabled IRQ mask.
591 */
592static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
593 u32 mask)
594{
595 u32 old_mask;
596
597 old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
598 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
599 mask);
600
601 return old_mask;
602}
603
604/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
605 * Returns the _previously_ enabled IRQ mask.
606 */
607static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
608 u32 mask)
609{
610 u32 old_mask;
611
612 old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
613 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
614
615 return old_mask;
616}
617
618/* Synchronize IRQ top- and bottom-half.
619 * IRQs must be masked before calling this.
620 * This must not be called with the irq_lock held.
621 */
622static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
623{
624 synchronize_irq(dev->dev->irq);
625 tasklet_kill(&dev->isr_tasklet);
626}
627
628/* DummyTransmission function, as documented on
629 * http://bcm-specs.sipsolutions.net/DummyTransmission
630 */
631void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
632{
633 struct b43legacy_phy *phy = &dev->phy;
634 unsigned int i;
635 unsigned int max_loop;
636 u16 value;
637 u32 buffer[5] = {
638 0x00000000,
639 0x00D40000,
640 0x00000000,
641 0x01000000,
642 0x00000000,
643 };
644
645 switch (phy->type) {
646 case B43legacy_PHYTYPE_B:
647 case B43legacy_PHYTYPE_G:
648 max_loop = 0xFA;
649 buffer[0] = 0x000B846E;
650 break;
651 default:
652 B43legacy_BUG_ON(1);
653 return;
654 }
655
656 for (i = 0; i < 5; i++)
657 b43legacy_ram_write(dev, i * 4, buffer[i]);
658
659 /* dummy read follows */
e78c9d28 660 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 661
662 b43legacy_write16(dev, 0x0568, 0x0000);
663 b43legacy_write16(dev, 0x07C0, 0x0000);
664 b43legacy_write16(dev, 0x050C, 0x0000);
665 b43legacy_write16(dev, 0x0508, 0x0000);
666 b43legacy_write16(dev, 0x050A, 0x0000);
667 b43legacy_write16(dev, 0x054C, 0x0000);
668 b43legacy_write16(dev, 0x056A, 0x0014);
669 b43legacy_write16(dev, 0x0568, 0x0826);
670 b43legacy_write16(dev, 0x0500, 0x0000);
671 b43legacy_write16(dev, 0x0502, 0x0030);
672
673 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
674 b43legacy_radio_write16(dev, 0x0051, 0x0017);
675 for (i = 0x00; i < max_loop; i++) {
676 value = b43legacy_read16(dev, 0x050E);
677 if (value & 0x0080)
678 break;
679 udelay(10);
680 }
681 for (i = 0x00; i < 0x0A; i++) {
682 value = b43legacy_read16(dev, 0x050E);
683 if (value & 0x0400)
684 break;
685 udelay(10);
686 }
687 for (i = 0x00; i < 0x0A; i++) {
688 value = b43legacy_read16(dev, 0x0690);
689 if (!(value & 0x0100))
690 break;
691 udelay(10);
692 }
693 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
694 b43legacy_radio_write16(dev, 0x0051, 0x0037);
695}
696
697/* Turn the Analog ON/OFF */
698static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
699{
700 b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
701}
702
703void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
704{
705 u32 tmslow;
706 u32 macctl;
707
708 flags |= B43legacy_TMSLOW_PHYCLKEN;
709 flags |= B43legacy_TMSLOW_PHYRESET;
710 ssb_device_enable(dev->dev, flags);
711 msleep(2); /* Wait for the PLL to turn on. */
712
713 /* Now take the PHY out of Reset again */
714 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
715 tmslow |= SSB_TMSLOW_FGC;
716 tmslow &= ~B43legacy_TMSLOW_PHYRESET;
717 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
718 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
719 msleep(1);
720 tmslow &= ~SSB_TMSLOW_FGC;
721 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
722 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
723 msleep(1);
724
725 /* Turn Analog ON */
726 b43legacy_switch_analog(dev, 1);
727
728 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
729 macctl &= ~B43legacy_MACCTL_GMODE;
730 if (flags & B43legacy_TMSLOW_GMODE) {
731 macctl |= B43legacy_MACCTL_GMODE;
732 dev->phy.gmode = 1;
733 } else
734 dev->phy.gmode = 0;
735 macctl |= B43legacy_MACCTL_IHR_ENABLED;
736 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
737}
738
739static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
740{
741 u32 v0;
742 u32 v1;
743 u16 tmp;
744 struct b43legacy_txstatus stat;
745
746 while (1) {
747 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
748 if (!(v0 & 0x00000001))
749 break;
750 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
751
752 stat.cookie = (v0 >> 16);
753 stat.seq = (v1 & 0x0000FFFF);
754 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
755 tmp = (v0 & 0x0000FFFF);
756 stat.frame_count = ((tmp & 0xF000) >> 12);
757 stat.rts_count = ((tmp & 0x0F00) >> 8);
758 stat.supp_reason = ((tmp & 0x001C) >> 2);
759 stat.pm_indicated = !!(tmp & 0x0080);
760 stat.intermediate = !!(tmp & 0x0040);
761 stat.for_ampdu = !!(tmp & 0x0020);
762 stat.acked = !!(tmp & 0x0002);
763
764 b43legacy_handle_txstatus(dev, &stat);
765 }
766}
767
768static void drain_txstatus_queue(struct b43legacy_wldev *dev)
769{
770 u32 dummy;
771
772 if (dev->dev->id.revision < 5)
773 return;
774 /* Read all entries from the microcode TXstatus FIFO
775 * and throw them away.
776 */
777 while (1) {
778 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
779 if (!(dummy & 0x00000001))
780 break;
781 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
782 }
783}
784
785static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
786{
787 u32 val = 0;
788
789 val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
790 val <<= 16;
791 val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
792
793 return val;
794}
795
796static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
797{
798 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
799 (jssi & 0x0000FFFF));
800 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
801 (jssi & 0xFFFF0000) >> 16);
802}
803
804static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
805{
806 b43legacy_jssi_write(dev, 0x7F7F7F7F);
e78c9d28 807 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
eed0fd21
SB		 808 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
809 | B43legacy_MACCMD_BGNOISE);
75388acd
LF		 810 B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
811 dev->phy.channel);
812}
813
814static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
815{
816 /* Top half of Link Quality calculation. */
817
818 if (dev->noisecalc.calculation_running)
819 return;
820 dev->noisecalc.channel_at_start = dev->phy.channel;
821 dev->noisecalc.calculation_running = 1;
822 dev->noisecalc.nr_samples = 0;
823
824 b43legacy_generate_noise_sample(dev);
825}
826
827static void handle_irq_noise(struct b43legacy_wldev *dev)
828{
829 struct b43legacy_phy *phy = &dev->phy;
830 u16 tmp;
831 u8 noise[4];
832 u8 i;
833 u8 j;
834 s32 average;
835
836 /* Bottom half of Link Quality calculation. */
837
838 B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
839 if (dev->noisecalc.channel_at_start != phy->channel)
840 goto drop_calculation;
841 *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
842 if (noise[0] == 0x7F || noise[1] == 0x7F ||
843 noise[2] == 0x7F || noise[3] == 0x7F)
844 goto generate_new;
845
846 /* Get the noise samples. */
847 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
848 i = dev->noisecalc.nr_samples;
849 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
850 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
851 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
852 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
853 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
854 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
855 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
856 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
857 dev->noisecalc.nr_samples++;
858 if (dev->noisecalc.nr_samples == 8) {
859 /* Calculate the Link Quality by the noise samples. */
860 average = 0;
861 for (i = 0; i < 8; i++) {
862 for (j = 0; j < 4; j++)
863 average += dev->noisecalc.samples[i][j];
864 }
865 average /= (8 * 4);
866 average *= 125;
867 average += 64;
868 average /= 128;
869 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
870 0x40C);
871 tmp = (tmp / 128) & 0x1F;
872 if (tmp >= 8)
873 average += 2;
874 else
875 average -= 25;
876 if (tmp == 8)
877 average -= 72;
878 else
879 average -= 48;
880
881 dev->stats.link_noise = average;
882drop_calculation:
883 dev->noisecalc.calculation_running = 0;
884 return;
885 }
886generate_new:
887 b43legacy_generate_noise_sample(dev);
888}
889
890static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
891{
892 if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
893 /* TODO: PS TBTT */
894 } else {
895 if (1/*FIXME: the last PSpoll frame was sent successfully */)
896 b43legacy_power_saving_ctl_bits(dev, -1, -1);
897 }
75388acd 898 if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
eed0fd21 899 dev->dfq_valid = 1;
75388acd
LF		 900}
901
902static void handle_irq_atim_end(struct b43legacy_wldev *dev)
903{
eed0fd21
SB		 904 if (dev->dfq_valid) {
905 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
906 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
907 | B43legacy_MACCMD_DFQ_VALID);
908 dev->dfq_valid = 0;
909 }
75388acd
LF		 910}
911
912static void handle_irq_pmq(struct b43legacy_wldev *dev)
913{
914 u32 tmp;
915
916 /* TODO: AP mode. */
917
918 while (1) {
919 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
920 if (!(tmp & 0x00000008))
921 break;
922 }
923 /* 16bit write is odd, but correct. */
924 b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
925}
926
927static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
928 const u8 *data, u16 size,
929 u16 ram_offset,
930 u16 shm_size_offset, u8 rate)
931{
932 u32 i;
933 u32 tmp;
934 struct b43legacy_plcp_hdr4 plcp;
935
936 plcp.data = 0;
937 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
938 b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
939 ram_offset += sizeof(u32);
940 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
941 * So leave the first two bytes of the next write blank.
942 */
943 tmp = (u32)(data[0]) << 16;
944 tmp |= (u32)(data[1]) << 24;
945 b43legacy_ram_write(dev, ram_offset, tmp);
946 ram_offset += sizeof(u32);
947 for (i = 2; i < size; i += sizeof(u32)) {
948 tmp = (u32)(data[i + 0]);
949 if (i + 1 < size)
950 tmp |= (u32)(data[i + 1]) << 8;
951 if (i + 2 < size)
952 tmp |= (u32)(data[i + 2]) << 16;
953 if (i + 3 < size)
954 tmp |= (u32)(data[i + 3]) << 24;
955 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
956 }
957 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
958 size + sizeof(struct b43legacy_plcp_hdr6));
959}
960
961static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
962 u16 ram_offset,
963 u16 shm_size_offset, u8 rate)
964{
965 int len;
966 const u8 *data;
967
968 B43legacy_WARN_ON(!dev->cached_beacon);
969 len = min((size_t)dev->cached_beacon->len,
970 0x200 - sizeof(struct b43legacy_plcp_hdr6));
971 data = (const u8 *)(dev->cached_beacon->data);
972 b43legacy_write_template_common(dev, data,
973 len, ram_offset,
974 shm_size_offset, rate);
975}
976
977static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
978 u16 shm_offset, u16 size,
8318d78a 979 struct ieee80211_rate *rate)
75388acd
LF		 980{
981 struct b43legacy_plcp_hdr4 plcp;
982 u32 tmp;
983 __le16 dur;
984
985 plcp.data = 0;
8318d78a 986 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->bitrate);
75388acd 987 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 988 dev->wl->vif,
75388acd 989 size,
8318d78a 990 rate);
75388acd
LF		 991 /* Write PLCP in two parts and timing for packet transfer */
992 tmp = le32_to_cpu(plcp.data);
993 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
994 tmp & 0xFFFF);
995 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
996 tmp >> 16);
997 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
998 le16_to_cpu(dur));
999}
1000
1001/* Instead of using custom probe response template, this function
1002 * just patches custom beacon template by:
1003 * 1) Changing packet type
1004 * 2) Patching duration field
1005 * 3) Stripping TIM
1006 */
1007static u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
8318d78a
JB		 1008 u16 *dest_size,
1009 struct ieee80211_rate *rate)
75388acd
LF		 1010{
1011 const u8 *src_data;
1012 u8 *dest_data;
1013 u16 src_size;
1014 u16 elem_size;
1015 u16 src_pos;
1016 u16 dest_pos;
1017 __le16 dur;
1018 struct ieee80211_hdr *hdr;
1019
1020 B43legacy_WARN_ON(!dev->cached_beacon);
1021 src_size = dev->cached_beacon->len;
1022 src_data = (const u8 *)dev->cached_beacon->data;
1023
1024 if (unlikely(src_size < 0x24)) {
1025 b43legacydbg(dev->wl, "b43legacy_generate_probe_resp: "
1026 "invalid beacon\n");
1027 return NULL;
1028 }
1029
1030 dest_data = kmalloc(src_size, GFP_ATOMIC);
1031 if (unlikely(!dest_data))
1032 return NULL;
1033
1034 /* 0x24 is offset of first variable-len Information-Element
1035 * in beacon frame.
1036 */
1037 memcpy(dest_data, src_data, 0x24);
1038 src_pos = 0x24;
1039 dest_pos = 0x24;
1040 for (; src_pos < src_size - 2; src_pos += elem_size) {
1041 elem_size = src_data[src_pos + 1] + 2;
1042 if (src_data[src_pos] != 0x05) { /* TIM */
1043 memcpy(dest_data + dest_pos, src_data + src_pos,
1044 elem_size);
1045 dest_pos += elem_size;
1046 }
1047 }
1048 *dest_size = dest_pos;
1049 hdr = (struct ieee80211_hdr *)dest_data;
1050
1051 /* Set the frame control. */
1052 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1053 IEEE80211_STYPE_PROBE_RESP);
1054 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1055 dev->wl->vif,
75388acd 1056 *dest_size,
8318d78a 1057 rate);
75388acd
LF		 1058 hdr->duration_id = dur;
1059
1060 return dest_data;
1061}
1062
1063static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1064 u16 ram_offset,
8318d78a
JB		 1065 u16 shm_size_offset,
1066 struct ieee80211_rate *rate)
75388acd
LF		 1067{
1068 u8 *probe_resp_data;
1069 u16 size;
1070
1071 B43legacy_WARN_ON(!dev->cached_beacon);
1072 size = dev->cached_beacon->len;
1073 probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1074 if (unlikely(!probe_resp_data))
1075 return;
1076
1077 /* Looks like PLCP headers plus packet timings are stored for
1078 * all possible basic rates
1079 */
1080 b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
8318d78a 1081 &b43legacy_b_ratetable[0]);
75388acd 1082 b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
8318d78a 1083 &b43legacy_b_ratetable[1]);
75388acd 1084 b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
8318d78a 1085 &b43legacy_b_ratetable[2]);
75388acd 1086 b43legacy_write_probe_resp_plcp(dev, 0x350, size,
8318d78a 1087 &b43legacy_b_ratetable[3]);
75388acd
LF		 1088
1089 size = min((size_t)size,
1090 0x200 - sizeof(struct b43legacy_plcp_hdr6));
1091 b43legacy_write_template_common(dev, probe_resp_data,
1092 size, ram_offset,
8318d78a 1093 shm_size_offset, rate->bitrate);
75388acd
LF		 1094 kfree(probe_resp_data);
1095}
1096
1097static int b43legacy_refresh_cached_beacon(struct b43legacy_wldev *dev,
1098 struct sk_buff *beacon)
1099{
1100 if (dev->cached_beacon)
1101 kfree_skb(dev->cached_beacon);
1102 dev->cached_beacon = beacon;
1103
1104 return 0;
1105}
1106
1107static void b43legacy_update_templates(struct b43legacy_wldev *dev)
1108{
eed0fd21 1109 u32 cmd;
75388acd
LF		 1110
1111 B43legacy_WARN_ON(!dev->cached_beacon);
1112
1113 b43legacy_write_beacon_template(dev, 0x68, 0x18,
1114 B43legacy_CCK_RATE_1MB);
1115 b43legacy_write_beacon_template(dev, 0x468, 0x1A,
1116 B43legacy_CCK_RATE_1MB);
1117 b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
8318d78a 1118 &b43legacy_b_ratetable[0]);
75388acd 1119
eed0fd21
SB		 1120 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1121 cmd |= B43legacy_MACCMD_BEACON0_VALID | B43legacy_MACCMD_BEACON1_VALID;
1122 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
75388acd
LF		 1123}
1124
1125static void b43legacy_refresh_templates(struct b43legacy_wldev *dev,
1126 struct sk_buff *beacon)
1127{
1128 int err;
1129
1130 err = b43legacy_refresh_cached_beacon(dev, beacon);
1131 if (unlikely(err))
1132 return;
1133 b43legacy_update_templates(dev);
1134}
1135
1136static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
1137 const u8 *ssid, u8 ssid_len)
1138{
1139 u32 tmp;
1140 u16 i;
1141 u16 len;
1142
1143 len = min((u16)ssid_len, (u16)0x100);
1144 for (i = 0; i < len; i += sizeof(u32)) {
1145 tmp = (u32)(ssid[i + 0]);
1146 if (i + 1 < len)
1147 tmp |= (u32)(ssid[i + 1]) << 8;
1148 if (i + 2 < len)
1149 tmp |= (u32)(ssid[i + 2]) << 16;
1150 if (i + 3 < len)
1151 tmp |= (u32)(ssid[i + 3]) << 24;
1152 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
1153 0x380 + i, tmp);
1154 }
1155 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1156 0x48, len);
1157}
1158
1159static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1160 u16 beacon_int)
1161{
1162 b43legacy_time_lock(dev);
1163 if (dev->dev->id.revision >= 3)
1164 b43legacy_write32(dev, 0x188, (beacon_int << 16));
1165 else {
1166 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1167 b43legacy_write16(dev, 0x610, beacon_int);
1168 }
1169 b43legacy_time_unlock(dev);
1170}
1171
1172static void handle_irq_beacon(struct b43legacy_wldev *dev)
1173{
1174 u32 status;
1175
1176 if (!b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1177 return;
1178
1179 dev->irq_savedstate &= ~B43legacy_IRQ_BEACON;
e78c9d28 1180 status = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
75388acd
LF		 1181
1182 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1183 /* ACK beacon IRQ. */
1184 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1185 B43legacy_IRQ_BEACON);
1186 dev->irq_savedstate |= B43legacy_IRQ_BEACON;
1187 if (dev->cached_beacon)
1188 kfree_skb(dev->cached_beacon);
1189 dev->cached_beacon = NULL;
1190 return;
1191 }
1192 if (!(status & 0x1)) {
1193 b43legacy_write_beacon_template(dev, 0x68, 0x18,
1194 B43legacy_CCK_RATE_1MB);
1195 status |= 0x1;
e78c9d28 1196 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
75388acd
LF		 1197 status);
1198 }
1199 if (!(status & 0x2)) {
1200 b43legacy_write_beacon_template(dev, 0x468, 0x1A,
1201 B43legacy_CCK_RATE_1MB);
1202 status |= 0x2;
e78c9d28 1203 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
75388acd
LF		 1204 status);
1205 }
1206}
1207
1208static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1209{
1210}
1211
1212/* Interrupt handler bottom-half */
1213static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1214{
1215 u32 reason;
1216 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1217 u32 merged_dma_reason = 0;
1218 int i;
75388acd
LF		 1219 unsigned long flags;
1220
1221 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1222
1223 B43legacy_WARN_ON(b43legacy_status(dev) <
1224 B43legacy_STAT_INITIALIZED);
1225
1226 reason = dev->irq_reason;
1227 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1228 dma_reason[i] = dev->dma_reason[i];
1229 merged_dma_reason |= dma_reason[i];
1230 }
1231
1232 if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1233 b43legacyerr(dev->wl, "MAC transmission error\n");
1234
a293ee99 1235 if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
75388acd 1236 b43legacyerr(dev->wl, "PHY transmission error\n");
a293ee99
SB		 1237 rmb();
1238 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1239 b43legacyerr(dev->wl, "Too many PHY TX errors, "
1240 "restarting the controller\n");
1241 b43legacy_controller_restart(dev, "PHY TX errors");
1242 }
1243 }
75388acd
LF		 1244
1245 if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1246 B43legacy_DMAIRQ_NONFATALMASK))) {
1247 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1248 b43legacyerr(dev->wl, "Fatal DMA error: "
1249 "0x%08X, 0x%08X, 0x%08X, "
1250 "0x%08X, 0x%08X, 0x%08X\n",
1251 dma_reason[0], dma_reason[1],
1252 dma_reason[2], dma_reason[3],
1253 dma_reason[4], dma_reason[5]);
1254 b43legacy_controller_restart(dev, "DMA error");
1255 mmiowb();
1256 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1257 return;
1258 }
1259 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1260 b43legacyerr(dev->wl, "DMA error: "
1261 "0x%08X, 0x%08X, 0x%08X, "
1262 "0x%08X, 0x%08X, 0x%08X\n",
1263 dma_reason[0], dma_reason[1],
1264 dma_reason[2], dma_reason[3],
1265 dma_reason[4], dma_reason[5]);
1266 }
1267
1268 if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1269 handle_irq_ucode_debug(dev);
1270 if (reason & B43legacy_IRQ_TBTT_INDI)
1271 handle_irq_tbtt_indication(dev);
1272 if (reason & B43legacy_IRQ_ATIM_END)
1273 handle_irq_atim_end(dev);
1274 if (reason & B43legacy_IRQ_BEACON)
1275 handle_irq_beacon(dev);
1276 if (reason & B43legacy_IRQ_PMQ)
1277 handle_irq_pmq(dev);
1278 if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1279 ;/*TODO*/
1280 if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1281 handle_irq_noise(dev);
1282
1283 /* Check the DMA reason registers for received data. */
1284 if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1285 if (b43legacy_using_pio(dev))
1286 b43legacy_pio_rx(dev->pio.queue0);
1287 else
1288 b43legacy_dma_rx(dev->dma.rx_ring0);
75388acd
LF		 1289 }
1290 B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1291 B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1292 if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1293 if (b43legacy_using_pio(dev))
1294 b43legacy_pio_rx(dev->pio.queue3);
1295 else
1296 b43legacy_dma_rx(dev->dma.rx_ring3);
75388acd
LF		 1297 }
1298 B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1299 B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1300
ba48f7bb 1301 if (reason & B43legacy_IRQ_TX_OK)
75388acd 1302 handle_irq_transmit_status(dev);
75388acd 1303
75388acd
LF		 1304 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1305 mmiowb();
1306 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1307}
1308
1309static void pio_irq_workaround(struct b43legacy_wldev *dev,
1310 u16 base, int queueidx)
1311{
1312 u16 rxctl;
1313
1314 rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1315 if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1316 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1317 else
1318 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1319}
1320
1321static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1322{
1323 if (b43legacy_using_pio(dev) &&
1324 (dev->dev->id.revision < 3) &&
1325 (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1326 /* Apply a PIO specific workaround to the dma_reasons */
1327 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1328 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1329 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1330 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1331 }
1332
1333 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1334
1335 b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1336 dev->dma_reason[0]);
1337 b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1338 dev->dma_reason[1]);
1339 b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1340 dev->dma_reason[2]);
1341 b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1342 dev->dma_reason[3]);
1343 b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1344 dev->dma_reason[4]);
1345 b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1346 dev->dma_reason[5]);
1347}
1348
1349/* Interrupt handler top-half */
1350static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1351{
1352 irqreturn_t ret = IRQ_NONE;
1353 struct b43legacy_wldev *dev = dev_id;
1354 u32 reason;
1355
1356 if (!dev)
1357 return IRQ_NONE;
1358
1359 spin_lock(&dev->wl->irq_lock);
1360
1361 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
1362 goto out;
1363 reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1364 if (reason == 0xffffffff) /* shared IRQ */
1365 goto out;
1366 ret = IRQ_HANDLED;
1367 reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
1368 if (!reason)
1369 goto out;
1370
1371 dev->dma_reason[0] = b43legacy_read32(dev,
1372 B43legacy_MMIO_DMA0_REASON)
1373 & 0x0001DC00;
1374 dev->dma_reason[1] = b43legacy_read32(dev,
1375 B43legacy_MMIO_DMA1_REASON)
1376 & 0x0000DC00;
1377 dev->dma_reason[2] = b43legacy_read32(dev,
1378 B43legacy_MMIO_DMA2_REASON)
1379 & 0x0000DC00;
1380 dev->dma_reason[3] = b43legacy_read32(dev,
1381 B43legacy_MMIO_DMA3_REASON)
1382 & 0x0001DC00;
1383 dev->dma_reason[4] = b43legacy_read32(dev,
1384 B43legacy_MMIO_DMA4_REASON)
1385 & 0x0000DC00;
1386 dev->dma_reason[5] = b43legacy_read32(dev,
1387 B43legacy_MMIO_DMA5_REASON)
1388 & 0x0000DC00;
1389
1390 b43legacy_interrupt_ack(dev, reason);
1391 /* disable all IRQs. They are enabled again in the bottom half. */
1392 dev->irq_savedstate = b43legacy_interrupt_disable(dev,
1393 B43legacy_IRQ_ALL);
1394 /* save the reason code and call our bottom half. */
1395 dev->irq_reason = reason;
1396 tasklet_schedule(&dev->isr_tasklet);
1397out:
1398 mmiowb();
1399 spin_unlock(&dev->wl->irq_lock);
1400
1401 return ret;
1402}
1403
1404static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1405{
1406 release_firmware(dev->fw.ucode);
1407 dev->fw.ucode = NULL;
1408 release_firmware(dev->fw.pcm);
1409 dev->fw.pcm = NULL;
1410 release_firmware(dev->fw.initvals);
1411 dev->fw.initvals = NULL;
1412 release_firmware(dev->fw.initvals_band);
1413 dev->fw.initvals_band = NULL;
1414}
1415
1416static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1417{
1418 b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
354807e0 1419 "Drivers/b43#devicefirmware "
75388acd
LF		 1420 "and download the correct firmware (version 3).\n");
1421}
1422
1423static int do_request_fw(struct b43legacy_wldev *dev,
1424 const char *name,
1425 const struct firmware **fw)
1426{
1427 char path[sizeof(modparam_fwpostfix) + 32];
1428 struct b43legacy_fw_header *hdr;
1429 u32 size;
1430 int err;
1431
1432 if (!name)
1433 return 0;
1434
1435 snprintf(path, ARRAY_SIZE(path),
1436 "b43legacy%s/%s.fw",
1437 modparam_fwpostfix, name);
1438 err = request_firmware(fw, path, dev->dev->dev);
1439 if (err) {
1440 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1441 "or load failed.\n", path);
1442 return err;
1443 }
1444 if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1445 goto err_format;
1446 hdr = (struct b43legacy_fw_header *)((*fw)->data);
1447 switch (hdr->type) {
1448 case B43legacy_FW_TYPE_UCODE:
1449 case B43legacy_FW_TYPE_PCM:
1450 size = be32_to_cpu(hdr->size);
1451 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1452 goto err_format;
1453 /* fallthrough */
1454 case B43legacy_FW_TYPE_IV:
1455 if (hdr->ver != 1)
1456 goto err_format;
1457 break;
1458 default:
1459 goto err_format;
1460 }
1461
1462 return err;
1463
1464err_format:
1465 b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1466 return -EPROTO;
1467}
1468
1469static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1470{
1471 struct b43legacy_firmware *fw = &dev->fw;
1472 const u8 rev = dev->dev->id.revision;
1473 const char *filename;
1474 u32 tmshigh;
1475 int err;
1476
1477 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1478 if (!fw->ucode) {
1479 if (rev == 2)
1480 filename = "ucode2";
1481 else if (rev == 4)
1482 filename = "ucode4";
1483 else
1484 filename = "ucode5";
1485 err = do_request_fw(dev, filename, &fw->ucode);
1486 if (err)
1487 goto err_load;
1488 }
1489 if (!fw->pcm) {
1490 if (rev < 5)
1491 filename = "pcm4";
1492 else
1493 filename = "pcm5";
1494 err = do_request_fw(dev, filename, &fw->pcm);
1495 if (err)
1496 goto err_load;
1497 }
1498 if (!fw->initvals) {
1499 switch (dev->phy.type) {
1500 case B43legacy_PHYTYPE_G:
1501 if ((rev >= 5) && (rev <= 10))
1502 filename = "b0g0initvals5";
1503 else if (rev == 2 || rev == 4)
1504 filename = "b0g0initvals2";
1505 else
1506 goto err_no_initvals;
1507 break;
1508 default:
1509 goto err_no_initvals;
1510 }
1511 err = do_request_fw(dev, filename, &fw->initvals);
1512 if (err)
1513 goto err_load;
1514 }
1515 if (!fw->initvals_band) {
1516 switch (dev->phy.type) {
1517 case B43legacy_PHYTYPE_G:
1518 if ((rev >= 5) && (rev <= 10))
1519 filename = "b0g0bsinitvals5";
1520 else if (rev >= 11)
1521 filename = NULL;
1522 else if (rev == 2 || rev == 4)
1523 filename = NULL;
1524 else
1525 goto err_no_initvals;
1526 break;
1527 default:
1528 goto err_no_initvals;
1529 }
1530 err = do_request_fw(dev, filename, &fw->initvals_band);
1531 if (err)
1532 goto err_load;
1533 }
1534
1535 return 0;
1536
1537err_load:
1538 b43legacy_print_fw_helptext(dev->wl);
1539 goto error;
1540
1541err_no_initvals:
1542 err = -ENODEV;
1543 b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1544 "core rev %u\n", dev->phy.type, rev);
1545 goto error;
1546
1547error:
1548 b43legacy_release_firmware(dev);
1549 return err;
1550}
1551
1552static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1553{
1554 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1555 const __be32 *data;
1556 unsigned int i;
1557 unsigned int len;
1558 u16 fwrev;
1559 u16 fwpatch;
1560 u16 fwdate;
1561 u16 fwtime;
e78c9d28 1562 u32 tmp, macctl;
75388acd
LF		 1563 int err = 0;
1564
e78c9d28
SB		 1565 /* Jump the microcode PSM to offset 0 */
1566 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1567 B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1568 macctl |= B43legacy_MACCTL_PSM_JMP0;
1569 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1570 /* Zero out all microcode PSM registers and shared memory. */
1571 for (i = 0; i < 64; i++)
1572 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1573 for (i = 0; i < 4096; i += 2)
1574 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1575
75388acd
LF		 1576 /* Upload Microcode. */
1577 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1578 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1579 b43legacy_shm_control_word(dev,
1580 B43legacy_SHM_UCODE |
1581 B43legacy_SHM_AUTOINC_W,
1582 0x0000);
1583 for (i = 0; i < len; i++) {
1584 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1585 be32_to_cpu(data[i]));
1586 udelay(10);
1587 }
1588
1589 if (dev->fw.pcm) {
1590 /* Upload PCM data. */
1591 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1592 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1593 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1594 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1595 /* No need for autoinc bit in SHM_HW */
1596 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1597 for (i = 0; i < len; i++) {
1598 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1599 be32_to_cpu(data[i]));
1600 udelay(10);
1601 }
1602 }
1603
1604 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1605 B43legacy_IRQ_ALL);
e78c9d28
SB		 1606
1607 /* Start the microcode PSM */
1608 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1609 macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1610 macctl |= B43legacy_MACCTL_PSM_RUN;
1611 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 1612
1613 /* Wait for the microcode to load and respond */
1614 i = 0;
1615 while (1) {
1616 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1617 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1618 break;
1619 i++;
1620 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1621 b43legacyerr(dev->wl, "Microcode not responding\n");
1622 b43legacy_print_fw_helptext(dev->wl);
1623 err = -ENODEV;
e78c9d28
SB		 1624 goto error;
1625 }
1626 msleep_interruptible(50);
1627 if (signal_pending(current)) {
1628 err = -EINTR;
1629 goto error;
75388acd 1630 }
75388acd
LF		 1631 }
1632 /* dummy read follows */
1633 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1634
1635 /* Get and check the revisions. */
1636 fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1637 B43legacy_SHM_SH_UCODEREV);
1638 fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1639 B43legacy_SHM_SH_UCODEPATCH);
1640 fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1641 B43legacy_SHM_SH_UCODEDATE);
1642 fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1643 B43legacy_SHM_SH_UCODETIME);
1644
1645 if (fwrev > 0x128) {
1646 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1647 " Only firmware from binary drivers version 3.x"
1648 " is supported. You must change your firmware"
1649 " files.\n");
1650 b43legacy_print_fw_helptext(dev->wl);
75388acd 1651 err = -EOPNOTSUPP;
e78c9d28 1652 goto error;
75388acd 1653 }
cfbc35b6
SB		 1654 b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1655 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1656 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1657 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1658 fwtime & 0x1F);
75388acd
LF		 1659
1660 dev->fw.rev = fwrev;
1661 dev->fw.patch = fwpatch;
1662
e78c9d28
SB		 1663 return 0;
1664
1665error:
1666 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1667 macctl &= ~B43legacy_MACCTL_PSM_RUN;
1668 macctl |= B43legacy_MACCTL_PSM_JMP0;
1669 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1670
75388acd
LF		 1671 return err;
1672}
1673
1674static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1675 const struct b43legacy_iv *ivals,
1676 size_t count,
1677 size_t array_size)
1678{
1679 const struct b43legacy_iv *iv;
1680 u16 offset;
1681 size_t i;
1682 bool bit32;
1683
1684 BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1685 iv = ivals;
1686 for (i = 0; i < count; i++) {
1687 if (array_size < sizeof(iv->offset_size))
1688 goto err_format;
1689 array_size -= sizeof(iv->offset_size);
1690 offset = be16_to_cpu(iv->offset_size);
1691 bit32 = !!(offset & B43legacy_IV_32BIT);
1692 offset &= B43legacy_IV_OFFSET_MASK;
1693 if (offset >= 0x1000)
1694 goto err_format;
1695 if (bit32) {
1696 u32 value;
1697
1698 if (array_size < sizeof(iv->data.d32))
1699 goto err_format;
1700 array_size -= sizeof(iv->data.d32);
1701
1702 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1703 b43legacy_write32(dev, offset, value);
1704
1705 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1706 sizeof(__be16) +
1707 sizeof(__be32));
1708 } else {
1709 u16 value;
1710
1711 if (array_size < sizeof(iv->data.d16))
1712 goto err_format;
1713 array_size -= sizeof(iv->data.d16);
1714
1715 value = be16_to_cpu(iv->data.d16);
1716 b43legacy_write16(dev, offset, value);
1717
1718 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1719 sizeof(__be16) +
1720 sizeof(__be16));
1721 }
1722 }
1723 if (array_size)
1724 goto err_format;
1725
1726 return 0;
1727
1728err_format:
1729 b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1730 b43legacy_print_fw_helptext(dev->wl);
1731
1732 return -EPROTO;
1733}
1734
1735static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1736{
1737 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1738 const struct b43legacy_fw_header *hdr;
1739 struct b43legacy_firmware *fw = &dev->fw;
1740 const struct b43legacy_iv *ivals;
1741 size_t count;
1742 int err;
1743
1744 hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1745 ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1746 count = be32_to_cpu(hdr->size);
1747 err = b43legacy_write_initvals(dev, ivals, count,
1748 fw->initvals->size - hdr_len);
1749 if (err)
1750 goto out;
1751 if (fw->initvals_band) {
1752 hdr = (const struct b43legacy_fw_header *)
1753 (fw->initvals_band->data);
1754 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1755 + hdr_len);
1756 count = be32_to_cpu(hdr->size);
1757 err = b43legacy_write_initvals(dev, ivals, count,
1758 fw->initvals_band->size - hdr_len);
1759 if (err)
1760 goto out;
1761 }
1762out:
1763
1764 return err;
1765}
1766
1767/* Initialize the GPIOs
1768 * http://bcm-specs.sipsolutions.net/GPIO
1769 */
1770static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1771{
1772 struct ssb_bus *bus = dev->dev->bus;
1773 struct ssb_device *gpiodev, *pcidev = NULL;
1774 u32 mask;
1775 u32 set;
1776
e78c9d28 1777 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1778 b43legacy_read32(dev,
e78c9d28 1779 B43legacy_MMIO_MACCTL)
75388acd
LF		 1780 & 0xFFFF3FFF);
1781
75388acd
LF		 1782 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1783 b43legacy_read16(dev,
1784 B43legacy_MMIO_GPIO_MASK)
1785 | 0x000F);
1786
1787 mask = 0x0000001F;
1788 set = 0x0000000F;
1789 if (dev->dev->bus->chip_id == 0x4301) {
1790 mask |= 0x0060;
1791 set |= 0x0060;
1792 }
7797aa38 1793 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
75388acd
LF		 1794 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1795 b43legacy_read16(dev,
1796 B43legacy_MMIO_GPIO_MASK)
1797 | 0x0200);
1798 mask |= 0x0200;
1799 set |= 0x0200;
1800 }
1801 if (dev->dev->id.revision >= 2)
1802 mask |= 0x0010; /* FIXME: This is redundant. */
1803
1804#ifdef CONFIG_SSB_DRIVER_PCICORE
1805 pcidev = bus->pcicore.dev;
1806#endif
1807 gpiodev = bus->chipco.dev ? : pcidev;
1808 if (!gpiodev)
1809 return 0;
1810 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1811 (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1812 & mask) | set);
1813
1814 return 0;
1815}
1816
1817/* Turn off all GPIO stuff. Call this on module unload, for example. */
1818static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1819{
1820 struct ssb_bus *bus = dev->dev->bus;
1821 struct ssb_device *gpiodev, *pcidev = NULL;
1822
1823#ifdef CONFIG_SSB_DRIVER_PCICORE
1824 pcidev = bus->pcicore.dev;
1825#endif
1826 gpiodev = bus->chipco.dev ? : pcidev;
1827 if (!gpiodev)
1828 return;
1829 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1830}
1831
1832/* http://bcm-specs.sipsolutions.net/EnableMac */
1833void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1834{
1835 dev->mac_suspended--;
1836 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1837 B43legacy_WARN_ON(irqs_disabled());
75388acd 1838 if (dev->mac_suspended == 0) {
e78c9d28 1839 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1840 b43legacy_read32(dev,
e78c9d28
SB		 1841 B43legacy_MMIO_MACCTL)
1842 | B43legacy_MACCTL_ENABLED);
75388acd
LF		 1843 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1844 B43legacy_IRQ_MAC_SUSPENDED);
1845 /* the next two are dummy reads */
e78c9d28 1846 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 1847 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1848 b43legacy_power_saving_ctl_bits(dev, -1, -1);
f34eb692
LF		 1849
1850 /* Re-enable IRQs. */
1851 spin_lock_irq(&dev->wl->irq_lock);
1852 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1853 spin_unlock_irq(&dev->wl->irq_lock);
75388acd
LF		 1854 }
1855}
1856
1857/* http://bcm-specs.sipsolutions.net/SuspendMAC */
1858void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1859{
1860 int i;
1861 u32 tmp;
1862
f34eb692
LF		 1863 might_sleep();
1864 B43legacy_WARN_ON(irqs_disabled());
75388acd 1865 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1866
75388acd 1867 if (dev->mac_suspended == 0) {
f34eb692
LF		 1868 /* Mask IRQs before suspending MAC. Otherwise
1869 * the MAC stays busy and won't suspend. */
1870 spin_lock_irq(&dev->wl->irq_lock);
1871 tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
1872 spin_unlock_irq(&dev->wl->irq_lock);
1873 b43legacy_synchronize_irq(dev);
1874 dev->irq_savedstate = tmp;
1875
75388acd 1876 b43legacy_power_saving_ctl_bits(dev, -1, 1);
e78c9d28 1877 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1878 b43legacy_read32(dev,
e78c9d28
SB		 1879 B43legacy_MMIO_MACCTL)
1880 & ~B43legacy_MACCTL_ENABLED);
75388acd 1881 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
f34eb692 1882 for (i = 40; i; i--) {
75388acd
LF		 1883 tmp = b43legacy_read32(dev,
1884 B43legacy_MMIO_GEN_IRQ_REASON);
1885 if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1886 goto out;
f34eb692 1887 msleep(1);
75388acd
LF		 1888 }
1889 b43legacyerr(dev->wl, "MAC suspend failed\n");
1890 }
1891out:
1892 dev->mac_suspended++;
1893}
1894
1895static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1896{
1897 struct b43legacy_wl *wl = dev->wl;
1898 u32 ctl;
1899 u16 cfp_pretbtt;
1900
1901 ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1902 /* Reset status to STA infrastructure mode. */
1903 ctl &= ~B43legacy_MACCTL_AP;
1904 ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1905 ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1906 ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1907 ctl &= ~B43legacy_MACCTL_PROMISC;
4150c572 1908 ctl &= ~B43legacy_MACCTL_BEACPROMISC;
75388acd
LF		 1909 ctl |= B43legacy_MACCTL_INFRA;
1910
4150c572
JB		 1911 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
1912 ctl |= B43legacy_MACCTL_AP;
1913 else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
1914 ctl &= ~B43legacy_MACCTL_INFRA;
1915
1916 if (wl->filter_flags & FIF_CONTROL)
75388acd 1917 ctl |= B43legacy_MACCTL_KEEP_CTL;
4150c572
JB		 1918 if (wl->filter_flags & FIF_FCSFAIL)
1919 ctl |= B43legacy_MACCTL_KEEP_BAD;
1920 if (wl->filter_flags & FIF_PLCPFAIL)
1921 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1922 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
75388acd 1923 ctl |= B43legacy_MACCTL_PROMISC;
4150c572
JB		 1924 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1925 ctl |= B43legacy_MACCTL_BEACPROMISC;
1926
75388acd
LF		 1927 /* Workaround: On old hardware the HW-MAC-address-filter
1928 * doesn't work properly, so always run promisc in filter
1929 * it in software. */
1930 if (dev->dev->id.revision <= 4)
1931 ctl |= B43legacy_MACCTL_PROMISC;
1932
1933 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
1934
1935 cfp_pretbtt = 2;
1936 if ((ctl & B43legacy_MACCTL_INFRA) &&
1937 !(ctl & B43legacy_MACCTL_AP)) {
1938 if (dev->dev->bus->chip_id == 0x4306 &&
1939 dev->dev->bus->chip_rev == 3)
1940 cfp_pretbtt = 100;
1941 else
1942 cfp_pretbtt = 50;
1943 }
1944 b43legacy_write16(dev, 0x612, cfp_pretbtt);
1945}
1946
1947static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
1948 u16 rate,
1949 int is_ofdm)
1950{
1951 u16 offset;
1952
1953 if (is_ofdm) {
1954 offset = 0x480;
1955 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
1956 } else {
1957 offset = 0x4C0;
1958 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
1959 }
1960 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
1961 b43legacy_shm_read16(dev,
1962 B43legacy_SHM_SHARED, offset));
1963}
1964
1965static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
1966{
1967 switch (dev->phy.type) {
1968 case B43legacy_PHYTYPE_G:
1969 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
1970 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
1971 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
1972 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
1973 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
1974 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
1975 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
1976 /* fallthrough */
1977 case B43legacy_PHYTYPE_B:
1978 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
1979 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
1980 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
1981 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
1982 break;
1983 default:
1984 B43legacy_BUG_ON(1);
1985 }
1986}
1987
1988/* Set the TX-Antenna for management frames sent by firmware. */
1989static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
1990 int antenna)
1991{
1992 u16 ant = 0;
1993 u16 tmp;
1994
1995 switch (antenna) {
1996 case B43legacy_ANTENNA0:
1997 ant |= B43legacy_TX4_PHY_ANT0;
1998 break;
1999 case B43legacy_ANTENNA1:
2000 ant |= B43legacy_TX4_PHY_ANT1;
2001 break;
2002 case B43legacy_ANTENNA_AUTO:
2003 ant |= B43legacy_TX4_PHY_ANTLAST;
2004 break;
2005 default:
2006 B43legacy_BUG_ON(1);
2007 }
2008
2009 /* FIXME We also need to set the other flags of the PHY control
2010 * field somewhere. */
2011
2012 /* For Beacons */
2013 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2014 B43legacy_SHM_SH_BEACPHYCTL);
2015 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2016 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2017 B43legacy_SHM_SH_BEACPHYCTL, tmp);
2018 /* For ACK/CTS */
2019 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2020 B43legacy_SHM_SH_ACKCTSPHYCTL);
2021 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2022 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2023 B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2024 /* For Probe Resposes */
2025 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2026 B43legacy_SHM_SH_PRPHYCTL);
2027 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2028 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2029 B43legacy_SHM_SH_PRPHYCTL, tmp);
2030}
2031
2032/* This is the opposite of b43legacy_chip_init() */
2033static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2034{
93bb7f3a 2035 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 2036 b43legacy_gpio_cleanup(dev);
2037 /* firmware is released later */
2038}
2039
2040/* Initialize the chip
2041 * http://bcm-specs.sipsolutions.net/ChipInit
2042 */
2043static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2044{
2045 struct b43legacy_phy *phy = &dev->phy;
2046 int err;
2047 int tmp;
e78c9d28 2048 u32 value32, macctl;
75388acd
LF		 2049 u16 value16;
2050
e78c9d28
SB		 2051 /* Initialize the MAC control */
2052 macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2053 if (dev->phy.gmode)
2054 macctl |= B43legacy_MACCTL_GMODE;
2055 macctl |= B43legacy_MACCTL_INFRA;
2056 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 2057
2058 err = b43legacy_request_firmware(dev);
2059 if (err)
2060 goto out;
2061 err = b43legacy_upload_microcode(dev);
2062 if (err)
2063 goto out; /* firmware is released later */
2064
2065 err = b43legacy_gpio_init(dev);
2066 if (err)
2067 goto out; /* firmware is released later */
ba48f7bb 2068
75388acd
LF		 2069 err = b43legacy_upload_initvals(dev);
2070 if (err)
4ad36d78 2071 goto err_gpio_clean;
75388acd 2072 b43legacy_radio_turn_on(dev);
75388acd
LF		 2073
2074 b43legacy_write16(dev, 0x03E6, 0x0000);
2075 err = b43legacy_phy_init(dev);
2076 if (err)
2077 goto err_radio_off;
2078
2079 /* Select initial Interference Mitigation. */
2080 tmp = phy->interfmode;
2081 phy->interfmode = B43legacy_INTERFMODE_NONE;
2082 b43legacy_radio_set_interference_mitigation(dev, tmp);
2083
2084 b43legacy_phy_set_antenna_diversity(dev);
2085 b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2086
2087 if (phy->type == B43legacy_PHYTYPE_B) {
2088 value16 = b43legacy_read16(dev, 0x005E);
2089 value16 |= 0x0004;
2090 b43legacy_write16(dev, 0x005E, value16);
2091 }
2092 b43legacy_write32(dev, 0x0100, 0x01000000);
2093 if (dev->dev->id.revision < 5)
2094 b43legacy_write32(dev, 0x010C, 0x01000000);
2095
e78c9d28
SB		 2096 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2097 value32 &= ~B43legacy_MACCTL_INFRA;
2098 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2099 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2100 value32 |= B43legacy_MACCTL_INFRA;
2101 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
75388acd 2102
75388acd
LF		 2103 if (b43legacy_using_pio(dev)) {
2104 b43legacy_write32(dev, 0x0210, 0x00000100);
2105 b43legacy_write32(dev, 0x0230, 0x00000100);
2106 b43legacy_write32(dev, 0x0250, 0x00000100);
2107 b43legacy_write32(dev, 0x0270, 0x00000100);
2108 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2109 0x0000);
2110 }
2111
2112 /* Probe Response Timeout value */
2113 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2114 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2115
2116 /* Initially set the wireless operation mode. */
2117 b43legacy_adjust_opmode(dev);
2118
2119 if (dev->dev->id.revision < 3) {
2120 b43legacy_write16(dev, 0x060E, 0x0000);
2121 b43legacy_write16(dev, 0x0610, 0x8000);
2122 b43legacy_write16(dev, 0x0604, 0x0000);
2123 b43legacy_write16(dev, 0x0606, 0x0200);
2124 } else {
2125 b43legacy_write32(dev, 0x0188, 0x80000000);
2126 b43legacy_write32(dev, 0x018C, 0x02000000);
2127 }
2128 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2129 b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2130 b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2131 b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2132 b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2133 b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2134 b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2135
2136 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2137 value32 |= 0x00100000;
2138 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2139
2140 b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2141 dev->dev->bus->chipco.fast_pwrup_delay);
2142
a293ee99
SB		 2143 /* PHY TX errors counter. */
2144 atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2145
75388acd
LF		 2146 B43legacy_WARN_ON(err != 0);
2147 b43legacydbg(dev->wl, "Chip initialized\n");
2148out:
2149 return err;
2150
2151err_radio_off:
93bb7f3a 2152 b43legacy_radio_turn_off(dev, 1);
4ad36d78 2153err_gpio_clean:
75388acd
LF		 2154 b43legacy_gpio_cleanup(dev);
2155 goto out;
2156}
2157
2158static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2159{
2160 struct b43legacy_phy *phy = &dev->phy;
2161
2162 if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2163 return;
2164
2165 b43legacy_mac_suspend(dev);
2166 b43legacy_phy_lo_g_measure(dev);
2167 b43legacy_mac_enable(dev);
2168}
2169
2170static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2171{
2172 b43legacy_phy_lo_mark_all_unused(dev);
7797aa38 2173 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
75388acd
LF		 2174 b43legacy_mac_suspend(dev);
2175 b43legacy_calc_nrssi_slope(dev);
2176 b43legacy_mac_enable(dev);
2177 }
2178}
2179
2180static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2181{
2182 /* Update device statistics. */
2183 b43legacy_calculate_link_quality(dev);
2184}
2185
2186static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2187{
2188 b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
a293ee99
SB		 2189
2190 atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2191 wmb();
75388acd
LF		 2192}
2193
75388acd
LF		 2194static void do_periodic_work(struct b43legacy_wldev *dev)
2195{
2196 unsigned int state;
2197
2198 state = dev->periodic_state;
6be50837 2199 if (state % 8 == 0)
75388acd 2200 b43legacy_periodic_every120sec(dev);
6be50837 2201 if (state % 4 == 0)
75388acd 2202 b43legacy_periodic_every60sec(dev);
6be50837 2203 if (state % 2 == 0)
75388acd 2204 b43legacy_periodic_every30sec(dev);
6be50837 2205 b43legacy_periodic_every15sec(dev);
75388acd
LF		 2206}
2207
f34eb692
LF		 2208/* Periodic work locking policy:
2209 * The whole periodic work handler is protected by
2210 * wl->mutex. If another lock is needed somewhere in the
2211 * pwork callchain, it's aquired in-place, where it's needed.
75388acd 2212 */
75388acd
LF		 2213static void b43legacy_periodic_work_handler(struct work_struct *work)
2214{
f34eb692
LF		 2215 struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2216 periodic_work.work);
2217 struct b43legacy_wl *wl = dev->wl;
75388acd 2218 unsigned long delay;
75388acd 2219
f34eb692 2220 mutex_lock(&wl->mutex);
75388acd
LF		 2221
2222 if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2223 goto out;
2224 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2225 goto out_requeue;
2226
f34eb692 2227 do_periodic_work(dev);
75388acd 2228
75388acd
LF		 2229 dev->periodic_state++;
2230out_requeue:
2231 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2232 delay = msecs_to_jiffies(50);
2233 else
6be50837 2234 delay = round_jiffies_relative(HZ * 15);
f34eb692 2235 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
75388acd 2236out:
f34eb692 2237 mutex_unlock(&wl->mutex);
75388acd
LF		 2238}
2239
2240static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2241{
2242 struct delayed_work *work = &dev->periodic_work;
2243
2244 dev->periodic_state = 0;
2245 INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2246 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2247}
2248
2249/* Validate access to the chip (SHM) */
2250static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2251{
2252 u32 value;
2253 u32 shm_backup;
2254
2255 shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2256 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2257 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2258 0xAA5555AA)
2259 goto error;
2260 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2261 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2262 0x55AAAA55)
2263 goto error;
2264 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2265
2266 value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2267 if ((value | B43legacy_MACCTL_GMODE) !=
2268 (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2269 goto error;
2270
2271 value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2272 if (value)
2273 goto error;
2274
2275 return 0;
2276error:
2277 b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2278 return -ENODEV;
2279}
2280
2281static void b43legacy_security_init(struct b43legacy_wldev *dev)
2282{
2283 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2284 B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2285 dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2286 0x0056);
2287 /* KTP is a word address, but we address SHM bytewise.
2288 * So multiply by two.
2289 */
2290 dev->ktp *= 2;
2291 if (dev->dev->id.revision >= 5)
2292 /* Number of RCMTA address slots */
2293 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2294 dev->max_nr_keys - 8);
2295}
2296
2297static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2298{
2299 struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2300 unsigned long flags;
2301
2302 /* Don't take wl->mutex here, as it could deadlock with
2303 * hwrng internal locking. It's not needed to take
2304 * wl->mutex here, anyway. */
2305
2306 spin_lock_irqsave(&wl->irq_lock, flags);
2307 *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2308 spin_unlock_irqrestore(&wl->irq_lock, flags);
2309
2310 return (sizeof(u16));
2311}
2312
2313static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2314{
2315 if (wl->rng_initialized)
2316 hwrng_unregister(&wl->rng);
2317}
2318
2319static int b43legacy_rng_init(struct b43legacy_wl *wl)
2320{
2321 int err;
2322
2323 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2324 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2325 wl->rng.name = wl->rng_name;
2326 wl->rng.data_read = b43legacy_rng_read;
2327 wl->rng.priv = (unsigned long)wl;
2328 wl->rng_initialized = 1;
2329 err = hwrng_register(&wl->rng);
2330 if (err) {
2331 wl->rng_initialized = 0;
2332 b43legacyerr(wl, "Failed to register the random "
2333 "number generator (%d)\n", err);
2334 }
2335
2336 return err;
2337}
2338
33a3dc93
SB		 2339static int b43legacy_op_tx(struct ieee80211_hw *hw,
2340 struct sk_buff *skb,
2341 struct ieee80211_tx_control *ctl)
75388acd
LF		 2342{
2343 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2344 struct b43legacy_wldev *dev = wl->current_dev;
2345 int err = -ENODEV;
2346 unsigned long flags;
2347
2348 if (unlikely(!dev))
2349 goto out;
2350 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2351 goto out;
2352 /* DMA-TX is done without a global lock. */
2353 if (b43legacy_using_pio(dev)) {
2354 spin_lock_irqsave(&wl->irq_lock, flags);
2355 err = b43legacy_pio_tx(dev, skb, ctl);
2356 spin_unlock_irqrestore(&wl->irq_lock, flags);
2357 } else
2358 err = b43legacy_dma_tx(dev, skb, ctl);
2359out:
2360 if (unlikely(err))
2361 return NETDEV_TX_BUSY;
2362 return NETDEV_TX_OK;
2363}
2364
33a3dc93
SB		 2365static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
2366 int queue,
2367 const struct ieee80211_tx_queue_params *params)
75388acd
LF		 2368{
2369 return 0;
2370}
2371
33a3dc93
SB		 2372static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
2373 struct ieee80211_tx_queue_stats *stats)
75388acd
LF		 2374{
2375 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2376 struct b43legacy_wldev *dev = wl->current_dev;
2377 unsigned long flags;
2378 int err = -ENODEV;
2379
2380 if (!dev)
2381 goto out;
2382 spin_lock_irqsave(&wl->irq_lock, flags);
2383 if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
2384 if (b43legacy_using_pio(dev))
2385 b43legacy_pio_get_tx_stats(dev, stats);
2386 else
2387 b43legacy_dma_get_tx_stats(dev, stats);
2388 err = 0;
2389 }
2390 spin_unlock_irqrestore(&wl->irq_lock, flags);
2391out:
2392 return err;
2393}
2394
33a3dc93
SB		 2395static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2396 struct ieee80211_low_level_stats *stats)
75388acd
LF		 2397{
2398 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2399 unsigned long flags;
2400
2401 spin_lock_irqsave(&wl->irq_lock, flags);
2402 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2403 spin_unlock_irqrestore(&wl->irq_lock, flags);
2404
2405 return 0;
2406}
2407
2408static const char *phymode_to_string(unsigned int phymode)
2409{
2410 switch (phymode) {
2411 case B43legacy_PHYMODE_B:
2412 return "B";
2413 case B43legacy_PHYMODE_G:
2414 return "G";
2415 default:
2416 B43legacy_BUG_ON(1);
2417 }
2418 return "";
2419}
2420
2421static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2422 unsigned int phymode,
2423 struct b43legacy_wldev **dev,
2424 bool *gmode)
2425{
2426 struct b43legacy_wldev *d;
2427
2428 list_for_each_entry(d, &wl->devlist, list) {
2429 if (d->phy.possible_phymodes & phymode) {
2430 /* Ok, this device supports the PHY-mode.
2431 * Set the gmode bit. */
2432 *gmode = 1;
2433 *dev = d;
2434
2435 return 0;
2436 }
2437 }
2438
2439 return -ESRCH;
2440}
2441
2442static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2443{
2444 struct ssb_device *sdev = dev->dev;
2445 u32 tmslow;
2446
2447 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2448 tmslow &= ~B43legacy_TMSLOW_GMODE;
2449 tmslow |= B43legacy_TMSLOW_PHYRESET;
2450 tmslow |= SSB_TMSLOW_FGC;
2451 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2452 msleep(1);
2453
2454 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2455 tmslow &= ~SSB_TMSLOW_FGC;
2456 tmslow |= B43legacy_TMSLOW_PHYRESET;
2457 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2458 msleep(1);
2459}
2460
2461/* Expects wl->mutex locked */
2462static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2463 unsigned int new_mode)
2464{
2465 struct b43legacy_wldev *up_dev;
2466 struct b43legacy_wldev *down_dev;
2467 int err;
2468 bool gmode = 0;
2469 int prev_status;
2470
2471 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2472 if (err) {
2473 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2474 phymode_to_string(new_mode));
2475 return err;
2476 }
2477 if ((up_dev == wl->current_dev) &&
2478 (!!wl->current_dev->phy.gmode == !!gmode))
2479 /* This device is already running. */
2480 return 0;
2481 b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2482 phymode_to_string(new_mode));
2483 down_dev = wl->current_dev;
2484
2485 prev_status = b43legacy_status(down_dev);
2486 /* Shutdown the currently running core. */
2487 if (prev_status >= B43legacy_STAT_STARTED)
2488 b43legacy_wireless_core_stop(down_dev);
2489 if (prev_status >= B43legacy_STAT_INITIALIZED)
2490 b43legacy_wireless_core_exit(down_dev);
2491
2492 if (down_dev != up_dev)
2493 /* We switch to a different core, so we put PHY into
2494 * RESET on the old core. */
2495 b43legacy_put_phy_into_reset(down_dev);
2496
2497 /* Now start the new core. */
2498 up_dev->phy.gmode = gmode;
2499 if (prev_status >= B43legacy_STAT_INITIALIZED) {
2500 err = b43legacy_wireless_core_init(up_dev);
2501 if (err) {
2502 b43legacyerr(wl, "Fatal: Could not initialize device"
2503 " for newly selected %s-PHY mode\n",
2504 phymode_to_string(new_mode));
2505 goto init_failure;
2506 }
2507 }
2508 if (prev_status >= B43legacy_STAT_STARTED) {
2509 err = b43legacy_wireless_core_start(up_dev);
2510 if (err) {
2511 b43legacyerr(wl, "Fatal: Coult not start device for "
2512 "newly selected %s-PHY mode\n",
2513 phymode_to_string(new_mode));
2514 b43legacy_wireless_core_exit(up_dev);
2515 goto init_failure;
2516 }
2517 }
2518 B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2519
2520 b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2521
2522 wl->current_dev = up_dev;
2523
2524 return 0;
2525init_failure:
2526 /* Whoops, failed to init the new core. No core is operating now. */
2527 wl->current_dev = NULL;
2528 return err;
2529}
2530
2531static int b43legacy_antenna_from_ieee80211(u8 antenna)
2532{
2533 switch (antenna) {
2534 case 0: /* default/diversity */
2535 return B43legacy_ANTENNA_DEFAULT;
2536 case 1: /* Antenna 0 */
2537 return B43legacy_ANTENNA0;
2538 case 2: /* Antenna 1 */
2539 return B43legacy_ANTENNA1;
2540 default:
2541 return B43legacy_ANTENNA_DEFAULT;
2542 }
2543}
2544
33a3dc93
SB		 2545static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2546 struct ieee80211_conf *conf)
75388acd
LF		 2547{
2548 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2549 struct b43legacy_wldev *dev;
2550 struct b43legacy_phy *phy;
2551 unsigned long flags;
2552 unsigned int new_phymode = 0xFFFF;
2553 int antenna_tx;
2554 int antenna_rx;
2555 int err = 0;
2556 u32 savedirqs;
2557
2558 antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
2559 antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
2560
2561 mutex_lock(&wl->mutex);
8318d78a
JB		 2562 dev = wl->current_dev;
2563 phy = &dev->phy;
75388acd
LF		 2564
2565 /* Switch the PHY mode (if necessary). */
8318d78a
JB		 2566 switch (conf->channel->band) {
2567 case IEEE80211_BAND_2GHZ:
2568 if (phy->type == B43legacy_PHYTYPE_B)
2569 new_phymode = B43legacy_PHYMODE_B;
2570 else
2571 new_phymode = B43legacy_PHYMODE_G;
75388acd
LF		 2572 break;
2573 default:
2574 B43legacy_WARN_ON(1);
2575 }
2576 err = b43legacy_switch_phymode(wl, new_phymode);
2577 if (err)
2578 goto out_unlock_mutex;
75388acd
LF		 2579
2580 /* Disable IRQs while reconfiguring the device.
2581 * This makes it possible to drop the spinlock throughout
2582 * the reconfiguration process. */
2583 spin_lock_irqsave(&wl->irq_lock, flags);
2584 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2585 spin_unlock_irqrestore(&wl->irq_lock, flags);
2586 goto out_unlock_mutex;
2587 }
2588 savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
2589 spin_unlock_irqrestore(&wl->irq_lock, flags);
2590 b43legacy_synchronize_irq(dev);
2591
2592 /* Switch to the requested channel.
2593 * The firmware takes care of races with the TX handler. */
8318d78a
JB		 2594 if (conf->channel->hw_value != phy->channel)
2595 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
75388acd
LF		 2596
2597 /* Enable/Disable ShortSlot timing. */
2598 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
2599 != dev->short_slot) {
2600 B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
2601 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2602 b43legacy_short_slot_timing_enable(dev);
2603 else
2604 b43legacy_short_slot_timing_disable(dev);
2605 }
2606
5be3bda8
JB		 2607 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2608
75388acd
LF		 2609 /* Adjust the desired TX power level. */
2610 if (conf->power_level != 0) {
2611 if (conf->power_level != phy->power_level) {
2612 phy->power_level = conf->power_level;
2613 b43legacy_phy_xmitpower(dev);
2614 }
2615 }
2616
2617 /* Antennas for RX and management frame TX. */
2618 b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2619
2620 /* Update templates for AP mode. */
2621 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
2622 b43legacy_set_beacon_int(dev, conf->beacon_int);
2623
2624
42a9174f
LF		 2625 if (!!conf->radio_enabled != phy->radio_on) {
2626 if (conf->radio_enabled) {
2627 b43legacy_radio_turn_on(dev);
2628 b43legacyinfo(dev->wl, "Radio turned on by software\n");
2629 if (!dev->radio_hw_enable)
2630 b43legacyinfo(dev->wl, "The hardware RF-kill"
2631 " button still turns the radio"
2632 " physically off. Press the"
2633 " button to turn it on.\n");
2634 } else {
93bb7f3a 2635 b43legacy_radio_turn_off(dev, 0);
42a9174f
LF		 2636 b43legacyinfo(dev->wl, "Radio turned off by"
2637 " software\n");
2638 }
2639 }
2640
75388acd
LF		 2641 spin_lock_irqsave(&wl->irq_lock, flags);
2642 b43legacy_interrupt_enable(dev, savedirqs);
2643 mmiowb();
2644 spin_unlock_irqrestore(&wl->irq_lock, flags);
2645out_unlock_mutex:
2646 mutex_unlock(&wl->mutex);
2647
2648 return err;
2649}
2650
33a3dc93
SB		 2651static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2652 unsigned int changed,
2653 unsigned int *fflags,
2654 int mc_count,
2655 struct dev_addr_list *mc_list)
75388acd
LF		 2656{
2657 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2658 struct b43legacy_wldev *dev = wl->current_dev;
2659 unsigned long flags;
2660
4150c572
JB		 2661 if (!dev) {
2662 *fflags = 0;
75388acd 2663 return;
75388acd 2664 }
4150c572
JB		 2665
2666 spin_lock_irqsave(&wl->irq_lock, flags);
2667 *fflags &= FIF_PROMISC_IN_BSS |
2668 FIF_ALLMULTI |
2669 FIF_FCSFAIL |
2670 FIF_PLCPFAIL |
2671 FIF_CONTROL |
2672 FIF_OTHER_BSS |
2673 FIF_BCN_PRBRESP_PROMISC;
2674
2675 changed &= FIF_PROMISC_IN_BSS |
2676 FIF_ALLMULTI |
2677 FIF_FCSFAIL |
2678 FIF_PLCPFAIL |
2679 FIF_CONTROL |
2680 FIF_OTHER_BSS |
2681 FIF_BCN_PRBRESP_PROMISC;
2682
2683 wl->filter_flags = *fflags;
2684
2685 if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2686 b43legacy_adjust_opmode(dev);
75388acd
LF		 2687 spin_unlock_irqrestore(&wl->irq_lock, flags);
2688}
2689
33a3dc93 2690static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 2691 struct ieee80211_vif *vif,
33a3dc93 2692 struct ieee80211_if_conf *conf)
75388acd
LF		 2693{
2694 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2695 struct b43legacy_wldev *dev = wl->current_dev;
2696 unsigned long flags;
2697
2698 if (!dev)
2699 return -ENODEV;
2700 mutex_lock(&wl->mutex);
2701 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 2702 B43legacy_WARN_ON(wl->vif != vif);
4150c572
JB		 2703 if (conf->bssid)
2704 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2705 else
2706 memset(wl->bssid, 0, ETH_ALEN);
2707 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2708 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2709 B43legacy_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2710 b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
2711 if (conf->beacon)
2712 b43legacy_refresh_templates(dev, conf->beacon);
75388acd 2713 }
4150c572 2714 b43legacy_write_mac_bssid_templates(dev);
75388acd
LF		 2715 }
2716 spin_unlock_irqrestore(&wl->irq_lock, flags);
2717 mutex_unlock(&wl->mutex);
2718
2719 return 0;
2720}
2721
2722/* Locking: wl->mutex */
2723static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2724{
2725 struct b43legacy_wl *wl = dev->wl;
2726 unsigned long flags;
2727
2728 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2729 return;
440cb58a
SB		 2730
2731 /* Disable and sync interrupts. We must do this before than
2732 * setting the status to INITIALIZED, as the interrupt handler
2733 * won't care about IRQs then. */
2734 spin_lock_irqsave(&wl->irq_lock, flags);
2735 dev->irq_savedstate = b43legacy_interrupt_disable(dev,
2736 B43legacy_IRQ_ALL);
2737 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2738 spin_unlock_irqrestore(&wl->irq_lock, flags);
2739 b43legacy_synchronize_irq(dev);
2740
75388acd
LF		 2741 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2742
2743 mutex_unlock(&wl->mutex);
2744 /* Must unlock as it would otherwise deadlock. No races here.
2745 * Cancel the possibly running self-rearming periodic work. */
2746 cancel_delayed_work_sync(&dev->periodic_work);
2747 mutex_lock(&wl->mutex);
2748
2749 ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2750
75388acd
LF		 2751 b43legacy_mac_suspend(dev);
2752 free_irq(dev->dev->irq, dev);
2753 b43legacydbg(wl, "Wireless interface stopped\n");
2754}
2755
2756/* Locking: wl->mutex */
2757static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2758{
2759 int err;
2760
2761 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2762
2763 drain_txstatus_queue(dev);
2764 err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2765 IRQF_SHARED, KBUILD_MODNAME, dev);
2766 if (err) {
2767 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2768 dev->dev->irq);
2769 goto out;
2770 }
2771 /* We are ready to run. */
2772 b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2773
2774 /* Start data flow (TX/RX) */
2775 b43legacy_mac_enable(dev);
2776 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
2777 ieee80211_start_queues(dev->wl->hw);
2778
2779 /* Start maintenance work */
2780 b43legacy_periodic_tasks_setup(dev);
2781
2782 b43legacydbg(dev->wl, "Wireless interface started\n");
2783out:
2784 return err;
2785}
2786
2787/* Get PHY and RADIO versioning numbers */
2788static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2789{
2790 struct b43legacy_phy *phy = &dev->phy;
2791 u32 tmp;
2792 u8 analog_type;
2793 u8 phy_type;
2794 u8 phy_rev;
2795 u16 radio_manuf;
2796 u16 radio_ver;
2797 u16 radio_rev;
2798 int unsupported = 0;
2799
2800 /* Get PHY versioning */
2801 tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2802 analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2803 >> B43legacy_PHYVER_ANALOG_SHIFT;
2804 phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2805 phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2806 switch (phy_type) {
2807 case B43legacy_PHYTYPE_B:
2808 if (phy_rev != 2 && phy_rev != 4
2809 && phy_rev != 6 && phy_rev != 7)
2810 unsupported = 1;
2811 break;
2812 case B43legacy_PHYTYPE_G:
2813 if (phy_rev > 8)
2814 unsupported = 1;
2815 break;
2816 default:
2817 unsupported = 1;
2818 };
2819 if (unsupported) {
2820 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2821 "(Analog %u, Type %u, Revision %u)\n",
2822 analog_type, phy_type, phy_rev);
2823 return -EOPNOTSUPP;
2824 }
2825 b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2826 analog_type, phy_type, phy_rev);
2827
2828
2829 /* Get RADIO versioning */
2830 if (dev->dev->bus->chip_id == 0x4317) {
2831 if (dev->dev->bus->chip_rev == 0)
2832 tmp = 0x3205017F;
2833 else if (dev->dev->bus->chip_rev == 1)
2834 tmp = 0x4205017F;
2835 else
2836 tmp = 0x5205017F;
2837 } else {
2838 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2839 B43legacy_RADIOCTL_ID);
2840 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2841 tmp <<= 16;
2842 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2843 B43legacy_RADIOCTL_ID);
2844 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2845 }
2846 radio_manuf = (tmp & 0x00000FFF);
2847 radio_ver = (tmp & 0x0FFFF000) >> 12;
2848 radio_rev = (tmp & 0xF0000000) >> 28;
2849 switch (phy_type) {
2850 case B43legacy_PHYTYPE_B:
2851 if ((radio_ver & 0xFFF0) != 0x2050)
2852 unsupported = 1;
2853 break;
2854 case B43legacy_PHYTYPE_G:
2855 if (radio_ver != 0x2050)
2856 unsupported = 1;
2857 break;
2858 default:
2859 B43legacy_BUG_ON(1);
2860 }
2861 if (unsupported) {
2862 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
2863 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
2864 radio_manuf, radio_ver, radio_rev);
2865 return -EOPNOTSUPP;
2866 }
2867 b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
2868 " Revision %u\n", radio_manuf, radio_ver, radio_rev);
2869
2870
2871 phy->radio_manuf = radio_manuf;
2872 phy->radio_ver = radio_ver;
2873 phy->radio_rev = radio_rev;
2874
2875 phy->analog = analog_type;
2876 phy->type = phy_type;
2877 phy->rev = phy_rev;
2878
2879 return 0;
2880}
2881
2882static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
2883 struct b43legacy_phy *phy)
2884{
2885 struct b43legacy_lopair *lo;
2886 int i;
2887
2888 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
2889 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
2890
1065de15
LF		 2891 /* Assume the radio is enabled. If it's not enabled, the state will
2892 * immediately get fixed on the first periodic work run. */
2893 dev->radio_hw_enable = 1;
75388acd
LF		 2894
2895 phy->savedpctlreg = 0xFFFF;
2896 phy->aci_enable = 0;
2897 phy->aci_wlan_automatic = 0;
2898 phy->aci_hw_rssi = 0;
2899
2900 lo = phy->_lo_pairs;
2901 if (lo)
2902 memset(lo, 0, sizeof(struct b43legacy_lopair) *
2903 B43legacy_LO_COUNT);
2904 phy->max_lb_gain = 0;
2905 phy->trsw_rx_gain = 0;
2906
2907 /* Set default attenuation values. */
2908 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
2909 phy->rfatt = b43legacy_default_radio_attenuation(dev);
2910 phy->txctl1 = b43legacy_default_txctl1(dev);
2911 phy->txpwr_offset = 0;
2912
2913 /* NRSSI */
2914 phy->nrssislope = 0;
2915 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
2916 phy->nrssi[i] = -1000;
2917 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
2918 phy->nrssi_lt[i] = i;
2919
2920 phy->lofcal = 0xFFFF;
2921 phy->initval = 0xFFFF;
2922
75388acd
LF		 2923 phy->interfmode = B43legacy_INTERFMODE_NONE;
2924 phy->channel = 0xFF;
2925}
2926
2927static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
2928{
2929 /* Flags */
eed0fd21 2930 dev->dfq_valid = 0;
75388acd
LF		 2931
2932 /* Stats */
2933 memset(&dev->stats, 0, sizeof(dev->stats));
2934
2935 setup_struct_phy_for_init(dev, &dev->phy);
2936
2937 /* IRQ related flags */
2938 dev->irq_reason = 0;
2939 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
2940 dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
2941
2942 dev->mac_suspended = 1;
2943
2944 /* Noise calculation context */
2945 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
2946}
2947
2948static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
2949{
2950#ifdef CONFIG_SSB_DRIVER_PCICORE
2951 struct ssb_bus *bus = dev->dev->bus;
2952 u32 tmp;
2953
2954 if (bus->pcicore.dev &&
2955 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
2956 bus->pcicore.dev->id.revision <= 5) {
2957 /* IMCFGLO timeouts workaround. */
2958 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
2959 tmp &= ~SSB_IMCFGLO_REQTO;
2960 tmp &= ~SSB_IMCFGLO_SERTO;
2961 switch (bus->bustype) {
2962 case SSB_BUSTYPE_PCI:
2963 case SSB_BUSTYPE_PCMCIA:
2964 tmp |= 0x32;
2965 break;
2966 case SSB_BUSTYPE_SSB:
2967 tmp |= 0x53;
2968 break;
2969 }
2970 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
2971 }
2972#endif /* CONFIG_SSB_DRIVER_PCICORE */
2973}
2974
0a6e1bee
SB		 2975/* Write the short and long frame retry limit values. */
2976static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2977 unsigned int short_retry,
2978 unsigned int long_retry)
2979{
2980 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2981 * the chip-internal counter. */
2982 short_retry = min(short_retry, (unsigned int)0xF);
2983 long_retry = min(long_retry, (unsigned int)0xF);
2984
2985 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2986 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2987}
2988
75388acd
LF		 2989/* Shutdown a wireless core */
2990/* Locking: wl->mutex */
2991static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
2992{
2993 struct b43legacy_wl *wl = dev->wl;
2994 struct b43legacy_phy *phy = &dev->phy;
e78c9d28 2995 u32 macctl;
75388acd
LF		 2996
2997 B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
2998 if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
2999 return;
3000 b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3001
e78c9d28
SB		 3002 /* Stop the microcode PSM. */
3003 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3004 macctl &= ~B43legacy_MACCTL_PSM_RUN;
3005 macctl |= B43legacy_MACCTL_PSM_JMP0;
3006 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3007
75388acd
LF		 3008 mutex_unlock(&wl->mutex);
3009 /* Must unlock as it would otherwise deadlock. No races here.
3010 * Cancel possibly pending workqueues. */
3011 cancel_work_sync(&dev->restart_work);
3012 mutex_lock(&wl->mutex);
3013
4ad36d78 3014 b43legacy_leds_exit(dev);
75388acd
LF		 3015 b43legacy_rng_exit(dev->wl);
3016 b43legacy_pio_free(dev);
3017 b43legacy_dma_free(dev);
3018 b43legacy_chip_exit(dev);
93bb7f3a 3019 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3020 b43legacy_switch_analog(dev, 0);
3021 if (phy->dyn_tssi_tbl)
3022 kfree(phy->tssi2dbm);
3023 kfree(phy->lo_control);
3024 phy->lo_control = NULL;
3025 ssb_device_disable(dev->dev, 0);
3026 ssb_bus_may_powerdown(dev->dev->bus);
3027}
3028
3029static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3030{
3031 struct b43legacy_phy *phy = &dev->phy;
3032 int i;
3033
3034 /* Set default attenuation values. */
3035 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3036 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3037 phy->txctl1 = b43legacy_default_txctl1(dev);
3038 phy->txctl2 = 0xFFFF;
3039 phy->txpwr_offset = 0;
3040
3041 /* NRSSI */
3042 phy->nrssislope = 0;
3043 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3044 phy->nrssi[i] = -1000;
3045 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3046 phy->nrssi_lt[i] = i;
3047
3048 phy->lofcal = 0xFFFF;
3049 phy->initval = 0xFFFF;
3050
3051 phy->aci_enable = 0;
3052 phy->aci_wlan_automatic = 0;
3053 phy->aci_hw_rssi = 0;
3054
3055 phy->antenna_diversity = 0xFFFF;
3056 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3057 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3058
3059 /* Flags */
3060 phy->calibrated = 0;
75388acd
LF		 3061
3062 if (phy->_lo_pairs)
3063 memset(phy->_lo_pairs, 0,
3064 sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3065 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3066}
3067
3068/* Initialize a wireless core */
3069static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3070{
3071 struct b43legacy_wl *wl = dev->wl;
3072 struct ssb_bus *bus = dev->dev->bus;
3073 struct b43legacy_phy *phy = &dev->phy;
3074 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3075 int err;
3076 u32 hf;
3077 u32 tmp;
3078
3079 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3080
3081 err = ssb_bus_powerup(bus, 0);
3082 if (err)
3083 goto out;
3084 if (!ssb_device_is_enabled(dev->dev)) {
3085 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3086 b43legacy_wireless_core_reset(dev, tmp);
3087 }
3088
3089 if ((phy->type == B43legacy_PHYTYPE_B) ||
3090 (phy->type == B43legacy_PHYTYPE_G)) {
3091 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3092 * B43legacy_LO_COUNT,
3093 GFP_KERNEL);
3094 if (!phy->_lo_pairs)
3095 return -ENOMEM;
3096 }
3097 setup_struct_wldev_for_init(dev);
3098
3099 err = b43legacy_phy_init_tssi2dbm_table(dev);
3100 if (err)
3101 goto err_kfree_lo_control;
3102
3103 /* Enable IRQ routing to this device. */
3104 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3105
3106 b43legacy_imcfglo_timeouts_workaround(dev);
3107 prepare_phy_data_for_init(dev);
3108 b43legacy_phy_calibrate(dev);
3109 err = b43legacy_chip_init(dev);
3110 if (err)
3111 goto err_kfree_tssitbl;
3112 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3113 B43legacy_SHM_SH_WLCOREREV,
3114 dev->dev->id.revision);
3115 hf = b43legacy_hf_read(dev);
3116 if (phy->type == B43legacy_PHYTYPE_G) {
3117 hf |= B43legacy_HF_SYMW;
3118 if (phy->rev == 1)
3119 hf |= B43legacy_HF_GDCW;
7797aa38 3120 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
75388acd
LF		 3121 hf |= B43legacy_HF_OFDMPABOOST;
3122 } else if (phy->type == B43legacy_PHYTYPE_B) {
3123 hf |= B43legacy_HF_SYMW;
3124 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3125 hf &= ~B43legacy_HF_GDCW;
3126 }
3127 b43legacy_hf_write(dev, hf);
3128
0a6e1bee
SB		 3129 b43legacy_set_retry_limits(dev,
3130 B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3131 B43legacy_DEFAULT_LONG_RETRY_LIMIT);
75388acd
LF		 3132
3133 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3134 0x0044, 3);
3135 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3136 0x0046, 2);
3137
3138 /* Disable sending probe responses from firmware.
3139 * Setting the MaxTime to one usec will always trigger
3140 * a timeout, so we never send any probe resp.
3141 * A timeout of zero is infinite. */
3142 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3143 B43legacy_SHM_SH_PRMAXTIME, 1);
3144
3145 b43legacy_rate_memory_init(dev);
3146
3147 /* Minimum Contention Window */
3148 if (phy->type == B43legacy_PHYTYPE_B)
3149 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3150 0x0003, 31);
3151 else
3152 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3153 0x0003, 15);
3154 /* Maximum Contention Window */
3155 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3156 0x0004, 1023);
3157
3158 do {
3159 if (b43legacy_using_pio(dev))
3160 err = b43legacy_pio_init(dev);
3161 else {
3162 err = b43legacy_dma_init(dev);
3163 if (!err)
3164 b43legacy_qos_init(dev);
3165 }
3166 } while (err == -EAGAIN);
3167 if (err)
3168 goto err_chip_exit;
3169
3170 b43legacy_write16(dev, 0x0612, 0x0050);
3171 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0416, 0x0050);
3172 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0414, 0x01F4);
3173
3174 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 3175 b43legacy_upload_card_macaddress(dev);
75388acd
LF		 3176 b43legacy_security_init(dev);
3177 b43legacy_rng_init(wl);
3178
3179 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3180
4ad36d78 3181 b43legacy_leds_init(dev);
75388acd
LF		 3182out:
3183 return err;
3184
3185err_chip_exit:
3186 b43legacy_chip_exit(dev);
3187err_kfree_tssitbl:
3188 if (phy->dyn_tssi_tbl)
3189 kfree(phy->tssi2dbm);
3190err_kfree_lo_control:
3191 kfree(phy->lo_control);
3192 phy->lo_control = NULL;
3193 ssb_bus_may_powerdown(bus);
3194 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3195 return err;
3196}
3197
33a3dc93
SB		 3198static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3199 struct ieee80211_if_init_conf *conf)
75388acd
LF		 3200{
3201 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3202 struct b43legacy_wldev *dev;
3203 unsigned long flags;
3204 int err = -EOPNOTSUPP;
4150c572
JB		 3205
3206 /* TODO: allow WDS/AP devices to coexist */
3207
3208 if (conf->type != IEEE80211_IF_TYPE_AP &&
3209 conf->type != IEEE80211_IF_TYPE_STA &&
3210 conf->type != IEEE80211_IF_TYPE_WDS &&
3211 conf->type != IEEE80211_IF_TYPE_IBSS)
3212 return -EOPNOTSUPP;
75388acd
LF		 3213
3214 mutex_lock(&wl->mutex);
4150c572 3215 if (wl->operating)
75388acd
LF		 3216 goto out_mutex_unlock;
3217
3218 b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
3219
3220 dev = wl->current_dev;
4150c572 3221 wl->operating = 1;
32bfd35d 3222 wl->vif = conf->vif;
4150c572
JB		 3223 wl->if_type = conf->type;
3224 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3225
3226 spin_lock_irqsave(&wl->irq_lock, flags);
3227 b43legacy_adjust_opmode(dev);
3228 b43legacy_upload_card_macaddress(dev);
3229 spin_unlock_irqrestore(&wl->irq_lock, flags);
3230
3231 err = 0;
3232 out_mutex_unlock:
3233 mutex_unlock(&wl->mutex);
3234
3235 return err;
3236}
3237
33a3dc93
SB		 3238static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3239 struct ieee80211_if_init_conf *conf)
4150c572
JB		 3240{
3241 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3242 struct b43legacy_wldev *dev = wl->current_dev;
3243 unsigned long flags;
3244
3245 b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
3246
3247 mutex_lock(&wl->mutex);
3248
3249 B43legacy_WARN_ON(!wl->operating);
32bfd35d
JB		 3250 B43legacy_WARN_ON(wl->vif != conf->vif);
3251 wl->vif = NULL;
4150c572
JB		 3252
3253 wl->operating = 0;
3254
3255 spin_lock_irqsave(&wl->irq_lock, flags);
3256 b43legacy_adjust_opmode(dev);
3257 memset(wl->mac_addr, 0, ETH_ALEN);
3258 b43legacy_upload_card_macaddress(dev);
3259 spin_unlock_irqrestore(&wl->irq_lock, flags);
3260
3261 mutex_unlock(&wl->mutex);
3262}
3263
33a3dc93 3264static int b43legacy_op_start(struct ieee80211_hw *hw)
4150c572
JB		 3265{
3266 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3267 struct b43legacy_wldev *dev = wl->current_dev;
3268 int did_init = 0;
208eec88 3269 int err = 0;
8712f276 3270 bool do_rfkill_exit = 0;
4150c572 3271
4ad36d78
LF		 3272 /* First register RFkill.
3273 * LEDs that are registered later depend on it. */
3274 b43legacy_rfkill_init(dev);
3275
ada50731
SB		 3276 /* Kill all old instance specific information to make sure
3277 * the card won't use it in the short timeframe between start
3278 * and mac80211 reconfiguring it. */
3279 memset(wl->bssid, 0, ETH_ALEN);
3280 memset(wl->mac_addr, 0, ETH_ALEN);
3281 wl->filter_flags = 0;
3282
4150c572
JB		 3283 mutex_lock(&wl->mutex);
3284
75388acd
LF		 3285 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3286 err = b43legacy_wireless_core_init(dev);
8712f276
MB		 3287 if (err) {
3288 do_rfkill_exit = 1;
75388acd 3289 goto out_mutex_unlock;
8712f276 3290 }
75388acd
LF		 3291 did_init = 1;
3292 }
4150c572 3293
75388acd
LF		 3294 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3295 err = b43legacy_wireless_core_start(dev);
3296 if (err) {
3297 if (did_init)
3298 b43legacy_wireless_core_exit(dev);
8712f276 3299 do_rfkill_exit = 1;
75388acd
LF		 3300 goto out_mutex_unlock;
3301 }
3302 }
3303
75388acd
LF		 3304out_mutex_unlock:
3305 mutex_unlock(&wl->mutex);
3306
8712f276
MB		 3307 if (do_rfkill_exit)
3308 b43legacy_rfkill_exit(dev);
3309
75388acd
LF		 3310 return err;
3311}
3312
33a3dc93 3313static void b43legacy_op_stop(struct ieee80211_hw *hw)
75388acd
LF		 3314{
3315 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
4150c572 3316 struct b43legacy_wldev *dev = wl->current_dev;
75388acd 3317
4ad36d78
LF		 3318 b43legacy_rfkill_exit(dev);
3319
75388acd 3320 mutex_lock(&wl->mutex);
4150c572
JB		 3321 if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3322 b43legacy_wireless_core_stop(dev);
3323 b43legacy_wireless_core_exit(dev);
75388acd
LF		 3324 mutex_unlock(&wl->mutex);
3325}
3326
0a6e1bee
SB		 3327static int b43legacy_op_set_retry_limit(struct ieee80211_hw *hw,
3328 u32 short_retry_limit,
3329 u32 long_retry_limit)
3330{
3331 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3332 struct b43legacy_wldev *dev;
3333 int err = 0;
3334
3335 mutex_lock(&wl->mutex);
3336 dev = wl->current_dev;
3337 if (unlikely(!dev ||
3338 (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED))) {
3339 err = -ENODEV;
3340 goto out_unlock;
3341 }
3342 b43legacy_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3343out_unlock:
3344 mutex_unlock(&wl->mutex);
3345
3346 return err;
3347}
75388acd
LF		 3348
3349static const struct ieee80211_ops b43legacy_hw_ops = {
33a3dc93
SB		 3350 .tx = b43legacy_op_tx,
3351 .conf_tx = b43legacy_op_conf_tx,
3352 .add_interface = b43legacy_op_add_interface,
3353 .remove_interface = b43legacy_op_remove_interface,
3354 .config = b43legacy_op_dev_config,
3355 .config_interface = b43legacy_op_config_interface,
3356 .configure_filter = b43legacy_op_configure_filter,
3357 .get_stats = b43legacy_op_get_stats,
3358 .get_tx_stats = b43legacy_op_get_tx_stats,
3359 .start = b43legacy_op_start,
3360 .stop = b43legacy_op_stop,
0a6e1bee 3361 .set_retry_limit = b43legacy_op_set_retry_limit,
75388acd
LF		 3362};
3363
3364/* Hard-reset the chip. Do not call this directly.
3365 * Use b43legacy_controller_restart()
3366 */
3367static void b43legacy_chip_reset(struct work_struct *work)
3368{
3369 struct b43legacy_wldev *dev =
3370 container_of(work, struct b43legacy_wldev, restart_work);
3371 struct b43legacy_wl *wl = dev->wl;
3372 int err = 0;
3373 int prev_status;
3374
3375 mutex_lock(&wl->mutex);
3376
3377 prev_status = b43legacy_status(dev);
3378 /* Bring the device down... */
3379 if (prev_status >= B43legacy_STAT_STARTED)
3380 b43legacy_wireless_core_stop(dev);
3381 if (prev_status >= B43legacy_STAT_INITIALIZED)
3382 b43legacy_wireless_core_exit(dev);
3383
3384 /* ...and up again. */
3385 if (prev_status >= B43legacy_STAT_INITIALIZED) {
3386 err = b43legacy_wireless_core_init(dev);
3387 if (err)
3388 goto out;
3389 }
3390 if (prev_status >= B43legacy_STAT_STARTED) {
3391 err = b43legacy_wireless_core_start(dev);
3392 if (err) {
3393 b43legacy_wireless_core_exit(dev);
3394 goto out;
3395 }
3396 }
3397out:
3398 mutex_unlock(&wl->mutex);
3399 if (err)
3400 b43legacyerr(wl, "Controller restart FAILED\n");
3401 else
3402 b43legacyinfo(wl, "Controller restarted\n");
3403}
3404
3405static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3406 int have_bphy,
3407 int have_gphy)
3408{
3409 struct ieee80211_hw *hw = dev->wl->hw;
75388acd 3410 struct b43legacy_phy *phy = &dev->phy;
75388acd
LF		 3411
3412 phy->possible_phymodes = 0;
8318d78a
JB		 3413 if (have_bphy) {
3414 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3415 &b43legacy_band_2GHz_BPHY;
3416 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3417 }
3418
3419 if (have_gphy) {
3420 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3421 &b43legacy_band_2GHz_GPHY;
3422 phy->possible_phymodes |= B43legacy_PHYMODE_G;
75388acd
LF		 3423 }
3424
3425 return 0;
3426}
3427
3428static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3429{
3430 /* We release firmware that late to not be required to re-request
3431 * is all the time when we reinit the core. */
3432 b43legacy_release_firmware(dev);
3433}
3434
3435static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3436{
3437 struct b43legacy_wl *wl = dev->wl;
3438 struct ssb_bus *bus = dev->dev->bus;
3439 struct pci_dev *pdev = bus->host_pci;
3440 int err;
3441 int have_bphy = 0;
3442 int have_gphy = 0;
3443 u32 tmp;
3444
3445 /* Do NOT do any device initialization here.
3446 * Do it in wireless_core_init() instead.
3447 * This function is for gathering basic information about the HW, only.
3448 * Also some structs may be set up here. But most likely you want to
3449 * have that in core_init(), too.
3450 */
3451
3452 err = ssb_bus_powerup(bus, 0);
3453 if (err) {
3454 b43legacyerr(wl, "Bus powerup failed\n");
3455 goto out;
3456 }
3457 /* Get the PHY type. */
3458 if (dev->dev->id.revision >= 5) {
3459 u32 tmshigh;
3460
3461 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3462 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3463 if (!have_gphy)
3464 have_bphy = 1;
3465 } else if (dev->dev->id.revision == 4)
3466 have_gphy = 1;
3467 else
3468 have_bphy = 1;
3469
75388acd
LF		 3470 dev->phy.gmode = (have_gphy || have_bphy);
3471 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3472 b43legacy_wireless_core_reset(dev, tmp);
3473
3474 err = b43legacy_phy_versioning(dev);
3475 if (err)
ba48f7bb 3476 goto err_powerdown;
75388acd
LF		 3477 /* Check if this device supports multiband. */
3478 if (!pdev ||
3479 (pdev->device != 0x4312 &&
3480 pdev->device != 0x4319 &&
3481 pdev->device != 0x4324)) {
3482 /* No multiband support. */
3483 have_bphy = 0;
3484 have_gphy = 0;
3485 switch (dev->phy.type) {
3486 case B43legacy_PHYTYPE_B:
3487 have_bphy = 1;
3488 break;
3489 case B43legacy_PHYTYPE_G:
3490 have_gphy = 1;
3491 break;
3492 default:
3493 B43legacy_BUG_ON(1);
3494 }
3495 }
3496 dev->phy.gmode = (have_gphy || have_bphy);
3497 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3498 b43legacy_wireless_core_reset(dev, tmp);
3499
3500 err = b43legacy_validate_chipaccess(dev);
3501 if (err)
ba48f7bb 3502 goto err_powerdown;
75388acd
LF		 3503 err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3504 if (err)
ba48f7bb 3505 goto err_powerdown;
75388acd
LF		 3506
3507 /* Now set some default "current_dev" */
3508 if (!wl->current_dev)
3509 wl->current_dev = dev;
3510 INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3511
93bb7f3a 3512 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3513 b43legacy_switch_analog(dev, 0);
3514 ssb_device_disable(dev->dev, 0);
3515 ssb_bus_may_powerdown(bus);
3516
3517out:
3518 return err;
3519
75388acd
LF		 3520err_powerdown:
3521 ssb_bus_may_powerdown(bus);
3522 return err;
3523}
3524
3525static void b43legacy_one_core_detach(struct ssb_device *dev)
3526{
3527 struct b43legacy_wldev *wldev;
3528 struct b43legacy_wl *wl;
3529
3530 wldev = ssb_get_drvdata(dev);
3531 wl = wldev->wl;
3532 cancel_work_sync(&wldev->restart_work);
3533 b43legacy_debugfs_remove_device(wldev);
3534 b43legacy_wireless_core_detach(wldev);
3535 list_del(&wldev->list);
3536 wl->nr_devs--;
3537 ssb_set_drvdata(dev, NULL);
3538 kfree(wldev);
3539}
3540
3541static int b43legacy_one_core_attach(struct ssb_device *dev,
3542 struct b43legacy_wl *wl)
3543{
3544 struct b43legacy_wldev *wldev;
3545 struct pci_dev *pdev;
3546 int err = -ENOMEM;
3547
3548 if (!list_empty(&wl->devlist)) {
3549 /* We are not the first core on this chip. */
3550 pdev = dev->bus->host_pci;
3551 /* Only special chips support more than one wireless
3552 * core, although some of the other chips have more than
3553 * one wireless core as well. Check for this and
3554 * bail out early.
3555 */
3556 if (!pdev ||
3557 ((pdev->device != 0x4321) &&
3558 (pdev->device != 0x4313) &&
3559 (pdev->device != 0x431A))) {
3560 b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
3561 return -ENODEV;
3562 }
3563 }
3564
3565 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3566 if (!wldev)
3567 goto out;
3568
3569 wldev->dev = dev;
3570 wldev->wl = wl;
3571 b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3572 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3573 tasklet_init(&wldev->isr_tasklet,
3574 (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3575 (unsigned long)wldev);
3576 if (modparam_pio)
3577 wldev->__using_pio = 1;
3578 INIT_LIST_HEAD(&wldev->list);
3579
3580 err = b43legacy_wireless_core_attach(wldev);
3581 if (err)
3582 goto err_kfree_wldev;
3583
3584 list_add(&wldev->list, &wl->devlist);
3585 wl->nr_devs++;
3586 ssb_set_drvdata(dev, wldev);
3587 b43legacy_debugfs_add_device(wldev);
3588out:
3589 return err;
3590
3591err_kfree_wldev:
3592 kfree(wldev);
3593 return err;
3594}
3595
3596static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3597{
3598 /* boardflags workarounds */
3599 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3600 bus->boardinfo.type == 0x4E &&
3601 bus->boardinfo.rev > 0x40)
7797aa38 3602 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
75388acd
LF		 3603}
3604
3605static void b43legacy_wireless_exit(struct ssb_device *dev,
3606 struct b43legacy_wl *wl)
3607{
3608 struct ieee80211_hw *hw = wl->hw;
3609
3610 ssb_set_devtypedata(dev, NULL);
3611 ieee80211_free_hw(hw);
3612}
3613
3614static int b43legacy_wireless_init(struct ssb_device *dev)
3615{
3616 struct ssb_sprom *sprom = &dev->bus->sprom;
3617 struct ieee80211_hw *hw;
3618 struct b43legacy_wl *wl;
3619 int err = -ENOMEM;
3620
3621 b43legacy_sprom_fixup(dev->bus);
3622
3623 hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3624 if (!hw) {
3625 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3626 goto out;
3627 }
3628
3629 /* fill hw info */
3630 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3631 IEEE80211_HW_RX_INCLUDES_FCS;
3632 hw->max_signal = 100;
3633 hw->max_rssi = -110;
3634 hw->max_noise = -110;
3635 hw->queues = 1; /* FIXME: hardware has more queues */
3636 SET_IEEE80211_DEV(hw, dev->dev);
7797aa38
LF		 3637 if (is_valid_ether_addr(sprom->et1mac))
3638 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
75388acd 3639 else
7797aa38 3640 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
75388acd
LF		 3641
3642 /* Get and initialize struct b43legacy_wl */
3643 wl = hw_to_b43legacy_wl(hw);
3644 memset(wl, 0, sizeof(*wl));
3645 wl->hw = hw;
3646 spin_lock_init(&wl->irq_lock);
3647 spin_lock_init(&wl->leds_lock);
3648 mutex_init(&wl->mutex);
3649 INIT_LIST_HEAD(&wl->devlist);
3650
3651 ssb_set_devtypedata(dev, wl);
3652 b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3653 err = 0;
3654out:
3655 return err;
3656}
3657
3658static int b43legacy_probe(struct ssb_device *dev,
3659 const struct ssb_device_id *id)
3660{
3661 struct b43legacy_wl *wl;
3662 int err;
3663 int first = 0;
3664
3665 wl = ssb_get_devtypedata(dev);
3666 if (!wl) {
3667 /* Probing the first core - setup common struct b43legacy_wl */
3668 first = 1;
3669 err = b43legacy_wireless_init(dev);
3670 if (err)
3671 goto out;
3672 wl = ssb_get_devtypedata(dev);
3673 B43legacy_WARN_ON(!wl);
3674 }
3675 err = b43legacy_one_core_attach(dev, wl);
3676 if (err)
3677 goto err_wireless_exit;
3678
3679 if (first) {
3680 err = ieee80211_register_hw(wl->hw);
3681 if (err)
3682 goto err_one_core_detach;
3683 }
3684
3685out:
3686 return err;
3687
3688err_one_core_detach:
3689 b43legacy_one_core_detach(dev);
3690err_wireless_exit:
3691 if (first)
3692 b43legacy_wireless_exit(dev, wl);
3693 return err;
3694}
3695
3696static void b43legacy_remove(struct ssb_device *dev)
3697{
3698 struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3699 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3700
3701 B43legacy_WARN_ON(!wl);
3702 if (wl->current_dev == wldev)
3703 ieee80211_unregister_hw(wl->hw);
3704
3705 b43legacy_one_core_detach(dev);
3706
3707 if (list_empty(&wl->devlist))
3708 /* Last core on the chip unregistered.
3709 * We can destroy common struct b43legacy_wl.
3710 */
3711 b43legacy_wireless_exit(dev, wl);
3712}
3713
3714/* Perform a hardware reset. This can be called from any context. */
3715void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3716 const char *reason)
3717{
3718 /* Must avoid requeueing, if we are in shutdown. */
3719 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3720 return;
3721 b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
3722 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3723}
3724
3725#ifdef CONFIG_PM
3726
3727static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3728{
3729 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3730 struct b43legacy_wl *wl = wldev->wl;
3731
3732 b43legacydbg(wl, "Suspending...\n");
3733
3734 mutex_lock(&wl->mutex);
3735 wldev->suspend_init_status = b43legacy_status(wldev);
3736 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3737 b43legacy_wireless_core_stop(wldev);
3738 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3739 b43legacy_wireless_core_exit(wldev);
3740 mutex_unlock(&wl->mutex);
3741
3742 b43legacydbg(wl, "Device suspended.\n");
3743
3744 return 0;
3745}
3746
3747static int b43legacy_resume(struct ssb_device *dev)
3748{
3749 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3750 struct b43legacy_wl *wl = wldev->wl;
3751 int err = 0;
3752
3753 b43legacydbg(wl, "Resuming...\n");
3754
3755 mutex_lock(&wl->mutex);
3756 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3757 err = b43legacy_wireless_core_init(wldev);
3758 if (err) {
3759 b43legacyerr(wl, "Resume failed at core init\n");
3760 goto out;
3761 }
3762 }
3763 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3764 err = b43legacy_wireless_core_start(wldev);
3765 if (err) {
3766 b43legacy_wireless_core_exit(wldev);
3767 b43legacyerr(wl, "Resume failed at core start\n");
3768 goto out;
3769 }
3770 }
3771 mutex_unlock(&wl->mutex);
3772
3773 b43legacydbg(wl, "Device resumed.\n");
3774out:
3775 return err;
3776}
3777
3778#else /* CONFIG_PM */
3779# define b43legacy_suspend NULL
3780# define b43legacy_resume NULL
3781#endif /* CONFIG_PM */
3782
3783static struct ssb_driver b43legacy_ssb_driver = {
3784 .name = KBUILD_MODNAME,
3785 .id_table = b43legacy_ssb_tbl,
3786 .probe = b43legacy_probe,
3787 .remove = b43legacy_remove,
3788 .suspend = b43legacy_suspend,
3789 .resume = b43legacy_resume,
3790};
3791
6fff1c64
SB		 3792static void b43legacy_print_driverinfo(void)
3793{
3794 const char *feat_pci = "", *feat_leds = "", *feat_rfkill = "",
3795 *feat_pio = "", *feat_dma = "";
3796
3797#ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3798 feat_pci = "P";
3799#endif
3800#ifdef CONFIG_B43LEGACY_LEDS
3801 feat_leds = "L";
3802#endif
3803#ifdef CONFIG_B43LEGACY_RFKILL
3804 feat_rfkill = "R";
3805#endif
3806#ifdef CONFIG_B43LEGACY_PIO
3807 feat_pio = "I";
3808#endif
3809#ifdef CONFIG_B43LEGACY_DMA
3810 feat_dma = "D";
3811#endif
3812 printk(KERN_INFO "Broadcom 43xx driver loaded "
3813 "[ Features: %s%s%s%s%s, Firmware-ID: "
3814 B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
3815 feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma);
3816}
3817
75388acd
LF		 3818static int __init b43legacy_init(void)
3819{
3820 int err;
3821
3822 b43legacy_debugfs_init();
3823
3824 err = ssb_driver_register(&b43legacy_ssb_driver);
3825 if (err)
3826 goto err_dfs_exit;
3827
6fff1c64
SB		 3828 b43legacy_print_driverinfo();
3829
75388acd
LF		 3830 return err;
3831
3832err_dfs_exit:
3833 b43legacy_debugfs_exit();
3834 return err;
3835}
3836
3837static void __exit b43legacy_exit(void)
3838{
3839 ssb_driver_unregister(&b43legacy_ssb_driver);
3840 b43legacy_debugfs_exit();
3841}
3842
3843module_init(b43legacy_init)
3844module_exit(b43legacy_exit)
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