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Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/driver-2.6
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / bcm43xx / bcm43xx_main.c
CommitLineData
f222313a
JL		 1/*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
d1ca6c4f 41#include <linux/dma-mapping.h>
f222313a
JL		 42#include <net/iw_handler.h>
43
44#include "bcm43xx.h"
45#include "bcm43xx_main.h"
46#include "bcm43xx_debugfs.h"
47#include "bcm43xx_radio.h"
48#include "bcm43xx_phy.h"
49#include "bcm43xx_dma.h"
50#include "bcm43xx_pio.h"
51#include "bcm43xx_power.h"
52#include "bcm43xx_wx.h"
6465ce1b 53#include "bcm43xx_ethtool.h"
f398f02d 54#include "bcm43xx_xmit.h"
b35d649c 55#include "bcm43xx_sysfs.h"
f222313a
JL		 56
57
58MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
59MODULE_AUTHOR("Martin Langer");
60MODULE_AUTHOR("Stefano Brivio");
61MODULE_AUTHOR("Michael Buesch");
62MODULE_LICENSE("GPL");
63
64#ifdef CONFIG_BCM947XX
65extern char *nvram_get(char *name);
66#endif
67
77db31ea 68#if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
f222313a
JL		 69static int modparam_pio;
70module_param_named(pio, modparam_pio, int, 0444);
71MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
77db31ea
MB		 72#elif defined(CONFIG_BCM43XX_DMA)
73# define modparam_pio 0
74#elif defined(CONFIG_BCM43XX_PIO)
75# define modparam_pio 1
76#endif
f222313a
JL		 77
78static int modparam_bad_frames_preempt;
79module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
81
82static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
83module_param_named(short_retry, modparam_short_retry, int, 0444);
84MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
85
86static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
87module_param_named(long_retry, modparam_long_retry, int, 0444);
88MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
89
90static int modparam_locale = -1;
91module_param_named(locale, modparam_locale, int, 0444);
92MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
93
f222313a
JL		 94static int modparam_noleds;
95module_param_named(noleds, modparam_noleds, int, 0444);
96MODULE_PARM_DESC(noleds, "Turn off all LED activity");
97
98#ifdef CONFIG_BCM43XX_DEBUG
99static char modparam_fwpostfix[64];
100module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
101MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
102#else
103# define modparam_fwpostfix ""
104#endif /* CONFIG_BCM43XX_DEBUG*/
105
106
107/* If you want to debug with just a single device, enable this,
108 * where the string is the pci device ID (as given by the kernel's
109 * pci_name function) of the device to be used.
110 */
111//#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
112
113/* If you want to enable printing of each MMIO access, enable this. */
114//#define DEBUG_ENABLE_MMIO_PRINT
115
116/* If you want to enable printing of MMIO access within
117 * ucode/pcm upload, initvals write, enable this.
118 */
119//#define DEBUG_ENABLE_UCODE_MMIO_PRINT
120
121/* If you want to enable printing of PCI Config Space access, enable this */
122//#define DEBUG_ENABLE_PCILOG
123
124
489423c8
MB		 125/* Detailed list maintained at:
126 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
127 */
128 static struct pci_device_id bcm43xx_pci_tbl[] = {
f222313a
JL		 129 /* Broadcom 4303 802.11b */
130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
ec000ca9 131 /* Broadcom 4307 802.11b */
f222313a 132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f3d1fca3
SB		 133 /* Broadcom 4311 802.11(a)/b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4312 802.11a/b/g */
136 { PCI_VENDOR_ID_BROADCOM, 0x4312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
ec000ca9 137 /* Broadcom 4318 802.11b/g */
f222313a 138 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f03cc4fd
SB		 139 /* Broadcom 4319 802.11a/b/g */
140 { PCI_VENDOR_ID_BROADCOM, 0x4319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f222313a
JL		 141 /* Broadcom 4306 802.11b/g */
142 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
ec000ca9 143 /* Broadcom 4306 802.11a */
f222313a 144// { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f222313a
JL		 145 /* Broadcom 4309 802.11a/b/g */
146 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f222313a
JL		 147 /* Broadcom 43XG 802.11b/g */
148 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
489423c8
MB		 149#ifdef CONFIG_BCM947XX
150 /* SB bus on BCM947xx */
151 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152#endif
153 { 0 },
f222313a
JL		 154};
155MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
156
157static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
158{
159 u32 status;
160
161 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
162 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
163 val = swab32(val);
164
165 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
73733847 166 mmiowb();
f222313a
JL		 167 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
168}
169
170static inline
171void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
172 u16 routing, u16 offset)
173{
174 u32 control;
175
176 /* "offset" is the WORD offset. */
177
178 control = routing;
179 control <<= 16;
180 control |= offset;
181 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
182}
183
184u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
185 u16 routing, u16 offset)
186{
187 u32 ret;
188
189 if (routing == BCM43xx_SHM_SHARED) {
190 if (offset & 0x0003) {
191 /* Unaligned access */
192 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
193 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
194 ret <<= 16;
195 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
196 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
197
198 return ret;
199 }
200 offset >>= 2;
201 }
202 bcm43xx_shm_control_word(bcm, routing, offset);
203 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
204
205 return ret;
206}
207
208u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
209 u16 routing, u16 offset)
210{
211 u16 ret;
212
213 if (routing == BCM43xx_SHM_SHARED) {
214 if (offset & 0x0003) {
215 /* Unaligned access */
216 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
217 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
218
219 return ret;
220 }
221 offset >>= 2;
222 }
223 bcm43xx_shm_control_word(bcm, routing, offset);
224 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
225
226 return ret;
227}
228
229void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
230 u16 routing, u16 offset,
231 u32 value)
232{
233 if (routing == BCM43xx_SHM_SHARED) {
234 if (offset & 0x0003) {
235 /* Unaligned access */
236 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
73733847 237 mmiowb();
f222313a
JL		 238 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
239 (value >> 16) & 0xffff);
73733847 240 mmiowb();
f222313a 241 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
73733847 242 mmiowb();
f222313a
JL		 243 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
244 value & 0xffff);
245 return;
246 }
247 offset >>= 2;
248 }
249 bcm43xx_shm_control_word(bcm, routing, offset);
73733847 250 mmiowb();
f222313a
JL		 251 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
252}
253
254void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
255 u16 routing, u16 offset,
256 u16 value)
257{
258 if (routing == BCM43xx_SHM_SHARED) {
259 if (offset & 0x0003) {
260 /* Unaligned access */
261 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
73733847 262 mmiowb();
f222313a
JL		 263 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
264 value);
265 return;
266 }
267 offset >>= 2;
268 }
269 bcm43xx_shm_control_word(bcm, routing, offset);
73733847 270 mmiowb();
f222313a
JL		 271 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
272}
273
274void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
275{
276 /* We need to be careful. As we read the TSF from multiple
277 * registers, we should take care of register overflows.
278 * In theory, the whole tsf read process should be atomic.
279 * We try to be atomic here, by restaring the read process,
280 * if any of the high registers changed (overflew).
281 */
282 if (bcm->current_core->rev >= 3) {
283 u32 low, high, high2;
284
285 do {
286 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
287 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
288 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
289 } while (unlikely(high != high2));
290
291 *tsf = high;
292 *tsf <<= 32;
293 *tsf |= low;
294 } else {
295 u64 tmp;
296 u16 v0, v1, v2, v3;
297 u16 test1, test2, test3;
298
299 do {
300 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
301 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
302 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
303 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
304
305 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
306 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
307 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
308 } while (v3 != test3 || v2 != test2 || v1 != test1);
309
310 *tsf = v3;
311 *tsf <<= 48;
312 tmp = v2;
313 tmp <<= 32;
314 *tsf |= tmp;
315 tmp = v1;
316 tmp <<= 16;
317 *tsf |= tmp;
318 *tsf |= v0;
319 }
320}
321
322void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
323{
324 u32 status;
325
326 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
327 status |= BCM43xx_SBF_TIME_UPDATE;
328 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
73733847 329 mmiowb();
f222313a
JL		 330
331 /* Be careful with the in-progress timer.
332 * First zero out the low register, so we have a full
333 * register-overflow duration to complete the operation.
334 */
335 if (bcm->current_core->rev >= 3) {
336 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
337 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
338
f222313a 339 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
73733847 340 mmiowb();
f222313a 341 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
73733847 342 mmiowb();
f222313a
JL		 343 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
344 } else {
345 u16 v0 = (tsf & 0x000000000000FFFFULL);
346 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
347 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
348 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
349
f222313a 350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
73733847 351 mmiowb();
f222313a 352 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
73733847 353 mmiowb();
f222313a 354 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
73733847 355 mmiowb();
f222313a 356 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
73733847 357 mmiowb();
f222313a
JL		 358 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
359 }
360
361 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
362 status &= ~BCM43xx_SBF_TIME_UPDATE;
363 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
364}
365
f222313a
JL		 366static
367void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
368 u16 offset,
369 const u8 *mac)
370{
371 u16 data;
372
373 offset |= 0x0020;
374 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
375
376 data = mac[0];
377 data |= mac[1] << 8;
378 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
379 data = mac[2];
380 data |= mac[3] << 8;
381 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
382 data = mac[4];
383 data |= mac[5] << 8;
384 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
385}
386
489423c8
MB		 387static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
388 u16 offset)
f222313a
JL		 389{
390 const u8 zero_addr[ETH_ALEN] = { 0 };
391
392 bcm43xx_macfilter_set(bcm, offset, zero_addr);
393}
394
395static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
396{
397 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
398 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
399 u8 mac_bssid[ETH_ALEN * 2];
400 int i;
401
402 memcpy(mac_bssid, mac, ETH_ALEN);
403 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
404
405 /* Write our MAC address and BSSID to template ram */
406 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
407 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
408 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
409 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
410 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
411 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
412}
413
b5e868ed
MB		 414//FIXME: Well, we should probably call them from somewhere.
415#if 0
489423c8 416static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
f222313a
JL		 417{
418 /* slot_time is in usec. */
e9357c05 419 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
f222313a
JL		 420 return;
421 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
422 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
423}
424
489423c8 425static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
f222313a
JL		 426{
427 bcm43xx_set_slot_time(bcm, 9);
428}
429
489423c8 430static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
f222313a
JL		 431{
432 bcm43xx_set_slot_time(bcm, 20);
433}
b5e868ed 434#endif
f222313a 435
b5e868ed
MB		 436/* FIXME: To get the MAC-filter working, we need to implement the
437 * following functions (and rename them :)
438 */
439#if 0
f222313a
JL		 440static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
441{
442 bcm43xx_mac_suspend(bcm);
443 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
444
445 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
446 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
447 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
448 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
449 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
450 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
451
452 if (bcm->current_core->rev < 3) {
453 bcm43xx_write16(bcm, 0x0610, 0x8000);
454 bcm43xx_write16(bcm, 0x060E, 0x0000);
455 } else
456 bcm43xx_write32(bcm, 0x0188, 0x80000000);
457
458 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
459
e9357c05 460 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
f222313a
JL		 461 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
462 bcm43xx_short_slot_timing_enable(bcm);
463
464 bcm43xx_mac_enable(bcm);
465}
466
f222313a
JL		 467static void bcm43xx_associate(struct bcm43xx_private *bcm,
468 const u8 *mac)
469{
470 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
471
472 bcm43xx_mac_suspend(bcm);
473 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
474 bcm43xx_write_mac_bssid_templates(bcm);
475 bcm43xx_mac_enable(bcm);
476}
b5e868ed 477#endif
f222313a
JL		 478
479/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
480 * Returns the _previously_ enabled IRQ mask.
481 */
482static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
483{
484 u32 old_mask;
485
486 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
487 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
488
489 return old_mask;
490}
491
492/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
493 * Returns the _previously_ enabled IRQ mask.
494 */
495static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
496{
497 u32 old_mask;
498
499 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
500 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
501
502 return old_mask;
503}
504
91769e7d
MB		 505/* Synchronize IRQ top- and bottom-half.
506 * IRQs must be masked before calling this.
507 * This must not be called with the irq_lock held.
508 */
509static void bcm43xx_synchronize_irq(struct bcm43xx_private *bcm)
510{
511 synchronize_irq(bcm->irq);
512 tasklet_disable(&bcm->isr_tasklet);
513}
514
f222313a 515/* Make sure we don't receive more data from the device. */
58e5528e 516static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm)
f222313a 517{
f222313a
JL		 518 unsigned long flags;
519
efa6a370 520 spin_lock_irqsave(&bcm->irq_lock, flags);
78ff56a0 521 if (unlikely(bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)) {
efa6a370 522 spin_unlock_irqrestore(&bcm->irq_lock, flags);
f222313a
JL		 523 return -EBUSY;
524 }
58e5528e 525 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
7d4b0394 526 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
efa6a370 527 spin_unlock_irqrestore(&bcm->irq_lock, flags);
91769e7d
MB		 528 bcm43xx_synchronize_irq(bcm);
529
f222313a
JL		 530 return 0;
531}
532
533static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
534{
e9357c05
MB		 535 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
536 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a
JL		 537 u32 radio_id;
538 u16 manufact;
539 u16 version;
540 u8 revision;
f222313a
JL		 541
542 if (bcm->chip_id == 0x4317) {
543 if (bcm->chip_rev == 0x00)
544 radio_id = 0x3205017F;
545 else if (bcm->chip_rev == 0x01)
546 radio_id = 0x4205017F;
547 else
548 radio_id = 0x5205017F;
549 } else {
550 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
551 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
552 radio_id <<= 16;
553 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
554 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
555 }
556
557 manufact = (radio_id & 0x00000FFF);
558 version = (radio_id & 0x0FFFF000) >> 12;
559 revision = (radio_id & 0xF0000000) >> 28;
560
489423c8 561 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
f222313a
JL		 562 radio_id, manufact, version, revision);
563
489423c8 564 switch (phy->type) {
f222313a
JL		 565 case BCM43xx_PHYTYPE_A:
566 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
567 goto err_unsupported_radio;
568 break;
569 case BCM43xx_PHYTYPE_B:
570 if ((version & 0xFFF0) != 0x2050)
571 goto err_unsupported_radio;
572 break;
573 case BCM43xx_PHYTYPE_G:
574 if (version != 0x2050)
575 goto err_unsupported_radio;
576 break;
577 }
578
489423c8
MB		 579 radio->manufact = manufact;
580 radio->version = version;
581 radio->revision = revision;
f222313a 582
e9357c05 583 if (phy->type == BCM43xx_PHYTYPE_A)
489423c8 584 radio->txpower_desired = bcm->sprom.maxpower_aphy;
393344f6 585 else
e9357c05 586 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
f222313a 587
f222313a
JL		 588 return 0;
589
590err_unsupported_radio:
591 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
592 return -ENODEV;
593}
594
595static const char * bcm43xx_locale_iso(u8 locale)
596{
597 /* ISO 3166-1 country codes.
598 * Note that there aren't ISO 3166-1 codes for
599 * all or locales. (Not all locales are countries)
600 */
601 switch (locale) {
602 case BCM43xx_LOCALE_WORLD:
603 case BCM43xx_LOCALE_ALL:
604 return "XX";
605 case BCM43xx_LOCALE_THAILAND:
606 return "TH";
607 case BCM43xx_LOCALE_ISRAEL:
608 return "IL";
609 case BCM43xx_LOCALE_JORDAN:
610 return "JO";
611 case BCM43xx_LOCALE_CHINA:
612 return "CN";
613 case BCM43xx_LOCALE_JAPAN:
614 case BCM43xx_LOCALE_JAPAN_HIGH:
615 return "JP";
616 case BCM43xx_LOCALE_USA_CANADA_ANZ:
617 case BCM43xx_LOCALE_USA_LOW:
618 return "US";
619 case BCM43xx_LOCALE_EUROPE:
620 return "EU";
621 case BCM43xx_LOCALE_NONE:
622 return " ";
623 }
624 assert(0);
625 return " ";
626}
627
628static const char * bcm43xx_locale_string(u8 locale)
629{
630 switch (locale) {
631 case BCM43xx_LOCALE_WORLD:
632 return "World";
633 case BCM43xx_LOCALE_THAILAND:
634 return "Thailand";
635 case BCM43xx_LOCALE_ISRAEL:
636 return "Israel";
637 case BCM43xx_LOCALE_JORDAN:
638 return "Jordan";
639 case BCM43xx_LOCALE_CHINA:
640 return "China";
641 case BCM43xx_LOCALE_JAPAN:
642 return "Japan";
643 case BCM43xx_LOCALE_USA_CANADA_ANZ:
644 return "USA/Canada/ANZ";
645 case BCM43xx_LOCALE_EUROPE:
646 return "Europe";
647 case BCM43xx_LOCALE_USA_LOW:
648 return "USAlow";
649 case BCM43xx_LOCALE_JAPAN_HIGH:
650 return "JapanHigh";
651 case BCM43xx_LOCALE_ALL:
652 return "All";
653 case BCM43xx_LOCALE_NONE:
654 return "None";
655 }
656 assert(0);
657 return "";
658}
659
660static inline u8 bcm43xx_crc8(u8 crc, u8 data)
661{
662 static const u8 t[] = {
663 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
664 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
665 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
666 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
667 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
668 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
669 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
670 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
671 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
672 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
673 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
674 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
675 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
676 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
677 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
678 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
679 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
680 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
681 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
682 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
683 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
684 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
685 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
686 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
687 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
688 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
689 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
690 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
691 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
692 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
693 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
694 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
695 };
696 return t[crc ^ data];
697}
698
ad3f086c 699static u8 bcm43xx_sprom_crc(const u16 *sprom)
f222313a
JL		 700{
701 int word;
702 u8 crc = 0xFF;
703
704 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
705 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
706 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
707 }
708 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
709 crc ^= 0xFF;
710
711 return crc;
712}
713
ea0922b0 714int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
f222313a
JL		 715{
716 int i;
ea0922b0
MB		 717 u8 crc, expected_crc;
718
719 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
720 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
721 /* CRC-8 check. */
722 crc = bcm43xx_sprom_crc(sprom);
723 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
724 if (crc != expected_crc) {
725 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
726 "(0x%02X, expected: 0x%02X)\n",
727 crc, expected_crc);
728 return -EINVAL;
729 }
730
731 return 0;
732}
733
734int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
735{
736 int i, err;
737 u8 crc, expected_crc;
738 u32 spromctl;
739
740 /* CRC-8 validation of the input data. */
741 crc = bcm43xx_sprom_crc(sprom);
742 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
743 if (crc != expected_crc) {
744 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
745 return -EINVAL;
746 }
747
748 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
749 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
750 if (err)
751 goto err_ctlreg;
752 spromctl |= 0x10; /* SPROM WRITE enable. */
3406118c 753 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
ea0922b0
MB		 754 if (err)
755 goto err_ctlreg;
756 /* We must burn lots of CPU cycles here, but that does not
757 * really matter as one does not write the SPROM every other minute...
758 */
759 printk(KERN_INFO PFX "[ 0%%");
760 mdelay(500);
761 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
762 if (i == 16)
763 printk("25%%");
764 else if (i == 32)
765 printk("50%%");
766 else if (i == 48)
767 printk("75%%");
768 else if (i % 2)
769 printk(".");
770 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
efccb647 771 mmiowb();
ea0922b0
MB		 772 mdelay(20);
773 }
774 spromctl &= ~0x10; /* SPROM WRITE enable. */
3406118c 775 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
ea0922b0
MB		 776 if (err)
777 goto err_ctlreg;
778 mdelay(500);
779 printk("100%% ]\n");
780 printk(KERN_INFO PFX "SPROM written.\n");
781 bcm43xx_controller_restart(bcm, "SPROM update");
782
783 return 0;
784err_ctlreg:
785 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
786 return -ENODEV;
787}
788
789static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
790{
f222313a
JL		 791 u16 value;
792 u16 *sprom;
f222313a
JL		 793#ifdef CONFIG_BCM947XX
794 char *c;
795#endif
796
797 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
798 GFP_KERNEL);
799 if (!sprom) {
ea0922b0 800 printk(KERN_ERR PFX "sprom_extract OOM\n");
f222313a
JL		 801 return -ENOMEM;
802 }
803#ifdef CONFIG_BCM947XX
804 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
805 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
806
807 if ((c = nvram_get("il0macaddr")) != NULL)
808 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
809
810 if ((c = nvram_get("et1macaddr")) != NULL)
811 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
812
813 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
814 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
815 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
816
817 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
818 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
819 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
820
821 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
822#else
ea0922b0 823 bcm43xx_sprom_read(bcm, sprom);
f222313a
JL		 824#endif
825
826 /* boardflags2 */
827 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
828 bcm->sprom.boardflags2 = value;
829
830 /* il0macaddr */
831 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
832 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
833 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
834 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
835 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
836 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
837
838 /* et0macaddr */
839 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
840 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
841 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
842 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
843 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
844 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
845
846 /* et1macaddr */
847 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
848 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
849 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
850 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
851 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
852 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
853
854 /* ethernet phy settings */
855 value = sprom[BCM43xx_SPROM_ETHPHY];
856 bcm->sprom.et0phyaddr = (value & 0x001F);
857 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
858 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
859 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
860
861 /* boardrev, antennas, locale */
862 value = sprom[BCM43xx_SPROM_BOARDREV];
863 bcm->sprom.boardrev = (value & 0x00FF);
864 bcm->sprom.locale = (value & 0x0F00) >> 8;
865 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
866 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
867 if (modparam_locale != -1) {
868 if (modparam_locale >= 0 && modparam_locale <= 11) {
869 bcm->sprom.locale = modparam_locale;
870 printk(KERN_WARNING PFX "Operating with modified "
871 "LocaleCode %u (%s)\n",
872 bcm->sprom.locale,
873 bcm43xx_locale_string(bcm->sprom.locale));
874 } else {
875 printk(KERN_WARNING PFX "Module parameter \"locale\" "
876 "invalid value. (0 - 11)\n");
877 }
878 }
879
880 /* pa0b* */
881 value = sprom[BCM43xx_SPROM_PA0B0];
882 bcm->sprom.pa0b0 = value;
883 value = sprom[BCM43xx_SPROM_PA0B1];
884 bcm->sprom.pa0b1 = value;
885 value = sprom[BCM43xx_SPROM_PA0B2];
886 bcm->sprom.pa0b2 = value;
887
888 /* wl0gpio* */
889 value = sprom[BCM43xx_SPROM_WL0GPIO0];
890 if (value == 0x0000)
891 value = 0xFFFF;
892 bcm->sprom.wl0gpio0 = value & 0x00FF;
893 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
894 value = sprom[BCM43xx_SPROM_WL0GPIO2];
895 if (value == 0x0000)
896 value = 0xFFFF;
897 bcm->sprom.wl0gpio2 = value & 0x00FF;
898 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
899
900 /* maxpower */
901 value = sprom[BCM43xx_SPROM_MAXPWR];
902 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
903 bcm->sprom.maxpower_bgphy = value & 0x00FF;
904
905 /* pa1b* */
906 value = sprom[BCM43xx_SPROM_PA1B0];
907 bcm->sprom.pa1b0 = value;
908 value = sprom[BCM43xx_SPROM_PA1B1];
909 bcm->sprom.pa1b1 = value;
910 value = sprom[BCM43xx_SPROM_PA1B2];
911 bcm->sprom.pa1b2 = value;
912
913 /* idle tssi target */
914 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
915 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
916 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
917
918 /* boardflags */
919 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
920 if (value == 0xFFFF)
921 value = 0x0000;
922 bcm->sprom.boardflags = value;
b3db5e55
MB		 923 /* boardflags workarounds */
924 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
925 bcm->chip_id == 0x4301 &&
926 bcm->board_revision == 0x74)
927 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
928 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
929 bcm->board_type == 0x4E &&
930 bcm->board_revision > 0x40)
931 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
f222313a
JL		 932
933 /* antenna gain */
934 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
935 if (value == 0x0000 || value == 0xFFFF)
936 value = 0x0202;
937 /* convert values to Q5.2 */
938 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
939 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
940
941 kfree(sprom);
942
943 return 0;
944}
945
869aaab1 946static int bcm43xx_geo_init(struct bcm43xx_private *bcm)
f222313a 947{
869aaab1 948 struct ieee80211_geo *geo;
f222313a
JL		 949 struct ieee80211_channel *chan;
950 int have_a = 0, have_bg = 0;
e9357c05 951 int i;
9e4a375b 952 u8 channel;
f222313a
JL		 953 struct bcm43xx_phyinfo *phy;
954 const char *iso_country;
955
869aaab1
MB		 956 geo = kzalloc(sizeof(*geo), GFP_KERNEL);
957 if (!geo)
958 return -ENOMEM;
959
e9357c05
MB		 960 for (i = 0; i < bcm->nr_80211_available; i++) {
961 phy = &(bcm->core_80211_ext[i].phy);
f222313a
JL		 962 switch (phy->type) {
963 case BCM43xx_PHYTYPE_B:
964 case BCM43xx_PHYTYPE_G:
965 have_bg = 1;
966 break;
967 case BCM43xx_PHYTYPE_A:
968 have_a = 1;
969 break;
970 default:
971 assert(0);
972 }
973 }
974 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
975
976 if (have_a) {
869aaab1
MB		 977 for (i = 0, channel = IEEE80211_52GHZ_MIN_CHANNEL;
978 channel <= IEEE80211_52GHZ_MAX_CHANNEL; channel++) {
979 chan = &geo->a[i++];
10d8dd88 980 chan->freq = bcm43xx_channel_to_freq_a(channel);
f222313a 981 chan->channel = channel;
f222313a 982 }
869aaab1 983 geo->a_channels = i;
f222313a
JL		 984 }
985 if (have_bg) {
869aaab1
MB		 986 for (i = 0, channel = IEEE80211_24GHZ_MIN_CHANNEL;
987 channel <= IEEE80211_24GHZ_MAX_CHANNEL; channel++) {
988 chan = &geo->bg[i++];
10d8dd88 989 chan->freq = bcm43xx_channel_to_freq_bg(channel);
f222313a 990 chan->channel = channel;
f222313a 991 }
869aaab1 992 geo->bg_channels = i;
f222313a 993 }
869aaab1 994 memcpy(geo->name, iso_country, 2);
f222313a 995 if (0 /*TODO: Outdoor use only */)
869aaab1 996 geo->name[2] = 'O';
f222313a 997 else if (0 /*TODO: Indoor use only */)
869aaab1 998 geo->name[2] = 'I';
f222313a 999 else
869aaab1
MB		 1000 geo->name[2] = ' ';
1001 geo->name[3] = '\0';
1002
1003 ieee80211_set_geo(bcm->ieee, geo);
1004 kfree(geo);
f222313a 1005
869aaab1 1006 return 0;
f222313a
JL		 1007}
1008
1009/* DummyTransmission function, as documented on
1010 * http://bcm-specs.sipsolutions.net/DummyTransmission
1011 */
1012void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
1013{
e9357c05
MB		 1014 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1015 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
f222313a
JL		 1016 unsigned int i, max_loop;
1017 u16 value = 0;
1018 u32 buffer[5] = {
1019 0x00000000,
1020 0x0000D400,
1021 0x00000000,
1022 0x00000001,
1023 0x00000000,
1024 };
1025
489423c8 1026 switch (phy->type) {
f222313a
JL		 1027 case BCM43xx_PHYTYPE_A:
1028 max_loop = 0x1E;
1029 buffer[0] = 0xCC010200;
1030 break;
1031 case BCM43xx_PHYTYPE_B:
1032 case BCM43xx_PHYTYPE_G:
1033 max_loop = 0xFA;
1034 buffer[0] = 0x6E840B00;
1035 break;
1036 default:
1037 assert(0);
1038 return;
1039 }
1040
1041 for (i = 0; i < 5; i++)
1042 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1043
1044 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1045
1046 bcm43xx_write16(bcm, 0x0568, 0x0000);
1047 bcm43xx_write16(bcm, 0x07C0, 0x0000);
489423c8 1048 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
f222313a
JL		 1049 bcm43xx_write16(bcm, 0x0508, 0x0000);
1050 bcm43xx_write16(bcm, 0x050A, 0x0000);
1051 bcm43xx_write16(bcm, 0x054C, 0x0000);
1052 bcm43xx_write16(bcm, 0x056A, 0x0014);
1053 bcm43xx_write16(bcm, 0x0568, 0x0826);
1054 bcm43xx_write16(bcm, 0x0500, 0x0000);
1055 bcm43xx_write16(bcm, 0x0502, 0x0030);
1056
73733847
MB		 1057 if (radio->version == 0x2050 && radio->revision <= 0x5)
1058 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
f222313a
JL		 1059 for (i = 0x00; i < max_loop; i++) {
1060 value = bcm43xx_read16(bcm, 0x050E);
73733847 1061 if (value & 0x0080)
f222313a
JL		 1062 break;
1063 udelay(10);
1064 }
1065 for (i = 0x00; i < 0x0A; i++) {
1066 value = bcm43xx_read16(bcm, 0x050E);
73733847 1067 if (value & 0x0400)
f222313a
JL		 1068 break;
1069 udelay(10);
1070 }
1071 for (i = 0x00; i < 0x0A; i++) {
1072 value = bcm43xx_read16(bcm, 0x0690);
73733847 1073 if (!(value & 0x0100))
f222313a
JL		 1074 break;
1075 udelay(10);
1076 }
73733847
MB		 1077 if (radio->version == 0x2050 && radio->revision <= 0x5)
1078 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
f222313a
JL		 1079}
1080
1081static void key_write(struct bcm43xx_private *bcm,
1082 u8 index, u8 algorithm, const u16 *key)
1083{
1084 unsigned int i, basic_wep = 0;
1085 u32 offset;
1086 u16 value;
1087
1088 /* Write associated key information */
1089 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1090 ((index << 4) | (algorithm & 0x0F)));
1091
1092 /* The first 4 WEP keys need extra love */
1093 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1094 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1095 basic_wep = 1;
1096
1097 /* Write key payload, 8 little endian words */
1098 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1099 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1100 value = cpu_to_le16(key[i]);
1101 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1102 offset + (i * 2), value);
1103
1104 if (!basic_wep)
1105 continue;
1106
1107 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1108 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1109 value);
1110 }
1111}
1112
1113static void keymac_write(struct bcm43xx_private *bcm,
1114 u8 index, const u32 *addr)
1115{
1116 /* for keys 0-3 there is no associated mac address */
1117 if (index < 4)
1118 return;
1119
1120 index -= 4;
1121 if (bcm->current_core->rev >= 5) {
1122 bcm43xx_shm_write32(bcm,
1123 BCM43xx_SHM_HWMAC,
1124 index * 2,
1125 cpu_to_be32(*addr));
1126 bcm43xx_shm_write16(bcm,
1127 BCM43xx_SHM_HWMAC,
1128 (index * 2) + 1,
1129 cpu_to_be16(*((u16 *)(addr + 1))));
1130 } else {
1131 if (index < 8) {
1132 TODO(); /* Put them in the macaddress filter */
1133 } else {
1134 TODO();
1135 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1136 Keep in mind to update the count of keymacs in 0x003E as well! */
1137 }
1138 }
1139}
1140
1141static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1142 u8 index, u8 algorithm,
1143 const u8 *_key, int key_len,
1144 const u8 *mac_addr)
1145{
1146 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1147
1148 if (index >= ARRAY_SIZE(bcm->key))
1149 return -EINVAL;
1150 if (key_len > ARRAY_SIZE(key))
1151 return -EINVAL;
1152 if (algorithm < 1 || algorithm > 5)
1153 return -EINVAL;
1154
1155 memcpy(key, _key, key_len);
1156 key_write(bcm, index, algorithm, (const u16 *)key);
1157 keymac_write(bcm, index, (const u32 *)mac_addr);
1158
1159 bcm->key[index].algorithm = algorithm;
1160
1161 return 0;
1162}
1163
1164static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1165{
1166 static const u32 zero_mac[2] = { 0 };
1167 unsigned int i,j, nr_keys = 54;
1168 u16 offset;
1169
1170 if (bcm->current_core->rev < 5)
1171 nr_keys = 16;
1172 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1173
1174 for (i = 0; i < nr_keys; i++) {
1175 bcm->key[i].enabled = 0;
1176 /* returns for i < 4 immediately */
1177 keymac_write(bcm, i, zero_mac);
1178 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1179 0x100 + (i * 2), 0x0000);
1180 for (j = 0; j < 8; j++) {
1181 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1182 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1183 offset, 0x0000);
1184 }
1185 }
1186 dprintk(KERN_INFO PFX "Keys cleared\n");
1187}
1188
f222313a
JL		 1189/* Lowlevel core-switch function. This is only to be used in
1190 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1191 */
1192static int _switch_core(struct bcm43xx_private *bcm, int core)
1193{
1194 int err;
1195 int attempts = 0;
489423c8 1196 u32 current_core;
f222313a
JL		 1197
1198 assert(core >= 0);
489423c8
MB		 1199 while (1) {
1200 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
f222313a 1201 (core * 0x1000) + 0x18000000);
489423c8
MB		 1202 if (unlikely(err))
1203 goto error;
1204 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1205 &current_core);
1206 if (unlikely(err))
1207 goto error;
1208 current_core = (current_core - 0x18000000) / 0x1000;
1209 if (current_core == core)
1210 break;
1211
1212 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1213 goto error;
1214 udelay(10);
1215 }
f222313a 1216#ifdef CONFIG_BCM947XX
489423c8
MB		 1217 if (bcm->pci_dev->bus->number == 0)
1218 bcm->current_core_offset = 0x1000 * core;
1219 else
1220 bcm->current_core_offset = 0;
f222313a 1221#endif
f222313a 1222
489423c8
MB		 1223 return 0;
1224error:
1225 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1226 return -ENODEV;
f222313a
JL		 1227}
1228
1229int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1230{
1231 int err;
1232
489423c8 1233 if (unlikely(!new_core))
f222313a 1234 return 0;
e9357c05 1235 if (!new_core->available)
f222313a
JL		 1236 return -ENODEV;
1237 if (bcm->current_core == new_core)
1238 return 0;
1239 err = _switch_core(bcm, new_core->index);
e9357c05
MB		 1240 if (unlikely(err))
1241 goto out;
f222313a 1242
e9357c05 1243 bcm->current_core = new_core;
e9357c05 1244out:
f222313a
JL		 1245 return err;
1246}
1247
489423c8 1248static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
f222313a
JL		 1249{
1250 u32 value;
1251
1252 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1253 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1254 | BCM43xx_SBTMSTATELOW_REJECT;
1255
1256 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1257}
1258
1259/* disable current core */
1260static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1261{
1262 u32 sbtmstatelow;
1263 u32 sbtmstatehigh;
1264 int i;
1265
1266 /* fetch sbtmstatelow from core information registers */
1267 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1268
1269 /* core is already in reset */
1270 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1271 goto out;
1272
1273 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1274 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1275 BCM43xx_SBTMSTATELOW_REJECT;
1276 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1277
1278 for (i = 0; i < 1000; i++) {
1279 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1280 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1281 i = -1;
1282 break;
1283 }
1284 udelay(10);
1285 }
1286 if (i != -1) {
1287 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1288 return -EBUSY;
1289 }
1290
1291 for (i = 0; i < 1000; i++) {
1292 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1293 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1294 i = -1;
1295 break;
1296 }
1297 udelay(10);
1298 }
1299 if (i != -1) {
1300 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1301 return -EBUSY;
1302 }
1303
1304 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1305 BCM43xx_SBTMSTATELOW_REJECT |
1306 BCM43xx_SBTMSTATELOW_RESET |
1307 BCM43xx_SBTMSTATELOW_CLOCK |
1308 core_flags;
1309 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1310 udelay(10);
1311 }
1312
1313 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1314 BCM43xx_SBTMSTATELOW_REJECT |
1315 core_flags;
1316 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1317
1318out:
e9357c05
MB		 1319 bcm->current_core->enabled = 0;
1320
f222313a
JL		 1321 return 0;
1322}
1323
1324/* enable (reset) current core */
1325static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1326{
1327 u32 sbtmstatelow;
1328 u32 sbtmstatehigh;
1329 u32 sbimstate;
1330 int err;
1331
1332 err = bcm43xx_core_disable(bcm, core_flags);
1333 if (err)
1334 goto out;
1335
1336 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1337 BCM43xx_SBTMSTATELOW_RESET |
1338 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1339 core_flags;
1340 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1341 udelay(1);
1342
1343 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1344 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1345 sbtmstatehigh = 0x00000000;
1346 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1347 }
1348
1349 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1350 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1351 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1352 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1353 }
1354
1355 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1356 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1357 core_flags;
1358 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1359 udelay(1);
1360
1361 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1362 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1363 udelay(1);
1364
e9357c05 1365 bcm->current_core->enabled = 1;
f222313a
JL		 1366 assert(err == 0);
1367out:
1368 return err;
1369}
1370
1371/* http://bcm-specs.sipsolutions.net/80211CoreReset */
1372void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1373{
1374 u32 flags = 0x00040000;
1375
77db31ea
MB		 1376 if ((bcm43xx_core_enabled(bcm)) &&
1377 !bcm43xx_using_pio(bcm)) {
f222313a 1378//FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
9218e02b 1379#if 0
f222313a
JL		 1380#ifndef CONFIG_BCM947XX
1381 /* reset all used DMA controllers. */
1382 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1383 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1384 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1385 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1386 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1387 if (bcm->current_core->rev < 5)
1388 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
9218e02b 1389#endif
f222313a
JL		 1390#endif
1391 }
78ff56a0 1392 if (bcm43xx_status(bcm) == BCM43xx_STAT_SHUTTINGDOWN) {
f222313a
JL		 1393 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1394 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1395 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1396 } else {
1397 if (connect_phy)
1398 flags |= 0x20000000;
1399 bcm43xx_phy_connect(bcm, connect_phy);
1400 bcm43xx_core_enable(bcm, flags);
1401 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1402 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1403 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1404 | BCM43xx_SBF_400);
1405 }
1406}
1407
1408static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1409{
1410 bcm43xx_radio_turn_off(bcm);
1411 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1412 bcm43xx_core_disable(bcm, 0);
1413}
1414
58e5528e
MB		 1415/* Mark the current 80211 core inactive. */
1416static void bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm)
f222313a
JL		 1417{
1418 u32 sbtmstatelow;
f222313a
JL		 1419
1420 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1421 bcm43xx_radio_turn_off(bcm);
1422 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
58e5528e
MB		 1423 sbtmstatelow &= 0xDFF5FFFF;
1424 sbtmstatelow |= 0x000A0000;
f222313a
JL		 1425 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1426 udelay(1);
1427 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
58e5528e
MB		 1428 sbtmstatelow &= 0xFFF5FFFF;
1429 sbtmstatelow |= 0x00080000;
f222313a
JL		 1430 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1431 udelay(1);
f222313a
JL		 1432}
1433
489423c8 1434static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
f222313a
JL		 1435{
1436 u32 v0, v1;
1437 u16 tmp;
1438 struct bcm43xx_xmitstatus stat;
1439
f222313a
JL		 1440 while (1) {
1441 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1442 if (!v0)
1443 break;
1444 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1445
1446 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1447 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1448 stat.flags = tmp & 0xFF;
1449 stat.cnt1 = (tmp & 0x0F00) >> 8;
1450 stat.cnt2 = (tmp & 0xF000) >> 12;
1451 stat.seq = (u16)(v1 & 0xFFFF);
1452 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1453
1454 bcm43xx_debugfs_log_txstat(bcm, &stat);
1455
1456 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1457 continue;
1458 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1459 //TODO: packet was not acked (was lost)
1460 }
1461 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1462
77db31ea 1463 if (bcm43xx_using_pio(bcm))
f222313a
JL		 1464 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1465 else
1466 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1467 }
1468}
1469
ecac598b
MB		 1470static void drain_txstatus_queue(struct bcm43xx_private *bcm)
1471{
1472 u32 dummy;
1473
1474 if (bcm->current_core->rev < 5)
1475 return;
1476 /* Read all entries from the microcode TXstatus FIFO
1477 * and throw them away.
1478 */
1479 while (1) {
1480 dummy = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1481 if (!dummy)
1482 break;
1483 dummy = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1484 }
1485}
1486
489423c8 1487static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
f222313a
JL		 1488{
1489 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1490 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1491 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1492 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1493 assert(bcm->noisecalc.core_at_start == bcm->current_core);
e9357c05 1494 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
f222313a
JL		 1495}
1496
1497static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1498{
1499 /* Top half of Link Quality calculation. */
1500
1501 if (bcm->noisecalc.calculation_running)
1502 return;
1503 bcm->noisecalc.core_at_start = bcm->current_core;
e9357c05 1504 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
f222313a
JL		 1505 bcm->noisecalc.calculation_running = 1;
1506 bcm->noisecalc.nr_samples = 0;
1507
1508 bcm43xx_generate_noise_sample(bcm);
1509}
1510
489423c8 1511static void handle_irq_noise(struct bcm43xx_private *bcm)
f222313a 1512{
e9357c05 1513 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
f222313a
JL		 1514 u16 tmp;
1515 u8 noise[4];
1516 u8 i, j;
1517 s32 average;
1518
1519 /* Bottom half of Link Quality calculation. */
1520
1521 assert(bcm->noisecalc.calculation_running);
1522 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1523 bcm->noisecalc.channel_at_start != radio->channel)
1524 goto drop_calculation;
1525 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1526 noise[0] = (tmp & 0x00FF);
1527 noise[1] = (tmp & 0xFF00) >> 8;
1528 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1529 noise[2] = (tmp & 0x00FF);
1530 noise[3] = (tmp & 0xFF00) >> 8;
1531 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1532 noise[2] == 0x7F || noise[3] == 0x7F)
1533 goto generate_new;
1534
1535 /* Get the noise samples. */
522536f6 1536 assert(bcm->noisecalc.nr_samples < 8);
f222313a
JL		 1537 i = bcm->noisecalc.nr_samples;
1538 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1539 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1540 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1541 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1542 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1543 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1544 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1545 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1546 bcm->noisecalc.nr_samples++;
1547 if (bcm->noisecalc.nr_samples == 8) {
1548 /* Calculate the Link Quality by the noise samples. */
1549 average = 0;
1550 for (i = 0; i < 8; i++) {
1551 for (j = 0; j < 4; j++)
1552 average += bcm->noisecalc.samples[i][j];
1553 }
1554 average /= (8 * 4);
1555 average *= 125;
1556 average += 64;
1557 average /= 128;
72fb851e 1558
f222313a
JL		 1559 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1560 tmp = (tmp / 128) & 0x1F;
1561 if (tmp >= 8)
1562 average += 2;
1563 else
1564 average -= 25;
1565 if (tmp == 8)
1566 average -= 72;
1567 else
1568 average -= 48;
1569
6807b507 1570 bcm->stats.noise = average;
f222313a
JL		 1571drop_calculation:
1572 bcm->noisecalc.calculation_running = 0;
1573 return;
1574 }
1575generate_new:
1576 bcm43xx_generate_noise_sample(bcm);
1577}
1578
489423c8 1579static void handle_irq_ps(struct bcm43xx_private *bcm)
f222313a
JL		 1580{
1581 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1582 ///TODO: PS TBTT
1583 } else {
1584 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1585 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1586 }
1587 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1588 bcm->reg124_set_0x4 = 1;
1589 //FIXME else set to false?
1590}
1591
489423c8 1592static void handle_irq_reg124(struct bcm43xx_private *bcm)
f222313a
JL		 1593{
1594 if (!bcm->reg124_set_0x4)
1595 return;
1596 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1597 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1598 | 0x4);
1599 //FIXME: reset reg124_set_0x4 to false?
1600}
1601
489423c8 1602static void handle_irq_pmq(struct bcm43xx_private *bcm)
f222313a
JL		 1603{
1604 u32 tmp;
1605
1606 //TODO: AP mode.
1607
1608 while (1) {
1609 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1610 if (!(tmp & 0x00000008))
1611 break;
1612 }
1613 /* 16bit write is odd, but correct. */
1614 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1615}
1616
1617static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1618 u16 ram_offset, u16 shm_size_offset)
1619{
1620 u32 value;
1621 u16 size = 0;
1622
1623 /* Timestamp. */
1624 //FIXME: assumption: The chip sets the timestamp
1625 value = 0;
1626 bcm43xx_ram_write(bcm, ram_offset++, value);
1627 bcm43xx_ram_write(bcm, ram_offset++, value);
1628 size += 8;
1629
1630 /* Beacon Interval / Capability Information */
1631 value = 0x0000;//FIXME: Which interval?
1632 value |= (1 << 0) << 16; /* ESS */
1633 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1634 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1635 if (!bcm->ieee->open_wep)
1636 value |= (1 << 4) << 16; /* Privacy */
1637 bcm43xx_ram_write(bcm, ram_offset++, value);
1638 size += 4;
1639
1640 /* SSID */
1641 //TODO
1642
1643 /* FH Parameter Set */
1644 //TODO
1645
1646 /* DS Parameter Set */
1647 //TODO
1648
1649 /* CF Parameter Set */
1650 //TODO
1651
1652 /* TIM */
1653 //TODO
1654
1655 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1656}
1657
489423c8 1658static void handle_irq_beacon(struct bcm43xx_private *bcm)
f222313a
JL		 1659{
1660 u32 status;
1661
1662 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1663 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1664
1665 if ((status & 0x1) && (status & 0x2)) {
1666 /* ACK beacon IRQ. */
1667 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1668 BCM43xx_IRQ_BEACON);
1669 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1670 return;
1671 }
1672 if (!(status & 0x1)) {
1673 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1674 status |= 0x1;
1675 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1676 }
1677 if (!(status & 0x2)) {
1678 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1679 status |= 0x2;
1680 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1681 }
1682}
1683
f222313a
JL		 1684/* Interrupt handler bottom-half */
1685static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1686{
1687 u32 reason;
9218e02b
MB		 1688 u32 dma_reason[6];
1689 u32 merged_dma_reason = 0;
1690 int i, activity = 0;
f222313a
JL		 1691 unsigned long flags;
1692
1693#ifdef CONFIG_BCM43XX_DEBUG
1694 u32 _handled = 0x00000000;
1695# define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1696#else
1697# define bcmirq_handled(irq) do { /* nothing */ } while (0)
1698#endif /* CONFIG_BCM43XX_DEBUG*/
1699
efa6a370 1700 spin_lock_irqsave(&bcm->irq_lock, flags);
f222313a 1701 reason = bcm->irq_reason;
9218e02b
MB		 1702 for (i = 5; i >= 0; i--) {
1703 dma_reason[i] = bcm->dma_reason[i];
1704 merged_dma_reason |= dma_reason[i];
1705 }
f222313a
JL		 1706
1707 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1708 /* TX error. We get this when Template Ram is written in wrong endianess
1709 * in dummy_tx(). We also get this if something is wrong with the TX header
1710 * on DMA or PIO queues.
1711 * Maybe we get this in other error conditions, too.
1712 */
73733847 1713 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
f222313a
JL		 1714 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1715 }
9218e02b 1716 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK)) {
73733847 1717 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
9218e02b
MB		 1718 "0x%08X, 0x%08X, 0x%08X, "
1719 "0x%08X, 0x%08X, 0x%08X\n",
73733847 1720 dma_reason[0], dma_reason[1],
9218e02b
MB		 1721 dma_reason[2], dma_reason[3],
1722 dma_reason[4], dma_reason[5]);
73733847 1723 bcm43xx_controller_restart(bcm, "DMA error");
78ff56a0 1724 mmiowb();
efa6a370 1725 spin_unlock_irqrestore(&bcm->irq_lock, flags);
73733847
MB		 1726 return;
1727 }
9218e02b 1728 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK)) {
73733847 1729 printkl(KERN_ERR PFX "DMA error: "
9218e02b
MB		 1730 "0x%08X, 0x%08X, 0x%08X, "
1731 "0x%08X, 0x%08X, 0x%08X\n",
73733847 1732 dma_reason[0], dma_reason[1],
9218e02b
MB		 1733 dma_reason[2], dma_reason[3],
1734 dma_reason[4], dma_reason[5]);
73733847 1735 }
f222313a
JL		 1736
1737 if (reason & BCM43xx_IRQ_PS) {
1738 handle_irq_ps(bcm);
1739 bcmirq_handled(BCM43xx_IRQ_PS);
1740 }
1741
1742 if (reason & BCM43xx_IRQ_REG124) {
1743 handle_irq_reg124(bcm);
1744 bcmirq_handled(BCM43xx_IRQ_REG124);
1745 }
1746
1747 if (reason & BCM43xx_IRQ_BEACON) {
1748 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1749 handle_irq_beacon(bcm);
1750 bcmirq_handled(BCM43xx_IRQ_BEACON);
1751 }
1752
1753 if (reason & BCM43xx_IRQ_PMQ) {
1754 handle_irq_pmq(bcm);
1755 bcmirq_handled(BCM43xx_IRQ_PMQ);
1756 }
1757
1758 if (reason & BCM43xx_IRQ_SCAN) {
1759 /*TODO*/
1760 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1761 }
1762
1763 if (reason & BCM43xx_IRQ_NOISE) {
1764 handle_irq_noise(bcm);
1765 bcmirq_handled(BCM43xx_IRQ_NOISE);
1766 }
1767
1768 /* Check the DMA reason registers for received data. */
f222313a 1769 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
77db31ea 1770 if (bcm43xx_using_pio(bcm))
e9357c05 1771 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
f222313a 1772 else
e9357c05 1773 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
dcfd720b 1774 /* We intentionally don't set "activity" to 1, here. */
f222313a 1775 }
9218e02b
MB		 1776 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1777 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
f222313a 1778 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
e1b1b581 1779 if (bcm43xx_using_pio(bcm))
e9357c05 1780 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
e1b1b581 1781 else
9218e02b 1782 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring3);
e1b1b581 1783 activity = 1;
f222313a 1784 }
9218e02b
MB		 1785 assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
1786 assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
f222313a
JL		 1787 bcmirq_handled(BCM43xx_IRQ_RX);
1788
1789 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
e1b1b581
MB		 1790 handle_irq_transmit_status(bcm);
1791 activity = 1;
f222313a
JL		 1792 //TODO: In AP mode, this also causes sending of powersave responses.
1793 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1794 }
1795
f222313a
JL		 1796 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1797 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1798#ifdef CONFIG_BCM43XX_DEBUG
1799 if (unlikely(reason & ~_handled)) {
1800 printkl(KERN_WARNING PFX
1801 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1802 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1803 reason, (reason & ~_handled),
1804 dma_reason[0], dma_reason[1],
1805 dma_reason[2], dma_reason[3]);
1806 }
1807#endif
1808#undef bcmirq_handled
1809
1810 if (!modparam_noleds)
1811 bcm43xx_leds_update(bcm, activity);
1812 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
78ff56a0 1813 mmiowb();
efa6a370 1814 spin_unlock_irqrestore(&bcm->irq_lock, flags);
f222313a
JL		 1815}
1816
0ac59dae
MB		 1817static void pio_irq_workaround(struct bcm43xx_private *bcm,
1818 u16 base, int queueidx)
f222313a 1819{
0ac59dae
MB		 1820 u16 rxctl;
1821
1822 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1823 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1824 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1825 else
1826 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1827}
f222313a 1828
0ac59dae
MB		 1829static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1830{
77db31ea 1831 if (bcm43xx_using_pio(bcm) &&
f222313a
JL		 1832 (bcm->current_core->rev < 3) &&
1833 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1834 /* Apply a PIO specific workaround to the dma_reasons */
0ac59dae
MB		 1835 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1836 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1837 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1838 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
f222313a
JL		 1839 }
1840
0ac59dae 1841 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
f222313a 1842
9218e02b 1843 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_REASON,
f222313a 1844 bcm->dma_reason[0]);
9218e02b 1845 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
f222313a 1846 bcm->dma_reason[1]);
9218e02b 1847 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
f222313a 1848 bcm->dma_reason[2]);
9218e02b 1849 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
f222313a 1850 bcm->dma_reason[3]);
9218e02b
MB		 1851 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1852 bcm->dma_reason[4]);
1853 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_REASON,
1854 bcm->dma_reason[5]);
f222313a
JL		 1855}
1856
1857/* Interrupt handler top-half */
7d12e780 1858static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id)
f222313a 1859{
efccb647 1860 irqreturn_t ret = IRQ_HANDLED;
f222313a 1861 struct bcm43xx_private *bcm = dev_id;
0ac59dae 1862 u32 reason;
f222313a
JL		 1863
1864 if (!bcm)
1865 return IRQ_NONE;
1866
78ff56a0 1867 spin_lock(&bcm->irq_lock);
f222313a 1868
58e5528e
MB		 1869 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
1870 assert(bcm->current_core->id == BCM43xx_COREID_80211);
a1d79aaa 1871
f222313a
JL		 1872 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1873 if (reason == 0xffffffff) {
1874 /* irq not for us (shared irq) */
efccb647
MB		 1875 ret = IRQ_NONE;
1876 goto out;
f222313a 1877 }
0ac59dae
MB		 1878 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1879 if (!reason)
efccb647 1880 goto out;
f222313a 1881
9218e02b
MB		 1882 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA0_REASON)
1883 & 0x0001DC00;
1884 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1885 & 0x0000DC00;
1886 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1887 & 0x0000DC00;
1888 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1889 & 0x0001DC00;
1890 bcm->dma_reason[4] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1891 & 0x0000DC00;
1892 bcm->dma_reason[5] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA5_REASON)
1893 & 0x0000DC00;
0ac59dae
MB		 1894
1895 bcm43xx_interrupt_ack(bcm, reason);
f222313a 1896
a1d79aaa
MB		 1897 /* disable all IRQs. They are enabled again in the bottom half. */
1898 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1899 /* save the reason code and call our bottom half. */
1900 bcm->irq_reason = reason;
1901 tasklet_schedule(&bcm->isr_tasklet);
f222313a 1902
efccb647
MB		 1903out:
1904 mmiowb();
78ff56a0 1905 spin_unlock(&bcm->irq_lock);
f222313a 1906
efccb647 1907 return ret;
f222313a
JL		 1908}
1909
a4a600d3 1910static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
f222313a 1911{
58e5528e
MB		 1912 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1913
a4a600d3 1914 if (bcm->firmware_norelease && !force)
f222313a 1915 return; /* Suspending or controller reset. */
58e5528e
MB		 1916 release_firmware(phy->ucode);
1917 phy->ucode = NULL;
1918 release_firmware(phy->pcm);
1919 phy->pcm = NULL;
1920 release_firmware(phy->initvals0);
1921 phy->initvals0 = NULL;
1922 release_firmware(phy->initvals1);
1923 phy->initvals1 = NULL;
f222313a
JL		 1924}
1925
1926static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1927{
e9357c05 1928 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a
JL		 1929 u8 rev = bcm->current_core->rev;
1930 int err = 0;
1931 int nr;
1932 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1933
58e5528e 1934 if (!phy->ucode) {
f222313a
JL		 1935 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1936 (rev >= 5 ? 5 : rev),
1937 modparam_fwpostfix);
58e5528e 1938 err = request_firmware(&phy->ucode, buf, &bcm->pci_dev->dev);
f222313a
JL		 1939 if (err) {
1940 printk(KERN_ERR PFX
1941 "Error: Microcode \"%s\" not available or load failed.\n",
1942 buf);
1943 goto error;
1944 }
1945 }
1946
58e5528e 1947 if (!phy->pcm) {
f222313a
JL		 1948 snprintf(buf, ARRAY_SIZE(buf),
1949 "bcm43xx_pcm%d%s.fw",
1950 (rev < 5 ? 4 : 5),
1951 modparam_fwpostfix);
58e5528e 1952 err = request_firmware(&phy->pcm, buf, &bcm->pci_dev->dev);
f222313a
JL		 1953 if (err) {
1954 printk(KERN_ERR PFX
1955 "Error: PCM \"%s\" not available or load failed.\n",
1956 buf);
1957 goto error;
1958 }
1959 }
1960
58e5528e 1961 if (!phy->initvals0) {
f222313a
JL		 1962 if (rev == 2 || rev == 4) {
1963 switch (phy->type) {
1964 case BCM43xx_PHYTYPE_A:
1965 nr = 3;
1966 break;
1967 case BCM43xx_PHYTYPE_B:
1968 case BCM43xx_PHYTYPE_G:
1969 nr = 1;
1970 break;
1971 default:
1972 goto err_noinitval;
1973 }
1974
1975 } else if (rev >= 5) {
1976 switch (phy->type) {
1977 case BCM43xx_PHYTYPE_A:
1978 nr = 7;
1979 break;
1980 case BCM43xx_PHYTYPE_B:
1981 case BCM43xx_PHYTYPE_G:
1982 nr = 5;
1983 break;
1984 default:
1985 goto err_noinitval;
1986 }
1987 } else
1988 goto err_noinitval;
1989 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1990 nr, modparam_fwpostfix);
1991
58e5528e 1992 err = request_firmware(&phy->initvals0, buf, &bcm->pci_dev->dev);
f222313a
JL		 1993 if (err) {
1994 printk(KERN_ERR PFX
1995 "Error: InitVals \"%s\" not available or load failed.\n",
1996 buf);
1997 goto error;
1998 }
58e5528e 1999 if (phy->initvals0->size % sizeof(struct bcm43xx_initval)) {
f222313a
JL		 2000 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2001 goto error;
2002 }
2003 }
2004
58e5528e 2005 if (!phy->initvals1) {
f222313a
JL		 2006 if (rev >= 5) {
2007 u32 sbtmstatehigh;
2008
2009 switch (phy->type) {
2010 case BCM43xx_PHYTYPE_A:
2011 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
2012 if (sbtmstatehigh & 0x00010000)
2013 nr = 9;
2014 else
2015 nr = 10;
2016 break;
2017 case BCM43xx_PHYTYPE_B:
2018 case BCM43xx_PHYTYPE_G:
2019 nr = 6;
2020 break;
2021 default:
2022 goto err_noinitval;
2023 }
2024 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2025 nr, modparam_fwpostfix);
2026
58e5528e 2027 err = request_firmware(&phy->initvals1, buf, &bcm->pci_dev->dev);
f222313a
JL		 2028 if (err) {
2029 printk(KERN_ERR PFX
2030 "Error: InitVals \"%s\" not available or load failed.\n",
2031 buf);
2032 goto error;
2033 }
58e5528e 2034 if (phy->initvals1->size % sizeof(struct bcm43xx_initval)) {
f222313a
JL		 2035 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2036 goto error;
2037 }
2038 }
2039 }
2040
2041out:
2042 return err;
2043error:
a4a600d3 2044 bcm43xx_release_firmware(bcm, 1);
f222313a
JL		 2045 goto out;
2046err_noinitval:
2047 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2048 err = -ENOENT;
2049 goto error;
2050}
2051
2052static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2053{
58e5528e 2054 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a
JL		 2055 const u32 *data;
2056 unsigned int i, len;
2057
f222313a 2058 /* Upload Microcode. */
58e5528e
MB		 2059 data = (u32 *)(phy->ucode->data);
2060 len = phy->ucode->size / sizeof(u32);
f222313a
JL		 2061 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2062 for (i = 0; i < len; i++) {
2063 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2064 be32_to_cpu(data[i]));
2065 udelay(10);
2066 }
2067
2068 /* Upload PCM data. */
58e5528e
MB		 2069 data = (u32 *)(phy->pcm->data);
2070 len = phy->pcm->size / sizeof(u32);
f222313a
JL		 2071 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2072 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2073 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2074 for (i = 0; i < len; i++) {
2075 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2076 be32_to_cpu(data[i]));
2077 udelay(10);
2078 }
f222313a
JL		 2079}
2080
a4a600d3
MB		 2081static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2082 const struct bcm43xx_initval *data,
2083 const unsigned int len)
f222313a
JL		 2084{
2085 u16 offset, size;
2086 u32 value;
2087 unsigned int i;
2088
2089 for (i = 0; i < len; i++) {
2090 offset = be16_to_cpu(data[i].offset);
2091 size = be16_to_cpu(data[i].size);
2092 value = be32_to_cpu(data[i].value);
2093
a4a600d3
MB		 2094 if (unlikely(offset >= 0x1000))
2095 goto err_format;
2096 if (size == 2) {
2097 if (unlikely(value & 0xFFFF0000))
2098 goto err_format;
2099 bcm43xx_write16(bcm, offset, (u16)value);
2100 } else if (size == 4) {
f222313a 2101 bcm43xx_write32(bcm, offset, value);
a4a600d3
MB		 2102 } else
2103 goto err_format;
f222313a 2104 }
a4a600d3
MB		 2105
2106 return 0;
2107
2108err_format:
2109 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2110 "Please fix your bcm43xx firmware files.\n");
2111 return -EPROTO;
f222313a
JL		 2112}
2113
a4a600d3 2114static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
f222313a 2115{
58e5528e 2116 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
a4a600d3
MB		 2117 int err;
2118
58e5528e
MB		 2119 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals0->data,
2120 phy->initvals0->size / sizeof(struct bcm43xx_initval));
a4a600d3
MB		 2121 if (err)
2122 goto out;
58e5528e
MB		 2123 if (phy->initvals1) {
2124 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals1->data,
2125 phy->initvals1->size / sizeof(struct bcm43xx_initval));
a4a600d3
MB		 2126 if (err)
2127 goto out;
f222313a 2128 }
a4a600d3 2129out:
a4a600d3 2130 return err;
f222313a
JL		 2131}
2132
12a37687
JS		 2133#ifdef CONFIG_BCM947XX
2134static struct pci_device_id bcm43xx_47xx_ids[] = {
2135 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
2136 { 0 }
2137};
2138#endif
2139
f222313a
JL		 2140static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2141{
58e5528e 2142 int err;
f222313a
JL		 2143
2144 bcm->irq = bcm->pci_dev->irq;
2145#ifdef CONFIG_BCM947XX
2146 if (bcm->pci_dev->bus->number == 0) {
12a37687
JS		 2147 struct pci_dev *d;
2148 struct pci_device_id *id;
2149 for (id = bcm43xx_47xx_ids; id->vendor; id++) {
2150 d = pci_get_device(id->vendor, id->device, NULL);
2151 if (d != NULL) {
2152 bcm->irq = d->irq;
2153 pci_dev_put(d);
2154 break;
2155 }
f222313a
JL		 2156 }
2157 }
2158#endif
58e5528e 2159 err = request_irq(bcm->irq, bcm43xx_interrupt_handler,
1fb9df5d 2160 IRQF_SHARED, KBUILD_MODNAME, bcm);
58e5528e 2161 if (err)
f222313a 2162 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
f222313a 2163
58e5528e 2164 return err;
f222313a
JL		 2165}
2166
2167/* Switch to the core used to write the GPIO register.
2168 * This is either the ChipCommon, or the PCI core.
2169 */
489423c8 2170static int switch_to_gpio_core(struct bcm43xx_private *bcm)
f222313a
JL		 2171{
2172 int err;
2173
2174 /* Where to find the GPIO register depends on the chipset.
2175 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2176 * control register. Otherwise the register at offset 0x6c in the
2177 * PCI core is the GPIO control register.
2178 */
2179 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2180 if (err == -ENODEV) {
2181 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
489423c8 2182 if (unlikely(err == -ENODEV)) {
f222313a
JL		 2183 printk(KERN_ERR PFX "gpio error: "
2184 "Neither ChipCommon nor PCI core available!\n");
714eece7
MB		 2185 }
2186 }
f222313a 2187
714eece7 2188 return err;
f222313a
JL		 2189}
2190
2191/* Initialize the GPIOs
2192 * http://bcm-specs.sipsolutions.net/GPIO
2193 */
2194static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2195{
2196 struct bcm43xx_coreinfo *old_core;
2197 int err;
714eece7 2198 u32 mask, set;
f222313a 2199
714eece7
MB		 2200 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2201 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2202 & 0xFFFF3FFF);
f222313a 2203
714eece7 2204 bcm43xx_leds_switch_all(bcm, 0);
f222313a
JL		 2205 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2206 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2207
714eece7
MB		 2208 mask = 0x0000001F;
2209 set = 0x0000000F;
f222313a 2210 if (bcm->chip_id == 0x4301) {
714eece7
MB		 2211 mask |= 0x0060;
2212 set |= 0x0060;
2213 }
2214 if (0 /* FIXME: conditional unknown */) {
2215 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2216 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2217 | 0x0100);
2218 mask |= 0x0180;
2219 set |= 0x0180;
f222313a
JL		 2220 }
2221 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
714eece7
MB		 2222 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2223 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2224 | 0x0200);
2225 mask |= 0x0200;
2226 set |= 0x0200;
f222313a 2227 }
714eece7
MB		 2228 if (bcm->current_core->rev >= 2)
2229 mask |= 0x0010; /* FIXME: This is redundant. */
f222313a 2230
714eece7
MB		 2231 old_core = bcm->current_core;
2232 err = switch_to_gpio_core(bcm);
2233 if (err)
2234 goto out;
f222313a 2235 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
714eece7 2236 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
f222313a 2237 err = bcm43xx_switch_core(bcm, old_core);
714eece7
MB		 2238out:
2239 return err;
f222313a
JL		 2240}
2241
2242/* Turn off all GPIO stuff. Call this on module unload, for example. */
2243static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2244{
2245 struct bcm43xx_coreinfo *old_core;
2246 int err;
2247
2248 old_core = bcm->current_core;
2249 err = switch_to_gpio_core(bcm);
2250 if (err)
2251 return err;
2252 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2253 err = bcm43xx_switch_core(bcm, old_core);
2254 assert(err == 0);
2255
2256 return 0;
2257}
2258
2259/* http://bcm-specs.sipsolutions.net/EnableMac */
2260void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2261{
062caf43
MB		 2262 bcm->mac_suspended--;
2263 assert(bcm->mac_suspended >= 0);
2264 if (bcm->mac_suspended == 0) {
2265 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2266 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2267 | BCM43xx_SBF_MAC_ENABLED);
2268 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2269 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2270 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2271 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2272 }
f222313a
JL		 2273}
2274
2275/* http://bcm-specs.sipsolutions.net/SuspendMAC */
2276void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2277{
2278 int i;
2279 u32 tmp;
2280
062caf43
MB		 2281 assert(bcm->mac_suspended >= 0);
2282 if (bcm->mac_suspended == 0) {
2283 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2284 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2285 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2286 & ~BCM43xx_SBF_MAC_ENABLED);
2287 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
48c86da1 2288 for (i = 10000; i; i--) {
062caf43
MB		 2289 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2290 if (tmp & BCM43xx_IRQ_READY)
2291 goto out;
b8e7cdb3 2292 udelay(1);
062caf43
MB		 2293 }
2294 printkl(KERN_ERR PFX "MAC suspend failed\n");
f222313a 2295 }
062caf43
MB		 2296out:
2297 bcm->mac_suspended++;
f222313a
JL		 2298}
2299
2300void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2301 int iw_mode)
2302{
2303 unsigned long flags;
6ab5b8e6 2304 struct net_device *net_dev = bcm->net_dev;
f222313a 2305 u32 status;
6ab5b8e6 2306 u16 value;
f222313a
JL		 2307
2308 spin_lock_irqsave(&bcm->ieee->lock, flags);
2309 bcm->ieee->iw_mode = iw_mode;
2310 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2311 if (iw_mode == IW_MODE_MONITOR)
6ab5b8e6 2312 net_dev->type = ARPHRD_IEEE80211;
f222313a 2313 else
6ab5b8e6 2314 net_dev->type = ARPHRD_ETHER;
f222313a 2315
f222313a
JL		 2316 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2317 /* Reset status to infrastructured mode */
2318 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
6ab5b8e6
MB		 2319 status &= ~BCM43xx_SBF_MODE_PROMISC;
2320 status |= BCM43xx_SBF_MODE_NOTADHOC;
2321
2322/* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2323status |= BCM43xx_SBF_MODE_PROMISC;
f222313a
JL		 2324
2325 switch (iw_mode) {
2326 case IW_MODE_MONITOR:
6ab5b8e6
MB		 2327 status |= BCM43xx_SBF_MODE_MONITOR;
2328 status |= BCM43xx_SBF_MODE_PROMISC;
f222313a
JL		 2329 break;
2330 case IW_MODE_ADHOC:
2331 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2332 break;
2333 case IW_MODE_MASTER:
6ab5b8e6
MB		 2334 status |= BCM43xx_SBF_MODE_AP;
2335 break;
f222313a
JL		 2336 case IW_MODE_SECOND:
2337 case IW_MODE_REPEAT:
6ab5b8e6 2338 TODO(); /* TODO */
f222313a
JL		 2339 break;
2340 case IW_MODE_INFRA:
2341 /* nothing to be done here... */
2342 break;
2343 default:
6ab5b8e6 2344 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
f222313a 2345 }
6ab5b8e6
MB		 2346 if (net_dev->flags & IFF_PROMISC)
2347 status |= BCM43xx_SBF_MODE_PROMISC;
f222313a 2348 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
6ab5b8e6
MB		 2349
2350 value = 0x0002;
2351 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2352 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2353 value = 0x0064;
2354 else
2355 value = 0x0032;
2356 }
2357 bcm43xx_write16(bcm, 0x0612, value);
f222313a
JL		 2358}
2359
2360/* This is the opposite of bcm43xx_chip_init() */
2361static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2362{
2363 bcm43xx_radio_turn_off(bcm);
2364 if (!modparam_noleds)
2365 bcm43xx_leds_exit(bcm);
2366 bcm43xx_gpio_cleanup(bcm);
a4a600d3 2367 bcm43xx_release_firmware(bcm, 0);
f222313a
JL		 2368}
2369
2370/* Initialize the chip
2371 * http://bcm-specs.sipsolutions.net/ChipInit
2372 */
2373static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2374{
e9357c05
MB		 2375 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2376 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a 2377 int err;
58e5528e 2378 int i, tmp;
f222313a
JL		 2379 u32 value32;
2380 u16 value16;
2381
2382 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2383 BCM43xx_SBF_CORE_READY
2384 | BCM43xx_SBF_400);
2385
2386 err = bcm43xx_request_firmware(bcm);
2387 if (err)
2388 goto out;
2389 bcm43xx_upload_microcode(bcm);
2390
58e5528e
MB		 2391 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xFFFFFFFF);
2392 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2393 i = 0;
2394 while (1) {
2395 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2396 if (value32 == BCM43xx_IRQ_READY)
2397 break;
2398 i++;
2399 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2400 printk(KERN_ERR PFX "IRQ_READY timeout\n");
2401 err = -ENODEV;
2402 goto err_release_fw;
2403 }
2404 udelay(10);
2405 }
2406 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
f222313a 2407
1ef4583e
LF		 2408 value16 = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2409 BCM43xx_UCODE_REVISION);
2410
2411 dprintk(KERN_INFO PFX "Microcode rev 0x%x, pl 0x%x "
2412 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", value16,
2413 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2414 BCM43xx_UCODE_PATCHLEVEL),
2415 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2416 BCM43xx_UCODE_DATE) >> 12) & 0xf,
2417 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2418 BCM43xx_UCODE_DATE) >> 8) & 0xf,
2419 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2420 BCM43xx_UCODE_DATE) & 0xff,
2421 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2422 BCM43xx_UCODE_TIME) >> 11) & 0x1f,
2423 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2424 BCM43xx_UCODE_TIME) >> 5) & 0x3f,
2425 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2426 BCM43xx_UCODE_TIME) & 0x1f);
2427
2428 if ( value16 > 0x128 ) {
8aeb9fc5
LF		 2429 printk(KERN_ERR PFX
2430 "Firmware: no support for microcode extracted "
2431 "from version 4.x binary drivers.\n");
2432 err = -EOPNOTSUPP;
1ef4583e
LF		 2433 goto err_release_fw;
2434 }
2435
f222313a
JL		 2436 err = bcm43xx_gpio_init(bcm);
2437 if (err)
58e5528e 2438 goto err_release_fw;
f222313a 2439
a4a600d3
MB		 2440 err = bcm43xx_upload_initvals(bcm);
2441 if (err)
2442 goto err_gpio_cleanup;
f222313a 2443 bcm43xx_radio_turn_on(bcm);
01917382
LF		 2444 bcm->radio_hw_enable = bcm43xx_is_hw_radio_enabled(bcm);
2445 dprintk(KERN_INFO PFX "Radio %s by hardware\n",
2446 (bcm->radio_hw_enable == 0) ? "disabled" : "enabled");
f222313a 2447
f222313a
JL		 2448 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2449 err = bcm43xx_phy_init(bcm);
2450 if (err)
2451 goto err_radio_off;
2452
2453 /* Select initial Interference Mitigation. */
e9357c05
MB		 2454 tmp = radio->interfmode;
2455 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
f222313a
JL		 2456 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2457
2458 bcm43xx_phy_set_antenna_diversity(bcm);
2459 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
e9357c05 2460 if (phy->type == BCM43xx_PHYTYPE_B) {
f222313a
JL		 2461 value16 = bcm43xx_read16(bcm, 0x005E);
2462 value16 |= 0x0004;
2463 bcm43xx_write16(bcm, 0x005E, value16);
2464 }
2465 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2466 if (bcm->current_core->rev < 5)
2467 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2468
2469 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2470 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2471 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2472 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2473 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2474 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
f222313a 2475
f222313a 2476 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
6ab5b8e6 2477 value32 |= 0x100000;
f222313a
JL		 2478 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2479
77db31ea 2480 if (bcm43xx_using_pio(bcm)) {
f222313a
JL		 2481 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2482 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2483 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2484 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2485 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2486 }
2487
2488 /* Probe Response Timeout value */
2489 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2490 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2491
6ab5b8e6
MB		 2492 /* Initially set the wireless operation mode. */
2493 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
f222313a
JL		 2494
2495 if (bcm->current_core->rev < 3) {
2496 bcm43xx_write16(bcm, 0x060E, 0x0000);
2497 bcm43xx_write16(bcm, 0x0610, 0x8000);
2498 bcm43xx_write16(bcm, 0x0604, 0x0000);
2499 bcm43xx_write16(bcm, 0x0606, 0x0200);
2500 } else {
2501 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2502 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2503 }
2504 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
9218e02b
MB		 2505 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2506 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
f222313a 2507 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
9218e02b
MB		 2508 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2509 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2510 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
f222313a
JL		 2511
2512 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2513 value32 |= 0x00100000;
2514 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2515
2516 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2517
2518 assert(err == 0);
2519 dprintk(KERN_INFO PFX "Chip initialized\n");
2520out:
2521 return err;
2522
2523err_radio_off:
2524 bcm43xx_radio_turn_off(bcm);
a4a600d3 2525err_gpio_cleanup:
f222313a 2526 bcm43xx_gpio_cleanup(bcm);
a4a600d3
MB		 2527err_release_fw:
2528 bcm43xx_release_firmware(bcm, 1);
f222313a
JL		 2529 goto out;
2530}
2531
2532/* Validate chip access
2533 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2534static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2535{
f222313a
JL		 2536 u32 value;
2537 u32 shm_backup;
2538
2539 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2540 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
489423c8
MB		 2541 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2542 goto error;
f222313a 2543 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
489423c8
MB		 2544 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2545 goto error;
f222313a
JL		 2546 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2547
2548 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
489423c8
MB		 2549 if ((value | 0x80000000) != 0x80000400)
2550 goto error;
f222313a
JL		 2551
2552 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
489423c8
MB		 2553 if (value != 0x00000000)
2554 goto error;
f222313a 2555
489423c8
MB		 2556 return 0;
2557error:
2558 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2559 return -ENODEV;
f222313a
JL		 2560}
2561
8afceb1e 2562static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
e9357c05
MB		 2563{
2564 /* Initialize a "phyinfo" structure. The structure is already
2565 * zeroed out.
58e5528e 2566 * This is called on insmod time to initialize members.
e9357c05 2567 */
e9357c05 2568 phy->savedpctlreg = 0xFFFF;
e9357c05
MB		 2569 spin_lock_init(&phy->lock);
2570}
2571
8afceb1e 2572static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
e9357c05
MB		 2573{
2574 /* Initialize a "radioinfo" structure. The structure is already
2575 * zeroed out.
58e5528e 2576 * This is called on insmod time to initialize members.
e9357c05
MB		 2577 */
2578 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2579 radio->channel = 0xFF;
2580 radio->initial_channel = 0xFF;
e9357c05
MB		 2581}
2582
f222313a
JL		 2583static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2584{
2585 int err, i;
2586 int current_core;
2587 u32 core_vendor, core_id, core_rev;
2588 u32 sb_id_hi, chip_id_32 = 0;
2589 u16 pci_device, chip_id_16;
2590 u8 core_count;
2591
2592 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2593 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
f222313a
JL		 2594 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2595 * BCM43xx_MAX_80211_CORES);
e9357c05
MB		 2596 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2597 * BCM43xx_MAX_80211_CORES);
e9357c05
MB		 2598 bcm->nr_80211_available = 0;
2599 bcm->current_core = NULL;
2600 bcm->active_80211_core = NULL;
f222313a
JL		 2601
2602 /* map core 0 */
2603 err = _switch_core(bcm, 0);
2604 if (err)
2605 goto out;
2606
2607 /* fetch sb_id_hi from core information registers */
2608 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2609
f3d1fca3
SB		 2610 core_id = (sb_id_hi & 0x8FF0) >> 4;
2611 core_rev = (sb_id_hi & 0x7000) >> 8;
2612 core_rev |= (sb_id_hi & 0xF);
f222313a
JL		 2613 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2614
2615 /* if present, chipcommon is always core 0; read the chipid from it */
2616 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2617 chip_id_32 = bcm43xx_read32(bcm, 0);
2618 chip_id_16 = chip_id_32 & 0xFFFF;
e9357c05 2619 bcm->core_chipcommon.available = 1;
f222313a
JL		 2620 bcm->core_chipcommon.id = core_id;
2621 bcm->core_chipcommon.rev = core_rev;
2622 bcm->core_chipcommon.index = 0;
2623 /* While we are at it, also read the capabilities. */
2624 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2625 } else {
2626 /* without a chipCommon, use a hard coded table. */
2627 pci_device = bcm->pci_dev->device;
2628 if (pci_device == 0x4301)
2629 chip_id_16 = 0x4301;
2630 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2631 chip_id_16 = 0x4307;
2632 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2633 chip_id_16 = 0x4402;
2634 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2635 chip_id_16 = 0x4610;
2636 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2637 chip_id_16 = 0x4710;
2638#ifdef CONFIG_BCM947XX
2639 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2640 chip_id_16 = 0x4309;
2641#endif
2642 else {
2643 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2644 return -ENODEV;
2645 }
2646 }
2647
2648 /* ChipCommon with Core Rev >=4 encodes number of cores,
2649 * otherwise consult hardcoded table */
2650 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2651 core_count = (chip_id_32 & 0x0F000000) >> 24;
2652 } else {
2653 switch (chip_id_16) {
2654 case 0x4610:
2655 case 0x4704:
2656 case 0x4710:
2657 core_count = 9;
2658 break;
2659 case 0x4310:
2660 core_count = 8;
2661 break;
2662 case 0x5365:
2663 core_count = 7;
2664 break;
2665 case 0x4306:
2666 core_count = 6;
2667 break;
2668 case 0x4301:
2669 case 0x4307:
2670 core_count = 5;
2671 break;
2672 case 0x4402:
2673 core_count = 3;
2674 break;
2675 default:
2676 /* SOL if we get here */
2677 assert(0);
2678 core_count = 1;
2679 }
2680 }
2681
2682 bcm->chip_id = chip_id_16;
adc40e97
MB		 2683 bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
2684 bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
f222313a
JL		 2685
2686 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2687 bcm->chip_id, bcm->chip_rev);
2688 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
e9357c05 2689 if (bcm->core_chipcommon.available) {
7f424ff4
LF		 2690 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2691 core_id, core_rev, core_vendor);
f222313a 2692 current_core = 1;
7f424ff4 2693 } else
f222313a
JL		 2694 current_core = 0;
2695 for ( ; current_core < core_count; current_core++) {
2696 struct bcm43xx_coreinfo *core;
e9357c05 2697 struct bcm43xx_coreinfo_80211 *ext_80211;
f222313a
JL		 2698
2699 err = _switch_core(bcm, current_core);
2700 if (err)
2701 goto out;
2702 /* Gather information */
2703 /* fetch sb_id_hi from core information registers */
2704 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2705
2706 /* extract core_id, core_rev, core_vendor */
10764889
LF		 2707 core_id = (sb_id_hi & 0x8FF0) >> 4;
2708 core_rev = ((sb_id_hi & 0xF) | ((sb_id_hi & 0x7000) >> 8));
f222313a
JL		 2709 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2710
7f424ff4
LF		 2711 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2712 current_core, core_id, core_rev, core_vendor);
f222313a
JL		 2713
2714 core = NULL;
2715 switch (core_id) {
2716 case BCM43xx_COREID_PCI:
f3d1fca3 2717 case BCM43xx_COREID_PCIE:
f222313a 2718 core = &bcm->core_pci;
e9357c05 2719 if (core->available) {
f222313a
JL		 2720 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2721 continue;
2722 }
2723 break;
f222313a
JL		 2724 case BCM43xx_COREID_80211:
2725 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2726 core = &(bcm->core_80211[i]);
e9357c05
MB		 2727 ext_80211 = &(bcm->core_80211_ext[i]);
2728 if (!core->available)
f222313a
JL		 2729 break;
2730 core = NULL;
2731 }
2732 if (!core) {
2733 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2734 BCM43xx_MAX_80211_CORES);
2735 continue;
2736 }
2737 if (i != 0) {
2738 /* More than one 80211 core is only supported
2739 * by special chips.
2740 * There are chips with two 80211 cores, but with
2741 * dangling pins on the second core. Be careful
2742 * and ignore these cores here.
2743 */
2744 if (bcm->pci_dev->device != 0x4324) {
2745 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2746 continue;
2747 }
2748 }
2749 switch (core_rev) {
2750 case 2:
2751 case 4:
2752 case 5:
2753 case 6:
2754 case 7:
2755 case 9:
f3d1fca3 2756 case 10:
f222313a
JL		 2757 break;
2758 default:
f3d1fca3
SB		 2759 printk(KERN_WARNING PFX
2760 "Unsupported 80211 core revision %u\n",
f222313a 2761 core_rev);
f222313a 2762 }
e9357c05 2763 bcm->nr_80211_available++;
58e5528e 2764 core->priv = ext_80211;
e9357c05
MB		 2765 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2766 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
f222313a
JL		 2767 break;
2768 case BCM43xx_COREID_CHIPCOMMON:
2769 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2770 break;
f222313a
JL		 2771 }
2772 if (core) {
e9357c05 2773 core->available = 1;
f222313a
JL		 2774 core->id = core_id;
2775 core->rev = core_rev;
2776 core->index = current_core;
2777 }
2778 }
2779
e9357c05 2780 if (!bcm->core_80211[0].available) {
f222313a
JL		 2781 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2782 err = -ENODEV;
2783 goto out;
2784 }
2785
2786 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2787
2788 assert(err == 0);
2789out:
2790 return err;
2791}
2792
2793static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2794{
2795 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2796 u8 *bssid = bcm->ieee->bssid;
2797
2798 switch (bcm->ieee->iw_mode) {
2799 case IW_MODE_ADHOC:
2800 random_ether_addr(bssid);
2801 break;
2802 case IW_MODE_MASTER:
2803 case IW_MODE_INFRA:
2804 case IW_MODE_REPEAT:
2805 case IW_MODE_SECOND:
2806 case IW_MODE_MONITOR:
2807 memcpy(bssid, mac, ETH_ALEN);
2808 break;
2809 default:
2810 assert(0);
2811 }
2812}
2813
2814static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2815 u16 rate,
2816 int is_ofdm)
2817{
2818 u16 offset;
2819
2820 if (is_ofdm) {
2821 offset = 0x480;
2822 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2823 }
2824 else {
2825 offset = 0x4C0;
2826 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2827 }
2828 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2829 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2830}
2831
2832static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2833{
e9357c05 2834 switch (bcm43xx_current_phy(bcm)->type) {
f222313a
JL		 2835 case BCM43xx_PHYTYPE_A:
2836 case BCM43xx_PHYTYPE_G:
2837 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2838 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2839 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2840 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2841 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2842 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2843 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2844 case BCM43xx_PHYTYPE_B:
2845 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2846 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2847 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2848 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2849 break;
2850 default:
2851 assert(0);
2852 }
2853}
2854
2855static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2856{
2857 bcm43xx_chip_cleanup(bcm);
2858 bcm43xx_pio_free(bcm);
2859 bcm43xx_dma_free(bcm);
2860
e9357c05 2861 bcm->current_core->initialized = 0;
f222313a
JL		 2862}
2863
2864/* http://bcm-specs.sipsolutions.net/80211Init */
58e5528e
MB		 2865static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2866 int active_wlcore)
f222313a 2867{
e9357c05
MB		 2868 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2869 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
f222313a
JL		 2870 u32 ucodeflags;
2871 int err;
2872 u32 sbimconfiglow;
2873 u8 limit;
2874
f3d1fca3 2875 if (bcm->core_pci.rev <= 5 && bcm->core_pci.id != BCM43xx_COREID_PCIE) {
f222313a
JL		 2876 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2877 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2878 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
10764889
LF		 2879 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2880 sbimconfiglow |= 0x32;
2881 else
2882 sbimconfiglow |= 0x53;
f222313a
JL		 2883 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2884 }
2885
2886 bcm43xx_phy_calibrate(bcm);
2887 err = bcm43xx_chip_init(bcm);
2888 if (err)
2889 goto out;
2890
2891 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2892 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2893
2894 if (0 /*FIXME: which condition has to be used here? */)
2895 ucodeflags |= 0x00000010;
2896
2897 /* HW decryption needs to be set now */
2898 ucodeflags |= 0x40000000;
2899
e9357c05 2900 if (phy->type == BCM43xx_PHYTYPE_G) {
f222313a 2901 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
e9357c05 2902 if (phy->rev == 1)
f222313a
JL		 2903 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2904 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2905 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
e9357c05 2906 } else if (phy->type == BCM43xx_PHYTYPE_B) {
f222313a 2907 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
e9357c05 2908 if (phy->rev >= 2 && radio->version == 0x2050)
f222313a
JL		 2909 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2910 }
2911
2912 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2913 BCM43xx_UCODEFLAGS_OFFSET)) {
2914 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2915 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2916 }
2917
2918 /* Short/Long Retry Limit.
2919 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2920 * the chip-internal counter.
2921 */
2922 limit = limit_value(modparam_short_retry, 0, 0xF);
2923 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2924 limit = limit_value(modparam_long_retry, 0, 0xF);
2925 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2926
2927 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2928 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2929
2930 bcm43xx_rate_memory_init(bcm);
2931
2932 /* Minimum Contention Window */
e9357c05 2933 if (phy->type == BCM43xx_PHYTYPE_B)
f222313a
JL		 2934 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2935 else
2936 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2937 /* Maximum Contention Window */
2938 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2939
2940 bcm43xx_gen_bssid(bcm);
2941 bcm43xx_write_mac_bssid_templates(bcm);
2942
2943 if (bcm->current_core->rev >= 5)
2944 bcm43xx_write16(bcm, 0x043C, 0x000C);
2945
58e5528e 2946 if (active_wlcore) {
8da81e52 2947 if (bcm43xx_using_pio(bcm)) {
58e5528e 2948 err = bcm43xx_pio_init(bcm);
8da81e52 2949 } else {
58e5528e 2950 err = bcm43xx_dma_init(bcm);
8da81e52
LF		 2951 if (err == -ENOSYS)
2952 err = bcm43xx_pio_init(bcm);
2953 }
58e5528e
MB		 2954 if (err)
2955 goto err_chip_cleanup;
2956 }
f222313a
JL		 2957 bcm43xx_write16(bcm, 0x0612, 0x0050);
2958 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2959 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2960
58e5528e
MB		 2961 if (active_wlcore) {
2962 if (radio->initial_channel != 0xFF)
2963 bcm43xx_radio_selectchannel(bcm, radio->initial_channel, 0);
2964 }
f222313a 2965
58e5528e
MB		 2966 /* Don't enable MAC/IRQ here, as it will race with the IRQ handler.
2967 * We enable it later.
2968 */
e9357c05 2969 bcm->current_core->initialized = 1;
f222313a
JL		 2970out:
2971 return err;
2972
2973err_chip_cleanup:
2974 bcm43xx_chip_cleanup(bcm);
2975 goto out;
2976}
2977
2978static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2979{
2980 int err;
2981 u16 pci_status;
2982
2983 err = bcm43xx_pctl_set_crystal(bcm, 1);
2984 if (err)
2985 goto out;
2986 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2987 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2988
2989out:
2990 return err;
2991}
2992
2993static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2994{
2995 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2996 bcm43xx_pctl_set_crystal(bcm, 0);
2997}
2998
489423c8
MB		 2999static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
3000 u32 address,
3001 u32 data)
f222313a
JL		 3002{
3003 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
3004 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
3005}
3006
3007static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
3008{
f3d1fca3 3009 int err = 0;
f222313a 3010
f3d1fca3 3011 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
f222313a 3012
f3d1fca3
SB		 3013 if (bcm->core_chipcommon.available) {
3014 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
3015 if (err)
3016 goto out;
3017
3018 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3019
3020 /* this function is always called when a PCI core is mapped */
3021 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3022 if (err)
3023 goto out;
3024 } else
3025 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3026
3027 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
f222313a 3028
f222313a
JL		 3029out:
3030 return err;
3031}
3032
f3d1fca3
SB		 3033static u32 bcm43xx_pcie_reg_read(struct bcm43xx_private *bcm, u32 address)
3034{
3035 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3036 return bcm43xx_read32(bcm, BCM43xx_PCIECORE_REG_DATA);
3037}
3038
3039static void bcm43xx_pcie_reg_write(struct bcm43xx_private *bcm, u32 address,
3040 u32 data)
3041{
3042 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3043 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_DATA, data);
3044}
3045
3046static void bcm43xx_pcie_mdio_write(struct bcm43xx_private *bcm, u8 dev, u8 reg,
3047 u16 data)
3048{
3049 int i;
3050
3051 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0x0082);
3052 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_DATA, BCM43xx_PCIE_MDIO_ST |
3053 BCM43xx_PCIE_MDIO_WT | (dev << BCM43xx_PCIE_MDIO_DEV) |
3054 (reg << BCM43xx_PCIE_MDIO_REG) | BCM43xx_PCIE_MDIO_TA |
3055 data);
3056 udelay(10);
3057
3058 for (i = 0; i < 10; i++) {
3059 if (bcm43xx_read32(bcm, BCM43xx_PCIECORE_MDIO_CTL) &
3060 BCM43xx_PCIE_MDIO_TC)
3061 break;
3062 msleep(1);
3063 }
3064 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0);
3065}
3066
f222313a
JL		 3067/* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
3068 * To enable core 0, pass a core_mask of 1<<0
3069 */
3070static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3071 u32 core_mask)
3072{
3073 u32 backplane_flag_nr;
3074 u32 value;
3075 struct bcm43xx_coreinfo *old_core;
3076 int err = 0;
3077
3078 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
3079 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
3080
3081 old_core = bcm->current_core;
3082 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3083 if (err)
3084 goto out;
3085
10764889 3086 if (bcm->current_core->rev < 6 &&
f3d1fca3 3087 bcm->current_core->id == BCM43xx_COREID_PCI) {
f222313a
JL		 3088 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3089 value |= (1 << backplane_flag_nr);
3090 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
3091 } else {
3092 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3093 if (err) {
3094 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3095 goto out_switch_back;
3096 }
3097 value |= core_mask << 8;
3098 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3099 if (err) {
3100 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3101 goto out_switch_back;
3102 }
3103 }
3104
f3d1fca3
SB		 3105 if (bcm->current_core->id == BCM43xx_COREID_PCI) {
3106 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3107 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3108 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3109
3110 if (bcm->current_core->rev < 5) {
3111 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3112 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3113 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3114 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3115 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3116 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3117 err = bcm43xx_pcicore_commit_settings(bcm);
3118 assert(err == 0);
3119 } else if (bcm->current_core->rev >= 11) {
3120 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3121 value |= BCM43xx_SBTOPCI2_MEMREAD_MULTI;
3122 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3123 }
3124 } else {
3125 if (bcm->current_core->rev == 0 || bcm->current_core->rev == 1) {
3126 value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_TLP_WORKAROUND);
3127 value |= 0x8;
3128 bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_TLP_WORKAROUND,
3129 value);
3130 }
3131 if (bcm->current_core->rev == 0) {
3132 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3133 BCM43xx_SERDES_RXTIMER, 0x8128);
3134 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3135 BCM43xx_SERDES_CDR, 0x0100);
3136 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3137 BCM43xx_SERDES_CDR_BW, 0x1466);
3138 } else if (bcm->current_core->rev == 1) {
3139 value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_DLLP_LINKCTL);
3140 value |= 0x40;
3141 bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_DLLP_LINKCTL,
3142 value);
3143 }
f222313a 3144 }
f222313a
JL		 3145out_switch_back:
3146 err = bcm43xx_switch_core(bcm, old_core);
3147out:
3148 return err;
3149}
3150
ab4977f8 3151static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
f222313a 3152{
e9357c05 3153 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a 3154
ab4977f8
MB		 3155 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3156 return;
f222313a 3157
ab4977f8
MB		 3158 bcm43xx_mac_suspend(bcm);
3159 bcm43xx_phy_lo_g_measure(bcm);
3160 bcm43xx_mac_enable(bcm);
f222313a
JL		 3161}
3162
ab4977f8 3163static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
f222313a 3164{
f222313a
JL		 3165 bcm43xx_phy_lo_mark_all_unused(bcm);
3166 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3167 bcm43xx_mac_suspend(bcm);
3168 bcm43xx_calc_nrssi_slope(bcm);
3169 bcm43xx_mac_enable(bcm);
3170 }
f222313a
JL		 3171}
3172
ab4977f8 3173static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
f222313a 3174{
ab4977f8
MB		 3175 /* Update device statistics. */
3176 bcm43xx_calculate_link_quality(bcm);
3177}
f222313a 3178
ab4977f8 3179static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
01917382
LF		 3180{
3181 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3182 //TODO for APHY (temperature?)
3183}
3184
3185static void bcm43xx_periodic_every1sec(struct bcm43xx_private *bcm)
ab4977f8 3186{
e9357c05
MB		 3187 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3188 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
01917382 3189 int radio_hw_enable;
f222313a 3190
01917382
LF		 3191 /* check if radio hardware enabled status changed */
3192 radio_hw_enable = bcm43xx_is_hw_radio_enabled(bcm);
3193 if (unlikely(bcm->radio_hw_enable != radio_hw_enable)) {
3194 bcm->radio_hw_enable = radio_hw_enable;
3195 dprintk(KERN_INFO PFX "Radio hardware status changed to %s\n",
3196 (radio_hw_enable == 0) ? "disabled" : "enabled");
3197 bcm43xx_leds_update(bcm, 0);
3198 }
ab4977f8
MB		 3199 if (phy->type == BCM43xx_PHYTYPE_G) {
3200 //TODO: update_aci_moving_average
3201 if (radio->aci_enable && radio->aci_wlan_automatic) {
3202 bcm43xx_mac_suspend(bcm);
3203 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3204 if (0 /*TODO: bunch of conditions*/) {
3205 bcm43xx_radio_set_interference_mitigation(bcm,
3206 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3207 }
3208 } else if (1/*TODO*/) {
3209 /*
3210 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3211 bcm43xx_radio_set_interference_mitigation(bcm,
3212 BCM43xx_RADIO_INTERFMODE_NONE);
3213 }
3214 */
3215 }
3216 bcm43xx_mac_enable(bcm);
3217 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3218 phy->rev == 1) {
3219 //TODO: implement rev1 workaround
3220 }
f222313a 3221 }
f222313a
JL		 3222}
3223
91769e7d 3224static void do_periodic_work(struct bcm43xx_private *bcm)
f222313a 3225{
01917382 3226 if (bcm->periodic_state % 120 == 0)
ab4977f8 3227 bcm43xx_periodic_every120sec(bcm);
01917382 3228 if (bcm->periodic_state % 60 == 0)
ab4977f8 3229 bcm43xx_periodic_every60sec(bcm);
01917382 3230 if (bcm->periodic_state % 30 == 0)
ab4977f8 3231 bcm43xx_periodic_every30sec(bcm);
01917382
LF		 3232 if (bcm->periodic_state % 15 == 0)
3233 bcm43xx_periodic_every15sec(bcm);
3234 bcm43xx_periodic_every1sec(bcm);
ab4977f8 3235
01917382 3236 schedule_delayed_work(&bcm->periodic_work, HZ);
91769e7d 3237}
f222313a 3238
c4028958 3239static void bcm43xx_periodic_work_handler(struct work_struct *work)
91769e7d 3240{
c4028958
DH		 3241 struct bcm43xx_private *bcm =
3242 container_of(work, struct bcm43xx_private, periodic_work.work);
81e171b9 3243 struct net_device *net_dev = bcm->net_dev;
91769e7d
MB		 3244 unsigned long flags;
3245 u32 savedirqs = 0;
81e171b9 3246 unsigned long orig_trans_start = 0;
91769e7d 3247
3693ec67 3248 mutex_lock(&bcm->mutex);
01917382 3249 if (unlikely(bcm->periodic_state % 60 == 0)) {
91769e7d
MB		 3250 /* Periodic work will take a long time, so we want it to
3251 * be preemtible.
3252 */
81e171b9
MB		 3253
3254 netif_tx_lock_bh(net_dev);
3255 /* We must fake a started transmission here, as we are going to
3256 * disable TX. If we wouldn't fake a TX, it would be possible to
3257 * trigger the netdev watchdog, if the last real TX is already
3258 * some time on the past (slightly less than 5secs)
3259 */
3260 orig_trans_start = net_dev->trans_start;
3261 net_dev->trans_start = jiffies;
3262 netif_stop_queue(net_dev);
3263 netif_tx_unlock_bh(net_dev);
3264
efa6a370 3265 spin_lock_irqsave(&bcm->irq_lock, flags);
062caf43 3266 bcm43xx_mac_suspend(bcm);
91769e7d
MB		 3267 if (bcm43xx_using_pio(bcm))
3268 bcm43xx_pio_freeze_txqueues(bcm);
3269 savedirqs = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
efa6a370 3270 spin_unlock_irqrestore(&bcm->irq_lock, flags);
91769e7d
MB		 3271 bcm43xx_synchronize_irq(bcm);
3272 } else {
3273 /* Periodic work should take short time, so we want low
3274 * locking overhead.
3275 */
efa6a370 3276 spin_lock_irqsave(&bcm->irq_lock, flags);
91769e7d
MB		 3277 }
3278
3279 do_periodic_work(bcm);
3280
01917382 3281 if (unlikely(bcm->periodic_state % 60 == 0)) {
efa6a370 3282 spin_lock_irqsave(&bcm->irq_lock, flags);
7d4b0394
LF		 3283 tasklet_enable(&bcm->isr_tasklet);
3284 bcm43xx_interrupt_enable(bcm, savedirqs);
3285 if (bcm43xx_using_pio(bcm))
3286 bcm43xx_pio_thaw_txqueues(bcm);
3287 bcm43xx_mac_enable(bcm);
91769e7d 3288 netif_wake_queue(bcm->net_dev);
81e171b9 3289 net_dev->trans_start = orig_trans_start;
91769e7d 3290 }
efa6a370 3291 mmiowb();
08c3103a 3292 bcm->periodic_state++;
efa6a370
MB		 3293 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3294 mutex_unlock(&bcm->mutex);
f222313a
JL		 3295}
3296
7d4b0394 3297void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
f222313a 3298{
78ff56a0 3299 cancel_rearming_delayed_work(&bcm->periodic_work);
f222313a
JL		 3300}
3301
7d4b0394 3302void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
f222313a 3303{
c4028958 3304 struct delayed_work *work = &bcm->periodic_work;
f222313a 3305
78ff56a0 3306 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
c4028958
DH		 3307 INIT_DELAYED_WORK(work, bcm43xx_periodic_work_handler);
3308 schedule_delayed_work(work, 0);
f222313a
JL		 3309}
3310
3311static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3312{
3313 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3314 0x0056) * 2;
3315 bcm43xx_clear_keys(bcm);
3316}
3317
71c0cd70
MB		 3318static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
3319{
3320 struct bcm43xx_private *bcm = (struct bcm43xx_private *)rng->priv;
3321 unsigned long flags;
3322
f1207ba1 3323 spin_lock_irqsave(&(bcm)->irq_lock, flags);
71c0cd70 3324 *data = bcm43xx_read16(bcm, BCM43xx_MMIO_RNG);
f1207ba1 3325 spin_unlock_irqrestore(&(bcm)->irq_lock, flags);
71c0cd70
MB		 3326
3327 return (sizeof(u16));
3328}
3329
3330static void bcm43xx_rng_exit(struct bcm43xx_private *bcm)
3331{
3332 hwrng_unregister(&bcm->rng);
3333}
3334
3335static int bcm43xx_rng_init(struct bcm43xx_private *bcm)
3336{
3337 int err;
3338
3339 snprintf(bcm->rng_name, ARRAY_SIZE(bcm->rng_name),
3340 "%s_%s", KBUILD_MODNAME, bcm->net_dev->name);
3341 bcm->rng.name = bcm->rng_name;
3342 bcm->rng.data_read = bcm43xx_rng_read;
3343 bcm->rng.priv = (unsigned long)bcm;
3344 err = hwrng_register(&bcm->rng);
3345 if (err)
3346 printk(KERN_ERR PFX "RNG init failed (%d)\n", err);
3347
3348 return err;
3349}
3350
58e5528e 3351static int bcm43xx_shutdown_all_wireless_cores(struct bcm43xx_private *bcm)
f222313a 3352{
58e5528e 3353 int ret = 0;
f222313a 3354 int i, err;
58e5528e 3355 struct bcm43xx_coreinfo *core;
f222313a 3356
58e5528e
MB		 3357 bcm43xx_set_status(bcm, BCM43xx_STAT_SHUTTINGDOWN);
3358 for (i = 0; i < bcm->nr_80211_available; i++) {
3359 core = &(bcm->core_80211[i]);
3360 assert(core->available);
3361 if (!core->initialized)
3362 continue;
3363 err = bcm43xx_switch_core(bcm, core);
3364 if (err) {
3365 dprintk(KERN_ERR PFX "shutdown_all_wireless_cores "
3366 "switch_core failed (%d)\n", err);
3367 ret = err;
3368 continue;
3369 }
3370 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3371 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
3372 bcm43xx_wireless_core_cleanup(bcm);
3373 if (core == bcm->active_80211_core)
3374 bcm->active_80211_core = NULL;
3375 }
3376 free_irq(bcm->irq, bcm);
3377 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3378
3379 return ret;
3380}
3381
3382/* This is the opposite of bcm43xx_init_board() */
3383static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3384{
7a9b8cda 3385 bcm43xx_rng_exit(bcm);
367f899a 3386 bcm43xx_sysfs_unregister(bcm);
ab4977f8
MB		 3387 bcm43xx_periodic_tasks_delete(bcm);
3388
f1207ba1 3389 mutex_lock(&(bcm)->mutex);
58e5528e
MB		 3390 bcm43xx_shutdown_all_wireless_cores(bcm);
3391 bcm43xx_pctl_set_crystal(bcm, 0);
f1207ba1 3392 mutex_unlock(&(bcm)->mutex);
58e5528e 3393}
f222313a 3394
58e5528e
MB		 3395static void prepare_phydata_for_init(struct bcm43xx_phyinfo *phy)
3396{
3397 phy->antenna_diversity = 0xFFFF;
3398 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3399 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3400
3401 /* Flags */
3402 phy->calibrated = 0;
3403 phy->is_locked = 0;
3404
3405 if (phy->_lo_pairs) {
3406 memset(phy->_lo_pairs, 0,
3407 sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT);
3408 }
3409 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3410}
3411
3412static void prepare_radiodata_for_init(struct bcm43xx_private *bcm,
3413 struct bcm43xx_radioinfo *radio)
3414{
3415 int i;
3416
3417 /* Set default attenuation values. */
3418 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
3419 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
3420 radio->txctl1 = bcm43xx_default_txctl1(bcm);
3421 radio->txctl2 = 0xFFFF;
3422 radio->txpwr_offset = 0;
3423
3424 /* NRSSI */
3425 radio->nrssislope = 0;
3426 for (i = 0; i < ARRAY_SIZE(radio->nrssi); i++)
3427 radio->nrssi[i] = -1000;
3428 for (i = 0; i < ARRAY_SIZE(radio->nrssi_lt); i++)
3429 radio->nrssi_lt[i] = i;
3430
3431 radio->lofcal = 0xFFFF;
3432 radio->initval = 0xFFFF;
3433
3434 radio->aci_enable = 0;
3435 radio->aci_wlan_automatic = 0;
3436 radio->aci_hw_rssi = 0;
3437}
3438
3439static void prepare_priv_for_init(struct bcm43xx_private *bcm)
3440{
3441 int i;
3442 struct bcm43xx_coreinfo *core;
3443 struct bcm43xx_coreinfo_80211 *wlext;
3444
3445 assert(!bcm->active_80211_core);
3446
3447 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3448
3449 /* Flags */
3450 bcm->was_initialized = 0;
3451 bcm->reg124_set_0x4 = 0;
3452
3453 /* Stats */
3454 memset(&bcm->stats, 0, sizeof(bcm->stats));
3455
3456 /* Wireless core data */
f222313a 3457 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
58e5528e
MB		 3458 core = &(bcm->core_80211[i]);
3459 wlext = core->priv;
3460
3461 if (!core->available)
f222313a 3462 continue;
58e5528e 3463 assert(wlext == &(bcm->core_80211_ext[i]));
f222313a 3464
58e5528e
MB		 3465 prepare_phydata_for_init(&wlext->phy);
3466 prepare_radiodata_for_init(bcm, &wlext->radio);
f222313a
JL		 3467 }
3468
58e5528e
MB		 3469 /* IRQ related flags */
3470 bcm->irq_reason = 0;
3471 memset(bcm->dma_reason, 0, sizeof(bcm->dma_reason));
3472 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
f222313a 3473
653d5b55
LF		 3474 bcm->mac_suspended = 1;
3475
58e5528e
MB		 3476 /* Noise calculation context */
3477 memset(&bcm->noisecalc, 0, sizeof(bcm->noisecalc));
3478
3479 /* Periodic work context */
3480 bcm->periodic_state = 0;
f222313a
JL		 3481}
3482
58e5528e
MB		 3483static int wireless_core_up(struct bcm43xx_private *bcm,
3484 int active_wlcore)
3485{
3486 int err;
3487
3488 if (!bcm43xx_core_enabled(bcm))
3489 bcm43xx_wireless_core_reset(bcm, 1);
3490 if (!active_wlcore)
3491 bcm43xx_wireless_core_mark_inactive(bcm);
3492 err = bcm43xx_wireless_core_init(bcm, active_wlcore);
3493 if (err)
3494 goto out;
3495 if (!active_wlcore)
3496 bcm43xx_radio_turn_off(bcm);
3497out:
3498 return err;
3499}
3500
3501/* Select and enable the "to be used" wireless core.
3502 * Locking: bcm->mutex must be aquired before calling this.
3503 * bcm->irq_lock must not be aquired.
3504 */
3505int bcm43xx_select_wireless_core(struct bcm43xx_private *bcm,
3506 int phytype)
f222313a
JL		 3507{
3508 int i, err;
58e5528e
MB		 3509 struct bcm43xx_coreinfo *active_core = NULL;
3510 struct bcm43xx_coreinfo_80211 *active_wlext = NULL;
3511 struct bcm43xx_coreinfo *core;
3512 struct bcm43xx_coreinfo_80211 *wlext;
3513 int adjust_active_sbtmstatelow = 0;
f222313a
JL		 3514
3515 might_sleep();
3516
58e5528e
MB		 3517 if (phytype < 0) {
3518 /* If no phytype is requested, select the first core. */
3519 assert(bcm->core_80211[0].available);
3520 wlext = bcm->core_80211[0].priv;
3521 phytype = wlext->phy.type;
3522 }
3523 /* Find the requested core. */
3524 for (i = 0; i < bcm->nr_80211_available; i++) {
3525 core = &(bcm->core_80211[i]);
3526 wlext = core->priv;
3527 if (wlext->phy.type == phytype) {
3528 active_core = core;
3529 active_wlext = wlext;
3530 break;
3531 }
3532 }
3533 if (!active_core)
3534 return -ESRCH; /* No such PHYTYPE on this board. */
3535
3536 if (bcm->active_80211_core) {
3537 /* We already selected a wl core in the past.
3538 * So first clean up everything.
3539 */
3540 dprintk(KERN_INFO PFX "select_wireless_core: cleanup\n");
3541 ieee80211softmac_stop(bcm->net_dev);
3542 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3543 err = bcm43xx_disable_interrupts_sync(bcm);
3544 assert(!err);
3545 tasklet_enable(&bcm->isr_tasklet);
3546 err = bcm43xx_shutdown_all_wireless_cores(bcm);
3547 if (err)
3548 goto error;
3549 /* Ok, everything down, continue to re-initialize. */
3550 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3551 }
f222313a 3552
58e5528e
MB		 3553 /* Reset all data structures. */
3554 prepare_priv_for_init(bcm);
3234faa8 3555
f222313a
JL		 3556 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3557 if (err)
58e5528e 3558 goto error;
f222313a 3559
58e5528e 3560 /* Mark all unused cores "inactive". */
e9357c05 3561 for (i = 0; i < bcm->nr_80211_available; i++) {
58e5528e
MB		 3562 core = &(bcm->core_80211[i]);
3563 wlext = core->priv;
f222313a 3564
58e5528e
MB		 3565 if (core == active_core)
3566 continue;
3567 err = bcm43xx_switch_core(bcm, core);
3568 if (err) {
3569 dprintk(KERN_ERR PFX "Could not switch to inactive "
3570 "802.11 core (%d)\n", err);
3571 goto error;
f222313a 3572 }
58e5528e
MB		 3573 err = wireless_core_up(bcm, 0);
3574 if (err) {
3575 dprintk(KERN_ERR PFX "core_up for inactive 802.11 core "
3576 "failed (%d)\n", err);
3577 goto error;
3578 }
3579 adjust_active_sbtmstatelow = 1;
3580 }
f222313a 3581
58e5528e
MB		 3582 /* Now initialize the active 802.11 core. */
3583 err = bcm43xx_switch_core(bcm, active_core);
3584 if (err) {
3585 dprintk(KERN_ERR PFX "Could not switch to active "
3586 "802.11 core (%d)\n", err);
3587 goto error;
3588 }
3589 if (adjust_active_sbtmstatelow &&
3590 active_wlext->phy.type == BCM43xx_PHYTYPE_G) {
3591 u32 sbtmstatelow;
f222313a 3592
58e5528e
MB		 3593 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
3594 sbtmstatelow |= 0x20000000;
3595 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
f222313a 3596 }
58e5528e
MB		 3597 err = wireless_core_up(bcm, 1);
3598 if (err) {
3599 dprintk(KERN_ERR PFX "core_up for active 802.11 core "
3600 "failed (%d)\n", err);
3601 goto error;
f222313a 3602 }
58e5528e 3603 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
71c0cd70 3604 if (err)
58e5528e
MB		 3605 goto error;
3606 bcm->active_80211_core = active_core;
3607
f222313a
JL		 3608 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3609 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
f222313a 3610 bcm43xx_security_init(bcm);
ecac598b 3611 drain_txstatus_queue(bcm);
58e5528e 3612 ieee80211softmac_start(bcm->net_dev);
f222313a 3613
58e5528e
MB		 3614 /* Let's go! Be careful after enabling the IRQs.
3615 * Don't switch cores, for example.
3616 */
3617 bcm43xx_mac_enable(bcm);
3618 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3619 err = bcm43xx_initialize_irq(bcm);
3620 if (err)
3621 goto error;
3622 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
f222313a 3623
58e5528e
MB		 3624 dprintk(KERN_INFO PFX "Selected 802.11 core (phytype %d)\n",
3625 active_wlext->phy.type);
cad2b31a 3626
58e5528e
MB		 3627 return 0;
3628
3629error:
3630 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3631 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
3632 return err;
3633}
3634
3635static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3636{
3637 int err;
3638
f1207ba1 3639 mutex_lock(&(bcm)->mutex);
58e5528e
MB		 3640
3641 tasklet_enable(&bcm->isr_tasklet);
3642 err = bcm43xx_pctl_set_crystal(bcm, 1);
3643 if (err)
3644 goto err_tasklet;
3645 err = bcm43xx_pctl_init(bcm);
3646 if (err)
3647 goto err_crystal_off;
3648 err = bcm43xx_select_wireless_core(bcm, -1);
3649 if (err)
3650 goto err_crystal_off;
58e5528e
MB		 3651 err = bcm43xx_sysfs_register(bcm);
3652 if (err)
3653 goto err_wlshutdown;
7a9b8cda
MB		 3654 err = bcm43xx_rng_init(bcm);
3655 if (err)
3656 goto err_sysfs_unreg;
6aeb3ddd 3657 bcm43xx_periodic_tasks_setup(bcm);
f222313a 3658
bc519f30 3659 /*FIXME: This should be handled by softmac instead. */
c4028958 3660 schedule_delayed_work(&bcm->softmac->associnfo.work, 0);
bc519f30 3661
f222313a 3662out:
f1207ba1 3663 mutex_unlock(&(bcm)->mutex);
78ff56a0 3664
f222313a
JL		 3665 return err;
3666
7a9b8cda
MB		 3667err_sysfs_unreg:
3668 bcm43xx_sysfs_unregister(bcm);
58e5528e
MB		 3669err_wlshutdown:
3670 bcm43xx_shutdown_all_wireless_cores(bcm);
f222313a
JL		 3671err_crystal_off:
3672 bcm43xx_pctl_set_crystal(bcm, 0);
58e5528e
MB		 3673err_tasklet:
3674 tasklet_disable(&bcm->isr_tasklet);
f222313a
JL		 3675 goto out;
3676}
3677
3678static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3679{
3680 struct pci_dev *pci_dev = bcm->pci_dev;
3681 int i;
3682
3683 bcm43xx_chipset_detach(bcm);
3684 /* Do _not_ access the chip, after it is detached. */
cc935710 3685 pci_iounmap(pci_dev, bcm->mmio_addr);
f222313a
JL		 3686 pci_release_regions(pci_dev);
3687 pci_disable_device(pci_dev);
3688
3689 /* Free allocated structures/fields */
3690 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
e9357c05
MB		 3691 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3692 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3693 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
f222313a
JL		 3694 }
3695}
3696
3697static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3698{
e9357c05 3699 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a
JL		 3700 u16 value;
3701 u8 phy_version;
3702 u8 phy_type;
3703 u8 phy_rev;
3704 int phy_rev_ok = 1;
3705 void *p;
3706
3707 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3708
3709 phy_version = (value & 0xF000) >> 12;
3710 phy_type = (value & 0x0F00) >> 8;
3711 phy_rev = (value & 0x000F);
3712
3713 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3714 phy_version, phy_type, phy_rev);
3715
3716 switch (phy_type) {
3717 case BCM43xx_PHYTYPE_A:
3718 if (phy_rev >= 4)
3719 phy_rev_ok = 0;
3720 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3721 * if we switch 80211 cores after init is done.
3722 * As we do not implement on the fly switching between
3723 * wireless cores, I will leave this as a future task.
3724 */
3725 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3726 bcm->ieee->mode = IEEE_A;
3727 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3728 IEEE80211_24GHZ_BAND;
3729 break;
3730 case BCM43xx_PHYTYPE_B:
3731 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3732 phy_rev_ok = 0;
3733 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3734 bcm->ieee->mode = IEEE_B;
3735 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3736 break;
3737 case BCM43xx_PHYTYPE_G:
f3d1fca3 3738 if (phy_rev > 8)
f222313a
JL		 3739 phy_rev_ok = 0;
3740 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3741 IEEE80211_CCK_MODULATION;
3742 bcm->ieee->mode = IEEE_G;
3743 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3744 break;
3745 default:
3746 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3747 phy_type);
3748 return -ENODEV;
3749 };
f04e2be7
LF		 3750 bcm->ieee->perfect_rssi = RX_RSSI_MAX;
3751 bcm->ieee->worst_rssi = 0;
f222313a
JL		 3752 if (!phy_rev_ok) {
3753 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3754 phy_rev);
3755 }
3756
489423c8
MB		 3757 phy->version = phy_version;
3758 phy->type = phy_type;
3759 phy->rev = phy_rev;
f222313a
JL		 3760 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3761 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3762 GFP_KERNEL);
3763 if (!p)
3764 return -ENOMEM;
489423c8 3765 phy->_lo_pairs = p;
f222313a
JL		 3766 }
3767
3768 return 0;
3769}
3770
3771static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3772{
3773 struct pci_dev *pci_dev = bcm->pci_dev;
3774 struct net_device *net_dev = bcm->net_dev;
3775 int err;
3776 int i;
f222313a
JL		 3777 u32 coremask;
3778
3779 err = pci_enable_device(pci_dev);
3780 if (err) {
cc935710 3781 printk(KERN_ERR PFX "pci_enable_device() failed\n");
f222313a
JL		 3782 goto out;
3783 }
65f3f191 3784 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
f222313a 3785 if (err) {
cc935710 3786 printk(KERN_ERR PFX "pci_request_regions() failed\n");
f222313a
JL		 3787 goto err_pci_disable;
3788 }
f222313a
JL		 3789 /* enable PCI bus-mastering */
3790 pci_set_master(pci_dev);
cc935710 3791 bcm->mmio_addr = pci_iomap(pci_dev, 0, ~0UL);
4a1821e4 3792 if (!bcm->mmio_addr) {
cc935710 3793 printk(KERN_ERR PFX "pci_iomap() failed\n");
f222313a
JL		 3794 err = -EIO;
3795 goto err_pci_release;
3796 }
4a1821e4 3797 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
f222313a
JL		 3798
3799 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3800 &bcm->board_vendor);
3801 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3802 &bcm->board_type);
3803 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3804 &bcm->board_revision);
3805
3806 err = bcm43xx_chipset_attach(bcm);
3807 if (err)
3808 goto err_iounmap;
3809 err = bcm43xx_pctl_init(bcm);
3810 if (err)
3811 goto err_chipset_detach;
3812 err = bcm43xx_probe_cores(bcm);
3813 if (err)
3814 goto err_chipset_detach;
3815
f222313a
JL		 3816 /* Attach all IO cores to the backplane. */
3817 coremask = 0;
e9357c05 3818 for (i = 0; i < bcm->nr_80211_available; i++)
f222313a
JL		 3819 coremask |= (1 << bcm->core_80211[i].index);
3820 //FIXME: Also attach some non80211 cores?
3821 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3822 if (err) {
3823 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3824 goto err_chipset_detach;
3825 }
3826
ea0922b0 3827 err = bcm43xx_sprom_extract(bcm);
f222313a
JL		 3828 if (err)
3829 goto err_chipset_detach;
3830 err = bcm43xx_leds_init(bcm);
3831 if (err)
3832 goto err_chipset_detach;
3833
e9357c05 3834 for (i = 0; i < bcm->nr_80211_available; i++) {
f222313a
JL		 3835 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3836 assert(err != -ENODEV);
3837 if (err)
3838 goto err_80211_unwind;
3839
3840 /* Enable the selected wireless core.
3841 * Connect PHY only on the first core.
3842 */
3843 bcm43xx_wireless_core_reset(bcm, (i == 0));
3844
3845 err = bcm43xx_read_phyinfo(bcm);
3846 if (err && (i == 0))
3847 goto err_80211_unwind;
3848
3849 err = bcm43xx_read_radioinfo(bcm);
3850 if (err && (i == 0))
3851 goto err_80211_unwind;
3852
3853 err = bcm43xx_validate_chip(bcm);
3854 if (err && (i == 0))
3855 goto err_80211_unwind;
3856
3857 bcm43xx_radio_turn_off(bcm);
3858 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3859 if (err)
3860 goto err_80211_unwind;
3861 bcm43xx_wireless_core_disable(bcm);
3862 }
869aaab1
MB		 3863 err = bcm43xx_geo_init(bcm);
3864 if (err)
3865 goto err_80211_unwind;
f222313a
JL		 3866 bcm43xx_pctl_set_crystal(bcm, 0);
3867
3868 /* Set the MAC address in the networking subsystem */
f9f7b960 3869 if (is_valid_ether_addr(bcm->sprom.et1macaddr))
f222313a
JL		 3870 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3871 else
3872 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3873
f222313a
JL		 3874 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3875 "Broadcom %04X", bcm->chip_id);
3876
3877 assert(err == 0);
3878out:
3879 return err;
3880
3881err_80211_unwind:
3882 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
e9357c05
MB		 3883 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3884 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3885 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
f222313a
JL		 3886 }
3887err_chipset_detach:
3888 bcm43xx_chipset_detach(bcm);
3889err_iounmap:
cc935710 3890 pci_iounmap(pci_dev, bcm->mmio_addr);
f222313a
JL		 3891err_pci_release:
3892 pci_release_regions(pci_dev);
3893err_pci_disable:
3894 pci_disable_device(pci_dev);
3895 goto out;
3896}
3897
f222313a
JL		 3898/* Do the Hardware IO operations to send the txb */
3899static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3900 struct ieee80211_txb *txb)
3901{
3902 int err = -ENODEV;
3903
77db31ea
MB		 3904 if (bcm43xx_using_pio(bcm))
3905 err = bcm43xx_pio_tx(bcm, txb);
f222313a 3906 else
ea72ab22 3907 err = bcm43xx_dma_tx(bcm, txb);
b79367a5 3908 bcm->net_dev->trans_start = jiffies;
f222313a
JL		 3909
3910 return err;
3911}
3912
3913static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3914 u8 channel)
3915{
3916 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
ec483781 3917 struct bcm43xx_radioinfo *radio;
f222313a
JL		 3918 unsigned long flags;
3919
efa6a370
MB		 3920 mutex_lock(&bcm->mutex);
3921 spin_lock_irqsave(&bcm->irq_lock, flags);
78ff56a0 3922 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
ec483781
MB		 3923 bcm43xx_mac_suspend(bcm);
3924 bcm43xx_radio_selectchannel(bcm, channel, 0);
3925 bcm43xx_mac_enable(bcm);
3926 } else {
3927 radio = bcm43xx_current_radio(bcm);
3928 radio->initial_channel = channel;
3929 }
efa6a370
MB		 3930 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3931 mutex_unlock(&bcm->mutex);
f222313a
JL		 3932}
3933
3934/* set_security() callback in struct ieee80211_device */
3935static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3936 struct ieee80211_security *sec)
3937{
3938 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3939 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3940 unsigned long flags;
3941 int keyidx;
3942
ff7562aa 3943 dprintk(KERN_INFO PFX "set security called");
efccb647 3944
efa6a370
MB		 3945 mutex_lock(&bcm->mutex);
3946 spin_lock_irqsave(&bcm->irq_lock, flags);
efccb647 3947
f222313a
JL		 3948 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3949 if (sec->flags & (1<<keyidx)) {
3950 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3951 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3952 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3953 }
3954
3955 if (sec->flags & SEC_ACTIVE_KEY) {
3956 secinfo->active_key = sec->active_key;
ff7562aa 3957 dprintk(", .active_key = %d", sec->active_key);
f222313a
JL		 3958 }
3959 if (sec->flags & SEC_UNICAST_GROUP) {
3960 secinfo->unicast_uses_group = sec->unicast_uses_group;
ff7562aa 3961 dprintk(", .unicast_uses_group = %d", sec->unicast_uses_group);
f222313a
JL		 3962 }
3963 if (sec->flags & SEC_LEVEL) {
3964 secinfo->level = sec->level;
ff7562aa 3965 dprintk(", .level = %d", sec->level);
f222313a
JL		 3966 }
3967 if (sec->flags & SEC_ENABLED) {
3968 secinfo->enabled = sec->enabled;
ff7562aa 3969 dprintk(", .enabled = %d", sec->enabled);
f222313a
JL		 3970 }
3971 if (sec->flags & SEC_ENCRYPT) {
3972 secinfo->encrypt = sec->encrypt;
ff7562aa 3973 dprintk(", .encrypt = %d", sec->encrypt);
f222313a 3974 }
43592194
DD		 3975 if (sec->flags & SEC_AUTH_MODE) {
3976 secinfo->auth_mode = sec->auth_mode;
345f6b8b 3977 dprintk(", .auth_mode = %d", sec->auth_mode);
43592194 3978 }
ff7562aa 3979 dprintk("\n");
78ff56a0
MB		 3980 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED &&
3981 !bcm->ieee->host_encrypt) {
f222313a
JL		 3982 if (secinfo->enabled) {
3983 /* upload WEP keys to hardware */
3984 char null_address[6] = { 0 };
3985 u8 algorithm = 0;
3986 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3987 if (!(sec->flags & (1<<keyidx)))
3988 continue;
3989 switch (sec->encode_alg[keyidx]) {
3990 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3991 case SEC_ALG_WEP:
3992 algorithm = BCM43xx_SEC_ALGO_WEP;
3993 if (secinfo->key_sizes[keyidx] == 13)
3994 algorithm = BCM43xx_SEC_ALGO_WEP104;
3995 break;
3996 case SEC_ALG_TKIP:
3997 FIXME();
3998 algorithm = BCM43xx_SEC_ALGO_TKIP;
3999 break;
4000 case SEC_ALG_CCMP:
4001 FIXME();
4002 algorithm = BCM43xx_SEC_ALGO_AES;
4003 break;
4004 default:
4005 assert(0);
4006 break;
4007 }
4008 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
4009 bcm->key[keyidx].enabled = 1;
4010 bcm->key[keyidx].algorithm = algorithm;
4011 }
4012 } else
4013 bcm43xx_clear_keys(bcm);
4014 }
efa6a370
MB		 4015 spin_unlock_irqrestore(&bcm->irq_lock, flags);
4016 mutex_unlock(&bcm->mutex);
f222313a
JL		 4017}
4018
4019/* hard_start_xmit() callback in struct ieee80211_device */
4020static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
4021 struct net_device *net_dev,
4022 int pri)
4023{
4024 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4025 int err = -ENODEV;
4026 unsigned long flags;
4027
efa6a370 4028 spin_lock_irqsave(&bcm->irq_lock, flags);
78ff56a0 4029 if (likely(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED))
f222313a 4030 err = bcm43xx_tx(bcm, txb);
efa6a370 4031 spin_unlock_irqrestore(&bcm->irq_lock, flags);
f222313a 4032
b6971c21
LF		 4033 if (unlikely(err))
4034 return NETDEV_TX_BUSY;
4035 return NETDEV_TX_OK;
f222313a
JL		 4036}
4037
f222313a
JL		 4038static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
4039{
4040 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
efccb647 4041 unsigned long flags;
f222313a 4042
efa6a370 4043 spin_lock_irqsave(&bcm->irq_lock, flags);
f222313a 4044 bcm43xx_controller_restart(bcm, "TX timeout");
efa6a370 4045 spin_unlock_irqrestore(&bcm->irq_lock, flags);
f222313a
JL		 4046}
4047
4048#ifdef CONFIG_NET_POLL_CONTROLLER
4049static void bcm43xx_net_poll_controller(struct net_device *net_dev)
4050{
4051 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4052 unsigned long flags;
4053
4054 local_irq_save(flags);
58e5528e 4055 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED)
7d12e780 4056 bcm43xx_interrupt_handler(bcm->irq, bcm);
f222313a
JL		 4057 local_irq_restore(flags);
4058}
4059#endif /* CONFIG_NET_POLL_CONTROLLER */
4060
4061static int bcm43xx_net_open(struct net_device *net_dev)
4062{
4063 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4064
4065 return bcm43xx_init_board(bcm);
4066}
4067
4068static int bcm43xx_net_stop(struct net_device *net_dev)
4069{
4070 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
91769e7d 4071 int err;
f222313a
JL		 4072
4073 ieee80211softmac_stop(net_dev);
58e5528e 4074 err = bcm43xx_disable_interrupts_sync(bcm);
91769e7d 4075 assert(!err);
f222313a 4076 bcm43xx_free_board(bcm);
7d4b0394 4077 flush_scheduled_work();
f222313a
JL		 4078
4079 return 0;
4080}
4081
77db31ea
MB		 4082static int bcm43xx_init_private(struct bcm43xx_private *bcm,
4083 struct net_device *net_dev,
ab4977f8 4084 struct pci_dev *pci_dev)
f222313a 4085{
78ff56a0 4086 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
f222313a
JL		 4087 bcm->ieee = netdev_priv(net_dev);
4088 bcm->softmac = ieee80211_priv(net_dev);
4089 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
f222313a 4090
f222313a 4091 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
894b6274 4092 bcm->mac_suspended = 1;
f222313a
JL		 4093 bcm->pci_dev = pci_dev;
4094 bcm->net_dev = net_dev;
4d5a9e0e 4095 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
78ff56a0 4096 spin_lock_init(&bcm->irq_lock);
efa6a370 4097 spin_lock_init(&bcm->leds_lock);
78ff56a0 4098 mutex_init(&bcm->mutex);
f222313a
JL		 4099 tasklet_init(&bcm->isr_tasklet,
4100 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
4101 (unsigned long)bcm);
4102 tasklet_disable_nosync(&bcm->isr_tasklet);
8da81e52 4103 if (modparam_pio)
77db31ea 4104 bcm->__using_pio = 1;
f222313a
JL		 4105 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
4106
4107 /* default to sw encryption for now */
4108 bcm->ieee->host_build_iv = 0;
4109 bcm->ieee->host_encrypt = 1;
4110 bcm->ieee->host_decrypt = 1;
4111
4112 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
4113 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
4114 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
4115 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
77db31ea
MB		 4116
4117 return 0;
f222313a
JL		 4118}
4119
4120static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
4121 const struct pci_device_id *ent)
4122{
4123 struct net_device *net_dev;
4124 struct bcm43xx_private *bcm;
f222313a
JL		 4125 int err;
4126
4127#ifdef CONFIG_BCM947XX
4128 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
4129 return -ENODEV;
4130#endif
4131
4132#ifdef DEBUG_SINGLE_DEVICE_ONLY
4133 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
4134 return -ENODEV;
4135#endif
4136
4137 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
4138 if (!net_dev) {
4139 printk(KERN_ERR PFX
4140 "could not allocate ieee80211 device %s\n",
4141 pci_name(pdev));
4142 err = -ENOMEM;
4143 goto out;
4144 }
4145 /* initialize the net_device struct */
4146 SET_MODULE_OWNER(net_dev);
4147 SET_NETDEV_DEV(net_dev, &pdev->dev);
4148
4149 net_dev->open = bcm43xx_net_open;
4150 net_dev->stop = bcm43xx_net_stop;
f222313a
JL		 4151 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
4152#ifdef CONFIG_NET_POLL_CONTROLLER
4153 net_dev->poll_controller = bcm43xx_net_poll_controller;
4154#endif
4155 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
4156 net_dev->irq = pdev->irq;
6465ce1b 4157 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
f222313a
JL		 4158
4159 /* initialize the bcm43xx_private struct */
4160 bcm = bcm43xx_priv(net_dev);
4161 memset(bcm, 0, sizeof(*bcm));
ab4977f8 4162 err = bcm43xx_init_private(bcm, net_dev, pdev);
77db31ea 4163 if (err)
ab4977f8 4164 goto err_free_netdev;
f222313a
JL		 4165
4166 pci_set_drvdata(pdev, net_dev);
4167
4168 err = bcm43xx_attach_board(bcm);
4169 if (err)
ab4977f8 4170 goto err_free_netdev;
f222313a
JL		 4171
4172 err = register_netdev(net_dev);
4173 if (err) {
4174 printk(KERN_ERR PFX "Cannot register net device, "
4175 "aborting.\n");
4176 err = -ENOMEM;
4177 goto err_detach_board;
4178 }
4179
4180 bcm43xx_debugfs_add_device(bcm);
4181
4182 assert(err == 0);
4183out:
4184 return err;
4185
4186err_detach_board:
4187 bcm43xx_detach_board(bcm);
f222313a
JL		 4188err_free_netdev:
4189 free_ieee80211softmac(net_dev);
4190 goto out;
4191}
4192
4193static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
4194{
4195 struct net_device *net_dev = pci_get_drvdata(pdev);
4196 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4197
4198 bcm43xx_debugfs_remove_device(bcm);
4199 unregister_netdev(net_dev);
4200 bcm43xx_detach_board(bcm);
f222313a
JL		 4201 free_ieee80211softmac(net_dev);
4202}
4203
4204/* Hard-reset the chip. Do not call this directly.
4205 * Use bcm43xx_controller_restart()
4206 */
c4028958 4207static void bcm43xx_chip_reset(struct work_struct *work)
f222313a 4208{
c4028958
DH		 4209 struct bcm43xx_private *bcm =
4210 container_of(work, struct bcm43xx_private, restart_work);
58e5528e 4211 struct bcm43xx_phyinfo *phy;
7d4b0394 4212 int err = -ENODEV;
f222313a 4213
f1207ba1 4214 mutex_lock(&(bcm)->mutex);
7d4b0394
LF		 4215 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4216 bcm43xx_periodic_tasks_delete(bcm);
4217 phy = bcm43xx_current_phy(bcm);
4218 err = bcm43xx_select_wireless_core(bcm, phy->type);
4219 if (!err)
4220 bcm43xx_periodic_tasks_setup(bcm);
4221 }
f1207ba1 4222 mutex_unlock(&(bcm)->mutex);
f222313a 4223
58e5528e
MB		 4224 printk(KERN_ERR PFX "Controller restart%s\n",
4225 (err == 0) ? "ed" : " failed");
f222313a
JL		 4226}
4227
4228/* Hard-reset the chip.
4229 * This can be called from interrupt or process context.
7d4b0394 4230 * bcm->irq_lock must be locked.
58e5528e 4231 */
f222313a
JL		 4232void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
4233{
7d4b0394
LF		 4234 if (bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)
4235 return;
f222313a 4236 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
c4028958 4237 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset);
ab4977f8 4238 schedule_work(&bcm->restart_work);
f222313a
JL		 4239}
4240
4241#ifdef CONFIG_PM
4242
4243static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
4244{
4245 struct net_device *net_dev = pci_get_drvdata(pdev);
4246 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
58e5528e 4247 int err;
f222313a
JL		 4248
4249 dprintk(KERN_INFO PFX "Suspending...\n");
4250
f222313a 4251 netif_device_detach(net_dev);
58e5528e
MB		 4252 bcm->was_initialized = 0;
4253 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4254 bcm->was_initialized = 1;
f222313a 4255 ieee80211softmac_stop(net_dev);
58e5528e 4256 err = bcm43xx_disable_interrupts_sync(bcm);
f222313a
JL		 4257 if (unlikely(err)) {
4258 dprintk(KERN_ERR PFX "Suspend failed.\n");
4259 return -EAGAIN;
4260 }
4261 bcm->firmware_norelease = 1;
4262 bcm43xx_free_board(bcm);
4263 bcm->firmware_norelease = 0;
4264 }
4265 bcm43xx_chipset_detach(bcm);
4266
4267 pci_save_state(pdev);
4268 pci_disable_device(pdev);
4269 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4270
4271 dprintk(KERN_INFO PFX "Device suspended.\n");
4272
4273 return 0;
4274}
4275
4276static int bcm43xx_resume(struct pci_dev *pdev)
4277{
4278 struct net_device *net_dev = pci_get_drvdata(pdev);
4279 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4280 int err = 0;
4281
4282 dprintk(KERN_INFO PFX "Resuming...\n");
4283
4284 pci_set_power_state(pdev, 0);
16bfa676
LF		 4285 err = pci_enable_device(pdev);
4286 if (err) {
4287 printk(KERN_ERR PFX "Failure with pci_enable_device!\n");
4288 return err;
4289 }
f222313a
JL		 4290 pci_restore_state(pdev);
4291
4292 bcm43xx_chipset_attach(bcm);
58e5528e 4293 if (bcm->was_initialized)
f222313a 4294 err = bcm43xx_init_board(bcm);
f222313a
JL		 4295 if (err) {
4296 printk(KERN_ERR PFX "Resume failed!\n");
4297 return err;
4298 }
f222313a 4299 netif_device_attach(net_dev);
58e5528e 4300
f222313a
JL		 4301 dprintk(KERN_INFO PFX "Device resumed.\n");
4302
4303 return 0;
4304}
4305
4306#endif /* CONFIG_PM */
4307
4308static struct pci_driver bcm43xx_pci_driver = {
65f3f191 4309 .name = KBUILD_MODNAME,
f222313a
JL		 4310 .id_table = bcm43xx_pci_tbl,
4311 .probe = bcm43xx_init_one,
4312 .remove = __devexit_p(bcm43xx_remove_one),
4313#ifdef CONFIG_PM
4314 .suspend = bcm43xx_suspend,
4315 .resume = bcm43xx_resume,
4316#endif /* CONFIG_PM */
4317};
4318
4319static int __init bcm43xx_init(void)
4320{
65f3f191 4321 printk(KERN_INFO KBUILD_MODNAME " driver\n");
f222313a
JL		 4322 bcm43xx_debugfs_init();
4323 return pci_register_driver(&bcm43xx_pci_driver);
4324}
4325
4326static void __exit bcm43xx_exit(void)
4327{
4328 pci_unregister_driver(&bcm43xx_pci_driver);
4329 bcm43xx_debugfs_exit();
4330}
4331
4332module_init(bcm43xx_init)
4333module_exit(bcm43xx_exit)
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