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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/printk.h> | |
21 | #include <linux/pci_ids.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/mmc/sdio.h> | |
cb7cf7be | 26 | #include <linux/mmc/sdio_ids.h> |
5b435de0 AS |
27 | #include <linux/mmc/sdio_func.h> |
28 | #include <linux/mmc/card.h> | |
29 | #include <linux/semaphore.h> | |
30 | #include <linux/firmware.h> | |
b7a57e76 | 31 | #include <linux/module.h> |
99ba15cd | 32 | #include <linux/bcma/bcma.h> |
4fc0d016 | 33 | #include <linux/debugfs.h> |
8dc01811 | 34 | #include <linux/vmalloc.h> |
668761ac | 35 | #include <linux/platform_data/brcmfmac-sdio.h> |
8da9d2c8 | 36 | #include <linux/moduleparam.h> |
5b435de0 AS |
37 | #include <asm/unaligned.h> |
38 | #include <defs.h> | |
39 | #include <brcmu_wifi.h> | |
40 | #include <brcmu_utils.h> | |
41 | #include <brcm_hw_ids.h> | |
42 | #include <soc.h> | |
43 | #include "sdio_host.h" | |
20c9c9bc | 44 | #include "chip.h" |
dabedab9 | 45 | #include "firmware.h" |
5b435de0 AS |
46 | |
47 | #define DCMD_RESP_TIMEOUT 2000 /* In milli second */ | |
48 | ||
8ae74654 | 49 | #ifdef DEBUG |
5b435de0 AS |
50 | |
51 | #define BRCMF_TRAP_INFO_SIZE 80 | |
52 | ||
53 | #define CBUF_LEN (128) | |
54 | ||
4fc0d016 AS |
55 | /* Device console log buffer state */ |
56 | #define CONSOLE_BUFFER_MAX 2024 | |
57 | ||
5b435de0 AS |
58 | struct rte_log_le { |
59 | __le32 buf; /* Can't be pointer on (64-bit) hosts */ | |
60 | __le32 buf_size; | |
61 | __le32 idx; | |
62 | char *_buf_compat; /* Redundant pointer for backward compat. */ | |
63 | }; | |
64 | ||
65 | struct rte_console { | |
66 | /* Virtual UART | |
67 | * When there is no UART (e.g. Quickturn), | |
68 | * the host should write a complete | |
69 | * input line directly into cbuf and then write | |
70 | * the length into vcons_in. | |
71 | * This may also be used when there is a real UART | |
72 | * (at risk of conflicting with | |
73 | * the real UART). vcons_out is currently unused. | |
74 | */ | |
75 | uint vcons_in; | |
76 | uint vcons_out; | |
77 | ||
78 | /* Output (logging) buffer | |
79 | * Console output is written to a ring buffer log_buf at index log_idx. | |
80 | * The host may read the output when it sees log_idx advance. | |
81 | * Output will be lost if the output wraps around faster than the host | |
82 | * polls. | |
83 | */ | |
84 | struct rte_log_le log_le; | |
85 | ||
86 | /* Console input line buffer | |
87 | * Characters are read one at a time into cbuf | |
88 | * until <CR> is received, then | |
89 | * the buffer is processed as a command line. | |
90 | * Also used for virtual UART. | |
91 | */ | |
92 | uint cbuf_idx; | |
93 | char cbuf[CBUF_LEN]; | |
94 | }; | |
95 | ||
8ae74654 | 96 | #endif /* DEBUG */ |
5b435de0 AS |
97 | #include <chipcommon.h> |
98 | ||
5b435de0 | 99 | #include "dhd_bus.h" |
5b435de0 | 100 | #include "dhd_dbg.h" |
40c1c249 | 101 | #include "tracepoint.h" |
5b435de0 AS |
102 | |
103 | #define TXQLEN 2048 /* bulk tx queue length */ | |
104 | #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ | |
105 | #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ | |
106 | #define PRIOMASK 7 | |
107 | ||
108 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
109 | ||
110 | #define BRCMF_RXBOUND 50 /* Default for max rx frames in | |
111 | one scheduling */ | |
112 | ||
113 | #define BRCMF_TXBOUND 20 /* Default for max tx frames in | |
114 | one scheduling */ | |
115 | ||
116 | #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ | |
117 | ||
118 | #define MEMBLOCK 2048 /* Block size used for downloading | |
119 | of dongle image */ | |
120 | #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold | |
121 | biggest possible glom */ | |
122 | ||
123 | #define BRCMF_FIRSTREAD (1 << 6) | |
124 | ||
125 | ||
126 | /* SBSDIO_DEVICE_CTL */ | |
127 | ||
128 | /* 1: device will assert busy signal when receiving CMD53 */ | |
129 | #define SBSDIO_DEVCTL_SETBUSY 0x01 | |
130 | /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ | |
131 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 | |
132 | /* 1: mask all interrupts to host except the chipActive (rev 8) */ | |
133 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 | |
134 | /* 1: isolate internal sdio signals, put external pads in tri-state; requires | |
135 | * sdio bus power cycle to clear (rev 9) */ | |
136 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 | |
137 | /* Force SD->SB reset mapping (rev 11) */ | |
138 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 | |
139 | /* Determined by CoreControl bit */ | |
140 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 | |
141 | /* Force backplane reset */ | |
142 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 | |
143 | /* Force no backplane reset */ | |
144 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 | |
145 | ||
5b435de0 AS |
146 | /* direct(mapped) cis space */ |
147 | ||
148 | /* MAPPED common CIS address */ | |
149 | #define SBSDIO_CIS_BASE_COMMON 0x1000 | |
150 | /* maximum bytes in one CIS */ | |
151 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 | |
152 | /* cis offset addr is < 17 bits */ | |
153 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF | |
154 | ||
155 | /* manfid tuple length, include tuple, link bytes */ | |
156 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 | |
157 | ||
cb7cf7be AS |
158 | #define CORE_BUS_REG(base, field) \ |
159 | (base + offsetof(struct sdpcmd_regs, field)) | |
160 | ||
161 | /* SDIO function 1 register CHIPCLKCSR */ | |
162 | /* Force ALP request to backplane */ | |
163 | #define SBSDIO_FORCE_ALP 0x01 | |
164 | /* Force HT request to backplane */ | |
165 | #define SBSDIO_FORCE_HT 0x02 | |
166 | /* Force ILP request to backplane */ | |
167 | #define SBSDIO_FORCE_ILP 0x04 | |
168 | /* Make ALP ready (power up xtal) */ | |
169 | #define SBSDIO_ALP_AVAIL_REQ 0x08 | |
170 | /* Make HT ready (power up PLL) */ | |
171 | #define SBSDIO_HT_AVAIL_REQ 0x10 | |
172 | /* Squelch clock requests from HW */ | |
173 | #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 | |
174 | /* Status: ALP is ready */ | |
175 | #define SBSDIO_ALP_AVAIL 0x40 | |
176 | /* Status: HT is ready */ | |
177 | #define SBSDIO_HT_AVAIL 0x80 | |
8a385ba5 | 178 | #define SBSDIO_CSR_MASK 0x1F |
cb7cf7be AS |
179 | #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) |
180 | #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) | |
181 | #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) | |
182 | #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) | |
183 | #define SBSDIO_CLKAV(regval, alponly) \ | |
184 | (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) | |
185 | ||
5b435de0 AS |
186 | /* intstatus */ |
187 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | |
188 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | |
189 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | |
190 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | |
191 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | |
192 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | |
193 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | |
194 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | |
195 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | |
196 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | |
197 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | |
198 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | |
199 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | |
200 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | |
201 | #define I_PC (1 << 10) /* descriptor error */ | |
202 | #define I_PD (1 << 11) /* data error */ | |
203 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | |
204 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | |
205 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | |
206 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | |
207 | #define I_RI (1 << 16) /* Receive Interrupt */ | |
208 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | |
209 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | |
210 | #define I_XI (1 << 24) /* Transmit Interrupt */ | |
211 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | |
212 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | |
213 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | |
214 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | |
215 | #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ | |
216 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | |
217 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | |
218 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) | |
219 | #define I_DMA (I_RI | I_XI | I_ERRORS) | |
220 | ||
221 | /* corecontrol */ | |
222 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | |
223 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ | |
224 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | |
225 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ | |
226 | #define CC_XMTDATAAVAIL_MODE (1 << 4) | |
227 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) | |
228 | ||
229 | /* SDA_FRAMECTRL */ | |
230 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | |
231 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | |
232 | #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ | |
233 | #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ | |
234 | ||
5b435de0 AS |
235 | /* |
236 | * Software allocation of To SB Mailbox resources | |
237 | */ | |
238 | ||
239 | /* tosbmailbox bits corresponding to intstatus bits */ | |
240 | #define SMB_NAK (1 << 0) /* Frame NAK */ | |
241 | #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ | |
242 | #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ | |
243 | #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ | |
244 | ||
245 | /* tosbmailboxdata */ | |
246 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ | |
247 | ||
248 | /* | |
249 | * Software allocation of To Host Mailbox resources | |
250 | */ | |
251 | ||
252 | /* intstatus bits */ | |
253 | #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ | |
254 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ | |
255 | #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ | |
256 | #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ | |
257 | ||
258 | /* tohostmailboxdata */ | |
259 | #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ | |
260 | #define HMB_DATA_DEVREADY 2 /* talk to host after enable */ | |
261 | #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ | |
262 | #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ | |
263 | ||
264 | #define HMB_DATA_FCDATA_MASK 0xff000000 | |
265 | #define HMB_DATA_FCDATA_SHIFT 24 | |
266 | ||
267 | #define HMB_DATA_VERSION_MASK 0x00ff0000 | |
268 | #define HMB_DATA_VERSION_SHIFT 16 | |
269 | ||
270 | /* | |
271 | * Software-defined protocol header | |
272 | */ | |
273 | ||
274 | /* Current protocol version */ | |
275 | #define SDPCM_PROT_VERSION 4 | |
276 | ||
5b435de0 AS |
277 | /* |
278 | * Shared structure between dongle and the host. | |
279 | * The structure contains pointers to trap or assert information. | |
280 | */ | |
4fc0d016 | 281 | #define SDPCM_SHARED_VERSION 0x0003 |
5b435de0 AS |
282 | #define SDPCM_SHARED_VERSION_MASK 0x00FF |
283 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | |
284 | #define SDPCM_SHARED_ASSERT 0x0200 | |
285 | #define SDPCM_SHARED_TRAP 0x0400 | |
286 | ||
287 | /* Space for header read, limit for data packets */ | |
288 | #define MAX_HDR_READ (1 << 6) | |
289 | #define MAX_RX_DATASZ 2048 | |
290 | ||
5b435de0 AS |
291 | /* Bump up limit on waiting for HT to account for first startup; |
292 | * if the image is doing a CRC calculation before programming the PMU | |
293 | * for HT availability, it could take a couple hundred ms more, so | |
294 | * max out at a 1 second (1000000us). | |
295 | */ | |
296 | #undef PMU_MAX_TRANSITION_DLY | |
297 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
298 | ||
299 | /* Value for ChipClockCSR during initial setup */ | |
300 | #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ | |
301 | SBSDIO_ALP_AVAIL_REQ) | |
302 | ||
303 | /* Flags for SDH calls */ | |
304 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
305 | ||
382a9e0f FL |
306 | #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change |
307 | * when idle | |
308 | */ | |
309 | #define BRCMF_IDLE_INTERVAL 1 | |
310 | ||
4a3da990 PH |
311 | #define KSO_WAIT_US 50 |
312 | #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) | |
313 | ||
5b435de0 AS |
314 | /* |
315 | * Conversion of 802.1D priority to precedence level | |
316 | */ | |
317 | static uint prio2prec(u32 prio) | |
318 | { | |
319 | return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? | |
320 | (prio^2) : prio; | |
321 | } | |
322 | ||
8ae74654 | 323 | #ifdef DEBUG |
5b435de0 AS |
324 | /* Device console log buffer state */ |
325 | struct brcmf_console { | |
326 | uint count; /* Poll interval msec counter */ | |
327 | uint log_addr; /* Log struct address (fixed) */ | |
328 | struct rte_log_le log_le; /* Log struct (host copy) */ | |
329 | uint bufsize; /* Size of log buffer */ | |
330 | u8 *buf; /* Log buffer (host copy) */ | |
331 | uint last; /* Last buffer read index */ | |
332 | }; | |
4fc0d016 AS |
333 | |
334 | struct brcmf_trap_info { | |
335 | __le32 type; | |
336 | __le32 epc; | |
337 | __le32 cpsr; | |
338 | __le32 spsr; | |
339 | __le32 r0; /* a1 */ | |
340 | __le32 r1; /* a2 */ | |
341 | __le32 r2; /* a3 */ | |
342 | __le32 r3; /* a4 */ | |
343 | __le32 r4; /* v1 */ | |
344 | __le32 r5; /* v2 */ | |
345 | __le32 r6; /* v3 */ | |
346 | __le32 r7; /* v4 */ | |
347 | __le32 r8; /* v5 */ | |
348 | __le32 r9; /* sb/v6 */ | |
349 | __le32 r10; /* sl/v7 */ | |
350 | __le32 r11; /* fp/v8 */ | |
351 | __le32 r12; /* ip */ | |
352 | __le32 r13; /* sp */ | |
353 | __le32 r14; /* lr */ | |
354 | __le32 pc; /* r15 */ | |
355 | }; | |
8ae74654 | 356 | #endif /* DEBUG */ |
5b435de0 AS |
357 | |
358 | struct sdpcm_shared { | |
359 | u32 flags; | |
360 | u32 trap_addr; | |
361 | u32 assert_exp_addr; | |
362 | u32 assert_file_addr; | |
363 | u32 assert_line; | |
364 | u32 console_addr; /* Address of struct rte_console */ | |
365 | u32 msgtrace_addr; | |
366 | u8 tag[32]; | |
4fc0d016 | 367 | u32 brpt_addr; |
5b435de0 AS |
368 | }; |
369 | ||
370 | struct sdpcm_shared_le { | |
371 | __le32 flags; | |
372 | __le32 trap_addr; | |
373 | __le32 assert_exp_addr; | |
374 | __le32 assert_file_addr; | |
375 | __le32 assert_line; | |
376 | __le32 console_addr; /* Address of struct rte_console */ | |
377 | __le32 msgtrace_addr; | |
378 | u8 tag[32]; | |
4fc0d016 | 379 | __le32 brpt_addr; |
5b435de0 AS |
380 | }; |
381 | ||
6bc52319 FL |
382 | /* dongle SDIO bus specific header info */ |
383 | struct brcmf_sdio_hdrinfo { | |
4754fcee FL |
384 | u8 seq_num; |
385 | u8 channel; | |
386 | u16 len; | |
387 | u16 len_left; | |
388 | u16 len_nxtfrm; | |
389 | u8 dat_offset; | |
8da9d2c8 FL |
390 | bool lastfrm; |
391 | u16 tail_pad; | |
4754fcee | 392 | }; |
5b435de0 AS |
393 | |
394 | /* misc chip info needed by some of the routines */ | |
5b435de0 | 395 | /* Private data for SDIO bus interaction */ |
e92eedf4 | 396 | struct brcmf_sdio { |
5b435de0 | 397 | struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ |
9cf218fc | 398 | struct brcmf_chip *ci; /* Chip info struct */ |
5b435de0 AS |
399 | |
400 | u32 ramsize; /* Size of RAM in SOCRAM (bytes) */ | |
401 | ||
402 | u32 hostintmask; /* Copy of Host Interrupt Mask */ | |
4531603a FL |
403 | atomic_t intstatus; /* Intstatus bits (events) pending */ |
404 | atomic_t fcstate; /* State of dongle flow-control */ | |
5b435de0 AS |
405 | |
406 | uint blocksize; /* Block size of SDIO transfers */ | |
407 | uint roundup; /* Max roundup limit */ | |
408 | ||
409 | struct pktq txq; /* Queue length used for flow-control */ | |
410 | u8 flowcontrol; /* per prio flow control bitmask */ | |
411 | u8 tx_seq; /* Transmit sequence number (next) */ | |
412 | u8 tx_max; /* Maximum transmit sequence allowed */ | |
413 | ||
9b2d2f2a | 414 | u8 *hdrbuf; /* buffer for handling rx frame */ |
5b435de0 | 415 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ |
5b435de0 | 416 | u8 rx_seq; /* Receive sequence number (expected) */ |
6bc52319 | 417 | struct brcmf_sdio_hdrinfo cur_read; |
4754fcee | 418 | /* info of current read frame */ |
5b435de0 | 419 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ |
4754fcee | 420 | bool rxpending; /* Data frame pending in dongle */ |
5b435de0 AS |
421 | |
422 | uint rxbound; /* Rx frames to read before resched */ | |
423 | uint txbound; /* Tx frames to send before resched */ | |
424 | uint txminmax; | |
425 | ||
426 | struct sk_buff *glomd; /* Packet containing glomming descriptor */ | |
b83db862 | 427 | struct sk_buff_head glom; /* Packet list for glommed superframe */ |
5b435de0 AS |
428 | uint glomerr; /* Glom packet read errors */ |
429 | ||
430 | u8 *rxbuf; /* Buffer for receiving control packets */ | |
431 | uint rxblen; /* Allocated length of rxbuf */ | |
432 | u8 *rxctl; /* Aligned pointer into rxbuf */ | |
dd43a01c | 433 | u8 *rxctl_orig; /* pointer for freeing rxctl */ |
5b435de0 | 434 | uint rxlen; /* Length of valid data in buffer */ |
dd43a01c | 435 | spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ |
5b435de0 AS |
436 | |
437 | u8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
438 | ||
439 | bool intr; /* Use interrupts */ | |
440 | bool poll; /* Use polling */ | |
1d382273 | 441 | atomic_t ipend; /* Device interrupt is pending */ |
5b435de0 AS |
442 | uint spurious; /* Count of spurious interrupts */ |
443 | uint pollrate; /* Ticks between device polls */ | |
444 | uint polltick; /* Tick counter */ | |
5b435de0 | 445 | |
8ae74654 | 446 | #ifdef DEBUG |
5b435de0 AS |
447 | uint console_interval; |
448 | struct brcmf_console console; /* Console output polling support */ | |
449 | uint console_addr; /* Console address from shared struct */ | |
8ae74654 | 450 | #endif /* DEBUG */ |
5b435de0 | 451 | |
5b435de0 AS |
452 | uint clkstate; /* State of sd and backplane clock(s) */ |
453 | bool activity; /* Activity flag for clock down */ | |
454 | s32 idletime; /* Control for activity timeout */ | |
455 | s32 idlecount; /* Activity timeout counter */ | |
456 | s32 idleclock; /* How to set bus driver when idle */ | |
5b435de0 AS |
457 | bool rxflow_mode; /* Rx flow control mode */ |
458 | bool rxflow; /* Is rx flow control on */ | |
459 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
5b435de0 | 460 | |
5b435de0 | 461 | u8 *ctrl_frame_buf; |
fed7ec44 | 462 | u16 ctrl_frame_len; |
5b435de0 AS |
463 | bool ctrl_frame_stat; |
464 | ||
fed7ec44 HM |
465 | spinlock_t txq_lock; /* protect bus->txq */ |
466 | struct semaphore tx_seq_lock; /* protect bus->tx_seq */ | |
5b435de0 AS |
467 | wait_queue_head_t ctrl_wait; |
468 | wait_queue_head_t dcmd_resp_wait; | |
469 | ||
470 | struct timer_list timer; | |
471 | struct completion watchdog_wait; | |
472 | struct task_struct *watchdog_tsk; | |
473 | bool wd_timer_valid; | |
474 | uint save_ms; | |
475 | ||
f1e68c2e FL |
476 | struct workqueue_struct *brcmf_wq; |
477 | struct work_struct datawork; | |
fccfe930 | 478 | atomic_t dpc_tskcnt; |
5b435de0 | 479 | |
c8bf3484 | 480 | bool txoff; /* Transmit flow-controlled */ |
80969836 | 481 | struct brcmf_sdio_count sdcnt; |
4a3da990 PH |
482 | bool sr_enabled; /* SaveRestore enabled */ |
483 | bool sleeping; /* SDIO bus sleeping */ | |
706478cb FL |
484 | |
485 | u8 tx_hdrlen; /* sdio bus header length for tx packet */ | |
8da9d2c8 | 486 | bool txglom; /* host tx glomming enable flag */ |
e217d1c8 AS |
487 | u16 head_align; /* buffer pointer alignment */ |
488 | u16 sgentry_align; /* scatter-gather buffer alignment */ | |
5b435de0 AS |
489 | }; |
490 | ||
5b435de0 AS |
491 | /* clkstate */ |
492 | #define CLK_NONE 0 | |
493 | #define CLK_SDONLY 1 | |
4a3da990 | 494 | #define CLK_PENDING 2 |
5b435de0 AS |
495 | #define CLK_AVAIL 3 |
496 | ||
8ae74654 | 497 | #ifdef DEBUG |
5b435de0 | 498 | static int qcount[NUMPRIO]; |
8ae74654 | 499 | #endif /* DEBUG */ |
5b435de0 | 500 | |
668761ac | 501 | #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ |
5b435de0 AS |
502 | |
503 | #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) | |
504 | ||
505 | /* Retry count for register access failures */ | |
506 | static const uint retry_limit = 2; | |
507 | ||
508 | /* Limit on rounding up frames */ | |
509 | static const uint max_roundup = 512; | |
510 | ||
511 | #define ALIGNMENT 4 | |
512 | ||
9d7d6f95 FL |
513 | enum brcmf_sdio_frmtype { |
514 | BRCMF_SDIO_FT_NORMAL, | |
515 | BRCMF_SDIO_FT_SUPER, | |
516 | BRCMF_SDIO_FT_SUB, | |
517 | }; | |
518 | ||
65d80d0b AS |
519 | #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) |
520 | ||
521 | /* SDIO Pad drive strength to select value mappings */ | |
522 | struct sdiod_drive_str { | |
523 | u8 strength; /* Pad Drive Strength in mA */ | |
524 | u8 sel; /* Chip-specific select value */ | |
525 | }; | |
526 | ||
527 | /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ | |
528 | static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { | |
529 | {32, 0x6}, | |
530 | {26, 0x7}, | |
531 | {22, 0x4}, | |
532 | {16, 0x5}, | |
533 | {12, 0x2}, | |
534 | {8, 0x3}, | |
535 | {4, 0x0}, | |
536 | {0, 0x1} | |
537 | }; | |
538 | ||
539 | /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ | |
540 | static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { | |
541 | {6, 0x7}, | |
542 | {5, 0x6}, | |
543 | {4, 0x5}, | |
544 | {3, 0x4}, | |
545 | {2, 0x2}, | |
546 | {1, 0x1}, | |
547 | {0, 0x0} | |
548 | }; | |
549 | ||
550 | /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ | |
551 | static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { | |
552 | {3, 0x3}, | |
553 | {2, 0x2}, | |
554 | {1, 0x1}, | |
555 | {0, 0x0} }; | |
556 | ||
557 | /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ | |
558 | static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { | |
559 | {16, 0x7}, | |
560 | {12, 0x5}, | |
561 | {8, 0x3}, | |
562 | {4, 0x1} | |
563 | }; | |
564 | ||
f2c44fe7 HM |
565 | #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin" |
566 | #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt" | |
567 | #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin" | |
568 | #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt" | |
569 | #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin" | |
570 | #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt" | |
571 | #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin" | |
572 | #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt" | |
573 | #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin" | |
574 | #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt" | |
575 | #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin" | |
576 | #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt" | |
577 | #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin" | |
578 | #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt" | |
11e69c36 AS |
579 | #define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin" |
580 | #define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt" | |
bed89b64 FL |
581 | #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin" |
582 | #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt" | |
a797ca1e FL |
583 | #define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin" |
584 | #define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt" | |
f2c44fe7 HM |
585 | |
586 | MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME); | |
587 | MODULE_FIRMWARE(BCM43143_NVRAM_NAME); | |
588 | MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME); | |
589 | MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME); | |
590 | MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME); | |
591 | MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME); | |
592 | MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME); | |
593 | MODULE_FIRMWARE(BCM4329_NVRAM_NAME); | |
594 | MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME); | |
595 | MODULE_FIRMWARE(BCM4330_NVRAM_NAME); | |
596 | MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME); | |
597 | MODULE_FIRMWARE(BCM4334_NVRAM_NAME); | |
598 | MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME); | |
599 | MODULE_FIRMWARE(BCM4335_NVRAM_NAME); | |
11e69c36 AS |
600 | MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME); |
601 | MODULE_FIRMWARE(BCM43362_NVRAM_NAME); | |
bed89b64 FL |
602 | MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME); |
603 | MODULE_FIRMWARE(BCM4339_NVRAM_NAME); | |
a797ca1e FL |
604 | MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME); |
605 | MODULE_FIRMWARE(BCM4354_NVRAM_NAME); | |
f2c44fe7 HM |
606 | |
607 | struct brcmf_firmware_names { | |
608 | u32 chipid; | |
609 | u32 revmsk; | |
610 | const char *bin; | |
611 | const char *nv; | |
612 | }; | |
613 | ||
614 | enum brcmf_firmware_type { | |
615 | BRCMF_FIRMWARE_BIN, | |
616 | BRCMF_FIRMWARE_NVRAM | |
617 | }; | |
618 | ||
619 | #define BRCMF_FIRMWARE_NVRAM(name) \ | |
620 | name ## _FIRMWARE_NAME, name ## _NVRAM_NAME | |
621 | ||
622 | static const struct brcmf_firmware_names brcmf_fwname_data[] = { | |
623 | { BCM43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) }, | |
624 | { BCM43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) }, | |
625 | { BCM43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) }, | |
626 | { BCM4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) }, | |
627 | { BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) }, | |
628 | { BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) }, | |
bed89b64 | 629 | { BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) }, |
11e69c36 | 630 | { BCM43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) }, |
a797ca1e FL |
631 | { BCM4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }, |
632 | { BCM4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) } | |
f2c44fe7 HM |
633 | }; |
634 | ||
bd0e1b1d AS |
635 | static const char *brcmf_sdio_get_fwname(struct brcmf_chip *ci, |
636 | enum brcmf_firmware_type type) | |
f2c44fe7 | 637 | { |
bd0e1b1d | 638 | int i; |
f2c44fe7 HM |
639 | |
640 | for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) { | |
bd0e1b1d AS |
641 | if (brcmf_fwname_data[i].chipid == ci->chip && |
642 | brcmf_fwname_data[i].revmsk & BIT(ci->chiprev)) { | |
f2c44fe7 HM |
643 | switch (type) { |
644 | case BRCMF_FIRMWARE_BIN: | |
bd0e1b1d | 645 | return brcmf_fwname_data[i].bin; |
f2c44fe7 | 646 | case BRCMF_FIRMWARE_NVRAM: |
bd0e1b1d | 647 | return brcmf_fwname_data[i].nv; |
f2c44fe7 HM |
648 | default: |
649 | brcmf_err("invalid firmware type (%d)\n", type); | |
650 | return NULL; | |
651 | } | |
f2c44fe7 HM |
652 | } |
653 | } | |
654 | brcmf_err("Unknown chipid %d [%d]\n", | |
bd0e1b1d | 655 | ci->chip, ci->chiprev); |
f2c44fe7 | 656 | return NULL; |
f2c44fe7 HM |
657 | } |
658 | ||
5b435de0 AS |
659 | static void pkt_align(struct sk_buff *p, int len, int align) |
660 | { | |
661 | uint datalign; | |
662 | datalign = (unsigned long)(p->data); | |
663 | datalign = roundup(datalign, (align)) - datalign; | |
664 | if (datalign) | |
665 | skb_pull(p, datalign); | |
666 | __skb_trim(p, len); | |
667 | } | |
668 | ||
669 | /* To check if there's window offered */ | |
e92eedf4 | 670 | static bool data_ok(struct brcmf_sdio *bus) |
5b435de0 AS |
671 | { |
672 | return (u8)(bus->tx_max - bus->tx_seq) != 0 && | |
673 | ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; | |
674 | } | |
675 | ||
676 | /* | |
677 | * Reads a register in the SDIO hardware block. This block occupies a series of | |
678 | * adresses on the 32 bit backplane bus. | |
679 | */ | |
cb7cf7be | 680 | static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset) |
5b435de0 | 681 | { |
cb7cf7be | 682 | struct brcmf_core *core; |
79ae3957 | 683 | int ret; |
58692750 | 684 | |
cb7cf7be AS |
685 | core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
686 | *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret); | |
58692750 FL |
687 | |
688 | return ret; | |
5b435de0 AS |
689 | } |
690 | ||
cb7cf7be | 691 | static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) |
5b435de0 | 692 | { |
cb7cf7be | 693 | struct brcmf_core *core; |
e13ce26b | 694 | int ret; |
58692750 | 695 | |
cb7cf7be AS |
696 | core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
697 | brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret); | |
58692750 FL |
698 | |
699 | return ret; | |
5b435de0 AS |
700 | } |
701 | ||
4a3da990 | 702 | static int |
82d7f3c1 | 703 | brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) |
4a3da990 PH |
704 | { |
705 | u8 wr_val = 0, rd_val, cmp_val, bmask; | |
706 | int err = 0; | |
707 | int try_cnt = 0; | |
708 | ||
8a385ba5 | 709 | brcmf_dbg(TRACE, "Enter: on=%d\n", on); |
4a3da990 PH |
710 | |
711 | wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
712 | /* 1st KSO write goes to AOS wake up core if device is asleep */ | |
a39be27b AS |
713 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
714 | wr_val, &err); | |
4a3da990 PH |
715 | |
716 | if (on) { | |
717 | /* device WAKEUP through KSO: | |
718 | * write bit 0 & read back until | |
719 | * both bits 0 (kso bit) & 1 (dev on status) are set | |
720 | */ | |
721 | cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | | |
722 | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; | |
723 | bmask = cmp_val; | |
724 | usleep_range(2000, 3000); | |
725 | } else { | |
726 | /* Put device to sleep, turn off KSO */ | |
727 | cmp_val = 0; | |
728 | /* only check for bit0, bit1(dev on status) may not | |
729 | * get cleared right away | |
730 | */ | |
731 | bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; | |
732 | } | |
733 | ||
734 | do { | |
735 | /* reliable KSO bit set/clr: | |
736 | * the sdiod sleep write access is synced to PMU 32khz clk | |
737 | * just one write attempt may fail, | |
738 | * read it back until it matches written value | |
739 | */ | |
a39be27b AS |
740 | rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
741 | &err); | |
4a3da990 PH |
742 | if (((rd_val & bmask) == cmp_val) && !err) |
743 | break; | |
8a385ba5 | 744 | |
4a3da990 | 745 | udelay(KSO_WAIT_US); |
a39be27b AS |
746 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
747 | wr_val, &err); | |
4a3da990 PH |
748 | } while (try_cnt++ < MAX_KSO_ATTEMPTS); |
749 | ||
8a385ba5 AS |
750 | if (try_cnt > 2) |
751 | brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, | |
752 | rd_val, err); | |
753 | ||
754 | if (try_cnt > MAX_KSO_ATTEMPTS) | |
755 | brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); | |
756 | ||
4a3da990 PH |
757 | return err; |
758 | } | |
759 | ||
5b435de0 AS |
760 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) |
761 | ||
5b435de0 | 762 | /* Turn backplane clock on or off */ |
82d7f3c1 | 763 | static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) |
5b435de0 AS |
764 | { |
765 | int err; | |
766 | u8 clkctl, clkreq, devctl; | |
767 | unsigned long timeout; | |
768 | ||
c3203374 | 769 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
770 | |
771 | clkctl = 0; | |
772 | ||
4a3da990 PH |
773 | if (bus->sr_enabled) { |
774 | bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); | |
775 | return 0; | |
776 | } | |
777 | ||
5b435de0 AS |
778 | if (on) { |
779 | /* Request HT Avail */ | |
780 | clkreq = | |
781 | bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
782 | ||
a39be27b AS |
783 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
784 | clkreq, &err); | |
5b435de0 | 785 | if (err) { |
5e8149f5 | 786 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
787 | return -EBADE; |
788 | } | |
789 | ||
5b435de0 | 790 | /* Check current status */ |
a39be27b AS |
791 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
792 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 793 | if (err) { |
5e8149f5 | 794 | brcmf_err("HT Avail read error: %d\n", err); |
5b435de0 AS |
795 | return -EBADE; |
796 | } | |
797 | ||
798 | /* Go to pending and await interrupt if appropriate */ | |
799 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
800 | /* Allow only clock-available interrupt */ | |
a39be27b AS |
801 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
802 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 803 | if (err) { |
5e8149f5 | 804 | brcmf_err("Devctl error setting CA: %d\n", |
5b435de0 AS |
805 | err); |
806 | return -EBADE; | |
807 | } | |
808 | ||
809 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
a39be27b AS |
810 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
811 | devctl, &err); | |
c3203374 | 812 | brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); |
5b435de0 AS |
813 | bus->clkstate = CLK_PENDING; |
814 | ||
815 | return 0; | |
816 | } else if (bus->clkstate == CLK_PENDING) { | |
817 | /* Cancel CA-only interrupt filter */ | |
a39be27b AS |
818 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
819 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 820 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
821 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
822 | devctl, &err); | |
5b435de0 AS |
823 | } |
824 | ||
825 | /* Otherwise, wait here (polling) for HT Avail */ | |
826 | timeout = jiffies + | |
827 | msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); | |
828 | while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
a39be27b AS |
829 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
830 | SBSDIO_FUNC1_CHIPCLKCSR, | |
831 | &err); | |
5b435de0 AS |
832 | if (time_after(jiffies, timeout)) |
833 | break; | |
834 | else | |
835 | usleep_range(5000, 10000); | |
836 | } | |
837 | if (err) { | |
5e8149f5 | 838 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
839 | return -EBADE; |
840 | } | |
841 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
5e8149f5 | 842 | brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", |
5b435de0 AS |
843 | PMU_MAX_TRANSITION_DLY, clkctl); |
844 | return -EBADE; | |
845 | } | |
846 | ||
847 | /* Mark clock available */ | |
848 | bus->clkstate = CLK_AVAIL; | |
c3203374 | 849 | brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); |
5b435de0 | 850 | |
8ae74654 | 851 | #if defined(DEBUG) |
23677ce3 | 852 | if (!bus->alp_only) { |
5b435de0 | 853 | if (SBSDIO_ALPONLY(clkctl)) |
5e8149f5 | 854 | brcmf_err("HT Clock should be on\n"); |
5b435de0 | 855 | } |
8ae74654 | 856 | #endif /* defined (DEBUG) */ |
5b435de0 | 857 | |
5b435de0 AS |
858 | } else { |
859 | clkreq = 0; | |
860 | ||
861 | if (bus->clkstate == CLK_PENDING) { | |
862 | /* Cancel CA-only interrupt filter */ | |
a39be27b AS |
863 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
864 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 865 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
866 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
867 | devctl, &err); | |
5b435de0 AS |
868 | } |
869 | ||
870 | bus->clkstate = CLK_SDONLY; | |
a39be27b AS |
871 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
872 | clkreq, &err); | |
c3203374 | 873 | brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); |
5b435de0 | 874 | if (err) { |
5e8149f5 | 875 | brcmf_err("Failed access turning clock off: %d\n", |
5b435de0 AS |
876 | err); |
877 | return -EBADE; | |
878 | } | |
879 | } | |
880 | return 0; | |
881 | } | |
882 | ||
883 | /* Change idle/active SD state */ | |
82d7f3c1 | 884 | static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) |
5b435de0 | 885 | { |
c3203374 | 886 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
887 | |
888 | if (on) | |
889 | bus->clkstate = CLK_SDONLY; | |
890 | else | |
891 | bus->clkstate = CLK_NONE; | |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
896 | /* Transition SD and backplane clock readiness */ | |
82d7f3c1 | 897 | static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) |
5b435de0 | 898 | { |
8ae74654 | 899 | #ifdef DEBUG |
5b435de0 | 900 | uint oldstate = bus->clkstate; |
8ae74654 | 901 | #endif /* DEBUG */ |
5b435de0 | 902 | |
c3203374 | 903 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
904 | |
905 | /* Early exit if we're already there */ | |
906 | if (bus->clkstate == target) { | |
907 | if (target == CLK_AVAIL) { | |
82d7f3c1 | 908 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); |
5b435de0 AS |
909 | bus->activity = true; |
910 | } | |
911 | return 0; | |
912 | } | |
913 | ||
914 | switch (target) { | |
915 | case CLK_AVAIL: | |
916 | /* Make sure SD clock is available */ | |
917 | if (bus->clkstate == CLK_NONE) | |
82d7f3c1 | 918 | brcmf_sdio_sdclk(bus, true); |
5b435de0 | 919 | /* Now request HT Avail on the backplane */ |
82d7f3c1 AS |
920 | brcmf_sdio_htclk(bus, true, pendok); |
921 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); | |
5b435de0 AS |
922 | bus->activity = true; |
923 | break; | |
924 | ||
925 | case CLK_SDONLY: | |
926 | /* Remove HT request, or bring up SD clock */ | |
927 | if (bus->clkstate == CLK_NONE) | |
82d7f3c1 | 928 | brcmf_sdio_sdclk(bus, true); |
5b435de0 | 929 | else if (bus->clkstate == CLK_AVAIL) |
82d7f3c1 | 930 | brcmf_sdio_htclk(bus, false, false); |
5b435de0 | 931 | else |
5e8149f5 | 932 | brcmf_err("request for %d -> %d\n", |
5b435de0 | 933 | bus->clkstate, target); |
82d7f3c1 | 934 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); |
5b435de0 AS |
935 | break; |
936 | ||
937 | case CLK_NONE: | |
938 | /* Make sure to remove HT request */ | |
939 | if (bus->clkstate == CLK_AVAIL) | |
82d7f3c1 | 940 | brcmf_sdio_htclk(bus, false, false); |
5b435de0 | 941 | /* Now remove the SD clock */ |
82d7f3c1 AS |
942 | brcmf_sdio_sdclk(bus, false); |
943 | brcmf_sdio_wd_timer(bus, 0); | |
5b435de0 AS |
944 | break; |
945 | } | |
8ae74654 | 946 | #ifdef DEBUG |
c3203374 | 947 | brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); |
8ae74654 | 948 | #endif /* DEBUG */ |
5b435de0 AS |
949 | |
950 | return 0; | |
951 | } | |
952 | ||
4a3da990 | 953 | static int |
82d7f3c1 | 954 | brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) |
4a3da990 PH |
955 | { |
956 | int err = 0; | |
8a385ba5 | 957 | u8 clkcsr; |
82030d6d AS |
958 | |
959 | brcmf_dbg(SDIO, "Enter: request %s currently %s\n", | |
4a3da990 PH |
960 | (sleep ? "SLEEP" : "WAKE"), |
961 | (bus->sleeping ? "SLEEP" : "WAKE")); | |
962 | ||
963 | /* If SR is enabled control bus state with KSO */ | |
964 | if (bus->sr_enabled) { | |
965 | /* Done if we're already in the requested state */ | |
966 | if (sleep == bus->sleeping) | |
967 | goto end; | |
968 | ||
969 | /* Going to sleep */ | |
970 | if (sleep) { | |
971 | /* Don't sleep if something is pending */ | |
972 | if (atomic_read(&bus->intstatus) || | |
973 | atomic_read(&bus->ipend) > 0 || | |
974 | (!atomic_read(&bus->fcstate) && | |
975 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
8a385ba5 AS |
976 | data_ok(bus))) { |
977 | err = -EBUSY; | |
978 | goto done; | |
979 | } | |
980 | ||
981 | clkcsr = brcmf_sdiod_regrb(bus->sdiodev, | |
982 | SBSDIO_FUNC1_CHIPCLKCSR, | |
983 | &err); | |
984 | if ((clkcsr & SBSDIO_CSR_MASK) == 0) { | |
985 | brcmf_dbg(SDIO, "no clock, set ALP\n"); | |
986 | brcmf_sdiod_regwb(bus->sdiodev, | |
987 | SBSDIO_FUNC1_CHIPCLKCSR, | |
988 | SBSDIO_ALP_AVAIL_REQ, &err); | |
989 | } | |
82d7f3c1 | 990 | err = brcmf_sdio_kso_control(bus, false); |
4a3da990 PH |
991 | /* disable watchdog */ |
992 | if (!err) | |
82d7f3c1 | 993 | brcmf_sdio_wd_timer(bus, 0); |
4a3da990 PH |
994 | } else { |
995 | bus->idlecount = 0; | |
82d7f3c1 | 996 | err = brcmf_sdio_kso_control(bus, true); |
4a3da990 PH |
997 | } |
998 | if (!err) { | |
999 | /* Change state */ | |
1000 | bus->sleeping = sleep; | |
1001 | brcmf_dbg(SDIO, "new state %s\n", | |
1002 | (sleep ? "SLEEP" : "WAKE")); | |
1003 | } else { | |
1004 | brcmf_err("error while changing bus sleep state %d\n", | |
1005 | err); | |
8a385ba5 | 1006 | goto done; |
4a3da990 PH |
1007 | } |
1008 | } | |
1009 | ||
1010 | end: | |
1011 | /* control clocks */ | |
1012 | if (sleep) { | |
1013 | if (!bus->sr_enabled) | |
82d7f3c1 | 1014 | brcmf_sdio_clkctl(bus, CLK_NONE, pendok); |
4a3da990 | 1015 | } else { |
82d7f3c1 | 1016 | brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); |
4a3da990 | 1017 | } |
8a385ba5 AS |
1018 | done: |
1019 | brcmf_dbg(SDIO, "Exit: err=%d\n", err); | |
4a3da990 PH |
1020 | return err; |
1021 | ||
1022 | } | |
1023 | ||
0801e6c5 DK |
1024 | #ifdef DEBUG |
1025 | static inline bool brcmf_sdio_valid_shared_address(u32 addr) | |
1026 | { | |
1027 | return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); | |
1028 | } | |
1029 | ||
1030 | static int brcmf_sdio_readshared(struct brcmf_sdio *bus, | |
1031 | struct sdpcm_shared *sh) | |
1032 | { | |
1033 | u32 addr; | |
1034 | int rv; | |
1035 | u32 shaddr = 0; | |
1036 | struct sdpcm_shared_le sh_le; | |
1037 | __le32 addr_le; | |
1038 | ||
1039 | shaddr = bus->ci->rambase + bus->ramsize - 4; | |
1040 | ||
1041 | /* | |
1042 | * Read last word in socram to determine | |
1043 | * address of sdpcm_shared structure | |
1044 | */ | |
1045 | sdio_claim_host(bus->sdiodev->func[1]); | |
1046 | brcmf_sdio_bus_sleep(bus, false, false); | |
1047 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4); | |
1048 | sdio_release_host(bus->sdiodev->func[1]); | |
1049 | if (rv < 0) | |
1050 | return rv; | |
1051 | ||
1052 | addr = le32_to_cpu(addr_le); | |
1053 | ||
1054 | brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr); | |
1055 | ||
1056 | /* | |
1057 | * Check if addr is valid. | |
1058 | * NVRAM length at the end of memory should have been overwritten. | |
1059 | */ | |
1060 | if (!brcmf_sdio_valid_shared_address(addr)) { | |
1061 | brcmf_err("invalid sdpcm_shared address 0x%08X\n", | |
1062 | addr); | |
1063 | return -EINVAL; | |
1064 | } | |
1065 | ||
1066 | /* Read hndrte_shared structure */ | |
1067 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, | |
1068 | sizeof(struct sdpcm_shared_le)); | |
1069 | if (rv < 0) | |
1070 | return rv; | |
1071 | ||
1072 | /* Endianness */ | |
1073 | sh->flags = le32_to_cpu(sh_le.flags); | |
1074 | sh->trap_addr = le32_to_cpu(sh_le.trap_addr); | |
1075 | sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); | |
1076 | sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); | |
1077 | sh->assert_line = le32_to_cpu(sh_le.assert_line); | |
1078 | sh->console_addr = le32_to_cpu(sh_le.console_addr); | |
1079 | sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); | |
1080 | ||
1081 | if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { | |
1082 | brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", | |
1083 | SDPCM_SHARED_VERSION, | |
1084 | sh->flags & SDPCM_SHARED_VERSION_MASK); | |
1085 | return -EPROTO; | |
1086 | } | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) | |
1092 | { | |
1093 | struct sdpcm_shared sh; | |
1094 | ||
1095 | if (brcmf_sdio_readshared(bus, &sh) == 0) | |
1096 | bus->console_addr = sh.console_addr; | |
1097 | } | |
1098 | #else | |
1099 | static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) | |
1100 | { | |
1101 | } | |
1102 | #endif /* DEBUG */ | |
1103 | ||
82d7f3c1 | 1104 | static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) |
5b435de0 AS |
1105 | { |
1106 | u32 intstatus = 0; | |
1107 | u32 hmb_data; | |
1108 | u8 fcbits; | |
58692750 | 1109 | int ret; |
5b435de0 | 1110 | |
c3203374 | 1111 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
1112 | |
1113 | /* Read mailbox data and ack that we did so */ | |
58692750 FL |
1114 | ret = r_sdreg32(bus, &hmb_data, |
1115 | offsetof(struct sdpcmd_regs, tohostmailboxdata)); | |
5b435de0 | 1116 | |
58692750 | 1117 | if (ret == 0) |
5b435de0 | 1118 | w_sdreg32(bus, SMB_INT_ACK, |
58692750 | 1119 | offsetof(struct sdpcmd_regs, tosbmailbox)); |
80969836 | 1120 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1121 | |
1122 | /* Dongle recomposed rx frames, accept them again */ | |
1123 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
c3203374 | 1124 | brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", |
5b435de0 AS |
1125 | bus->rx_seq); |
1126 | if (!bus->rxskip) | |
5e8149f5 | 1127 | brcmf_err("unexpected NAKHANDLED!\n"); |
5b435de0 AS |
1128 | |
1129 | bus->rxskip = false; | |
1130 | intstatus |= I_HMB_FRAME_IND; | |
1131 | } | |
1132 | ||
1133 | /* | |
1134 | * DEVREADY does not occur with gSPI. | |
1135 | */ | |
1136 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
1137 | bus->sdpcm_ver = | |
1138 | (hmb_data & HMB_DATA_VERSION_MASK) >> | |
1139 | HMB_DATA_VERSION_SHIFT; | |
1140 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
5e8149f5 | 1141 | brcmf_err("Version mismatch, dongle reports %d, " |
5b435de0 AS |
1142 | "expecting %d\n", |
1143 | bus->sdpcm_ver, SDPCM_PROT_VERSION); | |
1144 | else | |
c3203374 | 1145 | brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", |
5b435de0 | 1146 | bus->sdpcm_ver); |
0801e6c5 DK |
1147 | |
1148 | /* | |
1149 | * Retrieve console state address now that firmware should have | |
1150 | * updated it. | |
1151 | */ | |
1152 | brcmf_sdio_get_console_addr(bus); | |
5b435de0 AS |
1153 | } |
1154 | ||
1155 | /* | |
1156 | * Flow Control has been moved into the RX headers and this out of band | |
1157 | * method isn't used any more. | |
1158 | * remaining backward compatible with older dongles. | |
1159 | */ | |
1160 | if (hmb_data & HMB_DATA_FC) { | |
1161 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> | |
1162 | HMB_DATA_FCDATA_SHIFT; | |
1163 | ||
1164 | if (fcbits & ~bus->flowcontrol) | |
80969836 | 1165 | bus->sdcnt.fc_xoff++; |
5b435de0 AS |
1166 | |
1167 | if (bus->flowcontrol & ~fcbits) | |
80969836 | 1168 | bus->sdcnt.fc_xon++; |
5b435de0 | 1169 | |
80969836 | 1170 | bus->sdcnt.fc_rcvd++; |
5b435de0 AS |
1171 | bus->flowcontrol = fcbits; |
1172 | } | |
1173 | ||
1174 | /* Shouldn't be any others */ | |
1175 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
1176 | HMB_DATA_NAKHANDLED | | |
1177 | HMB_DATA_FC | | |
1178 | HMB_DATA_FWREADY | | |
1179 | HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) | |
5e8149f5 | 1180 | brcmf_err("Unknown mailbox data content: 0x%02x\n", |
5b435de0 AS |
1181 | hmb_data); |
1182 | ||
1183 | return intstatus; | |
1184 | } | |
1185 | ||
82d7f3c1 | 1186 | static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) |
5b435de0 AS |
1187 | { |
1188 | uint retries = 0; | |
1189 | u16 lastrbc; | |
1190 | u8 hi, lo; | |
1191 | int err; | |
1192 | ||
5e8149f5 | 1193 | brcmf_err("%sterminate frame%s\n", |
5b435de0 AS |
1194 | abort ? "abort command, " : "", |
1195 | rtx ? ", send NAK" : ""); | |
1196 | ||
1197 | if (abort) | |
a39be27b | 1198 | brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2); |
5b435de0 | 1199 | |
a39be27b AS |
1200 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
1201 | SFC_RF_TERM, &err); | |
80969836 | 1202 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
1203 | |
1204 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
1205 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
a39be27b AS |
1206 | hi = brcmf_sdiod_regrb(bus->sdiodev, |
1207 | SBSDIO_FUNC1_RFRAMEBCHI, &err); | |
1208 | lo = brcmf_sdiod_regrb(bus->sdiodev, | |
1209 | SBSDIO_FUNC1_RFRAMEBCLO, &err); | |
80969836 | 1210 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1211 | |
1212 | if ((hi == 0) && (lo == 0)) | |
1213 | break; | |
1214 | ||
1215 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
5e8149f5 | 1216 | brcmf_err("count growing: last 0x%04x now 0x%04x\n", |
5b435de0 AS |
1217 | lastrbc, (hi << 8) + lo); |
1218 | } | |
1219 | lastrbc = (hi << 8) + lo; | |
1220 | } | |
1221 | ||
1222 | if (!retries) | |
5e8149f5 | 1223 | brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); |
5b435de0 | 1224 | else |
c3203374 | 1225 | brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); |
5b435de0 AS |
1226 | |
1227 | if (rtx) { | |
80969836 | 1228 | bus->sdcnt.rxrtx++; |
58692750 FL |
1229 | err = w_sdreg32(bus, SMB_NAK, |
1230 | offsetof(struct sdpcmd_regs, tosbmailbox)); | |
5b435de0 | 1231 | |
80969836 | 1232 | bus->sdcnt.f1regdata++; |
58692750 | 1233 | if (err == 0) |
5b435de0 AS |
1234 | bus->rxskip = true; |
1235 | } | |
1236 | ||
1237 | /* Clear partial in any case */ | |
4754fcee | 1238 | bus->cur_read.len = 0; |
5b435de0 AS |
1239 | } |
1240 | ||
81c7883c HM |
1241 | static void brcmf_sdio_txfail(struct brcmf_sdio *bus) |
1242 | { | |
1243 | struct brcmf_sdio_dev *sdiodev = bus->sdiodev; | |
1244 | u8 i, hi, lo; | |
1245 | ||
1246 | /* On failure, abort the command and terminate the frame */ | |
1247 | brcmf_err("sdio error, abort command and terminate frame\n"); | |
1248 | bus->sdcnt.tx_sderrs++; | |
1249 | ||
1250 | brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2); | |
1251 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); | |
1252 | bus->sdcnt.f1regdata++; | |
1253 | ||
1254 | for (i = 0; i < 3; i++) { | |
1255 | hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); | |
1256 | lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); | |
1257 | bus->sdcnt.f1regdata += 2; | |
1258 | if ((hi == 0) && (lo == 0)) | |
1259 | break; | |
1260 | } | |
1261 | } | |
1262 | ||
9a95e60e | 1263 | /* return total length of buffer chain */ |
82d7f3c1 | 1264 | static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) |
9a95e60e AS |
1265 | { |
1266 | struct sk_buff *p; | |
1267 | uint total; | |
1268 | ||
1269 | total = 0; | |
1270 | skb_queue_walk(&bus->glom, p) | |
1271 | total += p->len; | |
1272 | return total; | |
1273 | } | |
1274 | ||
82d7f3c1 | 1275 | static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) |
046808da AS |
1276 | { |
1277 | struct sk_buff *cur, *next; | |
1278 | ||
1279 | skb_queue_walk_safe(&bus->glom, cur, next) { | |
1280 | skb_unlink(cur, &bus->glom); | |
1281 | brcmu_pkt_buf_free_skb(cur); | |
1282 | } | |
1283 | } | |
1284 | ||
6bc52319 FL |
1285 | /** |
1286 | * brcmfmac sdio bus specific header | |
1287 | * This is the lowest layer header wrapped on the packets transmitted between | |
1288 | * host and WiFi dongle which contains information needed for SDIO core and | |
1289 | * firmware | |
1290 | * | |
8da9d2c8 FL |
1291 | * It consists of 3 parts: hardware header, hardware extension header and |
1292 | * software header | |
6bc52319 FL |
1293 | * hardware header (frame tag) - 4 bytes |
1294 | * Byte 0~1: Frame length | |
1295 | * Byte 2~3: Checksum, bit-wise inverse of frame length | |
8da9d2c8 FL |
1296 | * hardware extension header - 8 bytes |
1297 | * Tx glom mode only, N/A for Rx or normal Tx | |
1298 | * Byte 0~1: Packet length excluding hw frame tag | |
1299 | * Byte 2: Reserved | |
1300 | * Byte 3: Frame flags, bit 0: last frame indication | |
1301 | * Byte 4~5: Reserved | |
1302 | * Byte 6~7: Tail padding length | |
6bc52319 FL |
1303 | * software header - 8 bytes |
1304 | * Byte 0: Rx/Tx sequence number | |
1305 | * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag | |
1306 | * Byte 2: Length of next data frame, reserved for Tx | |
1307 | * Byte 3: Data offset | |
1308 | * Byte 4: Flow control bits, reserved for Tx | |
1309 | * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet | |
1310 | * Byte 6~7: Reserved | |
1311 | */ | |
1312 | #define SDPCM_HWHDR_LEN 4 | |
8da9d2c8 | 1313 | #define SDPCM_HWEXT_LEN 8 |
6bc52319 FL |
1314 | #define SDPCM_SWHDR_LEN 8 |
1315 | #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) | |
6bc52319 FL |
1316 | /* software header */ |
1317 | #define SDPCM_SEQ_MASK 0x000000ff | |
1318 | #define SDPCM_SEQ_WRAP 256 | |
1319 | #define SDPCM_CHANNEL_MASK 0x00000f00 | |
1320 | #define SDPCM_CHANNEL_SHIFT 8 | |
1321 | #define SDPCM_CONTROL_CHANNEL 0 /* Control */ | |
1322 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ | |
1323 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ | |
1324 | #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ | |
1325 | #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ | |
1326 | #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) | |
1327 | #define SDPCM_NEXTLEN_MASK 0x00ff0000 | |
1328 | #define SDPCM_NEXTLEN_SHIFT 16 | |
1329 | #define SDPCM_DOFFSET_MASK 0xff000000 | |
1330 | #define SDPCM_DOFFSET_SHIFT 24 | |
1331 | #define SDPCM_FCMASK_MASK 0x000000ff | |
1332 | #define SDPCM_WINDOW_MASK 0x0000ff00 | |
1333 | #define SDPCM_WINDOW_SHIFT 8 | |
1334 | ||
1335 | static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) | |
1336 | { | |
1337 | u32 hdrvalue; | |
1338 | hdrvalue = *(u32 *)swheader; | |
1339 | return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); | |
1340 | } | |
1341 | ||
1342 | static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, | |
1343 | struct brcmf_sdio_hdrinfo *rd, | |
1344 | enum brcmf_sdio_frmtype type) | |
4754fcee FL |
1345 | { |
1346 | u16 len, checksum; | |
1347 | u8 rx_seq, fc, tx_seq_max; | |
6bc52319 | 1348 | u32 swheader; |
4754fcee | 1349 | |
4b776961 | 1350 | trace_brcmf_sdpcm_hdr(SDPCM_RX, header); |
76584ece | 1351 | |
6bc52319 | 1352 | /* hw header */ |
4754fcee FL |
1353 | len = get_unaligned_le16(header); |
1354 | checksum = get_unaligned_le16(header + sizeof(u16)); | |
1355 | /* All zero means no more to read */ | |
1356 | if (!(len | checksum)) { | |
1357 | bus->rxpending = false; | |
10510589 | 1358 | return -ENODATA; |
4754fcee FL |
1359 | } |
1360 | if ((u16)(~(len ^ checksum))) { | |
5e8149f5 | 1361 | brcmf_err("HW header checksum error\n"); |
4754fcee | 1362 | bus->sdcnt.rx_badhdr++; |
82d7f3c1 | 1363 | brcmf_sdio_rxfail(bus, false, false); |
10510589 | 1364 | return -EIO; |
4754fcee FL |
1365 | } |
1366 | if (len < SDPCM_HDRLEN) { | |
5e8149f5 | 1367 | brcmf_err("HW header length error\n"); |
10510589 | 1368 | return -EPROTO; |
4754fcee | 1369 | } |
9d7d6f95 FL |
1370 | if (type == BRCMF_SDIO_FT_SUPER && |
1371 | (roundup(len, bus->blocksize) != rd->len)) { | |
5e8149f5 | 1372 | brcmf_err("HW superframe header length error\n"); |
10510589 | 1373 | return -EPROTO; |
9d7d6f95 FL |
1374 | } |
1375 | if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { | |
5e8149f5 | 1376 | brcmf_err("HW subframe header length error\n"); |
10510589 | 1377 | return -EPROTO; |
9d7d6f95 | 1378 | } |
4754fcee FL |
1379 | rd->len = len; |
1380 | ||
6bc52319 FL |
1381 | /* software header */ |
1382 | header += SDPCM_HWHDR_LEN; | |
1383 | swheader = le32_to_cpu(*(__le32 *)header); | |
1384 | if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { | |
5e8149f5 | 1385 | brcmf_err("Glom descriptor found in superframe head\n"); |
9d7d6f95 | 1386 | rd->len = 0; |
10510589 | 1387 | return -EINVAL; |
9d7d6f95 | 1388 | } |
6bc52319 FL |
1389 | rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); |
1390 | rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; | |
9d7d6f95 FL |
1391 | if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && |
1392 | type != BRCMF_SDIO_FT_SUPER) { | |
5e8149f5 | 1393 | brcmf_err("HW header length too long\n"); |
4754fcee | 1394 | bus->sdcnt.rx_toolong++; |
82d7f3c1 | 1395 | brcmf_sdio_rxfail(bus, false, false); |
4754fcee | 1396 | rd->len = 0; |
10510589 | 1397 | return -EPROTO; |
4754fcee | 1398 | } |
9d7d6f95 | 1399 | if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { |
5e8149f5 | 1400 | brcmf_err("Wrong channel for superframe\n"); |
9d7d6f95 | 1401 | rd->len = 0; |
10510589 | 1402 | return -EINVAL; |
9d7d6f95 FL |
1403 | } |
1404 | if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && | |
1405 | rd->channel != SDPCM_EVENT_CHANNEL) { | |
5e8149f5 | 1406 | brcmf_err("Wrong channel for subframe\n"); |
9d7d6f95 | 1407 | rd->len = 0; |
10510589 | 1408 | return -EINVAL; |
9d7d6f95 | 1409 | } |
6bc52319 | 1410 | rd->dat_offset = brcmf_sdio_getdatoffset(header); |
4754fcee | 1411 | if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { |
5e8149f5 | 1412 | brcmf_err("seq %d: bad data offset\n", rx_seq); |
4754fcee | 1413 | bus->sdcnt.rx_badhdr++; |
82d7f3c1 | 1414 | brcmf_sdio_rxfail(bus, false, false); |
4754fcee | 1415 | rd->len = 0; |
10510589 | 1416 | return -ENXIO; |
4754fcee FL |
1417 | } |
1418 | if (rd->seq_num != rx_seq) { | |
5e8149f5 | 1419 | brcmf_err("seq %d: sequence number error, expect %d\n", |
4754fcee FL |
1420 | rx_seq, rd->seq_num); |
1421 | bus->sdcnt.rx_badseq++; | |
1422 | rd->seq_num = rx_seq; | |
1423 | } | |
9d7d6f95 FL |
1424 | /* no need to check the reset for subframe */ |
1425 | if (type == BRCMF_SDIO_FT_SUB) | |
10510589 | 1426 | return 0; |
6bc52319 | 1427 | rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; |
4754fcee FL |
1428 | if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { |
1429 | /* only warm for NON glom packet */ | |
1430 | if (rd->channel != SDPCM_GLOM_CHANNEL) | |
5e8149f5 | 1431 | brcmf_err("seq %d: next length error\n", rx_seq); |
4754fcee FL |
1432 | rd->len_nxtfrm = 0; |
1433 | } | |
6bc52319 FL |
1434 | swheader = le32_to_cpu(*(__le32 *)(header + 4)); |
1435 | fc = swheader & SDPCM_FCMASK_MASK; | |
4754fcee FL |
1436 | if (bus->flowcontrol != fc) { |
1437 | if (~bus->flowcontrol & fc) | |
1438 | bus->sdcnt.fc_xoff++; | |
1439 | if (bus->flowcontrol & ~fc) | |
1440 | bus->sdcnt.fc_xon++; | |
1441 | bus->sdcnt.fc_rcvd++; | |
1442 | bus->flowcontrol = fc; | |
1443 | } | |
6bc52319 | 1444 | tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; |
4754fcee | 1445 | if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { |
5e8149f5 | 1446 | brcmf_err("seq %d: max tx seq number error\n", rx_seq); |
4754fcee FL |
1447 | tx_seq_max = bus->tx_seq + 2; |
1448 | } | |
1449 | bus->tx_max = tx_seq_max; | |
1450 | ||
10510589 | 1451 | return 0; |
4754fcee FL |
1452 | } |
1453 | ||
6bc52319 FL |
1454 | static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) |
1455 | { | |
1456 | *(__le16 *)header = cpu_to_le16(frm_length); | |
1457 | *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); | |
1458 | } | |
1459 | ||
1460 | static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, | |
1461 | struct brcmf_sdio_hdrinfo *hd_info) | |
1462 | { | |
8da9d2c8 FL |
1463 | u32 hdrval; |
1464 | u8 hdr_offset; | |
6bc52319 FL |
1465 | |
1466 | brcmf_sdio_update_hwhdr(header, hd_info->len); | |
8da9d2c8 FL |
1467 | hdr_offset = SDPCM_HWHDR_LEN; |
1468 | ||
1469 | if (bus->txglom) { | |
1470 | hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); | |
1471 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1472 | hdrval = (u16)hd_info->tail_pad << 16; | |
1473 | *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); | |
1474 | hdr_offset += SDPCM_HWEXT_LEN; | |
1475 | } | |
6bc52319 | 1476 | |
8da9d2c8 FL |
1477 | hdrval = hd_info->seq_num; |
1478 | hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & | |
1479 | SDPCM_CHANNEL_MASK; | |
1480 | hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & | |
1481 | SDPCM_DOFFSET_MASK; | |
1482 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1483 | *(((__le32 *)(header + hdr_offset)) + 1) = 0; | |
1484 | trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); | |
6bc52319 FL |
1485 | } |
1486 | ||
82d7f3c1 | 1487 | static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) |
5b435de0 AS |
1488 | { |
1489 | u16 dlen, totlen; | |
1490 | u8 *dptr, num = 0; | |
9d7d6f95 | 1491 | u16 sublen; |
0b45bf74 | 1492 | struct sk_buff *pfirst, *pnext; |
5b435de0 AS |
1493 | |
1494 | int errcode; | |
9d7d6f95 | 1495 | u8 doff, sfdoff; |
5b435de0 | 1496 | |
6bc52319 | 1497 | struct brcmf_sdio_hdrinfo rd_new; |
5b435de0 AS |
1498 | |
1499 | /* If packets, issue read(s) and send up packet chain */ | |
1500 | /* Return sequence numbers consumed? */ | |
1501 | ||
c3203374 | 1502 | brcmf_dbg(SDIO, "start: glomd %p glom %p\n", |
b83db862 | 1503 | bus->glomd, skb_peek(&bus->glom)); |
5b435de0 AS |
1504 | |
1505 | /* If there's a descriptor, generate the packet chain */ | |
1506 | if (bus->glomd) { | |
0b45bf74 | 1507 | pfirst = pnext = NULL; |
5b435de0 AS |
1508 | dlen = (u16) (bus->glomd->len); |
1509 | dptr = bus->glomd->data; | |
1510 | if (!dlen || (dlen & 1)) { | |
5e8149f5 | 1511 | brcmf_err("bad glomd len(%d), ignore descriptor\n", |
5b435de0 AS |
1512 | dlen); |
1513 | dlen = 0; | |
1514 | } | |
1515 | ||
1516 | for (totlen = num = 0; dlen; num++) { | |
1517 | /* Get (and move past) next length */ | |
1518 | sublen = get_unaligned_le16(dptr); | |
1519 | dlen -= sizeof(u16); | |
1520 | dptr += sizeof(u16); | |
1521 | if ((sublen < SDPCM_HDRLEN) || | |
1522 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
5e8149f5 | 1523 | brcmf_err("descriptor len %d bad: %d\n", |
5b435de0 AS |
1524 | num, sublen); |
1525 | pnext = NULL; | |
1526 | break; | |
1527 | } | |
e217d1c8 | 1528 | if (sublen % bus->sgentry_align) { |
5e8149f5 | 1529 | brcmf_err("sublen %d not multiple of %d\n", |
e217d1c8 | 1530 | sublen, bus->sgentry_align); |
5b435de0 AS |
1531 | } |
1532 | totlen += sublen; | |
1533 | ||
1534 | /* For last frame, adjust read len so total | |
1535 | is a block multiple */ | |
1536 | if (!dlen) { | |
1537 | sublen += | |
1538 | (roundup(totlen, bus->blocksize) - totlen); | |
1539 | totlen = roundup(totlen, bus->blocksize); | |
1540 | } | |
1541 | ||
1542 | /* Allocate/chain packet for next subframe */ | |
e217d1c8 | 1543 | pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); |
5b435de0 | 1544 | if (pnext == NULL) { |
5e8149f5 | 1545 | brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", |
5b435de0 AS |
1546 | num, sublen); |
1547 | break; | |
1548 | } | |
b83db862 | 1549 | skb_queue_tail(&bus->glom, pnext); |
5b435de0 AS |
1550 | |
1551 | /* Adhere to start alignment requirements */ | |
e217d1c8 | 1552 | pkt_align(pnext, sublen, bus->sgentry_align); |
5b435de0 AS |
1553 | } |
1554 | ||
1555 | /* If all allocations succeeded, save packet chain | |
1556 | in bus structure */ | |
1557 | if (pnext) { | |
1558 | brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", | |
1559 | totlen, num); | |
4754fcee FL |
1560 | if (BRCMF_GLOM_ON() && bus->cur_read.len && |
1561 | totlen != bus->cur_read.len) { | |
5b435de0 | 1562 | brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", |
4754fcee | 1563 | bus->cur_read.len, totlen, rxseq); |
5b435de0 | 1564 | } |
5b435de0 AS |
1565 | pfirst = pnext = NULL; |
1566 | } else { | |
82d7f3c1 | 1567 | brcmf_sdio_free_glom(bus); |
5b435de0 AS |
1568 | num = 0; |
1569 | } | |
1570 | ||
1571 | /* Done with descriptor packet */ | |
1572 | brcmu_pkt_buf_free_skb(bus->glomd); | |
1573 | bus->glomd = NULL; | |
4754fcee | 1574 | bus->cur_read.len = 0; |
5b435de0 AS |
1575 | } |
1576 | ||
1577 | /* Ok -- either we just generated a packet chain, | |
1578 | or had one from before */ | |
b83db862 | 1579 | if (!skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1580 | if (BRCMF_GLOM_ON()) { |
1581 | brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); | |
b83db862 | 1582 | skb_queue_walk(&bus->glom, pnext) { |
5b435de0 AS |
1583 | brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", |
1584 | pnext, (u8 *) (pnext->data), | |
1585 | pnext->len, pnext->len); | |
1586 | } | |
1587 | } | |
1588 | ||
b83db862 | 1589 | pfirst = skb_peek(&bus->glom); |
82d7f3c1 | 1590 | dlen = (u16) brcmf_sdio_glom_len(bus); |
5b435de0 AS |
1591 | |
1592 | /* Do an SDIO read for the superframe. Configurable iovar to | |
1593 | * read directly into the chained packet, or allocate a large | |
1594 | * packet and and copy into the chain. | |
1595 | */ | |
38b0b0dd | 1596 | sdio_claim_host(bus->sdiodev->func[1]); |
a39be27b | 1597 | errcode = brcmf_sdiod_recv_chain(bus->sdiodev, |
a39be27b | 1598 | &bus->glom, dlen); |
38b0b0dd | 1599 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 1600 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1601 | |
1602 | /* On failure, kill the superframe, allow a couple retries */ | |
1603 | if (errcode < 0) { | |
5e8149f5 | 1604 | brcmf_err("glom read of %d bytes failed: %d\n", |
5b435de0 | 1605 | dlen, errcode); |
5b435de0 | 1606 | |
38b0b0dd | 1607 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 1608 | if (bus->glomerr++ < 3) { |
82d7f3c1 | 1609 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 AS |
1610 | } else { |
1611 | bus->glomerr = 0; | |
82d7f3c1 | 1612 | brcmf_sdio_rxfail(bus, true, false); |
80969836 | 1613 | bus->sdcnt.rxglomfail++; |
82d7f3c1 | 1614 | brcmf_sdio_free_glom(bus); |
5b435de0 | 1615 | } |
38b0b0dd | 1616 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1617 | return 0; |
1618 | } | |
1e023829 JP |
1619 | |
1620 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), | |
1621 | pfirst->data, min_t(int, pfirst->len, 48), | |
1622 | "SUPERFRAME:\n"); | |
5b435de0 | 1623 | |
9d7d6f95 FL |
1624 | rd_new.seq_num = rxseq; |
1625 | rd_new.len = dlen; | |
38b0b0dd | 1626 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1627 | errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, |
1628 | BRCMF_SDIO_FT_SUPER); | |
38b0b0dd | 1629 | sdio_release_host(bus->sdiodev->func[1]); |
9d7d6f95 | 1630 | bus->cur_read.len = rd_new.len_nxtfrm << 4; |
5b435de0 AS |
1631 | |
1632 | /* Remove superframe header, remember offset */ | |
9d7d6f95 FL |
1633 | skb_pull(pfirst, rd_new.dat_offset); |
1634 | sfdoff = rd_new.dat_offset; | |
0b45bf74 | 1635 | num = 0; |
5b435de0 AS |
1636 | |
1637 | /* Validate all the subframe headers */ | |
0b45bf74 AS |
1638 | skb_queue_walk(&bus->glom, pnext) { |
1639 | /* leave when invalid subframe is found */ | |
1640 | if (errcode) | |
1641 | break; | |
1642 | ||
9d7d6f95 FL |
1643 | rd_new.len = pnext->len; |
1644 | rd_new.seq_num = rxseq++; | |
38b0b0dd | 1645 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1646 | errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, |
1647 | BRCMF_SDIO_FT_SUB); | |
38b0b0dd | 1648 | sdio_release_host(bus->sdiodev->func[1]); |
1e023829 | 1649 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
9d7d6f95 | 1650 | pnext->data, 32, "subframe:\n"); |
5b435de0 | 1651 | |
0b45bf74 | 1652 | num++; |
5b435de0 AS |
1653 | } |
1654 | ||
1655 | if (errcode) { | |
1656 | /* Terminate frame on error, request | |
1657 | a couple retries */ | |
38b0b0dd | 1658 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1659 | if (bus->glomerr++ < 3) { |
1660 | /* Restore superframe header space */ | |
1661 | skb_push(pfirst, sfdoff); | |
82d7f3c1 | 1662 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 AS |
1663 | } else { |
1664 | bus->glomerr = 0; | |
82d7f3c1 | 1665 | brcmf_sdio_rxfail(bus, true, false); |
80969836 | 1666 | bus->sdcnt.rxglomfail++; |
82d7f3c1 | 1667 | brcmf_sdio_free_glom(bus); |
5b435de0 | 1668 | } |
38b0b0dd | 1669 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee | 1670 | bus->cur_read.len = 0; |
5b435de0 AS |
1671 | return 0; |
1672 | } | |
1673 | ||
1674 | /* Basic SD framing looks ok - process each packet (header) */ | |
5b435de0 | 1675 | |
0b45bf74 | 1676 | skb_queue_walk_safe(&bus->glom, pfirst, pnext) { |
5b435de0 AS |
1677 | dptr = (u8 *) (pfirst->data); |
1678 | sublen = get_unaligned_le16(dptr); | |
6bc52319 | 1679 | doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); |
5b435de0 | 1680 | |
1e023829 | 1681 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
9d7d6f95 FL |
1682 | dptr, pfirst->len, |
1683 | "Rx Subframe Data:\n"); | |
5b435de0 AS |
1684 | |
1685 | __skb_trim(pfirst, sublen); | |
1686 | skb_pull(pfirst, doff); | |
1687 | ||
1688 | if (pfirst->len == 0) { | |
0b45bf74 | 1689 | skb_unlink(pfirst, &bus->glom); |
5b435de0 | 1690 | brcmu_pkt_buf_free_skb(pfirst); |
5b435de0 | 1691 | continue; |
5b435de0 AS |
1692 | } |
1693 | ||
1e023829 JP |
1694 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
1695 | pfirst->data, | |
1696 | min_t(int, pfirst->len, 32), | |
1697 | "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", | |
1698 | bus->glom.qlen, pfirst, pfirst->data, | |
1699 | pfirst->len, pfirst->next, | |
1700 | pfirst->prev); | |
05f3820b AS |
1701 | skb_unlink(pfirst, &bus->glom); |
1702 | brcmf_rx_frame(bus->sdiodev->dev, pfirst); | |
1703 | bus->sdcnt.rxglompkts++; | |
5b435de0 | 1704 | } |
5b435de0 | 1705 | |
80969836 | 1706 | bus->sdcnt.rxglomframes++; |
5b435de0 AS |
1707 | } |
1708 | return num; | |
1709 | } | |
1710 | ||
82d7f3c1 AS |
1711 | static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, |
1712 | bool *pending) | |
5b435de0 AS |
1713 | { |
1714 | DECLARE_WAITQUEUE(wait, current); | |
1715 | int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT); | |
1716 | ||
1717 | /* Wait until control frame is available */ | |
1718 | add_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1719 | set_current_state(TASK_INTERRUPTIBLE); | |
1720 | ||
1721 | while (!(*condition) && (!signal_pending(current) && timeout)) | |
1722 | timeout = schedule_timeout(timeout); | |
1723 | ||
1724 | if (signal_pending(current)) | |
1725 | *pending = true; | |
1726 | ||
1727 | set_current_state(TASK_RUNNING); | |
1728 | remove_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1729 | ||
1730 | return timeout; | |
1731 | } | |
1732 | ||
82d7f3c1 | 1733 | static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) |
5b435de0 AS |
1734 | { |
1735 | if (waitqueue_active(&bus->dcmd_resp_wait)) | |
1736 | wake_up_interruptible(&bus->dcmd_resp_wait); | |
1737 | ||
1738 | return 0; | |
1739 | } | |
1740 | static void | |
82d7f3c1 | 1741 | brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) |
5b435de0 AS |
1742 | { |
1743 | uint rdlen, pad; | |
dd43a01c | 1744 | u8 *buf = NULL, *rbuf; |
5b435de0 AS |
1745 | int sdret; |
1746 | ||
1747 | brcmf_dbg(TRACE, "Enter\n"); | |
1748 | ||
dd43a01c FL |
1749 | if (bus->rxblen) |
1750 | buf = vzalloc(bus->rxblen); | |
14f8dc49 | 1751 | if (!buf) |
dd43a01c | 1752 | goto done; |
14f8dc49 | 1753 | |
dd43a01c | 1754 | rbuf = bus->rxbuf; |
9b2d2f2a | 1755 | pad = ((unsigned long)rbuf % bus->head_align); |
5b435de0 | 1756 | if (pad) |
9b2d2f2a | 1757 | rbuf += (bus->head_align - pad); |
5b435de0 AS |
1758 | |
1759 | /* Copy the already-read portion over */ | |
dd43a01c | 1760 | memcpy(buf, hdr, BRCMF_FIRSTREAD); |
5b435de0 AS |
1761 | if (len <= BRCMF_FIRSTREAD) |
1762 | goto gotpkt; | |
1763 | ||
1764 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
1765 | rdlen = len - BRCMF_FIRSTREAD; | |
1766 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
1767 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1768 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
b01a6b3c | 1769 | ((len + pad) < bus->sdiodev->bus_if->maxctl)) |
5b435de0 | 1770 | rdlen += pad; |
9b2d2f2a AS |
1771 | } else if (rdlen % bus->head_align) { |
1772 | rdlen += bus->head_align - (rdlen % bus->head_align); | |
5b435de0 AS |
1773 | } |
1774 | ||
5b435de0 | 1775 | /* Drop if the read is too big or it exceeds our maximum */ |
b01a6b3c | 1776 | if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1777 | brcmf_err("%d-byte control read exceeds %d-byte buffer\n", |
b01a6b3c | 1778 | rdlen, bus->sdiodev->bus_if->maxctl); |
82d7f3c1 | 1779 | brcmf_sdio_rxfail(bus, false, false); |
5b435de0 AS |
1780 | goto done; |
1781 | } | |
1782 | ||
b01a6b3c | 1783 | if ((len - doff) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1784 | brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", |
b01a6b3c | 1785 | len, len - doff, bus->sdiodev->bus_if->maxctl); |
80969836 | 1786 | bus->sdcnt.rx_toolong++; |
82d7f3c1 | 1787 | brcmf_sdio_rxfail(bus, false, false); |
5b435de0 AS |
1788 | goto done; |
1789 | } | |
1790 | ||
dd43a01c | 1791 | /* Read remain of frame body */ |
a7cdd821 | 1792 | sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); |
80969836 | 1793 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1794 | |
1795 | /* Control frame failures need retransmission */ | |
1796 | if (sdret < 0) { | |
5e8149f5 | 1797 | brcmf_err("read %d control bytes failed: %d\n", |
5b435de0 | 1798 | rdlen, sdret); |
80969836 | 1799 | bus->sdcnt.rxc_errors++; |
82d7f3c1 | 1800 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 | 1801 | goto done; |
dd43a01c FL |
1802 | } else |
1803 | memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); | |
5b435de0 AS |
1804 | |
1805 | gotpkt: | |
1806 | ||
1e023829 | 1807 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
dd43a01c | 1808 | buf, len, "RxCtrl:\n"); |
5b435de0 AS |
1809 | |
1810 | /* Point to valid data and indicate its length */ | |
dd43a01c FL |
1811 | spin_lock_bh(&bus->rxctl_lock); |
1812 | if (bus->rxctl) { | |
5e8149f5 | 1813 | brcmf_err("last control frame is being processed.\n"); |
dd43a01c FL |
1814 | spin_unlock_bh(&bus->rxctl_lock); |
1815 | vfree(buf); | |
1816 | goto done; | |
1817 | } | |
1818 | bus->rxctl = buf + doff; | |
1819 | bus->rxctl_orig = buf; | |
5b435de0 | 1820 | bus->rxlen = len - doff; |
dd43a01c | 1821 | spin_unlock_bh(&bus->rxctl_lock); |
5b435de0 AS |
1822 | |
1823 | done: | |
1824 | /* Awake any waiters */ | |
82d7f3c1 | 1825 | brcmf_sdio_dcmd_resp_wake(bus); |
5b435de0 AS |
1826 | } |
1827 | ||
1828 | /* Pad read to blocksize for efficiency */ | |
82d7f3c1 | 1829 | static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) |
5b435de0 AS |
1830 | { |
1831 | if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { | |
1832 | *pad = bus->blocksize - (*rdlen % bus->blocksize); | |
1833 | if (*pad <= bus->roundup && *pad < bus->blocksize && | |
1834 | *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) | |
1835 | *rdlen += *pad; | |
9b2d2f2a AS |
1836 | } else if (*rdlen % bus->head_align) { |
1837 | *rdlen += bus->head_align - (*rdlen % bus->head_align); | |
5b435de0 AS |
1838 | } |
1839 | } | |
1840 | ||
4754fcee | 1841 | static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 | 1842 | { |
5b435de0 AS |
1843 | struct sk_buff *pkt; /* Packet for event or data frames */ |
1844 | u16 pad; /* Number of pad bytes to read */ | |
5b435de0 | 1845 | uint rxleft = 0; /* Remaining number of frames allowed */ |
349e7104 | 1846 | int ret; /* Return code from calls */ |
5b435de0 | 1847 | uint rxcount = 0; /* Total frames read */ |
6bc52319 | 1848 | struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; |
4754fcee | 1849 | u8 head_read = 0; |
5b435de0 AS |
1850 | |
1851 | brcmf_dbg(TRACE, "Enter\n"); | |
1852 | ||
1853 | /* Not finished unless we encounter no more frames indication */ | |
4754fcee | 1854 | bus->rxpending = true; |
5b435de0 | 1855 | |
4754fcee | 1856 | for (rd->seq_num = bus->rx_seq, rxleft = maxframes; |
bb350711 | 1857 | !bus->rxskip && rxleft && brcmf_bus_ready(bus->sdiodev->bus_if); |
4754fcee | 1858 | rd->seq_num++, rxleft--) { |
5b435de0 AS |
1859 | |
1860 | /* Handle glomming separately */ | |
b83db862 | 1861 | if (bus->glomd || !skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1862 | u8 cnt; |
1863 | brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", | |
b83db862 | 1864 | bus->glomd, skb_peek(&bus->glom)); |
82d7f3c1 | 1865 | cnt = brcmf_sdio_rxglom(bus, rd->seq_num); |
5b435de0 | 1866 | brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); |
4754fcee | 1867 | rd->seq_num += cnt - 1; |
5b435de0 AS |
1868 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; |
1869 | continue; | |
1870 | } | |
1871 | ||
4754fcee FL |
1872 | rd->len_left = rd->len; |
1873 | /* read header first for unknow frame length */ | |
38b0b0dd | 1874 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee | 1875 | if (!rd->len) { |
a39be27b | 1876 | ret = brcmf_sdiod_recv_buf(bus->sdiodev, |
a39be27b | 1877 | bus->rxhdr, BRCMF_FIRSTREAD); |
4754fcee | 1878 | bus->sdcnt.f2rxhdrs++; |
349e7104 | 1879 | if (ret < 0) { |
5e8149f5 | 1880 | brcmf_err("RXHEADER FAILED: %d\n", |
349e7104 | 1881 | ret); |
4754fcee | 1882 | bus->sdcnt.rx_hdrfail++; |
82d7f3c1 | 1883 | brcmf_sdio_rxfail(bus, true, true); |
38b0b0dd | 1884 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1885 | continue; |
5b435de0 | 1886 | } |
5b435de0 | 1887 | |
4754fcee | 1888 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), |
1e023829 JP |
1889 | bus->rxhdr, SDPCM_HDRLEN, |
1890 | "RxHdr:\n"); | |
5b435de0 | 1891 | |
6bc52319 FL |
1892 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, |
1893 | BRCMF_SDIO_FT_NORMAL)) { | |
38b0b0dd | 1894 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1895 | if (!bus->rxpending) |
1896 | break; | |
1897 | else | |
1898 | continue; | |
5b435de0 AS |
1899 | } |
1900 | ||
4754fcee | 1901 | if (rd->channel == SDPCM_CONTROL_CHANNEL) { |
82d7f3c1 AS |
1902 | brcmf_sdio_read_control(bus, bus->rxhdr, |
1903 | rd->len, | |
1904 | rd->dat_offset); | |
4754fcee FL |
1905 | /* prepare the descriptor for the next read */ |
1906 | rd->len = rd->len_nxtfrm << 4; | |
1907 | rd->len_nxtfrm = 0; | |
1908 | /* treat all packet as event if we don't know */ | |
1909 | rd->channel = SDPCM_EVENT_CHANNEL; | |
38b0b0dd | 1910 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1911 | continue; |
1912 | } | |
4754fcee FL |
1913 | rd->len_left = rd->len > BRCMF_FIRSTREAD ? |
1914 | rd->len - BRCMF_FIRSTREAD : 0; | |
1915 | head_read = BRCMF_FIRSTREAD; | |
5b435de0 AS |
1916 | } |
1917 | ||
82d7f3c1 | 1918 | brcmf_sdio_pad(bus, &pad, &rd->len_left); |
5b435de0 | 1919 | |
4754fcee | 1920 | pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + |
9b2d2f2a | 1921 | bus->head_align); |
5b435de0 AS |
1922 | if (!pkt) { |
1923 | /* Give up on data, request rtx of events */ | |
5e8149f5 | 1924 | brcmf_err("brcmu_pkt_buf_get_skb failed\n"); |
82d7f3c1 | 1925 | brcmf_sdio_rxfail(bus, false, |
4754fcee | 1926 | RETRYCHAN(rd->channel)); |
38b0b0dd | 1927 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1928 | continue; |
1929 | } | |
4754fcee | 1930 | skb_pull(pkt, head_read); |
9b2d2f2a | 1931 | pkt_align(pkt, rd->len_left, bus->head_align); |
5b435de0 | 1932 | |
a7cdd821 | 1933 | ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); |
80969836 | 1934 | bus->sdcnt.f2rxdata++; |
38b0b0dd | 1935 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1936 | |
349e7104 | 1937 | if (ret < 0) { |
5e8149f5 | 1938 | brcmf_err("read %d bytes from channel %d failed: %d\n", |
349e7104 | 1939 | rd->len, rd->channel, ret); |
5b435de0 | 1940 | brcmu_pkt_buf_free_skb(pkt); |
38b0b0dd | 1941 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 1942 | brcmf_sdio_rxfail(bus, true, |
4754fcee | 1943 | RETRYCHAN(rd->channel)); |
38b0b0dd | 1944 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1945 | continue; |
1946 | } | |
1947 | ||
4754fcee FL |
1948 | if (head_read) { |
1949 | skb_push(pkt, head_read); | |
1950 | memcpy(pkt->data, bus->rxhdr, head_read); | |
1951 | head_read = 0; | |
1952 | } else { | |
1953 | memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); | |
1954 | rd_new.seq_num = rd->seq_num; | |
38b0b0dd | 1955 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1956 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, |
1957 | BRCMF_SDIO_FT_NORMAL)) { | |
4754fcee FL |
1958 | rd->len = 0; |
1959 | brcmu_pkt_buf_free_skb(pkt); | |
1960 | } | |
1961 | bus->sdcnt.rx_readahead_cnt++; | |
1962 | if (rd->len != roundup(rd_new.len, 16)) { | |
5e8149f5 | 1963 | brcmf_err("frame length mismatch:read %d, should be %d\n", |
4754fcee FL |
1964 | rd->len, |
1965 | roundup(rd_new.len, 16) >> 4); | |
1966 | rd->len = 0; | |
82d7f3c1 | 1967 | brcmf_sdio_rxfail(bus, true, true); |
38b0b0dd | 1968 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1969 | brcmu_pkt_buf_free_skb(pkt); |
1970 | continue; | |
1971 | } | |
38b0b0dd | 1972 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1973 | rd->len_nxtfrm = rd_new.len_nxtfrm; |
1974 | rd->channel = rd_new.channel; | |
1975 | rd->dat_offset = rd_new.dat_offset; | |
1976 | ||
1977 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && | |
1978 | BRCMF_DATA_ON()) && | |
1979 | BRCMF_HDRS_ON(), | |
1980 | bus->rxhdr, SDPCM_HDRLEN, | |
1981 | "RxHdr:\n"); | |
1982 | ||
1983 | if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { | |
5e8149f5 | 1984 | brcmf_err("readahead on control packet %d?\n", |
4754fcee FL |
1985 | rd_new.seq_num); |
1986 | /* Force retry w/normal header read */ | |
1987 | rd->len = 0; | |
38b0b0dd | 1988 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 1989 | brcmf_sdio_rxfail(bus, false, true); |
38b0b0dd | 1990 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1991 | brcmu_pkt_buf_free_skb(pkt); |
1992 | continue; | |
1993 | } | |
1994 | } | |
5b435de0 | 1995 | |
1e023829 | 1996 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
4754fcee | 1997 | pkt->data, rd->len, "Rx Data:\n"); |
5b435de0 | 1998 | |
5b435de0 | 1999 | /* Save superframe descriptor and allocate packet frame */ |
4754fcee | 2000 | if (rd->channel == SDPCM_GLOM_CHANNEL) { |
6bc52319 | 2001 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { |
5b435de0 | 2002 | brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", |
4754fcee | 2003 | rd->len); |
1e023829 | 2004 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
4754fcee | 2005 | pkt->data, rd->len, |
1e023829 | 2006 | "Glom Data:\n"); |
4754fcee | 2007 | __skb_trim(pkt, rd->len); |
5b435de0 AS |
2008 | skb_pull(pkt, SDPCM_HDRLEN); |
2009 | bus->glomd = pkt; | |
2010 | } else { | |
5e8149f5 | 2011 | brcmf_err("%s: glom superframe w/o " |
5b435de0 | 2012 | "descriptor!\n", __func__); |
38b0b0dd | 2013 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 2014 | brcmf_sdio_rxfail(bus, false, false); |
38b0b0dd | 2015 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 2016 | } |
4754fcee FL |
2017 | /* prepare the descriptor for the next read */ |
2018 | rd->len = rd->len_nxtfrm << 4; | |
2019 | rd->len_nxtfrm = 0; | |
2020 | /* treat all packet as event if we don't know */ | |
2021 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
2022 | continue; |
2023 | } | |
2024 | ||
2025 | /* Fill in packet len and prio, deliver upward */ | |
4754fcee FL |
2026 | __skb_trim(pkt, rd->len); |
2027 | skb_pull(pkt, rd->dat_offset); | |
2028 | ||
2029 | /* prepare the descriptor for the next read */ | |
2030 | rd->len = rd->len_nxtfrm << 4; | |
2031 | rd->len_nxtfrm = 0; | |
2032 | /* treat all packet as event if we don't know */ | |
2033 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
2034 | |
2035 | if (pkt->len == 0) { | |
2036 | brcmu_pkt_buf_free_skb(pkt); | |
2037 | continue; | |
5b435de0 AS |
2038 | } |
2039 | ||
05f3820b | 2040 | brcmf_rx_frame(bus->sdiodev->dev, pkt); |
5b435de0 | 2041 | } |
4754fcee | 2042 | |
5b435de0 | 2043 | rxcount = maxframes - rxleft; |
5b435de0 AS |
2044 | /* Message if we hit the limit */ |
2045 | if (!rxleft) | |
4754fcee | 2046 | brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); |
5b435de0 | 2047 | else |
5b435de0 AS |
2048 | brcmf_dbg(DATA, "processed %d frames\n", rxcount); |
2049 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
2050 | if (bus->rxskip) | |
4754fcee FL |
2051 | rd->seq_num--; |
2052 | bus->rx_seq = rd->seq_num; | |
5b435de0 AS |
2053 | |
2054 | return rxcount; | |
2055 | } | |
2056 | ||
5b435de0 | 2057 | static void |
82d7f3c1 | 2058 | brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) |
5b435de0 AS |
2059 | { |
2060 | if (waitqueue_active(&bus->ctrl_wait)) | |
2061 | wake_up_interruptible(&bus->ctrl_wait); | |
2062 | return; | |
2063 | } | |
2064 | ||
8da9d2c8 FL |
2065 | static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) |
2066 | { | |
e217d1c8 | 2067 | u16 head_pad; |
8da9d2c8 FL |
2068 | u8 *dat_buf; |
2069 | ||
8da9d2c8 FL |
2070 | dat_buf = (u8 *)(pkt->data); |
2071 | ||
2072 | /* Check head padding */ | |
e217d1c8 | 2073 | head_pad = ((unsigned long)dat_buf % bus->head_align); |
8da9d2c8 FL |
2074 | if (head_pad) { |
2075 | if (skb_headroom(pkt) < head_pad) { | |
2076 | bus->sdiodev->bus_if->tx_realloc++; | |
2077 | head_pad = 0; | |
2078 | if (skb_cow(pkt, head_pad)) | |
2079 | return -ENOMEM; | |
2080 | } | |
2081 | skb_push(pkt, head_pad); | |
2082 | dat_buf = (u8 *)(pkt->data); | |
2083 | memset(dat_buf, 0, head_pad + bus->tx_hdrlen); | |
2084 | } | |
2085 | return head_pad; | |
2086 | } | |
2087 | ||
5491c11c FL |
2088 | /** |
2089 | * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for | |
2090 | * bus layer usage. | |
2091 | */ | |
b05e9254 | 2092 | /* flag marking a dummy skb added for DMA alignment requirement */ |
5491c11c | 2093 | #define ALIGN_SKB_FLAG 0x8000 |
b05e9254 | 2094 | /* bit mask of data length chopped from the previous packet */ |
5491c11c FL |
2095 | #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff |
2096 | ||
8da9d2c8 | 2097 | static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, |
a64304f0 | 2098 | struct sk_buff_head *pktq, |
8da9d2c8 | 2099 | struct sk_buff *pkt, u16 total_len) |
a64304f0 | 2100 | { |
8da9d2c8 | 2101 | struct brcmf_sdio_dev *sdiodev; |
a64304f0 | 2102 | struct sk_buff *pkt_pad; |
e217d1c8 | 2103 | u16 tail_pad, tail_chop, chain_pad; |
a64304f0 | 2104 | unsigned int blksize; |
8da9d2c8 FL |
2105 | bool lastfrm; |
2106 | int ntail, ret; | |
a64304f0 | 2107 | |
8da9d2c8 | 2108 | sdiodev = bus->sdiodev; |
a64304f0 | 2109 | blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize; |
a64304f0 | 2110 | /* sg entry alignment should be a divisor of block size */ |
e217d1c8 | 2111 | WARN_ON(blksize % bus->sgentry_align); |
a64304f0 AS |
2112 | |
2113 | /* Check tail padding */ | |
8da9d2c8 FL |
2114 | lastfrm = skb_queue_is_last(pktq, pkt); |
2115 | tail_pad = 0; | |
e217d1c8 | 2116 | tail_chop = pkt->len % bus->sgentry_align; |
8da9d2c8 | 2117 | if (tail_chop) |
e217d1c8 | 2118 | tail_pad = bus->sgentry_align - tail_chop; |
8da9d2c8 FL |
2119 | chain_pad = (total_len + tail_pad) % blksize; |
2120 | if (lastfrm && chain_pad) | |
2121 | tail_pad += blksize - chain_pad; | |
a64304f0 | 2122 | if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { |
1eb43018 AS |
2123 | pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + |
2124 | bus->head_align); | |
a64304f0 AS |
2125 | if (pkt_pad == NULL) |
2126 | return -ENOMEM; | |
8da9d2c8 | 2127 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); |
2dc3a8e0 DJ |
2128 | if (unlikely(ret < 0)) { |
2129 | kfree_skb(pkt_pad); | |
8da9d2c8 | 2130 | return ret; |
2dc3a8e0 | 2131 | } |
a64304f0 AS |
2132 | memcpy(pkt_pad->data, |
2133 | pkt->data + pkt->len - tail_chop, | |
2134 | tail_chop); | |
5aa9f0ea | 2135 | *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; |
a64304f0 | 2136 | skb_trim(pkt, pkt->len - tail_chop); |
1eb43018 | 2137 | skb_trim(pkt_pad, tail_pad + tail_chop); |
a64304f0 AS |
2138 | __skb_queue_after(pktq, pkt, pkt_pad); |
2139 | } else { | |
2140 | ntail = pkt->data_len + tail_pad - | |
2141 | (pkt->end - pkt->tail); | |
2142 | if (skb_cloned(pkt) || ntail > 0) | |
2143 | if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) | |
2144 | return -ENOMEM; | |
2145 | if (skb_linearize(pkt)) | |
2146 | return -ENOMEM; | |
a64304f0 AS |
2147 | __skb_put(pkt, tail_pad); |
2148 | } | |
2149 | ||
8da9d2c8 | 2150 | return tail_pad; |
a64304f0 AS |
2151 | } |
2152 | ||
b05e9254 FL |
2153 | /** |
2154 | * brcmf_sdio_txpkt_prep - packet preparation for transmit | |
2155 | * @bus: brcmf_sdio structure pointer | |
2156 | * @pktq: packet list pointer | |
2157 | * @chan: virtual channel to transmit the packet | |
2158 | * | |
2159 | * Processes to be applied to the packet | |
2160 | * - Align data buffer pointer | |
2161 | * - Align data buffer length | |
2162 | * - Prepare header | |
2163 | * Return: negative value if there is error | |
2164 | */ | |
2165 | static int | |
2166 | brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, | |
2167 | uint chan) | |
5b435de0 | 2168 | { |
8da9d2c8 | 2169 | u16 head_pad, total_len; |
a64304f0 | 2170 | struct sk_buff *pkt_next; |
8da9d2c8 FL |
2171 | u8 txseq; |
2172 | int ret; | |
6bc52319 | 2173 | struct brcmf_sdio_hdrinfo hd_info = {0}; |
b05e9254 | 2174 | |
8da9d2c8 FL |
2175 | txseq = bus->tx_seq; |
2176 | total_len = 0; | |
2177 | skb_queue_walk(pktq, pkt_next) { | |
2178 | /* alignment packet inserted in previous | |
2179 | * loop cycle can be skipped as it is | |
2180 | * already properly aligned and does not | |
2181 | * need an sdpcm header. | |
2182 | */ | |
5aa9f0ea | 2183 | if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) |
8da9d2c8 | 2184 | continue; |
5b435de0 | 2185 | |
8da9d2c8 FL |
2186 | /* align packet data pointer */ |
2187 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); | |
2188 | if (ret < 0) | |
2189 | return ret; | |
2190 | head_pad = (u16)ret; | |
2191 | if (head_pad) | |
1eb43018 | 2192 | memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); |
5b435de0 | 2193 | |
8da9d2c8 | 2194 | total_len += pkt_next->len; |
5b435de0 | 2195 | |
a64304f0 | 2196 | hd_info.len = pkt_next->len; |
8da9d2c8 FL |
2197 | hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); |
2198 | if (bus->txglom && pktq->qlen > 1) { | |
2199 | ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, | |
2200 | pkt_next, total_len); | |
2201 | if (ret < 0) | |
2202 | return ret; | |
2203 | hd_info.tail_pad = (u16)ret; | |
2204 | total_len += (u16)ret; | |
2205 | } | |
5b435de0 | 2206 | |
8da9d2c8 FL |
2207 | hd_info.channel = chan; |
2208 | hd_info.dat_offset = head_pad + bus->tx_hdrlen; | |
2209 | hd_info.seq_num = txseq++; | |
2210 | ||
2211 | /* Now fill the header */ | |
2212 | brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); | |
2213 | ||
2214 | if (BRCMF_BYTES_ON() && | |
2215 | ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || | |
2216 | (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) | |
47ab4cd8 | 2217 | brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, |
8da9d2c8 FL |
2218 | "Tx Frame:\n"); |
2219 | else if (BRCMF_HDRS_ON()) | |
47ab4cd8 | 2220 | brcmf_dbg_hex_dump(true, pkt_next->data, |
8da9d2c8 FL |
2221 | head_pad + bus->tx_hdrlen, |
2222 | "Tx Header:\n"); | |
2223 | } | |
2224 | /* Hardware length tag of the first packet should be total | |
2225 | * length of the chain (including padding) | |
2226 | */ | |
2227 | if (bus->txglom) | |
2228 | brcmf_sdio_update_hwhdr(pktq->next->data, total_len); | |
b05e9254 FL |
2229 | return 0; |
2230 | } | |
5b435de0 | 2231 | |
b05e9254 FL |
2232 | /** |
2233 | * brcmf_sdio_txpkt_postp - packet post processing for transmit | |
2234 | * @bus: brcmf_sdio structure pointer | |
2235 | * @pktq: packet list pointer | |
2236 | * | |
2237 | * Processes to be applied to the packet | |
2238 | * - Remove head padding | |
2239 | * - Remove tail padding | |
2240 | */ | |
2241 | static void | |
2242 | brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) | |
2243 | { | |
2244 | u8 *hdr; | |
2245 | u32 dat_offset; | |
8da9d2c8 | 2246 | u16 tail_pad; |
5aa9f0ea | 2247 | u16 dummy_flags, chop_len; |
b05e9254 FL |
2248 | struct sk_buff *pkt_next, *tmp, *pkt_prev; |
2249 | ||
2250 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
5aa9f0ea | 2251 | dummy_flags = *(u16 *)(pkt_next->cb); |
5491c11c FL |
2252 | if (dummy_flags & ALIGN_SKB_FLAG) { |
2253 | chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; | |
b05e9254 FL |
2254 | if (chop_len) { |
2255 | pkt_prev = pkt_next->prev; | |
b05e9254 FL |
2256 | skb_put(pkt_prev, chop_len); |
2257 | } | |
2258 | __skb_unlink(pkt_next, pktq); | |
2259 | brcmu_pkt_buf_free_skb(pkt_next); | |
2260 | } else { | |
8da9d2c8 | 2261 | hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; |
b05e9254 FL |
2262 | dat_offset = le32_to_cpu(*(__le32 *)hdr); |
2263 | dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> | |
2264 | SDPCM_DOFFSET_SHIFT; | |
2265 | skb_pull(pkt_next, dat_offset); | |
8da9d2c8 FL |
2266 | if (bus->txglom) { |
2267 | tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); | |
2268 | skb_trim(pkt_next, pkt_next->len - tail_pad); | |
2269 | } | |
b05e9254 | 2270 | } |
5b435de0 | 2271 | } |
b05e9254 | 2272 | } |
5b435de0 | 2273 | |
b05e9254 FL |
2274 | /* Writes a HW/SW header into the packet and sends it. */ |
2275 | /* Assumes: (a) header space already there, (b) caller holds lock */ | |
82d7f3c1 AS |
2276 | static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, |
2277 | uint chan) | |
b05e9254 FL |
2278 | { |
2279 | int ret; | |
8da9d2c8 | 2280 | struct sk_buff *pkt_next, *tmp; |
b05e9254 FL |
2281 | |
2282 | brcmf_dbg(TRACE, "Enter\n"); | |
2283 | ||
8da9d2c8 | 2284 | ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); |
b05e9254 FL |
2285 | if (ret) |
2286 | goto done; | |
5b435de0 | 2287 | |
38b0b0dd | 2288 | sdio_claim_host(bus->sdiodev->func[1]); |
a7cdd821 | 2289 | ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); |
80969836 | 2290 | bus->sdcnt.f2txdata++; |
5b435de0 | 2291 | |
81c7883c HM |
2292 | if (ret < 0) |
2293 | brcmf_sdio_txfail(bus); | |
5b435de0 | 2294 | |
38b0b0dd | 2295 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2296 | |
2297 | done: | |
8da9d2c8 FL |
2298 | brcmf_sdio_txpkt_postp(bus, pktq); |
2299 | if (ret == 0) | |
2300 | bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; | |
2301 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
2302 | __skb_unlink(pkt_next, pktq); | |
2303 | brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0); | |
2304 | } | |
5b435de0 AS |
2305 | return ret; |
2306 | } | |
2307 | ||
82d7f3c1 | 2308 | static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 AS |
2309 | { |
2310 | struct sk_buff *pkt; | |
8da9d2c8 | 2311 | struct sk_buff_head pktq; |
5b435de0 | 2312 | u32 intstatus = 0; |
8da9d2c8 | 2313 | int ret = 0, prec_out, i; |
5b435de0 | 2314 | uint cnt = 0; |
8da9d2c8 | 2315 | u8 tx_prec_map, pkt_num; |
5b435de0 | 2316 | |
5b435de0 AS |
2317 | brcmf_dbg(TRACE, "Enter\n"); |
2318 | ||
2319 | tx_prec_map = ~bus->flowcontrol; | |
2320 | ||
2321 | /* Send frames until the limit or some other event */ | |
8da9d2c8 FL |
2322 | for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { |
2323 | pkt_num = 1; | |
fed7ec44 HM |
2324 | if (down_interruptible(&bus->tx_seq_lock)) |
2325 | return cnt; | |
8da9d2c8 FL |
2326 | if (bus->txglom) |
2327 | pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, | |
af1fa210 | 2328 | bus->sdiodev->txglomsz); |
8da9d2c8 FL |
2329 | pkt_num = min_t(u32, pkt_num, |
2330 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); | |
fed7ec44 HM |
2331 | __skb_queue_head_init(&pktq); |
2332 | spin_lock_bh(&bus->txq_lock); | |
8da9d2c8 FL |
2333 | for (i = 0; i < pkt_num; i++) { |
2334 | pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, | |
2335 | &prec_out); | |
2336 | if (pkt == NULL) | |
2337 | break; | |
2338 | __skb_queue_tail(&pktq, pkt); | |
5b435de0 | 2339 | } |
fed7ec44 HM |
2340 | spin_unlock_bh(&bus->txq_lock); |
2341 | if (i == 0) { | |
2342 | up(&bus->tx_seq_lock); | |
8da9d2c8 | 2343 | break; |
fed7ec44 | 2344 | } |
5b435de0 | 2345 | |
82d7f3c1 | 2346 | ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); |
fed7ec44 HM |
2347 | up(&bus->tx_seq_lock); |
2348 | ||
8da9d2c8 | 2349 | cnt += i; |
5b435de0 AS |
2350 | |
2351 | /* In poll mode, need to check for other events */ | |
b6a8cf2c | 2352 | if (!bus->intr) { |
5b435de0 | 2353 | /* Check device status, signal pending interrupt */ |
38b0b0dd | 2354 | sdio_claim_host(bus->sdiodev->func[1]); |
5c15c23a FL |
2355 | ret = r_sdreg32(bus, &intstatus, |
2356 | offsetof(struct sdpcmd_regs, | |
2357 | intstatus)); | |
38b0b0dd | 2358 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 2359 | bus->sdcnt.f2txdata++; |
5c15c23a | 2360 | if (ret != 0) |
5b435de0 AS |
2361 | break; |
2362 | if (intstatus & bus->hostintmask) | |
1d382273 | 2363 | atomic_set(&bus->ipend, 1); |
5b435de0 AS |
2364 | } |
2365 | } | |
2366 | ||
2367 | /* Deflow-control stack if needed */ | |
05dde977 | 2368 | if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) && |
c8bf3484 | 2369 | bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { |
90d03ff7 HM |
2370 | bus->txoff = false; |
2371 | brcmf_txflowblock(bus->sdiodev->dev, false); | |
c8bf3484 | 2372 | } |
5b435de0 AS |
2373 | |
2374 | return cnt; | |
2375 | } | |
2376 | ||
fed7ec44 HM |
2377 | static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) |
2378 | { | |
2379 | u8 doff; | |
2380 | u16 pad; | |
2381 | uint retries = 0; | |
2382 | struct brcmf_sdio_hdrinfo hd_info = {0}; | |
2383 | int ret; | |
2384 | ||
2385 | brcmf_dbg(TRACE, "Enter\n"); | |
2386 | ||
2387 | /* Back the pointer to make room for bus header */ | |
2388 | frame -= bus->tx_hdrlen; | |
2389 | len += bus->tx_hdrlen; | |
2390 | ||
2391 | /* Add alignment padding (optional for ctl frames) */ | |
2392 | doff = ((unsigned long)frame % bus->head_align); | |
2393 | if (doff) { | |
2394 | frame -= doff; | |
2395 | len += doff; | |
2396 | memset(frame + bus->tx_hdrlen, 0, doff); | |
2397 | } | |
2398 | ||
2399 | /* Round send length to next SDIO block */ | |
2400 | pad = 0; | |
2401 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2402 | pad = bus->blocksize - (len % bus->blocksize); | |
2403 | if ((pad > bus->roundup) || (pad >= bus->blocksize)) | |
2404 | pad = 0; | |
2405 | } else if (len % bus->head_align) { | |
2406 | pad = bus->head_align - (len % bus->head_align); | |
2407 | } | |
2408 | len += pad; | |
2409 | ||
2410 | hd_info.len = len - pad; | |
2411 | hd_info.channel = SDPCM_CONTROL_CHANNEL; | |
2412 | hd_info.dat_offset = doff + bus->tx_hdrlen; | |
2413 | hd_info.seq_num = bus->tx_seq; | |
2414 | hd_info.lastfrm = true; | |
2415 | hd_info.tail_pad = pad; | |
2416 | brcmf_sdio_hdpack(bus, frame, &hd_info); | |
2417 | ||
2418 | if (bus->txglom) | |
2419 | brcmf_sdio_update_hwhdr(frame, len); | |
2420 | ||
2421 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), | |
2422 | frame, len, "Tx Frame:\n"); | |
2423 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && | |
2424 | BRCMF_HDRS_ON(), | |
2425 | frame, min_t(u16, len, 16), "TxHdr:\n"); | |
2426 | ||
2427 | do { | |
2428 | ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); | |
2429 | ||
2430 | if (ret < 0) | |
2431 | brcmf_sdio_txfail(bus); | |
2432 | else | |
2433 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; | |
2434 | } while (ret < 0 && retries++ < TXRETRIES); | |
2435 | ||
2436 | return ret; | |
2437 | } | |
2438 | ||
82d7f3c1 | 2439 | static void brcmf_sdio_bus_stop(struct device *dev) |
a9ffda88 FL |
2440 | { |
2441 | u32 local_hostintmask; | |
2442 | u8 saveclk; | |
a9ffda88 FL |
2443 | int err; |
2444 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
0a332e46 | 2445 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
a9ffda88 FL |
2446 | struct brcmf_sdio *bus = sdiodev->bus; |
2447 | ||
2448 | brcmf_dbg(TRACE, "Enter\n"); | |
2449 | ||
2450 | if (bus->watchdog_tsk) { | |
2451 | send_sig(SIGTERM, bus->watchdog_tsk, 1); | |
2452 | kthread_stop(bus->watchdog_tsk); | |
2453 | bus->watchdog_tsk = NULL; | |
2454 | } | |
2455 | ||
bb350711 AS |
2456 | if (bus_if->state == BRCMF_BUS_DOWN) { |
2457 | sdio_claim_host(sdiodev->func[1]); | |
2458 | ||
2459 | /* Enable clock for device interrupts */ | |
2460 | brcmf_sdio_bus_sleep(bus, false, false); | |
2461 | ||
2462 | /* Disable and clear interrupts at the chip level also */ | |
2463 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask)); | |
2464 | local_hostintmask = bus->hostintmask; | |
2465 | bus->hostintmask = 0; | |
2466 | ||
2467 | /* Force backplane clocks to assure F2 interrupt propagates */ | |
2468 | saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
2469 | &err); | |
2470 | if (!err) | |
2471 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
2472 | (saveclk | SBSDIO_FORCE_HT), &err); | |
2473 | if (err) | |
2474 | brcmf_err("Failed to force clock for F2: err %d\n", | |
2475 | err); | |
a9ffda88 | 2476 | |
bb350711 AS |
2477 | /* Turn off the bus (F2), free any pending packets */ |
2478 | brcmf_dbg(INTR, "disable SDIO interrupts\n"); | |
2479 | sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); | |
a9ffda88 | 2480 | |
bb350711 AS |
2481 | /* Clear any pending interrupts now that F2 is disabled */ |
2482 | w_sdreg32(bus, local_hostintmask, | |
2483 | offsetof(struct sdpcmd_regs, intstatus)); | |
a9ffda88 | 2484 | |
bb350711 | 2485 | sdio_release_host(sdiodev->func[1]); |
a9ffda88 | 2486 | } |
a9ffda88 FL |
2487 | /* Clear the data packet queues */ |
2488 | brcmu_pktq_flush(&bus->txq, true, NULL, NULL); | |
2489 | ||
2490 | /* Clear any held glomming stuff */ | |
2491 | if (bus->glomd) | |
2492 | brcmu_pkt_buf_free_skb(bus->glomd); | |
82d7f3c1 | 2493 | brcmf_sdio_free_glom(bus); |
a9ffda88 FL |
2494 | |
2495 | /* Clear rx control and wake any waiters */ | |
dd43a01c | 2496 | spin_lock_bh(&bus->rxctl_lock); |
a9ffda88 | 2497 | bus->rxlen = 0; |
dd43a01c | 2498 | spin_unlock_bh(&bus->rxctl_lock); |
82d7f3c1 | 2499 | brcmf_sdio_dcmd_resp_wake(bus); |
a9ffda88 FL |
2500 | |
2501 | /* Reset some F2 state stuff */ | |
2502 | bus->rxskip = false; | |
2503 | bus->tx_seq = bus->rx_seq = 0; | |
a9ffda88 FL |
2504 | } |
2505 | ||
82d7f3c1 | 2506 | static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) |
ba89bf19 FL |
2507 | { |
2508 | unsigned long flags; | |
2509 | ||
668761ac HM |
2510 | if (bus->sdiodev->oob_irq_requested) { |
2511 | spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags); | |
2512 | if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) { | |
2513 | enable_irq(bus->sdiodev->pdata->oob_irq_nr); | |
2514 | bus->sdiodev->irq_en = true; | |
2515 | } | |
2516 | spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags); | |
ba89bf19 | 2517 | } |
ba89bf19 | 2518 | } |
ba89bf19 | 2519 | |
5cbb9c28 HM |
2520 | static void atomic_orr(int val, atomic_t *v) |
2521 | { | |
2522 | int old_val; | |
2523 | ||
2524 | old_val = atomic_read(v); | |
2525 | while (atomic_cmpxchg(v, old_val, val | old_val) != old_val) | |
2526 | old_val = atomic_read(v); | |
2527 | } | |
2528 | ||
4531603a FL |
2529 | static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) |
2530 | { | |
cb7cf7be | 2531 | struct brcmf_core *buscore; |
4531603a FL |
2532 | u32 addr; |
2533 | unsigned long val; | |
5cbb9c28 | 2534 | int ret; |
4531603a | 2535 | |
cb7cf7be AS |
2536 | buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
2537 | addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus); | |
4531603a | 2538 | |
a39be27b | 2539 | val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret); |
4531603a FL |
2540 | bus->sdcnt.f1regdata++; |
2541 | if (ret != 0) | |
5cbb9c28 | 2542 | return ret; |
4531603a FL |
2543 | |
2544 | val &= bus->hostintmask; | |
2545 | atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); | |
2546 | ||
2547 | /* Clear interrupts */ | |
2548 | if (val) { | |
a39be27b | 2549 | brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret); |
4531603a | 2550 | bus->sdcnt.f1regdata++; |
5cbb9c28 | 2551 | atomic_orr(val, &bus->intstatus); |
4531603a FL |
2552 | } |
2553 | ||
2554 | return ret; | |
2555 | } | |
2556 | ||
82d7f3c1 | 2557 | static void brcmf_sdio_dpc(struct brcmf_sdio *bus) |
5b435de0 | 2558 | { |
4531603a FL |
2559 | u32 newstatus = 0; |
2560 | unsigned long intstatus; | |
5b435de0 | 2561 | uint txlimit = bus->txbound; /* Tx frames to send before resched */ |
b6a8cf2c | 2562 | uint framecnt; /* Temporary counter of tx/rx frames */ |
5cbb9c28 | 2563 | int err = 0; |
5b435de0 AS |
2564 | |
2565 | brcmf_dbg(TRACE, "Enter\n"); | |
2566 | ||
38b0b0dd | 2567 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2568 | |
2569 | /* If waiting for HTAVAIL, check status */ | |
4a3da990 | 2570 | if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { |
5b435de0 AS |
2571 | u8 clkctl, devctl = 0; |
2572 | ||
8ae74654 | 2573 | #ifdef DEBUG |
5b435de0 | 2574 | /* Check for inconsistent device control */ |
a39be27b AS |
2575 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
2576 | SBSDIO_DEVICE_CTL, &err); | |
8ae74654 | 2577 | #endif /* DEBUG */ |
5b435de0 AS |
2578 | |
2579 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
a39be27b AS |
2580 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
2581 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 2582 | |
c3203374 | 2583 | brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", |
5b435de0 AS |
2584 | devctl, clkctl); |
2585 | ||
2586 | if (SBSDIO_HTAV(clkctl)) { | |
a39be27b AS |
2587 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
2588 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 2589 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
2590 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
2591 | devctl, &err); | |
5b435de0 | 2592 | bus->clkstate = CLK_AVAIL; |
5b435de0 AS |
2593 | } |
2594 | } | |
2595 | ||
5b435de0 | 2596 | /* Make sure backplane clock is on */ |
82d7f3c1 | 2597 | brcmf_sdio_bus_sleep(bus, false, true); |
5b435de0 AS |
2598 | |
2599 | /* Pending interrupt indicates new device status */ | |
1d382273 FL |
2600 | if (atomic_read(&bus->ipend) > 0) { |
2601 | atomic_set(&bus->ipend, 0); | |
4531603a | 2602 | err = brcmf_sdio_intr_rstatus(bus); |
5b435de0 AS |
2603 | } |
2604 | ||
4531603a FL |
2605 | /* Start with leftover status bits */ |
2606 | intstatus = atomic_xchg(&bus->intstatus, 0); | |
5b435de0 AS |
2607 | |
2608 | /* Handle flow-control change: read new state in case our ack | |
2609 | * crossed another change interrupt. If change still set, assume | |
2610 | * FC ON for safety, let next loop through do the debounce. | |
2611 | */ | |
2612 | if (intstatus & I_HMB_FC_CHANGE) { | |
2613 | intstatus &= ~I_HMB_FC_CHANGE; | |
5c15c23a FL |
2614 | err = w_sdreg32(bus, I_HMB_FC_CHANGE, |
2615 | offsetof(struct sdpcmd_regs, intstatus)); | |
5b435de0 | 2616 | |
5c15c23a FL |
2617 | err = r_sdreg32(bus, &newstatus, |
2618 | offsetof(struct sdpcmd_regs, intstatus)); | |
80969836 | 2619 | bus->sdcnt.f1regdata += 2; |
4531603a FL |
2620 | atomic_set(&bus->fcstate, |
2621 | !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); | |
5b435de0 AS |
2622 | intstatus |= (newstatus & bus->hostintmask); |
2623 | } | |
2624 | ||
2625 | /* Handle host mailbox indication */ | |
2626 | if (intstatus & I_HMB_HOST_INT) { | |
2627 | intstatus &= ~I_HMB_HOST_INT; | |
82d7f3c1 | 2628 | intstatus |= brcmf_sdio_hostmail(bus); |
5b435de0 AS |
2629 | } |
2630 | ||
38b0b0dd | 2631 | sdio_release_host(bus->sdiodev->func[1]); |
7cdf57d3 | 2632 | |
5b435de0 AS |
2633 | /* Generally don't ask for these, can get CRC errors... */ |
2634 | if (intstatus & I_WR_OOSYNC) { | |
5e8149f5 | 2635 | brcmf_err("Dongle reports WR_OOSYNC\n"); |
5b435de0 AS |
2636 | intstatus &= ~I_WR_OOSYNC; |
2637 | } | |
2638 | ||
2639 | if (intstatus & I_RD_OOSYNC) { | |
5e8149f5 | 2640 | brcmf_err("Dongle reports RD_OOSYNC\n"); |
5b435de0 AS |
2641 | intstatus &= ~I_RD_OOSYNC; |
2642 | } | |
2643 | ||
2644 | if (intstatus & I_SBINT) { | |
5e8149f5 | 2645 | brcmf_err("Dongle reports SBINT\n"); |
5b435de0 AS |
2646 | intstatus &= ~I_SBINT; |
2647 | } | |
2648 | ||
2649 | /* Would be active due to wake-wlan in gSPI */ | |
2650 | if (intstatus & I_CHIPACTIVE) { | |
2651 | brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); | |
2652 | intstatus &= ~I_CHIPACTIVE; | |
2653 | } | |
2654 | ||
2655 | /* Ignore frame indications if rxskip is set */ | |
2656 | if (bus->rxskip) | |
2657 | intstatus &= ~I_HMB_FRAME_IND; | |
2658 | ||
2659 | /* On frame indication, read available frames */ | |
b6a8cf2c HM |
2660 | if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { |
2661 | brcmf_sdio_readframes(bus, bus->rxbound); | |
4754fcee | 2662 | if (!bus->rxpending) |
5b435de0 | 2663 | intstatus &= ~I_HMB_FRAME_IND; |
5b435de0 AS |
2664 | } |
2665 | ||
2666 | /* Keep still-pending events for next scheduling */ | |
5cbb9c28 HM |
2667 | if (intstatus) |
2668 | atomic_orr(intstatus, &bus->intstatus); | |
5b435de0 | 2669 | |
82d7f3c1 | 2670 | brcmf_sdio_clrintr(bus); |
ba89bf19 | 2671 | |
fed7ec44 HM |
2672 | if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && |
2673 | (down_interruptible(&bus->tx_seq_lock) == 0)) { | |
2674 | if (data_ok(bus)) { | |
2675 | sdio_claim_host(bus->sdiodev->func[1]); | |
2676 | err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, | |
2677 | bus->ctrl_frame_len); | |
2678 | sdio_release_host(bus->sdiodev->func[1]); | |
81c7883c | 2679 | |
fed7ec44 HM |
2680 | bus->ctrl_frame_stat = false; |
2681 | brcmf_sdio_wait_event_wakeup(bus); | |
2682 | } | |
2683 | up(&bus->tx_seq_lock); | |
5b435de0 AS |
2684 | } |
2685 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
fed7ec44 HM |
2686 | if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && |
2687 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && | |
2688 | data_ok(bus)) { | |
4754fcee FL |
2689 | framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : |
2690 | txlimit; | |
b6a8cf2c | 2691 | brcmf_sdio_sendfromq(bus, framecnt); |
5b435de0 AS |
2692 | } |
2693 | ||
bb350711 | 2694 | if (!brcmf_bus_ready(bus->sdiodev->bus_if) || (err != 0)) { |
5e8149f5 | 2695 | brcmf_err("failed backplane access over SDIO, halting operation\n"); |
4531603a FL |
2696 | atomic_set(&bus->intstatus, 0); |
2697 | } else if (atomic_read(&bus->intstatus) || | |
2698 | atomic_read(&bus->ipend) > 0 || | |
2699 | (!atomic_read(&bus->fcstate) && | |
2700 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
b6a8cf2c | 2701 | data_ok(bus))) { |
fccfe930 | 2702 | atomic_inc(&bus->dpc_tskcnt); |
5b435de0 | 2703 | } |
5b435de0 AS |
2704 | } |
2705 | ||
82d7f3c1 | 2706 | static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) |
e2432b67 AS |
2707 | { |
2708 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
2709 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
2710 | struct brcmf_sdio *bus = sdiodev->bus; | |
2711 | ||
2712 | return &bus->txq; | |
2713 | } | |
2714 | ||
82d7f3c1 | 2715 | static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) |
5b435de0 AS |
2716 | { |
2717 | int ret = -EBADE; | |
44ff5660 | 2718 | uint prec; |
bf347bb9 | 2719 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2720 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
bf347bb9 | 2721 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 | 2722 | |
44ff5660 | 2723 | brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); |
5b435de0 AS |
2724 | |
2725 | /* Add space for the header */ | |
706478cb | 2726 | skb_push(pkt, bus->tx_hdrlen); |
5b435de0 AS |
2727 | /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ |
2728 | ||
2729 | prec = prio2prec((pkt->priority & PRIOMASK)); | |
2730 | ||
2731 | /* Check for existing queue, current flow-control, | |
2732 | pending event, or pending clock */ | |
2733 | brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); | |
80969836 | 2734 | bus->sdcnt.fcqueued++; |
5b435de0 AS |
2735 | |
2736 | /* Priority based enq */ | |
fed7ec44 | 2737 | spin_lock_bh(&bus->txq_lock); |
5aa9f0ea AS |
2738 | /* reset bus_flags in packet cb */ |
2739 | *(u16 *)(pkt->cb) = 0; | |
23677ce3 | 2740 | if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) { |
706478cb | 2741 | skb_pull(pkt, bus->tx_hdrlen); |
5e8149f5 | 2742 | brcmf_err("out of bus->txq !!!\n"); |
5b435de0 AS |
2743 | ret = -ENOSR; |
2744 | } else { | |
2745 | ret = 0; | |
2746 | } | |
5b435de0 | 2747 | |
c8bf3484 | 2748 | if (pktq_len(&bus->txq) >= TXHI) { |
90d03ff7 HM |
2749 | bus->txoff = true; |
2750 | brcmf_txflowblock(bus->sdiodev->dev, true); | |
c8bf3484 | 2751 | } |
fed7ec44 | 2752 | spin_unlock_bh(&bus->txq_lock); |
5b435de0 | 2753 | |
8ae74654 | 2754 | #ifdef DEBUG |
5b435de0 AS |
2755 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) |
2756 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2757 | #endif | |
f1e68c2e | 2758 | |
fccfe930 AS |
2759 | if (atomic_read(&bus->dpc_tskcnt) == 0) { |
2760 | atomic_inc(&bus->dpc_tskcnt); | |
f1e68c2e | 2761 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
2762 | } |
2763 | ||
2764 | return ret; | |
2765 | } | |
2766 | ||
8ae74654 | 2767 | #ifdef DEBUG |
5b435de0 AS |
2768 | #define CONSOLE_LINE_MAX 192 |
2769 | ||
82d7f3c1 | 2770 | static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) |
5b435de0 AS |
2771 | { |
2772 | struct brcmf_console *c = &bus->console; | |
2773 | u8 line[CONSOLE_LINE_MAX], ch; | |
2774 | u32 n, idx, addr; | |
2775 | int rv; | |
2776 | ||
2777 | /* Don't do anything until FWREADY updates console address */ | |
2778 | if (bus->console_addr == 0) | |
2779 | return 0; | |
2780 | ||
2781 | /* Read console log struct */ | |
2782 | addr = bus->console_addr + offsetof(struct rte_console, log_le); | |
a39be27b AS |
2783 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, |
2784 | sizeof(c->log_le)); | |
5b435de0 AS |
2785 | if (rv < 0) |
2786 | return rv; | |
2787 | ||
2788 | /* Allocate console buffer (one time only) */ | |
2789 | if (c->buf == NULL) { | |
2790 | c->bufsize = le32_to_cpu(c->log_le.buf_size); | |
2791 | c->buf = kmalloc(c->bufsize, GFP_ATOMIC); | |
2792 | if (c->buf == NULL) | |
2793 | return -ENOMEM; | |
2794 | } | |
2795 | ||
2796 | idx = le32_to_cpu(c->log_le.idx); | |
2797 | ||
2798 | /* Protect against corrupt value */ | |
2799 | if (idx > c->bufsize) | |
2800 | return -EBADE; | |
2801 | ||
2802 | /* Skip reading the console buffer if the index pointer | |
2803 | has not moved */ | |
2804 | if (idx == c->last) | |
2805 | return 0; | |
2806 | ||
2807 | /* Read the console buffer */ | |
2808 | addr = le32_to_cpu(c->log_le.buf); | |
a39be27b | 2809 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); |
5b435de0 AS |
2810 | if (rv < 0) |
2811 | return rv; | |
2812 | ||
2813 | while (c->last != idx) { | |
2814 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
2815 | if (c->last == idx) { | |
2816 | /* This would output a partial line. | |
2817 | * Instead, back up | |
2818 | * the buffer pointer and output this | |
2819 | * line next time around. | |
2820 | */ | |
2821 | if (c->last >= n) | |
2822 | c->last -= n; | |
2823 | else | |
2824 | c->last = c->bufsize - n; | |
2825 | goto break2; | |
2826 | } | |
2827 | ch = c->buf[c->last]; | |
2828 | c->last = (c->last + 1) % c->bufsize; | |
2829 | if (ch == '\n') | |
2830 | break; | |
2831 | line[n] = ch; | |
2832 | } | |
2833 | ||
2834 | if (n > 0) { | |
2835 | if (line[n - 1] == '\r') | |
2836 | n--; | |
2837 | line[n] = 0; | |
18aad4f8 | 2838 | pr_debug("CONSOLE: %s\n", line); |
5b435de0 AS |
2839 | } |
2840 | } | |
2841 | break2: | |
2842 | ||
2843 | return 0; | |
2844 | } | |
8ae74654 | 2845 | #endif /* DEBUG */ |
5b435de0 | 2846 | |
fcf094f4 | 2847 | static int |
82d7f3c1 | 2848 | brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 | 2849 | { |
47a1ce78 | 2850 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2851 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
47a1ce78 | 2852 | struct brcmf_sdio *bus = sdiodev->bus; |
fed7ec44 | 2853 | int ret = -1; |
5b435de0 AS |
2854 | |
2855 | brcmf_dbg(TRACE, "Enter\n"); | |
2856 | ||
fed7ec44 HM |
2857 | if (down_interruptible(&bus->tx_seq_lock)) |
2858 | return -EINTR; | |
8da9d2c8 | 2859 | |
5b435de0 AS |
2860 | if (!data_ok(bus)) { |
2861 | brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n", | |
2862 | bus->tx_max, bus->tx_seq); | |
fed7ec44 | 2863 | up(&bus->tx_seq_lock); |
5b435de0 | 2864 | /* Send from dpc */ |
fed7ec44 HM |
2865 | bus->ctrl_frame_buf = msg; |
2866 | bus->ctrl_frame_len = msglen; | |
2867 | bus->ctrl_frame_stat = true; | |
5b435de0 | 2868 | |
fd67dc83 FL |
2869 | wait_event_interruptible_timeout(bus->ctrl_wait, |
2870 | !bus->ctrl_frame_stat, | |
2871 | msecs_to_jiffies(2000)); | |
5b435de0 | 2872 | |
23677ce3 | 2873 | if (!bus->ctrl_frame_stat) { |
c3203374 | 2874 | brcmf_dbg(SDIO, "ctrl_frame_stat == false\n"); |
5b435de0 AS |
2875 | ret = 0; |
2876 | } else { | |
c3203374 | 2877 | brcmf_dbg(SDIO, "ctrl_frame_stat == true\n"); |
fed7ec44 HM |
2878 | bus->ctrl_frame_stat = false; |
2879 | if (down_interruptible(&bus->tx_seq_lock)) | |
2880 | return -EINTR; | |
5b435de0 AS |
2881 | ret = -1; |
2882 | } | |
2883 | } | |
5b435de0 | 2884 | if (ret == -1) { |
fed7ec44 HM |
2885 | sdio_claim_host(bus->sdiodev->func[1]); |
2886 | brcmf_sdio_bus_sleep(bus, false, false); | |
2887 | ret = brcmf_sdio_tx_ctrlframe(bus, msg, msglen); | |
2888 | sdio_release_host(bus->sdiodev->func[1]); | |
2889 | up(&bus->tx_seq_lock); | |
5b435de0 AS |
2890 | } |
2891 | ||
5b435de0 | 2892 | if (ret) |
80969836 | 2893 | bus->sdcnt.tx_ctlerrs++; |
5b435de0 | 2894 | else |
80969836 | 2895 | bus->sdcnt.tx_ctlpkts++; |
5b435de0 AS |
2896 | |
2897 | return ret ? -EIO : 0; | |
2898 | } | |
2899 | ||
80969836 | 2900 | #ifdef DEBUG |
4fc0d016 AS |
2901 | static int brcmf_sdio_dump_console(struct brcmf_sdio *bus, |
2902 | struct sdpcm_shared *sh, char __user *data, | |
2903 | size_t count) | |
2904 | { | |
2905 | u32 addr, console_ptr, console_size, console_index; | |
2906 | char *conbuf = NULL; | |
2907 | __le32 sh_val; | |
2908 | int rv; | |
2909 | loff_t pos = 0; | |
2910 | int nbytes = 0; | |
2911 | ||
2912 | /* obtain console information from device memory */ | |
2913 | addr = sh->console_addr + offsetof(struct rte_console, log_le); | |
a39be27b AS |
2914 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2915 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2916 | if (rv < 0) |
2917 | return rv; | |
2918 | console_ptr = le32_to_cpu(sh_val); | |
2919 | ||
2920 | addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); | |
a39be27b AS |
2921 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2922 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2923 | if (rv < 0) |
2924 | return rv; | |
2925 | console_size = le32_to_cpu(sh_val); | |
2926 | ||
2927 | addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); | |
a39be27b AS |
2928 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2929 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2930 | if (rv < 0) |
2931 | return rv; | |
2932 | console_index = le32_to_cpu(sh_val); | |
2933 | ||
2934 | /* allocate buffer for console data */ | |
2935 | if (console_size <= CONSOLE_BUFFER_MAX) | |
2936 | conbuf = vzalloc(console_size+1); | |
2937 | ||
2938 | if (!conbuf) | |
2939 | return -ENOMEM; | |
2940 | ||
2941 | /* obtain the console data from device */ | |
2942 | conbuf[console_size] = '\0'; | |
a39be27b AS |
2943 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, |
2944 | console_size); | |
4fc0d016 AS |
2945 | if (rv < 0) |
2946 | goto done; | |
2947 | ||
2948 | rv = simple_read_from_buffer(data, count, &pos, | |
2949 | conbuf + console_index, | |
2950 | console_size - console_index); | |
2951 | if (rv < 0) | |
2952 | goto done; | |
2953 | ||
2954 | nbytes = rv; | |
2955 | if (console_index > 0) { | |
2956 | pos = 0; | |
2957 | rv = simple_read_from_buffer(data+nbytes, count, &pos, | |
2958 | conbuf, console_index - 1); | |
2959 | if (rv < 0) | |
2960 | goto done; | |
2961 | rv += nbytes; | |
2962 | } | |
2963 | done: | |
2964 | vfree(conbuf); | |
2965 | return rv; | |
2966 | } | |
2967 | ||
2968 | static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh, | |
2969 | char __user *data, size_t count) | |
2970 | { | |
2971 | int error, res; | |
2972 | char buf[350]; | |
2973 | struct brcmf_trap_info tr; | |
4fc0d016 AS |
2974 | loff_t pos = 0; |
2975 | ||
baa9e609 PH |
2976 | if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { |
2977 | brcmf_dbg(INFO, "no trap in firmware\n"); | |
4fc0d016 | 2978 | return 0; |
baa9e609 | 2979 | } |
4fc0d016 | 2980 | |
a39be27b AS |
2981 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, |
2982 | sizeof(struct brcmf_trap_info)); | |
4fc0d016 AS |
2983 | if (error < 0) |
2984 | return error; | |
2985 | ||
4fc0d016 AS |
2986 | res = scnprintf(buf, sizeof(buf), |
2987 | "dongle trap info: type 0x%x @ epc 0x%08x\n" | |
2988 | " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" | |
2989 | " lr 0x%08x pc 0x%08x offset 0x%x\n" | |
2990 | " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" | |
2991 | " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", | |
2992 | le32_to_cpu(tr.type), le32_to_cpu(tr.epc), | |
2993 | le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), | |
2994 | le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), | |
9bd02c6b | 2995 | le32_to_cpu(tr.pc), sh->trap_addr, |
4fc0d016 AS |
2996 | le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), |
2997 | le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), | |
2998 | le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), | |
2999 | le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); | |
3000 | ||
baa9e609 | 3001 | return simple_read_from_buffer(data, count, &pos, buf, res); |
4fc0d016 AS |
3002 | } |
3003 | ||
3004 | static int brcmf_sdio_assert_info(struct brcmf_sdio *bus, | |
3005 | struct sdpcm_shared *sh, char __user *data, | |
3006 | size_t count) | |
3007 | { | |
3008 | int error = 0; | |
3009 | char buf[200]; | |
3010 | char file[80] = "?"; | |
3011 | char expr[80] = "<???>"; | |
3012 | int res; | |
3013 | loff_t pos = 0; | |
3014 | ||
3015 | if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { | |
3016 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3017 | return 0; | |
3018 | } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { | |
3019 | brcmf_dbg(INFO, "no assert in dongle\n"); | |
3020 | return 0; | |
3021 | } | |
3022 | ||
38b0b0dd | 3023 | sdio_claim_host(bus->sdiodev->func[1]); |
4fc0d016 | 3024 | if (sh->assert_file_addr != 0) { |
a39be27b AS |
3025 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, |
3026 | sh->assert_file_addr, (u8 *)file, 80); | |
4fc0d016 AS |
3027 | if (error < 0) |
3028 | return error; | |
3029 | } | |
3030 | if (sh->assert_exp_addr != 0) { | |
a39be27b AS |
3031 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, |
3032 | sh->assert_exp_addr, (u8 *)expr, 80); | |
4fc0d016 AS |
3033 | if (error < 0) |
3034 | return error; | |
3035 | } | |
38b0b0dd | 3036 | sdio_release_host(bus->sdiodev->func[1]); |
4fc0d016 AS |
3037 | |
3038 | res = scnprintf(buf, sizeof(buf), | |
3039 | "dongle assert: %s:%d: assert(%s)\n", | |
3040 | file, sh->assert_line, expr); | |
3041 | return simple_read_from_buffer(data, count, &pos, buf, res); | |
3042 | } | |
3043 | ||
82d7f3c1 | 3044 | static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) |
4fc0d016 AS |
3045 | { |
3046 | int error; | |
3047 | struct sdpcm_shared sh; | |
3048 | ||
4fc0d016 | 3049 | error = brcmf_sdio_readshared(bus, &sh); |
4fc0d016 AS |
3050 | |
3051 | if (error < 0) | |
3052 | return error; | |
3053 | ||
3054 | if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) | |
3055 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3056 | else if (sh.flags & SDPCM_SHARED_ASSERT) | |
5e8149f5 | 3057 | brcmf_err("assertion in dongle\n"); |
4fc0d016 AS |
3058 | |
3059 | if (sh.flags & SDPCM_SHARED_TRAP) | |
5e8149f5 | 3060 | brcmf_err("firmware trap in dongle\n"); |
4fc0d016 AS |
3061 | |
3062 | return 0; | |
3063 | } | |
3064 | ||
82d7f3c1 AS |
3065 | static int brcmf_sdio_died_dump(struct brcmf_sdio *bus, char __user *data, |
3066 | size_t count, loff_t *ppos) | |
4fc0d016 AS |
3067 | { |
3068 | int error = 0; | |
3069 | struct sdpcm_shared sh; | |
3070 | int nbytes = 0; | |
3071 | loff_t pos = *ppos; | |
3072 | ||
3073 | if (pos != 0) | |
3074 | return 0; | |
3075 | ||
4fc0d016 AS |
3076 | error = brcmf_sdio_readshared(bus, &sh); |
3077 | if (error < 0) | |
3078 | goto done; | |
3079 | ||
3080 | error = brcmf_sdio_assert_info(bus, &sh, data, count); | |
3081 | if (error < 0) | |
3082 | goto done; | |
4fc0d016 | 3083 | nbytes = error; |
baa9e609 PH |
3084 | |
3085 | error = brcmf_sdio_trap_info(bus, &sh, data+nbytes, count); | |
4fc0d016 AS |
3086 | if (error < 0) |
3087 | goto done; | |
baa9e609 PH |
3088 | nbytes += error; |
3089 | ||
3090 | error = brcmf_sdio_dump_console(bus, &sh, data+nbytes, count); | |
3091 | if (error < 0) | |
3092 | goto done; | |
3093 | nbytes += error; | |
4fc0d016 | 3094 | |
baa9e609 PH |
3095 | error = nbytes; |
3096 | *ppos += nbytes; | |
4fc0d016 | 3097 | done: |
4fc0d016 AS |
3098 | return error; |
3099 | } | |
3100 | ||
3101 | static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data, | |
3102 | size_t count, loff_t *ppos) | |
3103 | { | |
3104 | struct brcmf_sdio *bus = f->private_data; | |
3105 | int res; | |
3106 | ||
82d7f3c1 | 3107 | res = brcmf_sdio_died_dump(bus, data, count, ppos); |
4fc0d016 AS |
3108 | if (res > 0) |
3109 | *ppos += res; | |
3110 | return (ssize_t)res; | |
3111 | } | |
3112 | ||
3113 | static const struct file_operations brcmf_sdio_forensic_ops = { | |
3114 | .owner = THIS_MODULE, | |
3115 | .open = simple_open, | |
3116 | .read = brcmf_sdio_forensic_read | |
3117 | }; | |
3118 | ||
80969836 AS |
3119 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3120 | { | |
3121 | struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; | |
4fc0d016 | 3122 | struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); |
80969836 | 3123 | |
4fc0d016 AS |
3124 | if (IS_ERR_OR_NULL(dentry)) |
3125 | return; | |
3126 | ||
3127 | debugfs_create_file("forensics", S_IRUGO, dentry, bus, | |
3128 | &brcmf_sdio_forensic_ops); | |
80969836 | 3129 | brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt); |
0801e6c5 DK |
3130 | debugfs_create_u32("console_interval", 0644, dentry, |
3131 | &bus->console_interval); | |
80969836 AS |
3132 | } |
3133 | #else | |
82d7f3c1 | 3134 | static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) |
4fc0d016 AS |
3135 | { |
3136 | return 0; | |
3137 | } | |
3138 | ||
80969836 AS |
3139 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3140 | { | |
3141 | } | |
3142 | #endif /* DEBUG */ | |
3143 | ||
fcf094f4 | 3144 | static int |
82d7f3c1 | 3145 | brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
3146 | { |
3147 | int timeleft; | |
3148 | uint rxlen = 0; | |
3149 | bool pending; | |
dd43a01c | 3150 | u8 *buf; |
532cdd3b | 3151 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3152 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
532cdd3b | 3153 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
3154 | |
3155 | brcmf_dbg(TRACE, "Enter\n"); | |
3156 | ||
3157 | /* Wait until control frame is available */ | |
82d7f3c1 | 3158 | timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); |
5b435de0 | 3159 | |
dd43a01c | 3160 | spin_lock_bh(&bus->rxctl_lock); |
5b435de0 AS |
3161 | rxlen = bus->rxlen; |
3162 | memcpy(msg, bus->rxctl, min(msglen, rxlen)); | |
dd43a01c FL |
3163 | bus->rxctl = NULL; |
3164 | buf = bus->rxctl_orig; | |
3165 | bus->rxctl_orig = NULL; | |
5b435de0 | 3166 | bus->rxlen = 0; |
dd43a01c FL |
3167 | spin_unlock_bh(&bus->rxctl_lock); |
3168 | vfree(buf); | |
5b435de0 AS |
3169 | |
3170 | if (rxlen) { | |
3171 | brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", | |
3172 | rxlen, msglen); | |
3173 | } else if (timeleft == 0) { | |
5e8149f5 | 3174 | brcmf_err("resumed on timeout\n"); |
82d7f3c1 | 3175 | brcmf_sdio_checkdied(bus); |
23677ce3 | 3176 | } else if (pending) { |
5b435de0 AS |
3177 | brcmf_dbg(CTL, "cancelled\n"); |
3178 | return -ERESTARTSYS; | |
3179 | } else { | |
3180 | brcmf_dbg(CTL, "resumed for unknown reason?\n"); | |
82d7f3c1 | 3181 | brcmf_sdio_checkdied(bus); |
5b435de0 AS |
3182 | } |
3183 | ||
3184 | if (rxlen) | |
80969836 | 3185 | bus->sdcnt.rx_ctlpkts++; |
5b435de0 | 3186 | else |
80969836 | 3187 | bus->sdcnt.rx_ctlerrs++; |
5b435de0 AS |
3188 | |
3189 | return rxlen ? (int)rxlen : -ETIMEDOUT; | |
3190 | } | |
3191 | ||
a74d036f HM |
3192 | #ifdef DEBUG |
3193 | static bool | |
3194 | brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, | |
3195 | u8 *ram_data, uint ram_sz) | |
3196 | { | |
3197 | char *ram_cmp; | |
3198 | int err; | |
3199 | bool ret = true; | |
3200 | int address; | |
3201 | int offset; | |
3202 | int len; | |
3203 | ||
3204 | /* read back and verify */ | |
3205 | brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, | |
3206 | ram_sz); | |
3207 | ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); | |
3208 | /* do not proceed while no memory but */ | |
3209 | if (!ram_cmp) | |
3210 | return true; | |
3211 | ||
3212 | address = ram_addr; | |
3213 | offset = 0; | |
3214 | while (offset < ram_sz) { | |
3215 | len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : | |
3216 | ram_sz - offset; | |
3217 | err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); | |
3218 | if (err) { | |
3219 | brcmf_err("error %d on reading %d membytes at 0x%08x\n", | |
3220 | err, len, address); | |
3221 | ret = false; | |
3222 | break; | |
3223 | } else if (memcmp(ram_cmp, &ram_data[offset], len)) { | |
3224 | brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", | |
3225 | offset, len); | |
3226 | ret = false; | |
3227 | break; | |
3228 | } | |
3229 | offset += len; | |
3230 | address += len; | |
3231 | } | |
3232 | ||
3233 | kfree(ram_cmp); | |
3234 | ||
3235 | return ret; | |
3236 | } | |
3237 | #else /* DEBUG */ | |
3238 | static bool | |
3239 | brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, | |
3240 | u8 *ram_data, uint ram_sz) | |
3241 | { | |
3242 | return true; | |
3243 | } | |
3244 | #endif /* DEBUG */ | |
3245 | ||
3355650c AS |
3246 | static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, |
3247 | const struct firmware *fw) | |
5b435de0 | 3248 | { |
f2c44fe7 | 3249 | int err; |
f2c44fe7 | 3250 | |
a74d036f HM |
3251 | brcmf_dbg(TRACE, "Enter\n"); |
3252 | ||
f9951c13 HM |
3253 | err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, |
3254 | (u8 *)fw->data, fw->size); | |
3255 | if (err) | |
3256 | brcmf_err("error %d on writing %d membytes at 0x%08x\n", | |
3257 | err, (int)fw->size, bus->ci->rambase); | |
3258 | else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, | |
3259 | (u8 *)fw->data, fw->size)) | |
3260 | err = -EIO; | |
5b435de0 | 3261 | |
f2c44fe7 | 3262 | return err; |
5b435de0 AS |
3263 | } |
3264 | ||
3355650c | 3265 | static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, |
bd0e1b1d | 3266 | void *vars, u32 varsz) |
5b435de0 | 3267 | { |
a74d036f HM |
3268 | int address; |
3269 | int err; | |
3270 | ||
3271 | brcmf_dbg(TRACE, "Enter\n"); | |
5b435de0 | 3272 | |
a74d036f HM |
3273 | address = bus->ci->ramsize - varsz + bus->ci->rambase; |
3274 | err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); | |
3275 | if (err) | |
3276 | brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", | |
3277 | err, varsz, address); | |
3278 | else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) | |
3279 | err = -EIO; | |
3280 | ||
a74d036f | 3281 | return err; |
5b435de0 AS |
3282 | } |
3283 | ||
bd0e1b1d AS |
3284 | static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, |
3285 | const struct firmware *fw, | |
3286 | void *nvram, u32 nvlen) | |
5b435de0 | 3287 | { |
82d7f3c1 | 3288 | int bcmerror = -EFAULT; |
3355650c | 3289 | u32 rstvec; |
82d7f3c1 AS |
3290 | |
3291 | sdio_claim_host(bus->sdiodev->func[1]); | |
3292 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
5b435de0 AS |
3293 | |
3294 | /* Keep arm in reset */ | |
cb7cf7be | 3295 | brcmf_chip_enter_download(bus->ci); |
3355650c | 3296 | |
3355650c AS |
3297 | rstvec = get_unaligned_le32(fw->data); |
3298 | brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); | |
3299 | ||
3300 | bcmerror = brcmf_sdio_download_code_file(bus, fw); | |
3301 | release_firmware(fw); | |
3302 | if (bcmerror) { | |
5e8149f5 | 3303 | brcmf_err("dongle image file download failed\n"); |
bd0e1b1d | 3304 | brcmf_fw_nvram_free(nvram); |
5b435de0 AS |
3305 | goto err; |
3306 | } | |
3307 | ||
bd0e1b1d AS |
3308 | bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); |
3309 | brcmf_fw_nvram_free(nvram); | |
3355650c | 3310 | if (bcmerror) { |
5e8149f5 | 3311 | brcmf_err("dongle nvram file download failed\n"); |
3eaa956c FL |
3312 | goto err; |
3313 | } | |
5b435de0 AS |
3314 | |
3315 | /* Take arm out of reset */ | |
cb7cf7be | 3316 | if (!brcmf_chip_exit_download(bus->ci, rstvec)) { |
5e8149f5 | 3317 | brcmf_err("error getting out of ARM core reset\n"); |
5b435de0 AS |
3318 | goto err; |
3319 | } | |
3320 | ||
3355650c | 3321 | /* Allow HT Clock now that the ARM is running. */ |
bb350711 | 3322 | brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_LOAD); |
5b435de0 AS |
3323 | bcmerror = 0; |
3324 | ||
3325 | err: | |
82d7f3c1 AS |
3326 | brcmf_sdio_clkctl(bus, CLK_SDONLY, false); |
3327 | sdio_release_host(bus->sdiodev->func[1]); | |
5b435de0 AS |
3328 | return bcmerror; |
3329 | } | |
3330 | ||
82d7f3c1 | 3331 | static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) |
4a3da990 PH |
3332 | { |
3333 | int err = 0; | |
3334 | u8 val; | |
3335 | ||
3336 | brcmf_dbg(TRACE, "Enter\n"); | |
3337 | ||
a39be27b | 3338 | val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); |
4a3da990 PH |
3339 | if (err) { |
3340 | brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3341 | return; | |
3342 | } | |
3343 | ||
3344 | val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; | |
a39be27b | 3345 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); |
4a3da990 PH |
3346 | if (err) { |
3347 | brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3348 | return; | |
3349 | } | |
3350 | ||
3351 | /* Add CMD14 Support */ | |
a39be27b AS |
3352 | brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, |
3353 | (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | | |
3354 | SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), | |
3355 | &err); | |
4a3da990 PH |
3356 | if (err) { |
3357 | brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); | |
3358 | return; | |
3359 | } | |
3360 | ||
a39be27b AS |
3361 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3362 | SBSDIO_FORCE_HT, &err); | |
4a3da990 PH |
3363 | if (err) { |
3364 | brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); | |
3365 | return; | |
3366 | } | |
3367 | ||
3368 | /* set flag */ | |
3369 | bus->sr_enabled = true; | |
3370 | brcmf_dbg(INFO, "SR enabled\n"); | |
3371 | } | |
3372 | ||
3373 | /* enable KSO bit */ | |
82d7f3c1 | 3374 | static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) |
4a3da990 PH |
3375 | { |
3376 | u8 val; | |
3377 | int err = 0; | |
3378 | ||
3379 | brcmf_dbg(TRACE, "Enter\n"); | |
3380 | ||
3381 | /* KSO bit added in SDIO core rev 12 */ | |
cb7cf7be | 3382 | if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) |
4a3da990 PH |
3383 | return 0; |
3384 | ||
a39be27b | 3385 | val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); |
4a3da990 PH |
3386 | if (err) { |
3387 | brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); | |
3388 | return err; | |
3389 | } | |
3390 | ||
3391 | if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { | |
3392 | val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << | |
3393 | SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
a39be27b AS |
3394 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
3395 | val, &err); | |
4a3da990 PH |
3396 | if (err) { |
3397 | brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); | |
3398 | return err; | |
3399 | } | |
3400 | } | |
3401 | ||
3402 | return 0; | |
3403 | } | |
3404 | ||
3405 | ||
82d7f3c1 | 3406 | static int brcmf_sdio_bus_preinit(struct device *dev) |
cf458287 AS |
3407 | { |
3408 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3409 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3410 | struct brcmf_sdio *bus = sdiodev->bus; | |
8da9d2c8 | 3411 | uint pad_size; |
cf458287 | 3412 | u32 value; |
cf458287 AS |
3413 | int err; |
3414 | ||
8da9d2c8 FL |
3415 | /* the commands below use the terms tx and rx from |
3416 | * a device perspective, ie. bus:txglom affects the | |
3417 | * bus transfers from device to host. | |
3418 | */ | |
cb7cf7be | 3419 | if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) { |
cf458287 AS |
3420 | /* for sdio core rev < 12, disable txgloming */ |
3421 | value = 0; | |
3422 | err = brcmf_iovar_data_set(dev, "bus:txglom", &value, | |
3423 | sizeof(u32)); | |
3424 | } else { | |
3425 | /* otherwise, set txglomalign */ | |
3426 | value = 4; | |
3427 | if (sdiodev->pdata) | |
3428 | value = sdiodev->pdata->sd_sgentry_align; | |
3429 | /* SDIO ADMA requires at least 32 bit alignment */ | |
3430 | value = max_t(u32, value, 4); | |
3431 | err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, | |
3432 | sizeof(u32)); | |
3433 | } | |
8da9d2c8 FL |
3434 | |
3435 | if (err < 0) | |
3436 | goto done; | |
3437 | ||
3438 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
3439 | if (sdiodev->sg_support) { | |
3440 | bus->txglom = false; | |
3441 | value = 1; | |
3442 | pad_size = bus->sdiodev->func[2]->cur_blksize << 1; | |
8da9d2c8 FL |
3443 | err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", |
3444 | &value, sizeof(u32)); | |
3445 | if (err < 0) { | |
3446 | /* bus:rxglom is allowed to fail */ | |
3447 | err = 0; | |
3448 | } else { | |
3449 | bus->txglom = true; | |
3450 | bus->tx_hdrlen += SDPCM_HWEXT_LEN; | |
3451 | } | |
3452 | } | |
3453 | brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); | |
3454 | ||
3455 | done: | |
cf458287 AS |
3456 | return err; |
3457 | } | |
3458 | ||
82d7f3c1 | 3459 | void brcmf_sdio_isr(struct brcmf_sdio *bus) |
5b435de0 | 3460 | { |
5b435de0 AS |
3461 | brcmf_dbg(TRACE, "Enter\n"); |
3462 | ||
3463 | if (!bus) { | |
5e8149f5 | 3464 | brcmf_err("bus is null pointer, exiting\n"); |
5b435de0 AS |
3465 | return; |
3466 | } | |
3467 | ||
bb350711 | 3468 | if (!brcmf_bus_ready(bus->sdiodev->bus_if)) { |
5e8149f5 | 3469 | brcmf_err("bus is down. we have nothing to do\n"); |
5b435de0 AS |
3470 | return; |
3471 | } | |
3472 | /* Count the interrupt call */ | |
80969836 | 3473 | bus->sdcnt.intrcount++; |
4531603a FL |
3474 | if (in_interrupt()) |
3475 | atomic_set(&bus->ipend, 1); | |
3476 | else | |
3477 | if (brcmf_sdio_intr_rstatus(bus)) { | |
5e8149f5 | 3478 | brcmf_err("failed backplane access\n"); |
4531603a | 3479 | } |
5b435de0 | 3480 | |
5b435de0 AS |
3481 | /* Disable additional interrupts (is this needed now)? */ |
3482 | if (!bus->intr) | |
5e8149f5 | 3483 | brcmf_err("isr w/o interrupt configured!\n"); |
5b435de0 | 3484 | |
fccfe930 | 3485 | atomic_inc(&bus->dpc_tskcnt); |
f1e68c2e | 3486 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3487 | } |
3488 | ||
82d7f3c1 | 3489 | static bool brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) |
5b435de0 | 3490 | { |
8ae74654 | 3491 | #ifdef DEBUG |
cad2b26b | 3492 | struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev); |
8ae74654 | 3493 | #endif /* DEBUG */ |
5b435de0 AS |
3494 | |
3495 | brcmf_dbg(TIMER, "Enter\n"); | |
3496 | ||
5b435de0 | 3497 | /* Poll period: check device if appropriate. */ |
4a3da990 PH |
3498 | if (!bus->sr_enabled && |
3499 | bus->poll && (++bus->polltick >= bus->pollrate)) { | |
5b435de0 AS |
3500 | u32 intstatus = 0; |
3501 | ||
3502 | /* Reset poll tick */ | |
3503 | bus->polltick = 0; | |
3504 | ||
3505 | /* Check device if no interrupts */ | |
80969836 AS |
3506 | if (!bus->intr || |
3507 | (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { | |
5b435de0 | 3508 | |
fccfe930 | 3509 | if (atomic_read(&bus->dpc_tskcnt) == 0) { |
5b435de0 | 3510 | u8 devpend; |
fccfe930 | 3511 | |
38b0b0dd | 3512 | sdio_claim_host(bus->sdiodev->func[1]); |
a39be27b AS |
3513 | devpend = brcmf_sdiod_regrb(bus->sdiodev, |
3514 | SDIO_CCCR_INTx, | |
3515 | NULL); | |
38b0b0dd | 3516 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3517 | intstatus = |
3518 | devpend & (INTR_STATUS_FUNC1 | | |
3519 | INTR_STATUS_FUNC2); | |
3520 | } | |
3521 | ||
3522 | /* If there is something, make like the ISR and | |
3523 | schedule the DPC */ | |
3524 | if (intstatus) { | |
80969836 | 3525 | bus->sdcnt.pollcnt++; |
1d382273 | 3526 | atomic_set(&bus->ipend, 1); |
5b435de0 | 3527 | |
fccfe930 | 3528 | atomic_inc(&bus->dpc_tskcnt); |
f1e68c2e | 3529 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3530 | } |
3531 | } | |
3532 | ||
3533 | /* Update interrupt tracking */ | |
80969836 | 3534 | bus->sdcnt.lastintrs = bus->sdcnt.intrcount; |
5b435de0 | 3535 | } |
8ae74654 | 3536 | #ifdef DEBUG |
5b435de0 | 3537 | /* Poll for console output periodically */ |
2def5c10 | 3538 | if (bus_if && bus_if->state == BRCMF_BUS_DATA && |
8d169aa0 | 3539 | bus->console_interval != 0) { |
5b435de0 AS |
3540 | bus->console.count += BRCMF_WD_POLL_MS; |
3541 | if (bus->console.count >= bus->console_interval) { | |
3542 | bus->console.count -= bus->console_interval; | |
38b0b0dd | 3543 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 3544 | /* Make sure backplane clock is on */ |
82d7f3c1 AS |
3545 | brcmf_sdio_bus_sleep(bus, false, false); |
3546 | if (brcmf_sdio_readconsole(bus) < 0) | |
5b435de0 AS |
3547 | /* stop on error */ |
3548 | bus->console_interval = 0; | |
38b0b0dd | 3549 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3550 | } |
3551 | } | |
8ae74654 | 3552 | #endif /* DEBUG */ |
5b435de0 AS |
3553 | |
3554 | /* On idle timeout clear activity flag and/or turn off clock */ | |
3555 | if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) { | |
3556 | if (++bus->idlecount >= bus->idletime) { | |
3557 | bus->idlecount = 0; | |
3558 | if (bus->activity) { | |
3559 | bus->activity = false; | |
82d7f3c1 | 3560 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); |
5b435de0 | 3561 | } else { |
4a3da990 | 3562 | brcmf_dbg(SDIO, "idle\n"); |
38b0b0dd | 3563 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 3564 | brcmf_sdio_bus_sleep(bus, true, false); |
38b0b0dd | 3565 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3566 | } |
3567 | } | |
3568 | } | |
3569 | ||
1d382273 | 3570 | return (atomic_read(&bus->ipend) > 0); |
5b435de0 AS |
3571 | } |
3572 | ||
f1e68c2e FL |
3573 | static void brcmf_sdio_dataworker(struct work_struct *work) |
3574 | { | |
3575 | struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, | |
3576 | datawork); | |
f1e68c2e | 3577 | |
fccfe930 | 3578 | while (atomic_read(&bus->dpc_tskcnt)) { |
71abdc00 | 3579 | atomic_set(&bus->dpc_tskcnt, 0); |
82d7f3c1 | 3580 | brcmf_sdio_dpc(bus); |
f1e68c2e | 3581 | } |
f1e68c2e FL |
3582 | } |
3583 | ||
65d80d0b AS |
3584 | static void |
3585 | brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, | |
cb7cf7be | 3586 | struct brcmf_chip *ci, u32 drivestrength) |
65d80d0b AS |
3587 | { |
3588 | const struct sdiod_drive_str *str_tab = NULL; | |
3589 | u32 str_mask; | |
3590 | u32 str_shift; | |
cb7cf7be | 3591 | u32 base; |
65d80d0b AS |
3592 | u32 i; |
3593 | u32 drivestrength_sel = 0; | |
3594 | u32 cc_data_temp; | |
3595 | u32 addr; | |
3596 | ||
cb7cf7be | 3597 | if (!(ci->cc_caps & CC_CAP_PMU)) |
65d80d0b AS |
3598 | return; |
3599 | ||
3600 | switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { | |
3601 | case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12): | |
3602 | str_tab = sdiod_drvstr_tab1_1v8; | |
3603 | str_mask = 0x00003800; | |
3604 | str_shift = 11; | |
3605 | break; | |
3606 | case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17): | |
3607 | str_tab = sdiod_drvstr_tab6_1v8; | |
3608 | str_mask = 0x00001800; | |
3609 | str_shift = 11; | |
3610 | break; | |
3611 | case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17): | |
3612 | /* note: 43143 does not support tristate */ | |
3613 | i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; | |
3614 | if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { | |
3615 | str_tab = sdiod_drvstr_tab2_3v3; | |
3616 | str_mask = 0x00000007; | |
3617 | str_shift = 0; | |
3618 | } else | |
3619 | brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", | |
cb7cf7be | 3620 | ci->name, drivestrength); |
65d80d0b AS |
3621 | break; |
3622 | case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13): | |
3623 | str_tab = sdiod_drive_strength_tab5_1v8; | |
3624 | str_mask = 0x00003800; | |
3625 | str_shift = 11; | |
3626 | break; | |
3627 | default: | |
3628 | brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", | |
cb7cf7be | 3629 | ci->name, ci->chiprev, ci->pmurev); |
65d80d0b AS |
3630 | break; |
3631 | } | |
3632 | ||
3633 | if (str_tab != NULL) { | |
3634 | for (i = 0; str_tab[i].strength != 0; i++) { | |
3635 | if (drivestrength >= str_tab[i].strength) { | |
3636 | drivestrength_sel = str_tab[i].sel; | |
3637 | break; | |
3638 | } | |
3639 | } | |
cb7cf7be | 3640 | base = brcmf_chip_get_chipcommon(ci)->base; |
65d80d0b AS |
3641 | addr = CORE_CC_REG(base, chipcontrol_addr); |
3642 | brcmf_sdiod_regwl(sdiodev, addr, 1, NULL); | |
3643 | cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL); | |
3644 | cc_data_temp &= ~str_mask; | |
3645 | drivestrength_sel <<= str_shift; | |
3646 | cc_data_temp |= drivestrength_sel; | |
3647 | brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL); | |
3648 | ||
3649 | brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", | |
3650 | str_tab[i].strength, drivestrength, cc_data_temp); | |
3651 | } | |
3652 | } | |
3653 | ||
cb7cf7be | 3654 | static int brcmf_sdio_buscoreprep(void *ctx) |
65d80d0b | 3655 | { |
cb7cf7be | 3656 | struct brcmf_sdio_dev *sdiodev = ctx; |
65d80d0b AS |
3657 | int err = 0; |
3658 | u8 clkval, clkset; | |
3659 | ||
3660 | /* Try forcing SDIO core to do ALPAvail request only */ | |
3661 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; | |
3662 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
3663 | if (err) { | |
3664 | brcmf_err("error writing for HT off\n"); | |
3665 | return err; | |
3666 | } | |
3667 | ||
3668 | /* If register supported, wait for ALPAvail and then force ALP */ | |
3669 | /* This may take up to 15 milliseconds */ | |
3670 | clkval = brcmf_sdiod_regrb(sdiodev, | |
3671 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); | |
3672 | ||
3673 | if ((clkval & ~SBSDIO_AVBITS) != clkset) { | |
3674 | brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", | |
3675 | clkset, clkval); | |
3676 | return -EACCES; | |
3677 | } | |
3678 | ||
3679 | SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev, | |
3680 | SBSDIO_FUNC1_CHIPCLKCSR, NULL)), | |
3681 | !SBSDIO_ALPAV(clkval)), | |
3682 | PMU_MAX_TRANSITION_DLY); | |
3683 | if (!SBSDIO_ALPAV(clkval)) { | |
3684 | brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", | |
3685 | clkval); | |
3686 | return -EBUSY; | |
3687 | } | |
3688 | ||
3689 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; | |
3690 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
3691 | udelay(65); | |
3692 | ||
3693 | /* Also, disable the extra SDIO pull-ups */ | |
3694 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); | |
3695 | ||
3696 | return 0; | |
3697 | } | |
3698 | ||
cb7cf7be AS |
3699 | static void brcmf_sdio_buscore_exitdl(void *ctx, struct brcmf_chip *chip, |
3700 | u32 rstvec) | |
3701 | { | |
3702 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3703 | struct brcmf_core *core; | |
3704 | u32 reg_addr; | |
3705 | ||
3706 | /* clear all interrupts */ | |
3707 | core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV); | |
3708 | reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus); | |
3709 | brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL); | |
3710 | ||
3711 | if (rstvec) | |
3712 | /* Write reset vector to address 0 */ | |
3713 | brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, | |
3714 | sizeof(rstvec)); | |
3715 | } | |
3716 | ||
3717 | static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) | |
3718 | { | |
3719 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3720 | u32 val, rev; | |
3721 | ||
3722 | val = brcmf_sdiod_regrl(sdiodev, addr, NULL); | |
3723 | if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 && | |
3724 | addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) { | |
3725 | rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; | |
3726 | if (rev >= 2) { | |
3727 | val &= ~CID_ID_MASK; | |
3728 | val |= BCM4339_CHIP_ID; | |
3729 | } | |
3730 | } | |
3731 | return val; | |
3732 | } | |
3733 | ||
3734 | static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) | |
3735 | { | |
3736 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3737 | ||
3738 | brcmf_sdiod_regwl(sdiodev, addr, val, NULL); | |
3739 | } | |
3740 | ||
3741 | static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { | |
3742 | .prepare = brcmf_sdio_buscoreprep, | |
3743 | .exit_dl = brcmf_sdio_buscore_exitdl, | |
3744 | .read32 = brcmf_sdio_buscore_read32, | |
3745 | .write32 = brcmf_sdio_buscore_write32, | |
3746 | }; | |
3747 | ||
5b435de0 | 3748 | static bool |
82d7f3c1 | 3749 | brcmf_sdio_probe_attach(struct brcmf_sdio *bus) |
5b435de0 AS |
3750 | { |
3751 | u8 clkctl = 0; | |
3752 | int err = 0; | |
3753 | int reg_addr; | |
3754 | u32 reg_val; | |
668761ac | 3755 | u32 drivestrength; |
5b435de0 | 3756 | |
38b0b0dd FL |
3757 | sdio_claim_host(bus->sdiodev->func[1]); |
3758 | ||
18aad4f8 | 3759 | pr_debug("F1 signature read @0x18000000=0x%4x\n", |
a39be27b | 3760 | brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL)); |
5b435de0 AS |
3761 | |
3762 | /* | |
cb7cf7be | 3763 | * Force PLL off until brcmf_chip_attach() |
5b435de0 AS |
3764 | * programs PLL control regs |
3765 | */ | |
3766 | ||
a39be27b AS |
3767 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3768 | BRCMF_INIT_CLKCTL1, &err); | |
5b435de0 | 3769 | if (!err) |
a39be27b AS |
3770 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
3771 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 AS |
3772 | |
3773 | if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { | |
5e8149f5 | 3774 | brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", |
5b435de0 AS |
3775 | err, BRCMF_INIT_CLKCTL1, clkctl); |
3776 | goto fail; | |
3777 | } | |
3778 | ||
bb350711 AS |
3779 | /* SDIO register access works so moving |
3780 | * state from UNKNOWN to DOWN. | |
3781 | */ | |
3782 | brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_DOWN); | |
3783 | ||
cb7cf7be AS |
3784 | bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops); |
3785 | if (IS_ERR(bus->ci)) { | |
3786 | brcmf_err("brcmf_chip_attach failed!\n"); | |
3787 | bus->ci = NULL; | |
5b435de0 AS |
3788 | goto fail; |
3789 | } | |
3790 | ||
82d7f3c1 | 3791 | if (brcmf_sdio_kso_init(bus)) { |
4a3da990 PH |
3792 | brcmf_err("error enabling KSO\n"); |
3793 | goto fail; | |
3794 | } | |
3795 | ||
668761ac HM |
3796 | if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength)) |
3797 | drivestrength = bus->sdiodev->pdata->drive_strength; | |
3798 | else | |
3799 | drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; | |
65d80d0b | 3800 | brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength); |
5b435de0 | 3801 | |
454d2a88 | 3802 | /* Get info on the SOCRAM cores... */ |
5b435de0 AS |
3803 | bus->ramsize = bus->ci->ramsize; |
3804 | if (!(bus->ramsize)) { | |
5e8149f5 | 3805 | brcmf_err("failed to find SOCRAM memory!\n"); |
5b435de0 AS |
3806 | goto fail; |
3807 | } | |
3808 | ||
1e9ab4dd | 3809 | /* Set card control so an SDIO card reset does a WLAN backplane reset */ |
a39be27b AS |
3810 | reg_val = brcmf_sdiod_regrb(bus->sdiodev, |
3811 | SDIO_CCCR_BRCM_CARDCTRL, &err); | |
1e9ab4dd PH |
3812 | if (err) |
3813 | goto fail; | |
3814 | ||
3815 | reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; | |
3816 | ||
a39be27b AS |
3817 | brcmf_sdiod_regwb(bus->sdiodev, |
3818 | SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); | |
1e9ab4dd PH |
3819 | if (err) |
3820 | goto fail; | |
3821 | ||
3822 | /* set PMUControl so a backplane reset does PMU state reload */ | |
cb7cf7be | 3823 | reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base, |
1e9ab4dd | 3824 | pmucontrol); |
cb7cf7be | 3825 | reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err); |
1e9ab4dd PH |
3826 | if (err) |
3827 | goto fail; | |
3828 | ||
3829 | reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); | |
3830 | ||
cb7cf7be | 3831 | brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err); |
1e9ab4dd PH |
3832 | if (err) |
3833 | goto fail; | |
3834 | ||
38b0b0dd FL |
3835 | sdio_release_host(bus->sdiodev->func[1]); |
3836 | ||
5b435de0 AS |
3837 | brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); |
3838 | ||
9b2d2f2a AS |
3839 | /* allocate header buffer */ |
3840 | bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); | |
3841 | if (!bus->hdrbuf) | |
3842 | return false; | |
5b435de0 AS |
3843 | /* Locate an appropriately-aligned portion of hdrbuf */ |
3844 | bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], | |
9b2d2f2a | 3845 | bus->head_align); |
5b435de0 AS |
3846 | |
3847 | /* Set the poll and/or interrupt flags */ | |
3848 | bus->intr = true; | |
3849 | bus->poll = false; | |
3850 | if (bus->poll) | |
3851 | bus->pollrate = 1; | |
3852 | ||
3853 | return true; | |
3854 | ||
3855 | fail: | |
38b0b0dd | 3856 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3857 | return false; |
3858 | } | |
3859 | ||
5b435de0 | 3860 | static int |
82d7f3c1 | 3861 | brcmf_sdio_watchdog_thread(void *data) |
5b435de0 | 3862 | { |
e92eedf4 | 3863 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3864 | |
3865 | allow_signal(SIGTERM); | |
3866 | /* Run until signal received */ | |
3867 | while (1) { | |
3868 | if (kthread_should_stop()) | |
3869 | break; | |
3870 | if (!wait_for_completion_interruptible(&bus->watchdog_wait)) { | |
82d7f3c1 | 3871 | brcmf_sdio_bus_watchdog(bus); |
5b435de0 | 3872 | /* Count the tick for reference */ |
80969836 | 3873 | bus->sdcnt.tickcnt++; |
58e9df46 | 3874 | reinit_completion(&bus->watchdog_wait); |
5b435de0 AS |
3875 | } else |
3876 | break; | |
3877 | } | |
3878 | return 0; | |
3879 | } | |
3880 | ||
3881 | static void | |
82d7f3c1 | 3882 | brcmf_sdio_watchdog(unsigned long data) |
5b435de0 | 3883 | { |
e92eedf4 | 3884 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3885 | |
3886 | if (bus->watchdog_tsk) { | |
3887 | complete(&bus->watchdog_wait); | |
3888 | /* Reschedule the watchdog */ | |
3889 | if (bus->wd_timer_valid) | |
3890 | mod_timer(&bus->timer, | |
3891 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
3892 | } | |
3893 | } | |
3894 | ||
d9cb2596 | 3895 | static struct brcmf_bus_ops brcmf_sdio_bus_ops = { |
82d7f3c1 AS |
3896 | .stop = brcmf_sdio_bus_stop, |
3897 | .preinit = brcmf_sdio_bus_preinit, | |
82d7f3c1 AS |
3898 | .txdata = brcmf_sdio_bus_txdata, |
3899 | .txctl = brcmf_sdio_bus_txctl, | |
3900 | .rxctl = brcmf_sdio_bus_rxctl, | |
3901 | .gettxq = brcmf_sdio_bus_gettxq, | |
d9cb2596 AS |
3902 | }; |
3903 | ||
bd0e1b1d AS |
3904 | static void brcmf_sdio_firmware_callback(struct device *dev, |
3905 | const struct firmware *code, | |
3906 | void *nvram, u32 nvram_len) | |
3907 | { | |
3908 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3909 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3910 | struct brcmf_sdio *bus = sdiodev->bus; | |
3911 | int err = 0; | |
3912 | u8 saveclk; | |
3913 | ||
3914 | brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev)); | |
3915 | ||
3916 | /* try to download image and nvram to the dongle */ | |
3917 | if (bus_if->state == BRCMF_BUS_DOWN) { | |
3918 | bus->alp_only = true; | |
3919 | err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); | |
3920 | if (err) | |
3921 | goto fail; | |
3922 | bus->alp_only = false; | |
3923 | } | |
3924 | ||
3925 | if (!bus_if->drvr) | |
3926 | return; | |
3927 | ||
3928 | /* Start the watchdog timer */ | |
3929 | bus->sdcnt.tickcnt = 0; | |
3930 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); | |
3931 | ||
3932 | sdio_claim_host(sdiodev->func[1]); | |
3933 | ||
3934 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
3935 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
3936 | if (bus->clkstate != CLK_AVAIL) | |
3937 | goto release; | |
3938 | ||
3939 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
3940 | saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
3941 | if (!err) { | |
3942 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
3943 | (saveclk | SBSDIO_FORCE_HT), &err); | |
3944 | } | |
3945 | if (err) { | |
3946 | brcmf_err("Failed to force clock for F2: err %d\n", err); | |
3947 | goto release; | |
3948 | } | |
3949 | ||
3950 | /* Enable function 2 (frame transfers) */ | |
3951 | w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, | |
3952 | offsetof(struct sdpcmd_regs, tosbmailboxdata)); | |
3953 | err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]); | |
3954 | ||
3955 | ||
3956 | brcmf_dbg(INFO, "enable F2: err=%d\n", err); | |
3957 | ||
3958 | /* If F2 successfully enabled, set core and enable interrupts */ | |
3959 | if (!err) { | |
3960 | /* Set up the interrupt mask and enable interrupts */ | |
3961 | bus->hostintmask = HOSTINTMASK; | |
3962 | w_sdreg32(bus, bus->hostintmask, | |
3963 | offsetof(struct sdpcmd_regs, hostintmask)); | |
3964 | ||
3965 | brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err); | |
3966 | } else { | |
3967 | /* Disable F2 again */ | |
3968 | sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); | |
3969 | goto release; | |
3970 | } | |
3971 | ||
3972 | if (brcmf_chip_sr_capable(bus->ci)) { | |
3973 | brcmf_sdio_sr_init(bus); | |
3974 | } else { | |
3975 | /* Restore previous clock setting */ | |
3976 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
3977 | saveclk, &err); | |
3978 | } | |
3979 | ||
3980 | if (err == 0) { | |
3981 | err = brcmf_sdiod_intr_register(sdiodev); | |
3982 | if (err != 0) | |
3983 | brcmf_err("intr register failed:%d\n", err); | |
3984 | } | |
3985 | ||
3986 | /* If we didn't come up, turn off backplane clock */ | |
3987 | if (err != 0) | |
3988 | brcmf_sdio_clkctl(bus, CLK_NONE, false); | |
3989 | ||
3990 | sdio_release_host(sdiodev->func[1]); | |
3991 | ||
3992 | err = brcmf_bus_start(dev); | |
3993 | if (err != 0) { | |
3994 | brcmf_err("dongle is not responding\n"); | |
3995 | goto fail; | |
3996 | } | |
3997 | return; | |
3998 | ||
3999 | release: | |
4000 | sdio_release_host(sdiodev->func[1]); | |
4001 | fail: | |
4002 | brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); | |
4003 | device_release_driver(dev); | |
4004 | } | |
4005 | ||
82d7f3c1 | 4006 | struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) |
5b435de0 AS |
4007 | { |
4008 | int ret; | |
e92eedf4 | 4009 | struct brcmf_sdio *bus; |
5b435de0 | 4010 | |
5b435de0 AS |
4011 | brcmf_dbg(TRACE, "Enter\n"); |
4012 | ||
5b435de0 | 4013 | /* Allocate private bus interface state */ |
e92eedf4 | 4014 | bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); |
5b435de0 AS |
4015 | if (!bus) |
4016 | goto fail; | |
4017 | ||
4018 | bus->sdiodev = sdiodev; | |
4019 | sdiodev->bus = bus; | |
b83db862 | 4020 | skb_queue_head_init(&bus->glom); |
5b435de0 AS |
4021 | bus->txbound = BRCMF_TXBOUND; |
4022 | bus->rxbound = BRCMF_RXBOUND; | |
4023 | bus->txminmax = BRCMF_TXMINMAX; | |
6bc52319 | 4024 | bus->tx_seq = SDPCM_SEQ_WRAP - 1; |
5b435de0 | 4025 | |
e217d1c8 AS |
4026 | /* platform specific configuration: |
4027 | * alignments must be at least 4 bytes for ADMA | |
4028 | */ | |
4029 | bus->head_align = ALIGNMENT; | |
4030 | bus->sgentry_align = ALIGNMENT; | |
4031 | if (sdiodev->pdata) { | |
4032 | if (sdiodev->pdata->sd_head_align > ALIGNMENT) | |
4033 | bus->head_align = sdiodev->pdata->sd_head_align; | |
4034 | if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT) | |
4035 | bus->sgentry_align = sdiodev->pdata->sd_sgentry_align; | |
4036 | } | |
4037 | ||
37ac5780 HM |
4038 | INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); |
4039 | bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq"); | |
4040 | if (bus->brcmf_wq == NULL) { | |
5e8149f5 | 4041 | brcmf_err("insufficient memory to create txworkqueue\n"); |
37ac5780 HM |
4042 | goto fail; |
4043 | } | |
4044 | ||
5b435de0 | 4045 | /* attempt to attach to the dongle */ |
82d7f3c1 AS |
4046 | if (!(brcmf_sdio_probe_attach(bus))) { |
4047 | brcmf_err("brcmf_sdio_probe_attach failed\n"); | |
5b435de0 AS |
4048 | goto fail; |
4049 | } | |
4050 | ||
dd43a01c | 4051 | spin_lock_init(&bus->rxctl_lock); |
fed7ec44 HM |
4052 | spin_lock_init(&bus->txq_lock); |
4053 | sema_init(&bus->tx_seq_lock, 1); | |
5b435de0 AS |
4054 | init_waitqueue_head(&bus->ctrl_wait); |
4055 | init_waitqueue_head(&bus->dcmd_resp_wait); | |
4056 | ||
4057 | /* Set up the watchdog timer */ | |
4058 | init_timer(&bus->timer); | |
4059 | bus->timer.data = (unsigned long)bus; | |
82d7f3c1 | 4060 | bus->timer.function = brcmf_sdio_watchdog; |
5b435de0 | 4061 | |
5b435de0 AS |
4062 | /* Initialize watchdog thread */ |
4063 | init_completion(&bus->watchdog_wait); | |
82d7f3c1 | 4064 | bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, |
5b435de0 AS |
4065 | bus, "brcmf_watchdog"); |
4066 | if (IS_ERR(bus->watchdog_tsk)) { | |
02f77195 | 4067 | pr_warn("brcmf_watchdog thread failed to start\n"); |
5b435de0 AS |
4068 | bus->watchdog_tsk = NULL; |
4069 | } | |
4070 | /* Initialize DPC thread */ | |
fccfe930 | 4071 | atomic_set(&bus->dpc_tskcnt, 0); |
5b435de0 | 4072 | |
a9ffda88 | 4073 | /* Assign bus interface call back */ |
d9cb2596 AS |
4074 | bus->sdiodev->bus_if->dev = bus->sdiodev->dev; |
4075 | bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops; | |
75d907d3 AS |
4076 | bus->sdiodev->bus_if->chip = bus->ci->chip; |
4077 | bus->sdiodev->bus_if->chiprev = bus->ci->chiprev; | |
d9cb2596 | 4078 | |
706478cb FL |
4079 | /* default sdio bus header length for tx packet */ |
4080 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
4081 | ||
4082 | /* Attach to the common layer, reserve hdr space */ | |
8dee77ba | 4083 | ret = brcmf_attach(bus->sdiodev->dev); |
712ac5b3 | 4084 | if (ret != 0) { |
5e8149f5 | 4085 | brcmf_err("brcmf_attach failed\n"); |
5b435de0 AS |
4086 | goto fail; |
4087 | } | |
4088 | ||
4089 | /* Allocate buffers */ | |
fad13228 AS |
4090 | if (bus->sdiodev->bus_if->maxctl) { |
4091 | bus->rxblen = | |
4092 | roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), | |
4093 | ALIGNMENT) + bus->head_align; | |
4094 | bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); | |
4095 | if (!(bus->rxbuf)) { | |
4096 | brcmf_err("rxbuf allocation failed\n"); | |
4097 | goto fail; | |
4098 | } | |
5b435de0 AS |
4099 | } |
4100 | ||
fad13228 AS |
4101 | sdio_claim_host(bus->sdiodev->func[1]); |
4102 | ||
4103 | /* Disable F2 to clear any intermediate frame state on the dongle */ | |
4104 | sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]); | |
4105 | ||
fad13228 AS |
4106 | bus->rxflow = false; |
4107 | ||
4108 | /* Done with backplane-dependent accesses, can drop clock... */ | |
4109 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
4110 | ||
4111 | sdio_release_host(bus->sdiodev->func[1]); | |
4112 | ||
4113 | /* ...and initialize clock/power states */ | |
4114 | bus->clkstate = CLK_SDONLY; | |
4115 | bus->idletime = BRCMF_IDLE_INTERVAL; | |
4116 | bus->idleclock = BRCMF_IDLE_ACTIVE; | |
4117 | ||
4118 | /* Query the F2 block size, set roundup accordingly */ | |
4119 | bus->blocksize = bus->sdiodev->func[2]->cur_blksize; | |
4120 | bus->roundup = min(max_roundup, bus->blocksize); | |
4121 | ||
4122 | /* SR state */ | |
4123 | bus->sleeping = false; | |
4124 | bus->sr_enabled = false; | |
5b435de0 | 4125 | |
80969836 | 4126 | brcmf_sdio_debugfs_create(bus); |
5b435de0 AS |
4127 | brcmf_dbg(INFO, "completed!!\n"); |
4128 | ||
bd0e1b1d AS |
4129 | ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM, |
4130 | brcmf_sdio_get_fwname(bus->ci, | |
4131 | BRCMF_FIRMWARE_BIN), | |
4132 | brcmf_sdio_get_fwname(bus->ci, | |
4133 | BRCMF_FIRMWARE_NVRAM), | |
4134 | brcmf_sdio_firmware_callback); | |
5b435de0 | 4135 | if (ret != 0) { |
bd0e1b1d | 4136 | brcmf_err("async firmware request failed: %d\n", ret); |
1799ddf1 | 4137 | goto fail; |
5b435de0 | 4138 | } |
15d45b6f | 4139 | |
5b435de0 AS |
4140 | return bus; |
4141 | ||
4142 | fail: | |
9fbe2a6d | 4143 | brcmf_sdio_remove(bus); |
5b435de0 AS |
4144 | return NULL; |
4145 | } | |
4146 | ||
9fbe2a6d AS |
4147 | /* Detach and free everything */ |
4148 | void brcmf_sdio_remove(struct brcmf_sdio *bus) | |
5b435de0 | 4149 | { |
5b435de0 AS |
4150 | brcmf_dbg(TRACE, "Enter\n"); |
4151 | ||
9fbe2a6d AS |
4152 | if (bus) { |
4153 | /* De-register interrupt handler */ | |
4154 | brcmf_sdiod_intr_unregister(bus->sdiodev); | |
4155 | ||
4faf28b7 | 4156 | brcmf_detach(bus->sdiodev->dev); |
bfad4a04 | 4157 | |
e0c180ec HM |
4158 | cancel_work_sync(&bus->datawork); |
4159 | if (bus->brcmf_wq) | |
4160 | destroy_workqueue(bus->brcmf_wq); | |
4161 | ||
bfad4a04 | 4162 | if (bus->ci) { |
bb350711 AS |
4163 | if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) { |
4164 | sdio_claim_host(bus->sdiodev->func[1]); | |
4165 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
4166 | /* Leave the device in state where it is | |
4167 | * 'quiet'. This is done by putting it in | |
4168 | * download_state which essentially resets | |
4169 | * all necessary cores. | |
4170 | */ | |
4171 | msleep(20); | |
cb7cf7be | 4172 | brcmf_chip_enter_download(bus->ci); |
bb350711 AS |
4173 | brcmf_sdio_clkctl(bus, CLK_NONE, false); |
4174 | sdio_release_host(bus->sdiodev->func[1]); | |
4175 | } | |
cb7cf7be | 4176 | brcmf_chip_detach(bus->ci); |
9fbe2a6d AS |
4177 | } |
4178 | ||
bfad4a04 | 4179 | kfree(bus->rxbuf); |
9fbe2a6d AS |
4180 | kfree(bus->hdrbuf); |
4181 | kfree(bus); | |
4182 | } | |
5b435de0 AS |
4183 | |
4184 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4185 | } | |
4186 | ||
82d7f3c1 | 4187 | void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick) |
5b435de0 | 4188 | { |
5b435de0 | 4189 | /* Totally stop the timer */ |
23677ce3 | 4190 | if (!wdtick && bus->wd_timer_valid) { |
5b435de0 AS |
4191 | del_timer_sync(&bus->timer); |
4192 | bus->wd_timer_valid = false; | |
4193 | bus->save_ms = wdtick; | |
4194 | return; | |
4195 | } | |
4196 | ||
ece960ea | 4197 | /* don't start the wd until fw is loaded */ |
d6ae2c51 | 4198 | if (bus->sdiodev->bus_if->state != BRCMF_BUS_DATA) |
ece960ea FL |
4199 | return; |
4200 | ||
5b435de0 AS |
4201 | if (wdtick) { |
4202 | if (bus->save_ms != BRCMF_WD_POLL_MS) { | |
23677ce3 | 4203 | if (bus->wd_timer_valid) |
5b435de0 AS |
4204 | /* Stop timer and restart at new value */ |
4205 | del_timer_sync(&bus->timer); | |
4206 | ||
4207 | /* Create timer again when watchdog period is | |
4208 | dynamically changed or in the first instance | |
4209 | */ | |
4210 | bus->timer.expires = | |
4211 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000; | |
4212 | add_timer(&bus->timer); | |
4213 | ||
4214 | } else { | |
4215 | /* Re arm the timer, at last watchdog period */ | |
4216 | mod_timer(&bus->timer, | |
4217 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
4218 | } | |
4219 | ||
4220 | bus->wd_timer_valid = true; | |
4221 | bus->save_ms = wdtick; | |
4222 | } | |
4223 | } |