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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/printk.h> | |
21 | #include <linux/pci_ids.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/mmc/sdio.h> | |
26 | #include <linux/mmc/sdio_func.h> | |
27 | #include <linux/mmc/card.h> | |
28 | #include <linux/semaphore.h> | |
29 | #include <linux/firmware.h> | |
b7a57e76 | 30 | #include <linux/module.h> |
5b435de0 AS |
31 | #include <asm/unaligned.h> |
32 | #include <defs.h> | |
33 | #include <brcmu_wifi.h> | |
34 | #include <brcmu_utils.h> | |
35 | #include <brcm_hw_ids.h> | |
36 | #include <soc.h> | |
37 | #include "sdio_host.h" | |
38 | ||
39 | #define DCMD_RESP_TIMEOUT 2000 /* In milli second */ | |
40 | ||
41 | #ifdef BCMDBG | |
42 | ||
43 | #define BRCMF_TRAP_INFO_SIZE 80 | |
44 | ||
45 | #define CBUF_LEN (128) | |
46 | ||
47 | struct rte_log_le { | |
48 | __le32 buf; /* Can't be pointer on (64-bit) hosts */ | |
49 | __le32 buf_size; | |
50 | __le32 idx; | |
51 | char *_buf_compat; /* Redundant pointer for backward compat. */ | |
52 | }; | |
53 | ||
54 | struct rte_console { | |
55 | /* Virtual UART | |
56 | * When there is no UART (e.g. Quickturn), | |
57 | * the host should write a complete | |
58 | * input line directly into cbuf and then write | |
59 | * the length into vcons_in. | |
60 | * This may also be used when there is a real UART | |
61 | * (at risk of conflicting with | |
62 | * the real UART). vcons_out is currently unused. | |
63 | */ | |
64 | uint vcons_in; | |
65 | uint vcons_out; | |
66 | ||
67 | /* Output (logging) buffer | |
68 | * Console output is written to a ring buffer log_buf at index log_idx. | |
69 | * The host may read the output when it sees log_idx advance. | |
70 | * Output will be lost if the output wraps around faster than the host | |
71 | * polls. | |
72 | */ | |
73 | struct rte_log_le log_le; | |
74 | ||
75 | /* Console input line buffer | |
76 | * Characters are read one at a time into cbuf | |
77 | * until <CR> is received, then | |
78 | * the buffer is processed as a command line. | |
79 | * Also used for virtual UART. | |
80 | */ | |
81 | uint cbuf_idx; | |
82 | char cbuf[CBUF_LEN]; | |
83 | }; | |
84 | ||
85 | #endif /* BCMDBG */ | |
86 | #include <chipcommon.h> | |
87 | ||
88 | #include "dhd.h" | |
89 | #include "dhd_bus.h" | |
90 | #include "dhd_proto.h" | |
91 | #include "dhd_dbg.h" | |
92 | #include <bcmchip.h> | |
93 | ||
94 | #define TXQLEN 2048 /* bulk tx queue length */ | |
95 | #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ | |
96 | #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ | |
97 | #define PRIOMASK 7 | |
98 | ||
99 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
100 | ||
101 | #define BRCMF_RXBOUND 50 /* Default for max rx frames in | |
102 | one scheduling */ | |
103 | ||
104 | #define BRCMF_TXBOUND 20 /* Default for max tx frames in | |
105 | one scheduling */ | |
106 | ||
107 | #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ | |
108 | ||
109 | #define MEMBLOCK 2048 /* Block size used for downloading | |
110 | of dongle image */ | |
111 | #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold | |
112 | biggest possible glom */ | |
113 | ||
114 | #define BRCMF_FIRSTREAD (1 << 6) | |
115 | ||
116 | ||
117 | /* SBSDIO_DEVICE_CTL */ | |
118 | ||
119 | /* 1: device will assert busy signal when receiving CMD53 */ | |
120 | #define SBSDIO_DEVCTL_SETBUSY 0x01 | |
121 | /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ | |
122 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 | |
123 | /* 1: mask all interrupts to host except the chipActive (rev 8) */ | |
124 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 | |
125 | /* 1: isolate internal sdio signals, put external pads in tri-state; requires | |
126 | * sdio bus power cycle to clear (rev 9) */ | |
127 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 | |
128 | /* Force SD->SB reset mapping (rev 11) */ | |
129 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 | |
130 | /* Determined by CoreControl bit */ | |
131 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 | |
132 | /* Force backplane reset */ | |
133 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 | |
134 | /* Force no backplane reset */ | |
135 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 | |
136 | ||
137 | /* SBSDIO_FUNC1_CHIPCLKCSR */ | |
138 | ||
139 | /* Force ALP request to backplane */ | |
140 | #define SBSDIO_FORCE_ALP 0x01 | |
141 | /* Force HT request to backplane */ | |
142 | #define SBSDIO_FORCE_HT 0x02 | |
143 | /* Force ILP request to backplane */ | |
144 | #define SBSDIO_FORCE_ILP 0x04 | |
145 | /* Make ALP ready (power up xtal) */ | |
146 | #define SBSDIO_ALP_AVAIL_REQ 0x08 | |
147 | /* Make HT ready (power up PLL) */ | |
148 | #define SBSDIO_HT_AVAIL_REQ 0x10 | |
149 | /* Squelch clock requests from HW */ | |
150 | #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 | |
151 | /* Status: ALP is ready */ | |
152 | #define SBSDIO_ALP_AVAIL 0x40 | |
153 | /* Status: HT is ready */ | |
154 | #define SBSDIO_HT_AVAIL 0x80 | |
155 | ||
156 | #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) | |
157 | #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) | |
158 | #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) | |
159 | #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) | |
160 | ||
161 | #define SBSDIO_CLKAV(regval, alponly) \ | |
162 | (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) | |
163 | ||
164 | /* direct(mapped) cis space */ | |
165 | ||
166 | /* MAPPED common CIS address */ | |
167 | #define SBSDIO_CIS_BASE_COMMON 0x1000 | |
168 | /* maximum bytes in one CIS */ | |
169 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 | |
170 | /* cis offset addr is < 17 bits */ | |
171 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF | |
172 | ||
173 | /* manfid tuple length, include tuple, link bytes */ | |
174 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 | |
175 | ||
176 | /* intstatus */ | |
177 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | |
178 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | |
179 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | |
180 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | |
181 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | |
182 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | |
183 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | |
184 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | |
185 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | |
186 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | |
187 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | |
188 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | |
189 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | |
190 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | |
191 | #define I_PC (1 << 10) /* descriptor error */ | |
192 | #define I_PD (1 << 11) /* data error */ | |
193 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | |
194 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | |
195 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | |
196 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | |
197 | #define I_RI (1 << 16) /* Receive Interrupt */ | |
198 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | |
199 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | |
200 | #define I_XI (1 << 24) /* Transmit Interrupt */ | |
201 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | |
202 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | |
203 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | |
204 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | |
205 | #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ | |
206 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | |
207 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | |
208 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) | |
209 | #define I_DMA (I_RI | I_XI | I_ERRORS) | |
210 | ||
211 | /* corecontrol */ | |
212 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | |
213 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ | |
214 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | |
215 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ | |
216 | #define CC_XMTDATAAVAIL_MODE (1 << 4) | |
217 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) | |
218 | ||
219 | /* SDA_FRAMECTRL */ | |
220 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | |
221 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | |
222 | #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ | |
223 | #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ | |
224 | ||
225 | /* HW frame tag */ | |
226 | #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */ | |
227 | ||
228 | /* Total length of frame header for dongle protocol */ | |
229 | #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN) | |
230 | #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN) | |
231 | ||
232 | /* | |
233 | * Software allocation of To SB Mailbox resources | |
234 | */ | |
235 | ||
236 | /* tosbmailbox bits corresponding to intstatus bits */ | |
237 | #define SMB_NAK (1 << 0) /* Frame NAK */ | |
238 | #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ | |
239 | #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ | |
240 | #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ | |
241 | ||
242 | /* tosbmailboxdata */ | |
243 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ | |
244 | ||
245 | /* | |
246 | * Software allocation of To Host Mailbox resources | |
247 | */ | |
248 | ||
249 | /* intstatus bits */ | |
250 | #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ | |
251 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ | |
252 | #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ | |
253 | #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ | |
254 | ||
255 | /* tohostmailboxdata */ | |
256 | #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ | |
257 | #define HMB_DATA_DEVREADY 2 /* talk to host after enable */ | |
258 | #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ | |
259 | #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ | |
260 | ||
261 | #define HMB_DATA_FCDATA_MASK 0xff000000 | |
262 | #define HMB_DATA_FCDATA_SHIFT 24 | |
263 | ||
264 | #define HMB_DATA_VERSION_MASK 0x00ff0000 | |
265 | #define HMB_DATA_VERSION_SHIFT 16 | |
266 | ||
267 | /* | |
268 | * Software-defined protocol header | |
269 | */ | |
270 | ||
271 | /* Current protocol version */ | |
272 | #define SDPCM_PROT_VERSION 4 | |
273 | ||
274 | /* SW frame header */ | |
275 | #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff) | |
276 | ||
277 | #define SDPCM_CHANNEL_MASK 0x00000f00 | |
278 | #define SDPCM_CHANNEL_SHIFT 8 | |
279 | #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f) | |
280 | ||
281 | #define SDPCM_NEXTLEN_OFFSET 2 | |
282 | ||
283 | /* Data Offset from SOF (HW Tag, SW Tag, Pad) */ | |
284 | #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ | |
285 | #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) | |
286 | #define SDPCM_DOFFSET_MASK 0xff000000 | |
287 | #define SDPCM_DOFFSET_SHIFT 24 | |
288 | #define SDPCM_FCMASK_OFFSET 4 /* Flow control */ | |
289 | #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff) | |
290 | #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ | |
291 | #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) | |
292 | ||
293 | #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ | |
294 | ||
295 | /* logical channel numbers */ | |
296 | #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */ | |
297 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ | |
298 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ | |
299 | #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */ | |
300 | #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ | |
301 | ||
302 | #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */ | |
303 | ||
304 | #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) | |
305 | ||
306 | /* | |
307 | * Shared structure between dongle and the host. | |
308 | * The structure contains pointers to trap or assert information. | |
309 | */ | |
310 | #define SDPCM_SHARED_VERSION 0x0002 | |
311 | #define SDPCM_SHARED_VERSION_MASK 0x00FF | |
312 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | |
313 | #define SDPCM_SHARED_ASSERT 0x0200 | |
314 | #define SDPCM_SHARED_TRAP 0x0400 | |
315 | ||
316 | /* Space for header read, limit for data packets */ | |
317 | #define MAX_HDR_READ (1 << 6) | |
318 | #define MAX_RX_DATASZ 2048 | |
319 | ||
320 | /* Maximum milliseconds to wait for F2 to come up */ | |
321 | #define BRCMF_WAIT_F2RDY 3000 | |
322 | ||
323 | /* Bump up limit on waiting for HT to account for first startup; | |
324 | * if the image is doing a CRC calculation before programming the PMU | |
325 | * for HT availability, it could take a couple hundred ms more, so | |
326 | * max out at a 1 second (1000000us). | |
327 | */ | |
328 | #undef PMU_MAX_TRANSITION_DLY | |
329 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
330 | ||
331 | /* Value for ChipClockCSR during initial setup */ | |
332 | #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ | |
333 | SBSDIO_ALP_AVAIL_REQ) | |
334 | ||
335 | /* Flags for SDH calls */ | |
336 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
337 | ||
338 | /* sbimstate */ | |
339 | #define SBIM_IBE 0x20000 /* inbanderror */ | |
340 | #define SBIM_TO 0x40000 /* timeout */ | |
341 | #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */ | |
342 | #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */ | |
343 | ||
344 | /* sbtmstatelow */ | |
345 | ||
346 | /* reset */ | |
347 | #define SBTML_RESET 0x0001 | |
348 | /* reject field */ | |
349 | #define SBTML_REJ_MASK 0x0006 | |
350 | /* reject */ | |
351 | #define SBTML_REJ 0x0002 | |
352 | /* temporary reject, for error recovery */ | |
353 | #define SBTML_TMPREJ 0x0004 | |
354 | ||
355 | /* Shift to locate the SI control flags in sbtml */ | |
356 | #define SBTML_SICF_SHIFT 16 | |
357 | ||
358 | /* sbtmstatehigh */ | |
359 | #define SBTMH_SERR 0x0001 /* serror */ | |
360 | #define SBTMH_INT 0x0002 /* interrupt */ | |
361 | #define SBTMH_BUSY 0x0004 /* busy */ | |
362 | #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */ | |
363 | ||
364 | /* Shift to locate the SI status flags in sbtmh */ | |
365 | #define SBTMH_SISF_SHIFT 16 | |
366 | ||
367 | /* sbidlow */ | |
368 | #define SBIDL_INIT 0x80 /* initiator */ | |
369 | ||
370 | /* sbidhigh */ | |
371 | #define SBIDH_RC_MASK 0x000f /* revision code */ | |
372 | #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */ | |
373 | #define SBIDH_RCE_SHIFT 8 | |
374 | #define SBCOREREV(sbidh) \ | |
375 | ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \ | |
376 | ((sbidh) & SBIDH_RC_MASK)) | |
377 | #define SBIDH_CC_MASK 0x8ff0 /* core code */ | |
378 | #define SBIDH_CC_SHIFT 4 | |
379 | #define SBIDH_VC_MASK 0xffff0000 /* vendor code */ | |
380 | #define SBIDH_VC_SHIFT 16 | |
381 | ||
382 | /* | |
383 | * Conversion of 802.1D priority to precedence level | |
384 | */ | |
385 | static uint prio2prec(u32 prio) | |
386 | { | |
387 | return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? | |
388 | (prio^2) : prio; | |
389 | } | |
390 | ||
391 | /* | |
392 | * Core reg address translation. | |
393 | * Both macro's returns a 32 bits byte address on the backplane bus. | |
394 | */ | |
395 | #define CORE_CC_REG(base, field) \ | |
396 | (base + offsetof(struct chipcregs, field)) | |
397 | #define CORE_BUS_REG(base, field) \ | |
398 | (base + offsetof(struct sdpcmd_regs, field)) | |
399 | #define CORE_SB(base, field) \ | |
400 | (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) | |
401 | ||
402 | /* core registers */ | |
403 | struct sdpcmd_regs { | |
404 | u32 corecontrol; /* 0x00, rev8 */ | |
405 | u32 corestatus; /* rev8 */ | |
406 | u32 PAD[1]; | |
407 | u32 biststatus; /* rev8 */ | |
408 | ||
409 | /* PCMCIA access */ | |
410 | u16 pcmciamesportaladdr; /* 0x010, rev8 */ | |
411 | u16 PAD[1]; | |
412 | u16 pcmciamesportalmask; /* rev8 */ | |
413 | u16 PAD[1]; | |
414 | u16 pcmciawrframebc; /* rev8 */ | |
415 | u16 PAD[1]; | |
416 | u16 pcmciaunderflowtimer; /* rev8 */ | |
417 | u16 PAD[1]; | |
418 | ||
419 | /* interrupt */ | |
420 | u32 intstatus; /* 0x020, rev8 */ | |
421 | u32 hostintmask; /* rev8 */ | |
422 | u32 intmask; /* rev8 */ | |
423 | u32 sbintstatus; /* rev8 */ | |
424 | u32 sbintmask; /* rev8 */ | |
425 | u32 funcintmask; /* rev4 */ | |
426 | u32 PAD[2]; | |
427 | u32 tosbmailbox; /* 0x040, rev8 */ | |
428 | u32 tohostmailbox; /* rev8 */ | |
429 | u32 tosbmailboxdata; /* rev8 */ | |
430 | u32 tohostmailboxdata; /* rev8 */ | |
431 | ||
432 | /* synchronized access to registers in SDIO clock domain */ | |
433 | u32 sdioaccess; /* 0x050, rev8 */ | |
434 | u32 PAD[3]; | |
435 | ||
436 | /* PCMCIA frame control */ | |
437 | u8 pcmciaframectrl; /* 0x060, rev8 */ | |
438 | u8 PAD[3]; | |
439 | u8 pcmciawatermark; /* rev8 */ | |
440 | u8 PAD[155]; | |
441 | ||
442 | /* interrupt batching control */ | |
443 | u32 intrcvlazy; /* 0x100, rev8 */ | |
444 | u32 PAD[3]; | |
445 | ||
446 | /* counters */ | |
447 | u32 cmd52rd; /* 0x110, rev8 */ | |
448 | u32 cmd52wr; /* rev8 */ | |
449 | u32 cmd53rd; /* rev8 */ | |
450 | u32 cmd53wr; /* rev8 */ | |
451 | u32 abort; /* rev8 */ | |
452 | u32 datacrcerror; /* rev8 */ | |
453 | u32 rdoutofsync; /* rev8 */ | |
454 | u32 wroutofsync; /* rev8 */ | |
455 | u32 writebusy; /* rev8 */ | |
456 | u32 readwait; /* rev8 */ | |
457 | u32 readterm; /* rev8 */ | |
458 | u32 writeterm; /* rev8 */ | |
459 | u32 PAD[40]; | |
460 | u32 clockctlstatus; /* rev8 */ | |
461 | u32 PAD[7]; | |
462 | ||
463 | u32 PAD[128]; /* DMA engines */ | |
464 | ||
465 | /* SDIO/PCMCIA CIS region */ | |
466 | char cis[512]; /* 0x400-0x5ff, rev6 */ | |
467 | ||
468 | /* PCMCIA function control registers */ | |
469 | char pcmciafcr[256]; /* 0x600-6ff, rev6 */ | |
470 | u16 PAD[55]; | |
471 | ||
472 | /* PCMCIA backplane access */ | |
473 | u16 backplanecsr; /* 0x76E, rev6 */ | |
474 | u16 backplaneaddr0; /* rev6 */ | |
475 | u16 backplaneaddr1; /* rev6 */ | |
476 | u16 backplaneaddr2; /* rev6 */ | |
477 | u16 backplaneaddr3; /* rev6 */ | |
478 | u16 backplanedata0; /* rev6 */ | |
479 | u16 backplanedata1; /* rev6 */ | |
480 | u16 backplanedata2; /* rev6 */ | |
481 | u16 backplanedata3; /* rev6 */ | |
482 | u16 PAD[31]; | |
483 | ||
484 | /* sprom "size" & "blank" info */ | |
485 | u16 spromstatus; /* 0x7BE, rev2 */ | |
486 | u32 PAD[464]; | |
487 | ||
488 | u16 PAD[0x80]; | |
489 | }; | |
490 | ||
491 | #ifdef BCMDBG | |
492 | /* Device console log buffer state */ | |
493 | struct brcmf_console { | |
494 | uint count; /* Poll interval msec counter */ | |
495 | uint log_addr; /* Log struct address (fixed) */ | |
496 | struct rte_log_le log_le; /* Log struct (host copy) */ | |
497 | uint bufsize; /* Size of log buffer */ | |
498 | u8 *buf; /* Log buffer (host copy) */ | |
499 | uint last; /* Last buffer read index */ | |
500 | }; | |
501 | #endif /* BCMDBG */ | |
502 | ||
503 | struct sdpcm_shared { | |
504 | u32 flags; | |
505 | u32 trap_addr; | |
506 | u32 assert_exp_addr; | |
507 | u32 assert_file_addr; | |
508 | u32 assert_line; | |
509 | u32 console_addr; /* Address of struct rte_console */ | |
510 | u32 msgtrace_addr; | |
511 | u8 tag[32]; | |
512 | }; | |
513 | ||
514 | struct sdpcm_shared_le { | |
515 | __le32 flags; | |
516 | __le32 trap_addr; | |
517 | __le32 assert_exp_addr; | |
518 | __le32 assert_file_addr; | |
519 | __le32 assert_line; | |
520 | __le32 console_addr; /* Address of struct rte_console */ | |
521 | __le32 msgtrace_addr; | |
522 | u8 tag[32]; | |
523 | }; | |
524 | ||
525 | ||
526 | /* misc chip info needed by some of the routines */ | |
527 | struct chip_info { | |
528 | u32 chip; | |
529 | u32 chiprev; | |
530 | u32 cccorebase; | |
531 | u32 ccrev; | |
532 | u32 cccaps; | |
533 | u32 buscorebase; /* 32 bits backplane bus address */ | |
534 | u32 buscorerev; | |
535 | u32 buscoretype; | |
536 | u32 ramcorebase; | |
537 | u32 armcorebase; | |
538 | u32 pmurev; | |
539 | u32 ramsize; | |
540 | }; | |
541 | ||
542 | /* Private data for SDIO bus interaction */ | |
543 | struct brcmf_bus { | |
544 | struct brcmf_pub *drvr; | |
545 | ||
546 | struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ | |
547 | struct chip_info *ci; /* Chip info struct */ | |
548 | char *vars; /* Variables (from CIS and/or other) */ | |
549 | uint varsz; /* Size of variables buffer */ | |
550 | ||
551 | u32 ramsize; /* Size of RAM in SOCRAM (bytes) */ | |
552 | ||
553 | u32 hostintmask; /* Copy of Host Interrupt Mask */ | |
554 | u32 intstatus; /* Intstatus bits (events) pending */ | |
555 | bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */ | |
556 | bool fcstate; /* State of dongle flow-control */ | |
557 | ||
558 | uint blocksize; /* Block size of SDIO transfers */ | |
559 | uint roundup; /* Max roundup limit */ | |
560 | ||
561 | struct pktq txq; /* Queue length used for flow-control */ | |
562 | u8 flowcontrol; /* per prio flow control bitmask */ | |
563 | u8 tx_seq; /* Transmit sequence number (next) */ | |
564 | u8 tx_max; /* Maximum transmit sequence allowed */ | |
565 | ||
566 | u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN]; | |
567 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ | |
568 | u16 nextlen; /* Next Read Len from last header */ | |
569 | u8 rx_seq; /* Receive sequence number (expected) */ | |
570 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ | |
571 | ||
572 | uint rxbound; /* Rx frames to read before resched */ | |
573 | uint txbound; /* Tx frames to send before resched */ | |
574 | uint txminmax; | |
575 | ||
576 | struct sk_buff *glomd; /* Packet containing glomming descriptor */ | |
577 | struct sk_buff *glom; /* Packet chain for glommed superframe */ | |
578 | uint glomerr; /* Glom packet read errors */ | |
579 | ||
580 | u8 *rxbuf; /* Buffer for receiving control packets */ | |
581 | uint rxblen; /* Allocated length of rxbuf */ | |
582 | u8 *rxctl; /* Aligned pointer into rxbuf */ | |
583 | u8 *databuf; /* Buffer for receiving big glom packet */ | |
584 | u8 *dataptr; /* Aligned pointer into databuf */ | |
585 | uint rxlen; /* Length of valid data in buffer */ | |
586 | ||
587 | u8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
588 | ||
589 | bool intr; /* Use interrupts */ | |
590 | bool poll; /* Use polling */ | |
591 | bool ipend; /* Device interrupt is pending */ | |
592 | uint intrcount; /* Count of device interrupt callbacks */ | |
593 | uint lastintrs; /* Count as of last watchdog timer */ | |
594 | uint spurious; /* Count of spurious interrupts */ | |
595 | uint pollrate; /* Ticks between device polls */ | |
596 | uint polltick; /* Tick counter */ | |
597 | uint pollcnt; /* Count of active polls */ | |
598 | ||
599 | #ifdef BCMDBG | |
600 | uint console_interval; | |
601 | struct brcmf_console console; /* Console output polling support */ | |
602 | uint console_addr; /* Console address from shared struct */ | |
603 | #endif /* BCMDBG */ | |
604 | ||
605 | uint regfails; /* Count of R_REG failures */ | |
606 | ||
607 | uint clkstate; /* State of sd and backplane clock(s) */ | |
608 | bool activity; /* Activity flag for clock down */ | |
609 | s32 idletime; /* Control for activity timeout */ | |
610 | s32 idlecount; /* Activity timeout counter */ | |
611 | s32 idleclock; /* How to set bus driver when idle */ | |
612 | s32 sd_rxchain; | |
613 | bool use_rxchain; /* If brcmf should use PKT chains */ | |
614 | bool sleeping; /* Is SDIO bus sleeping? */ | |
615 | bool rxflow_mode; /* Rx flow control mode */ | |
616 | bool rxflow; /* Is rx flow control on */ | |
617 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
618 | /* Field to decide if rx of control frames happen in rxbuf or lb-pool */ | |
619 | bool usebufpool; | |
620 | ||
621 | /* Some additional counters */ | |
622 | uint tx_sderrs; /* Count of tx attempts with sd errors */ | |
623 | uint fcqueued; /* Tx packets that got queued */ | |
624 | uint rxrtx; /* Count of rtx requests (NAK to dongle) */ | |
625 | uint rx_toolong; /* Receive frames too long to receive */ | |
626 | uint rxc_errors; /* SDIO errors when reading control frames */ | |
627 | uint rx_hdrfail; /* SDIO errors on header reads */ | |
628 | uint rx_badhdr; /* Bad received headers (roosync?) */ | |
629 | uint rx_badseq; /* Mismatched rx sequence number */ | |
630 | uint fc_rcvd; /* Number of flow-control events received */ | |
631 | uint fc_xoff; /* Number which turned on flow-control */ | |
632 | uint fc_xon; /* Number which turned off flow-control */ | |
633 | uint rxglomfail; /* Failed deglom attempts */ | |
634 | uint rxglomframes; /* Number of glom frames (superframes) */ | |
635 | uint rxglompkts; /* Number of packets from glom frames */ | |
636 | uint f2rxhdrs; /* Number of header reads */ | |
637 | uint f2rxdata; /* Number of frame data reads */ | |
638 | uint f2txdata; /* Number of f2 frame writes */ | |
639 | uint f1regdata; /* Number of f1 register accesses */ | |
640 | ||
641 | u8 *ctrl_frame_buf; | |
642 | u32 ctrl_frame_len; | |
643 | bool ctrl_frame_stat; | |
644 | ||
645 | spinlock_t txqlock; | |
646 | wait_queue_head_t ctrl_wait; | |
647 | wait_queue_head_t dcmd_resp_wait; | |
648 | ||
649 | struct timer_list timer; | |
650 | struct completion watchdog_wait; | |
651 | struct task_struct *watchdog_tsk; | |
652 | bool wd_timer_valid; | |
653 | uint save_ms; | |
654 | ||
655 | struct task_struct *dpc_tsk; | |
656 | struct completion dpc_wait; | |
657 | ||
658 | struct semaphore sdsem; | |
659 | ||
660 | const char *fw_name; | |
661 | const struct firmware *firmware; | |
662 | const char *nv_name; | |
663 | u32 fw_ptr; | |
664 | }; | |
665 | ||
666 | struct sbconfig { | |
667 | u32 PAD[2]; | |
668 | u32 sbipsflag; /* initiator port ocp slave flag */ | |
669 | u32 PAD[3]; | |
670 | u32 sbtpsflag; /* target port ocp slave flag */ | |
671 | u32 PAD[11]; | |
672 | u32 sbtmerrloga; /* (sonics >= 2.3) */ | |
673 | u32 PAD; | |
674 | u32 sbtmerrlog; /* (sonics >= 2.3) */ | |
675 | u32 PAD[3]; | |
676 | u32 sbadmatch3; /* address match3 */ | |
677 | u32 PAD; | |
678 | u32 sbadmatch2; /* address match2 */ | |
679 | u32 PAD; | |
680 | u32 sbadmatch1; /* address match1 */ | |
681 | u32 PAD[7]; | |
682 | u32 sbimstate; /* initiator agent state */ | |
683 | u32 sbintvec; /* interrupt mask */ | |
684 | u32 sbtmstatelow; /* target state */ | |
685 | u32 sbtmstatehigh; /* target state */ | |
686 | u32 sbbwa0; /* bandwidth allocation table0 */ | |
687 | u32 PAD; | |
688 | u32 sbimconfiglow; /* initiator configuration */ | |
689 | u32 sbimconfighigh; /* initiator configuration */ | |
690 | u32 sbadmatch0; /* address match0 */ | |
691 | u32 PAD; | |
692 | u32 sbtmconfiglow; /* target configuration */ | |
693 | u32 sbtmconfighigh; /* target configuration */ | |
694 | u32 sbbconfig; /* broadcast configuration */ | |
695 | u32 PAD; | |
696 | u32 sbbstate; /* broadcast state */ | |
697 | u32 PAD[3]; | |
698 | u32 sbactcnfg; /* activate configuration */ | |
699 | u32 PAD[3]; | |
700 | u32 sbflagst; /* current sbflags */ | |
701 | u32 PAD[3]; | |
702 | u32 sbidlow; /* identification */ | |
703 | u32 sbidhigh; /* identification */ | |
704 | }; | |
705 | ||
706 | /* clkstate */ | |
707 | #define CLK_NONE 0 | |
708 | #define CLK_SDONLY 1 | |
709 | #define CLK_PENDING 2 /* Not used yet */ | |
710 | #define CLK_AVAIL 3 | |
711 | ||
712 | #ifdef BCMDBG | |
713 | static int qcount[NUMPRIO]; | |
714 | static int tx_packets[NUMPRIO]; | |
715 | #endif /* BCMDBG */ | |
716 | ||
717 | #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */ | |
718 | ||
719 | #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) | |
720 | ||
721 | /* Retry count for register access failures */ | |
722 | static const uint retry_limit = 2; | |
723 | ||
724 | /* Limit on rounding up frames */ | |
725 | static const uint max_roundup = 512; | |
726 | ||
727 | #define ALIGNMENT 4 | |
728 | ||
729 | static void pkt_align(struct sk_buff *p, int len, int align) | |
730 | { | |
731 | uint datalign; | |
732 | datalign = (unsigned long)(p->data); | |
733 | datalign = roundup(datalign, (align)) - datalign; | |
734 | if (datalign) | |
735 | skb_pull(p, datalign); | |
736 | __skb_trim(p, len); | |
737 | } | |
738 | ||
739 | /* To check if there's window offered */ | |
740 | static bool data_ok(struct brcmf_bus *bus) | |
741 | { | |
742 | return (u8)(bus->tx_max - bus->tx_seq) != 0 && | |
743 | ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; | |
744 | } | |
745 | ||
746 | /* | |
747 | * Reads a register in the SDIO hardware block. This block occupies a series of | |
748 | * adresses on the 32 bit backplane bus. | |
749 | */ | |
750 | static void | |
751 | r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar) | |
752 | { | |
753 | *retryvar = 0; | |
754 | do { | |
755 | *regvar = brcmf_sdcard_reg_read(bus->sdiodev, | |
756 | bus->ci->buscorebase + reg_offset, sizeof(u32)); | |
757 | } while (brcmf_sdcard_regfail(bus->sdiodev) && | |
758 | (++(*retryvar) <= retry_limit)); | |
759 | if (*retryvar) { | |
760 | bus->regfails += (*retryvar-1); | |
761 | if (*retryvar > retry_limit) { | |
762 | brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset); | |
763 | *regvar = 0; | |
764 | } | |
765 | } | |
766 | } | |
767 | ||
768 | static void | |
769 | w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar) | |
770 | { | |
771 | *retryvar = 0; | |
772 | do { | |
773 | brcmf_sdcard_reg_write(bus->sdiodev, | |
774 | bus->ci->buscorebase + reg_offset, | |
775 | sizeof(u32), regval); | |
776 | } while (brcmf_sdcard_regfail(bus->sdiodev) && | |
777 | (++(*retryvar) <= retry_limit)); | |
778 | if (*retryvar) { | |
779 | bus->regfails += (*retryvar-1); | |
780 | if (*retryvar > retry_limit) | |
781 | brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n", | |
782 | reg_offset); | |
783 | } | |
784 | } | |
785 | ||
786 | #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND) | |
787 | ||
788 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) | |
789 | ||
790 | /* Packet free applicable unconditionally for sdio and sdspi. | |
791 | * Conditional if bufpool was present for gspi bus. | |
792 | */ | |
793 | static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt) | |
794 | { | |
795 | if (bus->usebufpool) | |
796 | brcmu_pkt_buf_free_skb(pkt); | |
797 | } | |
798 | ||
799 | /* Turn backplane clock on or off */ | |
800 | static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok) | |
801 | { | |
802 | int err; | |
803 | u8 clkctl, clkreq, devctl; | |
804 | unsigned long timeout; | |
805 | ||
806 | brcmf_dbg(TRACE, "Enter\n"); | |
807 | ||
808 | clkctl = 0; | |
809 | ||
810 | if (on) { | |
811 | /* Request HT Avail */ | |
812 | clkreq = | |
813 | bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
814 | ||
815 | if ((bus->ci->chip == BCM4329_CHIP_ID) | |
816 | && (bus->ci->chiprev == 0)) | |
817 | clkreq |= SBSDIO_FORCE_ALP; | |
818 | ||
819 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
820 | SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); | |
821 | if (err) { | |
822 | brcmf_dbg(ERROR, "HT Avail request error: %d\n", err); | |
823 | return -EBADE; | |
824 | } | |
825 | ||
826 | if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID) | |
827 | && (bus->ci->buscorerev == 9))) { | |
828 | u32 dummy, retries; | |
829 | r_sdreg32(bus, &dummy, | |
830 | offsetof(struct sdpcmd_regs, clockctlstatus), | |
831 | &retries); | |
832 | } | |
833 | ||
834 | /* Check current status */ | |
835 | clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
836 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
837 | if (err) { | |
838 | brcmf_dbg(ERROR, "HT Avail read error: %d\n", err); | |
839 | return -EBADE; | |
840 | } | |
841 | ||
842 | /* Go to pending and await interrupt if appropriate */ | |
843 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
844 | /* Allow only clock-available interrupt */ | |
845 | devctl = brcmf_sdcard_cfg_read(bus->sdiodev, | |
846 | SDIO_FUNC_1, | |
847 | SBSDIO_DEVICE_CTL, &err); | |
848 | if (err) { | |
849 | brcmf_dbg(ERROR, "Devctl error setting CA: %d\n", | |
850 | err); | |
851 | return -EBADE; | |
852 | } | |
853 | ||
854 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
855 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
856 | SBSDIO_DEVICE_CTL, devctl, &err); | |
857 | brcmf_dbg(INFO, "CLKCTL: set PENDING\n"); | |
858 | bus->clkstate = CLK_PENDING; | |
859 | ||
860 | return 0; | |
861 | } else if (bus->clkstate == CLK_PENDING) { | |
862 | /* Cancel CA-only interrupt filter */ | |
863 | devctl = | |
864 | brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
865 | SBSDIO_DEVICE_CTL, &err); | |
866 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
867 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
868 | SBSDIO_DEVICE_CTL, devctl, &err); | |
869 | } | |
870 | ||
871 | /* Otherwise, wait here (polling) for HT Avail */ | |
872 | timeout = jiffies + | |
873 | msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); | |
874 | while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
875 | clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, | |
876 | SDIO_FUNC_1, | |
877 | SBSDIO_FUNC1_CHIPCLKCSR, | |
878 | &err); | |
879 | if (time_after(jiffies, timeout)) | |
880 | break; | |
881 | else | |
882 | usleep_range(5000, 10000); | |
883 | } | |
884 | if (err) { | |
885 | brcmf_dbg(ERROR, "HT Avail request error: %d\n", err); | |
886 | return -EBADE; | |
887 | } | |
888 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
889 | brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n", | |
890 | PMU_MAX_TRANSITION_DLY, clkctl); | |
891 | return -EBADE; | |
892 | } | |
893 | ||
894 | /* Mark clock available */ | |
895 | bus->clkstate = CLK_AVAIL; | |
896 | brcmf_dbg(INFO, "CLKCTL: turned ON\n"); | |
897 | ||
898 | #if defined(BCMDBG) | |
899 | if (bus->alp_only != true) { | |
900 | if (SBSDIO_ALPONLY(clkctl)) | |
901 | brcmf_dbg(ERROR, "HT Clock should be on\n"); | |
902 | } | |
903 | #endif /* defined (BCMDBG) */ | |
904 | ||
905 | bus->activity = true; | |
906 | } else { | |
907 | clkreq = 0; | |
908 | ||
909 | if (bus->clkstate == CLK_PENDING) { | |
910 | /* Cancel CA-only interrupt filter */ | |
911 | devctl = brcmf_sdcard_cfg_read(bus->sdiodev, | |
912 | SDIO_FUNC_1, | |
913 | SBSDIO_DEVICE_CTL, &err); | |
914 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
915 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
916 | SBSDIO_DEVICE_CTL, devctl, &err); | |
917 | } | |
918 | ||
919 | bus->clkstate = CLK_SDONLY; | |
920 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
921 | SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); | |
922 | brcmf_dbg(INFO, "CLKCTL: turned OFF\n"); | |
923 | if (err) { | |
924 | brcmf_dbg(ERROR, "Failed access turning clock off: %d\n", | |
925 | err); | |
926 | return -EBADE; | |
927 | } | |
928 | } | |
929 | return 0; | |
930 | } | |
931 | ||
932 | /* Change idle/active SD state */ | |
933 | static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on) | |
934 | { | |
935 | brcmf_dbg(TRACE, "Enter\n"); | |
936 | ||
937 | if (on) | |
938 | bus->clkstate = CLK_SDONLY; | |
939 | else | |
940 | bus->clkstate = CLK_NONE; | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | /* Transition SD and backplane clock readiness */ | |
946 | static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok) | |
947 | { | |
948 | #ifdef BCMDBG | |
949 | uint oldstate = bus->clkstate; | |
950 | #endif /* BCMDBG */ | |
951 | ||
952 | brcmf_dbg(TRACE, "Enter\n"); | |
953 | ||
954 | /* Early exit if we're already there */ | |
955 | if (bus->clkstate == target) { | |
956 | if (target == CLK_AVAIL) { | |
957 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
958 | bus->activity = true; | |
959 | } | |
960 | return 0; | |
961 | } | |
962 | ||
963 | switch (target) { | |
964 | case CLK_AVAIL: | |
965 | /* Make sure SD clock is available */ | |
966 | if (bus->clkstate == CLK_NONE) | |
967 | brcmf_sdbrcm_sdclk(bus, true); | |
968 | /* Now request HT Avail on the backplane */ | |
969 | brcmf_sdbrcm_htclk(bus, true, pendok); | |
970 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
971 | bus->activity = true; | |
972 | break; | |
973 | ||
974 | case CLK_SDONLY: | |
975 | /* Remove HT request, or bring up SD clock */ | |
976 | if (bus->clkstate == CLK_NONE) | |
977 | brcmf_sdbrcm_sdclk(bus, true); | |
978 | else if (bus->clkstate == CLK_AVAIL) | |
979 | brcmf_sdbrcm_htclk(bus, false, false); | |
980 | else | |
981 | brcmf_dbg(ERROR, "request for %d -> %d\n", | |
982 | bus->clkstate, target); | |
983 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
984 | break; | |
985 | ||
986 | case CLK_NONE: | |
987 | /* Make sure to remove HT request */ | |
988 | if (bus->clkstate == CLK_AVAIL) | |
989 | brcmf_sdbrcm_htclk(bus, false, false); | |
990 | /* Now remove the SD clock */ | |
991 | brcmf_sdbrcm_sdclk(bus, false); | |
992 | brcmf_sdbrcm_wd_timer(bus, 0); | |
993 | break; | |
994 | } | |
995 | #ifdef BCMDBG | |
996 | brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate); | |
997 | #endif /* BCMDBG */ | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep) | |
1003 | { | |
1004 | uint retries = 0; | |
1005 | ||
1006 | brcmf_dbg(INFO, "request %s (currently %s)\n", | |
1007 | sleep ? "SLEEP" : "WAKE", | |
1008 | bus->sleeping ? "SLEEP" : "WAKE"); | |
1009 | ||
1010 | /* Done if we're already in the requested state */ | |
1011 | if (sleep == bus->sleeping) | |
1012 | return 0; | |
1013 | ||
1014 | /* Going to sleep: set the alarm and turn off the lights... */ | |
1015 | if (sleep) { | |
1016 | /* Don't sleep if something is pending */ | |
1017 | if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq)) | |
1018 | return -EBUSY; | |
1019 | ||
1020 | /* Make sure the controller has the bus up */ | |
1021 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
1022 | ||
1023 | /* Tell device to start using OOB wakeup */ | |
1024 | w_sdreg32(bus, SMB_USE_OOB, | |
1025 | offsetof(struct sdpcmd_regs, tosbmailbox), &retries); | |
1026 | if (retries > retry_limit) | |
1027 | brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"); | |
1028 | ||
1029 | /* Turn off our contribution to the HT clock request */ | |
1030 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
1031 | ||
1032 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
1033 | SBSDIO_FUNC1_CHIPCLKCSR, | |
1034 | SBSDIO_FORCE_HW_CLKREQ_OFF, NULL); | |
1035 | ||
1036 | /* Isolate the bus */ | |
1037 | if (bus->ci->chip != BCM4329_CHIP_ID) { | |
1038 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
1039 | SBSDIO_DEVICE_CTL, | |
1040 | SBSDIO_DEVCTL_PADS_ISO, NULL); | |
1041 | } | |
1042 | ||
1043 | /* Change state */ | |
1044 | bus->sleeping = true; | |
1045 | ||
1046 | } else { | |
1047 | /* Waking up: bus power up is ok, set local state */ | |
1048 | ||
1049 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
1050 | SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
1051 | ||
1052 | /* Force pad isolation off if possible | |
1053 | (in case power never toggled) */ | |
1054 | if ((bus->ci->buscoretype == PCMCIA_CORE_ID) | |
1055 | && (bus->ci->buscorerev >= 10)) | |
1056 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
1057 | SBSDIO_DEVICE_CTL, 0, NULL); | |
1058 | ||
1059 | /* Make sure the controller has the bus up */ | |
1060 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
1061 | ||
1062 | /* Send misc interrupt to indicate OOB not needed */ | |
1063 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata), | |
1064 | &retries); | |
1065 | if (retries <= retry_limit) | |
1066 | w_sdreg32(bus, SMB_DEV_INT, | |
1067 | offsetof(struct sdpcmd_regs, tosbmailbox), | |
1068 | &retries); | |
1069 | ||
1070 | if (retries > retry_limit) | |
1071 | brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"); | |
1072 | ||
1073 | /* Make sure we have SD bus access */ | |
1074 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
1075 | ||
1076 | /* Change state */ | |
1077 | bus->sleeping = false; | |
1078 | } | |
1079 | ||
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | static void bus_wake(struct brcmf_bus *bus) | |
1084 | { | |
1085 | if (bus->sleeping) | |
1086 | brcmf_sdbrcm_bussleep(bus, false); | |
1087 | } | |
1088 | ||
1089 | static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus) | |
1090 | { | |
1091 | u32 intstatus = 0; | |
1092 | u32 hmb_data; | |
1093 | u8 fcbits; | |
1094 | uint retries = 0; | |
1095 | ||
1096 | brcmf_dbg(TRACE, "Enter\n"); | |
1097 | ||
1098 | /* Read mailbox data and ack that we did so */ | |
1099 | r_sdreg32(bus, &hmb_data, | |
1100 | offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries); | |
1101 | ||
1102 | if (retries <= retry_limit) | |
1103 | w_sdreg32(bus, SMB_INT_ACK, | |
1104 | offsetof(struct sdpcmd_regs, tosbmailbox), &retries); | |
1105 | bus->f1regdata += 2; | |
1106 | ||
1107 | /* Dongle recomposed rx frames, accept them again */ | |
1108 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
1109 | brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n", | |
1110 | bus->rx_seq); | |
1111 | if (!bus->rxskip) | |
1112 | brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n"); | |
1113 | ||
1114 | bus->rxskip = false; | |
1115 | intstatus |= I_HMB_FRAME_IND; | |
1116 | } | |
1117 | ||
1118 | /* | |
1119 | * DEVREADY does not occur with gSPI. | |
1120 | */ | |
1121 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
1122 | bus->sdpcm_ver = | |
1123 | (hmb_data & HMB_DATA_VERSION_MASK) >> | |
1124 | HMB_DATA_VERSION_SHIFT; | |
1125 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
1126 | brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, " | |
1127 | "expecting %d\n", | |
1128 | bus->sdpcm_ver, SDPCM_PROT_VERSION); | |
1129 | else | |
1130 | brcmf_dbg(INFO, "Dongle ready, protocol version %d\n", | |
1131 | bus->sdpcm_ver); | |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * Flow Control has been moved into the RX headers and this out of band | |
1136 | * method isn't used any more. | |
1137 | * remaining backward compatible with older dongles. | |
1138 | */ | |
1139 | if (hmb_data & HMB_DATA_FC) { | |
1140 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> | |
1141 | HMB_DATA_FCDATA_SHIFT; | |
1142 | ||
1143 | if (fcbits & ~bus->flowcontrol) | |
1144 | bus->fc_xoff++; | |
1145 | ||
1146 | if (bus->flowcontrol & ~fcbits) | |
1147 | bus->fc_xon++; | |
1148 | ||
1149 | bus->fc_rcvd++; | |
1150 | bus->flowcontrol = fcbits; | |
1151 | } | |
1152 | ||
1153 | /* Shouldn't be any others */ | |
1154 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
1155 | HMB_DATA_NAKHANDLED | | |
1156 | HMB_DATA_FC | | |
1157 | HMB_DATA_FWREADY | | |
1158 | HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) | |
1159 | brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n", | |
1160 | hmb_data); | |
1161 | ||
1162 | return intstatus; | |
1163 | } | |
1164 | ||
1165 | static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx) | |
1166 | { | |
1167 | uint retries = 0; | |
1168 | u16 lastrbc; | |
1169 | u8 hi, lo; | |
1170 | int err; | |
1171 | ||
1172 | brcmf_dbg(ERROR, "%sterminate frame%s\n", | |
1173 | abort ? "abort command, " : "", | |
1174 | rtx ? ", send NAK" : ""); | |
1175 | ||
1176 | if (abort) | |
1177 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
1178 | ||
1179 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
1180 | SBSDIO_FUNC1_FRAMECTRL, | |
1181 | SFC_RF_TERM, &err); | |
1182 | bus->f1regdata++; | |
1183 | ||
1184 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
1185 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
1186 | hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
1187 | SBSDIO_FUNC1_RFRAMEBCHI, NULL); | |
1188 | lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
1189 | SBSDIO_FUNC1_RFRAMEBCLO, NULL); | |
1190 | bus->f1regdata += 2; | |
1191 | ||
1192 | if ((hi == 0) && (lo == 0)) | |
1193 | break; | |
1194 | ||
1195 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
1196 | brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n", | |
1197 | lastrbc, (hi << 8) + lo); | |
1198 | } | |
1199 | lastrbc = (hi << 8) + lo; | |
1200 | } | |
1201 | ||
1202 | if (!retries) | |
1203 | brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc); | |
1204 | else | |
1205 | brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries); | |
1206 | ||
1207 | if (rtx) { | |
1208 | bus->rxrtx++; | |
1209 | w_sdreg32(bus, SMB_NAK, | |
1210 | offsetof(struct sdpcmd_regs, tosbmailbox), &retries); | |
1211 | ||
1212 | bus->f1regdata++; | |
1213 | if (retries <= retry_limit) | |
1214 | bus->rxskip = true; | |
1215 | } | |
1216 | ||
1217 | /* Clear partial in any case */ | |
1218 | bus->nextlen = 0; | |
1219 | ||
1220 | /* If we can't reach the device, signal failure */ | |
1221 | if (err || brcmf_sdcard_regfail(bus->sdiodev)) | |
1222 | bus->drvr->busstate = BRCMF_BUS_DOWN; | |
1223 | } | |
1224 | ||
20e5ca16 AS |
1225 | /* copy a buffer into a pkt buffer chain */ |
1226 | static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_bus *bus, uint len) | |
1227 | { | |
1228 | uint n, ret = 0; | |
1229 | struct sk_buff *p; | |
1230 | u8 *buf; | |
1231 | ||
1232 | p = bus->glom; | |
1233 | buf = bus->dataptr; | |
1234 | ||
1235 | /* copy the data */ | |
1236 | for (; p && len; p = p->next) { | |
1237 | n = min_t(uint, p->len, len); | |
1238 | memcpy(p->data, buf, n); | |
1239 | buf += n; | |
1240 | len -= n; | |
1241 | ret += n; | |
1242 | } | |
1243 | ||
1244 | return ret; | |
1245 | } | |
1246 | ||
5b435de0 AS |
1247 | static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq) |
1248 | { | |
1249 | u16 dlen, totlen; | |
1250 | u8 *dptr, num = 0; | |
1251 | ||
1252 | u16 sublen, check; | |
1253 | struct sk_buff *pfirst, *plast, *pnext, *save_pfirst; | |
1254 | ||
1255 | int errcode; | |
1256 | u8 chan, seq, doff, sfdoff; | |
1257 | u8 txmax; | |
1258 | ||
1259 | int ifidx = 0; | |
1260 | bool usechain = bus->use_rxchain; | |
1261 | ||
1262 | /* If packets, issue read(s) and send up packet chain */ | |
1263 | /* Return sequence numbers consumed? */ | |
1264 | ||
1265 | brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom); | |
1266 | ||
1267 | /* If there's a descriptor, generate the packet chain */ | |
1268 | if (bus->glomd) { | |
1269 | pfirst = plast = pnext = NULL; | |
1270 | dlen = (u16) (bus->glomd->len); | |
1271 | dptr = bus->glomd->data; | |
1272 | if (!dlen || (dlen & 1)) { | |
1273 | brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n", | |
1274 | dlen); | |
1275 | dlen = 0; | |
1276 | } | |
1277 | ||
1278 | for (totlen = num = 0; dlen; num++) { | |
1279 | /* Get (and move past) next length */ | |
1280 | sublen = get_unaligned_le16(dptr); | |
1281 | dlen -= sizeof(u16); | |
1282 | dptr += sizeof(u16); | |
1283 | if ((sublen < SDPCM_HDRLEN) || | |
1284 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
1285 | brcmf_dbg(ERROR, "descriptor len %d bad: %d\n", | |
1286 | num, sublen); | |
1287 | pnext = NULL; | |
1288 | break; | |
1289 | } | |
1290 | if (sublen % BRCMF_SDALIGN) { | |
1291 | brcmf_dbg(ERROR, "sublen %d not multiple of %d\n", | |
1292 | sublen, BRCMF_SDALIGN); | |
1293 | usechain = false; | |
1294 | } | |
1295 | totlen += sublen; | |
1296 | ||
1297 | /* For last frame, adjust read len so total | |
1298 | is a block multiple */ | |
1299 | if (!dlen) { | |
1300 | sublen += | |
1301 | (roundup(totlen, bus->blocksize) - totlen); | |
1302 | totlen = roundup(totlen, bus->blocksize); | |
1303 | } | |
1304 | ||
1305 | /* Allocate/chain packet for next subframe */ | |
1306 | pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN); | |
1307 | if (pnext == NULL) { | |
1308 | brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n", | |
1309 | num, sublen); | |
1310 | break; | |
1311 | } | |
1312 | if (!pfirst) { | |
1313 | pfirst = plast = pnext; | |
1314 | } else { | |
1315 | plast->next = pnext; | |
1316 | plast = pnext; | |
1317 | } | |
1318 | ||
1319 | /* Adhere to start alignment requirements */ | |
1320 | pkt_align(pnext, sublen, BRCMF_SDALIGN); | |
1321 | } | |
1322 | ||
1323 | /* If all allocations succeeded, save packet chain | |
1324 | in bus structure */ | |
1325 | if (pnext) { | |
1326 | brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", | |
1327 | totlen, num); | |
1328 | if (BRCMF_GLOM_ON() && bus->nextlen && | |
1329 | totlen != bus->nextlen) { | |
1330 | brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", | |
1331 | bus->nextlen, totlen, rxseq); | |
1332 | } | |
1333 | bus->glom = pfirst; | |
1334 | pfirst = pnext = NULL; | |
1335 | } else { | |
1336 | if (pfirst) | |
1337 | brcmu_pkt_buf_free_skb(pfirst); | |
1338 | bus->glom = NULL; | |
1339 | num = 0; | |
1340 | } | |
1341 | ||
1342 | /* Done with descriptor packet */ | |
1343 | brcmu_pkt_buf_free_skb(bus->glomd); | |
1344 | bus->glomd = NULL; | |
1345 | bus->nextlen = 0; | |
1346 | } | |
1347 | ||
1348 | /* Ok -- either we just generated a packet chain, | |
1349 | or had one from before */ | |
1350 | if (bus->glom) { | |
1351 | if (BRCMF_GLOM_ON()) { | |
1352 | brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); | |
1353 | for (pnext = bus->glom; pnext; pnext = pnext->next) { | |
1354 | brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", | |
1355 | pnext, (u8 *) (pnext->data), | |
1356 | pnext->len, pnext->len); | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | pfirst = bus->glom; | |
1361 | dlen = (u16) brcmu_pkttotlen(pfirst); | |
1362 | ||
1363 | /* Do an SDIO read for the superframe. Configurable iovar to | |
1364 | * read directly into the chained packet, or allocate a large | |
1365 | * packet and and copy into the chain. | |
1366 | */ | |
1367 | if (usechain) { | |
1368 | errcode = brcmf_sdcard_recv_buf(bus->sdiodev, | |
1369 | bus->sdiodev->sbwad, | |
1370 | SDIO_FUNC_2, | |
1371 | F2SYNC, (u8 *) pfirst->data, dlen, | |
1372 | pfirst); | |
1373 | } else if (bus->dataptr) { | |
1374 | errcode = brcmf_sdcard_recv_buf(bus->sdiodev, | |
1375 | bus->sdiodev->sbwad, | |
1376 | SDIO_FUNC_2, | |
1377 | F2SYNC, bus->dataptr, dlen, | |
1378 | NULL); | |
20e5ca16 | 1379 | sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen); |
5b435de0 AS |
1380 | if (sublen != dlen) { |
1381 | brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n", | |
1382 | dlen, sublen); | |
1383 | errcode = -1; | |
1384 | } | |
1385 | pnext = NULL; | |
1386 | } else { | |
1387 | brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n", | |
1388 | dlen); | |
1389 | errcode = -1; | |
1390 | } | |
1391 | bus->f2rxdata++; | |
1392 | ||
1393 | /* On failure, kill the superframe, allow a couple retries */ | |
1394 | if (errcode < 0) { | |
1395 | brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n", | |
1396 | dlen, errcode); | |
1397 | bus->drvr->rx_errors++; | |
1398 | ||
1399 | if (bus->glomerr++ < 3) { | |
1400 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1401 | } else { | |
1402 | bus->glomerr = 0; | |
1403 | brcmf_sdbrcm_rxfail(bus, true, false); | |
1404 | brcmu_pkt_buf_free_skb(bus->glom); | |
1405 | bus->rxglomfail++; | |
1406 | bus->glom = NULL; | |
1407 | } | |
1408 | return 0; | |
1409 | } | |
1410 | #ifdef BCMDBG | |
1411 | if (BRCMF_GLOM_ON()) { | |
1412 | printk(KERN_DEBUG "SUPERFRAME:\n"); | |
1413 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
1414 | pfirst->data, min_t(int, pfirst->len, 48)); | |
1415 | } | |
1416 | #endif | |
1417 | ||
1418 | /* Validate the superframe header */ | |
1419 | dptr = (u8 *) (pfirst->data); | |
1420 | sublen = get_unaligned_le16(dptr); | |
1421 | check = get_unaligned_le16(dptr + sizeof(u16)); | |
1422 | ||
1423 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
1424 | seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1425 | bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET]; | |
1426 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
1427 | brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n", | |
1428 | bus->nextlen, seq); | |
1429 | bus->nextlen = 0; | |
1430 | } | |
1431 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1432 | txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1433 | ||
1434 | errcode = 0; | |
1435 | if ((u16)~(sublen ^ check)) { | |
1436 | brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n", | |
1437 | sublen, check); | |
1438 | errcode = -1; | |
1439 | } else if (roundup(sublen, bus->blocksize) != dlen) { | |
1440 | brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n", | |
1441 | sublen, roundup(sublen, bus->blocksize), | |
1442 | dlen); | |
1443 | errcode = -1; | |
1444 | } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) != | |
1445 | SDPCM_GLOM_CHANNEL) { | |
1446 | brcmf_dbg(ERROR, "(superframe): bad channel %d\n", | |
1447 | SDPCM_PACKET_CHANNEL( | |
1448 | &dptr[SDPCM_FRAMETAG_LEN])); | |
1449 | errcode = -1; | |
1450 | } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) { | |
1451 | brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n"); | |
1452 | errcode = -1; | |
1453 | } else if ((doff < SDPCM_HDRLEN) || | |
1454 | (doff > (pfirst->len - SDPCM_HDRLEN))) { | |
1455 | brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n", | |
1456 | doff, sublen, pfirst->len, SDPCM_HDRLEN); | |
1457 | errcode = -1; | |
1458 | } | |
1459 | ||
1460 | /* Check sequence number of superframe SW header */ | |
1461 | if (rxseq != seq) { | |
1462 | brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n", | |
1463 | seq, rxseq); | |
1464 | bus->rx_badseq++; | |
1465 | rxseq = seq; | |
1466 | } | |
1467 | ||
1468 | /* Check window for sanity */ | |
1469 | if ((u8) (txmax - bus->tx_seq) > 0x40) { | |
1470 | brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n", | |
1471 | txmax, bus->tx_seq); | |
1472 | txmax = bus->tx_seq + 2; | |
1473 | } | |
1474 | bus->tx_max = txmax; | |
1475 | ||
1476 | /* Remove superframe header, remember offset */ | |
1477 | skb_pull(pfirst, doff); | |
1478 | sfdoff = doff; | |
1479 | ||
1480 | /* Validate all the subframe headers */ | |
1481 | for (num = 0, pnext = pfirst; pnext && !errcode; | |
1482 | num++, pnext = pnext->next) { | |
1483 | dptr = (u8 *) (pnext->data); | |
1484 | dlen = (u16) (pnext->len); | |
1485 | sublen = get_unaligned_le16(dptr); | |
1486 | check = get_unaligned_le16(dptr + sizeof(u16)); | |
1487 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
1488 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1489 | #ifdef BCMDBG | |
1490 | if (BRCMF_GLOM_ON()) { | |
1491 | printk(KERN_DEBUG "subframe:\n"); | |
1492 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
1493 | dptr, 32); | |
1494 | } | |
1495 | #endif | |
1496 | ||
1497 | if ((u16)~(sublen ^ check)) { | |
1498 | brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n", | |
1499 | num, sublen, check); | |
1500 | errcode = -1; | |
1501 | } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) { | |
1502 | brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n", | |
1503 | num, sublen, dlen); | |
1504 | errcode = -1; | |
1505 | } else if ((chan != SDPCM_DATA_CHANNEL) && | |
1506 | (chan != SDPCM_EVENT_CHANNEL)) { | |
1507 | brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n", | |
1508 | num, chan); | |
1509 | errcode = -1; | |
1510 | } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) { | |
1511 | brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n", | |
1512 | num, doff, sublen, SDPCM_HDRLEN); | |
1513 | errcode = -1; | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | if (errcode) { | |
1518 | /* Terminate frame on error, request | |
1519 | a couple retries */ | |
1520 | if (bus->glomerr++ < 3) { | |
1521 | /* Restore superframe header space */ | |
1522 | skb_push(pfirst, sfdoff); | |
1523 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1524 | } else { | |
1525 | bus->glomerr = 0; | |
1526 | brcmf_sdbrcm_rxfail(bus, true, false); | |
1527 | brcmu_pkt_buf_free_skb(bus->glom); | |
1528 | bus->rxglomfail++; | |
1529 | bus->glom = NULL; | |
1530 | } | |
1531 | bus->nextlen = 0; | |
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | /* Basic SD framing looks ok - process each packet (header) */ | |
1536 | save_pfirst = pfirst; | |
1537 | bus->glom = NULL; | |
1538 | plast = NULL; | |
1539 | ||
1540 | for (num = 0; pfirst; rxseq++, pfirst = pnext) { | |
1541 | pnext = pfirst->next; | |
1542 | pfirst->next = NULL; | |
1543 | ||
1544 | dptr = (u8 *) (pfirst->data); | |
1545 | sublen = get_unaligned_le16(dptr); | |
1546 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
1547 | seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1548 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1549 | ||
1550 | brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n", | |
1551 | num, pfirst, pfirst->data, | |
1552 | pfirst->len, sublen, chan, seq); | |
1553 | ||
1554 | /* precondition: chan == SDPCM_DATA_CHANNEL || | |
1555 | chan == SDPCM_EVENT_CHANNEL */ | |
1556 | ||
1557 | if (rxseq != seq) { | |
1558 | brcmf_dbg(GLOM, "rx_seq %d, expected %d\n", | |
1559 | seq, rxseq); | |
1560 | bus->rx_badseq++; | |
1561 | rxseq = seq; | |
1562 | } | |
1563 | #ifdef BCMDBG | |
1564 | if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) { | |
1565 | printk(KERN_DEBUG "Rx Subframe Data:\n"); | |
1566 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
1567 | dptr, dlen); | |
1568 | } | |
1569 | #endif | |
1570 | ||
1571 | __skb_trim(pfirst, sublen); | |
1572 | skb_pull(pfirst, doff); | |
1573 | ||
1574 | if (pfirst->len == 0) { | |
1575 | brcmu_pkt_buf_free_skb(pfirst); | |
1576 | if (plast) | |
1577 | plast->next = pnext; | |
1578 | else | |
1579 | save_pfirst = pnext; | |
1580 | ||
1581 | continue; | |
1582 | } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, | |
1583 | pfirst) != 0) { | |
1584 | brcmf_dbg(ERROR, "rx protocol error\n"); | |
1585 | bus->drvr->rx_errors++; | |
1586 | brcmu_pkt_buf_free_skb(pfirst); | |
1587 | if (plast) | |
1588 | plast->next = pnext; | |
1589 | else | |
1590 | save_pfirst = pnext; | |
1591 | ||
1592 | continue; | |
1593 | } | |
1594 | ||
1595 | /* this packet will go up, link back into | |
1596 | chain and count it */ | |
1597 | pfirst->next = pnext; | |
1598 | plast = pfirst; | |
1599 | num++; | |
1600 | ||
1601 | #ifdef BCMDBG | |
1602 | if (BRCMF_GLOM_ON()) { | |
1603 | brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", | |
1604 | num, pfirst, pfirst->data, | |
1605 | pfirst->len, pfirst->next, | |
1606 | pfirst->prev); | |
1607 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
1608 | pfirst->data, | |
1609 | min_t(int, pfirst->len, 32)); | |
1610 | } | |
1611 | #endif /* BCMDBG */ | |
1612 | } | |
1613 | if (num) { | |
1614 | up(&bus->sdsem); | |
1615 | brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num); | |
1616 | down(&bus->sdsem); | |
1617 | } | |
1618 | ||
1619 | bus->rxglomframes++; | |
1620 | bus->rxglompkts += num; | |
1621 | } | |
1622 | return num; | |
1623 | } | |
1624 | ||
1625 | static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition, | |
1626 | bool *pending) | |
1627 | { | |
1628 | DECLARE_WAITQUEUE(wait, current); | |
1629 | int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT); | |
1630 | ||
1631 | /* Wait until control frame is available */ | |
1632 | add_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1633 | set_current_state(TASK_INTERRUPTIBLE); | |
1634 | ||
1635 | while (!(*condition) && (!signal_pending(current) && timeout)) | |
1636 | timeout = schedule_timeout(timeout); | |
1637 | ||
1638 | if (signal_pending(current)) | |
1639 | *pending = true; | |
1640 | ||
1641 | set_current_state(TASK_RUNNING); | |
1642 | remove_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1643 | ||
1644 | return timeout; | |
1645 | } | |
1646 | ||
1647 | static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus) | |
1648 | { | |
1649 | if (waitqueue_active(&bus->dcmd_resp_wait)) | |
1650 | wake_up_interruptible(&bus->dcmd_resp_wait); | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | static void | |
1655 | brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff) | |
1656 | { | |
1657 | uint rdlen, pad; | |
1658 | ||
1659 | int sdret; | |
1660 | ||
1661 | brcmf_dbg(TRACE, "Enter\n"); | |
1662 | ||
1663 | /* Set rxctl for frame (w/optional alignment) */ | |
1664 | bus->rxctl = bus->rxbuf; | |
1665 | bus->rxctl += BRCMF_FIRSTREAD; | |
1666 | pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN); | |
1667 | if (pad) | |
1668 | bus->rxctl += (BRCMF_SDALIGN - pad); | |
1669 | bus->rxctl -= BRCMF_FIRSTREAD; | |
1670 | ||
1671 | /* Copy the already-read portion over */ | |
1672 | memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD); | |
1673 | if (len <= BRCMF_FIRSTREAD) | |
1674 | goto gotpkt; | |
1675 | ||
1676 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
1677 | rdlen = len - BRCMF_FIRSTREAD; | |
1678 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
1679 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1680 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
1681 | ((len + pad) < bus->drvr->maxctl)) | |
1682 | rdlen += pad; | |
1683 | } else if (rdlen % BRCMF_SDALIGN) { | |
1684 | rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN); | |
1685 | } | |
1686 | ||
1687 | /* Satisfy length-alignment requirements */ | |
1688 | if (rdlen & (ALIGNMENT - 1)) | |
1689 | rdlen = roundup(rdlen, ALIGNMENT); | |
1690 | ||
1691 | /* Drop if the read is too big or it exceeds our maximum */ | |
1692 | if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) { | |
1693 | brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n", | |
1694 | rdlen, bus->drvr->maxctl); | |
1695 | bus->drvr->rx_errors++; | |
1696 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1697 | goto done; | |
1698 | } | |
1699 | ||
1700 | if ((len - doff) > bus->drvr->maxctl) { | |
1701 | brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", | |
1702 | len, len - doff, bus->drvr->maxctl); | |
1703 | bus->drvr->rx_errors++; | |
1704 | bus->rx_toolong++; | |
1705 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1706 | goto done; | |
1707 | } | |
1708 | ||
1709 | /* Read remainder of frame body into the rxctl buffer */ | |
1710 | sdret = brcmf_sdcard_recv_buf(bus->sdiodev, | |
1711 | bus->sdiodev->sbwad, | |
1712 | SDIO_FUNC_2, | |
1713 | F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen, | |
1714 | NULL); | |
1715 | bus->f2rxdata++; | |
1716 | ||
1717 | /* Control frame failures need retransmission */ | |
1718 | if (sdret < 0) { | |
1719 | brcmf_dbg(ERROR, "read %d control bytes failed: %d\n", | |
1720 | rdlen, sdret); | |
1721 | bus->rxc_errors++; | |
1722 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1723 | goto done; | |
1724 | } | |
1725 | ||
1726 | gotpkt: | |
1727 | ||
1728 | #ifdef BCMDBG | |
1729 | if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) { | |
1730 | printk(KERN_DEBUG "RxCtrl:\n"); | |
1731 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len); | |
1732 | } | |
1733 | #endif | |
1734 | ||
1735 | /* Point to valid data and indicate its length */ | |
1736 | bus->rxctl += doff; | |
1737 | bus->rxlen = len - doff; | |
1738 | ||
1739 | done: | |
1740 | /* Awake any waiters */ | |
1741 | brcmf_sdbrcm_dcmd_resp_wake(bus); | |
1742 | } | |
1743 | ||
1744 | /* Pad read to blocksize for efficiency */ | |
1745 | static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen) | |
1746 | { | |
1747 | if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { | |
1748 | *pad = bus->blocksize - (*rdlen % bus->blocksize); | |
1749 | if (*pad <= bus->roundup && *pad < bus->blocksize && | |
1750 | *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) | |
1751 | *rdlen += *pad; | |
1752 | } else if (*rdlen % BRCMF_SDALIGN) { | |
1753 | *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN); | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | static void | |
1758 | brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen, | |
1759 | struct sk_buff **pkt, u8 **rxbuf) | |
1760 | { | |
1761 | int sdret; /* Return code from calls */ | |
1762 | ||
1763 | *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN); | |
1764 | if (*pkt == NULL) | |
1765 | return; | |
1766 | ||
1767 | pkt_align(*pkt, rdlen, BRCMF_SDALIGN); | |
1768 | *rxbuf = (u8 *) ((*pkt)->data); | |
1769 | /* Read the entire frame */ | |
1770 | sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad, | |
1771 | SDIO_FUNC_2, F2SYNC, | |
1772 | *rxbuf, rdlen, *pkt); | |
1773 | bus->f2rxdata++; | |
1774 | ||
1775 | if (sdret < 0) { | |
1776 | brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n", | |
1777 | rdlen, sdret); | |
1778 | brcmu_pkt_buf_free_skb(*pkt); | |
1779 | bus->drvr->rx_errors++; | |
1780 | /* Force retry w/normal header read. | |
1781 | * Don't attempt NAK for | |
1782 | * gSPI | |
1783 | */ | |
1784 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1785 | *pkt = NULL; | |
1786 | } | |
1787 | } | |
1788 | ||
1789 | /* Checks the header */ | |
1790 | static int | |
1791 | brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf, | |
1792 | u8 rxseq, u16 nextlen, u16 *len) | |
1793 | { | |
1794 | u16 check; | |
1795 | bool len_consistent; /* Result of comparing readahead len and | |
1796 | len from hw-hdr */ | |
1797 | ||
1798 | memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN); | |
1799 | ||
1800 | /* Extract hardware header fields */ | |
1801 | *len = get_unaligned_le16(bus->rxhdr); | |
1802 | check = get_unaligned_le16(bus->rxhdr + sizeof(u16)); | |
1803 | ||
1804 | /* All zeros means readahead info was bad */ | |
1805 | if (!(*len | check)) { | |
1806 | brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n"); | |
1807 | goto fail; | |
1808 | } | |
1809 | ||
1810 | /* Validate check bytes */ | |
1811 | if ((u16)~(*len ^ check)) { | |
1812 | brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n", | |
1813 | nextlen, *len, check); | |
1814 | bus->rx_badhdr++; | |
1815 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1816 | goto fail; | |
1817 | } | |
1818 | ||
1819 | /* Validate frame length */ | |
1820 | if (*len < SDPCM_HDRLEN) { | |
1821 | brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n", | |
1822 | *len); | |
1823 | goto fail; | |
1824 | } | |
1825 | ||
1826 | /* Check for consistency with readahead info */ | |
1827 | len_consistent = (nextlen != (roundup(*len, 16) >> 4)); | |
1828 | if (len_consistent) { | |
1829 | /* Mismatch, force retry w/normal | |
1830 | header (may be >4K) */ | |
1831 | brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n", | |
1832 | nextlen, *len, roundup(*len, 16), | |
1833 | rxseq); | |
1834 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1835 | goto fail; | |
1836 | } | |
1837 | ||
1838 | return 0; | |
1839 | ||
1840 | fail: | |
1841 | brcmf_sdbrcm_pktfree2(bus, pkt); | |
1842 | return -EINVAL; | |
1843 | } | |
1844 | ||
1845 | /* Return true if there may be more frames to read */ | |
1846 | static uint | |
1847 | brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished) | |
1848 | { | |
1849 | u16 len, check; /* Extracted hardware header fields */ | |
1850 | u8 chan, seq, doff; /* Extracted software header fields */ | |
1851 | u8 fcbits; /* Extracted fcbits from software header */ | |
1852 | ||
1853 | struct sk_buff *pkt; /* Packet for event or data frames */ | |
1854 | u16 pad; /* Number of pad bytes to read */ | |
1855 | u16 rdlen; /* Total number of bytes to read */ | |
1856 | u8 rxseq; /* Next sequence number to expect */ | |
1857 | uint rxleft = 0; /* Remaining number of frames allowed */ | |
1858 | int sdret; /* Return code from calls */ | |
1859 | u8 txmax; /* Maximum tx sequence offered */ | |
1860 | u8 *rxbuf; | |
1861 | int ifidx = 0; | |
1862 | uint rxcount = 0; /* Total frames read */ | |
1863 | ||
1864 | brcmf_dbg(TRACE, "Enter\n"); | |
1865 | ||
1866 | /* Not finished unless we encounter no more frames indication */ | |
1867 | *finished = false; | |
1868 | ||
1869 | for (rxseq = bus->rx_seq, rxleft = maxframes; | |
1870 | !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN; | |
1871 | rxseq++, rxleft--) { | |
1872 | ||
1873 | /* Handle glomming separately */ | |
1874 | if (bus->glom || bus->glomd) { | |
1875 | u8 cnt; | |
1876 | brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", | |
1877 | bus->glomd, bus->glom); | |
1878 | cnt = brcmf_sdbrcm_rxglom(bus, rxseq); | |
1879 | brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); | |
1880 | rxseq += cnt - 1; | |
1881 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; | |
1882 | continue; | |
1883 | } | |
1884 | ||
1885 | /* Try doing single read if we can */ | |
1886 | if (bus->nextlen) { | |
1887 | u16 nextlen = bus->nextlen; | |
1888 | bus->nextlen = 0; | |
1889 | ||
1890 | rdlen = len = nextlen << 4; | |
1891 | brcmf_pad(bus, &pad, &rdlen); | |
1892 | ||
1893 | /* | |
1894 | * After the frame is received we have to | |
1895 | * distinguish whether it is data | |
1896 | * or non-data frame. | |
1897 | */ | |
1898 | brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf); | |
1899 | if (pkt == NULL) { | |
1900 | /* Give up on data, request rtx of events */ | |
1901 | brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n", | |
1902 | len, rdlen, rxseq); | |
1903 | continue; | |
1904 | } | |
1905 | ||
1906 | if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen, | |
1907 | &len) < 0) | |
1908 | continue; | |
1909 | ||
1910 | /* Extract software header fields */ | |
1911 | chan = SDPCM_PACKET_CHANNEL( | |
1912 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1913 | seq = SDPCM_PACKET_SEQUENCE( | |
1914 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1915 | doff = SDPCM_DOFFSET_VALUE( | |
1916 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1917 | txmax = SDPCM_WINDOW_VALUE( | |
1918 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1919 | ||
1920 | bus->nextlen = | |
1921 | bus->rxhdr[SDPCM_FRAMETAG_LEN + | |
1922 | SDPCM_NEXTLEN_OFFSET]; | |
1923 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
1924 | brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n", | |
1925 | bus->nextlen, seq); | |
1926 | bus->nextlen = 0; | |
1927 | } | |
1928 | ||
1929 | bus->drvr->rx_readahead_cnt++; | |
1930 | ||
1931 | /* Handle Flow Control */ | |
1932 | fcbits = SDPCM_FCMASK_VALUE( | |
1933 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1934 | ||
1935 | if (bus->flowcontrol != fcbits) { | |
1936 | if (~bus->flowcontrol & fcbits) | |
1937 | bus->fc_xoff++; | |
1938 | ||
1939 | if (bus->flowcontrol & ~fcbits) | |
1940 | bus->fc_xon++; | |
1941 | ||
1942 | bus->fc_rcvd++; | |
1943 | bus->flowcontrol = fcbits; | |
1944 | } | |
1945 | ||
1946 | /* Check and update sequence number */ | |
1947 | if (rxseq != seq) { | |
1948 | brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n", | |
1949 | seq, rxseq); | |
1950 | bus->rx_badseq++; | |
1951 | rxseq = seq; | |
1952 | } | |
1953 | ||
1954 | /* Check window for sanity */ | |
1955 | if ((u8) (txmax - bus->tx_seq) > 0x40) { | |
1956 | brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n", | |
1957 | txmax, bus->tx_seq); | |
1958 | txmax = bus->tx_seq + 2; | |
1959 | } | |
1960 | bus->tx_max = txmax; | |
1961 | ||
1962 | #ifdef BCMDBG | |
1963 | if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) { | |
1964 | printk(KERN_DEBUG "Rx Data:\n"); | |
1965 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
1966 | rxbuf, len); | |
1967 | } else if (BRCMF_HDRS_ON()) { | |
1968 | printk(KERN_DEBUG "RxHdr:\n"); | |
1969 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
1970 | bus->rxhdr, SDPCM_HDRLEN); | |
1971 | } | |
1972 | #endif | |
1973 | ||
1974 | if (chan == SDPCM_CONTROL_CHANNEL) { | |
1975 | brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n", | |
1976 | seq); | |
1977 | /* Force retry w/normal header read */ | |
1978 | bus->nextlen = 0; | |
1979 | brcmf_sdbrcm_rxfail(bus, false, true); | |
1980 | brcmf_sdbrcm_pktfree2(bus, pkt); | |
1981 | continue; | |
1982 | } | |
1983 | ||
1984 | /* Validate data offset */ | |
1985 | if ((doff < SDPCM_HDRLEN) || (doff > len)) { | |
1986 | brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n", | |
1987 | doff, len, SDPCM_HDRLEN); | |
1988 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1989 | brcmf_sdbrcm_pktfree2(bus, pkt); | |
1990 | continue; | |
1991 | } | |
1992 | ||
1993 | /* All done with this one -- now deliver the packet */ | |
1994 | goto deliver; | |
1995 | } | |
1996 | ||
1997 | /* Read frame header (hardware and software) */ | |
1998 | sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad, | |
1999 | SDIO_FUNC_2, F2SYNC, bus->rxhdr, | |
2000 | BRCMF_FIRSTREAD, NULL); | |
2001 | bus->f2rxhdrs++; | |
2002 | ||
2003 | if (sdret < 0) { | |
2004 | brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret); | |
2005 | bus->rx_hdrfail++; | |
2006 | brcmf_sdbrcm_rxfail(bus, true, true); | |
2007 | continue; | |
2008 | } | |
2009 | #ifdef BCMDBG | |
2010 | if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) { | |
2011 | printk(KERN_DEBUG "RxHdr:\n"); | |
2012 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
2013 | bus->rxhdr, SDPCM_HDRLEN); | |
2014 | } | |
2015 | #endif | |
2016 | ||
2017 | /* Extract hardware header fields */ | |
2018 | len = get_unaligned_le16(bus->rxhdr); | |
2019 | check = get_unaligned_le16(bus->rxhdr + sizeof(u16)); | |
2020 | ||
2021 | /* All zeros means no more frames */ | |
2022 | if (!(len | check)) { | |
2023 | *finished = true; | |
2024 | break; | |
2025 | } | |
2026 | ||
2027 | /* Validate check bytes */ | |
2028 | if ((u16) ~(len ^ check)) { | |
2029 | brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n", | |
2030 | len, check); | |
2031 | bus->rx_badhdr++; | |
2032 | brcmf_sdbrcm_rxfail(bus, false, false); | |
2033 | continue; | |
2034 | } | |
2035 | ||
2036 | /* Validate frame length */ | |
2037 | if (len < SDPCM_HDRLEN) { | |
2038 | brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len); | |
2039 | continue; | |
2040 | } | |
2041 | ||
2042 | /* Extract software header fields */ | |
2043 | chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
2044 | seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
2045 | doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
2046 | txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
2047 | ||
2048 | /* Validate data offset */ | |
2049 | if ((doff < SDPCM_HDRLEN) || (doff > len)) { | |
2050 | brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n", | |
2051 | doff, len, SDPCM_HDRLEN, seq); | |
2052 | bus->rx_badhdr++; | |
2053 | brcmf_sdbrcm_rxfail(bus, false, false); | |
2054 | continue; | |
2055 | } | |
2056 | ||
2057 | /* Save the readahead length if there is one */ | |
2058 | bus->nextlen = | |
2059 | bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET]; | |
2060 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
2061 | brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n", | |
2062 | bus->nextlen, seq); | |
2063 | bus->nextlen = 0; | |
2064 | } | |
2065 | ||
2066 | /* Handle Flow Control */ | |
2067 | fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
2068 | ||
2069 | if (bus->flowcontrol != fcbits) { | |
2070 | if (~bus->flowcontrol & fcbits) | |
2071 | bus->fc_xoff++; | |
2072 | ||
2073 | if (bus->flowcontrol & ~fcbits) | |
2074 | bus->fc_xon++; | |
2075 | ||
2076 | bus->fc_rcvd++; | |
2077 | bus->flowcontrol = fcbits; | |
2078 | } | |
2079 | ||
2080 | /* Check and update sequence number */ | |
2081 | if (rxseq != seq) { | |
2082 | brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq); | |
2083 | bus->rx_badseq++; | |
2084 | rxseq = seq; | |
2085 | } | |
2086 | ||
2087 | /* Check window for sanity */ | |
2088 | if ((u8) (txmax - bus->tx_seq) > 0x40) { | |
2089 | brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n", | |
2090 | txmax, bus->tx_seq); | |
2091 | txmax = bus->tx_seq + 2; | |
2092 | } | |
2093 | bus->tx_max = txmax; | |
2094 | ||
2095 | /* Call a separate function for control frames */ | |
2096 | if (chan == SDPCM_CONTROL_CHANNEL) { | |
2097 | brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff); | |
2098 | continue; | |
2099 | } | |
2100 | ||
2101 | /* precondition: chan is either SDPCM_DATA_CHANNEL, | |
2102 | SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or | |
2103 | SDPCM_GLOM_CHANNEL */ | |
2104 | ||
2105 | /* Length to read */ | |
2106 | rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0; | |
2107 | ||
2108 | /* May pad read to blocksize for efficiency */ | |
2109 | if (bus->roundup && bus->blocksize && | |
2110 | (rdlen > bus->blocksize)) { | |
2111 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
2112 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
2113 | ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ)) | |
2114 | rdlen += pad; | |
2115 | } else if (rdlen % BRCMF_SDALIGN) { | |
2116 | rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN); | |
2117 | } | |
2118 | ||
2119 | /* Satisfy length-alignment requirements */ | |
2120 | if (rdlen & (ALIGNMENT - 1)) | |
2121 | rdlen = roundup(rdlen, ALIGNMENT); | |
2122 | ||
2123 | if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) { | |
2124 | /* Too long -- skip this frame */ | |
2125 | brcmf_dbg(ERROR, "too long: len %d rdlen %d\n", | |
2126 | len, rdlen); | |
2127 | bus->drvr->rx_errors++; | |
2128 | bus->rx_toolong++; | |
2129 | brcmf_sdbrcm_rxfail(bus, false, false); | |
2130 | continue; | |
2131 | } | |
2132 | ||
2133 | pkt = brcmu_pkt_buf_get_skb(rdlen + | |
2134 | BRCMF_FIRSTREAD + BRCMF_SDALIGN); | |
2135 | if (!pkt) { | |
2136 | /* Give up on data, request rtx of events */ | |
2137 | brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n", | |
2138 | rdlen, chan); | |
2139 | bus->drvr->rx_dropped++; | |
2140 | brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan)); | |
2141 | continue; | |
2142 | } | |
2143 | ||
2144 | /* Leave room for what we already read, and align remainder */ | |
2145 | skb_pull(pkt, BRCMF_FIRSTREAD); | |
2146 | pkt_align(pkt, rdlen, BRCMF_SDALIGN); | |
2147 | ||
2148 | /* Read the remaining frame data */ | |
2149 | sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad, | |
2150 | SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)), | |
2151 | rdlen, pkt); | |
2152 | bus->f2rxdata++; | |
2153 | ||
2154 | if (sdret < 0) { | |
2155 | brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen, | |
2156 | ((chan == SDPCM_EVENT_CHANNEL) ? "event" | |
2157 | : ((chan == SDPCM_DATA_CHANNEL) ? "data" | |
2158 | : "test")), sdret); | |
2159 | brcmu_pkt_buf_free_skb(pkt); | |
2160 | bus->drvr->rx_errors++; | |
2161 | brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan)); | |
2162 | continue; | |
2163 | } | |
2164 | ||
2165 | /* Copy the already-read portion */ | |
2166 | skb_push(pkt, BRCMF_FIRSTREAD); | |
2167 | memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD); | |
2168 | ||
2169 | #ifdef BCMDBG | |
2170 | if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) { | |
2171 | printk(KERN_DEBUG "Rx Data:\n"); | |
2172 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
2173 | pkt->data, len); | |
2174 | } | |
2175 | #endif | |
2176 | ||
2177 | deliver: | |
2178 | /* Save superframe descriptor and allocate packet frame */ | |
2179 | if (chan == SDPCM_GLOM_CHANNEL) { | |
2180 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) { | |
2181 | brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", | |
2182 | len); | |
2183 | #ifdef BCMDBG | |
2184 | if (BRCMF_GLOM_ON()) { | |
2185 | printk(KERN_DEBUG "Glom Data:\n"); | |
2186 | print_hex_dump_bytes("", | |
2187 | DUMP_PREFIX_OFFSET, | |
2188 | pkt->data, len); | |
2189 | } | |
2190 | #endif | |
2191 | __skb_trim(pkt, len); | |
2192 | skb_pull(pkt, SDPCM_HDRLEN); | |
2193 | bus->glomd = pkt; | |
2194 | } else { | |
2195 | brcmf_dbg(ERROR, "%s: glom superframe w/o " | |
2196 | "descriptor!\n", __func__); | |
2197 | brcmf_sdbrcm_rxfail(bus, false, false); | |
2198 | } | |
2199 | continue; | |
2200 | } | |
2201 | ||
2202 | /* Fill in packet len and prio, deliver upward */ | |
2203 | __skb_trim(pkt, len); | |
2204 | skb_pull(pkt, doff); | |
2205 | ||
2206 | if (pkt->len == 0) { | |
2207 | brcmu_pkt_buf_free_skb(pkt); | |
2208 | continue; | |
2209 | } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) { | |
2210 | brcmf_dbg(ERROR, "rx protocol error\n"); | |
2211 | brcmu_pkt_buf_free_skb(pkt); | |
2212 | bus->drvr->rx_errors++; | |
2213 | continue; | |
2214 | } | |
2215 | ||
2216 | /* Unlock during rx call */ | |
2217 | up(&bus->sdsem); | |
2218 | brcmf_rx_frame(bus->drvr, ifidx, pkt, 1); | |
2219 | down(&bus->sdsem); | |
2220 | } | |
2221 | rxcount = maxframes - rxleft; | |
2222 | #ifdef BCMDBG | |
2223 | /* Message if we hit the limit */ | |
2224 | if (!rxleft) | |
2225 | brcmf_dbg(DATA, "hit rx limit of %d frames\n", | |
2226 | maxframes); | |
2227 | else | |
2228 | #endif /* BCMDBG */ | |
2229 | brcmf_dbg(DATA, "processed %d frames\n", rxcount); | |
2230 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
2231 | if (bus->rxskip) | |
2232 | rxseq--; | |
2233 | bus->rx_seq = rxseq; | |
2234 | ||
2235 | return rxcount; | |
2236 | } | |
2237 | ||
2238 | static int | |
2239 | brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags, | |
2240 | u8 *buf, uint nbytes, struct sk_buff *pkt) | |
2241 | { | |
2242 | return brcmf_sdcard_send_buf | |
2243 | (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt); | |
2244 | } | |
2245 | ||
2246 | static void | |
2247 | brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar) | |
2248 | { | |
2249 | up(&bus->sdsem); | |
2250 | wait_event_interruptible_timeout(bus->ctrl_wait, | |
2251 | (*lockvar == false), HZ * 2); | |
2252 | down(&bus->sdsem); | |
2253 | return; | |
2254 | } | |
2255 | ||
2256 | static void | |
2257 | brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus) | |
2258 | { | |
2259 | if (waitqueue_active(&bus->ctrl_wait)) | |
2260 | wake_up_interruptible(&bus->ctrl_wait); | |
2261 | return; | |
2262 | } | |
2263 | ||
2264 | /* Writes a HW/SW header into the packet and sends it. */ | |
2265 | /* Assumes: (a) header space already there, (b) caller holds lock */ | |
2266 | static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt, | |
2267 | uint chan, bool free_pkt) | |
2268 | { | |
2269 | int ret; | |
2270 | u8 *frame; | |
2271 | u16 len, pad = 0; | |
2272 | u32 swheader; | |
2273 | struct sk_buff *new; | |
2274 | int i; | |
2275 | ||
2276 | brcmf_dbg(TRACE, "Enter\n"); | |
2277 | ||
2278 | frame = (u8 *) (pkt->data); | |
2279 | ||
2280 | /* Add alignment padding, allocate new packet if needed */ | |
2281 | pad = ((unsigned long)frame % BRCMF_SDALIGN); | |
2282 | if (pad) { | |
2283 | if (skb_headroom(pkt) < pad) { | |
2284 | brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n", | |
2285 | skb_headroom(pkt), pad); | |
2286 | bus->drvr->tx_realloc++; | |
2287 | new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN); | |
2288 | if (!new) { | |
2289 | brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n", | |
2290 | pkt->len + BRCMF_SDALIGN); | |
2291 | ret = -ENOMEM; | |
2292 | goto done; | |
2293 | } | |
2294 | ||
2295 | pkt_align(new, pkt->len, BRCMF_SDALIGN); | |
2296 | memcpy(new->data, pkt->data, pkt->len); | |
2297 | if (free_pkt) | |
2298 | brcmu_pkt_buf_free_skb(pkt); | |
2299 | /* free the pkt if canned one is not used */ | |
2300 | free_pkt = true; | |
2301 | pkt = new; | |
2302 | frame = (u8 *) (pkt->data); | |
2303 | /* precondition: (frame % BRCMF_SDALIGN) == 0) */ | |
2304 | pad = 0; | |
2305 | } else { | |
2306 | skb_push(pkt, pad); | |
2307 | frame = (u8 *) (pkt->data); | |
2308 | /* precondition: pad + SDPCM_HDRLEN <= pkt->len */ | |
2309 | memset(frame, 0, pad + SDPCM_HDRLEN); | |
2310 | } | |
2311 | } | |
2312 | /* precondition: pad < BRCMF_SDALIGN */ | |
2313 | ||
2314 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ | |
2315 | len = (u16) (pkt->len); | |
2316 | *(__le16 *) frame = cpu_to_le16(len); | |
2317 | *(((__le16 *) frame) + 1) = cpu_to_le16(~len); | |
2318 | ||
2319 | /* Software tag: channel, sequence number, data offset */ | |
2320 | swheader = | |
2321 | ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq | | |
2322 | (((pad + | |
2323 | SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK); | |
2324 | ||
2325 | put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN); | |
2326 | put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader)); | |
2327 | ||
2328 | #ifdef BCMDBG | |
2329 | tx_packets[pkt->priority]++; | |
2330 | if (BRCMF_BYTES_ON() && | |
2331 | (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) || | |
2332 | (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) { | |
2333 | printk(KERN_DEBUG "Tx Frame:\n"); | |
2334 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len); | |
2335 | } else if (BRCMF_HDRS_ON()) { | |
2336 | printk(KERN_DEBUG "TxHdr:\n"); | |
2337 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
2338 | frame, min_t(u16, len, 16)); | |
2339 | } | |
2340 | #endif | |
2341 | ||
2342 | /* Raise len to next SDIO block to eliminate tail command */ | |
2343 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2344 | u16 pad = bus->blocksize - (len % bus->blocksize); | |
2345 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) | |
2346 | len += pad; | |
2347 | } else if (len % BRCMF_SDALIGN) { | |
2348 | len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN); | |
2349 | } | |
2350 | ||
2351 | /* Some controllers have trouble with odd bytes -- round to even */ | |
2352 | if (len & (ALIGNMENT - 1)) | |
2353 | len = roundup(len, ALIGNMENT); | |
2354 | ||
2355 | ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad, | |
2356 | SDIO_FUNC_2, F2SYNC, frame, | |
2357 | len, pkt); | |
2358 | bus->f2txdata++; | |
2359 | ||
2360 | if (ret < 0) { | |
2361 | /* On failure, abort the command and terminate the frame */ | |
2362 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2363 | ret); | |
2364 | bus->tx_sderrs++; | |
2365 | ||
2366 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2367 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2368 | SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, | |
2369 | NULL); | |
2370 | bus->f1regdata++; | |
2371 | ||
2372 | for (i = 0; i < 3; i++) { | |
2373 | u8 hi, lo; | |
2374 | hi = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2375 | SDIO_FUNC_1, | |
2376 | SBSDIO_FUNC1_WFRAMEBCHI, | |
2377 | NULL); | |
2378 | lo = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2379 | SDIO_FUNC_1, | |
2380 | SBSDIO_FUNC1_WFRAMEBCLO, | |
2381 | NULL); | |
2382 | bus->f1regdata += 2; | |
2383 | if ((hi == 0) && (lo == 0)) | |
2384 | break; | |
2385 | } | |
2386 | ||
2387 | } | |
2388 | if (ret == 0) | |
2389 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; | |
2390 | ||
2391 | done: | |
2392 | /* restore pkt buffer pointer before calling tx complete routine */ | |
2393 | skb_pull(pkt, SDPCM_HDRLEN + pad); | |
2394 | up(&bus->sdsem); | |
2395 | brcmf_txcomplete(bus->drvr, pkt, ret != 0); | |
2396 | down(&bus->sdsem); | |
2397 | ||
2398 | if (free_pkt) | |
2399 | brcmu_pkt_buf_free_skb(pkt); | |
2400 | ||
2401 | return ret; | |
2402 | } | |
2403 | ||
2404 | static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes) | |
2405 | { | |
2406 | struct sk_buff *pkt; | |
2407 | u32 intstatus = 0; | |
2408 | uint retries = 0; | |
2409 | int ret = 0, prec_out; | |
2410 | uint cnt = 0; | |
2411 | uint datalen; | |
2412 | u8 tx_prec_map; | |
2413 | ||
2414 | struct brcmf_pub *drvr = bus->drvr; | |
2415 | ||
2416 | brcmf_dbg(TRACE, "Enter\n"); | |
2417 | ||
2418 | tx_prec_map = ~bus->flowcontrol; | |
2419 | ||
2420 | /* Send frames until the limit or some other event */ | |
2421 | for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) { | |
2422 | spin_lock_bh(&bus->txqlock); | |
2423 | pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out); | |
2424 | if (pkt == NULL) { | |
2425 | spin_unlock_bh(&bus->txqlock); | |
2426 | break; | |
2427 | } | |
2428 | spin_unlock_bh(&bus->txqlock); | |
2429 | datalen = pkt->len - SDPCM_HDRLEN; | |
2430 | ||
2431 | ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true); | |
2432 | if (ret) | |
2433 | bus->drvr->tx_errors++; | |
2434 | else | |
2435 | bus->drvr->dstats.tx_bytes += datalen; | |
2436 | ||
2437 | /* In poll mode, need to check for other events */ | |
2438 | if (!bus->intr && cnt) { | |
2439 | /* Check device status, signal pending interrupt */ | |
2440 | r_sdreg32(bus, &intstatus, | |
2441 | offsetof(struct sdpcmd_regs, intstatus), | |
2442 | &retries); | |
2443 | bus->f2txdata++; | |
2444 | if (brcmf_sdcard_regfail(bus->sdiodev)) | |
2445 | break; | |
2446 | if (intstatus & bus->hostintmask) | |
2447 | bus->ipend = true; | |
2448 | } | |
2449 | } | |
2450 | ||
2451 | /* Deflow-control stack if needed */ | |
2452 | if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) && | |
2453 | drvr->txoff && (pktq_len(&bus->txq) < TXLOW)) | |
2454 | brcmf_txflowcontrol(drvr, 0, OFF); | |
2455 | ||
2456 | return cnt; | |
2457 | } | |
2458 | ||
2459 | static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus) | |
2460 | { | |
2461 | u32 intstatus, newstatus = 0; | |
2462 | uint retries = 0; | |
2463 | uint rxlimit = bus->rxbound; /* Rx frames to read before resched */ | |
2464 | uint txlimit = bus->txbound; /* Tx frames to send before resched */ | |
2465 | uint framecnt = 0; /* Temporary counter of tx/rx frames */ | |
2466 | bool rxdone = true; /* Flag for no more read data */ | |
2467 | bool resched = false; /* Flag indicating resched wanted */ | |
2468 | ||
2469 | brcmf_dbg(TRACE, "Enter\n"); | |
2470 | ||
2471 | /* Start with leftover status bits */ | |
2472 | intstatus = bus->intstatus; | |
2473 | ||
2474 | down(&bus->sdsem); | |
2475 | ||
2476 | /* If waiting for HTAVAIL, check status */ | |
2477 | if (bus->clkstate == CLK_PENDING) { | |
2478 | int err; | |
2479 | u8 clkctl, devctl = 0; | |
2480 | ||
2481 | #ifdef BCMDBG | |
2482 | /* Check for inconsistent device control */ | |
2483 | devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2484 | SBSDIO_DEVICE_CTL, &err); | |
2485 | if (err) { | |
2486 | brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err); | |
2487 | bus->drvr->busstate = BRCMF_BUS_DOWN; | |
2488 | } | |
2489 | #endif /* BCMDBG */ | |
2490 | ||
2491 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
2492 | clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2493 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
2494 | if (err) { | |
2495 | brcmf_dbg(ERROR, "error reading CSR: %d\n", | |
2496 | err); | |
2497 | bus->drvr->busstate = BRCMF_BUS_DOWN; | |
2498 | } | |
2499 | ||
2500 | brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", | |
2501 | devctl, clkctl); | |
2502 | ||
2503 | if (SBSDIO_HTAV(clkctl)) { | |
2504 | devctl = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2505 | SDIO_FUNC_1, | |
2506 | SBSDIO_DEVICE_CTL, &err); | |
2507 | if (err) { | |
2508 | brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", | |
2509 | err); | |
2510 | bus->drvr->busstate = BRCMF_BUS_DOWN; | |
2511 | } | |
2512 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
2513 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2514 | SBSDIO_DEVICE_CTL, devctl, &err); | |
2515 | if (err) { | |
2516 | brcmf_dbg(ERROR, "error writing DEVCTL: %d\n", | |
2517 | err); | |
2518 | bus->drvr->busstate = BRCMF_BUS_DOWN; | |
2519 | } | |
2520 | bus->clkstate = CLK_AVAIL; | |
2521 | } else { | |
2522 | goto clkwait; | |
2523 | } | |
2524 | } | |
2525 | ||
2526 | bus_wake(bus); | |
2527 | ||
2528 | /* Make sure backplane clock is on */ | |
2529 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true); | |
2530 | if (bus->clkstate == CLK_PENDING) | |
2531 | goto clkwait; | |
2532 | ||
2533 | /* Pending interrupt indicates new device status */ | |
2534 | if (bus->ipend) { | |
2535 | bus->ipend = false; | |
2536 | r_sdreg32(bus, &newstatus, | |
2537 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
2538 | bus->f1regdata++; | |
2539 | if (brcmf_sdcard_regfail(bus->sdiodev)) | |
2540 | newstatus = 0; | |
2541 | newstatus &= bus->hostintmask; | |
2542 | bus->fcstate = !!(newstatus & I_HMB_FC_STATE); | |
2543 | if (newstatus) { | |
2544 | w_sdreg32(bus, newstatus, | |
2545 | offsetof(struct sdpcmd_regs, intstatus), | |
2546 | &retries); | |
2547 | bus->f1regdata++; | |
2548 | } | |
2549 | } | |
2550 | ||
2551 | /* Merge new bits with previous */ | |
2552 | intstatus |= newstatus; | |
2553 | bus->intstatus = 0; | |
2554 | ||
2555 | /* Handle flow-control change: read new state in case our ack | |
2556 | * crossed another change interrupt. If change still set, assume | |
2557 | * FC ON for safety, let next loop through do the debounce. | |
2558 | */ | |
2559 | if (intstatus & I_HMB_FC_CHANGE) { | |
2560 | intstatus &= ~I_HMB_FC_CHANGE; | |
2561 | w_sdreg32(bus, I_HMB_FC_CHANGE, | |
2562 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
2563 | ||
2564 | r_sdreg32(bus, &newstatus, | |
2565 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
2566 | bus->f1regdata += 2; | |
2567 | bus->fcstate = | |
2568 | !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)); | |
2569 | intstatus |= (newstatus & bus->hostintmask); | |
2570 | } | |
2571 | ||
2572 | /* Handle host mailbox indication */ | |
2573 | if (intstatus & I_HMB_HOST_INT) { | |
2574 | intstatus &= ~I_HMB_HOST_INT; | |
2575 | intstatus |= brcmf_sdbrcm_hostmail(bus); | |
2576 | } | |
2577 | ||
2578 | /* Generally don't ask for these, can get CRC errors... */ | |
2579 | if (intstatus & I_WR_OOSYNC) { | |
2580 | brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n"); | |
2581 | intstatus &= ~I_WR_OOSYNC; | |
2582 | } | |
2583 | ||
2584 | if (intstatus & I_RD_OOSYNC) { | |
2585 | brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n"); | |
2586 | intstatus &= ~I_RD_OOSYNC; | |
2587 | } | |
2588 | ||
2589 | if (intstatus & I_SBINT) { | |
2590 | brcmf_dbg(ERROR, "Dongle reports SBINT\n"); | |
2591 | intstatus &= ~I_SBINT; | |
2592 | } | |
2593 | ||
2594 | /* Would be active due to wake-wlan in gSPI */ | |
2595 | if (intstatus & I_CHIPACTIVE) { | |
2596 | brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); | |
2597 | intstatus &= ~I_CHIPACTIVE; | |
2598 | } | |
2599 | ||
2600 | /* Ignore frame indications if rxskip is set */ | |
2601 | if (bus->rxskip) | |
2602 | intstatus &= ~I_HMB_FRAME_IND; | |
2603 | ||
2604 | /* On frame indication, read available frames */ | |
2605 | if (PKT_AVAILABLE()) { | |
2606 | framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone); | |
2607 | if (rxdone || bus->rxskip) | |
2608 | intstatus &= ~I_HMB_FRAME_IND; | |
2609 | rxlimit -= min(framecnt, rxlimit); | |
2610 | } | |
2611 | ||
2612 | /* Keep still-pending events for next scheduling */ | |
2613 | bus->intstatus = intstatus; | |
2614 | ||
2615 | clkwait: | |
2616 | if (data_ok(bus) && bus->ctrl_frame_stat && | |
2617 | (bus->clkstate == CLK_AVAIL)) { | |
2618 | int ret, i; | |
2619 | ||
2620 | ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad, | |
2621 | SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf, | |
2622 | (u32) bus->ctrl_frame_len, NULL); | |
2623 | ||
2624 | if (ret < 0) { | |
2625 | /* On failure, abort the command and | |
2626 | terminate the frame */ | |
2627 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2628 | ret); | |
2629 | bus->tx_sderrs++; | |
2630 | ||
2631 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2632 | ||
2633 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2634 | SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, | |
2635 | NULL); | |
2636 | bus->f1regdata++; | |
2637 | ||
2638 | for (i = 0; i < 3; i++) { | |
2639 | u8 hi, lo; | |
2640 | hi = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2641 | SDIO_FUNC_1, | |
2642 | SBSDIO_FUNC1_WFRAMEBCHI, | |
2643 | NULL); | |
2644 | lo = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2645 | SDIO_FUNC_1, | |
2646 | SBSDIO_FUNC1_WFRAMEBCLO, | |
2647 | NULL); | |
2648 | bus->f1regdata += 2; | |
2649 | if ((hi == 0) && (lo == 0)) | |
2650 | break; | |
2651 | } | |
2652 | ||
2653 | } | |
2654 | if (ret == 0) | |
2655 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; | |
2656 | ||
2657 | brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret); | |
2658 | bus->ctrl_frame_stat = false; | |
2659 | brcmf_sdbrcm_wait_event_wakeup(bus); | |
2660 | } | |
2661 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
2662 | else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate && | |
2663 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit | |
2664 | && data_ok(bus)) { | |
2665 | framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax); | |
2666 | framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt); | |
2667 | txlimit -= framecnt; | |
2668 | } | |
2669 | ||
2670 | /* Resched if events or tx frames are pending, | |
2671 | else await next interrupt */ | |
2672 | /* On failed register access, all bets are off: | |
2673 | no resched or interrupts */ | |
2674 | if ((bus->drvr->busstate == BRCMF_BUS_DOWN) || | |
2675 | brcmf_sdcard_regfail(bus->sdiodev)) { | |
2676 | brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n", | |
2677 | brcmf_sdcard_regfail(bus->sdiodev)); | |
2678 | bus->drvr->busstate = BRCMF_BUS_DOWN; | |
2679 | bus->intstatus = 0; | |
2680 | } else if (bus->clkstate == CLK_PENDING) { | |
2681 | brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n"); | |
2682 | resched = true; | |
2683 | } else if (bus->intstatus || bus->ipend || | |
2684 | (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) | |
2685 | && data_ok(bus)) || PKT_AVAILABLE()) { | |
2686 | resched = true; | |
2687 | } | |
2688 | ||
2689 | bus->dpc_sched = resched; | |
2690 | ||
2691 | /* If we're done for now, turn off clock request. */ | |
2692 | if ((bus->clkstate != CLK_PENDING) | |
2693 | && bus->idletime == BRCMF_IDLE_IMMEDIATE) { | |
2694 | bus->activity = false; | |
2695 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
2696 | } | |
2697 | ||
2698 | up(&bus->sdsem); | |
2699 | ||
2700 | return resched; | |
2701 | } | |
2702 | ||
2703 | static int brcmf_sdbrcm_dpc_thread(void *data) | |
2704 | { | |
2705 | struct brcmf_bus *bus = (struct brcmf_bus *) data; | |
2706 | ||
2707 | allow_signal(SIGTERM); | |
2708 | /* Run until signal received */ | |
2709 | while (1) { | |
2710 | if (kthread_should_stop()) | |
2711 | break; | |
2712 | if (!wait_for_completion_interruptible(&bus->dpc_wait)) { | |
2713 | /* Call bus dpc unless it indicated down | |
2714 | (then clean stop) */ | |
2715 | if (bus->drvr->busstate != BRCMF_BUS_DOWN) { | |
2716 | if (brcmf_sdbrcm_dpc(bus)) | |
2717 | complete(&bus->dpc_wait); | |
2718 | } else { | |
2719 | /* after stopping the bus, exit thread */ | |
2720 | brcmf_sdbrcm_bus_stop(bus); | |
2721 | bus->dpc_tsk = NULL; | |
2722 | break; | |
2723 | } | |
2724 | } else | |
2725 | break; | |
2726 | } | |
2727 | return 0; | |
2728 | } | |
2729 | ||
2730 | int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt) | |
2731 | { | |
2732 | int ret = -EBADE; | |
2733 | uint datalen, prec; | |
2734 | ||
2735 | brcmf_dbg(TRACE, "Enter\n"); | |
2736 | ||
2737 | datalen = pkt->len; | |
2738 | ||
2739 | /* Add space for the header */ | |
2740 | skb_push(pkt, SDPCM_HDRLEN); | |
2741 | /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ | |
2742 | ||
2743 | prec = prio2prec((pkt->priority & PRIOMASK)); | |
2744 | ||
2745 | /* Check for existing queue, current flow-control, | |
2746 | pending event, or pending clock */ | |
2747 | brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); | |
2748 | bus->fcqueued++; | |
2749 | ||
2750 | /* Priority based enq */ | |
2751 | spin_lock_bh(&bus->txqlock); | |
2752 | if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) { | |
2753 | skb_pull(pkt, SDPCM_HDRLEN); | |
2754 | brcmf_txcomplete(bus->drvr, pkt, false); | |
2755 | brcmu_pkt_buf_free_skb(pkt); | |
2756 | brcmf_dbg(ERROR, "out of bus->txq !!!\n"); | |
2757 | ret = -ENOSR; | |
2758 | } else { | |
2759 | ret = 0; | |
2760 | } | |
2761 | spin_unlock_bh(&bus->txqlock); | |
2762 | ||
2763 | if (pktq_len(&bus->txq) >= TXHI) | |
2764 | brcmf_txflowcontrol(bus->drvr, 0, ON); | |
2765 | ||
2766 | #ifdef BCMDBG | |
2767 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) | |
2768 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2769 | #endif | |
2770 | /* Schedule DPC if needed to send queued packet(s) */ | |
2771 | if (!bus->dpc_sched) { | |
2772 | bus->dpc_sched = true; | |
2773 | if (bus->dpc_tsk) | |
2774 | complete(&bus->dpc_wait); | |
2775 | } | |
2776 | ||
2777 | return ret; | |
2778 | } | |
2779 | ||
2780 | static int | |
2781 | brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data, | |
2782 | uint size) | |
2783 | { | |
2784 | int bcmerror = 0; | |
2785 | u32 sdaddr; | |
2786 | uint dsize; | |
2787 | ||
2788 | /* Determine initial transfer parameters */ | |
2789 | sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK; | |
2790 | if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK) | |
2791 | dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr); | |
2792 | else | |
2793 | dsize = size; | |
2794 | ||
2795 | /* Set the backplane window to include the start address */ | |
2796 | bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address); | |
2797 | if (bcmerror) { | |
2798 | brcmf_dbg(ERROR, "window change failed\n"); | |
2799 | goto xfer_done; | |
2800 | } | |
2801 | ||
2802 | /* Do the transfer(s) */ | |
2803 | while (size) { | |
2804 | brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n", | |
2805 | write ? "write" : "read", dsize, | |
2806 | sdaddr, address & SBSDIO_SBWINDOW_MASK); | |
2807 | bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write, | |
2808 | sdaddr, data, dsize); | |
2809 | if (bcmerror) { | |
2810 | brcmf_dbg(ERROR, "membytes transfer failed\n"); | |
2811 | break; | |
2812 | } | |
2813 | ||
2814 | /* Adjust for next transfer (if any) */ | |
2815 | size -= dsize; | |
2816 | if (size) { | |
2817 | data += dsize; | |
2818 | address += dsize; | |
2819 | bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, | |
2820 | address); | |
2821 | if (bcmerror) { | |
2822 | brcmf_dbg(ERROR, "window change failed\n"); | |
2823 | break; | |
2824 | } | |
2825 | sdaddr = 0; | |
2826 | dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size); | |
2827 | } | |
2828 | } | |
2829 | ||
2830 | xfer_done: | |
2831 | /* Return the window to backplane enumeration space for core access */ | |
2832 | if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad)) | |
2833 | brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n", | |
2834 | bus->sdiodev->sbwad); | |
2835 | ||
2836 | return bcmerror; | |
2837 | } | |
2838 | ||
2839 | #ifdef BCMDBG | |
2840 | #define CONSOLE_LINE_MAX 192 | |
2841 | ||
2842 | static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus) | |
2843 | { | |
2844 | struct brcmf_console *c = &bus->console; | |
2845 | u8 line[CONSOLE_LINE_MAX], ch; | |
2846 | u32 n, idx, addr; | |
2847 | int rv; | |
2848 | ||
2849 | /* Don't do anything until FWREADY updates console address */ | |
2850 | if (bus->console_addr == 0) | |
2851 | return 0; | |
2852 | ||
2853 | /* Read console log struct */ | |
2854 | addr = bus->console_addr + offsetof(struct rte_console, log_le); | |
2855 | rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le, | |
2856 | sizeof(c->log_le)); | |
2857 | if (rv < 0) | |
2858 | return rv; | |
2859 | ||
2860 | /* Allocate console buffer (one time only) */ | |
2861 | if (c->buf == NULL) { | |
2862 | c->bufsize = le32_to_cpu(c->log_le.buf_size); | |
2863 | c->buf = kmalloc(c->bufsize, GFP_ATOMIC); | |
2864 | if (c->buf == NULL) | |
2865 | return -ENOMEM; | |
2866 | } | |
2867 | ||
2868 | idx = le32_to_cpu(c->log_le.idx); | |
2869 | ||
2870 | /* Protect against corrupt value */ | |
2871 | if (idx > c->bufsize) | |
2872 | return -EBADE; | |
2873 | ||
2874 | /* Skip reading the console buffer if the index pointer | |
2875 | has not moved */ | |
2876 | if (idx == c->last) | |
2877 | return 0; | |
2878 | ||
2879 | /* Read the console buffer */ | |
2880 | addr = le32_to_cpu(c->log_le.buf); | |
2881 | rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize); | |
2882 | if (rv < 0) | |
2883 | return rv; | |
2884 | ||
2885 | while (c->last != idx) { | |
2886 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
2887 | if (c->last == idx) { | |
2888 | /* This would output a partial line. | |
2889 | * Instead, back up | |
2890 | * the buffer pointer and output this | |
2891 | * line next time around. | |
2892 | */ | |
2893 | if (c->last >= n) | |
2894 | c->last -= n; | |
2895 | else | |
2896 | c->last = c->bufsize - n; | |
2897 | goto break2; | |
2898 | } | |
2899 | ch = c->buf[c->last]; | |
2900 | c->last = (c->last + 1) % c->bufsize; | |
2901 | if (ch == '\n') | |
2902 | break; | |
2903 | line[n] = ch; | |
2904 | } | |
2905 | ||
2906 | if (n > 0) { | |
2907 | if (line[n - 1] == '\r') | |
2908 | n--; | |
2909 | line[n] = 0; | |
2910 | printk(KERN_DEBUG "CONSOLE: %s\n", line); | |
2911 | } | |
2912 | } | |
2913 | break2: | |
2914 | ||
2915 | return 0; | |
2916 | } | |
2917 | #endif /* BCMDBG */ | |
2918 | ||
2919 | static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len) | |
2920 | { | |
2921 | int i; | |
2922 | int ret; | |
2923 | ||
2924 | bus->ctrl_frame_stat = false; | |
2925 | ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad, | |
2926 | SDIO_FUNC_2, F2SYNC, frame, len, NULL); | |
2927 | ||
2928 | if (ret < 0) { | |
2929 | /* On failure, abort the command and terminate the frame */ | |
2930 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2931 | ret); | |
2932 | bus->tx_sderrs++; | |
2933 | ||
2934 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2935 | ||
2936 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2937 | SBSDIO_FUNC1_FRAMECTRL, | |
2938 | SFC_WF_TERM, NULL); | |
2939 | bus->f1regdata++; | |
2940 | ||
2941 | for (i = 0; i < 3; i++) { | |
2942 | u8 hi, lo; | |
2943 | hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2944 | SBSDIO_FUNC1_WFRAMEBCHI, | |
2945 | NULL); | |
2946 | lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2947 | SBSDIO_FUNC1_WFRAMEBCLO, | |
2948 | NULL); | |
2949 | bus->f1regdata += 2; | |
2950 | if (hi == 0 && lo == 0) | |
2951 | break; | |
2952 | } | |
2953 | return ret; | |
2954 | } | |
2955 | ||
2956 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; | |
2957 | ||
2958 | return ret; | |
2959 | } | |
2960 | ||
2961 | int | |
2962 | brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen) | |
2963 | { | |
2964 | u8 *frame; | |
2965 | u16 len; | |
2966 | u32 swheader; | |
2967 | uint retries = 0; | |
2968 | u8 doff = 0; | |
2969 | int ret = -1; | |
2970 | ||
2971 | brcmf_dbg(TRACE, "Enter\n"); | |
2972 | ||
2973 | /* Back the pointer to make a room for bus header */ | |
2974 | frame = msg - SDPCM_HDRLEN; | |
2975 | len = (msglen += SDPCM_HDRLEN); | |
2976 | ||
2977 | /* Add alignment padding (optional for ctl frames) */ | |
2978 | doff = ((unsigned long)frame % BRCMF_SDALIGN); | |
2979 | if (doff) { | |
2980 | frame -= doff; | |
2981 | len += doff; | |
2982 | msglen += doff; | |
2983 | memset(frame, 0, doff + SDPCM_HDRLEN); | |
2984 | } | |
2985 | /* precondition: doff < BRCMF_SDALIGN */ | |
2986 | doff += SDPCM_HDRLEN; | |
2987 | ||
2988 | /* Round send length to next SDIO block */ | |
2989 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2990 | u16 pad = bus->blocksize - (len % bus->blocksize); | |
2991 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) | |
2992 | len += pad; | |
2993 | } else if (len % BRCMF_SDALIGN) { | |
2994 | len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN); | |
2995 | } | |
2996 | ||
2997 | /* Satisfy length-alignment requirements */ | |
2998 | if (len & (ALIGNMENT - 1)) | |
2999 | len = roundup(len, ALIGNMENT); | |
3000 | ||
3001 | /* precondition: IS_ALIGNED((unsigned long)frame, 2) */ | |
3002 | ||
3003 | /* Need to lock here to protect txseq and SDIO tx calls */ | |
3004 | down(&bus->sdsem); | |
3005 | ||
3006 | bus_wake(bus); | |
3007 | ||
3008 | /* Make sure backplane clock is on */ | |
3009 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3010 | ||
3011 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ | |
3012 | *(__le16 *) frame = cpu_to_le16((u16) msglen); | |
3013 | *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen); | |
3014 | ||
3015 | /* Software tag: channel, sequence number, data offset */ | |
3016 | swheader = | |
3017 | ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & | |
3018 | SDPCM_CHANNEL_MASK) | |
3019 | | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) & | |
3020 | SDPCM_DOFFSET_MASK); | |
3021 | put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN); | |
3022 | put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader)); | |
3023 | ||
3024 | if (!data_ok(bus)) { | |
3025 | brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n", | |
3026 | bus->tx_max, bus->tx_seq); | |
3027 | bus->ctrl_frame_stat = true; | |
3028 | /* Send from dpc */ | |
3029 | bus->ctrl_frame_buf = frame; | |
3030 | bus->ctrl_frame_len = len; | |
3031 | ||
3032 | brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat); | |
3033 | ||
3034 | if (bus->ctrl_frame_stat == false) { | |
3035 | brcmf_dbg(INFO, "ctrl_frame_stat == false\n"); | |
3036 | ret = 0; | |
3037 | } else { | |
3038 | brcmf_dbg(INFO, "ctrl_frame_stat == true\n"); | |
3039 | ret = -1; | |
3040 | } | |
3041 | } | |
3042 | ||
3043 | if (ret == -1) { | |
3044 | #ifdef BCMDBG | |
3045 | if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) { | |
3046 | printk(KERN_DEBUG "Tx Frame:\n"); | |
3047 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
3048 | frame, len); | |
3049 | } else if (BRCMF_HDRS_ON()) { | |
3050 | printk(KERN_DEBUG "TxHdr:\n"); | |
3051 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, | |
3052 | frame, min_t(u16, len, 16)); | |
3053 | } | |
3054 | #endif | |
3055 | ||
3056 | do { | |
3057 | ret = brcmf_tx_frame(bus, frame, len); | |
3058 | } while (ret < 0 && retries++ < TXRETRIES); | |
3059 | } | |
3060 | ||
3061 | if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) { | |
3062 | bus->activity = false; | |
3063 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, true); | |
3064 | } | |
3065 | ||
3066 | up(&bus->sdsem); | |
3067 | ||
3068 | if (ret) | |
3069 | bus->drvr->tx_ctlerrs++; | |
3070 | else | |
3071 | bus->drvr->tx_ctlpkts++; | |
3072 | ||
3073 | return ret ? -EIO : 0; | |
3074 | } | |
3075 | ||
3076 | int | |
3077 | brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen) | |
3078 | { | |
3079 | int timeleft; | |
3080 | uint rxlen = 0; | |
3081 | bool pending; | |
3082 | ||
3083 | brcmf_dbg(TRACE, "Enter\n"); | |
3084 | ||
3085 | /* Wait until control frame is available */ | |
3086 | timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending); | |
3087 | ||
3088 | down(&bus->sdsem); | |
3089 | rxlen = bus->rxlen; | |
3090 | memcpy(msg, bus->rxctl, min(msglen, rxlen)); | |
3091 | bus->rxlen = 0; | |
3092 | up(&bus->sdsem); | |
3093 | ||
3094 | if (rxlen) { | |
3095 | brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", | |
3096 | rxlen, msglen); | |
3097 | } else if (timeleft == 0) { | |
3098 | brcmf_dbg(ERROR, "resumed on timeout\n"); | |
3099 | } else if (pending == true) { | |
3100 | brcmf_dbg(CTL, "cancelled\n"); | |
3101 | return -ERESTARTSYS; | |
3102 | } else { | |
3103 | brcmf_dbg(CTL, "resumed for unknown reason?\n"); | |
3104 | } | |
3105 | ||
3106 | if (rxlen) | |
3107 | bus->drvr->rx_ctlpkts++; | |
3108 | else | |
3109 | bus->drvr->rx_ctlerrs++; | |
3110 | ||
3111 | return rxlen ? (int)rxlen : -ETIMEDOUT; | |
3112 | } | |
3113 | ||
3114 | static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len) | |
3115 | { | |
3116 | int bcmerror = 0; | |
3117 | ||
3118 | brcmf_dbg(TRACE, "Enter\n"); | |
3119 | ||
3120 | /* Basic sanity checks */ | |
3121 | if (bus->drvr->up) { | |
3122 | bcmerror = -EISCONN; | |
3123 | goto err; | |
3124 | } | |
3125 | if (!len) { | |
3126 | bcmerror = -EOVERFLOW; | |
3127 | goto err; | |
3128 | } | |
3129 | ||
3130 | /* Free the old ones and replace with passed variables */ | |
3131 | kfree(bus->vars); | |
3132 | ||
3133 | bus->vars = kmalloc(len, GFP_ATOMIC); | |
3134 | bus->varsz = bus->vars ? len : 0; | |
3135 | if (bus->vars == NULL) { | |
3136 | bcmerror = -ENOMEM; | |
3137 | goto err; | |
3138 | } | |
3139 | ||
3140 | /* Copy the passed variables, which should include the | |
3141 | terminating double-null */ | |
3142 | memcpy(bus->vars, arg, bus->varsz); | |
3143 | err: | |
3144 | return bcmerror; | |
3145 | } | |
3146 | ||
3147 | static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus) | |
3148 | { | |
3149 | int bcmerror = 0; | |
3150 | u32 varsize; | |
3151 | u32 varaddr; | |
3152 | u8 *vbuffer; | |
3153 | u32 varsizew; | |
3154 | __le32 varsizew_le; | |
3155 | #ifdef BCMDBG | |
3156 | char *nvram_ularray; | |
3157 | #endif /* BCMDBG */ | |
3158 | ||
3159 | /* Even if there are no vars are to be written, we still | |
3160 | need to set the ramsize. */ | |
3161 | varsize = bus->varsz ? roundup(bus->varsz, 4) : 0; | |
3162 | varaddr = (bus->ramsize - 4) - varsize; | |
3163 | ||
3164 | if (bus->vars) { | |
3165 | vbuffer = kzalloc(varsize, GFP_ATOMIC); | |
3166 | if (!vbuffer) | |
3167 | return -ENOMEM; | |
3168 | ||
3169 | memcpy(vbuffer, bus->vars, bus->varsz); | |
3170 | ||
3171 | /* Write the vars list */ | |
3172 | bcmerror = | |
3173 | brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize); | |
3174 | #ifdef BCMDBG | |
3175 | /* Verify NVRAM bytes */ | |
3176 | brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize); | |
3177 | nvram_ularray = kmalloc(varsize, GFP_ATOMIC); | |
3178 | if (!nvram_ularray) | |
3179 | return -ENOMEM; | |
3180 | ||
3181 | /* Upload image to verify downloaded contents. */ | |
3182 | memset(nvram_ularray, 0xaa, varsize); | |
3183 | ||
3184 | /* Read the vars list to temp buffer for comparison */ | |
3185 | bcmerror = | |
3186 | brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray, | |
3187 | varsize); | |
3188 | if (bcmerror) { | |
3189 | brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n", | |
3190 | bcmerror, varsize, varaddr); | |
3191 | } | |
3192 | /* Compare the org NVRAM with the one read from RAM */ | |
3193 | if (memcmp(vbuffer, nvram_ularray, varsize)) | |
3194 | brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n"); | |
3195 | else | |
3196 | brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n"); | |
3197 | ||
3198 | kfree(nvram_ularray); | |
3199 | #endif /* BCMDBG */ | |
3200 | ||
3201 | kfree(vbuffer); | |
3202 | } | |
3203 | ||
3204 | /* adjust to the user specified RAM */ | |
3205 | brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize); | |
3206 | brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n", | |
3207 | varaddr, varsize); | |
3208 | varsize = ((bus->ramsize - 4) - varaddr); | |
3209 | ||
3210 | /* | |
3211 | * Determine the length token: | |
3212 | * Varsize, converted to words, in lower 16-bits, checksum | |
3213 | * in upper 16-bits. | |
3214 | */ | |
3215 | if (bcmerror) { | |
3216 | varsizew = 0; | |
3217 | varsizew_le = cpu_to_le32(0); | |
3218 | } else { | |
3219 | varsizew = varsize / 4; | |
3220 | varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF); | |
3221 | varsizew_le = cpu_to_le32(varsizew); | |
3222 | } | |
3223 | ||
3224 | brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n", | |
3225 | varsize, varsizew); | |
3226 | ||
3227 | /* Write the length token to the last word */ | |
3228 | bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4), | |
3229 | (u8 *)&varsizew_le, 4); | |
3230 | ||
3231 | return bcmerror; | |
3232 | } | |
3233 | ||
3234 | static void | |
3235 | brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase) | |
3236 | { | |
3237 | u32 regdata; | |
3238 | ||
3239 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3240 | CORE_SB(corebase, sbtmstatelow), 4); | |
3241 | if (regdata & SBTML_RESET) | |
3242 | return; | |
3243 | ||
3244 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3245 | CORE_SB(corebase, sbtmstatelow), 4); | |
3246 | if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) { | |
3247 | /* | |
3248 | * set target reject and spin until busy is clear | |
3249 | * (preserve core-specific bits) | |
3250 | */ | |
3251 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3252 | CORE_SB(corebase, sbtmstatelow), 4); | |
3253 | brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), | |
3254 | 4, regdata | SBTML_REJ); | |
3255 | ||
3256 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3257 | CORE_SB(corebase, sbtmstatelow), 4); | |
3258 | udelay(1); | |
3259 | SPINWAIT((brcmf_sdcard_reg_read(sdiodev, | |
3260 | CORE_SB(corebase, sbtmstatehigh), 4) & | |
3261 | SBTMH_BUSY), 100000); | |
3262 | ||
3263 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3264 | CORE_SB(corebase, sbtmstatehigh), 4); | |
3265 | if (regdata & SBTMH_BUSY) | |
3266 | brcmf_dbg(ERROR, "ARM core still busy\n"); | |
3267 | ||
3268 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3269 | CORE_SB(corebase, sbidlow), 4); | |
3270 | if (regdata & SBIDL_INIT) { | |
3271 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3272 | CORE_SB(corebase, sbimstate), 4) | | |
3273 | SBIM_RJ; | |
3274 | brcmf_sdcard_reg_write(sdiodev, | |
3275 | CORE_SB(corebase, sbimstate), 4, | |
3276 | regdata); | |
3277 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3278 | CORE_SB(corebase, sbimstate), 4); | |
3279 | udelay(1); | |
3280 | SPINWAIT((brcmf_sdcard_reg_read(sdiodev, | |
3281 | CORE_SB(corebase, sbimstate), 4) & | |
3282 | SBIM_BY), 100000); | |
3283 | } | |
3284 | ||
3285 | /* set reset and reject while enabling the clocks */ | |
3286 | brcmf_sdcard_reg_write(sdiodev, | |
3287 | CORE_SB(corebase, sbtmstatelow), 4, | |
3288 | (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) | | |
3289 | SBTML_REJ | SBTML_RESET)); | |
3290 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3291 | CORE_SB(corebase, sbtmstatelow), 4); | |
3292 | udelay(10); | |
3293 | ||
3294 | /* clear the initiator reject bit */ | |
3295 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3296 | CORE_SB(corebase, sbidlow), 4); | |
3297 | if (regdata & SBIDL_INIT) { | |
3298 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3299 | CORE_SB(corebase, sbimstate), 4) & | |
3300 | ~SBIM_RJ; | |
3301 | brcmf_sdcard_reg_write(sdiodev, | |
3302 | CORE_SB(corebase, sbimstate), 4, | |
3303 | regdata); | |
3304 | } | |
3305 | } | |
3306 | ||
3307 | /* leave reset and reject asserted */ | |
3308 | brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4, | |
3309 | (SBTML_REJ | SBTML_RESET)); | |
3310 | udelay(1); | |
3311 | } | |
3312 | ||
3313 | static void | |
3314 | brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase) | |
3315 | { | |
3316 | u32 regdata; | |
3317 | ||
3318 | /* | |
3319 | * Must do the disable sequence first to work for | |
3320 | * arbitrary current core state. | |
3321 | */ | |
3322 | brcmf_sdbrcm_chip_disablecore(sdiodev, corebase); | |
3323 | ||
3324 | /* | |
3325 | * Now do the initialization sequence. | |
3326 | * set reset while enabling the clock and | |
3327 | * forcing them on throughout the core | |
3328 | */ | |
3329 | brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4, | |
3330 | ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) | | |
3331 | SBTML_RESET); | |
3332 | udelay(1); | |
3333 | ||
3334 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3335 | CORE_SB(corebase, sbtmstatehigh), 4); | |
3336 | if (regdata & SBTMH_SERR) | |
3337 | brcmf_sdcard_reg_write(sdiodev, | |
3338 | CORE_SB(corebase, sbtmstatehigh), 4, 0); | |
3339 | ||
3340 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
3341 | CORE_SB(corebase, sbimstate), 4); | |
3342 | if (regdata & (SBIM_IBE | SBIM_TO)) | |
3343 | brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4, | |
3344 | regdata & ~(SBIM_IBE | SBIM_TO)); | |
3345 | ||
3346 | /* clear reset and allow it to propagate throughout the core */ | |
3347 | brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4, | |
3348 | (SICF_FGC << SBTML_SICF_SHIFT) | | |
3349 | (SICF_CLOCK_EN << SBTML_SICF_SHIFT)); | |
3350 | udelay(1); | |
3351 | ||
3352 | /* leave clock enabled */ | |
3353 | brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4, | |
3354 | (SICF_CLOCK_EN << SBTML_SICF_SHIFT)); | |
3355 | udelay(1); | |
3356 | } | |
3357 | ||
3358 | static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter) | |
3359 | { | |
3360 | uint retries; | |
3361 | u32 regdata; | |
3362 | int bcmerror = 0; | |
3363 | ||
3364 | /* To enter download state, disable ARM and reset SOCRAM. | |
3365 | * To exit download state, simply reset ARM (default is RAM boot). | |
3366 | */ | |
3367 | if (enter) { | |
3368 | bus->alp_only = true; | |
3369 | ||
3370 | brcmf_sdbrcm_chip_disablecore(bus->sdiodev, | |
3371 | bus->ci->armcorebase); | |
3372 | ||
3373 | brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase); | |
3374 | ||
3375 | /* Clear the top bit of memory */ | |
3376 | if (bus->ramsize) { | |
3377 | u32 zeros = 0; | |
3378 | brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4, | |
3379 | (u8 *)&zeros, 4); | |
3380 | } | |
3381 | } else { | |
3382 | regdata = brcmf_sdcard_reg_read(bus->sdiodev, | |
3383 | CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4); | |
3384 | regdata &= (SBTML_RESET | SBTML_REJ_MASK | | |
3385 | (SICF_CLOCK_EN << SBTML_SICF_SHIFT)); | |
3386 | if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) { | |
3387 | brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n"); | |
3388 | bcmerror = -EBADE; | |
3389 | goto fail; | |
3390 | } | |
3391 | ||
3392 | bcmerror = brcmf_sdbrcm_write_vars(bus); | |
3393 | if (bcmerror) { | |
3394 | brcmf_dbg(ERROR, "no vars written to RAM\n"); | |
3395 | bcmerror = 0; | |
3396 | } | |
3397 | ||
3398 | w_sdreg32(bus, 0xFFFFFFFF, | |
3399 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
3400 | ||
3401 | brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase); | |
3402 | ||
3403 | /* Allow HT Clock now that the ARM is running. */ | |
3404 | bus->alp_only = false; | |
3405 | ||
3406 | bus->drvr->busstate = BRCMF_BUS_LOAD; | |
3407 | } | |
3408 | fail: | |
3409 | return bcmerror; | |
3410 | } | |
3411 | ||
3412 | static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus) | |
3413 | { | |
3414 | if (bus->firmware->size < bus->fw_ptr + len) | |
3415 | len = bus->firmware->size - bus->fw_ptr; | |
3416 | ||
3417 | memcpy(buf, &bus->firmware->data[bus->fw_ptr], len); | |
3418 | bus->fw_ptr += len; | |
3419 | return len; | |
3420 | } | |
3421 | ||
3422 | MODULE_FIRMWARE(BCM4329_FW_NAME); | |
3423 | MODULE_FIRMWARE(BCM4329_NV_NAME); | |
3424 | ||
3425 | static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus) | |
3426 | { | |
3427 | int offset = 0; | |
3428 | uint len; | |
3429 | u8 *memblock = NULL, *memptr; | |
3430 | int ret; | |
3431 | ||
3432 | brcmf_dbg(INFO, "Enter\n"); | |
3433 | ||
3434 | bus->fw_name = BCM4329_FW_NAME; | |
3435 | ret = request_firmware(&bus->firmware, bus->fw_name, | |
3436 | &bus->sdiodev->func[2]->dev); | |
3437 | if (ret) { | |
3438 | brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret); | |
3439 | return ret; | |
3440 | } | |
3441 | bus->fw_ptr = 0; | |
3442 | ||
3443 | memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC); | |
3444 | if (memblock == NULL) { | |
3445 | ret = -ENOMEM; | |
3446 | goto err; | |
3447 | } | |
3448 | if ((u32)(unsigned long)memblock % BRCMF_SDALIGN) | |
3449 | memptr += (BRCMF_SDALIGN - | |
3450 | ((u32)(unsigned long)memblock % BRCMF_SDALIGN)); | |
3451 | ||
3452 | /* Download image */ | |
3453 | while ((len = | |
3454 | brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) { | |
3455 | ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len); | |
3456 | if (ret) { | |
3457 | brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n", | |
3458 | ret, MEMBLOCK, offset); | |
3459 | goto err; | |
3460 | } | |
3461 | ||
3462 | offset += MEMBLOCK; | |
3463 | } | |
3464 | ||
3465 | err: | |
3466 | kfree(memblock); | |
3467 | ||
3468 | release_firmware(bus->firmware); | |
3469 | bus->fw_ptr = 0; | |
3470 | ||
3471 | return ret; | |
3472 | } | |
3473 | ||
3474 | /* | |
3475 | * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file | |
3476 | * and ending in a NUL. | |
3477 | * Removes carriage returns, empty lines, comment lines, and converts | |
3478 | * newlines to NULs. | |
3479 | * Shortens buffer as needed and pads with NULs. End of buffer is marked | |
3480 | * by two NULs. | |
3481 | */ | |
3482 | ||
3483 | static uint brcmf_process_nvram_vars(char *varbuf, uint len) | |
3484 | { | |
3485 | char *dp; | |
3486 | bool findNewline; | |
3487 | int column; | |
3488 | uint buf_len, n; | |
3489 | ||
3490 | dp = varbuf; | |
3491 | ||
3492 | findNewline = false; | |
3493 | column = 0; | |
3494 | ||
3495 | for (n = 0; n < len; n++) { | |
3496 | if (varbuf[n] == 0) | |
3497 | break; | |
3498 | if (varbuf[n] == '\r') | |
3499 | continue; | |
3500 | if (findNewline && varbuf[n] != '\n') | |
3501 | continue; | |
3502 | findNewline = false; | |
3503 | if (varbuf[n] == '#') { | |
3504 | findNewline = true; | |
3505 | continue; | |
3506 | } | |
3507 | if (varbuf[n] == '\n') { | |
3508 | if (column == 0) | |
3509 | continue; | |
3510 | *dp++ = 0; | |
3511 | column = 0; | |
3512 | continue; | |
3513 | } | |
3514 | *dp++ = varbuf[n]; | |
3515 | column++; | |
3516 | } | |
3517 | buf_len = dp - varbuf; | |
3518 | ||
3519 | while (dp < varbuf + n) | |
3520 | *dp++ = 0; | |
3521 | ||
3522 | return buf_len; | |
3523 | } | |
3524 | ||
3525 | static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus) | |
3526 | { | |
3527 | uint len; | |
3528 | char *memblock = NULL; | |
3529 | char *bufp; | |
3530 | int ret; | |
3531 | ||
3532 | bus->nv_name = BCM4329_NV_NAME; | |
3533 | ret = request_firmware(&bus->firmware, bus->nv_name, | |
3534 | &bus->sdiodev->func[2]->dev); | |
3535 | if (ret) { | |
3536 | brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret); | |
3537 | return ret; | |
3538 | } | |
3539 | bus->fw_ptr = 0; | |
3540 | ||
3541 | memblock = kmalloc(MEMBLOCK, GFP_ATOMIC); | |
3542 | if (memblock == NULL) { | |
3543 | ret = -ENOMEM; | |
3544 | goto err; | |
3545 | } | |
3546 | ||
3547 | len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus); | |
3548 | ||
3549 | if (len > 0 && len < MEMBLOCK) { | |
3550 | bufp = (char *)memblock; | |
3551 | bufp[len] = 0; | |
3552 | len = brcmf_process_nvram_vars(bufp, len); | |
3553 | bufp += len; | |
3554 | *bufp++ = 0; | |
3555 | if (len) | |
3556 | ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1); | |
3557 | if (ret) | |
3558 | brcmf_dbg(ERROR, "error downloading vars: %d\n", ret); | |
3559 | } else { | |
3560 | brcmf_dbg(ERROR, "error reading nvram file: %d\n", len); | |
3561 | ret = -EIO; | |
3562 | } | |
3563 | ||
3564 | err: | |
3565 | kfree(memblock); | |
3566 | ||
3567 | release_firmware(bus->firmware); | |
3568 | bus->fw_ptr = 0; | |
3569 | ||
3570 | return ret; | |
3571 | } | |
3572 | ||
3573 | static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus) | |
3574 | { | |
3575 | int bcmerror = -1; | |
3576 | ||
3577 | /* Keep arm in reset */ | |
3578 | if (brcmf_sdbrcm_download_state(bus, true)) { | |
3579 | brcmf_dbg(ERROR, "error placing ARM core in reset\n"); | |
3580 | goto err; | |
3581 | } | |
3582 | ||
3583 | /* External image takes precedence if specified */ | |
3584 | if (brcmf_sdbrcm_download_code_file(bus)) { | |
3585 | brcmf_dbg(ERROR, "dongle image file download failed\n"); | |
3586 | goto err; | |
3587 | } | |
3588 | ||
3589 | /* External nvram takes precedence if specified */ | |
3590 | if (brcmf_sdbrcm_download_nvram(bus)) | |
3591 | brcmf_dbg(ERROR, "dongle nvram file download failed\n"); | |
3592 | ||
3593 | /* Take arm out of reset */ | |
3594 | if (brcmf_sdbrcm_download_state(bus, false)) { | |
3595 | brcmf_dbg(ERROR, "error getting out of ARM core reset\n"); | |
3596 | goto err; | |
3597 | } | |
3598 | ||
3599 | bcmerror = 0; | |
3600 | ||
3601 | err: | |
3602 | return bcmerror; | |
3603 | } | |
3604 | ||
3605 | static bool | |
3606 | brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus) | |
3607 | { | |
3608 | bool ret; | |
3609 | ||
3610 | /* Download the firmware */ | |
3611 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3612 | ||
3613 | ret = _brcmf_sdbrcm_download_firmware(bus) == 0; | |
3614 | ||
3615 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
3616 | ||
3617 | return ret; | |
3618 | } | |
3619 | ||
3620 | void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus) | |
3621 | { | |
3622 | u32 local_hostintmask; | |
3623 | u8 saveclk; | |
3624 | uint retries; | |
3625 | int err; | |
3626 | ||
3627 | brcmf_dbg(TRACE, "Enter\n"); | |
3628 | ||
3629 | if (bus->watchdog_tsk) { | |
3630 | send_sig(SIGTERM, bus->watchdog_tsk, 1); | |
3631 | kthread_stop(bus->watchdog_tsk); | |
3632 | bus->watchdog_tsk = NULL; | |
3633 | } | |
3634 | ||
3635 | if (bus->dpc_tsk && bus->dpc_tsk != current) { | |
3636 | send_sig(SIGTERM, bus->dpc_tsk, 1); | |
3637 | kthread_stop(bus->dpc_tsk); | |
3638 | bus->dpc_tsk = NULL; | |
3639 | } | |
3640 | ||
3641 | down(&bus->sdsem); | |
3642 | ||
3643 | bus_wake(bus); | |
3644 | ||
3645 | /* Enable clock for device interrupts */ | |
3646 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3647 | ||
3648 | /* Disable and clear interrupts at the chip level also */ | |
3649 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries); | |
3650 | local_hostintmask = bus->hostintmask; | |
3651 | bus->hostintmask = 0; | |
3652 | ||
3653 | /* Change our idea of bus state */ | |
3654 | bus->drvr->busstate = BRCMF_BUS_DOWN; | |
3655 | ||
3656 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
3657 | saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
3658 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
3659 | if (!err) { | |
3660 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3661 | SBSDIO_FUNC1_CHIPCLKCSR, | |
3662 | (saveclk | SBSDIO_FORCE_HT), &err); | |
3663 | } | |
3664 | if (err) | |
3665 | brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err); | |
3666 | ||
3667 | /* Turn off the bus (F2), free any pending packets */ | |
3668 | brcmf_dbg(INTR, "disable SDIO interrupts\n"); | |
3669 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx, | |
3670 | SDIO_FUNC_ENABLE_1, NULL); | |
3671 | ||
3672 | /* Clear any pending interrupts now that F2 is disabled */ | |
3673 | w_sdreg32(bus, local_hostintmask, | |
3674 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
3675 | ||
3676 | /* Turn off the backplane clock (only) */ | |
3677 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
3678 | ||
3679 | /* Clear the data packet queues */ | |
3680 | brcmu_pktq_flush(&bus->txq, true, NULL, NULL); | |
3681 | ||
3682 | /* Clear any held glomming stuff */ | |
3683 | if (bus->glomd) | |
3684 | brcmu_pkt_buf_free_skb(bus->glomd); | |
3685 | ||
3686 | if (bus->glom) | |
3687 | brcmu_pkt_buf_free_skb(bus->glom); | |
3688 | ||
3689 | bus->glom = bus->glomd = NULL; | |
3690 | ||
3691 | /* Clear rx control and wake any waiters */ | |
3692 | bus->rxlen = 0; | |
3693 | brcmf_sdbrcm_dcmd_resp_wake(bus); | |
3694 | ||
3695 | /* Reset some F2 state stuff */ | |
3696 | bus->rxskip = false; | |
3697 | bus->tx_seq = bus->rx_seq = 0; | |
3698 | ||
3699 | up(&bus->sdsem); | |
3700 | } | |
3701 | ||
3702 | int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr) | |
3703 | { | |
3704 | struct brcmf_bus *bus = drvr->bus; | |
3705 | unsigned long timeout; | |
3706 | uint retries = 0; | |
3707 | u8 ready, enable; | |
3708 | int err, ret = 0; | |
3709 | u8 saveclk; | |
3710 | ||
3711 | brcmf_dbg(TRACE, "Enter\n"); | |
3712 | ||
3713 | /* try to download image and nvram to the dongle */ | |
3714 | if (drvr->busstate == BRCMF_BUS_DOWN) { | |
3715 | if (!(brcmf_sdbrcm_download_firmware(bus))) | |
3716 | return -1; | |
3717 | } | |
3718 | ||
3719 | if (!bus->drvr) | |
3720 | return 0; | |
3721 | ||
3722 | /* Start the watchdog timer */ | |
3723 | bus->drvr->tickcnt = 0; | |
3724 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
3725 | ||
3726 | down(&bus->sdsem); | |
3727 | ||
3728 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
3729 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3730 | if (bus->clkstate != CLK_AVAIL) | |
3731 | goto exit; | |
3732 | ||
3733 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
3734 | saveclk = | |
3735 | brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
3736 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
3737 | if (!err) { | |
3738 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3739 | SBSDIO_FUNC1_CHIPCLKCSR, | |
3740 | (saveclk | SBSDIO_FORCE_HT), &err); | |
3741 | } | |
3742 | if (err) { | |
3743 | brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err); | |
3744 | goto exit; | |
3745 | } | |
3746 | ||
3747 | /* Enable function 2 (frame transfers) */ | |
3748 | w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, | |
3749 | offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries); | |
3750 | enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2); | |
3751 | ||
3752 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx, | |
3753 | enable, NULL); | |
3754 | ||
3755 | timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY); | |
3756 | ready = 0; | |
3757 | while (enable != ready) { | |
3758 | ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0, | |
3759 | SDIO_CCCR_IORx, NULL); | |
3760 | if (time_after(jiffies, timeout)) | |
3761 | break; | |
3762 | else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50)) | |
3763 | /* prevent busy waiting if it takes too long */ | |
3764 | msleep_interruptible(20); | |
3765 | } | |
3766 | ||
3767 | brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready); | |
3768 | ||
3769 | /* If F2 successfully enabled, set core and enable interrupts */ | |
3770 | if (ready == enable) { | |
3771 | /* Set up the interrupt mask and enable interrupts */ | |
3772 | bus->hostintmask = HOSTINTMASK; | |
3773 | w_sdreg32(bus, bus->hostintmask, | |
3774 | offsetof(struct sdpcmd_regs, hostintmask), &retries); | |
3775 | ||
3776 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3777 | SBSDIO_WATERMARK, 8, &err); | |
3778 | ||
3779 | /* Set bus state according to enable result */ | |
3780 | drvr->busstate = BRCMF_BUS_DATA; | |
3781 | } | |
3782 | ||
3783 | else { | |
3784 | /* Disable F2 again */ | |
3785 | enable = SDIO_FUNC_ENABLE_1; | |
3786 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, | |
3787 | SDIO_CCCR_IOEx, enable, NULL); | |
3788 | } | |
3789 | ||
3790 | /* Restore previous clock setting */ | |
3791 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3792 | SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err); | |
3793 | ||
3794 | /* If we didn't come up, turn off backplane clock */ | |
3795 | if (drvr->busstate != BRCMF_BUS_DATA) | |
3796 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
3797 | ||
3798 | exit: | |
3799 | up(&bus->sdsem); | |
3800 | ||
3801 | return ret; | |
3802 | } | |
3803 | ||
3804 | void brcmf_sdbrcm_isr(void *arg) | |
3805 | { | |
3806 | struct brcmf_bus *bus = (struct brcmf_bus *) arg; | |
3807 | ||
3808 | brcmf_dbg(TRACE, "Enter\n"); | |
3809 | ||
3810 | if (!bus) { | |
3811 | brcmf_dbg(ERROR, "bus is null pointer, exiting\n"); | |
3812 | return; | |
3813 | } | |
3814 | ||
3815 | if (bus->drvr->busstate == BRCMF_BUS_DOWN) { | |
3816 | brcmf_dbg(ERROR, "bus is down. we have nothing to do\n"); | |
3817 | return; | |
3818 | } | |
3819 | /* Count the interrupt call */ | |
3820 | bus->intrcount++; | |
3821 | bus->ipend = true; | |
3822 | ||
3823 | /* Shouldn't get this interrupt if we're sleeping? */ | |
3824 | if (bus->sleeping) { | |
3825 | brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n"); | |
3826 | return; | |
3827 | } | |
3828 | ||
3829 | /* Disable additional interrupts (is this needed now)? */ | |
3830 | if (!bus->intr) | |
3831 | brcmf_dbg(ERROR, "isr w/o interrupt configured!\n"); | |
3832 | ||
3833 | bus->dpc_sched = true; | |
3834 | if (bus->dpc_tsk) | |
3835 | complete(&bus->dpc_wait); | |
3836 | } | |
3837 | ||
3838 | static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr) | |
3839 | { | |
3840 | struct brcmf_bus *bus; | |
3841 | ||
3842 | brcmf_dbg(TIMER, "Enter\n"); | |
3843 | ||
3844 | bus = drvr->bus; | |
3845 | ||
3846 | /* Ignore the timer if simulating bus down */ | |
3847 | if (bus->sleeping) | |
3848 | return false; | |
3849 | ||
3850 | down(&bus->sdsem); | |
3851 | ||
3852 | /* Poll period: check device if appropriate. */ | |
3853 | if (bus->poll && (++bus->polltick >= bus->pollrate)) { | |
3854 | u32 intstatus = 0; | |
3855 | ||
3856 | /* Reset poll tick */ | |
3857 | bus->polltick = 0; | |
3858 | ||
3859 | /* Check device if no interrupts */ | |
3860 | if (!bus->intr || (bus->intrcount == bus->lastintrs)) { | |
3861 | ||
3862 | if (!bus->dpc_sched) { | |
3863 | u8 devpend; | |
3864 | devpend = brcmf_sdcard_cfg_read(bus->sdiodev, | |
3865 | SDIO_FUNC_0, SDIO_CCCR_INTx, | |
3866 | NULL); | |
3867 | intstatus = | |
3868 | devpend & (INTR_STATUS_FUNC1 | | |
3869 | INTR_STATUS_FUNC2); | |
3870 | } | |
3871 | ||
3872 | /* If there is something, make like the ISR and | |
3873 | schedule the DPC */ | |
3874 | if (intstatus) { | |
3875 | bus->pollcnt++; | |
3876 | bus->ipend = true; | |
3877 | ||
3878 | bus->dpc_sched = true; | |
3879 | if (bus->dpc_tsk) | |
3880 | complete(&bus->dpc_wait); | |
3881 | } | |
3882 | } | |
3883 | ||
3884 | /* Update interrupt tracking */ | |
3885 | bus->lastintrs = bus->intrcount; | |
3886 | } | |
3887 | #ifdef BCMDBG | |
3888 | /* Poll for console output periodically */ | |
3889 | if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) { | |
3890 | bus->console.count += BRCMF_WD_POLL_MS; | |
3891 | if (bus->console.count >= bus->console_interval) { | |
3892 | bus->console.count -= bus->console_interval; | |
3893 | /* Make sure backplane clock is on */ | |
3894 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3895 | if (brcmf_sdbrcm_readconsole(bus) < 0) | |
3896 | /* stop on error */ | |
3897 | bus->console_interval = 0; | |
3898 | } | |
3899 | } | |
3900 | #endif /* BCMDBG */ | |
3901 | ||
3902 | /* On idle timeout clear activity flag and/or turn off clock */ | |
3903 | if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) { | |
3904 | if (++bus->idlecount >= bus->idletime) { | |
3905 | bus->idlecount = 0; | |
3906 | if (bus->activity) { | |
3907 | bus->activity = false; | |
3908 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
3909 | } else { | |
3910 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
3911 | } | |
3912 | } | |
3913 | } | |
3914 | ||
3915 | up(&bus->sdsem); | |
3916 | ||
3917 | return bus->ipend; | |
3918 | } | |
3919 | ||
3920 | static bool brcmf_sdbrcm_chipmatch(u16 chipid) | |
3921 | { | |
3922 | if (chipid == BCM4329_CHIP_ID) | |
3923 | return true; | |
3924 | return false; | |
3925 | } | |
3926 | ||
3927 | static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus) | |
3928 | { | |
3929 | brcmf_dbg(TRACE, "Enter\n"); | |
3930 | ||
3931 | kfree(bus->rxbuf); | |
3932 | bus->rxctl = bus->rxbuf = NULL; | |
3933 | bus->rxlen = 0; | |
3934 | ||
3935 | kfree(bus->databuf); | |
3936 | bus->databuf = NULL; | |
3937 | } | |
3938 | ||
3939 | static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus) | |
3940 | { | |
3941 | brcmf_dbg(TRACE, "Enter\n"); | |
3942 | ||
3943 | if (bus->drvr->maxctl) { | |
3944 | bus->rxblen = | |
3945 | roundup((bus->drvr->maxctl + SDPCM_HDRLEN), | |
3946 | ALIGNMENT) + BRCMF_SDALIGN; | |
3947 | bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); | |
3948 | if (!(bus->rxbuf)) | |
3949 | goto fail; | |
3950 | } | |
3951 | ||
3952 | /* Allocate buffer to receive glomed packet */ | |
3953 | bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC); | |
3954 | if (!(bus->databuf)) { | |
3955 | /* release rxbuf which was already located as above */ | |
3956 | if (!bus->rxblen) | |
3957 | kfree(bus->rxbuf); | |
3958 | goto fail; | |
3959 | } | |
3960 | ||
3961 | /* Align the buffer */ | |
3962 | if ((unsigned long)bus->databuf % BRCMF_SDALIGN) | |
3963 | bus->dataptr = bus->databuf + (BRCMF_SDALIGN - | |
3964 | ((unsigned long)bus->databuf % BRCMF_SDALIGN)); | |
3965 | else | |
3966 | bus->dataptr = bus->databuf; | |
3967 | ||
3968 | return true; | |
3969 | ||
3970 | fail: | |
3971 | return false; | |
3972 | } | |
3973 | ||
3974 | /* SDIO Pad drive strength to select value mappings */ | |
3975 | struct sdiod_drive_str { | |
3976 | u8 strength; /* Pad Drive Strength in mA */ | |
3977 | u8 sel; /* Chip-specific select value */ | |
3978 | }; | |
3979 | ||
3980 | /* SDIO Drive Strength to sel value table for PMU Rev 1 */ | |
3981 | static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = { | |
3982 | { | |
3983 | 4, 0x2}, { | |
3984 | 2, 0x3}, { | |
3985 | 1, 0x0}, { | |
3986 | 0, 0x0} | |
3987 | }; | |
3988 | ||
3989 | /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */ | |
3990 | static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = { | |
3991 | { | |
3992 | 12, 0x7}, { | |
3993 | 10, 0x6}, { | |
3994 | 8, 0x5}, { | |
3995 | 6, 0x4}, { | |
3996 | 4, 0x2}, { | |
3997 | 2, 0x1}, { | |
3998 | 0, 0x0} | |
3999 | }; | |
4000 | ||
4001 | /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */ | |
4002 | static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = { | |
4003 | { | |
4004 | 32, 0x7}, { | |
4005 | 26, 0x6}, { | |
4006 | 22, 0x5}, { | |
4007 | 16, 0x4}, { | |
4008 | 12, 0x3}, { | |
4009 | 8, 0x2}, { | |
4010 | 4, 0x1}, { | |
4011 | 0, 0x0} | |
4012 | }; | |
4013 | ||
4014 | #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) | |
4015 | ||
b0551fb7 AB |
4016 | static char *brcmf_chipname(uint chipid, char *buf, uint len) |
4017 | { | |
4018 | const char *fmt; | |
4019 | ||
4020 | fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x"; | |
4021 | snprintf(buf, len, fmt, chipid); | |
4022 | return buf; | |
4023 | } | |
4024 | ||
5b435de0 AS |
4025 | static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus, |
4026 | u32 drivestrength) { | |
4027 | struct sdiod_drive_str *str_tab = NULL; | |
4028 | u32 str_mask = 0; | |
4029 | u32 str_shift = 0; | |
4030 | char chn[8]; | |
4031 | ||
4032 | if (!(bus->ci->cccaps & CC_CAP_PMU)) | |
4033 | return; | |
4034 | ||
4035 | switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) { | |
4036 | case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1): | |
4037 | str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1; | |
4038 | str_mask = 0x30000000; | |
4039 | str_shift = 28; | |
4040 | break; | |
4041 | case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2): | |
4042 | case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3): | |
4043 | str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2; | |
4044 | str_mask = 0x00003800; | |
4045 | str_shift = 11; | |
4046 | break; | |
4047 | case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8): | |
4048 | str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3; | |
4049 | str_mask = 0x00003800; | |
4050 | str_shift = 11; | |
4051 | break; | |
4052 | default: | |
4053 | brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", | |
b0551fb7 | 4054 | brcmf_chipname(bus->ci->chip, chn, 8), |
5b435de0 AS |
4055 | bus->ci->chiprev, bus->ci->pmurev); |
4056 | break; | |
4057 | } | |
4058 | ||
4059 | if (str_tab != NULL) { | |
4060 | u32 drivestrength_sel = 0; | |
4061 | u32 cc_data_temp; | |
4062 | int i; | |
4063 | ||
4064 | for (i = 0; str_tab[i].strength != 0; i++) { | |
4065 | if (drivestrength >= str_tab[i].strength) { | |
4066 | drivestrength_sel = str_tab[i].sel; | |
4067 | break; | |
4068 | } | |
4069 | } | |
4070 | ||
4071 | brcmf_sdcard_reg_write(bus->sdiodev, | |
4072 | CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), | |
4073 | 4, 1); | |
4074 | cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev, | |
4075 | CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4); | |
4076 | cc_data_temp &= ~str_mask; | |
4077 | drivestrength_sel <<= str_shift; | |
4078 | cc_data_temp |= drivestrength_sel; | |
4079 | brcmf_sdcard_reg_write(bus->sdiodev, | |
4080 | CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), | |
4081 | 4, cc_data_temp); | |
4082 | ||
4083 | brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n", | |
4084 | drivestrength, cc_data_temp); | |
4085 | } | |
4086 | } | |
4087 | ||
4088 | static int | |
4089 | brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev, | |
4090 | struct chip_info *ci, u32 regs) | |
4091 | { | |
4092 | u32 regdata; | |
4093 | ||
4094 | /* | |
4095 | * Get CC core rev | |
4096 | * Chipid is assume to be at offset 0 from regs arg | |
4097 | * For different chiptypes or old sdio hosts w/o chipcommon, | |
4098 | * other ways of recognition should be added here. | |
4099 | */ | |
4100 | ci->cccorebase = regs; | |
4101 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
4102 | CORE_CC_REG(ci->cccorebase, chipid), 4); | |
4103 | ci->chip = regdata & CID_ID_MASK; | |
4104 | ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT; | |
4105 | ||
4106 | brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev); | |
4107 | ||
4108 | /* Address of cores for new chips should be added here */ | |
4109 | switch (ci->chip) { | |
4110 | case BCM4329_CHIP_ID: | |
4111 | ci->buscorebase = BCM4329_CORE_BUS_BASE; | |
4112 | ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE; | |
4113 | ci->armcorebase = BCM4329_CORE_ARM_BASE; | |
4114 | ci->ramsize = BCM4329_RAMSIZE; | |
4115 | break; | |
4116 | default: | |
4117 | brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip); | |
4118 | return -ENODEV; | |
4119 | } | |
4120 | ||
4121 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
4122 | CORE_SB(ci->cccorebase, sbidhigh), 4); | |
4123 | ci->ccrev = SBCOREREV(regdata); | |
4124 | ||
4125 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
4126 | CORE_CC_REG(ci->cccorebase, pmucapabilities), 4); | |
4127 | ci->pmurev = regdata & PCAP_REV_MASK; | |
4128 | ||
4129 | regdata = brcmf_sdcard_reg_read(sdiodev, | |
4130 | CORE_SB(ci->buscorebase, sbidhigh), 4); | |
4131 | ci->buscorerev = SBCOREREV(regdata); | |
4132 | ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT; | |
4133 | ||
4134 | brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n", | |
4135 | ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype); | |
4136 | ||
4137 | /* get chipcommon capabilites */ | |
4138 | ci->cccaps = brcmf_sdcard_reg_read(sdiodev, | |
4139 | CORE_CC_REG(ci->cccorebase, capabilities), 4); | |
4140 | ||
4141 | return 0; | |
4142 | } | |
4143 | ||
4144 | static int | |
4145 | brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs) | |
4146 | { | |
4147 | struct chip_info *ci; | |
4148 | int err; | |
4149 | u8 clkval, clkset; | |
4150 | ||
4151 | brcmf_dbg(TRACE, "Enter\n"); | |
4152 | ||
4153 | /* alloc chip_info_t */ | |
4154 | ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC); | |
4155 | if (NULL == ci) | |
4156 | return -ENOMEM; | |
4157 | ||
4158 | /* bus/core/clk setup for register access */ | |
4159 | /* Try forcing SDIO core to do ALPAvail request only */ | |
4160 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; | |
4161 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
4162 | SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
4163 | if (err) { | |
4164 | brcmf_dbg(ERROR, "error writing for HT off\n"); | |
4165 | goto fail; | |
4166 | } | |
4167 | ||
4168 | /* If register supported, wait for ALPAvail and then force ALP */ | |
4169 | /* This may take up to 15 milliseconds */ | |
4170 | clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
4171 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); | |
4172 | if ((clkval & ~SBSDIO_AVBITS) == clkset) { | |
4173 | SPINWAIT(((clkval = | |
4174 | brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
4175 | SBSDIO_FUNC1_CHIPCLKCSR, | |
4176 | NULL)), | |
4177 | !SBSDIO_ALPAV(clkval)), | |
4178 | PMU_MAX_TRANSITION_DLY); | |
4179 | if (!SBSDIO_ALPAV(clkval)) { | |
4180 | brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n", | |
4181 | clkval); | |
4182 | err = -EBUSY; | |
4183 | goto fail; | |
4184 | } | |
4185 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | | |
4186 | SBSDIO_FORCE_ALP; | |
4187 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
4188 | SBSDIO_FUNC1_CHIPCLKCSR, | |
4189 | clkset, &err); | |
4190 | udelay(65); | |
4191 | } else { | |
4192 | brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n", | |
4193 | clkset, clkval); | |
4194 | err = -EACCES; | |
4195 | goto fail; | |
4196 | } | |
4197 | ||
4198 | /* Also, disable the extra SDIO pull-ups */ | |
4199 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
4200 | SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); | |
4201 | ||
4202 | err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs); | |
4203 | if (err) | |
4204 | goto fail; | |
4205 | ||
4206 | /* | |
4207 | * Make sure any on-chip ARM is off (in case strapping is wrong), | |
4208 | * or downloaded code was already running. | |
4209 | */ | |
4210 | brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase); | |
4211 | ||
4212 | brcmf_sdcard_reg_write(bus->sdiodev, | |
4213 | CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0); | |
4214 | brcmf_sdcard_reg_write(bus->sdiodev, | |
4215 | CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0); | |
4216 | ||
4217 | /* Disable F2 to clear any intermediate frame state on the dongle */ | |
4218 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx, | |
4219 | SDIO_FUNC_ENABLE_1, NULL); | |
4220 | ||
4221 | /* WAR: cmd52 backplane read so core HW will drop ALPReq */ | |
4222 | clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
4223 | 0, NULL); | |
4224 | ||
4225 | /* Done with backplane-dependent accesses, can drop clock... */ | |
4226 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
4227 | SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
4228 | ||
4229 | bus->ci = ci; | |
4230 | return 0; | |
4231 | fail: | |
4232 | bus->ci = NULL; | |
4233 | kfree(ci); | |
4234 | return err; | |
4235 | } | |
4236 | ||
4237 | static bool | |
4238 | brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva) | |
4239 | { | |
4240 | u8 clkctl = 0; | |
4241 | int err = 0; | |
4242 | int reg_addr; | |
4243 | u32 reg_val; | |
4244 | ||
4245 | bus->alp_only = true; | |
4246 | ||
4247 | /* Return the window to backplane enumeration space for core access */ | |
4248 | if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE)) | |
4249 | brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n"); | |
4250 | ||
4251 | #ifdef BCMDBG | |
4252 | printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n", | |
4253 | brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4)); | |
4254 | ||
4255 | #endif /* BCMDBG */ | |
4256 | ||
4257 | /* | |
4258 | * Force PLL off until brcmf_sdbrcm_chip_attach() | |
4259 | * programs PLL control regs | |
4260 | */ | |
4261 | ||
4262 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
4263 | SBSDIO_FUNC1_CHIPCLKCSR, | |
4264 | BRCMF_INIT_CLKCTL1, &err); | |
4265 | if (!err) | |
4266 | clkctl = | |
4267 | brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
4268 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
4269 | ||
4270 | if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { | |
4271 | brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", | |
4272 | err, BRCMF_INIT_CLKCTL1, clkctl); | |
4273 | goto fail; | |
4274 | } | |
4275 | ||
4276 | if (brcmf_sdbrcm_chip_attach(bus, regsva)) { | |
4277 | brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n"); | |
4278 | goto fail; | |
4279 | } | |
4280 | ||
4281 | if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) { | |
4282 | brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip); | |
4283 | goto fail; | |
4284 | } | |
4285 | ||
4286 | brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH); | |
4287 | ||
4288 | /* Get info on the ARM and SOCRAM cores... */ | |
4289 | brcmf_sdcard_reg_read(bus->sdiodev, | |
4290 | CORE_SB(bus->ci->armcorebase, sbidhigh), 4); | |
4291 | bus->ramsize = bus->ci->ramsize; | |
4292 | if (!(bus->ramsize)) { | |
4293 | brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n"); | |
4294 | goto fail; | |
4295 | } | |
4296 | ||
4297 | /* Set core control so an SDIO reset does a backplane reset */ | |
4298 | reg_addr = bus->ci->buscorebase + | |
4299 | offsetof(struct sdpcmd_regs, corecontrol); | |
4300 | reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32)); | |
4301 | brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32), | |
4302 | reg_val | CC_BPRESEN); | |
4303 | ||
4304 | brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); | |
4305 | ||
4306 | /* Locate an appropriately-aligned portion of hdrbuf */ | |
4307 | bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], | |
4308 | BRCMF_SDALIGN); | |
4309 | ||
4310 | /* Set the poll and/or interrupt flags */ | |
4311 | bus->intr = true; | |
4312 | bus->poll = false; | |
4313 | if (bus->poll) | |
4314 | bus->pollrate = 1; | |
4315 | ||
4316 | return true; | |
4317 | ||
4318 | fail: | |
4319 | return false; | |
4320 | } | |
4321 | ||
4322 | static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus) | |
4323 | { | |
4324 | brcmf_dbg(TRACE, "Enter\n"); | |
4325 | ||
4326 | /* Disable F2 to clear any intermediate frame state on the dongle */ | |
4327 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx, | |
4328 | SDIO_FUNC_ENABLE_1, NULL); | |
4329 | ||
4330 | bus->drvr->busstate = BRCMF_BUS_DOWN; | |
4331 | bus->sleeping = false; | |
4332 | bus->rxflow = false; | |
4333 | ||
4334 | /* Done with backplane-dependent accesses, can drop clock... */ | |
4335 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
4336 | SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
4337 | ||
4338 | /* ...and initialize clock/power states */ | |
4339 | bus->clkstate = CLK_SDONLY; | |
4340 | bus->idletime = BRCMF_IDLE_INTERVAL; | |
4341 | bus->idleclock = BRCMF_IDLE_ACTIVE; | |
4342 | ||
4343 | /* Query the F2 block size, set roundup accordingly */ | |
4344 | bus->blocksize = bus->sdiodev->func[2]->cur_blksize; | |
4345 | bus->roundup = min(max_roundup, bus->blocksize); | |
4346 | ||
4347 | /* bus module does not support packet chaining */ | |
4348 | bus->use_rxchain = false; | |
4349 | bus->sd_rxchain = false; | |
4350 | ||
4351 | return true; | |
4352 | } | |
4353 | ||
4354 | static int | |
4355 | brcmf_sdbrcm_watchdog_thread(void *data) | |
4356 | { | |
4357 | struct brcmf_bus *bus = (struct brcmf_bus *)data; | |
4358 | ||
4359 | allow_signal(SIGTERM); | |
4360 | /* Run until signal received */ | |
4361 | while (1) { | |
4362 | if (kthread_should_stop()) | |
4363 | break; | |
4364 | if (!wait_for_completion_interruptible(&bus->watchdog_wait)) { | |
4365 | brcmf_sdbrcm_bus_watchdog(bus->drvr); | |
4366 | /* Count the tick for reference */ | |
4367 | bus->drvr->tickcnt++; | |
4368 | } else | |
4369 | break; | |
4370 | } | |
4371 | return 0; | |
4372 | } | |
4373 | ||
4374 | static void | |
4375 | brcmf_sdbrcm_watchdog(unsigned long data) | |
4376 | { | |
4377 | struct brcmf_bus *bus = (struct brcmf_bus *)data; | |
4378 | ||
4379 | if (bus->watchdog_tsk) { | |
4380 | complete(&bus->watchdog_wait); | |
4381 | /* Reschedule the watchdog */ | |
4382 | if (bus->wd_timer_valid) | |
4383 | mod_timer(&bus->timer, | |
4384 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
4385 | } | |
4386 | } | |
4387 | ||
4388 | static void | |
4389 | brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus) | |
4390 | { | |
4391 | brcmf_dbg(TRACE, "Enter\n"); | |
4392 | ||
4393 | kfree(bus->ci); | |
4394 | bus->ci = NULL; | |
4395 | } | |
4396 | ||
4397 | static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus) | |
4398 | { | |
4399 | brcmf_dbg(TRACE, "Enter\n"); | |
4400 | ||
4401 | if (bus->ci) { | |
4402 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
4403 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
4404 | brcmf_sdbrcm_chip_detach(bus); | |
4405 | if (bus->vars && bus->varsz) | |
4406 | kfree(bus->vars); | |
4407 | bus->vars = NULL; | |
4408 | } | |
4409 | ||
4410 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4411 | } | |
4412 | ||
4413 | /* Detach and free everything */ | |
4414 | static void brcmf_sdbrcm_release(struct brcmf_bus *bus) | |
4415 | { | |
4416 | brcmf_dbg(TRACE, "Enter\n"); | |
4417 | ||
4418 | if (bus) { | |
4419 | /* De-register interrupt handler */ | |
4420 | brcmf_sdcard_intr_dereg(bus->sdiodev); | |
4421 | ||
4422 | if (bus->drvr) { | |
4423 | brcmf_detach(bus->drvr); | |
4424 | brcmf_sdbrcm_release_dongle(bus); | |
4425 | bus->drvr = NULL; | |
4426 | } | |
4427 | ||
4428 | brcmf_sdbrcm_release_malloc(bus); | |
4429 | ||
4430 | kfree(bus); | |
4431 | } | |
4432 | ||
4433 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4434 | } | |
4435 | ||
4436 | void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype, | |
4437 | u32 regsva, struct brcmf_sdio_dev *sdiodev) | |
4438 | { | |
4439 | int ret; | |
4440 | struct brcmf_bus *bus; | |
4441 | ||
4442 | /* Init global variables at run-time, not as part of the declaration. | |
4443 | * This is required to support init/de-init of the driver. | |
4444 | * Initialization | |
4445 | * of globals as part of the declaration results in non-deterministic | |
4446 | * behavior since the value of the globals may be different on the | |
4447 | * first time that the driver is initialized vs subsequent | |
4448 | * initializations. | |
4449 | */ | |
4450 | brcmf_c_init(); | |
4451 | ||
4452 | brcmf_dbg(TRACE, "Enter\n"); | |
4453 | ||
4454 | /* We make an assumption about address window mappings: | |
4455 | * regsva == SI_ENUM_BASE*/ | |
4456 | ||
4457 | /* Allocate private bus interface state */ | |
4458 | bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC); | |
4459 | if (!bus) | |
4460 | goto fail; | |
4461 | ||
4462 | bus->sdiodev = sdiodev; | |
4463 | sdiodev->bus = bus; | |
4464 | bus->txbound = BRCMF_TXBOUND; | |
4465 | bus->rxbound = BRCMF_RXBOUND; | |
4466 | bus->txminmax = BRCMF_TXMINMAX; | |
4467 | bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1; | |
4468 | bus->usebufpool = false; /* Use bufpool if allocated, | |
4469 | else use locally malloced rxbuf */ | |
4470 | ||
4471 | /* attempt to attach to the dongle */ | |
4472 | if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) { | |
4473 | brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n"); | |
4474 | goto fail; | |
4475 | } | |
4476 | ||
4477 | spin_lock_init(&bus->txqlock); | |
4478 | init_waitqueue_head(&bus->ctrl_wait); | |
4479 | init_waitqueue_head(&bus->dcmd_resp_wait); | |
4480 | ||
4481 | /* Set up the watchdog timer */ | |
4482 | init_timer(&bus->timer); | |
4483 | bus->timer.data = (unsigned long)bus; | |
4484 | bus->timer.function = brcmf_sdbrcm_watchdog; | |
4485 | ||
4486 | /* Initialize thread based operation and lock */ | |
4487 | sema_init(&bus->sdsem, 1); | |
4488 | ||
4489 | /* Initialize watchdog thread */ | |
4490 | init_completion(&bus->watchdog_wait); | |
4491 | bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread, | |
4492 | bus, "brcmf_watchdog"); | |
4493 | if (IS_ERR(bus->watchdog_tsk)) { | |
4494 | printk(KERN_WARNING | |
4495 | "brcmf_watchdog thread failed to start\n"); | |
4496 | bus->watchdog_tsk = NULL; | |
4497 | } | |
4498 | /* Initialize DPC thread */ | |
4499 | init_completion(&bus->dpc_wait); | |
4500 | bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread, | |
4501 | bus, "brcmf_dpc"); | |
4502 | if (IS_ERR(bus->dpc_tsk)) { | |
4503 | printk(KERN_WARNING | |
4504 | "brcmf_dpc thread failed to start\n"); | |
4505 | bus->dpc_tsk = NULL; | |
4506 | } | |
4507 | ||
4508 | /* Attach to the brcmf/OS/network interface */ | |
4509 | bus->drvr = brcmf_attach(bus, SDPCM_RESERVE); | |
4510 | if (!bus->drvr) { | |
4511 | brcmf_dbg(ERROR, "brcmf_attach failed\n"); | |
4512 | goto fail; | |
4513 | } | |
4514 | ||
4515 | /* Allocate buffers */ | |
4516 | if (!(brcmf_sdbrcm_probe_malloc(bus))) { | |
4517 | brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n"); | |
4518 | goto fail; | |
4519 | } | |
4520 | ||
4521 | if (!(brcmf_sdbrcm_probe_init(bus))) { | |
4522 | brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n"); | |
4523 | goto fail; | |
4524 | } | |
4525 | ||
4526 | /* Register interrupt callback, but mask it (not operational yet). */ | |
4527 | brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n"); | |
4528 | ret = brcmf_sdcard_intr_reg(bus->sdiodev); | |
4529 | if (ret != 0) { | |
4530 | brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret); | |
4531 | goto fail; | |
4532 | } | |
4533 | brcmf_dbg(INTR, "registered SDIO interrupt function ok\n"); | |
4534 | ||
4535 | brcmf_dbg(INFO, "completed!!\n"); | |
4536 | ||
4537 | /* if firmware path present try to download and bring up bus */ | |
4538 | ret = brcmf_bus_start(bus->drvr); | |
4539 | if (ret != 0) { | |
4540 | if (ret == -ENOLINK) { | |
4541 | brcmf_dbg(ERROR, "dongle is not responding\n"); | |
4542 | goto fail; | |
4543 | } | |
4544 | } | |
4545 | /* Ok, have the per-port tell the stack we're open for business */ | |
4546 | if (brcmf_net_attach(bus->drvr, 0) != 0) { | |
4547 | brcmf_dbg(ERROR, "Net attach failed!!\n"); | |
4548 | goto fail; | |
4549 | } | |
4550 | ||
4551 | return bus; | |
4552 | ||
4553 | fail: | |
4554 | brcmf_sdbrcm_release(bus); | |
4555 | return NULL; | |
4556 | } | |
4557 | ||
4558 | void brcmf_sdbrcm_disconnect(void *ptr) | |
4559 | { | |
4560 | struct brcmf_bus *bus = (struct brcmf_bus *)ptr; | |
4561 | ||
4562 | brcmf_dbg(TRACE, "Enter\n"); | |
4563 | ||
4564 | if (bus) | |
4565 | brcmf_sdbrcm_release(bus); | |
4566 | ||
4567 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4568 | } | |
4569 | ||
4570 | struct device *brcmf_bus_get_device(struct brcmf_bus *bus) | |
4571 | { | |
4572 | return &bus->sdiodev->func[2]->dev; | |
4573 | } | |
4574 | ||
4575 | void | |
4576 | brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick) | |
4577 | { | |
4578 | /* don't start the wd until fw is loaded */ | |
4579 | if (bus->drvr->busstate == BRCMF_BUS_DOWN) | |
4580 | return; | |
4581 | ||
4582 | /* Totally stop the timer */ | |
4583 | if (!wdtick && bus->wd_timer_valid == true) { | |
4584 | del_timer_sync(&bus->timer); | |
4585 | bus->wd_timer_valid = false; | |
4586 | bus->save_ms = wdtick; | |
4587 | return; | |
4588 | } | |
4589 | ||
4590 | if (wdtick) { | |
4591 | if (bus->save_ms != BRCMF_WD_POLL_MS) { | |
4592 | if (bus->wd_timer_valid == true) | |
4593 | /* Stop timer and restart at new value */ | |
4594 | del_timer_sync(&bus->timer); | |
4595 | ||
4596 | /* Create timer again when watchdog period is | |
4597 | dynamically changed or in the first instance | |
4598 | */ | |
4599 | bus->timer.expires = | |
4600 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000; | |
4601 | add_timer(&bus->timer); | |
4602 | ||
4603 | } else { | |
4604 | /* Re arm the timer, at last watchdog period */ | |
4605 | mod_timer(&bus->timer, | |
4606 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
4607 | } | |
4608 | ||
4609 | bus->wd_timer_valid = true; | |
4610 | bus->save_ms = wdtick; | |
4611 | } | |
4612 | } |