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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/printk.h> | |
21 | #include <linux/pci_ids.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/mmc/sdio.h> | |
cb7cf7be | 26 | #include <linux/mmc/sdio_ids.h> |
5b435de0 AS |
27 | #include <linux/mmc/sdio_func.h> |
28 | #include <linux/mmc/card.h> | |
29 | #include <linux/semaphore.h> | |
30 | #include <linux/firmware.h> | |
b7a57e76 | 31 | #include <linux/module.h> |
99ba15cd | 32 | #include <linux/bcma/bcma.h> |
4fc0d016 | 33 | #include <linux/debugfs.h> |
8dc01811 | 34 | #include <linux/vmalloc.h> |
668761ac | 35 | #include <linux/platform_data/brcmfmac-sdio.h> |
8da9d2c8 | 36 | #include <linux/moduleparam.h> |
5b435de0 AS |
37 | #include <asm/unaligned.h> |
38 | #include <defs.h> | |
39 | #include <brcmu_wifi.h> | |
40 | #include <brcmu_utils.h> | |
41 | #include <brcm_hw_ids.h> | |
42 | #include <soc.h> | |
888bf76e | 43 | #include "sdio.h" |
20c9c9bc | 44 | #include "chip.h" |
dabedab9 | 45 | #include "firmware.h" |
5b435de0 | 46 | |
4dd8b26a HM |
47 | #define DCMD_RESP_TIMEOUT 2000 /* In milli second */ |
48 | #define CTL_DONE_TIMEOUT 2000 /* In milli second */ | |
5b435de0 | 49 | |
8ae74654 | 50 | #ifdef DEBUG |
5b435de0 AS |
51 | |
52 | #define BRCMF_TRAP_INFO_SIZE 80 | |
53 | ||
54 | #define CBUF_LEN (128) | |
55 | ||
4fc0d016 AS |
56 | /* Device console log buffer state */ |
57 | #define CONSOLE_BUFFER_MAX 2024 | |
58 | ||
5b435de0 AS |
59 | struct rte_log_le { |
60 | __le32 buf; /* Can't be pointer on (64-bit) hosts */ | |
61 | __le32 buf_size; | |
62 | __le32 idx; | |
63 | char *_buf_compat; /* Redundant pointer for backward compat. */ | |
64 | }; | |
65 | ||
66 | struct rte_console { | |
67 | /* Virtual UART | |
68 | * When there is no UART (e.g. Quickturn), | |
69 | * the host should write a complete | |
70 | * input line directly into cbuf and then write | |
71 | * the length into vcons_in. | |
72 | * This may also be used when there is a real UART | |
73 | * (at risk of conflicting with | |
74 | * the real UART). vcons_out is currently unused. | |
75 | */ | |
76 | uint vcons_in; | |
77 | uint vcons_out; | |
78 | ||
79 | /* Output (logging) buffer | |
80 | * Console output is written to a ring buffer log_buf at index log_idx. | |
81 | * The host may read the output when it sees log_idx advance. | |
82 | * Output will be lost if the output wraps around faster than the host | |
83 | * polls. | |
84 | */ | |
85 | struct rte_log_le log_le; | |
86 | ||
87 | /* Console input line buffer | |
88 | * Characters are read one at a time into cbuf | |
89 | * until <CR> is received, then | |
90 | * the buffer is processed as a command line. | |
91 | * Also used for virtual UART. | |
92 | */ | |
93 | uint cbuf_idx; | |
94 | char cbuf[CBUF_LEN]; | |
95 | }; | |
96 | ||
8ae74654 | 97 | #endif /* DEBUG */ |
5b435de0 AS |
98 | #include <chipcommon.h> |
99 | ||
d14f78b9 | 100 | #include "bus.h" |
a8e8ed34 | 101 | #include "debug.h" |
40c1c249 | 102 | #include "tracepoint.h" |
5b435de0 AS |
103 | |
104 | #define TXQLEN 2048 /* bulk tx queue length */ | |
105 | #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ | |
106 | #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ | |
107 | #define PRIOMASK 7 | |
108 | ||
109 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
110 | ||
111 | #define BRCMF_RXBOUND 50 /* Default for max rx frames in | |
112 | one scheduling */ | |
113 | ||
114 | #define BRCMF_TXBOUND 20 /* Default for max tx frames in | |
115 | one scheduling */ | |
116 | ||
117 | #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ | |
118 | ||
119 | #define MEMBLOCK 2048 /* Block size used for downloading | |
120 | of dongle image */ | |
121 | #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold | |
122 | biggest possible glom */ | |
123 | ||
124 | #define BRCMF_FIRSTREAD (1 << 6) | |
125 | ||
9d6c1dc4 | 126 | #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */ |
5b435de0 AS |
127 | |
128 | /* SBSDIO_DEVICE_CTL */ | |
129 | ||
130 | /* 1: device will assert busy signal when receiving CMD53 */ | |
131 | #define SBSDIO_DEVCTL_SETBUSY 0x01 | |
132 | /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ | |
133 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 | |
134 | /* 1: mask all interrupts to host except the chipActive (rev 8) */ | |
135 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 | |
136 | /* 1: isolate internal sdio signals, put external pads in tri-state; requires | |
137 | * sdio bus power cycle to clear (rev 9) */ | |
138 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 | |
139 | /* Force SD->SB reset mapping (rev 11) */ | |
140 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 | |
141 | /* Determined by CoreControl bit */ | |
142 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 | |
143 | /* Force backplane reset */ | |
144 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 | |
145 | /* Force no backplane reset */ | |
146 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 | |
147 | ||
5b435de0 AS |
148 | /* direct(mapped) cis space */ |
149 | ||
150 | /* MAPPED common CIS address */ | |
151 | #define SBSDIO_CIS_BASE_COMMON 0x1000 | |
152 | /* maximum bytes in one CIS */ | |
153 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 | |
154 | /* cis offset addr is < 17 bits */ | |
155 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF | |
156 | ||
157 | /* manfid tuple length, include tuple, link bytes */ | |
158 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 | |
159 | ||
cb7cf7be AS |
160 | #define CORE_BUS_REG(base, field) \ |
161 | (base + offsetof(struct sdpcmd_regs, field)) | |
162 | ||
163 | /* SDIO function 1 register CHIPCLKCSR */ | |
164 | /* Force ALP request to backplane */ | |
165 | #define SBSDIO_FORCE_ALP 0x01 | |
166 | /* Force HT request to backplane */ | |
167 | #define SBSDIO_FORCE_HT 0x02 | |
168 | /* Force ILP request to backplane */ | |
169 | #define SBSDIO_FORCE_ILP 0x04 | |
170 | /* Make ALP ready (power up xtal) */ | |
171 | #define SBSDIO_ALP_AVAIL_REQ 0x08 | |
172 | /* Make HT ready (power up PLL) */ | |
173 | #define SBSDIO_HT_AVAIL_REQ 0x10 | |
174 | /* Squelch clock requests from HW */ | |
175 | #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 | |
176 | /* Status: ALP is ready */ | |
177 | #define SBSDIO_ALP_AVAIL 0x40 | |
178 | /* Status: HT is ready */ | |
179 | #define SBSDIO_HT_AVAIL 0x80 | |
8a385ba5 | 180 | #define SBSDIO_CSR_MASK 0x1F |
cb7cf7be AS |
181 | #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) |
182 | #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) | |
183 | #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) | |
184 | #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) | |
185 | #define SBSDIO_CLKAV(regval, alponly) \ | |
186 | (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) | |
187 | ||
5b435de0 AS |
188 | /* intstatus */ |
189 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | |
190 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | |
191 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | |
192 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | |
193 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | |
194 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | |
195 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | |
196 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | |
197 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | |
198 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | |
199 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | |
200 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | |
201 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | |
202 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | |
203 | #define I_PC (1 << 10) /* descriptor error */ | |
204 | #define I_PD (1 << 11) /* data error */ | |
205 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | |
206 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | |
207 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | |
208 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | |
209 | #define I_RI (1 << 16) /* Receive Interrupt */ | |
210 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | |
211 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | |
212 | #define I_XI (1 << 24) /* Transmit Interrupt */ | |
213 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | |
214 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | |
215 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | |
216 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | |
217 | #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ | |
218 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | |
219 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | |
220 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) | |
221 | #define I_DMA (I_RI | I_XI | I_ERRORS) | |
222 | ||
223 | /* corecontrol */ | |
224 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | |
225 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ | |
226 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | |
227 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ | |
228 | #define CC_XMTDATAAVAIL_MODE (1 << 4) | |
229 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) | |
230 | ||
231 | /* SDA_FRAMECTRL */ | |
232 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | |
233 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | |
234 | #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ | |
235 | #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ | |
236 | ||
5b435de0 AS |
237 | /* |
238 | * Software allocation of To SB Mailbox resources | |
239 | */ | |
240 | ||
241 | /* tosbmailbox bits corresponding to intstatus bits */ | |
242 | #define SMB_NAK (1 << 0) /* Frame NAK */ | |
243 | #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ | |
244 | #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ | |
245 | #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ | |
246 | ||
247 | /* tosbmailboxdata */ | |
248 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ | |
249 | ||
250 | /* | |
251 | * Software allocation of To Host Mailbox resources | |
252 | */ | |
253 | ||
254 | /* intstatus bits */ | |
255 | #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ | |
256 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ | |
257 | #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ | |
258 | #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ | |
259 | ||
260 | /* tohostmailboxdata */ | |
261 | #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ | |
262 | #define HMB_DATA_DEVREADY 2 /* talk to host after enable */ | |
263 | #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ | |
264 | #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ | |
265 | ||
266 | #define HMB_DATA_FCDATA_MASK 0xff000000 | |
267 | #define HMB_DATA_FCDATA_SHIFT 24 | |
268 | ||
269 | #define HMB_DATA_VERSION_MASK 0x00ff0000 | |
270 | #define HMB_DATA_VERSION_SHIFT 16 | |
271 | ||
272 | /* | |
273 | * Software-defined protocol header | |
274 | */ | |
275 | ||
276 | /* Current protocol version */ | |
277 | #define SDPCM_PROT_VERSION 4 | |
278 | ||
5b435de0 AS |
279 | /* |
280 | * Shared structure between dongle and the host. | |
281 | * The structure contains pointers to trap or assert information. | |
282 | */ | |
4fc0d016 | 283 | #define SDPCM_SHARED_VERSION 0x0003 |
5b435de0 AS |
284 | #define SDPCM_SHARED_VERSION_MASK 0x00FF |
285 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | |
286 | #define SDPCM_SHARED_ASSERT 0x0200 | |
287 | #define SDPCM_SHARED_TRAP 0x0400 | |
288 | ||
289 | /* Space for header read, limit for data packets */ | |
290 | #define MAX_HDR_READ (1 << 6) | |
291 | #define MAX_RX_DATASZ 2048 | |
292 | ||
5b435de0 AS |
293 | /* Bump up limit on waiting for HT to account for first startup; |
294 | * if the image is doing a CRC calculation before programming the PMU | |
295 | * for HT availability, it could take a couple hundred ms more, so | |
296 | * max out at a 1 second (1000000us). | |
297 | */ | |
298 | #undef PMU_MAX_TRANSITION_DLY | |
299 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
300 | ||
301 | /* Value for ChipClockCSR during initial setup */ | |
302 | #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ | |
303 | SBSDIO_ALP_AVAIL_REQ) | |
304 | ||
305 | /* Flags for SDH calls */ | |
306 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
307 | ||
382a9e0f FL |
308 | #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change |
309 | * when idle | |
310 | */ | |
311 | #define BRCMF_IDLE_INTERVAL 1 | |
312 | ||
4a3da990 PH |
313 | #define KSO_WAIT_US 50 |
314 | #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) | |
315 | ||
5b435de0 AS |
316 | /* |
317 | * Conversion of 802.1D priority to precedence level | |
318 | */ | |
319 | static uint prio2prec(u32 prio) | |
320 | { | |
321 | return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? | |
322 | (prio^2) : prio; | |
323 | } | |
324 | ||
8ae74654 | 325 | #ifdef DEBUG |
5b435de0 AS |
326 | /* Device console log buffer state */ |
327 | struct brcmf_console { | |
328 | uint count; /* Poll interval msec counter */ | |
329 | uint log_addr; /* Log struct address (fixed) */ | |
330 | struct rte_log_le log_le; /* Log struct (host copy) */ | |
331 | uint bufsize; /* Size of log buffer */ | |
332 | u8 *buf; /* Log buffer (host copy) */ | |
333 | uint last; /* Last buffer read index */ | |
334 | }; | |
4fc0d016 AS |
335 | |
336 | struct brcmf_trap_info { | |
337 | __le32 type; | |
338 | __le32 epc; | |
339 | __le32 cpsr; | |
340 | __le32 spsr; | |
341 | __le32 r0; /* a1 */ | |
342 | __le32 r1; /* a2 */ | |
343 | __le32 r2; /* a3 */ | |
344 | __le32 r3; /* a4 */ | |
345 | __le32 r4; /* v1 */ | |
346 | __le32 r5; /* v2 */ | |
347 | __le32 r6; /* v3 */ | |
348 | __le32 r7; /* v4 */ | |
349 | __le32 r8; /* v5 */ | |
350 | __le32 r9; /* sb/v6 */ | |
351 | __le32 r10; /* sl/v7 */ | |
352 | __le32 r11; /* fp/v8 */ | |
353 | __le32 r12; /* ip */ | |
354 | __le32 r13; /* sp */ | |
355 | __le32 r14; /* lr */ | |
356 | __le32 pc; /* r15 */ | |
357 | }; | |
8ae74654 | 358 | #endif /* DEBUG */ |
5b435de0 AS |
359 | |
360 | struct sdpcm_shared { | |
361 | u32 flags; | |
362 | u32 trap_addr; | |
363 | u32 assert_exp_addr; | |
364 | u32 assert_file_addr; | |
365 | u32 assert_line; | |
366 | u32 console_addr; /* Address of struct rte_console */ | |
367 | u32 msgtrace_addr; | |
368 | u8 tag[32]; | |
4fc0d016 | 369 | u32 brpt_addr; |
5b435de0 AS |
370 | }; |
371 | ||
372 | struct sdpcm_shared_le { | |
373 | __le32 flags; | |
374 | __le32 trap_addr; | |
375 | __le32 assert_exp_addr; | |
376 | __le32 assert_file_addr; | |
377 | __le32 assert_line; | |
378 | __le32 console_addr; /* Address of struct rte_console */ | |
379 | __le32 msgtrace_addr; | |
380 | u8 tag[32]; | |
4fc0d016 | 381 | __le32 brpt_addr; |
5b435de0 AS |
382 | }; |
383 | ||
6bc52319 FL |
384 | /* dongle SDIO bus specific header info */ |
385 | struct brcmf_sdio_hdrinfo { | |
4754fcee FL |
386 | u8 seq_num; |
387 | u8 channel; | |
388 | u16 len; | |
389 | u16 len_left; | |
390 | u16 len_nxtfrm; | |
391 | u8 dat_offset; | |
8da9d2c8 FL |
392 | bool lastfrm; |
393 | u16 tail_pad; | |
4754fcee | 394 | }; |
5b435de0 | 395 | |
82d957e0 AS |
396 | /* |
397 | * hold counter variables | |
398 | */ | |
399 | struct brcmf_sdio_count { | |
400 | uint intrcount; /* Count of device interrupt callbacks */ | |
401 | uint lastintrs; /* Count as of last watchdog timer */ | |
402 | uint pollcnt; /* Count of active polls */ | |
403 | uint regfails; /* Count of R_REG failures */ | |
404 | uint tx_sderrs; /* Count of tx attempts with sd errors */ | |
405 | uint fcqueued; /* Tx packets that got queued */ | |
406 | uint rxrtx; /* Count of rtx requests (NAK to dongle) */ | |
407 | uint rx_toolong; /* Receive frames too long to receive */ | |
408 | uint rxc_errors; /* SDIO errors when reading control frames */ | |
409 | uint rx_hdrfail; /* SDIO errors on header reads */ | |
410 | uint rx_badhdr; /* Bad received headers (roosync?) */ | |
411 | uint rx_badseq; /* Mismatched rx sequence number */ | |
412 | uint fc_rcvd; /* Number of flow-control events received */ | |
413 | uint fc_xoff; /* Number which turned on flow-control */ | |
414 | uint fc_xon; /* Number which turned off flow-control */ | |
415 | uint rxglomfail; /* Failed deglom attempts */ | |
416 | uint rxglomframes; /* Number of glom frames (superframes) */ | |
417 | uint rxglompkts; /* Number of packets from glom frames */ | |
418 | uint f2rxhdrs; /* Number of header reads */ | |
419 | uint f2rxdata; /* Number of frame data reads */ | |
420 | uint f2txdata; /* Number of f2 frame writes */ | |
421 | uint f1regdata; /* Number of f1 register accesses */ | |
422 | uint tickcnt; /* Number of watchdog been schedule */ | |
423 | ulong tx_ctlerrs; /* Err of sending ctrl frames */ | |
424 | ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ | |
425 | ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ | |
426 | ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ | |
427 | ulong rx_readahead_cnt; /* packets where header read-ahead was used */ | |
428 | }; | |
429 | ||
5b435de0 | 430 | /* misc chip info needed by some of the routines */ |
5b435de0 | 431 | /* Private data for SDIO bus interaction */ |
e92eedf4 | 432 | struct brcmf_sdio { |
5b435de0 | 433 | struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ |
9cf218fc | 434 | struct brcmf_chip *ci; /* Chip info struct */ |
5b435de0 | 435 | |
5b435de0 | 436 | u32 hostintmask; /* Copy of Host Interrupt Mask */ |
4531603a FL |
437 | atomic_t intstatus; /* Intstatus bits (events) pending */ |
438 | atomic_t fcstate; /* State of dongle flow-control */ | |
5b435de0 AS |
439 | |
440 | uint blocksize; /* Block size of SDIO transfers */ | |
441 | uint roundup; /* Max roundup limit */ | |
442 | ||
443 | struct pktq txq; /* Queue length used for flow-control */ | |
444 | u8 flowcontrol; /* per prio flow control bitmask */ | |
445 | u8 tx_seq; /* Transmit sequence number (next) */ | |
446 | u8 tx_max; /* Maximum transmit sequence allowed */ | |
447 | ||
9b2d2f2a | 448 | u8 *hdrbuf; /* buffer for handling rx frame */ |
5b435de0 | 449 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ |
5b435de0 | 450 | u8 rx_seq; /* Receive sequence number (expected) */ |
6bc52319 | 451 | struct brcmf_sdio_hdrinfo cur_read; |
4754fcee | 452 | /* info of current read frame */ |
5b435de0 | 453 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ |
4754fcee | 454 | bool rxpending; /* Data frame pending in dongle */ |
5b435de0 AS |
455 | |
456 | uint rxbound; /* Rx frames to read before resched */ | |
457 | uint txbound; /* Tx frames to send before resched */ | |
458 | uint txminmax; | |
459 | ||
460 | struct sk_buff *glomd; /* Packet containing glomming descriptor */ | |
b83db862 | 461 | struct sk_buff_head glom; /* Packet list for glommed superframe */ |
5b435de0 AS |
462 | uint glomerr; /* Glom packet read errors */ |
463 | ||
464 | u8 *rxbuf; /* Buffer for receiving control packets */ | |
465 | uint rxblen; /* Allocated length of rxbuf */ | |
466 | u8 *rxctl; /* Aligned pointer into rxbuf */ | |
dd43a01c | 467 | u8 *rxctl_orig; /* pointer for freeing rxctl */ |
5b435de0 | 468 | uint rxlen; /* Length of valid data in buffer */ |
dd43a01c | 469 | spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ |
5b435de0 AS |
470 | |
471 | u8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
472 | ||
473 | bool intr; /* Use interrupts */ | |
474 | bool poll; /* Use polling */ | |
1d382273 | 475 | atomic_t ipend; /* Device interrupt is pending */ |
5b435de0 AS |
476 | uint spurious; /* Count of spurious interrupts */ |
477 | uint pollrate; /* Ticks between device polls */ | |
478 | uint polltick; /* Tick counter */ | |
5b435de0 | 479 | |
8ae74654 | 480 | #ifdef DEBUG |
5b435de0 AS |
481 | uint console_interval; |
482 | struct brcmf_console console; /* Console output polling support */ | |
483 | uint console_addr; /* Console address from shared struct */ | |
8ae74654 | 484 | #endif /* DEBUG */ |
5b435de0 | 485 | |
5b435de0 | 486 | uint clkstate; /* State of sd and backplane clock(s) */ |
5b435de0 | 487 | s32 idletime; /* Control for activity timeout */ |
b441ba8d HM |
488 | s32 idlecount; /* Activity timeout counter */ |
489 | s32 idleclock; /* How to set bus driver when idle */ | |
5b435de0 AS |
490 | bool rxflow_mode; /* Rx flow control mode */ |
491 | bool rxflow; /* Is rx flow control on */ | |
492 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
5b435de0 | 493 | |
5b435de0 | 494 | u8 *ctrl_frame_buf; |
fed7ec44 | 495 | u16 ctrl_frame_len; |
5b435de0 | 496 | bool ctrl_frame_stat; |
4dd8b26a | 497 | int ctrl_frame_err; |
5b435de0 | 498 | |
fed7ec44 | 499 | spinlock_t txq_lock; /* protect bus->txq */ |
5b435de0 AS |
500 | wait_queue_head_t ctrl_wait; |
501 | wait_queue_head_t dcmd_resp_wait; | |
502 | ||
503 | struct timer_list timer; | |
504 | struct completion watchdog_wait; | |
505 | struct task_struct *watchdog_tsk; | |
506 | bool wd_timer_valid; | |
507 | uint save_ms; | |
508 | ||
f1e68c2e FL |
509 | struct workqueue_struct *brcmf_wq; |
510 | struct work_struct datawork; | |
2c64e16d HM |
511 | bool dpc_triggered; |
512 | bool dpc_running; | |
5b435de0 | 513 | |
c8bf3484 | 514 | bool txoff; /* Transmit flow-controlled */ |
80969836 | 515 | struct brcmf_sdio_count sdcnt; |
4a3da990 | 516 | bool sr_enabled; /* SaveRestore enabled */ |
99824643 | 517 | bool sleeping; |
706478cb FL |
518 | |
519 | u8 tx_hdrlen; /* sdio bus header length for tx packet */ | |
8da9d2c8 | 520 | bool txglom; /* host tx glomming enable flag */ |
e217d1c8 AS |
521 | u16 head_align; /* buffer pointer alignment */ |
522 | u16 sgentry_align; /* scatter-gather buffer alignment */ | |
5b435de0 AS |
523 | }; |
524 | ||
5b435de0 AS |
525 | /* clkstate */ |
526 | #define CLK_NONE 0 | |
527 | #define CLK_SDONLY 1 | |
4a3da990 | 528 | #define CLK_PENDING 2 |
5b435de0 AS |
529 | #define CLK_AVAIL 3 |
530 | ||
8ae74654 | 531 | #ifdef DEBUG |
5b435de0 | 532 | static int qcount[NUMPRIO]; |
8ae74654 | 533 | #endif /* DEBUG */ |
5b435de0 | 534 | |
668761ac | 535 | #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ |
5b435de0 AS |
536 | |
537 | #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) | |
538 | ||
539 | /* Retry count for register access failures */ | |
540 | static const uint retry_limit = 2; | |
541 | ||
542 | /* Limit on rounding up frames */ | |
543 | static const uint max_roundup = 512; | |
544 | ||
545 | #define ALIGNMENT 4 | |
546 | ||
9d7d6f95 FL |
547 | enum brcmf_sdio_frmtype { |
548 | BRCMF_SDIO_FT_NORMAL, | |
549 | BRCMF_SDIO_FT_SUPER, | |
550 | BRCMF_SDIO_FT_SUB, | |
551 | }; | |
552 | ||
65d80d0b AS |
553 | #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) |
554 | ||
555 | /* SDIO Pad drive strength to select value mappings */ | |
556 | struct sdiod_drive_str { | |
557 | u8 strength; /* Pad Drive Strength in mA */ | |
558 | u8 sel; /* Chip-specific select value */ | |
559 | }; | |
560 | ||
561 | /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ | |
562 | static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { | |
563 | {32, 0x6}, | |
564 | {26, 0x7}, | |
565 | {22, 0x4}, | |
566 | {16, 0x5}, | |
567 | {12, 0x2}, | |
568 | {8, 0x3}, | |
569 | {4, 0x0}, | |
570 | {0, 0x1} | |
571 | }; | |
572 | ||
573 | /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ | |
574 | static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { | |
575 | {6, 0x7}, | |
576 | {5, 0x6}, | |
577 | {4, 0x5}, | |
578 | {3, 0x4}, | |
579 | {2, 0x2}, | |
580 | {1, 0x1}, | |
581 | {0, 0x0} | |
582 | }; | |
583 | ||
584 | /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ | |
585 | static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { | |
586 | {3, 0x3}, | |
587 | {2, 0x2}, | |
588 | {1, 0x1}, | |
589 | {0, 0x0} }; | |
590 | ||
591 | /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ | |
592 | static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { | |
593 | {16, 0x7}, | |
594 | {12, 0x5}, | |
595 | {8, 0x3}, | |
596 | {4, 0x1} | |
597 | }; | |
598 | ||
f2c44fe7 HM |
599 | #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin" |
600 | #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt" | |
601 | #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin" | |
602 | #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt" | |
603 | #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin" | |
604 | #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt" | |
ba5e8665 AS |
605 | #define BCM43241B5_FIRMWARE_NAME "brcm/brcmfmac43241b5-sdio.bin" |
606 | #define BCM43241B5_NVRAM_NAME "brcm/brcmfmac43241b5-sdio.txt" | |
f2c44fe7 HM |
607 | #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin" |
608 | #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt" | |
609 | #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin" | |
610 | #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt" | |
611 | #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin" | |
612 | #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt" | |
8b3a38da AS |
613 | #define BCM43340_FIRMWARE_NAME "brcm/brcmfmac43340-sdio.bin" |
614 | #define BCM43340_NVRAM_NAME "brcm/brcmfmac43340-sdio.txt" | |
f2c44fe7 HM |
615 | #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin" |
616 | #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt" | |
11e69c36 AS |
617 | #define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin" |
618 | #define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt" | |
bed89b64 FL |
619 | #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin" |
620 | #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt" | |
25911556 AS |
621 | #define BCM43430_FIRMWARE_NAME "brcm/brcmfmac43430-sdio.bin" |
622 | #define BCM43430_NVRAM_NAME "brcm/brcmfmac43430-sdio.txt" | |
228a7176 AS |
623 | #define BCM43455_FIRMWARE_NAME "brcm/brcmfmac43455-sdio.bin" |
624 | #define BCM43455_NVRAM_NAME "brcm/brcmfmac43455-sdio.txt" | |
a797ca1e FL |
625 | #define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin" |
626 | #define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt" | |
f2c44fe7 HM |
627 | |
628 | MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME); | |
629 | MODULE_FIRMWARE(BCM43143_NVRAM_NAME); | |
630 | MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME); | |
631 | MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME); | |
632 | MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME); | |
633 | MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME); | |
ba5e8665 AS |
634 | MODULE_FIRMWARE(BCM43241B5_FIRMWARE_NAME); |
635 | MODULE_FIRMWARE(BCM43241B5_NVRAM_NAME); | |
f2c44fe7 HM |
636 | MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME); |
637 | MODULE_FIRMWARE(BCM4329_NVRAM_NAME); | |
638 | MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME); | |
639 | MODULE_FIRMWARE(BCM4330_NVRAM_NAME); | |
640 | MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME); | |
641 | MODULE_FIRMWARE(BCM4334_NVRAM_NAME); | |
8b3a38da AS |
642 | MODULE_FIRMWARE(BCM43340_FIRMWARE_NAME); |
643 | MODULE_FIRMWARE(BCM43340_NVRAM_NAME); | |
f2c44fe7 HM |
644 | MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME); |
645 | MODULE_FIRMWARE(BCM4335_NVRAM_NAME); | |
11e69c36 AS |
646 | MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME); |
647 | MODULE_FIRMWARE(BCM43362_NVRAM_NAME); | |
bed89b64 FL |
648 | MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME); |
649 | MODULE_FIRMWARE(BCM4339_NVRAM_NAME); | |
25911556 AS |
650 | MODULE_FIRMWARE(BCM43430_FIRMWARE_NAME); |
651 | MODULE_FIRMWARE(BCM43430_NVRAM_NAME); | |
228a7176 AS |
652 | MODULE_FIRMWARE(BCM43455_FIRMWARE_NAME); |
653 | MODULE_FIRMWARE(BCM43455_NVRAM_NAME); | |
a797ca1e FL |
654 | MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME); |
655 | MODULE_FIRMWARE(BCM4354_NVRAM_NAME); | |
f2c44fe7 HM |
656 | |
657 | struct brcmf_firmware_names { | |
658 | u32 chipid; | |
659 | u32 revmsk; | |
660 | const char *bin; | |
661 | const char *nv; | |
662 | }; | |
663 | ||
664 | enum brcmf_firmware_type { | |
665 | BRCMF_FIRMWARE_BIN, | |
666 | BRCMF_FIRMWARE_NVRAM | |
667 | }; | |
668 | ||
669 | #define BRCMF_FIRMWARE_NVRAM(name) \ | |
670 | name ## _FIRMWARE_NAME, name ## _NVRAM_NAME | |
671 | ||
672 | static const struct brcmf_firmware_names brcmf_fwname_data[] = { | |
5779ae6a HM |
673 | { BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) }, |
674 | { BRCM_CC_43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) }, | |
ba5e8665 AS |
675 | { BRCM_CC_43241_CHIP_ID, 0x00000020, BRCMF_FIRMWARE_NVRAM(BCM43241B4) }, |
676 | { BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, BRCMF_FIRMWARE_NVRAM(BCM43241B5) }, | |
5779ae6a HM |
677 | { BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) }, |
678 | { BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) }, | |
679 | { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) }, | |
8b3a38da | 680 | { BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) }, |
5779ae6a HM |
681 | { BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) }, |
682 | { BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) }, | |
683 | { BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }, | |
25911556 | 684 | { BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43430) }, |
228a7176 | 685 | { BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, BRCMF_FIRMWARE_NVRAM(BCM43455) }, |
5779ae6a | 686 | { BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) } |
f2c44fe7 HM |
687 | }; |
688 | ||
c1b20532 DK |
689 | static int brcmf_sdio_get_fwnames(struct brcmf_chip *ci, |
690 | struct brcmf_sdio_dev *sdiodev) | |
f2c44fe7 | 691 | { |
bd0e1b1d | 692 | int i; |
46de0683 | 693 | char end; |
f2c44fe7 HM |
694 | |
695 | for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) { | |
bd0e1b1d | 696 | if (brcmf_fwname_data[i].chipid == ci->chip && |
c1b20532 DK |
697 | brcmf_fwname_data[i].revmsk & BIT(ci->chiprev)) |
698 | break; | |
f2c44fe7 | 699 | } |
c1b20532 DK |
700 | |
701 | if (i == ARRAY_SIZE(brcmf_fwname_data)) { | |
702 | brcmf_err("Unknown chipid %d [%d]\n", ci->chip, ci->chiprev); | |
703 | return -ENODEV; | |
704 | } | |
705 | ||
706 | /* check if firmware path is provided by module parameter */ | |
707 | if (brcmf_firmware_path[0] != '\0') { | |
59dfdd92 RS |
708 | strlcpy(sdiodev->fw_name, brcmf_firmware_path, |
709 | sizeof(sdiodev->fw_name)); | |
710 | strlcpy(sdiodev->nvram_name, brcmf_firmware_path, | |
711 | sizeof(sdiodev->nvram_name)); | |
46de0683 DK |
712 | |
713 | end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1]; | |
714 | if (end != '/') { | |
59dfdd92 RS |
715 | strlcat(sdiodev->fw_name, "/", |
716 | sizeof(sdiodev->fw_name)); | |
717 | strlcat(sdiodev->nvram_name, "/", | |
718 | sizeof(sdiodev->nvram_name)); | |
46de0683 | 719 | } |
c1b20532 | 720 | } |
59dfdd92 RS |
721 | strlcat(sdiodev->fw_name, brcmf_fwname_data[i].bin, |
722 | sizeof(sdiodev->fw_name)); | |
723 | strlcat(sdiodev->nvram_name, brcmf_fwname_data[i].nv, | |
724 | sizeof(sdiodev->nvram_name)); | |
c1b20532 DK |
725 | |
726 | return 0; | |
f2c44fe7 HM |
727 | } |
728 | ||
5b435de0 AS |
729 | static void pkt_align(struct sk_buff *p, int len, int align) |
730 | { | |
731 | uint datalign; | |
732 | datalign = (unsigned long)(p->data); | |
733 | datalign = roundup(datalign, (align)) - datalign; | |
734 | if (datalign) | |
735 | skb_pull(p, datalign); | |
736 | __skb_trim(p, len); | |
737 | } | |
738 | ||
739 | /* To check if there's window offered */ | |
e92eedf4 | 740 | static bool data_ok(struct brcmf_sdio *bus) |
5b435de0 AS |
741 | { |
742 | return (u8)(bus->tx_max - bus->tx_seq) != 0 && | |
743 | ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; | |
744 | } | |
745 | ||
746 | /* | |
747 | * Reads a register in the SDIO hardware block. This block occupies a series of | |
748 | * adresses on the 32 bit backplane bus. | |
749 | */ | |
cb7cf7be | 750 | static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset) |
5b435de0 | 751 | { |
cb7cf7be | 752 | struct brcmf_core *core; |
79ae3957 | 753 | int ret; |
58692750 | 754 | |
cb7cf7be AS |
755 | core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
756 | *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret); | |
58692750 FL |
757 | |
758 | return ret; | |
5b435de0 AS |
759 | } |
760 | ||
cb7cf7be | 761 | static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) |
5b435de0 | 762 | { |
cb7cf7be | 763 | struct brcmf_core *core; |
e13ce26b | 764 | int ret; |
58692750 | 765 | |
cb7cf7be AS |
766 | core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
767 | brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret); | |
58692750 FL |
768 | |
769 | return ret; | |
5b435de0 AS |
770 | } |
771 | ||
4a3da990 | 772 | static int |
82d7f3c1 | 773 | brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) |
4a3da990 PH |
774 | { |
775 | u8 wr_val = 0, rd_val, cmp_val, bmask; | |
776 | int err = 0; | |
777 | int try_cnt = 0; | |
778 | ||
8a385ba5 | 779 | brcmf_dbg(TRACE, "Enter: on=%d\n", on); |
4a3da990 PH |
780 | |
781 | wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
782 | /* 1st KSO write goes to AOS wake up core if device is asleep */ | |
a39be27b AS |
783 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
784 | wr_val, &err); | |
4a3da990 PH |
785 | |
786 | if (on) { | |
787 | /* device WAKEUP through KSO: | |
788 | * write bit 0 & read back until | |
789 | * both bits 0 (kso bit) & 1 (dev on status) are set | |
790 | */ | |
791 | cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | | |
792 | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; | |
793 | bmask = cmp_val; | |
794 | usleep_range(2000, 3000); | |
795 | } else { | |
796 | /* Put device to sleep, turn off KSO */ | |
797 | cmp_val = 0; | |
798 | /* only check for bit0, bit1(dev on status) may not | |
799 | * get cleared right away | |
800 | */ | |
801 | bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; | |
802 | } | |
803 | ||
804 | do { | |
805 | /* reliable KSO bit set/clr: | |
806 | * the sdiod sleep write access is synced to PMU 32khz clk | |
807 | * just one write attempt may fail, | |
808 | * read it back until it matches written value | |
809 | */ | |
a39be27b AS |
810 | rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
811 | &err); | |
4a3da990 PH |
812 | if (((rd_val & bmask) == cmp_val) && !err) |
813 | break; | |
8a385ba5 | 814 | |
4a3da990 | 815 | udelay(KSO_WAIT_US); |
a39be27b AS |
816 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
817 | wr_val, &err); | |
4a3da990 PH |
818 | } while (try_cnt++ < MAX_KSO_ATTEMPTS); |
819 | ||
8a385ba5 AS |
820 | if (try_cnt > 2) |
821 | brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, | |
822 | rd_val, err); | |
823 | ||
824 | if (try_cnt > MAX_KSO_ATTEMPTS) | |
825 | brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); | |
826 | ||
4a3da990 PH |
827 | return err; |
828 | } | |
829 | ||
5b435de0 AS |
830 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) |
831 | ||
5b435de0 | 832 | /* Turn backplane clock on or off */ |
82d7f3c1 | 833 | static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) |
5b435de0 AS |
834 | { |
835 | int err; | |
836 | u8 clkctl, clkreq, devctl; | |
837 | unsigned long timeout; | |
838 | ||
c3203374 | 839 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
840 | |
841 | clkctl = 0; | |
842 | ||
4a3da990 PH |
843 | if (bus->sr_enabled) { |
844 | bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); | |
845 | return 0; | |
846 | } | |
847 | ||
5b435de0 AS |
848 | if (on) { |
849 | /* Request HT Avail */ | |
850 | clkreq = | |
851 | bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
852 | ||
a39be27b AS |
853 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
854 | clkreq, &err); | |
5b435de0 | 855 | if (err) { |
5e8149f5 | 856 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
857 | return -EBADE; |
858 | } | |
859 | ||
5b435de0 | 860 | /* Check current status */ |
a39be27b AS |
861 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
862 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 863 | if (err) { |
5e8149f5 | 864 | brcmf_err("HT Avail read error: %d\n", err); |
5b435de0 AS |
865 | return -EBADE; |
866 | } | |
867 | ||
868 | /* Go to pending and await interrupt if appropriate */ | |
869 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
870 | /* Allow only clock-available interrupt */ | |
a39be27b AS |
871 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
872 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 873 | if (err) { |
5e8149f5 | 874 | brcmf_err("Devctl error setting CA: %d\n", |
5b435de0 AS |
875 | err); |
876 | return -EBADE; | |
877 | } | |
878 | ||
879 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
a39be27b AS |
880 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
881 | devctl, &err); | |
c3203374 | 882 | brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); |
5b435de0 AS |
883 | bus->clkstate = CLK_PENDING; |
884 | ||
885 | return 0; | |
886 | } else if (bus->clkstate == CLK_PENDING) { | |
887 | /* Cancel CA-only interrupt filter */ | |
a39be27b AS |
888 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
889 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 890 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
891 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
892 | devctl, &err); | |
5b435de0 AS |
893 | } |
894 | ||
895 | /* Otherwise, wait here (polling) for HT Avail */ | |
896 | timeout = jiffies + | |
897 | msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); | |
898 | while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
a39be27b AS |
899 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
900 | SBSDIO_FUNC1_CHIPCLKCSR, | |
901 | &err); | |
5b435de0 AS |
902 | if (time_after(jiffies, timeout)) |
903 | break; | |
904 | else | |
905 | usleep_range(5000, 10000); | |
906 | } | |
907 | if (err) { | |
5e8149f5 | 908 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
909 | return -EBADE; |
910 | } | |
911 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
5e8149f5 | 912 | brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", |
5b435de0 AS |
913 | PMU_MAX_TRANSITION_DLY, clkctl); |
914 | return -EBADE; | |
915 | } | |
916 | ||
917 | /* Mark clock available */ | |
918 | bus->clkstate = CLK_AVAIL; | |
c3203374 | 919 | brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); |
5b435de0 | 920 | |
8ae74654 | 921 | #if defined(DEBUG) |
23677ce3 | 922 | if (!bus->alp_only) { |
5b435de0 | 923 | if (SBSDIO_ALPONLY(clkctl)) |
5e8149f5 | 924 | brcmf_err("HT Clock should be on\n"); |
5b435de0 | 925 | } |
8ae74654 | 926 | #endif /* defined (DEBUG) */ |
5b435de0 | 927 | |
5b435de0 AS |
928 | } else { |
929 | clkreq = 0; | |
930 | ||
931 | if (bus->clkstate == CLK_PENDING) { | |
932 | /* Cancel CA-only interrupt filter */ | |
a39be27b AS |
933 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
934 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 935 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
936 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
937 | devctl, &err); | |
5b435de0 AS |
938 | } |
939 | ||
940 | bus->clkstate = CLK_SDONLY; | |
a39be27b AS |
941 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
942 | clkreq, &err); | |
c3203374 | 943 | brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); |
5b435de0 | 944 | if (err) { |
5e8149f5 | 945 | brcmf_err("Failed access turning clock off: %d\n", |
5b435de0 AS |
946 | err); |
947 | return -EBADE; | |
948 | } | |
949 | } | |
950 | return 0; | |
951 | } | |
952 | ||
953 | /* Change idle/active SD state */ | |
82d7f3c1 | 954 | static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) |
5b435de0 | 955 | { |
c3203374 | 956 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
957 | |
958 | if (on) | |
959 | bus->clkstate = CLK_SDONLY; | |
960 | else | |
961 | bus->clkstate = CLK_NONE; | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | /* Transition SD and backplane clock readiness */ | |
82d7f3c1 | 967 | static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) |
5b435de0 | 968 | { |
8ae74654 | 969 | #ifdef DEBUG |
5b435de0 | 970 | uint oldstate = bus->clkstate; |
8ae74654 | 971 | #endif /* DEBUG */ |
5b435de0 | 972 | |
c3203374 | 973 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
974 | |
975 | /* Early exit if we're already there */ | |
b441ba8d | 976 | if (bus->clkstate == target) |
5b435de0 | 977 | return 0; |
5b435de0 AS |
978 | |
979 | switch (target) { | |
980 | case CLK_AVAIL: | |
981 | /* Make sure SD clock is available */ | |
982 | if (bus->clkstate == CLK_NONE) | |
82d7f3c1 | 983 | brcmf_sdio_sdclk(bus, true); |
5b435de0 | 984 | /* Now request HT Avail on the backplane */ |
82d7f3c1 | 985 | brcmf_sdio_htclk(bus, true, pendok); |
5b435de0 AS |
986 | break; |
987 | ||
988 | case CLK_SDONLY: | |
989 | /* Remove HT request, or bring up SD clock */ | |
990 | if (bus->clkstate == CLK_NONE) | |
82d7f3c1 | 991 | brcmf_sdio_sdclk(bus, true); |
5b435de0 | 992 | else if (bus->clkstate == CLK_AVAIL) |
82d7f3c1 | 993 | brcmf_sdio_htclk(bus, false, false); |
5b435de0 | 994 | else |
5e8149f5 | 995 | brcmf_err("request for %d -> %d\n", |
5b435de0 | 996 | bus->clkstate, target); |
5b435de0 AS |
997 | break; |
998 | ||
999 | case CLK_NONE: | |
1000 | /* Make sure to remove HT request */ | |
1001 | if (bus->clkstate == CLK_AVAIL) | |
82d7f3c1 | 1002 | brcmf_sdio_htclk(bus, false, false); |
5b435de0 | 1003 | /* Now remove the SD clock */ |
82d7f3c1 | 1004 | brcmf_sdio_sdclk(bus, false); |
5b435de0 AS |
1005 | break; |
1006 | } | |
8ae74654 | 1007 | #ifdef DEBUG |
c3203374 | 1008 | brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); |
8ae74654 | 1009 | #endif /* DEBUG */ |
5b435de0 AS |
1010 | |
1011 | return 0; | |
1012 | } | |
1013 | ||
4a3da990 | 1014 | static int |
82d7f3c1 | 1015 | brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) |
4a3da990 PH |
1016 | { |
1017 | int err = 0; | |
8a385ba5 | 1018 | u8 clkcsr; |
82030d6d AS |
1019 | |
1020 | brcmf_dbg(SDIO, "Enter: request %s currently %s\n", | |
4a3da990 | 1021 | (sleep ? "SLEEP" : "WAKE"), |
99824643 | 1022 | (bus->sleeping ? "SLEEP" : "WAKE")); |
4a3da990 PH |
1023 | |
1024 | /* If SR is enabled control bus state with KSO */ | |
1025 | if (bus->sr_enabled) { | |
1026 | /* Done if we're already in the requested state */ | |
99824643 | 1027 | if (sleep == bus->sleeping) |
4a3da990 PH |
1028 | goto end; |
1029 | ||
1030 | /* Going to sleep */ | |
1031 | if (sleep) { | |
8a385ba5 AS |
1032 | clkcsr = brcmf_sdiod_regrb(bus->sdiodev, |
1033 | SBSDIO_FUNC1_CHIPCLKCSR, | |
1034 | &err); | |
1035 | if ((clkcsr & SBSDIO_CSR_MASK) == 0) { | |
1036 | brcmf_dbg(SDIO, "no clock, set ALP\n"); | |
1037 | brcmf_sdiod_regwb(bus->sdiodev, | |
1038 | SBSDIO_FUNC1_CHIPCLKCSR, | |
1039 | SBSDIO_ALP_AVAIL_REQ, &err); | |
1040 | } | |
82d7f3c1 | 1041 | err = brcmf_sdio_kso_control(bus, false); |
4a3da990 | 1042 | } else { |
82d7f3c1 | 1043 | err = brcmf_sdio_kso_control(bus, true); |
4a3da990 | 1044 | } |
8982cd40 | 1045 | if (err) { |
4a3da990 PH |
1046 | brcmf_err("error while changing bus sleep state %d\n", |
1047 | err); | |
8a385ba5 | 1048 | goto done; |
4a3da990 PH |
1049 | } |
1050 | } | |
1051 | ||
1052 | end: | |
1053 | /* control clocks */ | |
1054 | if (sleep) { | |
1055 | if (!bus->sr_enabled) | |
82d7f3c1 | 1056 | brcmf_sdio_clkctl(bus, CLK_NONE, pendok); |
4a3da990 | 1057 | } else { |
82d7f3c1 | 1058 | brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); |
cf45932a | 1059 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); |
4a3da990 | 1060 | } |
99824643 | 1061 | bus->sleeping = sleep; |
8982cd40 AS |
1062 | brcmf_dbg(SDIO, "new state %s\n", |
1063 | (sleep ? "SLEEP" : "WAKE")); | |
8a385ba5 AS |
1064 | done: |
1065 | brcmf_dbg(SDIO, "Exit: err=%d\n", err); | |
4a3da990 PH |
1066 | return err; |
1067 | ||
1068 | } | |
1069 | ||
0801e6c5 DK |
1070 | #ifdef DEBUG |
1071 | static inline bool brcmf_sdio_valid_shared_address(u32 addr) | |
1072 | { | |
1073 | return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); | |
1074 | } | |
1075 | ||
1076 | static int brcmf_sdio_readshared(struct brcmf_sdio *bus, | |
1077 | struct sdpcm_shared *sh) | |
1078 | { | |
9819a902 | 1079 | u32 addr = 0; |
0801e6c5 DK |
1080 | int rv; |
1081 | u32 shaddr = 0; | |
1082 | struct sdpcm_shared_le sh_le; | |
1083 | __le32 addr_le; | |
1084 | ||
9819a902 AS |
1085 | sdio_claim_host(bus->sdiodev->func[1]); |
1086 | brcmf_sdio_bus_sleep(bus, false, false); | |
0801e6c5 DK |
1087 | |
1088 | /* | |
1089 | * Read last word in socram to determine | |
1090 | * address of sdpcm_shared structure | |
1091 | */ | |
9819a902 AS |
1092 | shaddr = bus->ci->rambase + bus->ci->ramsize - 4; |
1093 | if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci)) | |
1094 | shaddr -= bus->ci->srsize; | |
1095 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, | |
1096 | (u8 *)&addr_le, 4); | |
0801e6c5 | 1097 | if (rv < 0) |
9819a902 | 1098 | goto fail; |
0801e6c5 DK |
1099 | |
1100 | /* | |
1101 | * Check if addr is valid. | |
1102 | * NVRAM length at the end of memory should have been overwritten. | |
1103 | */ | |
9819a902 | 1104 | addr = le32_to_cpu(addr_le); |
0801e6c5 | 1105 | if (!brcmf_sdio_valid_shared_address(addr)) { |
9819a902 AS |
1106 | brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr); |
1107 | rv = -EINVAL; | |
1108 | goto fail; | |
0801e6c5 DK |
1109 | } |
1110 | ||
9819a902 AS |
1111 | brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr); |
1112 | ||
0801e6c5 DK |
1113 | /* Read hndrte_shared structure */ |
1114 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, | |
1115 | sizeof(struct sdpcm_shared_le)); | |
1116 | if (rv < 0) | |
9819a902 AS |
1117 | goto fail; |
1118 | ||
1119 | sdio_release_host(bus->sdiodev->func[1]); | |
0801e6c5 DK |
1120 | |
1121 | /* Endianness */ | |
1122 | sh->flags = le32_to_cpu(sh_le.flags); | |
1123 | sh->trap_addr = le32_to_cpu(sh_le.trap_addr); | |
1124 | sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); | |
1125 | sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); | |
1126 | sh->assert_line = le32_to_cpu(sh_le.assert_line); | |
1127 | sh->console_addr = le32_to_cpu(sh_le.console_addr); | |
1128 | sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); | |
1129 | ||
1130 | if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { | |
1131 | brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", | |
1132 | SDPCM_SHARED_VERSION, | |
1133 | sh->flags & SDPCM_SHARED_VERSION_MASK); | |
1134 | return -EPROTO; | |
1135 | } | |
0801e6c5 | 1136 | return 0; |
9819a902 AS |
1137 | |
1138 | fail: | |
1139 | brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n", | |
1140 | rv, addr); | |
1141 | sdio_release_host(bus->sdiodev->func[1]); | |
1142 | return rv; | |
0801e6c5 DK |
1143 | } |
1144 | ||
1145 | static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) | |
1146 | { | |
1147 | struct sdpcm_shared sh; | |
1148 | ||
1149 | if (brcmf_sdio_readshared(bus, &sh) == 0) | |
1150 | bus->console_addr = sh.console_addr; | |
1151 | } | |
1152 | #else | |
1153 | static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) | |
1154 | { | |
1155 | } | |
1156 | #endif /* DEBUG */ | |
1157 | ||
82d7f3c1 | 1158 | static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) |
5b435de0 AS |
1159 | { |
1160 | u32 intstatus = 0; | |
1161 | u32 hmb_data; | |
1162 | u8 fcbits; | |
58692750 | 1163 | int ret; |
5b435de0 | 1164 | |
c3203374 | 1165 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
1166 | |
1167 | /* Read mailbox data and ack that we did so */ | |
58692750 FL |
1168 | ret = r_sdreg32(bus, &hmb_data, |
1169 | offsetof(struct sdpcmd_regs, tohostmailboxdata)); | |
5b435de0 | 1170 | |
58692750 | 1171 | if (ret == 0) |
5b435de0 | 1172 | w_sdreg32(bus, SMB_INT_ACK, |
58692750 | 1173 | offsetof(struct sdpcmd_regs, tosbmailbox)); |
80969836 | 1174 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1175 | |
1176 | /* Dongle recomposed rx frames, accept them again */ | |
1177 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
c3203374 | 1178 | brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", |
5b435de0 AS |
1179 | bus->rx_seq); |
1180 | if (!bus->rxskip) | |
5e8149f5 | 1181 | brcmf_err("unexpected NAKHANDLED!\n"); |
5b435de0 AS |
1182 | |
1183 | bus->rxskip = false; | |
1184 | intstatus |= I_HMB_FRAME_IND; | |
1185 | } | |
1186 | ||
1187 | /* | |
1188 | * DEVREADY does not occur with gSPI. | |
1189 | */ | |
1190 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
1191 | bus->sdpcm_ver = | |
1192 | (hmb_data & HMB_DATA_VERSION_MASK) >> | |
1193 | HMB_DATA_VERSION_SHIFT; | |
1194 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
5e8149f5 | 1195 | brcmf_err("Version mismatch, dongle reports %d, " |
5b435de0 AS |
1196 | "expecting %d\n", |
1197 | bus->sdpcm_ver, SDPCM_PROT_VERSION); | |
1198 | else | |
c3203374 | 1199 | brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", |
5b435de0 | 1200 | bus->sdpcm_ver); |
0801e6c5 DK |
1201 | |
1202 | /* | |
1203 | * Retrieve console state address now that firmware should have | |
1204 | * updated it. | |
1205 | */ | |
1206 | brcmf_sdio_get_console_addr(bus); | |
5b435de0 AS |
1207 | } |
1208 | ||
1209 | /* | |
1210 | * Flow Control has been moved into the RX headers and this out of band | |
1211 | * method isn't used any more. | |
1212 | * remaining backward compatible with older dongles. | |
1213 | */ | |
1214 | if (hmb_data & HMB_DATA_FC) { | |
1215 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> | |
1216 | HMB_DATA_FCDATA_SHIFT; | |
1217 | ||
1218 | if (fcbits & ~bus->flowcontrol) | |
80969836 | 1219 | bus->sdcnt.fc_xoff++; |
5b435de0 AS |
1220 | |
1221 | if (bus->flowcontrol & ~fcbits) | |
80969836 | 1222 | bus->sdcnt.fc_xon++; |
5b435de0 | 1223 | |
80969836 | 1224 | bus->sdcnt.fc_rcvd++; |
5b435de0 AS |
1225 | bus->flowcontrol = fcbits; |
1226 | } | |
1227 | ||
1228 | /* Shouldn't be any others */ | |
1229 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
1230 | HMB_DATA_NAKHANDLED | | |
1231 | HMB_DATA_FC | | |
1232 | HMB_DATA_FWREADY | | |
1233 | HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) | |
5e8149f5 | 1234 | brcmf_err("Unknown mailbox data content: 0x%02x\n", |
5b435de0 AS |
1235 | hmb_data); |
1236 | ||
1237 | return intstatus; | |
1238 | } | |
1239 | ||
82d7f3c1 | 1240 | static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) |
5b435de0 AS |
1241 | { |
1242 | uint retries = 0; | |
1243 | u16 lastrbc; | |
1244 | u8 hi, lo; | |
1245 | int err; | |
1246 | ||
5e8149f5 | 1247 | brcmf_err("%sterminate frame%s\n", |
5b435de0 AS |
1248 | abort ? "abort command, " : "", |
1249 | rtx ? ", send NAK" : ""); | |
1250 | ||
1251 | if (abort) | |
a39be27b | 1252 | brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2); |
5b435de0 | 1253 | |
a39be27b AS |
1254 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
1255 | SFC_RF_TERM, &err); | |
80969836 | 1256 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
1257 | |
1258 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
1259 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
a39be27b AS |
1260 | hi = brcmf_sdiod_regrb(bus->sdiodev, |
1261 | SBSDIO_FUNC1_RFRAMEBCHI, &err); | |
1262 | lo = brcmf_sdiod_regrb(bus->sdiodev, | |
1263 | SBSDIO_FUNC1_RFRAMEBCLO, &err); | |
80969836 | 1264 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1265 | |
1266 | if ((hi == 0) && (lo == 0)) | |
1267 | break; | |
1268 | ||
1269 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
5e8149f5 | 1270 | brcmf_err("count growing: last 0x%04x now 0x%04x\n", |
5b435de0 AS |
1271 | lastrbc, (hi << 8) + lo); |
1272 | } | |
1273 | lastrbc = (hi << 8) + lo; | |
1274 | } | |
1275 | ||
1276 | if (!retries) | |
5e8149f5 | 1277 | brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); |
5b435de0 | 1278 | else |
c3203374 | 1279 | brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); |
5b435de0 AS |
1280 | |
1281 | if (rtx) { | |
80969836 | 1282 | bus->sdcnt.rxrtx++; |
58692750 FL |
1283 | err = w_sdreg32(bus, SMB_NAK, |
1284 | offsetof(struct sdpcmd_regs, tosbmailbox)); | |
5b435de0 | 1285 | |
80969836 | 1286 | bus->sdcnt.f1regdata++; |
58692750 | 1287 | if (err == 0) |
5b435de0 AS |
1288 | bus->rxskip = true; |
1289 | } | |
1290 | ||
1291 | /* Clear partial in any case */ | |
4754fcee | 1292 | bus->cur_read.len = 0; |
5b435de0 AS |
1293 | } |
1294 | ||
81c7883c HM |
1295 | static void brcmf_sdio_txfail(struct brcmf_sdio *bus) |
1296 | { | |
1297 | struct brcmf_sdio_dev *sdiodev = bus->sdiodev; | |
1298 | u8 i, hi, lo; | |
1299 | ||
1300 | /* On failure, abort the command and terminate the frame */ | |
1301 | brcmf_err("sdio error, abort command and terminate frame\n"); | |
1302 | bus->sdcnt.tx_sderrs++; | |
1303 | ||
1304 | brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2); | |
1305 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); | |
1306 | bus->sdcnt.f1regdata++; | |
1307 | ||
1308 | for (i = 0; i < 3; i++) { | |
1309 | hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); | |
1310 | lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); | |
1311 | bus->sdcnt.f1regdata += 2; | |
1312 | if ((hi == 0) && (lo == 0)) | |
1313 | break; | |
1314 | } | |
1315 | } | |
1316 | ||
9a95e60e | 1317 | /* return total length of buffer chain */ |
82d7f3c1 | 1318 | static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) |
9a95e60e AS |
1319 | { |
1320 | struct sk_buff *p; | |
1321 | uint total; | |
1322 | ||
1323 | total = 0; | |
1324 | skb_queue_walk(&bus->glom, p) | |
1325 | total += p->len; | |
1326 | return total; | |
1327 | } | |
1328 | ||
82d7f3c1 | 1329 | static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) |
046808da AS |
1330 | { |
1331 | struct sk_buff *cur, *next; | |
1332 | ||
1333 | skb_queue_walk_safe(&bus->glom, cur, next) { | |
1334 | skb_unlink(cur, &bus->glom); | |
1335 | brcmu_pkt_buf_free_skb(cur); | |
1336 | } | |
1337 | } | |
1338 | ||
6bc52319 FL |
1339 | /** |
1340 | * brcmfmac sdio bus specific header | |
1341 | * This is the lowest layer header wrapped on the packets transmitted between | |
1342 | * host and WiFi dongle which contains information needed for SDIO core and | |
1343 | * firmware | |
1344 | * | |
8da9d2c8 FL |
1345 | * It consists of 3 parts: hardware header, hardware extension header and |
1346 | * software header | |
6bc52319 FL |
1347 | * hardware header (frame tag) - 4 bytes |
1348 | * Byte 0~1: Frame length | |
1349 | * Byte 2~3: Checksum, bit-wise inverse of frame length | |
8da9d2c8 FL |
1350 | * hardware extension header - 8 bytes |
1351 | * Tx glom mode only, N/A for Rx or normal Tx | |
1352 | * Byte 0~1: Packet length excluding hw frame tag | |
1353 | * Byte 2: Reserved | |
1354 | * Byte 3: Frame flags, bit 0: last frame indication | |
1355 | * Byte 4~5: Reserved | |
1356 | * Byte 6~7: Tail padding length | |
6bc52319 FL |
1357 | * software header - 8 bytes |
1358 | * Byte 0: Rx/Tx sequence number | |
1359 | * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag | |
1360 | * Byte 2: Length of next data frame, reserved for Tx | |
1361 | * Byte 3: Data offset | |
1362 | * Byte 4: Flow control bits, reserved for Tx | |
1363 | * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet | |
1364 | * Byte 6~7: Reserved | |
1365 | */ | |
1366 | #define SDPCM_HWHDR_LEN 4 | |
8da9d2c8 | 1367 | #define SDPCM_HWEXT_LEN 8 |
6bc52319 FL |
1368 | #define SDPCM_SWHDR_LEN 8 |
1369 | #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) | |
6bc52319 FL |
1370 | /* software header */ |
1371 | #define SDPCM_SEQ_MASK 0x000000ff | |
1372 | #define SDPCM_SEQ_WRAP 256 | |
1373 | #define SDPCM_CHANNEL_MASK 0x00000f00 | |
1374 | #define SDPCM_CHANNEL_SHIFT 8 | |
1375 | #define SDPCM_CONTROL_CHANNEL 0 /* Control */ | |
1376 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ | |
1377 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ | |
1378 | #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ | |
1379 | #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ | |
1380 | #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) | |
1381 | #define SDPCM_NEXTLEN_MASK 0x00ff0000 | |
1382 | #define SDPCM_NEXTLEN_SHIFT 16 | |
1383 | #define SDPCM_DOFFSET_MASK 0xff000000 | |
1384 | #define SDPCM_DOFFSET_SHIFT 24 | |
1385 | #define SDPCM_FCMASK_MASK 0x000000ff | |
1386 | #define SDPCM_WINDOW_MASK 0x0000ff00 | |
1387 | #define SDPCM_WINDOW_SHIFT 8 | |
1388 | ||
1389 | static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) | |
1390 | { | |
1391 | u32 hdrvalue; | |
1392 | hdrvalue = *(u32 *)swheader; | |
1393 | return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); | |
1394 | } | |
1395 | ||
1396 | static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, | |
1397 | struct brcmf_sdio_hdrinfo *rd, | |
1398 | enum brcmf_sdio_frmtype type) | |
4754fcee FL |
1399 | { |
1400 | u16 len, checksum; | |
1401 | u8 rx_seq, fc, tx_seq_max; | |
6bc52319 | 1402 | u32 swheader; |
4754fcee | 1403 | |
4b776961 | 1404 | trace_brcmf_sdpcm_hdr(SDPCM_RX, header); |
76584ece | 1405 | |
6bc52319 | 1406 | /* hw header */ |
4754fcee FL |
1407 | len = get_unaligned_le16(header); |
1408 | checksum = get_unaligned_le16(header + sizeof(u16)); | |
1409 | /* All zero means no more to read */ | |
1410 | if (!(len | checksum)) { | |
1411 | bus->rxpending = false; | |
10510589 | 1412 | return -ENODATA; |
4754fcee FL |
1413 | } |
1414 | if ((u16)(~(len ^ checksum))) { | |
5e8149f5 | 1415 | brcmf_err("HW header checksum error\n"); |
4754fcee | 1416 | bus->sdcnt.rx_badhdr++; |
82d7f3c1 | 1417 | brcmf_sdio_rxfail(bus, false, false); |
10510589 | 1418 | return -EIO; |
4754fcee FL |
1419 | } |
1420 | if (len < SDPCM_HDRLEN) { | |
5e8149f5 | 1421 | brcmf_err("HW header length error\n"); |
10510589 | 1422 | return -EPROTO; |
4754fcee | 1423 | } |
9d7d6f95 FL |
1424 | if (type == BRCMF_SDIO_FT_SUPER && |
1425 | (roundup(len, bus->blocksize) != rd->len)) { | |
5e8149f5 | 1426 | brcmf_err("HW superframe header length error\n"); |
10510589 | 1427 | return -EPROTO; |
9d7d6f95 FL |
1428 | } |
1429 | if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { | |
5e8149f5 | 1430 | brcmf_err("HW subframe header length error\n"); |
10510589 | 1431 | return -EPROTO; |
9d7d6f95 | 1432 | } |
4754fcee FL |
1433 | rd->len = len; |
1434 | ||
6bc52319 FL |
1435 | /* software header */ |
1436 | header += SDPCM_HWHDR_LEN; | |
1437 | swheader = le32_to_cpu(*(__le32 *)header); | |
1438 | if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { | |
5e8149f5 | 1439 | brcmf_err("Glom descriptor found in superframe head\n"); |
9d7d6f95 | 1440 | rd->len = 0; |
10510589 | 1441 | return -EINVAL; |
9d7d6f95 | 1442 | } |
6bc52319 FL |
1443 | rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); |
1444 | rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; | |
9d7d6f95 FL |
1445 | if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && |
1446 | type != BRCMF_SDIO_FT_SUPER) { | |
5e8149f5 | 1447 | brcmf_err("HW header length too long\n"); |
4754fcee | 1448 | bus->sdcnt.rx_toolong++; |
82d7f3c1 | 1449 | brcmf_sdio_rxfail(bus, false, false); |
4754fcee | 1450 | rd->len = 0; |
10510589 | 1451 | return -EPROTO; |
4754fcee | 1452 | } |
9d7d6f95 | 1453 | if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { |
5e8149f5 | 1454 | brcmf_err("Wrong channel for superframe\n"); |
9d7d6f95 | 1455 | rd->len = 0; |
10510589 | 1456 | return -EINVAL; |
9d7d6f95 FL |
1457 | } |
1458 | if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && | |
1459 | rd->channel != SDPCM_EVENT_CHANNEL) { | |
5e8149f5 | 1460 | brcmf_err("Wrong channel for subframe\n"); |
9d7d6f95 | 1461 | rd->len = 0; |
10510589 | 1462 | return -EINVAL; |
9d7d6f95 | 1463 | } |
6bc52319 | 1464 | rd->dat_offset = brcmf_sdio_getdatoffset(header); |
4754fcee | 1465 | if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { |
5e8149f5 | 1466 | brcmf_err("seq %d: bad data offset\n", rx_seq); |
4754fcee | 1467 | bus->sdcnt.rx_badhdr++; |
82d7f3c1 | 1468 | brcmf_sdio_rxfail(bus, false, false); |
4754fcee | 1469 | rd->len = 0; |
10510589 | 1470 | return -ENXIO; |
4754fcee FL |
1471 | } |
1472 | if (rd->seq_num != rx_seq) { | |
5e8149f5 | 1473 | brcmf_err("seq %d: sequence number error, expect %d\n", |
4754fcee FL |
1474 | rx_seq, rd->seq_num); |
1475 | bus->sdcnt.rx_badseq++; | |
1476 | rd->seq_num = rx_seq; | |
1477 | } | |
9d7d6f95 FL |
1478 | /* no need to check the reset for subframe */ |
1479 | if (type == BRCMF_SDIO_FT_SUB) | |
10510589 | 1480 | return 0; |
6bc52319 | 1481 | rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; |
4754fcee FL |
1482 | if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { |
1483 | /* only warm for NON glom packet */ | |
1484 | if (rd->channel != SDPCM_GLOM_CHANNEL) | |
5e8149f5 | 1485 | brcmf_err("seq %d: next length error\n", rx_seq); |
4754fcee FL |
1486 | rd->len_nxtfrm = 0; |
1487 | } | |
6bc52319 FL |
1488 | swheader = le32_to_cpu(*(__le32 *)(header + 4)); |
1489 | fc = swheader & SDPCM_FCMASK_MASK; | |
4754fcee FL |
1490 | if (bus->flowcontrol != fc) { |
1491 | if (~bus->flowcontrol & fc) | |
1492 | bus->sdcnt.fc_xoff++; | |
1493 | if (bus->flowcontrol & ~fc) | |
1494 | bus->sdcnt.fc_xon++; | |
1495 | bus->sdcnt.fc_rcvd++; | |
1496 | bus->flowcontrol = fc; | |
1497 | } | |
6bc52319 | 1498 | tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; |
4754fcee | 1499 | if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { |
5e8149f5 | 1500 | brcmf_err("seq %d: max tx seq number error\n", rx_seq); |
4754fcee FL |
1501 | tx_seq_max = bus->tx_seq + 2; |
1502 | } | |
1503 | bus->tx_max = tx_seq_max; | |
1504 | ||
10510589 | 1505 | return 0; |
4754fcee FL |
1506 | } |
1507 | ||
6bc52319 FL |
1508 | static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) |
1509 | { | |
1510 | *(__le16 *)header = cpu_to_le16(frm_length); | |
1511 | *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); | |
1512 | } | |
1513 | ||
1514 | static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, | |
1515 | struct brcmf_sdio_hdrinfo *hd_info) | |
1516 | { | |
8da9d2c8 FL |
1517 | u32 hdrval; |
1518 | u8 hdr_offset; | |
6bc52319 FL |
1519 | |
1520 | brcmf_sdio_update_hwhdr(header, hd_info->len); | |
8da9d2c8 FL |
1521 | hdr_offset = SDPCM_HWHDR_LEN; |
1522 | ||
1523 | if (bus->txglom) { | |
1524 | hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); | |
1525 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1526 | hdrval = (u16)hd_info->tail_pad << 16; | |
1527 | *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); | |
1528 | hdr_offset += SDPCM_HWEXT_LEN; | |
1529 | } | |
6bc52319 | 1530 | |
8da9d2c8 FL |
1531 | hdrval = hd_info->seq_num; |
1532 | hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & | |
1533 | SDPCM_CHANNEL_MASK; | |
1534 | hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & | |
1535 | SDPCM_DOFFSET_MASK; | |
1536 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1537 | *(((__le32 *)(header + hdr_offset)) + 1) = 0; | |
1538 | trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); | |
6bc52319 FL |
1539 | } |
1540 | ||
82d7f3c1 | 1541 | static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) |
5b435de0 AS |
1542 | { |
1543 | u16 dlen, totlen; | |
1544 | u8 *dptr, num = 0; | |
9d7d6f95 | 1545 | u16 sublen; |
0b45bf74 | 1546 | struct sk_buff *pfirst, *pnext; |
5b435de0 AS |
1547 | |
1548 | int errcode; | |
9d7d6f95 | 1549 | u8 doff, sfdoff; |
5b435de0 | 1550 | |
6bc52319 | 1551 | struct brcmf_sdio_hdrinfo rd_new; |
5b435de0 AS |
1552 | |
1553 | /* If packets, issue read(s) and send up packet chain */ | |
1554 | /* Return sequence numbers consumed? */ | |
1555 | ||
c3203374 | 1556 | brcmf_dbg(SDIO, "start: glomd %p glom %p\n", |
b83db862 | 1557 | bus->glomd, skb_peek(&bus->glom)); |
5b435de0 AS |
1558 | |
1559 | /* If there's a descriptor, generate the packet chain */ | |
1560 | if (bus->glomd) { | |
0b45bf74 | 1561 | pfirst = pnext = NULL; |
5b435de0 AS |
1562 | dlen = (u16) (bus->glomd->len); |
1563 | dptr = bus->glomd->data; | |
1564 | if (!dlen || (dlen & 1)) { | |
5e8149f5 | 1565 | brcmf_err("bad glomd len(%d), ignore descriptor\n", |
5b435de0 AS |
1566 | dlen); |
1567 | dlen = 0; | |
1568 | } | |
1569 | ||
1570 | for (totlen = num = 0; dlen; num++) { | |
1571 | /* Get (and move past) next length */ | |
1572 | sublen = get_unaligned_le16(dptr); | |
1573 | dlen -= sizeof(u16); | |
1574 | dptr += sizeof(u16); | |
1575 | if ((sublen < SDPCM_HDRLEN) || | |
1576 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
5e8149f5 | 1577 | brcmf_err("descriptor len %d bad: %d\n", |
5b435de0 AS |
1578 | num, sublen); |
1579 | pnext = NULL; | |
1580 | break; | |
1581 | } | |
e217d1c8 | 1582 | if (sublen % bus->sgentry_align) { |
5e8149f5 | 1583 | brcmf_err("sublen %d not multiple of %d\n", |
e217d1c8 | 1584 | sublen, bus->sgentry_align); |
5b435de0 AS |
1585 | } |
1586 | totlen += sublen; | |
1587 | ||
1588 | /* For last frame, adjust read len so total | |
1589 | is a block multiple */ | |
1590 | if (!dlen) { | |
1591 | sublen += | |
1592 | (roundup(totlen, bus->blocksize) - totlen); | |
1593 | totlen = roundup(totlen, bus->blocksize); | |
1594 | } | |
1595 | ||
1596 | /* Allocate/chain packet for next subframe */ | |
e217d1c8 | 1597 | pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); |
5b435de0 | 1598 | if (pnext == NULL) { |
5e8149f5 | 1599 | brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", |
5b435de0 AS |
1600 | num, sublen); |
1601 | break; | |
1602 | } | |
b83db862 | 1603 | skb_queue_tail(&bus->glom, pnext); |
5b435de0 AS |
1604 | |
1605 | /* Adhere to start alignment requirements */ | |
e217d1c8 | 1606 | pkt_align(pnext, sublen, bus->sgentry_align); |
5b435de0 AS |
1607 | } |
1608 | ||
1609 | /* If all allocations succeeded, save packet chain | |
1610 | in bus structure */ | |
1611 | if (pnext) { | |
1612 | brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", | |
1613 | totlen, num); | |
4754fcee FL |
1614 | if (BRCMF_GLOM_ON() && bus->cur_read.len && |
1615 | totlen != bus->cur_read.len) { | |
5b435de0 | 1616 | brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", |
4754fcee | 1617 | bus->cur_read.len, totlen, rxseq); |
5b435de0 | 1618 | } |
5b435de0 AS |
1619 | pfirst = pnext = NULL; |
1620 | } else { | |
82d7f3c1 | 1621 | brcmf_sdio_free_glom(bus); |
5b435de0 AS |
1622 | num = 0; |
1623 | } | |
1624 | ||
1625 | /* Done with descriptor packet */ | |
1626 | brcmu_pkt_buf_free_skb(bus->glomd); | |
1627 | bus->glomd = NULL; | |
4754fcee | 1628 | bus->cur_read.len = 0; |
5b435de0 AS |
1629 | } |
1630 | ||
1631 | /* Ok -- either we just generated a packet chain, | |
1632 | or had one from before */ | |
b83db862 | 1633 | if (!skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1634 | if (BRCMF_GLOM_ON()) { |
1635 | brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); | |
b83db862 | 1636 | skb_queue_walk(&bus->glom, pnext) { |
5b435de0 AS |
1637 | brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", |
1638 | pnext, (u8 *) (pnext->data), | |
1639 | pnext->len, pnext->len); | |
1640 | } | |
1641 | } | |
1642 | ||
b83db862 | 1643 | pfirst = skb_peek(&bus->glom); |
82d7f3c1 | 1644 | dlen = (u16) brcmf_sdio_glom_len(bus); |
5b435de0 AS |
1645 | |
1646 | /* Do an SDIO read for the superframe. Configurable iovar to | |
1647 | * read directly into the chained packet, or allocate a large | |
1648 | * packet and and copy into the chain. | |
1649 | */ | |
38b0b0dd | 1650 | sdio_claim_host(bus->sdiodev->func[1]); |
a39be27b | 1651 | errcode = brcmf_sdiod_recv_chain(bus->sdiodev, |
a39be27b | 1652 | &bus->glom, dlen); |
38b0b0dd | 1653 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 1654 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1655 | |
1656 | /* On failure, kill the superframe, allow a couple retries */ | |
1657 | if (errcode < 0) { | |
5e8149f5 | 1658 | brcmf_err("glom read of %d bytes failed: %d\n", |
5b435de0 | 1659 | dlen, errcode); |
5b435de0 | 1660 | |
38b0b0dd | 1661 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 1662 | if (bus->glomerr++ < 3) { |
82d7f3c1 | 1663 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 AS |
1664 | } else { |
1665 | bus->glomerr = 0; | |
82d7f3c1 | 1666 | brcmf_sdio_rxfail(bus, true, false); |
80969836 | 1667 | bus->sdcnt.rxglomfail++; |
82d7f3c1 | 1668 | brcmf_sdio_free_glom(bus); |
5b435de0 | 1669 | } |
38b0b0dd | 1670 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1671 | return 0; |
1672 | } | |
1e023829 JP |
1673 | |
1674 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), | |
1675 | pfirst->data, min_t(int, pfirst->len, 48), | |
1676 | "SUPERFRAME:\n"); | |
5b435de0 | 1677 | |
9d7d6f95 FL |
1678 | rd_new.seq_num = rxseq; |
1679 | rd_new.len = dlen; | |
38b0b0dd | 1680 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1681 | errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, |
1682 | BRCMF_SDIO_FT_SUPER); | |
38b0b0dd | 1683 | sdio_release_host(bus->sdiodev->func[1]); |
9d7d6f95 | 1684 | bus->cur_read.len = rd_new.len_nxtfrm << 4; |
5b435de0 AS |
1685 | |
1686 | /* Remove superframe header, remember offset */ | |
9d7d6f95 FL |
1687 | skb_pull(pfirst, rd_new.dat_offset); |
1688 | sfdoff = rd_new.dat_offset; | |
0b45bf74 | 1689 | num = 0; |
5b435de0 AS |
1690 | |
1691 | /* Validate all the subframe headers */ | |
0b45bf74 AS |
1692 | skb_queue_walk(&bus->glom, pnext) { |
1693 | /* leave when invalid subframe is found */ | |
1694 | if (errcode) | |
1695 | break; | |
1696 | ||
9d7d6f95 FL |
1697 | rd_new.len = pnext->len; |
1698 | rd_new.seq_num = rxseq++; | |
38b0b0dd | 1699 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1700 | errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, |
1701 | BRCMF_SDIO_FT_SUB); | |
38b0b0dd | 1702 | sdio_release_host(bus->sdiodev->func[1]); |
1e023829 | 1703 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
9d7d6f95 | 1704 | pnext->data, 32, "subframe:\n"); |
5b435de0 | 1705 | |
0b45bf74 | 1706 | num++; |
5b435de0 AS |
1707 | } |
1708 | ||
1709 | if (errcode) { | |
1710 | /* Terminate frame on error, request | |
1711 | a couple retries */ | |
38b0b0dd | 1712 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1713 | if (bus->glomerr++ < 3) { |
1714 | /* Restore superframe header space */ | |
1715 | skb_push(pfirst, sfdoff); | |
82d7f3c1 | 1716 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 AS |
1717 | } else { |
1718 | bus->glomerr = 0; | |
82d7f3c1 | 1719 | brcmf_sdio_rxfail(bus, true, false); |
80969836 | 1720 | bus->sdcnt.rxglomfail++; |
82d7f3c1 | 1721 | brcmf_sdio_free_glom(bus); |
5b435de0 | 1722 | } |
38b0b0dd | 1723 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee | 1724 | bus->cur_read.len = 0; |
5b435de0 AS |
1725 | return 0; |
1726 | } | |
1727 | ||
1728 | /* Basic SD framing looks ok - process each packet (header) */ | |
5b435de0 | 1729 | |
0b45bf74 | 1730 | skb_queue_walk_safe(&bus->glom, pfirst, pnext) { |
5b435de0 AS |
1731 | dptr = (u8 *) (pfirst->data); |
1732 | sublen = get_unaligned_le16(dptr); | |
6bc52319 | 1733 | doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); |
5b435de0 | 1734 | |
1e023829 | 1735 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
9d7d6f95 FL |
1736 | dptr, pfirst->len, |
1737 | "Rx Subframe Data:\n"); | |
5b435de0 AS |
1738 | |
1739 | __skb_trim(pfirst, sublen); | |
1740 | skb_pull(pfirst, doff); | |
1741 | ||
1742 | if (pfirst->len == 0) { | |
0b45bf74 | 1743 | skb_unlink(pfirst, &bus->glom); |
5b435de0 | 1744 | brcmu_pkt_buf_free_skb(pfirst); |
5b435de0 | 1745 | continue; |
5b435de0 AS |
1746 | } |
1747 | ||
1e023829 JP |
1748 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
1749 | pfirst->data, | |
1750 | min_t(int, pfirst->len, 32), | |
1751 | "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", | |
1752 | bus->glom.qlen, pfirst, pfirst->data, | |
1753 | pfirst->len, pfirst->next, | |
1754 | pfirst->prev); | |
05f3820b AS |
1755 | skb_unlink(pfirst, &bus->glom); |
1756 | brcmf_rx_frame(bus->sdiodev->dev, pfirst); | |
1757 | bus->sdcnt.rxglompkts++; | |
5b435de0 | 1758 | } |
5b435de0 | 1759 | |
80969836 | 1760 | bus->sdcnt.rxglomframes++; |
5b435de0 AS |
1761 | } |
1762 | return num; | |
1763 | } | |
1764 | ||
82d7f3c1 AS |
1765 | static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, |
1766 | bool *pending) | |
5b435de0 AS |
1767 | { |
1768 | DECLARE_WAITQUEUE(wait, current); | |
1769 | int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT); | |
1770 | ||
1771 | /* Wait until control frame is available */ | |
1772 | add_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1773 | set_current_state(TASK_INTERRUPTIBLE); | |
1774 | ||
1775 | while (!(*condition) && (!signal_pending(current) && timeout)) | |
1776 | timeout = schedule_timeout(timeout); | |
1777 | ||
1778 | if (signal_pending(current)) | |
1779 | *pending = true; | |
1780 | ||
1781 | set_current_state(TASK_RUNNING); | |
1782 | remove_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1783 | ||
1784 | return timeout; | |
1785 | } | |
1786 | ||
82d7f3c1 | 1787 | static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) |
5b435de0 AS |
1788 | { |
1789 | if (waitqueue_active(&bus->dcmd_resp_wait)) | |
1790 | wake_up_interruptible(&bus->dcmd_resp_wait); | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | static void | |
82d7f3c1 | 1795 | brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) |
5b435de0 AS |
1796 | { |
1797 | uint rdlen, pad; | |
dd43a01c | 1798 | u8 *buf = NULL, *rbuf; |
5b435de0 AS |
1799 | int sdret; |
1800 | ||
1801 | brcmf_dbg(TRACE, "Enter\n"); | |
1802 | ||
dd43a01c FL |
1803 | if (bus->rxblen) |
1804 | buf = vzalloc(bus->rxblen); | |
14f8dc49 | 1805 | if (!buf) |
dd43a01c | 1806 | goto done; |
14f8dc49 | 1807 | |
dd43a01c | 1808 | rbuf = bus->rxbuf; |
9b2d2f2a | 1809 | pad = ((unsigned long)rbuf % bus->head_align); |
5b435de0 | 1810 | if (pad) |
9b2d2f2a | 1811 | rbuf += (bus->head_align - pad); |
5b435de0 AS |
1812 | |
1813 | /* Copy the already-read portion over */ | |
dd43a01c | 1814 | memcpy(buf, hdr, BRCMF_FIRSTREAD); |
5b435de0 AS |
1815 | if (len <= BRCMF_FIRSTREAD) |
1816 | goto gotpkt; | |
1817 | ||
1818 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
1819 | rdlen = len - BRCMF_FIRSTREAD; | |
1820 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
1821 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1822 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
b01a6b3c | 1823 | ((len + pad) < bus->sdiodev->bus_if->maxctl)) |
5b435de0 | 1824 | rdlen += pad; |
9b2d2f2a AS |
1825 | } else if (rdlen % bus->head_align) { |
1826 | rdlen += bus->head_align - (rdlen % bus->head_align); | |
5b435de0 AS |
1827 | } |
1828 | ||
5b435de0 | 1829 | /* Drop if the read is too big or it exceeds our maximum */ |
b01a6b3c | 1830 | if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1831 | brcmf_err("%d-byte control read exceeds %d-byte buffer\n", |
b01a6b3c | 1832 | rdlen, bus->sdiodev->bus_if->maxctl); |
82d7f3c1 | 1833 | brcmf_sdio_rxfail(bus, false, false); |
5b435de0 AS |
1834 | goto done; |
1835 | } | |
1836 | ||
b01a6b3c | 1837 | if ((len - doff) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1838 | brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", |
b01a6b3c | 1839 | len, len - doff, bus->sdiodev->bus_if->maxctl); |
80969836 | 1840 | bus->sdcnt.rx_toolong++; |
82d7f3c1 | 1841 | brcmf_sdio_rxfail(bus, false, false); |
5b435de0 AS |
1842 | goto done; |
1843 | } | |
1844 | ||
dd43a01c | 1845 | /* Read remain of frame body */ |
a7cdd821 | 1846 | sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); |
80969836 | 1847 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1848 | |
1849 | /* Control frame failures need retransmission */ | |
1850 | if (sdret < 0) { | |
5e8149f5 | 1851 | brcmf_err("read %d control bytes failed: %d\n", |
5b435de0 | 1852 | rdlen, sdret); |
80969836 | 1853 | bus->sdcnt.rxc_errors++; |
82d7f3c1 | 1854 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 | 1855 | goto done; |
dd43a01c FL |
1856 | } else |
1857 | memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); | |
5b435de0 AS |
1858 | |
1859 | gotpkt: | |
1860 | ||
1e023829 | 1861 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
dd43a01c | 1862 | buf, len, "RxCtrl:\n"); |
5b435de0 AS |
1863 | |
1864 | /* Point to valid data and indicate its length */ | |
dd43a01c FL |
1865 | spin_lock_bh(&bus->rxctl_lock); |
1866 | if (bus->rxctl) { | |
5e8149f5 | 1867 | brcmf_err("last control frame is being processed.\n"); |
dd43a01c FL |
1868 | spin_unlock_bh(&bus->rxctl_lock); |
1869 | vfree(buf); | |
1870 | goto done; | |
1871 | } | |
1872 | bus->rxctl = buf + doff; | |
1873 | bus->rxctl_orig = buf; | |
5b435de0 | 1874 | bus->rxlen = len - doff; |
dd43a01c | 1875 | spin_unlock_bh(&bus->rxctl_lock); |
5b435de0 AS |
1876 | |
1877 | done: | |
1878 | /* Awake any waiters */ | |
82d7f3c1 | 1879 | brcmf_sdio_dcmd_resp_wake(bus); |
5b435de0 AS |
1880 | } |
1881 | ||
1882 | /* Pad read to blocksize for efficiency */ | |
82d7f3c1 | 1883 | static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) |
5b435de0 AS |
1884 | { |
1885 | if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { | |
1886 | *pad = bus->blocksize - (*rdlen % bus->blocksize); | |
1887 | if (*pad <= bus->roundup && *pad < bus->blocksize && | |
1888 | *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) | |
1889 | *rdlen += *pad; | |
9b2d2f2a AS |
1890 | } else if (*rdlen % bus->head_align) { |
1891 | *rdlen += bus->head_align - (*rdlen % bus->head_align); | |
5b435de0 AS |
1892 | } |
1893 | } | |
1894 | ||
4754fcee | 1895 | static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 | 1896 | { |
5b435de0 AS |
1897 | struct sk_buff *pkt; /* Packet for event or data frames */ |
1898 | u16 pad; /* Number of pad bytes to read */ | |
5b435de0 | 1899 | uint rxleft = 0; /* Remaining number of frames allowed */ |
349e7104 | 1900 | int ret; /* Return code from calls */ |
5b435de0 | 1901 | uint rxcount = 0; /* Total frames read */ |
6bc52319 | 1902 | struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; |
4754fcee | 1903 | u8 head_read = 0; |
5b435de0 AS |
1904 | |
1905 | brcmf_dbg(TRACE, "Enter\n"); | |
1906 | ||
1907 | /* Not finished unless we encounter no more frames indication */ | |
4754fcee | 1908 | bus->rxpending = true; |
5b435de0 | 1909 | |
4754fcee | 1910 | for (rd->seq_num = bus->rx_seq, rxleft = maxframes; |
a1ce7a0d | 1911 | !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; |
4754fcee | 1912 | rd->seq_num++, rxleft--) { |
5b435de0 AS |
1913 | |
1914 | /* Handle glomming separately */ | |
b83db862 | 1915 | if (bus->glomd || !skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1916 | u8 cnt; |
1917 | brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", | |
b83db862 | 1918 | bus->glomd, skb_peek(&bus->glom)); |
82d7f3c1 | 1919 | cnt = brcmf_sdio_rxglom(bus, rd->seq_num); |
5b435de0 | 1920 | brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); |
4754fcee | 1921 | rd->seq_num += cnt - 1; |
5b435de0 AS |
1922 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; |
1923 | continue; | |
1924 | } | |
1925 | ||
4754fcee FL |
1926 | rd->len_left = rd->len; |
1927 | /* read header first for unknow frame length */ | |
38b0b0dd | 1928 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee | 1929 | if (!rd->len) { |
a39be27b | 1930 | ret = brcmf_sdiod_recv_buf(bus->sdiodev, |
a39be27b | 1931 | bus->rxhdr, BRCMF_FIRSTREAD); |
4754fcee | 1932 | bus->sdcnt.f2rxhdrs++; |
349e7104 | 1933 | if (ret < 0) { |
5e8149f5 | 1934 | brcmf_err("RXHEADER FAILED: %d\n", |
349e7104 | 1935 | ret); |
4754fcee | 1936 | bus->sdcnt.rx_hdrfail++; |
82d7f3c1 | 1937 | brcmf_sdio_rxfail(bus, true, true); |
38b0b0dd | 1938 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1939 | continue; |
5b435de0 | 1940 | } |
5b435de0 | 1941 | |
4754fcee | 1942 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), |
1e023829 JP |
1943 | bus->rxhdr, SDPCM_HDRLEN, |
1944 | "RxHdr:\n"); | |
5b435de0 | 1945 | |
6bc52319 FL |
1946 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, |
1947 | BRCMF_SDIO_FT_NORMAL)) { | |
38b0b0dd | 1948 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1949 | if (!bus->rxpending) |
1950 | break; | |
1951 | else | |
1952 | continue; | |
5b435de0 AS |
1953 | } |
1954 | ||
4754fcee | 1955 | if (rd->channel == SDPCM_CONTROL_CHANNEL) { |
82d7f3c1 AS |
1956 | brcmf_sdio_read_control(bus, bus->rxhdr, |
1957 | rd->len, | |
1958 | rd->dat_offset); | |
4754fcee FL |
1959 | /* prepare the descriptor for the next read */ |
1960 | rd->len = rd->len_nxtfrm << 4; | |
1961 | rd->len_nxtfrm = 0; | |
1962 | /* treat all packet as event if we don't know */ | |
1963 | rd->channel = SDPCM_EVENT_CHANNEL; | |
38b0b0dd | 1964 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1965 | continue; |
1966 | } | |
4754fcee FL |
1967 | rd->len_left = rd->len > BRCMF_FIRSTREAD ? |
1968 | rd->len - BRCMF_FIRSTREAD : 0; | |
1969 | head_read = BRCMF_FIRSTREAD; | |
5b435de0 AS |
1970 | } |
1971 | ||
82d7f3c1 | 1972 | brcmf_sdio_pad(bus, &pad, &rd->len_left); |
5b435de0 | 1973 | |
4754fcee | 1974 | pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + |
9b2d2f2a | 1975 | bus->head_align); |
5b435de0 AS |
1976 | if (!pkt) { |
1977 | /* Give up on data, request rtx of events */ | |
5e8149f5 | 1978 | brcmf_err("brcmu_pkt_buf_get_skb failed\n"); |
82d7f3c1 | 1979 | brcmf_sdio_rxfail(bus, false, |
4754fcee | 1980 | RETRYCHAN(rd->channel)); |
38b0b0dd | 1981 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1982 | continue; |
1983 | } | |
4754fcee | 1984 | skb_pull(pkt, head_read); |
9b2d2f2a | 1985 | pkt_align(pkt, rd->len_left, bus->head_align); |
5b435de0 | 1986 | |
a7cdd821 | 1987 | ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); |
80969836 | 1988 | bus->sdcnt.f2rxdata++; |
38b0b0dd | 1989 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1990 | |
349e7104 | 1991 | if (ret < 0) { |
5e8149f5 | 1992 | brcmf_err("read %d bytes from channel %d failed: %d\n", |
349e7104 | 1993 | rd->len, rd->channel, ret); |
5b435de0 | 1994 | brcmu_pkt_buf_free_skb(pkt); |
38b0b0dd | 1995 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 1996 | brcmf_sdio_rxfail(bus, true, |
4754fcee | 1997 | RETRYCHAN(rd->channel)); |
38b0b0dd | 1998 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1999 | continue; |
2000 | } | |
2001 | ||
4754fcee FL |
2002 | if (head_read) { |
2003 | skb_push(pkt, head_read); | |
2004 | memcpy(pkt->data, bus->rxhdr, head_read); | |
2005 | head_read = 0; | |
2006 | } else { | |
2007 | memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); | |
2008 | rd_new.seq_num = rd->seq_num; | |
38b0b0dd | 2009 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
2010 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, |
2011 | BRCMF_SDIO_FT_NORMAL)) { | |
4754fcee FL |
2012 | rd->len = 0; |
2013 | brcmu_pkt_buf_free_skb(pkt); | |
2014 | } | |
2015 | bus->sdcnt.rx_readahead_cnt++; | |
2016 | if (rd->len != roundup(rd_new.len, 16)) { | |
5e8149f5 | 2017 | brcmf_err("frame length mismatch:read %d, should be %d\n", |
4754fcee FL |
2018 | rd->len, |
2019 | roundup(rd_new.len, 16) >> 4); | |
2020 | rd->len = 0; | |
82d7f3c1 | 2021 | brcmf_sdio_rxfail(bus, true, true); |
38b0b0dd | 2022 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
2023 | brcmu_pkt_buf_free_skb(pkt); |
2024 | continue; | |
2025 | } | |
38b0b0dd | 2026 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
2027 | rd->len_nxtfrm = rd_new.len_nxtfrm; |
2028 | rd->channel = rd_new.channel; | |
2029 | rd->dat_offset = rd_new.dat_offset; | |
2030 | ||
2031 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && | |
2032 | BRCMF_DATA_ON()) && | |
2033 | BRCMF_HDRS_ON(), | |
2034 | bus->rxhdr, SDPCM_HDRLEN, | |
2035 | "RxHdr:\n"); | |
2036 | ||
2037 | if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { | |
5e8149f5 | 2038 | brcmf_err("readahead on control packet %d?\n", |
4754fcee FL |
2039 | rd_new.seq_num); |
2040 | /* Force retry w/normal header read */ | |
2041 | rd->len = 0; | |
38b0b0dd | 2042 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 2043 | brcmf_sdio_rxfail(bus, false, true); |
38b0b0dd | 2044 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
2045 | brcmu_pkt_buf_free_skb(pkt); |
2046 | continue; | |
2047 | } | |
2048 | } | |
5b435de0 | 2049 | |
1e023829 | 2050 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
4754fcee | 2051 | pkt->data, rd->len, "Rx Data:\n"); |
5b435de0 | 2052 | |
5b435de0 | 2053 | /* Save superframe descriptor and allocate packet frame */ |
4754fcee | 2054 | if (rd->channel == SDPCM_GLOM_CHANNEL) { |
6bc52319 | 2055 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { |
5b435de0 | 2056 | brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", |
4754fcee | 2057 | rd->len); |
1e023829 | 2058 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
4754fcee | 2059 | pkt->data, rd->len, |
1e023829 | 2060 | "Glom Data:\n"); |
4754fcee | 2061 | __skb_trim(pkt, rd->len); |
5b435de0 AS |
2062 | skb_pull(pkt, SDPCM_HDRLEN); |
2063 | bus->glomd = pkt; | |
2064 | } else { | |
5e8149f5 | 2065 | brcmf_err("%s: glom superframe w/o " |
5b435de0 | 2066 | "descriptor!\n", __func__); |
38b0b0dd | 2067 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 2068 | brcmf_sdio_rxfail(bus, false, false); |
38b0b0dd | 2069 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 2070 | } |
4754fcee FL |
2071 | /* prepare the descriptor for the next read */ |
2072 | rd->len = rd->len_nxtfrm << 4; | |
2073 | rd->len_nxtfrm = 0; | |
2074 | /* treat all packet as event if we don't know */ | |
2075 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
2076 | continue; |
2077 | } | |
2078 | ||
2079 | /* Fill in packet len and prio, deliver upward */ | |
4754fcee FL |
2080 | __skb_trim(pkt, rd->len); |
2081 | skb_pull(pkt, rd->dat_offset); | |
2082 | ||
2083 | /* prepare the descriptor for the next read */ | |
2084 | rd->len = rd->len_nxtfrm << 4; | |
2085 | rd->len_nxtfrm = 0; | |
2086 | /* treat all packet as event if we don't know */ | |
2087 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
2088 | |
2089 | if (pkt->len == 0) { | |
2090 | brcmu_pkt_buf_free_skb(pkt); | |
2091 | continue; | |
5b435de0 AS |
2092 | } |
2093 | ||
05f3820b | 2094 | brcmf_rx_frame(bus->sdiodev->dev, pkt); |
5b435de0 | 2095 | } |
4754fcee | 2096 | |
5b435de0 | 2097 | rxcount = maxframes - rxleft; |
5b435de0 AS |
2098 | /* Message if we hit the limit */ |
2099 | if (!rxleft) | |
4754fcee | 2100 | brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); |
5b435de0 | 2101 | else |
5b435de0 AS |
2102 | brcmf_dbg(DATA, "processed %d frames\n", rxcount); |
2103 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
2104 | if (bus->rxskip) | |
4754fcee FL |
2105 | rd->seq_num--; |
2106 | bus->rx_seq = rd->seq_num; | |
5b435de0 AS |
2107 | |
2108 | return rxcount; | |
2109 | } | |
2110 | ||
5b435de0 | 2111 | static void |
82d7f3c1 | 2112 | brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) |
5b435de0 AS |
2113 | { |
2114 | if (waitqueue_active(&bus->ctrl_wait)) | |
2115 | wake_up_interruptible(&bus->ctrl_wait); | |
2116 | return; | |
2117 | } | |
2118 | ||
8da9d2c8 FL |
2119 | static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) |
2120 | { | |
e217d1c8 | 2121 | u16 head_pad; |
8da9d2c8 FL |
2122 | u8 *dat_buf; |
2123 | ||
8da9d2c8 FL |
2124 | dat_buf = (u8 *)(pkt->data); |
2125 | ||
2126 | /* Check head padding */ | |
e217d1c8 | 2127 | head_pad = ((unsigned long)dat_buf % bus->head_align); |
8da9d2c8 FL |
2128 | if (head_pad) { |
2129 | if (skb_headroom(pkt) < head_pad) { | |
2130 | bus->sdiodev->bus_if->tx_realloc++; | |
2131 | head_pad = 0; | |
2132 | if (skb_cow(pkt, head_pad)) | |
2133 | return -ENOMEM; | |
2134 | } | |
2135 | skb_push(pkt, head_pad); | |
2136 | dat_buf = (u8 *)(pkt->data); | |
2137 | memset(dat_buf, 0, head_pad + bus->tx_hdrlen); | |
2138 | } | |
2139 | return head_pad; | |
2140 | } | |
2141 | ||
5491c11c FL |
2142 | /** |
2143 | * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for | |
2144 | * bus layer usage. | |
2145 | */ | |
b05e9254 | 2146 | /* flag marking a dummy skb added for DMA alignment requirement */ |
5491c11c | 2147 | #define ALIGN_SKB_FLAG 0x8000 |
b05e9254 | 2148 | /* bit mask of data length chopped from the previous packet */ |
5491c11c FL |
2149 | #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff |
2150 | ||
8da9d2c8 | 2151 | static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, |
a64304f0 | 2152 | struct sk_buff_head *pktq, |
8da9d2c8 | 2153 | struct sk_buff *pkt, u16 total_len) |
a64304f0 | 2154 | { |
8da9d2c8 | 2155 | struct brcmf_sdio_dev *sdiodev; |
a64304f0 | 2156 | struct sk_buff *pkt_pad; |
e217d1c8 | 2157 | u16 tail_pad, tail_chop, chain_pad; |
a64304f0 | 2158 | unsigned int blksize; |
8da9d2c8 FL |
2159 | bool lastfrm; |
2160 | int ntail, ret; | |
a64304f0 | 2161 | |
8da9d2c8 | 2162 | sdiodev = bus->sdiodev; |
a64304f0 | 2163 | blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize; |
a64304f0 | 2164 | /* sg entry alignment should be a divisor of block size */ |
e217d1c8 | 2165 | WARN_ON(blksize % bus->sgentry_align); |
a64304f0 AS |
2166 | |
2167 | /* Check tail padding */ | |
8da9d2c8 FL |
2168 | lastfrm = skb_queue_is_last(pktq, pkt); |
2169 | tail_pad = 0; | |
e217d1c8 | 2170 | tail_chop = pkt->len % bus->sgentry_align; |
8da9d2c8 | 2171 | if (tail_chop) |
e217d1c8 | 2172 | tail_pad = bus->sgentry_align - tail_chop; |
8da9d2c8 FL |
2173 | chain_pad = (total_len + tail_pad) % blksize; |
2174 | if (lastfrm && chain_pad) | |
2175 | tail_pad += blksize - chain_pad; | |
a64304f0 | 2176 | if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { |
1eb43018 AS |
2177 | pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + |
2178 | bus->head_align); | |
a64304f0 AS |
2179 | if (pkt_pad == NULL) |
2180 | return -ENOMEM; | |
8da9d2c8 | 2181 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); |
2dc3a8e0 DJ |
2182 | if (unlikely(ret < 0)) { |
2183 | kfree_skb(pkt_pad); | |
8da9d2c8 | 2184 | return ret; |
2dc3a8e0 | 2185 | } |
a64304f0 AS |
2186 | memcpy(pkt_pad->data, |
2187 | pkt->data + pkt->len - tail_chop, | |
2188 | tail_chop); | |
5aa9f0ea | 2189 | *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; |
a64304f0 | 2190 | skb_trim(pkt, pkt->len - tail_chop); |
1eb43018 | 2191 | skb_trim(pkt_pad, tail_pad + tail_chop); |
a64304f0 AS |
2192 | __skb_queue_after(pktq, pkt, pkt_pad); |
2193 | } else { | |
2194 | ntail = pkt->data_len + tail_pad - | |
2195 | (pkt->end - pkt->tail); | |
2196 | if (skb_cloned(pkt) || ntail > 0) | |
2197 | if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) | |
2198 | return -ENOMEM; | |
2199 | if (skb_linearize(pkt)) | |
2200 | return -ENOMEM; | |
a64304f0 AS |
2201 | __skb_put(pkt, tail_pad); |
2202 | } | |
2203 | ||
8da9d2c8 | 2204 | return tail_pad; |
a64304f0 AS |
2205 | } |
2206 | ||
b05e9254 FL |
2207 | /** |
2208 | * brcmf_sdio_txpkt_prep - packet preparation for transmit | |
2209 | * @bus: brcmf_sdio structure pointer | |
2210 | * @pktq: packet list pointer | |
2211 | * @chan: virtual channel to transmit the packet | |
2212 | * | |
2213 | * Processes to be applied to the packet | |
2214 | * - Align data buffer pointer | |
2215 | * - Align data buffer length | |
2216 | * - Prepare header | |
2217 | * Return: negative value if there is error | |
2218 | */ | |
2219 | static int | |
2220 | brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, | |
2221 | uint chan) | |
5b435de0 | 2222 | { |
8da9d2c8 | 2223 | u16 head_pad, total_len; |
a64304f0 | 2224 | struct sk_buff *pkt_next; |
8da9d2c8 FL |
2225 | u8 txseq; |
2226 | int ret; | |
6bc52319 | 2227 | struct brcmf_sdio_hdrinfo hd_info = {0}; |
b05e9254 | 2228 | |
8da9d2c8 FL |
2229 | txseq = bus->tx_seq; |
2230 | total_len = 0; | |
2231 | skb_queue_walk(pktq, pkt_next) { | |
2232 | /* alignment packet inserted in previous | |
2233 | * loop cycle can be skipped as it is | |
2234 | * already properly aligned and does not | |
2235 | * need an sdpcm header. | |
2236 | */ | |
5aa9f0ea | 2237 | if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) |
8da9d2c8 | 2238 | continue; |
5b435de0 | 2239 | |
8da9d2c8 FL |
2240 | /* align packet data pointer */ |
2241 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); | |
2242 | if (ret < 0) | |
2243 | return ret; | |
2244 | head_pad = (u16)ret; | |
2245 | if (head_pad) | |
1eb43018 | 2246 | memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); |
5b435de0 | 2247 | |
8da9d2c8 | 2248 | total_len += pkt_next->len; |
5b435de0 | 2249 | |
a64304f0 | 2250 | hd_info.len = pkt_next->len; |
8da9d2c8 FL |
2251 | hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); |
2252 | if (bus->txglom && pktq->qlen > 1) { | |
2253 | ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, | |
2254 | pkt_next, total_len); | |
2255 | if (ret < 0) | |
2256 | return ret; | |
2257 | hd_info.tail_pad = (u16)ret; | |
2258 | total_len += (u16)ret; | |
2259 | } | |
5b435de0 | 2260 | |
8da9d2c8 FL |
2261 | hd_info.channel = chan; |
2262 | hd_info.dat_offset = head_pad + bus->tx_hdrlen; | |
2263 | hd_info.seq_num = txseq++; | |
2264 | ||
2265 | /* Now fill the header */ | |
2266 | brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); | |
2267 | ||
2268 | if (BRCMF_BYTES_ON() && | |
2269 | ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || | |
2270 | (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) | |
47ab4cd8 | 2271 | brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, |
8da9d2c8 FL |
2272 | "Tx Frame:\n"); |
2273 | else if (BRCMF_HDRS_ON()) | |
47ab4cd8 | 2274 | brcmf_dbg_hex_dump(true, pkt_next->data, |
8da9d2c8 FL |
2275 | head_pad + bus->tx_hdrlen, |
2276 | "Tx Header:\n"); | |
2277 | } | |
2278 | /* Hardware length tag of the first packet should be total | |
2279 | * length of the chain (including padding) | |
2280 | */ | |
2281 | if (bus->txglom) | |
2282 | brcmf_sdio_update_hwhdr(pktq->next->data, total_len); | |
b05e9254 FL |
2283 | return 0; |
2284 | } | |
5b435de0 | 2285 | |
b05e9254 FL |
2286 | /** |
2287 | * brcmf_sdio_txpkt_postp - packet post processing for transmit | |
2288 | * @bus: brcmf_sdio structure pointer | |
2289 | * @pktq: packet list pointer | |
2290 | * | |
2291 | * Processes to be applied to the packet | |
2292 | * - Remove head padding | |
2293 | * - Remove tail padding | |
2294 | */ | |
2295 | static void | |
2296 | brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) | |
2297 | { | |
2298 | u8 *hdr; | |
2299 | u32 dat_offset; | |
8da9d2c8 | 2300 | u16 tail_pad; |
5aa9f0ea | 2301 | u16 dummy_flags, chop_len; |
b05e9254 FL |
2302 | struct sk_buff *pkt_next, *tmp, *pkt_prev; |
2303 | ||
2304 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
5aa9f0ea | 2305 | dummy_flags = *(u16 *)(pkt_next->cb); |
5491c11c FL |
2306 | if (dummy_flags & ALIGN_SKB_FLAG) { |
2307 | chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; | |
b05e9254 FL |
2308 | if (chop_len) { |
2309 | pkt_prev = pkt_next->prev; | |
b05e9254 FL |
2310 | skb_put(pkt_prev, chop_len); |
2311 | } | |
2312 | __skb_unlink(pkt_next, pktq); | |
2313 | brcmu_pkt_buf_free_skb(pkt_next); | |
2314 | } else { | |
8da9d2c8 | 2315 | hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; |
b05e9254 FL |
2316 | dat_offset = le32_to_cpu(*(__le32 *)hdr); |
2317 | dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> | |
2318 | SDPCM_DOFFSET_SHIFT; | |
2319 | skb_pull(pkt_next, dat_offset); | |
8da9d2c8 FL |
2320 | if (bus->txglom) { |
2321 | tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); | |
2322 | skb_trim(pkt_next, pkt_next->len - tail_pad); | |
2323 | } | |
b05e9254 | 2324 | } |
5b435de0 | 2325 | } |
b05e9254 | 2326 | } |
5b435de0 | 2327 | |
b05e9254 FL |
2328 | /* Writes a HW/SW header into the packet and sends it. */ |
2329 | /* Assumes: (a) header space already there, (b) caller holds lock */ | |
82d7f3c1 AS |
2330 | static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, |
2331 | uint chan) | |
b05e9254 FL |
2332 | { |
2333 | int ret; | |
8da9d2c8 | 2334 | struct sk_buff *pkt_next, *tmp; |
b05e9254 FL |
2335 | |
2336 | brcmf_dbg(TRACE, "Enter\n"); | |
2337 | ||
8da9d2c8 | 2338 | ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); |
b05e9254 FL |
2339 | if (ret) |
2340 | goto done; | |
5b435de0 | 2341 | |
38b0b0dd | 2342 | sdio_claim_host(bus->sdiodev->func[1]); |
a7cdd821 | 2343 | ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); |
80969836 | 2344 | bus->sdcnt.f2txdata++; |
5b435de0 | 2345 | |
81c7883c HM |
2346 | if (ret < 0) |
2347 | brcmf_sdio_txfail(bus); | |
5b435de0 | 2348 | |
38b0b0dd | 2349 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2350 | |
2351 | done: | |
8da9d2c8 FL |
2352 | brcmf_sdio_txpkt_postp(bus, pktq); |
2353 | if (ret == 0) | |
2354 | bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; | |
2355 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
2356 | __skb_unlink(pkt_next, pktq); | |
2357 | brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0); | |
2358 | } | |
5b435de0 AS |
2359 | return ret; |
2360 | } | |
2361 | ||
82d7f3c1 | 2362 | static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 AS |
2363 | { |
2364 | struct sk_buff *pkt; | |
8da9d2c8 | 2365 | struct sk_buff_head pktq; |
5b435de0 | 2366 | u32 intstatus = 0; |
8da9d2c8 | 2367 | int ret = 0, prec_out, i; |
5b435de0 | 2368 | uint cnt = 0; |
8da9d2c8 | 2369 | u8 tx_prec_map, pkt_num; |
5b435de0 | 2370 | |
5b435de0 AS |
2371 | brcmf_dbg(TRACE, "Enter\n"); |
2372 | ||
2373 | tx_prec_map = ~bus->flowcontrol; | |
2374 | ||
2375 | /* Send frames until the limit or some other event */ | |
8da9d2c8 FL |
2376 | for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { |
2377 | pkt_num = 1; | |
8da9d2c8 FL |
2378 | if (bus->txglom) |
2379 | pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, | |
af1fa210 | 2380 | bus->sdiodev->txglomsz); |
8da9d2c8 FL |
2381 | pkt_num = min_t(u32, pkt_num, |
2382 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); | |
fed7ec44 HM |
2383 | __skb_queue_head_init(&pktq); |
2384 | spin_lock_bh(&bus->txq_lock); | |
8da9d2c8 FL |
2385 | for (i = 0; i < pkt_num; i++) { |
2386 | pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, | |
2387 | &prec_out); | |
2388 | if (pkt == NULL) | |
2389 | break; | |
2390 | __skb_queue_tail(&pktq, pkt); | |
5b435de0 | 2391 | } |
fed7ec44 | 2392 | spin_unlock_bh(&bus->txq_lock); |
4dd8b26a | 2393 | if (i == 0) |
8da9d2c8 | 2394 | break; |
5b435de0 | 2395 | |
82d7f3c1 | 2396 | ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); |
fed7ec44 | 2397 | |
8da9d2c8 | 2398 | cnt += i; |
5b435de0 AS |
2399 | |
2400 | /* In poll mode, need to check for other events */ | |
b6a8cf2c | 2401 | if (!bus->intr) { |
5b435de0 | 2402 | /* Check device status, signal pending interrupt */ |
38b0b0dd | 2403 | sdio_claim_host(bus->sdiodev->func[1]); |
5c15c23a FL |
2404 | ret = r_sdreg32(bus, &intstatus, |
2405 | offsetof(struct sdpcmd_regs, | |
2406 | intstatus)); | |
38b0b0dd | 2407 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 2408 | bus->sdcnt.f2txdata++; |
5c15c23a | 2409 | if (ret != 0) |
5b435de0 AS |
2410 | break; |
2411 | if (intstatus & bus->hostintmask) | |
1d382273 | 2412 | atomic_set(&bus->ipend, 1); |
5b435de0 AS |
2413 | } |
2414 | } | |
2415 | ||
2416 | /* Deflow-control stack if needed */ | |
a1ce7a0d | 2417 | if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && |
c8bf3484 | 2418 | bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { |
90d03ff7 HM |
2419 | bus->txoff = false; |
2420 | brcmf_txflowblock(bus->sdiodev->dev, false); | |
c8bf3484 | 2421 | } |
5b435de0 AS |
2422 | |
2423 | return cnt; | |
2424 | } | |
2425 | ||
fed7ec44 HM |
2426 | static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) |
2427 | { | |
2428 | u8 doff; | |
2429 | u16 pad; | |
2430 | uint retries = 0; | |
2431 | struct brcmf_sdio_hdrinfo hd_info = {0}; | |
2432 | int ret; | |
2433 | ||
2434 | brcmf_dbg(TRACE, "Enter\n"); | |
2435 | ||
2436 | /* Back the pointer to make room for bus header */ | |
2437 | frame -= bus->tx_hdrlen; | |
2438 | len += bus->tx_hdrlen; | |
2439 | ||
2440 | /* Add alignment padding (optional for ctl frames) */ | |
2441 | doff = ((unsigned long)frame % bus->head_align); | |
2442 | if (doff) { | |
2443 | frame -= doff; | |
2444 | len += doff; | |
2445 | memset(frame + bus->tx_hdrlen, 0, doff); | |
2446 | } | |
2447 | ||
2448 | /* Round send length to next SDIO block */ | |
2449 | pad = 0; | |
2450 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2451 | pad = bus->blocksize - (len % bus->blocksize); | |
2452 | if ((pad > bus->roundup) || (pad >= bus->blocksize)) | |
2453 | pad = 0; | |
2454 | } else if (len % bus->head_align) { | |
2455 | pad = bus->head_align - (len % bus->head_align); | |
2456 | } | |
2457 | len += pad; | |
2458 | ||
2459 | hd_info.len = len - pad; | |
2460 | hd_info.channel = SDPCM_CONTROL_CHANNEL; | |
2461 | hd_info.dat_offset = doff + bus->tx_hdrlen; | |
2462 | hd_info.seq_num = bus->tx_seq; | |
2463 | hd_info.lastfrm = true; | |
2464 | hd_info.tail_pad = pad; | |
2465 | brcmf_sdio_hdpack(bus, frame, &hd_info); | |
2466 | ||
2467 | if (bus->txglom) | |
2468 | brcmf_sdio_update_hwhdr(frame, len); | |
2469 | ||
2470 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), | |
2471 | frame, len, "Tx Frame:\n"); | |
2472 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && | |
2473 | BRCMF_HDRS_ON(), | |
2474 | frame, min_t(u16, len, 16), "TxHdr:\n"); | |
2475 | ||
2476 | do { | |
2477 | ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); | |
2478 | ||
2479 | if (ret < 0) | |
2480 | brcmf_sdio_txfail(bus); | |
2481 | else | |
2482 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; | |
2483 | } while (ret < 0 && retries++ < TXRETRIES); | |
2484 | ||
2485 | return ret; | |
2486 | } | |
2487 | ||
82d7f3c1 | 2488 | static void brcmf_sdio_bus_stop(struct device *dev) |
a9ffda88 FL |
2489 | { |
2490 | u32 local_hostintmask; | |
2491 | u8 saveclk; | |
a9ffda88 FL |
2492 | int err; |
2493 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
0a332e46 | 2494 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
a9ffda88 FL |
2495 | struct brcmf_sdio *bus = sdiodev->bus; |
2496 | ||
2497 | brcmf_dbg(TRACE, "Enter\n"); | |
2498 | ||
2499 | if (bus->watchdog_tsk) { | |
2500 | send_sig(SIGTERM, bus->watchdog_tsk, 1); | |
2501 | kthread_stop(bus->watchdog_tsk); | |
2502 | bus->watchdog_tsk = NULL; | |
2503 | } | |
2504 | ||
a1ce7a0d | 2505 | if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { |
bb350711 AS |
2506 | sdio_claim_host(sdiodev->func[1]); |
2507 | ||
2508 | /* Enable clock for device interrupts */ | |
2509 | brcmf_sdio_bus_sleep(bus, false, false); | |
2510 | ||
2511 | /* Disable and clear interrupts at the chip level also */ | |
2512 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask)); | |
2513 | local_hostintmask = bus->hostintmask; | |
2514 | bus->hostintmask = 0; | |
2515 | ||
2516 | /* Force backplane clocks to assure F2 interrupt propagates */ | |
2517 | saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
2518 | &err); | |
2519 | if (!err) | |
2520 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
2521 | (saveclk | SBSDIO_FORCE_HT), &err); | |
2522 | if (err) | |
2523 | brcmf_err("Failed to force clock for F2: err %d\n", | |
2524 | err); | |
a9ffda88 | 2525 | |
bb350711 AS |
2526 | /* Turn off the bus (F2), free any pending packets */ |
2527 | brcmf_dbg(INTR, "disable SDIO interrupts\n"); | |
2528 | sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); | |
a9ffda88 | 2529 | |
bb350711 AS |
2530 | /* Clear any pending interrupts now that F2 is disabled */ |
2531 | w_sdreg32(bus, local_hostintmask, | |
2532 | offsetof(struct sdpcmd_regs, intstatus)); | |
a9ffda88 | 2533 | |
bb350711 | 2534 | sdio_release_host(sdiodev->func[1]); |
a9ffda88 | 2535 | } |
a9ffda88 FL |
2536 | /* Clear the data packet queues */ |
2537 | brcmu_pktq_flush(&bus->txq, true, NULL, NULL); | |
2538 | ||
2539 | /* Clear any held glomming stuff */ | |
297540f6 | 2540 | brcmu_pkt_buf_free_skb(bus->glomd); |
82d7f3c1 | 2541 | brcmf_sdio_free_glom(bus); |
a9ffda88 FL |
2542 | |
2543 | /* Clear rx control and wake any waiters */ | |
dd43a01c | 2544 | spin_lock_bh(&bus->rxctl_lock); |
a9ffda88 | 2545 | bus->rxlen = 0; |
dd43a01c | 2546 | spin_unlock_bh(&bus->rxctl_lock); |
82d7f3c1 | 2547 | brcmf_sdio_dcmd_resp_wake(bus); |
a9ffda88 FL |
2548 | |
2549 | /* Reset some F2 state stuff */ | |
2550 | bus->rxskip = false; | |
2551 | bus->tx_seq = bus->rx_seq = 0; | |
a9ffda88 FL |
2552 | } |
2553 | ||
82d7f3c1 | 2554 | static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) |
ba89bf19 FL |
2555 | { |
2556 | unsigned long flags; | |
2557 | ||
668761ac HM |
2558 | if (bus->sdiodev->oob_irq_requested) { |
2559 | spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags); | |
2560 | if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) { | |
2561 | enable_irq(bus->sdiodev->pdata->oob_irq_nr); | |
2562 | bus->sdiodev->irq_en = true; | |
2563 | } | |
2564 | spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags); | |
ba89bf19 | 2565 | } |
ba89bf19 | 2566 | } |
ba89bf19 | 2567 | |
4531603a FL |
2568 | static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) |
2569 | { | |
cb7cf7be | 2570 | struct brcmf_core *buscore; |
4531603a FL |
2571 | u32 addr; |
2572 | unsigned long val; | |
5cbb9c28 | 2573 | int ret; |
4531603a | 2574 | |
cb7cf7be AS |
2575 | buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
2576 | addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus); | |
4531603a | 2577 | |
a39be27b | 2578 | val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret); |
4531603a FL |
2579 | bus->sdcnt.f1regdata++; |
2580 | if (ret != 0) | |
5cbb9c28 | 2581 | return ret; |
4531603a FL |
2582 | |
2583 | val &= bus->hostintmask; | |
2584 | atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); | |
2585 | ||
2586 | /* Clear interrupts */ | |
2587 | if (val) { | |
a39be27b | 2588 | brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret); |
4531603a | 2589 | bus->sdcnt.f1regdata++; |
d3928d09 | 2590 | atomic_or(val, &bus->intstatus); |
4531603a FL |
2591 | } |
2592 | ||
2593 | return ret; | |
2594 | } | |
2595 | ||
82d7f3c1 | 2596 | static void brcmf_sdio_dpc(struct brcmf_sdio *bus) |
5b435de0 | 2597 | { |
4531603a FL |
2598 | u32 newstatus = 0; |
2599 | unsigned long intstatus; | |
5b435de0 | 2600 | uint txlimit = bus->txbound; /* Tx frames to send before resched */ |
b6a8cf2c | 2601 | uint framecnt; /* Temporary counter of tx/rx frames */ |
5cbb9c28 | 2602 | int err = 0; |
5b435de0 AS |
2603 | |
2604 | brcmf_dbg(TRACE, "Enter\n"); | |
2605 | ||
38b0b0dd | 2606 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2607 | |
2608 | /* If waiting for HTAVAIL, check status */ | |
4a3da990 | 2609 | if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { |
5b435de0 AS |
2610 | u8 clkctl, devctl = 0; |
2611 | ||
8ae74654 | 2612 | #ifdef DEBUG |
5b435de0 | 2613 | /* Check for inconsistent device control */ |
a39be27b AS |
2614 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
2615 | SBSDIO_DEVICE_CTL, &err); | |
8ae74654 | 2616 | #endif /* DEBUG */ |
5b435de0 AS |
2617 | |
2618 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
a39be27b AS |
2619 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
2620 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 2621 | |
c3203374 | 2622 | brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", |
5b435de0 AS |
2623 | devctl, clkctl); |
2624 | ||
2625 | if (SBSDIO_HTAV(clkctl)) { | |
a39be27b AS |
2626 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
2627 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 2628 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
2629 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
2630 | devctl, &err); | |
5b435de0 | 2631 | bus->clkstate = CLK_AVAIL; |
5b435de0 AS |
2632 | } |
2633 | } | |
2634 | ||
5b435de0 | 2635 | /* Make sure backplane clock is on */ |
82d7f3c1 | 2636 | brcmf_sdio_bus_sleep(bus, false, true); |
5b435de0 AS |
2637 | |
2638 | /* Pending interrupt indicates new device status */ | |
1d382273 FL |
2639 | if (atomic_read(&bus->ipend) > 0) { |
2640 | atomic_set(&bus->ipend, 0); | |
4531603a | 2641 | err = brcmf_sdio_intr_rstatus(bus); |
5b435de0 AS |
2642 | } |
2643 | ||
4531603a FL |
2644 | /* Start with leftover status bits */ |
2645 | intstatus = atomic_xchg(&bus->intstatus, 0); | |
5b435de0 AS |
2646 | |
2647 | /* Handle flow-control change: read new state in case our ack | |
2648 | * crossed another change interrupt. If change still set, assume | |
2649 | * FC ON for safety, let next loop through do the debounce. | |
2650 | */ | |
2651 | if (intstatus & I_HMB_FC_CHANGE) { | |
2652 | intstatus &= ~I_HMB_FC_CHANGE; | |
5c15c23a FL |
2653 | err = w_sdreg32(bus, I_HMB_FC_CHANGE, |
2654 | offsetof(struct sdpcmd_regs, intstatus)); | |
5b435de0 | 2655 | |
5c15c23a FL |
2656 | err = r_sdreg32(bus, &newstatus, |
2657 | offsetof(struct sdpcmd_regs, intstatus)); | |
80969836 | 2658 | bus->sdcnt.f1regdata += 2; |
4531603a FL |
2659 | atomic_set(&bus->fcstate, |
2660 | !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); | |
5b435de0 AS |
2661 | intstatus |= (newstatus & bus->hostintmask); |
2662 | } | |
2663 | ||
2664 | /* Handle host mailbox indication */ | |
2665 | if (intstatus & I_HMB_HOST_INT) { | |
2666 | intstatus &= ~I_HMB_HOST_INT; | |
82d7f3c1 | 2667 | intstatus |= brcmf_sdio_hostmail(bus); |
5b435de0 AS |
2668 | } |
2669 | ||
38b0b0dd | 2670 | sdio_release_host(bus->sdiodev->func[1]); |
7cdf57d3 | 2671 | |
5b435de0 AS |
2672 | /* Generally don't ask for these, can get CRC errors... */ |
2673 | if (intstatus & I_WR_OOSYNC) { | |
5e8149f5 | 2674 | brcmf_err("Dongle reports WR_OOSYNC\n"); |
5b435de0 AS |
2675 | intstatus &= ~I_WR_OOSYNC; |
2676 | } | |
2677 | ||
2678 | if (intstatus & I_RD_OOSYNC) { | |
5e8149f5 | 2679 | brcmf_err("Dongle reports RD_OOSYNC\n"); |
5b435de0 AS |
2680 | intstatus &= ~I_RD_OOSYNC; |
2681 | } | |
2682 | ||
2683 | if (intstatus & I_SBINT) { | |
5e8149f5 | 2684 | brcmf_err("Dongle reports SBINT\n"); |
5b435de0 AS |
2685 | intstatus &= ~I_SBINT; |
2686 | } | |
2687 | ||
2688 | /* Would be active due to wake-wlan in gSPI */ | |
2689 | if (intstatus & I_CHIPACTIVE) { | |
2690 | brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); | |
2691 | intstatus &= ~I_CHIPACTIVE; | |
2692 | } | |
2693 | ||
2694 | /* Ignore frame indications if rxskip is set */ | |
2695 | if (bus->rxskip) | |
2696 | intstatus &= ~I_HMB_FRAME_IND; | |
2697 | ||
2698 | /* On frame indication, read available frames */ | |
b6a8cf2c HM |
2699 | if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { |
2700 | brcmf_sdio_readframes(bus, bus->rxbound); | |
4754fcee | 2701 | if (!bus->rxpending) |
5b435de0 | 2702 | intstatus &= ~I_HMB_FRAME_IND; |
5b435de0 AS |
2703 | } |
2704 | ||
2705 | /* Keep still-pending events for next scheduling */ | |
5cbb9c28 | 2706 | if (intstatus) |
d3928d09 | 2707 | atomic_or(intstatus, &bus->intstatus); |
5b435de0 | 2708 | |
82d7f3c1 | 2709 | brcmf_sdio_clrintr(bus); |
ba89bf19 | 2710 | |
fed7ec44 | 2711 | if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && |
4dd8b26a HM |
2712 | data_ok(bus)) { |
2713 | sdio_claim_host(bus->sdiodev->func[1]); | |
449e58b8 HM |
2714 | if (bus->ctrl_frame_stat) { |
2715 | err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, | |
2716 | bus->ctrl_frame_len); | |
2717 | bus->ctrl_frame_err = err; | |
2c64e16d | 2718 | wmb(); |
449e58b8 HM |
2719 | bus->ctrl_frame_stat = false; |
2720 | } | |
4dd8b26a | 2721 | sdio_release_host(bus->sdiodev->func[1]); |
4dd8b26a | 2722 | brcmf_sdio_wait_event_wakeup(bus); |
5b435de0 AS |
2723 | } |
2724 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
fed7ec44 HM |
2725 | if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && |
2726 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && | |
2727 | data_ok(bus)) { | |
4754fcee FL |
2728 | framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : |
2729 | txlimit; | |
b6a8cf2c | 2730 | brcmf_sdio_sendfromq(bus, framecnt); |
5b435de0 AS |
2731 | } |
2732 | ||
a1ce7a0d | 2733 | if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { |
5e8149f5 | 2734 | brcmf_err("failed backplane access over SDIO, halting operation\n"); |
4531603a | 2735 | atomic_set(&bus->intstatus, 0); |
de6878c8 | 2736 | if (bus->ctrl_frame_stat) { |
449e58b8 HM |
2737 | sdio_claim_host(bus->sdiodev->func[1]); |
2738 | if (bus->ctrl_frame_stat) { | |
2739 | bus->ctrl_frame_err = -ENODEV; | |
2c64e16d | 2740 | wmb(); |
449e58b8 HM |
2741 | bus->ctrl_frame_stat = false; |
2742 | brcmf_sdio_wait_event_wakeup(bus); | |
2743 | } | |
2744 | sdio_release_host(bus->sdiodev->func[1]); | |
de6878c8 | 2745 | } |
4531603a FL |
2746 | } else if (atomic_read(&bus->intstatus) || |
2747 | atomic_read(&bus->ipend) > 0 || | |
2748 | (!atomic_read(&bus->fcstate) && | |
2749 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
b6a8cf2c | 2750 | data_ok(bus))) { |
2c64e16d | 2751 | bus->dpc_triggered = true; |
5b435de0 | 2752 | } |
5b435de0 AS |
2753 | } |
2754 | ||
82d7f3c1 | 2755 | static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) |
e2432b67 AS |
2756 | { |
2757 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
2758 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
2759 | struct brcmf_sdio *bus = sdiodev->bus; | |
2760 | ||
2761 | return &bus->txq; | |
2762 | } | |
2763 | ||
84936626 HM |
2764 | static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) |
2765 | { | |
2766 | struct sk_buff *p; | |
2767 | int eprec = -1; /* precedence to evict from */ | |
2768 | ||
2769 | /* Fast case, precedence queue is not full and we are also not | |
2770 | * exceeding total queue length | |
2771 | */ | |
2772 | if (!pktq_pfull(q, prec) && !pktq_full(q)) { | |
2773 | brcmu_pktq_penq(q, prec, pkt); | |
2774 | return true; | |
2775 | } | |
2776 | ||
2777 | /* Determine precedence from which to evict packet, if any */ | |
2778 | if (pktq_pfull(q, prec)) { | |
2779 | eprec = prec; | |
2780 | } else if (pktq_full(q)) { | |
2781 | p = brcmu_pktq_peek_tail(q, &eprec); | |
2782 | if (eprec > prec) | |
2783 | return false; | |
2784 | } | |
2785 | ||
2786 | /* Evict if needed */ | |
2787 | if (eprec >= 0) { | |
2788 | /* Detect queueing to unconfigured precedence */ | |
2789 | if (eprec == prec) | |
2790 | return false; /* refuse newer (incoming) packet */ | |
2791 | /* Evict packet according to discard policy */ | |
2792 | p = brcmu_pktq_pdeq_tail(q, eprec); | |
2793 | if (p == NULL) | |
2794 | brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); | |
2795 | brcmu_pkt_buf_free_skb(p); | |
2796 | } | |
2797 | ||
2798 | /* Enqueue */ | |
2799 | p = brcmu_pktq_penq(q, prec, pkt); | |
2800 | if (p == NULL) | |
2801 | brcmf_err("brcmu_pktq_penq() failed\n"); | |
2802 | ||
2803 | return p != NULL; | |
2804 | } | |
2805 | ||
82d7f3c1 | 2806 | static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) |
5b435de0 AS |
2807 | { |
2808 | int ret = -EBADE; | |
44ff5660 | 2809 | uint prec; |
bf347bb9 | 2810 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2811 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
bf347bb9 | 2812 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 | 2813 | |
44ff5660 | 2814 | brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); |
5768f31e AS |
2815 | if (sdiodev->state != BRCMF_SDIOD_DATA) |
2816 | return -EIO; | |
5b435de0 AS |
2817 | |
2818 | /* Add space for the header */ | |
706478cb | 2819 | skb_push(pkt, bus->tx_hdrlen); |
5b435de0 AS |
2820 | /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ |
2821 | ||
2822 | prec = prio2prec((pkt->priority & PRIOMASK)); | |
2823 | ||
2824 | /* Check for existing queue, current flow-control, | |
2825 | pending event, or pending clock */ | |
2826 | brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); | |
80969836 | 2827 | bus->sdcnt.fcqueued++; |
5b435de0 AS |
2828 | |
2829 | /* Priority based enq */ | |
fed7ec44 | 2830 | spin_lock_bh(&bus->txq_lock); |
5aa9f0ea AS |
2831 | /* reset bus_flags in packet cb */ |
2832 | *(u16 *)(pkt->cb) = 0; | |
84936626 | 2833 | if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { |
706478cb | 2834 | skb_pull(pkt, bus->tx_hdrlen); |
5e8149f5 | 2835 | brcmf_err("out of bus->txq !!!\n"); |
5b435de0 AS |
2836 | ret = -ENOSR; |
2837 | } else { | |
2838 | ret = 0; | |
2839 | } | |
5b435de0 | 2840 | |
c8bf3484 | 2841 | if (pktq_len(&bus->txq) >= TXHI) { |
90d03ff7 | 2842 | bus->txoff = true; |
84936626 | 2843 | brcmf_txflowblock(dev, true); |
c8bf3484 | 2844 | } |
fed7ec44 | 2845 | spin_unlock_bh(&bus->txq_lock); |
5b435de0 | 2846 | |
8ae74654 | 2847 | #ifdef DEBUG |
5b435de0 AS |
2848 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) |
2849 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2850 | #endif | |
f1e68c2e | 2851 | |
99824643 | 2852 | brcmf_sdio_trigger_dpc(bus); |
5b435de0 AS |
2853 | return ret; |
2854 | } | |
2855 | ||
8ae74654 | 2856 | #ifdef DEBUG |
5b435de0 AS |
2857 | #define CONSOLE_LINE_MAX 192 |
2858 | ||
82d7f3c1 | 2859 | static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) |
5b435de0 AS |
2860 | { |
2861 | struct brcmf_console *c = &bus->console; | |
2862 | u8 line[CONSOLE_LINE_MAX], ch; | |
2863 | u32 n, idx, addr; | |
2864 | int rv; | |
2865 | ||
2866 | /* Don't do anything until FWREADY updates console address */ | |
2867 | if (bus->console_addr == 0) | |
2868 | return 0; | |
2869 | ||
2870 | /* Read console log struct */ | |
2871 | addr = bus->console_addr + offsetof(struct rte_console, log_le); | |
a39be27b AS |
2872 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, |
2873 | sizeof(c->log_le)); | |
5b435de0 AS |
2874 | if (rv < 0) |
2875 | return rv; | |
2876 | ||
2877 | /* Allocate console buffer (one time only) */ | |
2878 | if (c->buf == NULL) { | |
2879 | c->bufsize = le32_to_cpu(c->log_le.buf_size); | |
2880 | c->buf = kmalloc(c->bufsize, GFP_ATOMIC); | |
2881 | if (c->buf == NULL) | |
2882 | return -ENOMEM; | |
2883 | } | |
2884 | ||
2885 | idx = le32_to_cpu(c->log_le.idx); | |
2886 | ||
2887 | /* Protect against corrupt value */ | |
2888 | if (idx > c->bufsize) | |
2889 | return -EBADE; | |
2890 | ||
2891 | /* Skip reading the console buffer if the index pointer | |
2892 | has not moved */ | |
2893 | if (idx == c->last) | |
2894 | return 0; | |
2895 | ||
2896 | /* Read the console buffer */ | |
2897 | addr = le32_to_cpu(c->log_le.buf); | |
a39be27b | 2898 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); |
5b435de0 AS |
2899 | if (rv < 0) |
2900 | return rv; | |
2901 | ||
2902 | while (c->last != idx) { | |
2903 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
2904 | if (c->last == idx) { | |
2905 | /* This would output a partial line. | |
2906 | * Instead, back up | |
2907 | * the buffer pointer and output this | |
2908 | * line next time around. | |
2909 | */ | |
2910 | if (c->last >= n) | |
2911 | c->last -= n; | |
2912 | else | |
2913 | c->last = c->bufsize - n; | |
2914 | goto break2; | |
2915 | } | |
2916 | ch = c->buf[c->last]; | |
2917 | c->last = (c->last + 1) % c->bufsize; | |
2918 | if (ch == '\n') | |
2919 | break; | |
2920 | line[n] = ch; | |
2921 | } | |
2922 | ||
2923 | if (n > 0) { | |
2924 | if (line[n - 1] == '\r') | |
2925 | n--; | |
2926 | line[n] = 0; | |
18aad4f8 | 2927 | pr_debug("CONSOLE: %s\n", line); |
5b435de0 AS |
2928 | } |
2929 | } | |
2930 | break2: | |
2931 | ||
2932 | return 0; | |
2933 | } | |
8ae74654 | 2934 | #endif /* DEBUG */ |
5b435de0 | 2935 | |
fcf094f4 | 2936 | static int |
82d7f3c1 | 2937 | brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 | 2938 | { |
47a1ce78 | 2939 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2940 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
47a1ce78 | 2941 | struct brcmf_sdio *bus = sdiodev->bus; |
4dd8b26a | 2942 | int ret; |
5b435de0 AS |
2943 | |
2944 | brcmf_dbg(TRACE, "Enter\n"); | |
5768f31e AS |
2945 | if (sdiodev->state != BRCMF_SDIOD_DATA) |
2946 | return -EIO; | |
5b435de0 | 2947 | |
4dd8b26a HM |
2948 | /* Send from dpc */ |
2949 | bus->ctrl_frame_buf = msg; | |
2950 | bus->ctrl_frame_len = msglen; | |
2c64e16d | 2951 | wmb(); |
4dd8b26a | 2952 | bus->ctrl_frame_stat = true; |
4dd8b26a | 2953 | |
99824643 | 2954 | brcmf_sdio_trigger_dpc(bus); |
4dd8b26a HM |
2955 | wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, |
2956 | msecs_to_jiffies(CTL_DONE_TIMEOUT)); | |
449e58b8 HM |
2957 | ret = 0; |
2958 | if (bus->ctrl_frame_stat) { | |
2959 | sdio_claim_host(bus->sdiodev->func[1]); | |
2960 | if (bus->ctrl_frame_stat) { | |
2961 | brcmf_dbg(SDIO, "ctrl_frame timeout\n"); | |
2962 | bus->ctrl_frame_stat = false; | |
2963 | ret = -ETIMEDOUT; | |
2964 | } | |
2965 | sdio_release_host(bus->sdiodev->func[1]); | |
2966 | } | |
2967 | if (!ret) { | |
4dd8b26a HM |
2968 | brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", |
2969 | bus->ctrl_frame_err); | |
2c64e16d | 2970 | rmb(); |
4dd8b26a | 2971 | ret = bus->ctrl_frame_err; |
5b435de0 AS |
2972 | } |
2973 | ||
5b435de0 | 2974 | if (ret) |
80969836 | 2975 | bus->sdcnt.tx_ctlerrs++; |
5b435de0 | 2976 | else |
80969836 | 2977 | bus->sdcnt.tx_ctlpkts++; |
5b435de0 | 2978 | |
4dd8b26a | 2979 | return ret; |
5b435de0 AS |
2980 | } |
2981 | ||
80969836 | 2982 | #ifdef DEBUG |
1b1e4e9e AS |
2983 | static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, |
2984 | struct sdpcm_shared *sh) | |
4fc0d016 AS |
2985 | { |
2986 | u32 addr, console_ptr, console_size, console_index; | |
2987 | char *conbuf = NULL; | |
2988 | __le32 sh_val; | |
2989 | int rv; | |
4fc0d016 AS |
2990 | |
2991 | /* obtain console information from device memory */ | |
2992 | addr = sh->console_addr + offsetof(struct rte_console, log_le); | |
a39be27b AS |
2993 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2994 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2995 | if (rv < 0) |
2996 | return rv; | |
2997 | console_ptr = le32_to_cpu(sh_val); | |
2998 | ||
2999 | addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); | |
a39be27b AS |
3000 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
3001 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
3002 | if (rv < 0) |
3003 | return rv; | |
3004 | console_size = le32_to_cpu(sh_val); | |
3005 | ||
3006 | addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); | |
a39be27b AS |
3007 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
3008 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
3009 | if (rv < 0) |
3010 | return rv; | |
3011 | console_index = le32_to_cpu(sh_val); | |
3012 | ||
3013 | /* allocate buffer for console data */ | |
3014 | if (console_size <= CONSOLE_BUFFER_MAX) | |
3015 | conbuf = vzalloc(console_size+1); | |
3016 | ||
3017 | if (!conbuf) | |
3018 | return -ENOMEM; | |
3019 | ||
3020 | /* obtain the console data from device */ | |
3021 | conbuf[console_size] = '\0'; | |
a39be27b AS |
3022 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, |
3023 | console_size); | |
4fc0d016 AS |
3024 | if (rv < 0) |
3025 | goto done; | |
3026 | ||
1b1e4e9e AS |
3027 | rv = seq_write(seq, conbuf + console_index, |
3028 | console_size - console_index); | |
4fc0d016 AS |
3029 | if (rv < 0) |
3030 | goto done; | |
3031 | ||
1b1e4e9e AS |
3032 | if (console_index > 0) |
3033 | rv = seq_write(seq, conbuf, console_index - 1); | |
3034 | ||
4fc0d016 AS |
3035 | done: |
3036 | vfree(conbuf); | |
3037 | return rv; | |
3038 | } | |
3039 | ||
1b1e4e9e AS |
3040 | static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, |
3041 | struct sdpcm_shared *sh) | |
4fc0d016 | 3042 | { |
1b1e4e9e | 3043 | int error; |
4fc0d016 | 3044 | struct brcmf_trap_info tr; |
4fc0d016 | 3045 | |
baa9e609 PH |
3046 | if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { |
3047 | brcmf_dbg(INFO, "no trap in firmware\n"); | |
4fc0d016 | 3048 | return 0; |
baa9e609 | 3049 | } |
4fc0d016 | 3050 | |
a39be27b AS |
3051 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, |
3052 | sizeof(struct brcmf_trap_info)); | |
4fc0d016 AS |
3053 | if (error < 0) |
3054 | return error; | |
3055 | ||
1b1e4e9e AS |
3056 | seq_printf(seq, |
3057 | "dongle trap info: type 0x%x @ epc 0x%08x\n" | |
3058 | " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" | |
3059 | " lr 0x%08x pc 0x%08x offset 0x%x\n" | |
3060 | " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" | |
3061 | " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", | |
3062 | le32_to_cpu(tr.type), le32_to_cpu(tr.epc), | |
3063 | le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), | |
3064 | le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), | |
3065 | le32_to_cpu(tr.pc), sh->trap_addr, | |
3066 | le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), | |
3067 | le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), | |
3068 | le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), | |
3069 | le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); | |
3070 | ||
3071 | return 0; | |
4fc0d016 AS |
3072 | } |
3073 | ||
1b1e4e9e AS |
3074 | static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, |
3075 | struct sdpcm_shared *sh) | |
4fc0d016 AS |
3076 | { |
3077 | int error = 0; | |
4fc0d016 AS |
3078 | char file[80] = "?"; |
3079 | char expr[80] = "<???>"; | |
4fc0d016 AS |
3080 | |
3081 | if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { | |
3082 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3083 | return 0; | |
3084 | } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { | |
3085 | brcmf_dbg(INFO, "no assert in dongle\n"); | |
3086 | return 0; | |
3087 | } | |
3088 | ||
38b0b0dd | 3089 | sdio_claim_host(bus->sdiodev->func[1]); |
4fc0d016 | 3090 | if (sh->assert_file_addr != 0) { |
a39be27b AS |
3091 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, |
3092 | sh->assert_file_addr, (u8 *)file, 80); | |
4fc0d016 AS |
3093 | if (error < 0) |
3094 | return error; | |
3095 | } | |
3096 | if (sh->assert_exp_addr != 0) { | |
a39be27b AS |
3097 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, |
3098 | sh->assert_exp_addr, (u8 *)expr, 80); | |
4fc0d016 AS |
3099 | if (error < 0) |
3100 | return error; | |
3101 | } | |
38b0b0dd | 3102 | sdio_release_host(bus->sdiodev->func[1]); |
4fc0d016 | 3103 | |
1b1e4e9e AS |
3104 | seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", |
3105 | file, sh->assert_line, expr); | |
3106 | return 0; | |
4fc0d016 AS |
3107 | } |
3108 | ||
82d7f3c1 | 3109 | static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) |
4fc0d016 AS |
3110 | { |
3111 | int error; | |
3112 | struct sdpcm_shared sh; | |
3113 | ||
4fc0d016 | 3114 | error = brcmf_sdio_readshared(bus, &sh); |
4fc0d016 AS |
3115 | |
3116 | if (error < 0) | |
3117 | return error; | |
3118 | ||
3119 | if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) | |
3120 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3121 | else if (sh.flags & SDPCM_SHARED_ASSERT) | |
5e8149f5 | 3122 | brcmf_err("assertion in dongle\n"); |
4fc0d016 AS |
3123 | |
3124 | if (sh.flags & SDPCM_SHARED_TRAP) | |
5e8149f5 | 3125 | brcmf_err("firmware trap in dongle\n"); |
4fc0d016 AS |
3126 | |
3127 | return 0; | |
3128 | } | |
3129 | ||
1b1e4e9e | 3130 | static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) |
4fc0d016 AS |
3131 | { |
3132 | int error = 0; | |
3133 | struct sdpcm_shared sh; | |
4fc0d016 | 3134 | |
4fc0d016 AS |
3135 | error = brcmf_sdio_readshared(bus, &sh); |
3136 | if (error < 0) | |
3137 | goto done; | |
3138 | ||
1b1e4e9e | 3139 | error = brcmf_sdio_assert_info(seq, bus, &sh); |
4fc0d016 AS |
3140 | if (error < 0) |
3141 | goto done; | |
baa9e609 | 3142 | |
1b1e4e9e | 3143 | error = brcmf_sdio_trap_info(seq, bus, &sh); |
4fc0d016 AS |
3144 | if (error < 0) |
3145 | goto done; | |
baa9e609 | 3146 | |
1b1e4e9e | 3147 | error = brcmf_sdio_dump_console(seq, bus, &sh); |
4fc0d016 | 3148 | |
4fc0d016 | 3149 | done: |
4fc0d016 AS |
3150 | return error; |
3151 | } | |
3152 | ||
1b1e4e9e | 3153 | static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) |
4fc0d016 | 3154 | { |
82d957e0 AS |
3155 | struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); |
3156 | struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; | |
4fc0d016 | 3157 | |
1b1e4e9e AS |
3158 | return brcmf_sdio_died_dump(seq, bus); |
3159 | } | |
3160 | ||
82d957e0 | 3161 | static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) |
1b1e4e9e | 3162 | { |
82d957e0 AS |
3163 | struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); |
3164 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3165 | struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; | |
4fc0d016 | 3166 | |
82d957e0 AS |
3167 | seq_printf(seq, |
3168 | "intrcount: %u\nlastintrs: %u\n" | |
3169 | "pollcnt: %u\nregfails: %u\n" | |
3170 | "tx_sderrs: %u\nfcqueued: %u\n" | |
3171 | "rxrtx: %u\nrx_toolong: %u\n" | |
3172 | "rxc_errors: %u\nrx_hdrfail: %u\n" | |
3173 | "rx_badhdr: %u\nrx_badseq: %u\n" | |
3174 | "fc_rcvd: %u\nfc_xoff: %u\n" | |
3175 | "fc_xon: %u\nrxglomfail: %u\n" | |
3176 | "rxglomframes: %u\nrxglompkts: %u\n" | |
3177 | "f2rxhdrs: %u\nf2rxdata: %u\n" | |
3178 | "f2txdata: %u\nf1regdata: %u\n" | |
3179 | "tickcnt: %u\ntx_ctlerrs: %lu\n" | |
3180 | "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" | |
3181 | "rx_ctlpkts: %lu\nrx_readahead: %lu\n", | |
3182 | sdcnt->intrcount, sdcnt->lastintrs, | |
3183 | sdcnt->pollcnt, sdcnt->regfails, | |
3184 | sdcnt->tx_sderrs, sdcnt->fcqueued, | |
3185 | sdcnt->rxrtx, sdcnt->rx_toolong, | |
3186 | sdcnt->rxc_errors, sdcnt->rx_hdrfail, | |
3187 | sdcnt->rx_badhdr, sdcnt->rx_badseq, | |
3188 | sdcnt->fc_rcvd, sdcnt->fc_xoff, | |
3189 | sdcnt->fc_xon, sdcnt->rxglomfail, | |
3190 | sdcnt->rxglomframes, sdcnt->rxglompkts, | |
3191 | sdcnt->f2rxhdrs, sdcnt->f2rxdata, | |
3192 | sdcnt->f2txdata, sdcnt->f1regdata, | |
3193 | sdcnt->tickcnt, sdcnt->tx_ctlerrs, | |
3194 | sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, | |
3195 | sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); | |
3196 | ||
3197 | return 0; | |
3198 | } | |
4fc0d016 | 3199 | |
80969836 AS |
3200 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3201 | { | |
3202 | struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; | |
4fc0d016 | 3203 | struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); |
80969836 | 3204 | |
4fc0d016 AS |
3205 | if (IS_ERR_OR_NULL(dentry)) |
3206 | return; | |
3207 | ||
9d6c1dc4 AS |
3208 | bus->console_interval = BRCMF_CONSOLE; |
3209 | ||
82d957e0 AS |
3210 | brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); |
3211 | brcmf_debugfs_add_entry(drvr, "counters", | |
3212 | brcmf_debugfs_sdio_count_read); | |
0801e6c5 DK |
3213 | debugfs_create_u32("console_interval", 0644, dentry, |
3214 | &bus->console_interval); | |
80969836 AS |
3215 | } |
3216 | #else | |
82d7f3c1 | 3217 | static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) |
4fc0d016 AS |
3218 | { |
3219 | return 0; | |
3220 | } | |
3221 | ||
80969836 AS |
3222 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3223 | { | |
3224 | } | |
3225 | #endif /* DEBUG */ | |
3226 | ||
fcf094f4 | 3227 | static int |
82d7f3c1 | 3228 | brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
3229 | { |
3230 | int timeleft; | |
3231 | uint rxlen = 0; | |
3232 | bool pending; | |
dd43a01c | 3233 | u8 *buf; |
532cdd3b | 3234 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3235 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
532cdd3b | 3236 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
3237 | |
3238 | brcmf_dbg(TRACE, "Enter\n"); | |
5768f31e AS |
3239 | if (sdiodev->state != BRCMF_SDIOD_DATA) |
3240 | return -EIO; | |
5b435de0 AS |
3241 | |
3242 | /* Wait until control frame is available */ | |
82d7f3c1 | 3243 | timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); |
5b435de0 | 3244 | |
dd43a01c | 3245 | spin_lock_bh(&bus->rxctl_lock); |
5b435de0 AS |
3246 | rxlen = bus->rxlen; |
3247 | memcpy(msg, bus->rxctl, min(msglen, rxlen)); | |
dd43a01c FL |
3248 | bus->rxctl = NULL; |
3249 | buf = bus->rxctl_orig; | |
3250 | bus->rxctl_orig = NULL; | |
5b435de0 | 3251 | bus->rxlen = 0; |
dd43a01c FL |
3252 | spin_unlock_bh(&bus->rxctl_lock); |
3253 | vfree(buf); | |
5b435de0 AS |
3254 | |
3255 | if (rxlen) { | |
3256 | brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", | |
3257 | rxlen, msglen); | |
3258 | } else if (timeleft == 0) { | |
5e8149f5 | 3259 | brcmf_err("resumed on timeout\n"); |
82d7f3c1 | 3260 | brcmf_sdio_checkdied(bus); |
23677ce3 | 3261 | } else if (pending) { |
5b435de0 AS |
3262 | brcmf_dbg(CTL, "cancelled\n"); |
3263 | return -ERESTARTSYS; | |
3264 | } else { | |
3265 | brcmf_dbg(CTL, "resumed for unknown reason?\n"); | |
82d7f3c1 | 3266 | brcmf_sdio_checkdied(bus); |
5b435de0 AS |
3267 | } |
3268 | ||
3269 | if (rxlen) | |
80969836 | 3270 | bus->sdcnt.rx_ctlpkts++; |
5b435de0 | 3271 | else |
80969836 | 3272 | bus->sdcnt.rx_ctlerrs++; |
5b435de0 AS |
3273 | |
3274 | return rxlen ? (int)rxlen : -ETIMEDOUT; | |
3275 | } | |
3276 | ||
a74d036f HM |
3277 | #ifdef DEBUG |
3278 | static bool | |
3279 | brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, | |
3280 | u8 *ram_data, uint ram_sz) | |
3281 | { | |
3282 | char *ram_cmp; | |
3283 | int err; | |
3284 | bool ret = true; | |
3285 | int address; | |
3286 | int offset; | |
3287 | int len; | |
3288 | ||
3289 | /* read back and verify */ | |
3290 | brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, | |
3291 | ram_sz); | |
3292 | ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); | |
3293 | /* do not proceed while no memory but */ | |
3294 | if (!ram_cmp) | |
3295 | return true; | |
3296 | ||
3297 | address = ram_addr; | |
3298 | offset = 0; | |
3299 | while (offset < ram_sz) { | |
3300 | len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : | |
3301 | ram_sz - offset; | |
3302 | err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); | |
3303 | if (err) { | |
3304 | brcmf_err("error %d on reading %d membytes at 0x%08x\n", | |
3305 | err, len, address); | |
3306 | ret = false; | |
3307 | break; | |
3308 | } else if (memcmp(ram_cmp, &ram_data[offset], len)) { | |
3309 | brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", | |
3310 | offset, len); | |
3311 | ret = false; | |
3312 | break; | |
3313 | } | |
3314 | offset += len; | |
3315 | address += len; | |
3316 | } | |
3317 | ||
3318 | kfree(ram_cmp); | |
3319 | ||
3320 | return ret; | |
3321 | } | |
3322 | #else /* DEBUG */ | |
3323 | static bool | |
3324 | brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, | |
3325 | u8 *ram_data, uint ram_sz) | |
3326 | { | |
3327 | return true; | |
3328 | } | |
3329 | #endif /* DEBUG */ | |
3330 | ||
3355650c AS |
3331 | static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, |
3332 | const struct firmware *fw) | |
5b435de0 | 3333 | { |
f2c44fe7 | 3334 | int err; |
f2c44fe7 | 3335 | |
a74d036f HM |
3336 | brcmf_dbg(TRACE, "Enter\n"); |
3337 | ||
f9951c13 HM |
3338 | err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, |
3339 | (u8 *)fw->data, fw->size); | |
3340 | if (err) | |
3341 | brcmf_err("error %d on writing %d membytes at 0x%08x\n", | |
3342 | err, (int)fw->size, bus->ci->rambase); | |
3343 | else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, | |
3344 | (u8 *)fw->data, fw->size)) | |
3345 | err = -EIO; | |
5b435de0 | 3346 | |
f2c44fe7 | 3347 | return err; |
5b435de0 AS |
3348 | } |
3349 | ||
3355650c | 3350 | static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, |
bd0e1b1d | 3351 | void *vars, u32 varsz) |
5b435de0 | 3352 | { |
a74d036f HM |
3353 | int address; |
3354 | int err; | |
3355 | ||
3356 | brcmf_dbg(TRACE, "Enter\n"); | |
5b435de0 | 3357 | |
a74d036f HM |
3358 | address = bus->ci->ramsize - varsz + bus->ci->rambase; |
3359 | err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); | |
3360 | if (err) | |
3361 | brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", | |
3362 | err, varsz, address); | |
3363 | else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) | |
3364 | err = -EIO; | |
3365 | ||
a74d036f | 3366 | return err; |
5b435de0 AS |
3367 | } |
3368 | ||
bd0e1b1d AS |
3369 | static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, |
3370 | const struct firmware *fw, | |
3371 | void *nvram, u32 nvlen) | |
5b435de0 | 3372 | { |
82d7f3c1 | 3373 | int bcmerror = -EFAULT; |
3355650c | 3374 | u32 rstvec; |
82d7f3c1 AS |
3375 | |
3376 | sdio_claim_host(bus->sdiodev->func[1]); | |
3377 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
5b435de0 | 3378 | |
3355650c AS |
3379 | rstvec = get_unaligned_le32(fw->data); |
3380 | brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); | |
3381 | ||
3382 | bcmerror = brcmf_sdio_download_code_file(bus, fw); | |
3383 | release_firmware(fw); | |
3384 | if (bcmerror) { | |
5e8149f5 | 3385 | brcmf_err("dongle image file download failed\n"); |
bd0e1b1d | 3386 | brcmf_fw_nvram_free(nvram); |
5b435de0 AS |
3387 | goto err; |
3388 | } | |
3389 | ||
bd0e1b1d AS |
3390 | bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); |
3391 | brcmf_fw_nvram_free(nvram); | |
3355650c | 3392 | if (bcmerror) { |
5e8149f5 | 3393 | brcmf_err("dongle nvram file download failed\n"); |
3eaa956c FL |
3394 | goto err; |
3395 | } | |
5b435de0 AS |
3396 | |
3397 | /* Take arm out of reset */ | |
d380ebc9 | 3398 | if (!brcmf_chip_set_active(bus->ci, rstvec)) { |
5e8149f5 | 3399 | brcmf_err("error getting out of ARM core reset\n"); |
5b435de0 AS |
3400 | goto err; |
3401 | } | |
3402 | ||
a1cee865 | 3403 | /* Allow full data communication using DPC from now on. */ |
a1ce7a0d | 3404 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); |
5b435de0 AS |
3405 | bcmerror = 0; |
3406 | ||
3407 | err: | |
82d7f3c1 AS |
3408 | brcmf_sdio_clkctl(bus, CLK_SDONLY, false); |
3409 | sdio_release_host(bus->sdiodev->func[1]); | |
5b435de0 AS |
3410 | return bcmerror; |
3411 | } | |
3412 | ||
82d7f3c1 | 3413 | static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) |
4a3da990 PH |
3414 | { |
3415 | int err = 0; | |
3416 | u8 val; | |
3417 | ||
3418 | brcmf_dbg(TRACE, "Enter\n"); | |
3419 | ||
a39be27b | 3420 | val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); |
4a3da990 PH |
3421 | if (err) { |
3422 | brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3423 | return; | |
3424 | } | |
3425 | ||
3426 | val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; | |
a39be27b | 3427 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); |
4a3da990 PH |
3428 | if (err) { |
3429 | brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3430 | return; | |
3431 | } | |
3432 | ||
3433 | /* Add CMD14 Support */ | |
a39be27b AS |
3434 | brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, |
3435 | (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | | |
3436 | SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), | |
3437 | &err); | |
4a3da990 PH |
3438 | if (err) { |
3439 | brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); | |
3440 | return; | |
3441 | } | |
3442 | ||
a39be27b AS |
3443 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3444 | SBSDIO_FORCE_HT, &err); | |
4a3da990 PH |
3445 | if (err) { |
3446 | brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); | |
3447 | return; | |
3448 | } | |
3449 | ||
3450 | /* set flag */ | |
3451 | bus->sr_enabled = true; | |
3452 | brcmf_dbg(INFO, "SR enabled\n"); | |
3453 | } | |
3454 | ||
3455 | /* enable KSO bit */ | |
82d7f3c1 | 3456 | static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) |
4a3da990 PH |
3457 | { |
3458 | u8 val; | |
3459 | int err = 0; | |
3460 | ||
3461 | brcmf_dbg(TRACE, "Enter\n"); | |
3462 | ||
3463 | /* KSO bit added in SDIO core rev 12 */ | |
cb7cf7be | 3464 | if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) |
4a3da990 PH |
3465 | return 0; |
3466 | ||
a39be27b | 3467 | val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); |
4a3da990 PH |
3468 | if (err) { |
3469 | brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); | |
3470 | return err; | |
3471 | } | |
3472 | ||
3473 | if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { | |
3474 | val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << | |
3475 | SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
a39be27b AS |
3476 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
3477 | val, &err); | |
4a3da990 PH |
3478 | if (err) { |
3479 | brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); | |
3480 | return err; | |
3481 | } | |
3482 | } | |
3483 | ||
3484 | return 0; | |
3485 | } | |
3486 | ||
3487 | ||
82d7f3c1 | 3488 | static int brcmf_sdio_bus_preinit(struct device *dev) |
cf458287 AS |
3489 | { |
3490 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3491 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3492 | struct brcmf_sdio *bus = sdiodev->bus; | |
8da9d2c8 | 3493 | uint pad_size; |
cf458287 | 3494 | u32 value; |
cf458287 AS |
3495 | int err; |
3496 | ||
8da9d2c8 FL |
3497 | /* the commands below use the terms tx and rx from |
3498 | * a device perspective, ie. bus:txglom affects the | |
3499 | * bus transfers from device to host. | |
3500 | */ | |
cb7cf7be | 3501 | if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) { |
cf458287 AS |
3502 | /* for sdio core rev < 12, disable txgloming */ |
3503 | value = 0; | |
3504 | err = brcmf_iovar_data_set(dev, "bus:txglom", &value, | |
3505 | sizeof(u32)); | |
3506 | } else { | |
3507 | /* otherwise, set txglomalign */ | |
3508 | value = 4; | |
3509 | if (sdiodev->pdata) | |
3510 | value = sdiodev->pdata->sd_sgentry_align; | |
3511 | /* SDIO ADMA requires at least 32 bit alignment */ | |
3512 | value = max_t(u32, value, 4); | |
3513 | err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, | |
3514 | sizeof(u32)); | |
3515 | } | |
8da9d2c8 FL |
3516 | |
3517 | if (err < 0) | |
3518 | goto done; | |
3519 | ||
3520 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
3521 | if (sdiodev->sg_support) { | |
3522 | bus->txglom = false; | |
3523 | value = 1; | |
3524 | pad_size = bus->sdiodev->func[2]->cur_blksize << 1; | |
8da9d2c8 FL |
3525 | err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", |
3526 | &value, sizeof(u32)); | |
3527 | if (err < 0) { | |
3528 | /* bus:rxglom is allowed to fail */ | |
3529 | err = 0; | |
3530 | } else { | |
3531 | bus->txglom = true; | |
3532 | bus->tx_hdrlen += SDPCM_HWEXT_LEN; | |
3533 | } | |
3534 | } | |
3535 | brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); | |
3536 | ||
3537 | done: | |
cf458287 AS |
3538 | return err; |
3539 | } | |
3540 | ||
99824643 AS |
3541 | void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) |
3542 | { | |
2c64e16d HM |
3543 | if (!bus->dpc_triggered) { |
3544 | bus->dpc_triggered = true; | |
99824643 AS |
3545 | queue_work(bus->brcmf_wq, &bus->datawork); |
3546 | } | |
3547 | } | |
3548 | ||
82d7f3c1 | 3549 | void brcmf_sdio_isr(struct brcmf_sdio *bus) |
5b435de0 | 3550 | { |
5b435de0 AS |
3551 | brcmf_dbg(TRACE, "Enter\n"); |
3552 | ||
3553 | if (!bus) { | |
5e8149f5 | 3554 | brcmf_err("bus is null pointer, exiting\n"); |
5b435de0 AS |
3555 | return; |
3556 | } | |
3557 | ||
5b435de0 | 3558 | /* Count the interrupt call */ |
80969836 | 3559 | bus->sdcnt.intrcount++; |
4531603a FL |
3560 | if (in_interrupt()) |
3561 | atomic_set(&bus->ipend, 1); | |
3562 | else | |
3563 | if (brcmf_sdio_intr_rstatus(bus)) { | |
5e8149f5 | 3564 | brcmf_err("failed backplane access\n"); |
4531603a | 3565 | } |
5b435de0 | 3566 | |
5b435de0 AS |
3567 | /* Disable additional interrupts (is this needed now)? */ |
3568 | if (!bus->intr) | |
5e8149f5 | 3569 | brcmf_err("isr w/o interrupt configured!\n"); |
5b435de0 | 3570 | |
2c64e16d | 3571 | bus->dpc_triggered = true; |
f1e68c2e | 3572 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3573 | } |
3574 | ||
b441ba8d | 3575 | static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) |
5b435de0 | 3576 | { |
5b435de0 AS |
3577 | brcmf_dbg(TIMER, "Enter\n"); |
3578 | ||
5b435de0 | 3579 | /* Poll period: check device if appropriate. */ |
4a3da990 PH |
3580 | if (!bus->sr_enabled && |
3581 | bus->poll && (++bus->polltick >= bus->pollrate)) { | |
5b435de0 AS |
3582 | u32 intstatus = 0; |
3583 | ||
3584 | /* Reset poll tick */ | |
3585 | bus->polltick = 0; | |
3586 | ||
3587 | /* Check device if no interrupts */ | |
80969836 AS |
3588 | if (!bus->intr || |
3589 | (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { | |
5b435de0 | 3590 | |
2c64e16d | 3591 | if (!bus->dpc_triggered) { |
5b435de0 | 3592 | u8 devpend; |
fccfe930 | 3593 | |
38b0b0dd | 3594 | sdio_claim_host(bus->sdiodev->func[1]); |
a39be27b AS |
3595 | devpend = brcmf_sdiod_regrb(bus->sdiodev, |
3596 | SDIO_CCCR_INTx, | |
3597 | NULL); | |
38b0b0dd | 3598 | sdio_release_host(bus->sdiodev->func[1]); |
99824643 AS |
3599 | intstatus = devpend & (INTR_STATUS_FUNC1 | |
3600 | INTR_STATUS_FUNC2); | |
5b435de0 AS |
3601 | } |
3602 | ||
3603 | /* If there is something, make like the ISR and | |
3604 | schedule the DPC */ | |
3605 | if (intstatus) { | |
80969836 | 3606 | bus->sdcnt.pollcnt++; |
1d382273 | 3607 | atomic_set(&bus->ipend, 1); |
5b435de0 | 3608 | |
2c64e16d | 3609 | bus->dpc_triggered = true; |
f1e68c2e | 3610 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3611 | } |
3612 | } | |
3613 | ||
3614 | /* Update interrupt tracking */ | |
80969836 | 3615 | bus->sdcnt.lastintrs = bus->sdcnt.intrcount; |
5b435de0 | 3616 | } |
8ae74654 | 3617 | #ifdef DEBUG |
5b435de0 | 3618 | /* Poll for console output periodically */ |
9d6c1dc4 | 3619 | if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() && |
8d169aa0 | 3620 | bus->console_interval != 0) { |
5b435de0 AS |
3621 | bus->console.count += BRCMF_WD_POLL_MS; |
3622 | if (bus->console.count >= bus->console_interval) { | |
3623 | bus->console.count -= bus->console_interval; | |
38b0b0dd | 3624 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 3625 | /* Make sure backplane clock is on */ |
82d7f3c1 AS |
3626 | brcmf_sdio_bus_sleep(bus, false, false); |
3627 | if (brcmf_sdio_readconsole(bus) < 0) | |
5b435de0 AS |
3628 | /* stop on error */ |
3629 | bus->console_interval = 0; | |
38b0b0dd | 3630 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3631 | } |
3632 | } | |
8ae74654 | 3633 | #endif /* DEBUG */ |
5b435de0 AS |
3634 | |
3635 | /* On idle timeout clear activity flag and/or turn off clock */ | |
2c64e16d HM |
3636 | if (!bus->dpc_triggered) { |
3637 | rmb(); | |
3638 | if ((!bus->dpc_running) && (bus->idletime > 0) && | |
3639 | (bus->clkstate == CLK_AVAIL)) { | |
3640 | bus->idlecount++; | |
3641 | if (bus->idlecount > bus->idletime) { | |
3642 | brcmf_dbg(SDIO, "idle\n"); | |
3643 | sdio_claim_host(bus->sdiodev->func[1]); | |
3644 | brcmf_sdio_wd_timer(bus, 0); | |
3645 | bus->idlecount = 0; | |
3646 | brcmf_sdio_bus_sleep(bus, true, false); | |
3647 | sdio_release_host(bus->sdiodev->func[1]); | |
3648 | } | |
3649 | } else { | |
5b435de0 | 3650 | bus->idlecount = 0; |
5b435de0 | 3651 | } |
b441ba8d HM |
3652 | } else { |
3653 | bus->idlecount = 0; | |
5b435de0 | 3654 | } |
5b435de0 AS |
3655 | } |
3656 | ||
f1e68c2e FL |
3657 | static void brcmf_sdio_dataworker(struct work_struct *work) |
3658 | { | |
3659 | struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, | |
3660 | datawork); | |
f1e68c2e | 3661 | |
2c64e16d HM |
3662 | bus->dpc_running = true; |
3663 | wmb(); | |
3664 | while (ACCESS_ONCE(bus->dpc_triggered)) { | |
3665 | bus->dpc_triggered = false; | |
82d7f3c1 | 3666 | brcmf_sdio_dpc(bus); |
b441ba8d | 3667 | bus->idlecount = 0; |
f1e68c2e | 3668 | } |
2c64e16d | 3669 | bus->dpc_running = false; |
99824643 AS |
3670 | if (brcmf_sdiod_freezing(bus->sdiodev)) { |
3671 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); | |
3672 | brcmf_sdiod_try_freeze(bus->sdiodev); | |
3673 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); | |
3674 | } | |
f1e68c2e FL |
3675 | } |
3676 | ||
65d80d0b AS |
3677 | static void |
3678 | brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, | |
cb7cf7be | 3679 | struct brcmf_chip *ci, u32 drivestrength) |
65d80d0b AS |
3680 | { |
3681 | const struct sdiod_drive_str *str_tab = NULL; | |
3682 | u32 str_mask; | |
3683 | u32 str_shift; | |
cb7cf7be | 3684 | u32 base; |
65d80d0b AS |
3685 | u32 i; |
3686 | u32 drivestrength_sel = 0; | |
3687 | u32 cc_data_temp; | |
3688 | u32 addr; | |
3689 | ||
cb7cf7be | 3690 | if (!(ci->cc_caps & CC_CAP_PMU)) |
65d80d0b AS |
3691 | return; |
3692 | ||
3693 | switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { | |
5779ae6a | 3694 | case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): |
65d80d0b AS |
3695 | str_tab = sdiod_drvstr_tab1_1v8; |
3696 | str_mask = 0x00003800; | |
3697 | str_shift = 11; | |
3698 | break; | |
5779ae6a | 3699 | case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): |
65d80d0b AS |
3700 | str_tab = sdiod_drvstr_tab6_1v8; |
3701 | str_mask = 0x00001800; | |
3702 | str_shift = 11; | |
3703 | break; | |
5779ae6a | 3704 | case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): |
65d80d0b AS |
3705 | /* note: 43143 does not support tristate */ |
3706 | i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; | |
3707 | if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { | |
3708 | str_tab = sdiod_drvstr_tab2_3v3; | |
3709 | str_mask = 0x00000007; | |
3710 | str_shift = 0; | |
3711 | } else | |
3712 | brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", | |
cb7cf7be | 3713 | ci->name, drivestrength); |
65d80d0b | 3714 | break; |
5779ae6a | 3715 | case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): |
65d80d0b AS |
3716 | str_tab = sdiod_drive_strength_tab5_1v8; |
3717 | str_mask = 0x00003800; | |
3718 | str_shift = 11; | |
3719 | break; | |
3720 | default: | |
3721 | brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", | |
cb7cf7be | 3722 | ci->name, ci->chiprev, ci->pmurev); |
65d80d0b AS |
3723 | break; |
3724 | } | |
3725 | ||
3726 | if (str_tab != NULL) { | |
3727 | for (i = 0; str_tab[i].strength != 0; i++) { | |
3728 | if (drivestrength >= str_tab[i].strength) { | |
3729 | drivestrength_sel = str_tab[i].sel; | |
3730 | break; | |
3731 | } | |
3732 | } | |
cb7cf7be | 3733 | base = brcmf_chip_get_chipcommon(ci)->base; |
65d80d0b AS |
3734 | addr = CORE_CC_REG(base, chipcontrol_addr); |
3735 | brcmf_sdiod_regwl(sdiodev, addr, 1, NULL); | |
3736 | cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL); | |
3737 | cc_data_temp &= ~str_mask; | |
3738 | drivestrength_sel <<= str_shift; | |
3739 | cc_data_temp |= drivestrength_sel; | |
3740 | brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL); | |
3741 | ||
3742 | brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", | |
3743 | str_tab[i].strength, drivestrength, cc_data_temp); | |
3744 | } | |
3745 | } | |
3746 | ||
cb7cf7be | 3747 | static int brcmf_sdio_buscoreprep(void *ctx) |
65d80d0b | 3748 | { |
cb7cf7be | 3749 | struct brcmf_sdio_dev *sdiodev = ctx; |
65d80d0b AS |
3750 | int err = 0; |
3751 | u8 clkval, clkset; | |
3752 | ||
3753 | /* Try forcing SDIO core to do ALPAvail request only */ | |
3754 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; | |
3755 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
3756 | if (err) { | |
3757 | brcmf_err("error writing for HT off\n"); | |
3758 | return err; | |
3759 | } | |
3760 | ||
3761 | /* If register supported, wait for ALPAvail and then force ALP */ | |
3762 | /* This may take up to 15 milliseconds */ | |
3763 | clkval = brcmf_sdiod_regrb(sdiodev, | |
3764 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); | |
3765 | ||
3766 | if ((clkval & ~SBSDIO_AVBITS) != clkset) { | |
3767 | brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", | |
3768 | clkset, clkval); | |
3769 | return -EACCES; | |
3770 | } | |
3771 | ||
3772 | SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev, | |
3773 | SBSDIO_FUNC1_CHIPCLKCSR, NULL)), | |
3774 | !SBSDIO_ALPAV(clkval)), | |
3775 | PMU_MAX_TRANSITION_DLY); | |
3776 | if (!SBSDIO_ALPAV(clkval)) { | |
3777 | brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", | |
3778 | clkval); | |
3779 | return -EBUSY; | |
3780 | } | |
3781 | ||
3782 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; | |
3783 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
3784 | udelay(65); | |
3785 | ||
3786 | /* Also, disable the extra SDIO pull-ups */ | |
3787 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); | |
3788 | ||
3789 | return 0; | |
3790 | } | |
3791 | ||
d380ebc9 AS |
3792 | static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, |
3793 | u32 rstvec) | |
cb7cf7be AS |
3794 | { |
3795 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3796 | struct brcmf_core *core; | |
3797 | u32 reg_addr; | |
3798 | ||
3799 | /* clear all interrupts */ | |
3800 | core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV); | |
3801 | reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus); | |
3802 | brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL); | |
3803 | ||
3804 | if (rstvec) | |
3805 | /* Write reset vector to address 0 */ | |
3806 | brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, | |
3807 | sizeof(rstvec)); | |
3808 | } | |
3809 | ||
3810 | static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) | |
3811 | { | |
3812 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3813 | u32 val, rev; | |
3814 | ||
3815 | val = brcmf_sdiod_regrl(sdiodev, addr, NULL); | |
8bd61f8d | 3816 | if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 && |
cb7cf7be AS |
3817 | addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) { |
3818 | rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; | |
3819 | if (rev >= 2) { | |
3820 | val &= ~CID_ID_MASK; | |
5779ae6a | 3821 | val |= BRCM_CC_4339_CHIP_ID; |
cb7cf7be AS |
3822 | } |
3823 | } | |
3824 | return val; | |
3825 | } | |
3826 | ||
3827 | static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) | |
3828 | { | |
3829 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3830 | ||
3831 | brcmf_sdiod_regwl(sdiodev, addr, val, NULL); | |
3832 | } | |
3833 | ||
3834 | static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { | |
3835 | .prepare = brcmf_sdio_buscoreprep, | |
d380ebc9 | 3836 | .activate = brcmf_sdio_buscore_activate, |
cb7cf7be AS |
3837 | .read32 = brcmf_sdio_buscore_read32, |
3838 | .write32 = brcmf_sdio_buscore_write32, | |
3839 | }; | |
3840 | ||
5b435de0 | 3841 | static bool |
82d7f3c1 | 3842 | brcmf_sdio_probe_attach(struct brcmf_sdio *bus) |
5b435de0 AS |
3843 | { |
3844 | u8 clkctl = 0; | |
3845 | int err = 0; | |
3846 | int reg_addr; | |
3847 | u32 reg_val; | |
668761ac | 3848 | u32 drivestrength; |
5b435de0 | 3849 | |
38b0b0dd FL |
3850 | sdio_claim_host(bus->sdiodev->func[1]); |
3851 | ||
18aad4f8 | 3852 | pr_debug("F1 signature read @0x18000000=0x%4x\n", |
a39be27b | 3853 | brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL)); |
5b435de0 AS |
3854 | |
3855 | /* | |
cb7cf7be | 3856 | * Force PLL off until brcmf_chip_attach() |
5b435de0 AS |
3857 | * programs PLL control regs |
3858 | */ | |
3859 | ||
a39be27b AS |
3860 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3861 | BRCMF_INIT_CLKCTL1, &err); | |
5b435de0 | 3862 | if (!err) |
a39be27b AS |
3863 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
3864 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 AS |
3865 | |
3866 | if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { | |
5e8149f5 | 3867 | brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", |
5b435de0 AS |
3868 | err, BRCMF_INIT_CLKCTL1, clkctl); |
3869 | goto fail; | |
3870 | } | |
3871 | ||
cb7cf7be AS |
3872 | bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops); |
3873 | if (IS_ERR(bus->ci)) { | |
3874 | brcmf_err("brcmf_chip_attach failed!\n"); | |
3875 | bus->ci = NULL; | |
5b435de0 AS |
3876 | goto fail; |
3877 | } | |
3878 | ||
82d7f3c1 | 3879 | if (brcmf_sdio_kso_init(bus)) { |
4a3da990 PH |
3880 | brcmf_err("error enabling KSO\n"); |
3881 | goto fail; | |
3882 | } | |
3883 | ||
668761ac HM |
3884 | if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength)) |
3885 | drivestrength = bus->sdiodev->pdata->drive_strength; | |
3886 | else | |
3887 | drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; | |
65d80d0b | 3888 | brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength); |
5b435de0 | 3889 | |
1e9ab4dd | 3890 | /* Set card control so an SDIO card reset does a WLAN backplane reset */ |
a39be27b AS |
3891 | reg_val = brcmf_sdiod_regrb(bus->sdiodev, |
3892 | SDIO_CCCR_BRCM_CARDCTRL, &err); | |
1e9ab4dd PH |
3893 | if (err) |
3894 | goto fail; | |
3895 | ||
3896 | reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; | |
3897 | ||
a39be27b AS |
3898 | brcmf_sdiod_regwb(bus->sdiodev, |
3899 | SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); | |
1e9ab4dd PH |
3900 | if (err) |
3901 | goto fail; | |
3902 | ||
3903 | /* set PMUControl so a backplane reset does PMU state reload */ | |
cb7cf7be | 3904 | reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base, |
1e9ab4dd | 3905 | pmucontrol); |
cb7cf7be | 3906 | reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err); |
1e9ab4dd PH |
3907 | if (err) |
3908 | goto fail; | |
3909 | ||
3910 | reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); | |
3911 | ||
cb7cf7be | 3912 | brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err); |
1e9ab4dd PH |
3913 | if (err) |
3914 | goto fail; | |
3915 | ||
38b0b0dd FL |
3916 | sdio_release_host(bus->sdiodev->func[1]); |
3917 | ||
5b435de0 AS |
3918 | brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); |
3919 | ||
9b2d2f2a AS |
3920 | /* allocate header buffer */ |
3921 | bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); | |
3922 | if (!bus->hdrbuf) | |
3923 | return false; | |
5b435de0 AS |
3924 | /* Locate an appropriately-aligned portion of hdrbuf */ |
3925 | bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], | |
9b2d2f2a | 3926 | bus->head_align); |
5b435de0 AS |
3927 | |
3928 | /* Set the poll and/or interrupt flags */ | |
3929 | bus->intr = true; | |
3930 | bus->poll = false; | |
3931 | if (bus->poll) | |
3932 | bus->pollrate = 1; | |
3933 | ||
3934 | return true; | |
3935 | ||
3936 | fail: | |
38b0b0dd | 3937 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3938 | return false; |
3939 | } | |
3940 | ||
5b435de0 | 3941 | static int |
82d7f3c1 | 3942 | brcmf_sdio_watchdog_thread(void *data) |
5b435de0 | 3943 | { |
e92eedf4 | 3944 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
99824643 | 3945 | int wait; |
5b435de0 AS |
3946 | |
3947 | allow_signal(SIGTERM); | |
3948 | /* Run until signal received */ | |
99824643 | 3949 | brcmf_sdiod_freezer_count(bus->sdiodev); |
5b435de0 AS |
3950 | while (1) { |
3951 | if (kthread_should_stop()) | |
3952 | break; | |
99824643 AS |
3953 | brcmf_sdiod_freezer_uncount(bus->sdiodev); |
3954 | wait = wait_for_completion_interruptible(&bus->watchdog_wait); | |
3955 | brcmf_sdiod_freezer_count(bus->sdiodev); | |
3956 | brcmf_sdiod_try_freeze(bus->sdiodev); | |
3957 | if (!wait) { | |
82d7f3c1 | 3958 | brcmf_sdio_bus_watchdog(bus); |
5b435de0 | 3959 | /* Count the tick for reference */ |
80969836 | 3960 | bus->sdcnt.tickcnt++; |
58e9df46 | 3961 | reinit_completion(&bus->watchdog_wait); |
5b435de0 AS |
3962 | } else |
3963 | break; | |
3964 | } | |
3965 | return 0; | |
3966 | } | |
3967 | ||
3968 | static void | |
82d7f3c1 | 3969 | brcmf_sdio_watchdog(unsigned long data) |
5b435de0 | 3970 | { |
e92eedf4 | 3971 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3972 | |
3973 | if (bus->watchdog_tsk) { | |
3974 | complete(&bus->watchdog_wait); | |
3975 | /* Reschedule the watchdog */ | |
3976 | if (bus->wd_timer_valid) | |
3977 | mod_timer(&bus->timer, | |
187d3c33 | 3978 | jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS)); |
5b435de0 AS |
3979 | } |
3980 | } | |
3981 | ||
d9cb2596 | 3982 | static struct brcmf_bus_ops brcmf_sdio_bus_ops = { |
82d7f3c1 AS |
3983 | .stop = brcmf_sdio_bus_stop, |
3984 | .preinit = brcmf_sdio_bus_preinit, | |
82d7f3c1 AS |
3985 | .txdata = brcmf_sdio_bus_txdata, |
3986 | .txctl = brcmf_sdio_bus_txctl, | |
3987 | .rxctl = brcmf_sdio_bus_rxctl, | |
3988 | .gettxq = brcmf_sdio_bus_gettxq, | |
330b4e4b | 3989 | .wowl_config = brcmf_sdio_wowl_config |
d9cb2596 AS |
3990 | }; |
3991 | ||
bd0e1b1d AS |
3992 | static void brcmf_sdio_firmware_callback(struct device *dev, |
3993 | const struct firmware *code, | |
3994 | void *nvram, u32 nvram_len) | |
3995 | { | |
3996 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3997 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3998 | struct brcmf_sdio *bus = sdiodev->bus; | |
3999 | int err = 0; | |
4000 | u8 saveclk; | |
4001 | ||
4002 | brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev)); | |
4003 | ||
bd0e1b1d AS |
4004 | if (!bus_if->drvr) |
4005 | return; | |
4006 | ||
a1cee865 HM |
4007 | /* try to download image and nvram to the dongle */ |
4008 | bus->alp_only = true; | |
4009 | err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); | |
4010 | if (err) | |
4011 | goto fail; | |
4012 | bus->alp_only = false; | |
4013 | ||
bd0e1b1d AS |
4014 | /* Start the watchdog timer */ |
4015 | bus->sdcnt.tickcnt = 0; | |
4016 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); | |
4017 | ||
4018 | sdio_claim_host(sdiodev->func[1]); | |
4019 | ||
4020 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
4021 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
4022 | if (bus->clkstate != CLK_AVAIL) | |
4023 | goto release; | |
4024 | ||
4025 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
4026 | saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
4027 | if (!err) { | |
4028 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
4029 | (saveclk | SBSDIO_FORCE_HT), &err); | |
4030 | } | |
4031 | if (err) { | |
4032 | brcmf_err("Failed to force clock for F2: err %d\n", err); | |
4033 | goto release; | |
4034 | } | |
4035 | ||
4036 | /* Enable function 2 (frame transfers) */ | |
4037 | w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, | |
4038 | offsetof(struct sdpcmd_regs, tosbmailboxdata)); | |
4039 | err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]); | |
4040 | ||
4041 | ||
4042 | brcmf_dbg(INFO, "enable F2: err=%d\n", err); | |
4043 | ||
4044 | /* If F2 successfully enabled, set core and enable interrupts */ | |
4045 | if (!err) { | |
4046 | /* Set up the interrupt mask and enable interrupts */ | |
4047 | bus->hostintmask = HOSTINTMASK; | |
4048 | w_sdreg32(bus, bus->hostintmask, | |
4049 | offsetof(struct sdpcmd_regs, hostintmask)); | |
4050 | ||
4051 | brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err); | |
4052 | } else { | |
4053 | /* Disable F2 again */ | |
4054 | sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); | |
4055 | goto release; | |
4056 | } | |
4057 | ||
4058 | if (brcmf_chip_sr_capable(bus->ci)) { | |
4059 | brcmf_sdio_sr_init(bus); | |
4060 | } else { | |
4061 | /* Restore previous clock setting */ | |
4062 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
4063 | saveclk, &err); | |
4064 | } | |
4065 | ||
4066 | if (err == 0) { | |
4067 | err = brcmf_sdiod_intr_register(sdiodev); | |
4068 | if (err != 0) | |
4069 | brcmf_err("intr register failed:%d\n", err); | |
4070 | } | |
4071 | ||
4072 | /* If we didn't come up, turn off backplane clock */ | |
4073 | if (err != 0) | |
4074 | brcmf_sdio_clkctl(bus, CLK_NONE, false); | |
4075 | ||
4076 | sdio_release_host(sdiodev->func[1]); | |
4077 | ||
4078 | err = brcmf_bus_start(dev); | |
4079 | if (err != 0) { | |
4080 | brcmf_err("dongle is not responding\n"); | |
4081 | goto fail; | |
4082 | } | |
4083 | return; | |
4084 | ||
4085 | release: | |
4086 | sdio_release_host(sdiodev->func[1]); | |
4087 | fail: | |
4088 | brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); | |
4089 | device_release_driver(dev); | |
4090 | } | |
4091 | ||
82d7f3c1 | 4092 | struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) |
5b435de0 AS |
4093 | { |
4094 | int ret; | |
e92eedf4 | 4095 | struct brcmf_sdio *bus; |
99824643 | 4096 | struct workqueue_struct *wq; |
5b435de0 | 4097 | |
5b435de0 AS |
4098 | brcmf_dbg(TRACE, "Enter\n"); |
4099 | ||
5b435de0 | 4100 | /* Allocate private bus interface state */ |
e92eedf4 | 4101 | bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); |
5b435de0 AS |
4102 | if (!bus) |
4103 | goto fail; | |
4104 | ||
4105 | bus->sdiodev = sdiodev; | |
4106 | sdiodev->bus = bus; | |
b83db862 | 4107 | skb_queue_head_init(&bus->glom); |
5b435de0 AS |
4108 | bus->txbound = BRCMF_TXBOUND; |
4109 | bus->rxbound = BRCMF_RXBOUND; | |
4110 | bus->txminmax = BRCMF_TXMINMAX; | |
6bc52319 | 4111 | bus->tx_seq = SDPCM_SEQ_WRAP - 1; |
5b435de0 | 4112 | |
e217d1c8 AS |
4113 | /* platform specific configuration: |
4114 | * alignments must be at least 4 bytes for ADMA | |
888bf76e | 4115 | */ |
e217d1c8 AS |
4116 | bus->head_align = ALIGNMENT; |
4117 | bus->sgentry_align = ALIGNMENT; | |
4118 | if (sdiodev->pdata) { | |
4119 | if (sdiodev->pdata->sd_head_align > ALIGNMENT) | |
4120 | bus->head_align = sdiodev->pdata->sd_head_align; | |
4121 | if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT) | |
4122 | bus->sgentry_align = sdiodev->pdata->sd_sgentry_align; | |
4123 | } | |
4124 | ||
99824643 AS |
4125 | /* single-threaded workqueue */ |
4126 | wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM, | |
4127 | dev_name(&sdiodev->func[1]->dev)); | |
4128 | if (!wq) { | |
5e8149f5 | 4129 | brcmf_err("insufficient memory to create txworkqueue\n"); |
37ac5780 HM |
4130 | goto fail; |
4131 | } | |
99824643 AS |
4132 | brcmf_sdiod_freezer_count(sdiodev); |
4133 | INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); | |
4134 | bus->brcmf_wq = wq; | |
37ac5780 | 4135 | |
5b435de0 | 4136 | /* attempt to attach to the dongle */ |
82d7f3c1 AS |
4137 | if (!(brcmf_sdio_probe_attach(bus))) { |
4138 | brcmf_err("brcmf_sdio_probe_attach failed\n"); | |
5b435de0 AS |
4139 | goto fail; |
4140 | } | |
4141 | ||
dd43a01c | 4142 | spin_lock_init(&bus->rxctl_lock); |
fed7ec44 | 4143 | spin_lock_init(&bus->txq_lock); |
5b435de0 AS |
4144 | init_waitqueue_head(&bus->ctrl_wait); |
4145 | init_waitqueue_head(&bus->dcmd_resp_wait); | |
4146 | ||
4147 | /* Set up the watchdog timer */ | |
4148 | init_timer(&bus->timer); | |
4149 | bus->timer.data = (unsigned long)bus; | |
82d7f3c1 | 4150 | bus->timer.function = brcmf_sdio_watchdog; |
5b435de0 | 4151 | |
5b435de0 AS |
4152 | /* Initialize watchdog thread */ |
4153 | init_completion(&bus->watchdog_wait); | |
82d7f3c1 | 4154 | bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, |
99824643 AS |
4155 | bus, "brcmf_wdog/%s", |
4156 | dev_name(&sdiodev->func[1]->dev)); | |
5b435de0 | 4157 | if (IS_ERR(bus->watchdog_tsk)) { |
02f77195 | 4158 | pr_warn("brcmf_watchdog thread failed to start\n"); |
5b435de0 AS |
4159 | bus->watchdog_tsk = NULL; |
4160 | } | |
4161 | /* Initialize DPC thread */ | |
2c64e16d HM |
4162 | bus->dpc_triggered = false; |
4163 | bus->dpc_running = false; | |
5b435de0 | 4164 | |
a9ffda88 | 4165 | /* Assign bus interface call back */ |
d9cb2596 AS |
4166 | bus->sdiodev->bus_if->dev = bus->sdiodev->dev; |
4167 | bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops; | |
75d907d3 AS |
4168 | bus->sdiodev->bus_if->chip = bus->ci->chip; |
4169 | bus->sdiodev->bus_if->chiprev = bus->ci->chiprev; | |
d9cb2596 | 4170 | |
706478cb FL |
4171 | /* default sdio bus header length for tx packet */ |
4172 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
4173 | ||
4174 | /* Attach to the common layer, reserve hdr space */ | |
8dee77ba | 4175 | ret = brcmf_attach(bus->sdiodev->dev); |
712ac5b3 | 4176 | if (ret != 0) { |
5e8149f5 | 4177 | brcmf_err("brcmf_attach failed\n"); |
5b435de0 AS |
4178 | goto fail; |
4179 | } | |
4180 | ||
7dd3abc1 DK |
4181 | /* Query the F2 block size, set roundup accordingly */ |
4182 | bus->blocksize = bus->sdiodev->func[2]->cur_blksize; | |
4183 | bus->roundup = min(max_roundup, bus->blocksize); | |
4184 | ||
5b435de0 | 4185 | /* Allocate buffers */ |
fad13228 | 4186 | if (bus->sdiodev->bus_if->maxctl) { |
7dd3abc1 | 4187 | bus->sdiodev->bus_if->maxctl += bus->roundup; |
fad13228 AS |
4188 | bus->rxblen = |
4189 | roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), | |
4190 | ALIGNMENT) + bus->head_align; | |
4191 | bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); | |
4192 | if (!(bus->rxbuf)) { | |
4193 | brcmf_err("rxbuf allocation failed\n"); | |
4194 | goto fail; | |
4195 | } | |
5b435de0 AS |
4196 | } |
4197 | ||
fad13228 AS |
4198 | sdio_claim_host(bus->sdiodev->func[1]); |
4199 | ||
4200 | /* Disable F2 to clear any intermediate frame state on the dongle */ | |
4201 | sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]); | |
4202 | ||
fad13228 AS |
4203 | bus->rxflow = false; |
4204 | ||
4205 | /* Done with backplane-dependent accesses, can drop clock... */ | |
4206 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
4207 | ||
4208 | sdio_release_host(bus->sdiodev->func[1]); | |
4209 | ||
4210 | /* ...and initialize clock/power states */ | |
4211 | bus->clkstate = CLK_SDONLY; | |
4212 | bus->idletime = BRCMF_IDLE_INTERVAL; | |
4213 | bus->idleclock = BRCMF_IDLE_ACTIVE; | |
4214 | ||
fad13228 | 4215 | /* SR state */ |
fad13228 | 4216 | bus->sr_enabled = false; |
5b435de0 | 4217 | |
80969836 | 4218 | brcmf_sdio_debugfs_create(bus); |
5b435de0 AS |
4219 | brcmf_dbg(INFO, "completed!!\n"); |
4220 | ||
c1b20532 DK |
4221 | ret = brcmf_sdio_get_fwnames(bus->ci, sdiodev); |
4222 | if (ret) | |
4223 | goto fail; | |
4224 | ||
bd0e1b1d | 4225 | ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM, |
c1b20532 | 4226 | sdiodev->fw_name, sdiodev->nvram_name, |
bd0e1b1d | 4227 | brcmf_sdio_firmware_callback); |
5b435de0 | 4228 | if (ret != 0) { |
bd0e1b1d | 4229 | brcmf_err("async firmware request failed: %d\n", ret); |
1799ddf1 | 4230 | goto fail; |
5b435de0 | 4231 | } |
15d45b6f | 4232 | |
5b435de0 AS |
4233 | return bus; |
4234 | ||
4235 | fail: | |
9fbe2a6d | 4236 | brcmf_sdio_remove(bus); |
5b435de0 AS |
4237 | return NULL; |
4238 | } | |
4239 | ||
9fbe2a6d AS |
4240 | /* Detach and free everything */ |
4241 | void brcmf_sdio_remove(struct brcmf_sdio *bus) | |
5b435de0 | 4242 | { |
5b435de0 AS |
4243 | brcmf_dbg(TRACE, "Enter\n"); |
4244 | ||
9fbe2a6d AS |
4245 | if (bus) { |
4246 | /* De-register interrupt handler */ | |
4247 | brcmf_sdiod_intr_unregister(bus->sdiodev); | |
4248 | ||
4faf28b7 | 4249 | brcmf_detach(bus->sdiodev->dev); |
bfad4a04 | 4250 | |
e0c180ec HM |
4251 | cancel_work_sync(&bus->datawork); |
4252 | if (bus->brcmf_wq) | |
4253 | destroy_workqueue(bus->brcmf_wq); | |
4254 | ||
bfad4a04 | 4255 | if (bus->ci) { |
a1ce7a0d | 4256 | if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { |
bb350711 | 4257 | sdio_claim_host(bus->sdiodev->func[1]); |
cf45932a | 4258 | brcmf_sdio_wd_timer(bus, 0); |
bb350711 AS |
4259 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); |
4260 | /* Leave the device in state where it is | |
d380ebc9 AS |
4261 | * 'passive'. This is done by resetting all |
4262 | * necessary cores. | |
bb350711 AS |
4263 | */ |
4264 | msleep(20); | |
d380ebc9 | 4265 | brcmf_chip_set_passive(bus->ci); |
bb350711 AS |
4266 | brcmf_sdio_clkctl(bus, CLK_NONE, false); |
4267 | sdio_release_host(bus->sdiodev->func[1]); | |
4268 | } | |
cb7cf7be | 4269 | brcmf_chip_detach(bus->ci); |
9fbe2a6d AS |
4270 | } |
4271 | ||
bfad4a04 | 4272 | kfree(bus->rxbuf); |
9fbe2a6d AS |
4273 | kfree(bus->hdrbuf); |
4274 | kfree(bus); | |
4275 | } | |
5b435de0 AS |
4276 | |
4277 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4278 | } | |
4279 | ||
82d7f3c1 | 4280 | void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick) |
5b435de0 | 4281 | { |
5b435de0 | 4282 | /* Totally stop the timer */ |
23677ce3 | 4283 | if (!wdtick && bus->wd_timer_valid) { |
5b435de0 AS |
4284 | del_timer_sync(&bus->timer); |
4285 | bus->wd_timer_valid = false; | |
4286 | bus->save_ms = wdtick; | |
4287 | return; | |
4288 | } | |
4289 | ||
ece960ea | 4290 | /* don't start the wd until fw is loaded */ |
a1ce7a0d | 4291 | if (bus->sdiodev->state != BRCMF_SDIOD_DATA) |
ece960ea FL |
4292 | return; |
4293 | ||
5b435de0 AS |
4294 | if (wdtick) { |
4295 | if (bus->save_ms != BRCMF_WD_POLL_MS) { | |
23677ce3 | 4296 | if (bus->wd_timer_valid) |
5b435de0 AS |
4297 | /* Stop timer and restart at new value */ |
4298 | del_timer_sync(&bus->timer); | |
4299 | ||
4300 | /* Create timer again when watchdog period is | |
4301 | dynamically changed or in the first instance | |
4302 | */ | |
4303 | bus->timer.expires = | |
187d3c33 | 4304 | jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS); |
5b435de0 AS |
4305 | add_timer(&bus->timer); |
4306 | ||
4307 | } else { | |
4308 | /* Re arm the timer, at last watchdog period */ | |
4309 | mod_timer(&bus->timer, | |
187d3c33 | 4310 | jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS)); |
5b435de0 AS |
4311 | } |
4312 | ||
4313 | bus->wd_timer_valid = true; | |
4314 | bus->save_ms = wdtick; | |
4315 | } | |
4316 | } | |
99824643 AS |
4317 | |
4318 | int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) | |
4319 | { | |
4320 | int ret; | |
4321 | ||
4322 | sdio_claim_host(bus->sdiodev->func[1]); | |
4323 | ret = brcmf_sdio_bus_sleep(bus, sleep, false); | |
4324 | sdio_release_host(bus->sdiodev->func[1]); | |
4325 | ||
4326 | return ret; | |
4327 | } | |
4328 |