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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/printk.h> | |
21 | #include <linux/pci_ids.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/mmc/sdio.h> | |
cb7cf7be | 26 | #include <linux/mmc/sdio_ids.h> |
5b435de0 AS |
27 | #include <linux/mmc/sdio_func.h> |
28 | #include <linux/mmc/card.h> | |
29 | #include <linux/semaphore.h> | |
30 | #include <linux/firmware.h> | |
b7a57e76 | 31 | #include <linux/module.h> |
99ba15cd | 32 | #include <linux/bcma/bcma.h> |
4fc0d016 | 33 | #include <linux/debugfs.h> |
8dc01811 | 34 | #include <linux/vmalloc.h> |
668761ac | 35 | #include <linux/platform_data/brcmfmac-sdio.h> |
8da9d2c8 | 36 | #include <linux/moduleparam.h> |
5b435de0 AS |
37 | #include <asm/unaligned.h> |
38 | #include <defs.h> | |
39 | #include <brcmu_wifi.h> | |
40 | #include <brcmu_utils.h> | |
41 | #include <brcm_hw_ids.h> | |
42 | #include <soc.h> | |
888bf76e | 43 | #include "sdio.h" |
20c9c9bc | 44 | #include "chip.h" |
dabedab9 | 45 | #include "firmware.h" |
5b435de0 | 46 | |
4dd8b26a HM |
47 | #define DCMD_RESP_TIMEOUT 2000 /* In milli second */ |
48 | #define CTL_DONE_TIMEOUT 2000 /* In milli second */ | |
5b435de0 | 49 | |
8ae74654 | 50 | #ifdef DEBUG |
5b435de0 AS |
51 | |
52 | #define BRCMF_TRAP_INFO_SIZE 80 | |
53 | ||
54 | #define CBUF_LEN (128) | |
55 | ||
4fc0d016 AS |
56 | /* Device console log buffer state */ |
57 | #define CONSOLE_BUFFER_MAX 2024 | |
58 | ||
5b435de0 AS |
59 | struct rte_log_le { |
60 | __le32 buf; /* Can't be pointer on (64-bit) hosts */ | |
61 | __le32 buf_size; | |
62 | __le32 idx; | |
63 | char *_buf_compat; /* Redundant pointer for backward compat. */ | |
64 | }; | |
65 | ||
66 | struct rte_console { | |
67 | /* Virtual UART | |
68 | * When there is no UART (e.g. Quickturn), | |
69 | * the host should write a complete | |
70 | * input line directly into cbuf and then write | |
71 | * the length into vcons_in. | |
72 | * This may also be used when there is a real UART | |
73 | * (at risk of conflicting with | |
74 | * the real UART). vcons_out is currently unused. | |
75 | */ | |
76 | uint vcons_in; | |
77 | uint vcons_out; | |
78 | ||
79 | /* Output (logging) buffer | |
80 | * Console output is written to a ring buffer log_buf at index log_idx. | |
81 | * The host may read the output when it sees log_idx advance. | |
82 | * Output will be lost if the output wraps around faster than the host | |
83 | * polls. | |
84 | */ | |
85 | struct rte_log_le log_le; | |
86 | ||
87 | /* Console input line buffer | |
88 | * Characters are read one at a time into cbuf | |
89 | * until <CR> is received, then | |
90 | * the buffer is processed as a command line. | |
91 | * Also used for virtual UART. | |
92 | */ | |
93 | uint cbuf_idx; | |
94 | char cbuf[CBUF_LEN]; | |
95 | }; | |
96 | ||
8ae74654 | 97 | #endif /* DEBUG */ |
5b435de0 AS |
98 | #include <chipcommon.h> |
99 | ||
d14f78b9 | 100 | #include "bus.h" |
a8e8ed34 | 101 | #include "debug.h" |
40c1c249 | 102 | #include "tracepoint.h" |
5b435de0 AS |
103 | |
104 | #define TXQLEN 2048 /* bulk tx queue length */ | |
105 | #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ | |
106 | #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ | |
107 | #define PRIOMASK 7 | |
108 | ||
109 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
110 | ||
111 | #define BRCMF_RXBOUND 50 /* Default for max rx frames in | |
112 | one scheduling */ | |
113 | ||
114 | #define BRCMF_TXBOUND 20 /* Default for max tx frames in | |
115 | one scheduling */ | |
116 | ||
117 | #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ | |
118 | ||
119 | #define MEMBLOCK 2048 /* Block size used for downloading | |
120 | of dongle image */ | |
121 | #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold | |
122 | biggest possible glom */ | |
123 | ||
124 | #define BRCMF_FIRSTREAD (1 << 6) | |
125 | ||
126 | ||
127 | /* SBSDIO_DEVICE_CTL */ | |
128 | ||
129 | /* 1: device will assert busy signal when receiving CMD53 */ | |
130 | #define SBSDIO_DEVCTL_SETBUSY 0x01 | |
131 | /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ | |
132 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 | |
133 | /* 1: mask all interrupts to host except the chipActive (rev 8) */ | |
134 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 | |
135 | /* 1: isolate internal sdio signals, put external pads in tri-state; requires | |
136 | * sdio bus power cycle to clear (rev 9) */ | |
137 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 | |
138 | /* Force SD->SB reset mapping (rev 11) */ | |
139 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 | |
140 | /* Determined by CoreControl bit */ | |
141 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 | |
142 | /* Force backplane reset */ | |
143 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 | |
144 | /* Force no backplane reset */ | |
145 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 | |
146 | ||
5b435de0 AS |
147 | /* direct(mapped) cis space */ |
148 | ||
149 | /* MAPPED common CIS address */ | |
150 | #define SBSDIO_CIS_BASE_COMMON 0x1000 | |
151 | /* maximum bytes in one CIS */ | |
152 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 | |
153 | /* cis offset addr is < 17 bits */ | |
154 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF | |
155 | ||
156 | /* manfid tuple length, include tuple, link bytes */ | |
157 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 | |
158 | ||
cb7cf7be AS |
159 | #define CORE_BUS_REG(base, field) \ |
160 | (base + offsetof(struct sdpcmd_regs, field)) | |
161 | ||
162 | /* SDIO function 1 register CHIPCLKCSR */ | |
163 | /* Force ALP request to backplane */ | |
164 | #define SBSDIO_FORCE_ALP 0x01 | |
165 | /* Force HT request to backplane */ | |
166 | #define SBSDIO_FORCE_HT 0x02 | |
167 | /* Force ILP request to backplane */ | |
168 | #define SBSDIO_FORCE_ILP 0x04 | |
169 | /* Make ALP ready (power up xtal) */ | |
170 | #define SBSDIO_ALP_AVAIL_REQ 0x08 | |
171 | /* Make HT ready (power up PLL) */ | |
172 | #define SBSDIO_HT_AVAIL_REQ 0x10 | |
173 | /* Squelch clock requests from HW */ | |
174 | #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 | |
175 | /* Status: ALP is ready */ | |
176 | #define SBSDIO_ALP_AVAIL 0x40 | |
177 | /* Status: HT is ready */ | |
178 | #define SBSDIO_HT_AVAIL 0x80 | |
8a385ba5 | 179 | #define SBSDIO_CSR_MASK 0x1F |
cb7cf7be AS |
180 | #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) |
181 | #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) | |
182 | #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) | |
183 | #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) | |
184 | #define SBSDIO_CLKAV(regval, alponly) \ | |
185 | (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) | |
186 | ||
5b435de0 AS |
187 | /* intstatus */ |
188 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | |
189 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | |
190 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | |
191 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | |
192 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | |
193 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | |
194 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | |
195 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | |
196 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | |
197 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | |
198 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | |
199 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | |
200 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | |
201 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | |
202 | #define I_PC (1 << 10) /* descriptor error */ | |
203 | #define I_PD (1 << 11) /* data error */ | |
204 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | |
205 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | |
206 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | |
207 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | |
208 | #define I_RI (1 << 16) /* Receive Interrupt */ | |
209 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | |
210 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | |
211 | #define I_XI (1 << 24) /* Transmit Interrupt */ | |
212 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | |
213 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | |
214 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | |
215 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | |
216 | #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ | |
217 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | |
218 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | |
219 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) | |
220 | #define I_DMA (I_RI | I_XI | I_ERRORS) | |
221 | ||
222 | /* corecontrol */ | |
223 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | |
224 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ | |
225 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | |
226 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ | |
227 | #define CC_XMTDATAAVAIL_MODE (1 << 4) | |
228 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) | |
229 | ||
230 | /* SDA_FRAMECTRL */ | |
231 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | |
232 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | |
233 | #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ | |
234 | #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ | |
235 | ||
5b435de0 AS |
236 | /* |
237 | * Software allocation of To SB Mailbox resources | |
238 | */ | |
239 | ||
240 | /* tosbmailbox bits corresponding to intstatus bits */ | |
241 | #define SMB_NAK (1 << 0) /* Frame NAK */ | |
242 | #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ | |
243 | #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ | |
244 | #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ | |
245 | ||
246 | /* tosbmailboxdata */ | |
247 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ | |
248 | ||
249 | /* | |
250 | * Software allocation of To Host Mailbox resources | |
251 | */ | |
252 | ||
253 | /* intstatus bits */ | |
254 | #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ | |
255 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ | |
256 | #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ | |
257 | #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ | |
258 | ||
259 | /* tohostmailboxdata */ | |
260 | #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ | |
261 | #define HMB_DATA_DEVREADY 2 /* talk to host after enable */ | |
262 | #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ | |
263 | #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ | |
264 | ||
265 | #define HMB_DATA_FCDATA_MASK 0xff000000 | |
266 | #define HMB_DATA_FCDATA_SHIFT 24 | |
267 | ||
268 | #define HMB_DATA_VERSION_MASK 0x00ff0000 | |
269 | #define HMB_DATA_VERSION_SHIFT 16 | |
270 | ||
271 | /* | |
272 | * Software-defined protocol header | |
273 | */ | |
274 | ||
275 | /* Current protocol version */ | |
276 | #define SDPCM_PROT_VERSION 4 | |
277 | ||
5b435de0 AS |
278 | /* |
279 | * Shared structure between dongle and the host. | |
280 | * The structure contains pointers to trap or assert information. | |
281 | */ | |
4fc0d016 | 282 | #define SDPCM_SHARED_VERSION 0x0003 |
5b435de0 AS |
283 | #define SDPCM_SHARED_VERSION_MASK 0x00FF |
284 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | |
285 | #define SDPCM_SHARED_ASSERT 0x0200 | |
286 | #define SDPCM_SHARED_TRAP 0x0400 | |
287 | ||
288 | /* Space for header read, limit for data packets */ | |
289 | #define MAX_HDR_READ (1 << 6) | |
290 | #define MAX_RX_DATASZ 2048 | |
291 | ||
5b435de0 AS |
292 | /* Bump up limit on waiting for HT to account for first startup; |
293 | * if the image is doing a CRC calculation before programming the PMU | |
294 | * for HT availability, it could take a couple hundred ms more, so | |
295 | * max out at a 1 second (1000000us). | |
296 | */ | |
297 | #undef PMU_MAX_TRANSITION_DLY | |
298 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
299 | ||
300 | /* Value for ChipClockCSR during initial setup */ | |
301 | #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ | |
302 | SBSDIO_ALP_AVAIL_REQ) | |
303 | ||
304 | /* Flags for SDH calls */ | |
305 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
306 | ||
382a9e0f FL |
307 | #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change |
308 | * when idle | |
309 | */ | |
310 | #define BRCMF_IDLE_INTERVAL 1 | |
311 | ||
4a3da990 PH |
312 | #define KSO_WAIT_US 50 |
313 | #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) | |
314 | ||
5b435de0 AS |
315 | /* |
316 | * Conversion of 802.1D priority to precedence level | |
317 | */ | |
318 | static uint prio2prec(u32 prio) | |
319 | { | |
320 | return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? | |
321 | (prio^2) : prio; | |
322 | } | |
323 | ||
8ae74654 | 324 | #ifdef DEBUG |
5b435de0 AS |
325 | /* Device console log buffer state */ |
326 | struct brcmf_console { | |
327 | uint count; /* Poll interval msec counter */ | |
328 | uint log_addr; /* Log struct address (fixed) */ | |
329 | struct rte_log_le log_le; /* Log struct (host copy) */ | |
330 | uint bufsize; /* Size of log buffer */ | |
331 | u8 *buf; /* Log buffer (host copy) */ | |
332 | uint last; /* Last buffer read index */ | |
333 | }; | |
4fc0d016 AS |
334 | |
335 | struct brcmf_trap_info { | |
336 | __le32 type; | |
337 | __le32 epc; | |
338 | __le32 cpsr; | |
339 | __le32 spsr; | |
340 | __le32 r0; /* a1 */ | |
341 | __le32 r1; /* a2 */ | |
342 | __le32 r2; /* a3 */ | |
343 | __le32 r3; /* a4 */ | |
344 | __le32 r4; /* v1 */ | |
345 | __le32 r5; /* v2 */ | |
346 | __le32 r6; /* v3 */ | |
347 | __le32 r7; /* v4 */ | |
348 | __le32 r8; /* v5 */ | |
349 | __le32 r9; /* sb/v6 */ | |
350 | __le32 r10; /* sl/v7 */ | |
351 | __le32 r11; /* fp/v8 */ | |
352 | __le32 r12; /* ip */ | |
353 | __le32 r13; /* sp */ | |
354 | __le32 r14; /* lr */ | |
355 | __le32 pc; /* r15 */ | |
356 | }; | |
8ae74654 | 357 | #endif /* DEBUG */ |
5b435de0 AS |
358 | |
359 | struct sdpcm_shared { | |
360 | u32 flags; | |
361 | u32 trap_addr; | |
362 | u32 assert_exp_addr; | |
363 | u32 assert_file_addr; | |
364 | u32 assert_line; | |
365 | u32 console_addr; /* Address of struct rte_console */ | |
366 | u32 msgtrace_addr; | |
367 | u8 tag[32]; | |
4fc0d016 | 368 | u32 brpt_addr; |
5b435de0 AS |
369 | }; |
370 | ||
371 | struct sdpcm_shared_le { | |
372 | __le32 flags; | |
373 | __le32 trap_addr; | |
374 | __le32 assert_exp_addr; | |
375 | __le32 assert_file_addr; | |
376 | __le32 assert_line; | |
377 | __le32 console_addr; /* Address of struct rte_console */ | |
378 | __le32 msgtrace_addr; | |
379 | u8 tag[32]; | |
4fc0d016 | 380 | __le32 brpt_addr; |
5b435de0 AS |
381 | }; |
382 | ||
6bc52319 FL |
383 | /* dongle SDIO bus specific header info */ |
384 | struct brcmf_sdio_hdrinfo { | |
4754fcee FL |
385 | u8 seq_num; |
386 | u8 channel; | |
387 | u16 len; | |
388 | u16 len_left; | |
389 | u16 len_nxtfrm; | |
390 | u8 dat_offset; | |
8da9d2c8 FL |
391 | bool lastfrm; |
392 | u16 tail_pad; | |
4754fcee | 393 | }; |
5b435de0 | 394 | |
82d957e0 AS |
395 | /* |
396 | * hold counter variables | |
397 | */ | |
398 | struct brcmf_sdio_count { | |
399 | uint intrcount; /* Count of device interrupt callbacks */ | |
400 | uint lastintrs; /* Count as of last watchdog timer */ | |
401 | uint pollcnt; /* Count of active polls */ | |
402 | uint regfails; /* Count of R_REG failures */ | |
403 | uint tx_sderrs; /* Count of tx attempts with sd errors */ | |
404 | uint fcqueued; /* Tx packets that got queued */ | |
405 | uint rxrtx; /* Count of rtx requests (NAK to dongle) */ | |
406 | uint rx_toolong; /* Receive frames too long to receive */ | |
407 | uint rxc_errors; /* SDIO errors when reading control frames */ | |
408 | uint rx_hdrfail; /* SDIO errors on header reads */ | |
409 | uint rx_badhdr; /* Bad received headers (roosync?) */ | |
410 | uint rx_badseq; /* Mismatched rx sequence number */ | |
411 | uint fc_rcvd; /* Number of flow-control events received */ | |
412 | uint fc_xoff; /* Number which turned on flow-control */ | |
413 | uint fc_xon; /* Number which turned off flow-control */ | |
414 | uint rxglomfail; /* Failed deglom attempts */ | |
415 | uint rxglomframes; /* Number of glom frames (superframes) */ | |
416 | uint rxglompkts; /* Number of packets from glom frames */ | |
417 | uint f2rxhdrs; /* Number of header reads */ | |
418 | uint f2rxdata; /* Number of frame data reads */ | |
419 | uint f2txdata; /* Number of f2 frame writes */ | |
420 | uint f1regdata; /* Number of f1 register accesses */ | |
421 | uint tickcnt; /* Number of watchdog been schedule */ | |
422 | ulong tx_ctlerrs; /* Err of sending ctrl frames */ | |
423 | ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ | |
424 | ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ | |
425 | ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ | |
426 | ulong rx_readahead_cnt; /* packets where header read-ahead was used */ | |
427 | }; | |
428 | ||
5b435de0 | 429 | /* misc chip info needed by some of the routines */ |
5b435de0 | 430 | /* Private data for SDIO bus interaction */ |
e92eedf4 | 431 | struct brcmf_sdio { |
5b435de0 | 432 | struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ |
9cf218fc | 433 | struct brcmf_chip *ci; /* Chip info struct */ |
5b435de0 AS |
434 | |
435 | u32 ramsize; /* Size of RAM in SOCRAM (bytes) */ | |
436 | ||
437 | u32 hostintmask; /* Copy of Host Interrupt Mask */ | |
4531603a FL |
438 | atomic_t intstatus; /* Intstatus bits (events) pending */ |
439 | atomic_t fcstate; /* State of dongle flow-control */ | |
5b435de0 AS |
440 | |
441 | uint blocksize; /* Block size of SDIO transfers */ | |
442 | uint roundup; /* Max roundup limit */ | |
443 | ||
444 | struct pktq txq; /* Queue length used for flow-control */ | |
445 | u8 flowcontrol; /* per prio flow control bitmask */ | |
446 | u8 tx_seq; /* Transmit sequence number (next) */ | |
447 | u8 tx_max; /* Maximum transmit sequence allowed */ | |
448 | ||
9b2d2f2a | 449 | u8 *hdrbuf; /* buffer for handling rx frame */ |
5b435de0 | 450 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ |
5b435de0 | 451 | u8 rx_seq; /* Receive sequence number (expected) */ |
6bc52319 | 452 | struct brcmf_sdio_hdrinfo cur_read; |
4754fcee | 453 | /* info of current read frame */ |
5b435de0 | 454 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ |
4754fcee | 455 | bool rxpending; /* Data frame pending in dongle */ |
5b435de0 AS |
456 | |
457 | uint rxbound; /* Rx frames to read before resched */ | |
458 | uint txbound; /* Tx frames to send before resched */ | |
459 | uint txminmax; | |
460 | ||
461 | struct sk_buff *glomd; /* Packet containing glomming descriptor */ | |
b83db862 | 462 | struct sk_buff_head glom; /* Packet list for glommed superframe */ |
5b435de0 AS |
463 | uint glomerr; /* Glom packet read errors */ |
464 | ||
465 | u8 *rxbuf; /* Buffer for receiving control packets */ | |
466 | uint rxblen; /* Allocated length of rxbuf */ | |
467 | u8 *rxctl; /* Aligned pointer into rxbuf */ | |
dd43a01c | 468 | u8 *rxctl_orig; /* pointer for freeing rxctl */ |
5b435de0 | 469 | uint rxlen; /* Length of valid data in buffer */ |
dd43a01c | 470 | spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ |
5b435de0 AS |
471 | |
472 | u8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
473 | ||
474 | bool intr; /* Use interrupts */ | |
475 | bool poll; /* Use polling */ | |
1d382273 | 476 | atomic_t ipend; /* Device interrupt is pending */ |
5b435de0 AS |
477 | uint spurious; /* Count of spurious interrupts */ |
478 | uint pollrate; /* Ticks between device polls */ | |
479 | uint polltick; /* Tick counter */ | |
5b435de0 | 480 | |
8ae74654 | 481 | #ifdef DEBUG |
5b435de0 AS |
482 | uint console_interval; |
483 | struct brcmf_console console; /* Console output polling support */ | |
484 | uint console_addr; /* Console address from shared struct */ | |
8ae74654 | 485 | #endif /* DEBUG */ |
5b435de0 | 486 | |
5b435de0 AS |
487 | uint clkstate; /* State of sd and backplane clock(s) */ |
488 | bool activity; /* Activity flag for clock down */ | |
489 | s32 idletime; /* Control for activity timeout */ | |
490 | s32 idlecount; /* Activity timeout counter */ | |
491 | s32 idleclock; /* How to set bus driver when idle */ | |
5b435de0 AS |
492 | bool rxflow_mode; /* Rx flow control mode */ |
493 | bool rxflow; /* Is rx flow control on */ | |
494 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
5b435de0 | 495 | |
5b435de0 | 496 | u8 *ctrl_frame_buf; |
fed7ec44 | 497 | u16 ctrl_frame_len; |
5b435de0 | 498 | bool ctrl_frame_stat; |
4dd8b26a | 499 | int ctrl_frame_err; |
5b435de0 | 500 | |
fed7ec44 | 501 | spinlock_t txq_lock; /* protect bus->txq */ |
5b435de0 AS |
502 | wait_queue_head_t ctrl_wait; |
503 | wait_queue_head_t dcmd_resp_wait; | |
504 | ||
505 | struct timer_list timer; | |
506 | struct completion watchdog_wait; | |
507 | struct task_struct *watchdog_tsk; | |
508 | bool wd_timer_valid; | |
509 | uint save_ms; | |
510 | ||
f1e68c2e FL |
511 | struct workqueue_struct *brcmf_wq; |
512 | struct work_struct datawork; | |
fccfe930 | 513 | atomic_t dpc_tskcnt; |
5b435de0 | 514 | |
c8bf3484 | 515 | bool txoff; /* Transmit flow-controlled */ |
80969836 | 516 | struct brcmf_sdio_count sdcnt; |
4a3da990 | 517 | bool sr_enabled; /* SaveRestore enabled */ |
99824643 | 518 | bool sleeping; |
706478cb FL |
519 | |
520 | u8 tx_hdrlen; /* sdio bus header length for tx packet */ | |
8da9d2c8 | 521 | bool txglom; /* host tx glomming enable flag */ |
e217d1c8 AS |
522 | u16 head_align; /* buffer pointer alignment */ |
523 | u16 sgentry_align; /* scatter-gather buffer alignment */ | |
5b435de0 AS |
524 | }; |
525 | ||
5b435de0 AS |
526 | /* clkstate */ |
527 | #define CLK_NONE 0 | |
528 | #define CLK_SDONLY 1 | |
4a3da990 | 529 | #define CLK_PENDING 2 |
5b435de0 AS |
530 | #define CLK_AVAIL 3 |
531 | ||
8ae74654 | 532 | #ifdef DEBUG |
5b435de0 | 533 | static int qcount[NUMPRIO]; |
8ae74654 | 534 | #endif /* DEBUG */ |
5b435de0 | 535 | |
668761ac | 536 | #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ |
5b435de0 AS |
537 | |
538 | #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) | |
539 | ||
540 | /* Retry count for register access failures */ | |
541 | static const uint retry_limit = 2; | |
542 | ||
543 | /* Limit on rounding up frames */ | |
544 | static const uint max_roundup = 512; | |
545 | ||
546 | #define ALIGNMENT 4 | |
547 | ||
9d7d6f95 FL |
548 | enum brcmf_sdio_frmtype { |
549 | BRCMF_SDIO_FT_NORMAL, | |
550 | BRCMF_SDIO_FT_SUPER, | |
551 | BRCMF_SDIO_FT_SUB, | |
552 | }; | |
553 | ||
65d80d0b AS |
554 | #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) |
555 | ||
556 | /* SDIO Pad drive strength to select value mappings */ | |
557 | struct sdiod_drive_str { | |
558 | u8 strength; /* Pad Drive Strength in mA */ | |
559 | u8 sel; /* Chip-specific select value */ | |
560 | }; | |
561 | ||
562 | /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ | |
563 | static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { | |
564 | {32, 0x6}, | |
565 | {26, 0x7}, | |
566 | {22, 0x4}, | |
567 | {16, 0x5}, | |
568 | {12, 0x2}, | |
569 | {8, 0x3}, | |
570 | {4, 0x0}, | |
571 | {0, 0x1} | |
572 | }; | |
573 | ||
574 | /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ | |
575 | static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { | |
576 | {6, 0x7}, | |
577 | {5, 0x6}, | |
578 | {4, 0x5}, | |
579 | {3, 0x4}, | |
580 | {2, 0x2}, | |
581 | {1, 0x1}, | |
582 | {0, 0x0} | |
583 | }; | |
584 | ||
585 | /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ | |
586 | static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { | |
587 | {3, 0x3}, | |
588 | {2, 0x2}, | |
589 | {1, 0x1}, | |
590 | {0, 0x0} }; | |
591 | ||
592 | /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ | |
593 | static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { | |
594 | {16, 0x7}, | |
595 | {12, 0x5}, | |
596 | {8, 0x3}, | |
597 | {4, 0x1} | |
598 | }; | |
599 | ||
f2c44fe7 HM |
600 | #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin" |
601 | #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt" | |
602 | #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin" | |
603 | #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt" | |
604 | #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin" | |
605 | #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt" | |
606 | #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin" | |
607 | #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt" | |
608 | #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin" | |
609 | #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt" | |
610 | #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin" | |
611 | #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt" | |
8b3a38da AS |
612 | #define BCM43340_FIRMWARE_NAME "brcm/brcmfmac43340-sdio.bin" |
613 | #define BCM43340_NVRAM_NAME "brcm/brcmfmac43340-sdio.txt" | |
f2c44fe7 HM |
614 | #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin" |
615 | #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt" | |
11e69c36 AS |
616 | #define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin" |
617 | #define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt" | |
bed89b64 FL |
618 | #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin" |
619 | #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt" | |
a797ca1e FL |
620 | #define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin" |
621 | #define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt" | |
f2c44fe7 HM |
622 | |
623 | MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME); | |
624 | MODULE_FIRMWARE(BCM43143_NVRAM_NAME); | |
625 | MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME); | |
626 | MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME); | |
627 | MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME); | |
628 | MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME); | |
629 | MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME); | |
630 | MODULE_FIRMWARE(BCM4329_NVRAM_NAME); | |
631 | MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME); | |
632 | MODULE_FIRMWARE(BCM4330_NVRAM_NAME); | |
633 | MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME); | |
634 | MODULE_FIRMWARE(BCM4334_NVRAM_NAME); | |
8b3a38da AS |
635 | MODULE_FIRMWARE(BCM43340_FIRMWARE_NAME); |
636 | MODULE_FIRMWARE(BCM43340_NVRAM_NAME); | |
f2c44fe7 HM |
637 | MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME); |
638 | MODULE_FIRMWARE(BCM4335_NVRAM_NAME); | |
11e69c36 AS |
639 | MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME); |
640 | MODULE_FIRMWARE(BCM43362_NVRAM_NAME); | |
bed89b64 FL |
641 | MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME); |
642 | MODULE_FIRMWARE(BCM4339_NVRAM_NAME); | |
a797ca1e FL |
643 | MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME); |
644 | MODULE_FIRMWARE(BCM4354_NVRAM_NAME); | |
f2c44fe7 HM |
645 | |
646 | struct brcmf_firmware_names { | |
647 | u32 chipid; | |
648 | u32 revmsk; | |
649 | const char *bin; | |
650 | const char *nv; | |
651 | }; | |
652 | ||
653 | enum brcmf_firmware_type { | |
654 | BRCMF_FIRMWARE_BIN, | |
655 | BRCMF_FIRMWARE_NVRAM | |
656 | }; | |
657 | ||
658 | #define BRCMF_FIRMWARE_NVRAM(name) \ | |
659 | name ## _FIRMWARE_NAME, name ## _NVRAM_NAME | |
660 | ||
661 | static const struct brcmf_firmware_names brcmf_fwname_data[] = { | |
5779ae6a HM |
662 | { BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) }, |
663 | { BRCM_CC_43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) }, | |
664 | { BRCM_CC_43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) }, | |
665 | { BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) }, | |
666 | { BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) }, | |
667 | { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) }, | |
8b3a38da | 668 | { BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) }, |
5779ae6a HM |
669 | { BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) }, |
670 | { BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) }, | |
671 | { BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }, | |
672 | { BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) } | |
f2c44fe7 HM |
673 | }; |
674 | ||
c1b20532 DK |
675 | static int brcmf_sdio_get_fwnames(struct brcmf_chip *ci, |
676 | struct brcmf_sdio_dev *sdiodev) | |
f2c44fe7 | 677 | { |
bd0e1b1d | 678 | int i; |
46de0683 | 679 | char end; |
f2c44fe7 HM |
680 | |
681 | for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) { | |
bd0e1b1d | 682 | if (brcmf_fwname_data[i].chipid == ci->chip && |
c1b20532 DK |
683 | brcmf_fwname_data[i].revmsk & BIT(ci->chiprev)) |
684 | break; | |
f2c44fe7 | 685 | } |
c1b20532 DK |
686 | |
687 | if (i == ARRAY_SIZE(brcmf_fwname_data)) { | |
688 | brcmf_err("Unknown chipid %d [%d]\n", ci->chip, ci->chiprev); | |
689 | return -ENODEV; | |
690 | } | |
691 | ||
692 | /* check if firmware path is provided by module parameter */ | |
693 | if (brcmf_firmware_path[0] != '\0') { | |
59dfdd92 RS |
694 | strlcpy(sdiodev->fw_name, brcmf_firmware_path, |
695 | sizeof(sdiodev->fw_name)); | |
696 | strlcpy(sdiodev->nvram_name, brcmf_firmware_path, | |
697 | sizeof(sdiodev->nvram_name)); | |
46de0683 DK |
698 | |
699 | end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1]; | |
700 | if (end != '/') { | |
59dfdd92 RS |
701 | strlcat(sdiodev->fw_name, "/", |
702 | sizeof(sdiodev->fw_name)); | |
703 | strlcat(sdiodev->nvram_name, "/", | |
704 | sizeof(sdiodev->nvram_name)); | |
46de0683 | 705 | } |
c1b20532 | 706 | } |
59dfdd92 RS |
707 | strlcat(sdiodev->fw_name, brcmf_fwname_data[i].bin, |
708 | sizeof(sdiodev->fw_name)); | |
709 | strlcat(sdiodev->nvram_name, brcmf_fwname_data[i].nv, | |
710 | sizeof(sdiodev->nvram_name)); | |
c1b20532 DK |
711 | |
712 | return 0; | |
f2c44fe7 HM |
713 | } |
714 | ||
5b435de0 AS |
715 | static void pkt_align(struct sk_buff *p, int len, int align) |
716 | { | |
717 | uint datalign; | |
718 | datalign = (unsigned long)(p->data); | |
719 | datalign = roundup(datalign, (align)) - datalign; | |
720 | if (datalign) | |
721 | skb_pull(p, datalign); | |
722 | __skb_trim(p, len); | |
723 | } | |
724 | ||
725 | /* To check if there's window offered */ | |
e92eedf4 | 726 | static bool data_ok(struct brcmf_sdio *bus) |
5b435de0 AS |
727 | { |
728 | return (u8)(bus->tx_max - bus->tx_seq) != 0 && | |
729 | ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; | |
730 | } | |
731 | ||
732 | /* | |
733 | * Reads a register in the SDIO hardware block. This block occupies a series of | |
734 | * adresses on the 32 bit backplane bus. | |
735 | */ | |
cb7cf7be | 736 | static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset) |
5b435de0 | 737 | { |
cb7cf7be | 738 | struct brcmf_core *core; |
79ae3957 | 739 | int ret; |
58692750 | 740 | |
cb7cf7be AS |
741 | core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
742 | *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret); | |
58692750 FL |
743 | |
744 | return ret; | |
5b435de0 AS |
745 | } |
746 | ||
cb7cf7be | 747 | static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) |
5b435de0 | 748 | { |
cb7cf7be | 749 | struct brcmf_core *core; |
e13ce26b | 750 | int ret; |
58692750 | 751 | |
cb7cf7be AS |
752 | core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
753 | brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret); | |
58692750 FL |
754 | |
755 | return ret; | |
5b435de0 AS |
756 | } |
757 | ||
4a3da990 | 758 | static int |
82d7f3c1 | 759 | brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) |
4a3da990 PH |
760 | { |
761 | u8 wr_val = 0, rd_val, cmp_val, bmask; | |
762 | int err = 0; | |
763 | int try_cnt = 0; | |
764 | ||
8a385ba5 | 765 | brcmf_dbg(TRACE, "Enter: on=%d\n", on); |
4a3da990 PH |
766 | |
767 | wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
768 | /* 1st KSO write goes to AOS wake up core if device is asleep */ | |
a39be27b AS |
769 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
770 | wr_val, &err); | |
4a3da990 PH |
771 | |
772 | if (on) { | |
773 | /* device WAKEUP through KSO: | |
774 | * write bit 0 & read back until | |
775 | * both bits 0 (kso bit) & 1 (dev on status) are set | |
776 | */ | |
777 | cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | | |
778 | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; | |
779 | bmask = cmp_val; | |
780 | usleep_range(2000, 3000); | |
781 | } else { | |
782 | /* Put device to sleep, turn off KSO */ | |
783 | cmp_val = 0; | |
784 | /* only check for bit0, bit1(dev on status) may not | |
785 | * get cleared right away | |
786 | */ | |
787 | bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; | |
788 | } | |
789 | ||
790 | do { | |
791 | /* reliable KSO bit set/clr: | |
792 | * the sdiod sleep write access is synced to PMU 32khz clk | |
793 | * just one write attempt may fail, | |
794 | * read it back until it matches written value | |
795 | */ | |
a39be27b AS |
796 | rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
797 | &err); | |
4a3da990 PH |
798 | if (((rd_val & bmask) == cmp_val) && !err) |
799 | break; | |
8a385ba5 | 800 | |
4a3da990 | 801 | udelay(KSO_WAIT_US); |
a39be27b AS |
802 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
803 | wr_val, &err); | |
4a3da990 PH |
804 | } while (try_cnt++ < MAX_KSO_ATTEMPTS); |
805 | ||
8a385ba5 AS |
806 | if (try_cnt > 2) |
807 | brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, | |
808 | rd_val, err); | |
809 | ||
810 | if (try_cnt > MAX_KSO_ATTEMPTS) | |
811 | brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); | |
812 | ||
4a3da990 PH |
813 | return err; |
814 | } | |
815 | ||
5b435de0 AS |
816 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) |
817 | ||
5b435de0 | 818 | /* Turn backplane clock on or off */ |
82d7f3c1 | 819 | static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) |
5b435de0 AS |
820 | { |
821 | int err; | |
822 | u8 clkctl, clkreq, devctl; | |
823 | unsigned long timeout; | |
824 | ||
c3203374 | 825 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
826 | |
827 | clkctl = 0; | |
828 | ||
4a3da990 PH |
829 | if (bus->sr_enabled) { |
830 | bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); | |
831 | return 0; | |
832 | } | |
833 | ||
5b435de0 AS |
834 | if (on) { |
835 | /* Request HT Avail */ | |
836 | clkreq = | |
837 | bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
838 | ||
a39be27b AS |
839 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
840 | clkreq, &err); | |
5b435de0 | 841 | if (err) { |
5e8149f5 | 842 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
843 | return -EBADE; |
844 | } | |
845 | ||
5b435de0 | 846 | /* Check current status */ |
a39be27b AS |
847 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
848 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 849 | if (err) { |
5e8149f5 | 850 | brcmf_err("HT Avail read error: %d\n", err); |
5b435de0 AS |
851 | return -EBADE; |
852 | } | |
853 | ||
854 | /* Go to pending and await interrupt if appropriate */ | |
855 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
856 | /* Allow only clock-available interrupt */ | |
a39be27b AS |
857 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
858 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 859 | if (err) { |
5e8149f5 | 860 | brcmf_err("Devctl error setting CA: %d\n", |
5b435de0 AS |
861 | err); |
862 | return -EBADE; | |
863 | } | |
864 | ||
865 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
a39be27b AS |
866 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
867 | devctl, &err); | |
c3203374 | 868 | brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); |
5b435de0 AS |
869 | bus->clkstate = CLK_PENDING; |
870 | ||
871 | return 0; | |
872 | } else if (bus->clkstate == CLK_PENDING) { | |
873 | /* Cancel CA-only interrupt filter */ | |
a39be27b AS |
874 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
875 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 876 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
877 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
878 | devctl, &err); | |
5b435de0 AS |
879 | } |
880 | ||
881 | /* Otherwise, wait here (polling) for HT Avail */ | |
882 | timeout = jiffies + | |
883 | msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); | |
884 | while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
a39be27b AS |
885 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
886 | SBSDIO_FUNC1_CHIPCLKCSR, | |
887 | &err); | |
5b435de0 AS |
888 | if (time_after(jiffies, timeout)) |
889 | break; | |
890 | else | |
891 | usleep_range(5000, 10000); | |
892 | } | |
893 | if (err) { | |
5e8149f5 | 894 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
895 | return -EBADE; |
896 | } | |
897 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
5e8149f5 | 898 | brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", |
5b435de0 AS |
899 | PMU_MAX_TRANSITION_DLY, clkctl); |
900 | return -EBADE; | |
901 | } | |
902 | ||
903 | /* Mark clock available */ | |
904 | bus->clkstate = CLK_AVAIL; | |
c3203374 | 905 | brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); |
5b435de0 | 906 | |
8ae74654 | 907 | #if defined(DEBUG) |
23677ce3 | 908 | if (!bus->alp_only) { |
5b435de0 | 909 | if (SBSDIO_ALPONLY(clkctl)) |
5e8149f5 | 910 | brcmf_err("HT Clock should be on\n"); |
5b435de0 | 911 | } |
8ae74654 | 912 | #endif /* defined (DEBUG) */ |
5b435de0 | 913 | |
5b435de0 AS |
914 | } else { |
915 | clkreq = 0; | |
916 | ||
917 | if (bus->clkstate == CLK_PENDING) { | |
918 | /* Cancel CA-only interrupt filter */ | |
a39be27b AS |
919 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
920 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 921 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
922 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
923 | devctl, &err); | |
5b435de0 AS |
924 | } |
925 | ||
926 | bus->clkstate = CLK_SDONLY; | |
a39be27b AS |
927 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
928 | clkreq, &err); | |
c3203374 | 929 | brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); |
5b435de0 | 930 | if (err) { |
5e8149f5 | 931 | brcmf_err("Failed access turning clock off: %d\n", |
5b435de0 AS |
932 | err); |
933 | return -EBADE; | |
934 | } | |
935 | } | |
936 | return 0; | |
937 | } | |
938 | ||
939 | /* Change idle/active SD state */ | |
82d7f3c1 | 940 | static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) |
5b435de0 | 941 | { |
c3203374 | 942 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
943 | |
944 | if (on) | |
945 | bus->clkstate = CLK_SDONLY; | |
946 | else | |
947 | bus->clkstate = CLK_NONE; | |
948 | ||
949 | return 0; | |
950 | } | |
951 | ||
952 | /* Transition SD and backplane clock readiness */ | |
82d7f3c1 | 953 | static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) |
5b435de0 | 954 | { |
8ae74654 | 955 | #ifdef DEBUG |
5b435de0 | 956 | uint oldstate = bus->clkstate; |
8ae74654 | 957 | #endif /* DEBUG */ |
5b435de0 | 958 | |
c3203374 | 959 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
960 | |
961 | /* Early exit if we're already there */ | |
962 | if (bus->clkstate == target) { | |
963 | if (target == CLK_AVAIL) { | |
82d7f3c1 | 964 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); |
5b435de0 AS |
965 | bus->activity = true; |
966 | } | |
967 | return 0; | |
968 | } | |
969 | ||
970 | switch (target) { | |
971 | case CLK_AVAIL: | |
972 | /* Make sure SD clock is available */ | |
973 | if (bus->clkstate == CLK_NONE) | |
82d7f3c1 | 974 | brcmf_sdio_sdclk(bus, true); |
5b435de0 | 975 | /* Now request HT Avail on the backplane */ |
82d7f3c1 AS |
976 | brcmf_sdio_htclk(bus, true, pendok); |
977 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); | |
5b435de0 AS |
978 | bus->activity = true; |
979 | break; | |
980 | ||
981 | case CLK_SDONLY: | |
982 | /* Remove HT request, or bring up SD clock */ | |
983 | if (bus->clkstate == CLK_NONE) | |
82d7f3c1 | 984 | brcmf_sdio_sdclk(bus, true); |
5b435de0 | 985 | else if (bus->clkstate == CLK_AVAIL) |
82d7f3c1 | 986 | brcmf_sdio_htclk(bus, false, false); |
5b435de0 | 987 | else |
5e8149f5 | 988 | brcmf_err("request for %d -> %d\n", |
5b435de0 | 989 | bus->clkstate, target); |
82d7f3c1 | 990 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); |
5b435de0 AS |
991 | break; |
992 | ||
993 | case CLK_NONE: | |
994 | /* Make sure to remove HT request */ | |
995 | if (bus->clkstate == CLK_AVAIL) | |
82d7f3c1 | 996 | brcmf_sdio_htclk(bus, false, false); |
5b435de0 | 997 | /* Now remove the SD clock */ |
82d7f3c1 AS |
998 | brcmf_sdio_sdclk(bus, false); |
999 | brcmf_sdio_wd_timer(bus, 0); | |
5b435de0 AS |
1000 | break; |
1001 | } | |
8ae74654 | 1002 | #ifdef DEBUG |
c3203374 | 1003 | brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); |
8ae74654 | 1004 | #endif /* DEBUG */ |
5b435de0 AS |
1005 | |
1006 | return 0; | |
1007 | } | |
1008 | ||
4a3da990 | 1009 | static int |
82d7f3c1 | 1010 | brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) |
4a3da990 PH |
1011 | { |
1012 | int err = 0; | |
8a385ba5 | 1013 | u8 clkcsr; |
82030d6d AS |
1014 | |
1015 | brcmf_dbg(SDIO, "Enter: request %s currently %s\n", | |
4a3da990 | 1016 | (sleep ? "SLEEP" : "WAKE"), |
99824643 | 1017 | (bus->sleeping ? "SLEEP" : "WAKE")); |
4a3da990 PH |
1018 | |
1019 | /* If SR is enabled control bus state with KSO */ | |
1020 | if (bus->sr_enabled) { | |
1021 | /* Done if we're already in the requested state */ | |
99824643 | 1022 | if (sleep == bus->sleeping) |
4a3da990 PH |
1023 | goto end; |
1024 | ||
1025 | /* Going to sleep */ | |
1026 | if (sleep) { | |
1027 | /* Don't sleep if something is pending */ | |
1028 | if (atomic_read(&bus->intstatus) || | |
1029 | atomic_read(&bus->ipend) > 0 || | |
a7b134a7 | 1030 | bus->ctrl_frame_stat || |
4a3da990 PH |
1031 | (!atomic_read(&bus->fcstate) && |
1032 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
8a385ba5 AS |
1033 | data_ok(bus))) { |
1034 | err = -EBUSY; | |
1035 | goto done; | |
1036 | } | |
1037 | ||
1038 | clkcsr = brcmf_sdiod_regrb(bus->sdiodev, | |
1039 | SBSDIO_FUNC1_CHIPCLKCSR, | |
1040 | &err); | |
1041 | if ((clkcsr & SBSDIO_CSR_MASK) == 0) { | |
1042 | brcmf_dbg(SDIO, "no clock, set ALP\n"); | |
1043 | brcmf_sdiod_regwb(bus->sdiodev, | |
1044 | SBSDIO_FUNC1_CHIPCLKCSR, | |
1045 | SBSDIO_ALP_AVAIL_REQ, &err); | |
1046 | } | |
82d7f3c1 | 1047 | err = brcmf_sdio_kso_control(bus, false); |
4a3da990 PH |
1048 | /* disable watchdog */ |
1049 | if (!err) | |
82d7f3c1 | 1050 | brcmf_sdio_wd_timer(bus, 0); |
4a3da990 PH |
1051 | } else { |
1052 | bus->idlecount = 0; | |
82d7f3c1 | 1053 | err = brcmf_sdio_kso_control(bus, true); |
4a3da990 | 1054 | } |
8982cd40 | 1055 | if (err) { |
4a3da990 PH |
1056 | brcmf_err("error while changing bus sleep state %d\n", |
1057 | err); | |
8a385ba5 | 1058 | goto done; |
4a3da990 PH |
1059 | } |
1060 | } | |
1061 | ||
1062 | end: | |
1063 | /* control clocks */ | |
1064 | if (sleep) { | |
1065 | if (!bus->sr_enabled) | |
82d7f3c1 | 1066 | brcmf_sdio_clkctl(bus, CLK_NONE, pendok); |
4a3da990 | 1067 | } else { |
82d7f3c1 | 1068 | brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); |
4a3da990 | 1069 | } |
99824643 | 1070 | bus->sleeping = sleep; |
8982cd40 AS |
1071 | brcmf_dbg(SDIO, "new state %s\n", |
1072 | (sleep ? "SLEEP" : "WAKE")); | |
8a385ba5 AS |
1073 | done: |
1074 | brcmf_dbg(SDIO, "Exit: err=%d\n", err); | |
4a3da990 PH |
1075 | return err; |
1076 | ||
1077 | } | |
1078 | ||
0801e6c5 DK |
1079 | #ifdef DEBUG |
1080 | static inline bool brcmf_sdio_valid_shared_address(u32 addr) | |
1081 | { | |
1082 | return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); | |
1083 | } | |
1084 | ||
1085 | static int brcmf_sdio_readshared(struct brcmf_sdio *bus, | |
1086 | struct sdpcm_shared *sh) | |
1087 | { | |
1088 | u32 addr; | |
1089 | int rv; | |
1090 | u32 shaddr = 0; | |
1091 | struct sdpcm_shared_le sh_le; | |
1092 | __le32 addr_le; | |
1093 | ||
1094 | shaddr = bus->ci->rambase + bus->ramsize - 4; | |
1095 | ||
1096 | /* | |
1097 | * Read last word in socram to determine | |
1098 | * address of sdpcm_shared structure | |
1099 | */ | |
1100 | sdio_claim_host(bus->sdiodev->func[1]); | |
1101 | brcmf_sdio_bus_sleep(bus, false, false); | |
1102 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4); | |
1103 | sdio_release_host(bus->sdiodev->func[1]); | |
1104 | if (rv < 0) | |
1105 | return rv; | |
1106 | ||
1107 | addr = le32_to_cpu(addr_le); | |
1108 | ||
1109 | brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr); | |
1110 | ||
1111 | /* | |
1112 | * Check if addr is valid. | |
1113 | * NVRAM length at the end of memory should have been overwritten. | |
1114 | */ | |
1115 | if (!brcmf_sdio_valid_shared_address(addr)) { | |
1116 | brcmf_err("invalid sdpcm_shared address 0x%08X\n", | |
1117 | addr); | |
1118 | return -EINVAL; | |
1119 | } | |
1120 | ||
1121 | /* Read hndrte_shared structure */ | |
1122 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, | |
1123 | sizeof(struct sdpcm_shared_le)); | |
1124 | if (rv < 0) | |
1125 | return rv; | |
1126 | ||
1127 | /* Endianness */ | |
1128 | sh->flags = le32_to_cpu(sh_le.flags); | |
1129 | sh->trap_addr = le32_to_cpu(sh_le.trap_addr); | |
1130 | sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); | |
1131 | sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); | |
1132 | sh->assert_line = le32_to_cpu(sh_le.assert_line); | |
1133 | sh->console_addr = le32_to_cpu(sh_le.console_addr); | |
1134 | sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); | |
1135 | ||
1136 | if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { | |
1137 | brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", | |
1138 | SDPCM_SHARED_VERSION, | |
1139 | sh->flags & SDPCM_SHARED_VERSION_MASK); | |
1140 | return -EPROTO; | |
1141 | } | |
1142 | ||
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) | |
1147 | { | |
1148 | struct sdpcm_shared sh; | |
1149 | ||
1150 | if (brcmf_sdio_readshared(bus, &sh) == 0) | |
1151 | bus->console_addr = sh.console_addr; | |
1152 | } | |
1153 | #else | |
1154 | static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) | |
1155 | { | |
1156 | } | |
1157 | #endif /* DEBUG */ | |
1158 | ||
82d7f3c1 | 1159 | static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) |
5b435de0 AS |
1160 | { |
1161 | u32 intstatus = 0; | |
1162 | u32 hmb_data; | |
1163 | u8 fcbits; | |
58692750 | 1164 | int ret; |
5b435de0 | 1165 | |
c3203374 | 1166 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
1167 | |
1168 | /* Read mailbox data and ack that we did so */ | |
58692750 FL |
1169 | ret = r_sdreg32(bus, &hmb_data, |
1170 | offsetof(struct sdpcmd_regs, tohostmailboxdata)); | |
5b435de0 | 1171 | |
58692750 | 1172 | if (ret == 0) |
5b435de0 | 1173 | w_sdreg32(bus, SMB_INT_ACK, |
58692750 | 1174 | offsetof(struct sdpcmd_regs, tosbmailbox)); |
80969836 | 1175 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1176 | |
1177 | /* Dongle recomposed rx frames, accept them again */ | |
1178 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
c3203374 | 1179 | brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", |
5b435de0 AS |
1180 | bus->rx_seq); |
1181 | if (!bus->rxskip) | |
5e8149f5 | 1182 | brcmf_err("unexpected NAKHANDLED!\n"); |
5b435de0 AS |
1183 | |
1184 | bus->rxskip = false; | |
1185 | intstatus |= I_HMB_FRAME_IND; | |
1186 | } | |
1187 | ||
1188 | /* | |
1189 | * DEVREADY does not occur with gSPI. | |
1190 | */ | |
1191 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
1192 | bus->sdpcm_ver = | |
1193 | (hmb_data & HMB_DATA_VERSION_MASK) >> | |
1194 | HMB_DATA_VERSION_SHIFT; | |
1195 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
5e8149f5 | 1196 | brcmf_err("Version mismatch, dongle reports %d, " |
5b435de0 AS |
1197 | "expecting %d\n", |
1198 | bus->sdpcm_ver, SDPCM_PROT_VERSION); | |
1199 | else | |
c3203374 | 1200 | brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", |
5b435de0 | 1201 | bus->sdpcm_ver); |
0801e6c5 DK |
1202 | |
1203 | /* | |
1204 | * Retrieve console state address now that firmware should have | |
1205 | * updated it. | |
1206 | */ | |
1207 | brcmf_sdio_get_console_addr(bus); | |
5b435de0 AS |
1208 | } |
1209 | ||
1210 | /* | |
1211 | * Flow Control has been moved into the RX headers and this out of band | |
1212 | * method isn't used any more. | |
1213 | * remaining backward compatible with older dongles. | |
1214 | */ | |
1215 | if (hmb_data & HMB_DATA_FC) { | |
1216 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> | |
1217 | HMB_DATA_FCDATA_SHIFT; | |
1218 | ||
1219 | if (fcbits & ~bus->flowcontrol) | |
80969836 | 1220 | bus->sdcnt.fc_xoff++; |
5b435de0 AS |
1221 | |
1222 | if (bus->flowcontrol & ~fcbits) | |
80969836 | 1223 | bus->sdcnt.fc_xon++; |
5b435de0 | 1224 | |
80969836 | 1225 | bus->sdcnt.fc_rcvd++; |
5b435de0 AS |
1226 | bus->flowcontrol = fcbits; |
1227 | } | |
1228 | ||
1229 | /* Shouldn't be any others */ | |
1230 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
1231 | HMB_DATA_NAKHANDLED | | |
1232 | HMB_DATA_FC | | |
1233 | HMB_DATA_FWREADY | | |
1234 | HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) | |
5e8149f5 | 1235 | brcmf_err("Unknown mailbox data content: 0x%02x\n", |
5b435de0 AS |
1236 | hmb_data); |
1237 | ||
1238 | return intstatus; | |
1239 | } | |
1240 | ||
82d7f3c1 | 1241 | static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) |
5b435de0 AS |
1242 | { |
1243 | uint retries = 0; | |
1244 | u16 lastrbc; | |
1245 | u8 hi, lo; | |
1246 | int err; | |
1247 | ||
5e8149f5 | 1248 | brcmf_err("%sterminate frame%s\n", |
5b435de0 AS |
1249 | abort ? "abort command, " : "", |
1250 | rtx ? ", send NAK" : ""); | |
1251 | ||
1252 | if (abort) | |
a39be27b | 1253 | brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2); |
5b435de0 | 1254 | |
a39be27b AS |
1255 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
1256 | SFC_RF_TERM, &err); | |
80969836 | 1257 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
1258 | |
1259 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
1260 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
a39be27b AS |
1261 | hi = brcmf_sdiod_regrb(bus->sdiodev, |
1262 | SBSDIO_FUNC1_RFRAMEBCHI, &err); | |
1263 | lo = brcmf_sdiod_regrb(bus->sdiodev, | |
1264 | SBSDIO_FUNC1_RFRAMEBCLO, &err); | |
80969836 | 1265 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1266 | |
1267 | if ((hi == 0) && (lo == 0)) | |
1268 | break; | |
1269 | ||
1270 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
5e8149f5 | 1271 | brcmf_err("count growing: last 0x%04x now 0x%04x\n", |
5b435de0 AS |
1272 | lastrbc, (hi << 8) + lo); |
1273 | } | |
1274 | lastrbc = (hi << 8) + lo; | |
1275 | } | |
1276 | ||
1277 | if (!retries) | |
5e8149f5 | 1278 | brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); |
5b435de0 | 1279 | else |
c3203374 | 1280 | brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); |
5b435de0 AS |
1281 | |
1282 | if (rtx) { | |
80969836 | 1283 | bus->sdcnt.rxrtx++; |
58692750 FL |
1284 | err = w_sdreg32(bus, SMB_NAK, |
1285 | offsetof(struct sdpcmd_regs, tosbmailbox)); | |
5b435de0 | 1286 | |
80969836 | 1287 | bus->sdcnt.f1regdata++; |
58692750 | 1288 | if (err == 0) |
5b435de0 AS |
1289 | bus->rxskip = true; |
1290 | } | |
1291 | ||
1292 | /* Clear partial in any case */ | |
4754fcee | 1293 | bus->cur_read.len = 0; |
5b435de0 AS |
1294 | } |
1295 | ||
81c7883c HM |
1296 | static void brcmf_sdio_txfail(struct brcmf_sdio *bus) |
1297 | { | |
1298 | struct brcmf_sdio_dev *sdiodev = bus->sdiodev; | |
1299 | u8 i, hi, lo; | |
1300 | ||
1301 | /* On failure, abort the command and terminate the frame */ | |
1302 | brcmf_err("sdio error, abort command and terminate frame\n"); | |
1303 | bus->sdcnt.tx_sderrs++; | |
1304 | ||
1305 | brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2); | |
1306 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); | |
1307 | bus->sdcnt.f1regdata++; | |
1308 | ||
1309 | for (i = 0; i < 3; i++) { | |
1310 | hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); | |
1311 | lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); | |
1312 | bus->sdcnt.f1regdata += 2; | |
1313 | if ((hi == 0) && (lo == 0)) | |
1314 | break; | |
1315 | } | |
1316 | } | |
1317 | ||
9a95e60e | 1318 | /* return total length of buffer chain */ |
82d7f3c1 | 1319 | static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) |
9a95e60e AS |
1320 | { |
1321 | struct sk_buff *p; | |
1322 | uint total; | |
1323 | ||
1324 | total = 0; | |
1325 | skb_queue_walk(&bus->glom, p) | |
1326 | total += p->len; | |
1327 | return total; | |
1328 | } | |
1329 | ||
82d7f3c1 | 1330 | static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) |
046808da AS |
1331 | { |
1332 | struct sk_buff *cur, *next; | |
1333 | ||
1334 | skb_queue_walk_safe(&bus->glom, cur, next) { | |
1335 | skb_unlink(cur, &bus->glom); | |
1336 | brcmu_pkt_buf_free_skb(cur); | |
1337 | } | |
1338 | } | |
1339 | ||
6bc52319 FL |
1340 | /** |
1341 | * brcmfmac sdio bus specific header | |
1342 | * This is the lowest layer header wrapped on the packets transmitted between | |
1343 | * host and WiFi dongle which contains information needed for SDIO core and | |
1344 | * firmware | |
1345 | * | |
8da9d2c8 FL |
1346 | * It consists of 3 parts: hardware header, hardware extension header and |
1347 | * software header | |
6bc52319 FL |
1348 | * hardware header (frame tag) - 4 bytes |
1349 | * Byte 0~1: Frame length | |
1350 | * Byte 2~3: Checksum, bit-wise inverse of frame length | |
8da9d2c8 FL |
1351 | * hardware extension header - 8 bytes |
1352 | * Tx glom mode only, N/A for Rx or normal Tx | |
1353 | * Byte 0~1: Packet length excluding hw frame tag | |
1354 | * Byte 2: Reserved | |
1355 | * Byte 3: Frame flags, bit 0: last frame indication | |
1356 | * Byte 4~5: Reserved | |
1357 | * Byte 6~7: Tail padding length | |
6bc52319 FL |
1358 | * software header - 8 bytes |
1359 | * Byte 0: Rx/Tx sequence number | |
1360 | * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag | |
1361 | * Byte 2: Length of next data frame, reserved for Tx | |
1362 | * Byte 3: Data offset | |
1363 | * Byte 4: Flow control bits, reserved for Tx | |
1364 | * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet | |
1365 | * Byte 6~7: Reserved | |
1366 | */ | |
1367 | #define SDPCM_HWHDR_LEN 4 | |
8da9d2c8 | 1368 | #define SDPCM_HWEXT_LEN 8 |
6bc52319 FL |
1369 | #define SDPCM_SWHDR_LEN 8 |
1370 | #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) | |
6bc52319 FL |
1371 | /* software header */ |
1372 | #define SDPCM_SEQ_MASK 0x000000ff | |
1373 | #define SDPCM_SEQ_WRAP 256 | |
1374 | #define SDPCM_CHANNEL_MASK 0x00000f00 | |
1375 | #define SDPCM_CHANNEL_SHIFT 8 | |
1376 | #define SDPCM_CONTROL_CHANNEL 0 /* Control */ | |
1377 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ | |
1378 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ | |
1379 | #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ | |
1380 | #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ | |
1381 | #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) | |
1382 | #define SDPCM_NEXTLEN_MASK 0x00ff0000 | |
1383 | #define SDPCM_NEXTLEN_SHIFT 16 | |
1384 | #define SDPCM_DOFFSET_MASK 0xff000000 | |
1385 | #define SDPCM_DOFFSET_SHIFT 24 | |
1386 | #define SDPCM_FCMASK_MASK 0x000000ff | |
1387 | #define SDPCM_WINDOW_MASK 0x0000ff00 | |
1388 | #define SDPCM_WINDOW_SHIFT 8 | |
1389 | ||
1390 | static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) | |
1391 | { | |
1392 | u32 hdrvalue; | |
1393 | hdrvalue = *(u32 *)swheader; | |
1394 | return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); | |
1395 | } | |
1396 | ||
1397 | static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, | |
1398 | struct brcmf_sdio_hdrinfo *rd, | |
1399 | enum brcmf_sdio_frmtype type) | |
4754fcee FL |
1400 | { |
1401 | u16 len, checksum; | |
1402 | u8 rx_seq, fc, tx_seq_max; | |
6bc52319 | 1403 | u32 swheader; |
4754fcee | 1404 | |
4b776961 | 1405 | trace_brcmf_sdpcm_hdr(SDPCM_RX, header); |
76584ece | 1406 | |
6bc52319 | 1407 | /* hw header */ |
4754fcee FL |
1408 | len = get_unaligned_le16(header); |
1409 | checksum = get_unaligned_le16(header + sizeof(u16)); | |
1410 | /* All zero means no more to read */ | |
1411 | if (!(len | checksum)) { | |
1412 | bus->rxpending = false; | |
10510589 | 1413 | return -ENODATA; |
4754fcee FL |
1414 | } |
1415 | if ((u16)(~(len ^ checksum))) { | |
5e8149f5 | 1416 | brcmf_err("HW header checksum error\n"); |
4754fcee | 1417 | bus->sdcnt.rx_badhdr++; |
82d7f3c1 | 1418 | brcmf_sdio_rxfail(bus, false, false); |
10510589 | 1419 | return -EIO; |
4754fcee FL |
1420 | } |
1421 | if (len < SDPCM_HDRLEN) { | |
5e8149f5 | 1422 | brcmf_err("HW header length error\n"); |
10510589 | 1423 | return -EPROTO; |
4754fcee | 1424 | } |
9d7d6f95 FL |
1425 | if (type == BRCMF_SDIO_FT_SUPER && |
1426 | (roundup(len, bus->blocksize) != rd->len)) { | |
5e8149f5 | 1427 | brcmf_err("HW superframe header length error\n"); |
10510589 | 1428 | return -EPROTO; |
9d7d6f95 FL |
1429 | } |
1430 | if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { | |
5e8149f5 | 1431 | brcmf_err("HW subframe header length error\n"); |
10510589 | 1432 | return -EPROTO; |
9d7d6f95 | 1433 | } |
4754fcee FL |
1434 | rd->len = len; |
1435 | ||
6bc52319 FL |
1436 | /* software header */ |
1437 | header += SDPCM_HWHDR_LEN; | |
1438 | swheader = le32_to_cpu(*(__le32 *)header); | |
1439 | if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { | |
5e8149f5 | 1440 | brcmf_err("Glom descriptor found in superframe head\n"); |
9d7d6f95 | 1441 | rd->len = 0; |
10510589 | 1442 | return -EINVAL; |
9d7d6f95 | 1443 | } |
6bc52319 FL |
1444 | rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); |
1445 | rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; | |
9d7d6f95 FL |
1446 | if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && |
1447 | type != BRCMF_SDIO_FT_SUPER) { | |
5e8149f5 | 1448 | brcmf_err("HW header length too long\n"); |
4754fcee | 1449 | bus->sdcnt.rx_toolong++; |
82d7f3c1 | 1450 | brcmf_sdio_rxfail(bus, false, false); |
4754fcee | 1451 | rd->len = 0; |
10510589 | 1452 | return -EPROTO; |
4754fcee | 1453 | } |
9d7d6f95 | 1454 | if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { |
5e8149f5 | 1455 | brcmf_err("Wrong channel for superframe\n"); |
9d7d6f95 | 1456 | rd->len = 0; |
10510589 | 1457 | return -EINVAL; |
9d7d6f95 FL |
1458 | } |
1459 | if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && | |
1460 | rd->channel != SDPCM_EVENT_CHANNEL) { | |
5e8149f5 | 1461 | brcmf_err("Wrong channel for subframe\n"); |
9d7d6f95 | 1462 | rd->len = 0; |
10510589 | 1463 | return -EINVAL; |
9d7d6f95 | 1464 | } |
6bc52319 | 1465 | rd->dat_offset = brcmf_sdio_getdatoffset(header); |
4754fcee | 1466 | if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { |
5e8149f5 | 1467 | brcmf_err("seq %d: bad data offset\n", rx_seq); |
4754fcee | 1468 | bus->sdcnt.rx_badhdr++; |
82d7f3c1 | 1469 | brcmf_sdio_rxfail(bus, false, false); |
4754fcee | 1470 | rd->len = 0; |
10510589 | 1471 | return -ENXIO; |
4754fcee FL |
1472 | } |
1473 | if (rd->seq_num != rx_seq) { | |
5e8149f5 | 1474 | brcmf_err("seq %d: sequence number error, expect %d\n", |
4754fcee FL |
1475 | rx_seq, rd->seq_num); |
1476 | bus->sdcnt.rx_badseq++; | |
1477 | rd->seq_num = rx_seq; | |
1478 | } | |
9d7d6f95 FL |
1479 | /* no need to check the reset for subframe */ |
1480 | if (type == BRCMF_SDIO_FT_SUB) | |
10510589 | 1481 | return 0; |
6bc52319 | 1482 | rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; |
4754fcee FL |
1483 | if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { |
1484 | /* only warm for NON glom packet */ | |
1485 | if (rd->channel != SDPCM_GLOM_CHANNEL) | |
5e8149f5 | 1486 | brcmf_err("seq %d: next length error\n", rx_seq); |
4754fcee FL |
1487 | rd->len_nxtfrm = 0; |
1488 | } | |
6bc52319 FL |
1489 | swheader = le32_to_cpu(*(__le32 *)(header + 4)); |
1490 | fc = swheader & SDPCM_FCMASK_MASK; | |
4754fcee FL |
1491 | if (bus->flowcontrol != fc) { |
1492 | if (~bus->flowcontrol & fc) | |
1493 | bus->sdcnt.fc_xoff++; | |
1494 | if (bus->flowcontrol & ~fc) | |
1495 | bus->sdcnt.fc_xon++; | |
1496 | bus->sdcnt.fc_rcvd++; | |
1497 | bus->flowcontrol = fc; | |
1498 | } | |
6bc52319 | 1499 | tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; |
4754fcee | 1500 | if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { |
5e8149f5 | 1501 | brcmf_err("seq %d: max tx seq number error\n", rx_seq); |
4754fcee FL |
1502 | tx_seq_max = bus->tx_seq + 2; |
1503 | } | |
1504 | bus->tx_max = tx_seq_max; | |
1505 | ||
10510589 | 1506 | return 0; |
4754fcee FL |
1507 | } |
1508 | ||
6bc52319 FL |
1509 | static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) |
1510 | { | |
1511 | *(__le16 *)header = cpu_to_le16(frm_length); | |
1512 | *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); | |
1513 | } | |
1514 | ||
1515 | static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, | |
1516 | struct brcmf_sdio_hdrinfo *hd_info) | |
1517 | { | |
8da9d2c8 FL |
1518 | u32 hdrval; |
1519 | u8 hdr_offset; | |
6bc52319 FL |
1520 | |
1521 | brcmf_sdio_update_hwhdr(header, hd_info->len); | |
8da9d2c8 FL |
1522 | hdr_offset = SDPCM_HWHDR_LEN; |
1523 | ||
1524 | if (bus->txglom) { | |
1525 | hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); | |
1526 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1527 | hdrval = (u16)hd_info->tail_pad << 16; | |
1528 | *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); | |
1529 | hdr_offset += SDPCM_HWEXT_LEN; | |
1530 | } | |
6bc52319 | 1531 | |
8da9d2c8 FL |
1532 | hdrval = hd_info->seq_num; |
1533 | hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & | |
1534 | SDPCM_CHANNEL_MASK; | |
1535 | hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & | |
1536 | SDPCM_DOFFSET_MASK; | |
1537 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1538 | *(((__le32 *)(header + hdr_offset)) + 1) = 0; | |
1539 | trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); | |
6bc52319 FL |
1540 | } |
1541 | ||
82d7f3c1 | 1542 | static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) |
5b435de0 AS |
1543 | { |
1544 | u16 dlen, totlen; | |
1545 | u8 *dptr, num = 0; | |
9d7d6f95 | 1546 | u16 sublen; |
0b45bf74 | 1547 | struct sk_buff *pfirst, *pnext; |
5b435de0 AS |
1548 | |
1549 | int errcode; | |
9d7d6f95 | 1550 | u8 doff, sfdoff; |
5b435de0 | 1551 | |
6bc52319 | 1552 | struct brcmf_sdio_hdrinfo rd_new; |
5b435de0 AS |
1553 | |
1554 | /* If packets, issue read(s) and send up packet chain */ | |
1555 | /* Return sequence numbers consumed? */ | |
1556 | ||
c3203374 | 1557 | brcmf_dbg(SDIO, "start: glomd %p glom %p\n", |
b83db862 | 1558 | bus->glomd, skb_peek(&bus->glom)); |
5b435de0 AS |
1559 | |
1560 | /* If there's a descriptor, generate the packet chain */ | |
1561 | if (bus->glomd) { | |
0b45bf74 | 1562 | pfirst = pnext = NULL; |
5b435de0 AS |
1563 | dlen = (u16) (bus->glomd->len); |
1564 | dptr = bus->glomd->data; | |
1565 | if (!dlen || (dlen & 1)) { | |
5e8149f5 | 1566 | brcmf_err("bad glomd len(%d), ignore descriptor\n", |
5b435de0 AS |
1567 | dlen); |
1568 | dlen = 0; | |
1569 | } | |
1570 | ||
1571 | for (totlen = num = 0; dlen; num++) { | |
1572 | /* Get (and move past) next length */ | |
1573 | sublen = get_unaligned_le16(dptr); | |
1574 | dlen -= sizeof(u16); | |
1575 | dptr += sizeof(u16); | |
1576 | if ((sublen < SDPCM_HDRLEN) || | |
1577 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
5e8149f5 | 1578 | brcmf_err("descriptor len %d bad: %d\n", |
5b435de0 AS |
1579 | num, sublen); |
1580 | pnext = NULL; | |
1581 | break; | |
1582 | } | |
e217d1c8 | 1583 | if (sublen % bus->sgentry_align) { |
5e8149f5 | 1584 | brcmf_err("sublen %d not multiple of %d\n", |
e217d1c8 | 1585 | sublen, bus->sgentry_align); |
5b435de0 AS |
1586 | } |
1587 | totlen += sublen; | |
1588 | ||
1589 | /* For last frame, adjust read len so total | |
1590 | is a block multiple */ | |
1591 | if (!dlen) { | |
1592 | sublen += | |
1593 | (roundup(totlen, bus->blocksize) - totlen); | |
1594 | totlen = roundup(totlen, bus->blocksize); | |
1595 | } | |
1596 | ||
1597 | /* Allocate/chain packet for next subframe */ | |
e217d1c8 | 1598 | pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); |
5b435de0 | 1599 | if (pnext == NULL) { |
5e8149f5 | 1600 | brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", |
5b435de0 AS |
1601 | num, sublen); |
1602 | break; | |
1603 | } | |
b83db862 | 1604 | skb_queue_tail(&bus->glom, pnext); |
5b435de0 AS |
1605 | |
1606 | /* Adhere to start alignment requirements */ | |
e217d1c8 | 1607 | pkt_align(pnext, sublen, bus->sgentry_align); |
5b435de0 AS |
1608 | } |
1609 | ||
1610 | /* If all allocations succeeded, save packet chain | |
1611 | in bus structure */ | |
1612 | if (pnext) { | |
1613 | brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", | |
1614 | totlen, num); | |
4754fcee FL |
1615 | if (BRCMF_GLOM_ON() && bus->cur_read.len && |
1616 | totlen != bus->cur_read.len) { | |
5b435de0 | 1617 | brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", |
4754fcee | 1618 | bus->cur_read.len, totlen, rxseq); |
5b435de0 | 1619 | } |
5b435de0 AS |
1620 | pfirst = pnext = NULL; |
1621 | } else { | |
82d7f3c1 | 1622 | brcmf_sdio_free_glom(bus); |
5b435de0 AS |
1623 | num = 0; |
1624 | } | |
1625 | ||
1626 | /* Done with descriptor packet */ | |
1627 | brcmu_pkt_buf_free_skb(bus->glomd); | |
1628 | bus->glomd = NULL; | |
4754fcee | 1629 | bus->cur_read.len = 0; |
5b435de0 AS |
1630 | } |
1631 | ||
1632 | /* Ok -- either we just generated a packet chain, | |
1633 | or had one from before */ | |
b83db862 | 1634 | if (!skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1635 | if (BRCMF_GLOM_ON()) { |
1636 | brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); | |
b83db862 | 1637 | skb_queue_walk(&bus->glom, pnext) { |
5b435de0 AS |
1638 | brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", |
1639 | pnext, (u8 *) (pnext->data), | |
1640 | pnext->len, pnext->len); | |
1641 | } | |
1642 | } | |
1643 | ||
b83db862 | 1644 | pfirst = skb_peek(&bus->glom); |
82d7f3c1 | 1645 | dlen = (u16) brcmf_sdio_glom_len(bus); |
5b435de0 AS |
1646 | |
1647 | /* Do an SDIO read for the superframe. Configurable iovar to | |
1648 | * read directly into the chained packet, or allocate a large | |
1649 | * packet and and copy into the chain. | |
1650 | */ | |
38b0b0dd | 1651 | sdio_claim_host(bus->sdiodev->func[1]); |
a39be27b | 1652 | errcode = brcmf_sdiod_recv_chain(bus->sdiodev, |
a39be27b | 1653 | &bus->glom, dlen); |
38b0b0dd | 1654 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 1655 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1656 | |
1657 | /* On failure, kill the superframe, allow a couple retries */ | |
1658 | if (errcode < 0) { | |
5e8149f5 | 1659 | brcmf_err("glom read of %d bytes failed: %d\n", |
5b435de0 | 1660 | dlen, errcode); |
5b435de0 | 1661 | |
38b0b0dd | 1662 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 1663 | if (bus->glomerr++ < 3) { |
82d7f3c1 | 1664 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 AS |
1665 | } else { |
1666 | bus->glomerr = 0; | |
82d7f3c1 | 1667 | brcmf_sdio_rxfail(bus, true, false); |
80969836 | 1668 | bus->sdcnt.rxglomfail++; |
82d7f3c1 | 1669 | brcmf_sdio_free_glom(bus); |
5b435de0 | 1670 | } |
38b0b0dd | 1671 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1672 | return 0; |
1673 | } | |
1e023829 JP |
1674 | |
1675 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), | |
1676 | pfirst->data, min_t(int, pfirst->len, 48), | |
1677 | "SUPERFRAME:\n"); | |
5b435de0 | 1678 | |
9d7d6f95 FL |
1679 | rd_new.seq_num = rxseq; |
1680 | rd_new.len = dlen; | |
38b0b0dd | 1681 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1682 | errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, |
1683 | BRCMF_SDIO_FT_SUPER); | |
38b0b0dd | 1684 | sdio_release_host(bus->sdiodev->func[1]); |
9d7d6f95 | 1685 | bus->cur_read.len = rd_new.len_nxtfrm << 4; |
5b435de0 AS |
1686 | |
1687 | /* Remove superframe header, remember offset */ | |
9d7d6f95 FL |
1688 | skb_pull(pfirst, rd_new.dat_offset); |
1689 | sfdoff = rd_new.dat_offset; | |
0b45bf74 | 1690 | num = 0; |
5b435de0 AS |
1691 | |
1692 | /* Validate all the subframe headers */ | |
0b45bf74 AS |
1693 | skb_queue_walk(&bus->glom, pnext) { |
1694 | /* leave when invalid subframe is found */ | |
1695 | if (errcode) | |
1696 | break; | |
1697 | ||
9d7d6f95 FL |
1698 | rd_new.len = pnext->len; |
1699 | rd_new.seq_num = rxseq++; | |
38b0b0dd | 1700 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1701 | errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, |
1702 | BRCMF_SDIO_FT_SUB); | |
38b0b0dd | 1703 | sdio_release_host(bus->sdiodev->func[1]); |
1e023829 | 1704 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
9d7d6f95 | 1705 | pnext->data, 32, "subframe:\n"); |
5b435de0 | 1706 | |
0b45bf74 | 1707 | num++; |
5b435de0 AS |
1708 | } |
1709 | ||
1710 | if (errcode) { | |
1711 | /* Terminate frame on error, request | |
1712 | a couple retries */ | |
38b0b0dd | 1713 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1714 | if (bus->glomerr++ < 3) { |
1715 | /* Restore superframe header space */ | |
1716 | skb_push(pfirst, sfdoff); | |
82d7f3c1 | 1717 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 AS |
1718 | } else { |
1719 | bus->glomerr = 0; | |
82d7f3c1 | 1720 | brcmf_sdio_rxfail(bus, true, false); |
80969836 | 1721 | bus->sdcnt.rxglomfail++; |
82d7f3c1 | 1722 | brcmf_sdio_free_glom(bus); |
5b435de0 | 1723 | } |
38b0b0dd | 1724 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee | 1725 | bus->cur_read.len = 0; |
5b435de0 AS |
1726 | return 0; |
1727 | } | |
1728 | ||
1729 | /* Basic SD framing looks ok - process each packet (header) */ | |
5b435de0 | 1730 | |
0b45bf74 | 1731 | skb_queue_walk_safe(&bus->glom, pfirst, pnext) { |
5b435de0 AS |
1732 | dptr = (u8 *) (pfirst->data); |
1733 | sublen = get_unaligned_le16(dptr); | |
6bc52319 | 1734 | doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); |
5b435de0 | 1735 | |
1e023829 | 1736 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
9d7d6f95 FL |
1737 | dptr, pfirst->len, |
1738 | "Rx Subframe Data:\n"); | |
5b435de0 AS |
1739 | |
1740 | __skb_trim(pfirst, sublen); | |
1741 | skb_pull(pfirst, doff); | |
1742 | ||
1743 | if (pfirst->len == 0) { | |
0b45bf74 | 1744 | skb_unlink(pfirst, &bus->glom); |
5b435de0 | 1745 | brcmu_pkt_buf_free_skb(pfirst); |
5b435de0 | 1746 | continue; |
5b435de0 AS |
1747 | } |
1748 | ||
1e023829 JP |
1749 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
1750 | pfirst->data, | |
1751 | min_t(int, pfirst->len, 32), | |
1752 | "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", | |
1753 | bus->glom.qlen, pfirst, pfirst->data, | |
1754 | pfirst->len, pfirst->next, | |
1755 | pfirst->prev); | |
05f3820b AS |
1756 | skb_unlink(pfirst, &bus->glom); |
1757 | brcmf_rx_frame(bus->sdiodev->dev, pfirst); | |
1758 | bus->sdcnt.rxglompkts++; | |
5b435de0 | 1759 | } |
5b435de0 | 1760 | |
80969836 | 1761 | bus->sdcnt.rxglomframes++; |
5b435de0 AS |
1762 | } |
1763 | return num; | |
1764 | } | |
1765 | ||
82d7f3c1 AS |
1766 | static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, |
1767 | bool *pending) | |
5b435de0 AS |
1768 | { |
1769 | DECLARE_WAITQUEUE(wait, current); | |
1770 | int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT); | |
1771 | ||
1772 | /* Wait until control frame is available */ | |
1773 | add_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1774 | set_current_state(TASK_INTERRUPTIBLE); | |
1775 | ||
1776 | while (!(*condition) && (!signal_pending(current) && timeout)) | |
1777 | timeout = schedule_timeout(timeout); | |
1778 | ||
1779 | if (signal_pending(current)) | |
1780 | *pending = true; | |
1781 | ||
1782 | set_current_state(TASK_RUNNING); | |
1783 | remove_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1784 | ||
1785 | return timeout; | |
1786 | } | |
1787 | ||
82d7f3c1 | 1788 | static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) |
5b435de0 AS |
1789 | { |
1790 | if (waitqueue_active(&bus->dcmd_resp_wait)) | |
1791 | wake_up_interruptible(&bus->dcmd_resp_wait); | |
1792 | ||
1793 | return 0; | |
1794 | } | |
1795 | static void | |
82d7f3c1 | 1796 | brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) |
5b435de0 AS |
1797 | { |
1798 | uint rdlen, pad; | |
dd43a01c | 1799 | u8 *buf = NULL, *rbuf; |
5b435de0 AS |
1800 | int sdret; |
1801 | ||
1802 | brcmf_dbg(TRACE, "Enter\n"); | |
1803 | ||
dd43a01c FL |
1804 | if (bus->rxblen) |
1805 | buf = vzalloc(bus->rxblen); | |
14f8dc49 | 1806 | if (!buf) |
dd43a01c | 1807 | goto done; |
14f8dc49 | 1808 | |
dd43a01c | 1809 | rbuf = bus->rxbuf; |
9b2d2f2a | 1810 | pad = ((unsigned long)rbuf % bus->head_align); |
5b435de0 | 1811 | if (pad) |
9b2d2f2a | 1812 | rbuf += (bus->head_align - pad); |
5b435de0 AS |
1813 | |
1814 | /* Copy the already-read portion over */ | |
dd43a01c | 1815 | memcpy(buf, hdr, BRCMF_FIRSTREAD); |
5b435de0 AS |
1816 | if (len <= BRCMF_FIRSTREAD) |
1817 | goto gotpkt; | |
1818 | ||
1819 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
1820 | rdlen = len - BRCMF_FIRSTREAD; | |
1821 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
1822 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1823 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
b01a6b3c | 1824 | ((len + pad) < bus->sdiodev->bus_if->maxctl)) |
5b435de0 | 1825 | rdlen += pad; |
9b2d2f2a AS |
1826 | } else if (rdlen % bus->head_align) { |
1827 | rdlen += bus->head_align - (rdlen % bus->head_align); | |
5b435de0 AS |
1828 | } |
1829 | ||
5b435de0 | 1830 | /* Drop if the read is too big or it exceeds our maximum */ |
b01a6b3c | 1831 | if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1832 | brcmf_err("%d-byte control read exceeds %d-byte buffer\n", |
b01a6b3c | 1833 | rdlen, bus->sdiodev->bus_if->maxctl); |
82d7f3c1 | 1834 | brcmf_sdio_rxfail(bus, false, false); |
5b435de0 AS |
1835 | goto done; |
1836 | } | |
1837 | ||
b01a6b3c | 1838 | if ((len - doff) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1839 | brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", |
b01a6b3c | 1840 | len, len - doff, bus->sdiodev->bus_if->maxctl); |
80969836 | 1841 | bus->sdcnt.rx_toolong++; |
82d7f3c1 | 1842 | brcmf_sdio_rxfail(bus, false, false); |
5b435de0 AS |
1843 | goto done; |
1844 | } | |
1845 | ||
dd43a01c | 1846 | /* Read remain of frame body */ |
a7cdd821 | 1847 | sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); |
80969836 | 1848 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1849 | |
1850 | /* Control frame failures need retransmission */ | |
1851 | if (sdret < 0) { | |
5e8149f5 | 1852 | brcmf_err("read %d control bytes failed: %d\n", |
5b435de0 | 1853 | rdlen, sdret); |
80969836 | 1854 | bus->sdcnt.rxc_errors++; |
82d7f3c1 | 1855 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 | 1856 | goto done; |
dd43a01c FL |
1857 | } else |
1858 | memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); | |
5b435de0 AS |
1859 | |
1860 | gotpkt: | |
1861 | ||
1e023829 | 1862 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
dd43a01c | 1863 | buf, len, "RxCtrl:\n"); |
5b435de0 AS |
1864 | |
1865 | /* Point to valid data and indicate its length */ | |
dd43a01c FL |
1866 | spin_lock_bh(&bus->rxctl_lock); |
1867 | if (bus->rxctl) { | |
5e8149f5 | 1868 | brcmf_err("last control frame is being processed.\n"); |
dd43a01c FL |
1869 | spin_unlock_bh(&bus->rxctl_lock); |
1870 | vfree(buf); | |
1871 | goto done; | |
1872 | } | |
1873 | bus->rxctl = buf + doff; | |
1874 | bus->rxctl_orig = buf; | |
5b435de0 | 1875 | bus->rxlen = len - doff; |
dd43a01c | 1876 | spin_unlock_bh(&bus->rxctl_lock); |
5b435de0 AS |
1877 | |
1878 | done: | |
1879 | /* Awake any waiters */ | |
82d7f3c1 | 1880 | brcmf_sdio_dcmd_resp_wake(bus); |
5b435de0 AS |
1881 | } |
1882 | ||
1883 | /* Pad read to blocksize for efficiency */ | |
82d7f3c1 | 1884 | static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) |
5b435de0 AS |
1885 | { |
1886 | if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { | |
1887 | *pad = bus->blocksize - (*rdlen % bus->blocksize); | |
1888 | if (*pad <= bus->roundup && *pad < bus->blocksize && | |
1889 | *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) | |
1890 | *rdlen += *pad; | |
9b2d2f2a AS |
1891 | } else if (*rdlen % bus->head_align) { |
1892 | *rdlen += bus->head_align - (*rdlen % bus->head_align); | |
5b435de0 AS |
1893 | } |
1894 | } | |
1895 | ||
4754fcee | 1896 | static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 | 1897 | { |
5b435de0 AS |
1898 | struct sk_buff *pkt; /* Packet for event or data frames */ |
1899 | u16 pad; /* Number of pad bytes to read */ | |
5b435de0 | 1900 | uint rxleft = 0; /* Remaining number of frames allowed */ |
349e7104 | 1901 | int ret; /* Return code from calls */ |
5b435de0 | 1902 | uint rxcount = 0; /* Total frames read */ |
6bc52319 | 1903 | struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; |
4754fcee | 1904 | u8 head_read = 0; |
5b435de0 AS |
1905 | |
1906 | brcmf_dbg(TRACE, "Enter\n"); | |
1907 | ||
1908 | /* Not finished unless we encounter no more frames indication */ | |
4754fcee | 1909 | bus->rxpending = true; |
5b435de0 | 1910 | |
4754fcee | 1911 | for (rd->seq_num = bus->rx_seq, rxleft = maxframes; |
a1ce7a0d | 1912 | !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; |
4754fcee | 1913 | rd->seq_num++, rxleft--) { |
5b435de0 AS |
1914 | |
1915 | /* Handle glomming separately */ | |
b83db862 | 1916 | if (bus->glomd || !skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1917 | u8 cnt; |
1918 | brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", | |
b83db862 | 1919 | bus->glomd, skb_peek(&bus->glom)); |
82d7f3c1 | 1920 | cnt = brcmf_sdio_rxglom(bus, rd->seq_num); |
5b435de0 | 1921 | brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); |
4754fcee | 1922 | rd->seq_num += cnt - 1; |
5b435de0 AS |
1923 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; |
1924 | continue; | |
1925 | } | |
1926 | ||
4754fcee FL |
1927 | rd->len_left = rd->len; |
1928 | /* read header first for unknow frame length */ | |
38b0b0dd | 1929 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee | 1930 | if (!rd->len) { |
a39be27b | 1931 | ret = brcmf_sdiod_recv_buf(bus->sdiodev, |
a39be27b | 1932 | bus->rxhdr, BRCMF_FIRSTREAD); |
4754fcee | 1933 | bus->sdcnt.f2rxhdrs++; |
349e7104 | 1934 | if (ret < 0) { |
5e8149f5 | 1935 | brcmf_err("RXHEADER FAILED: %d\n", |
349e7104 | 1936 | ret); |
4754fcee | 1937 | bus->sdcnt.rx_hdrfail++; |
82d7f3c1 | 1938 | brcmf_sdio_rxfail(bus, true, true); |
38b0b0dd | 1939 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1940 | continue; |
5b435de0 | 1941 | } |
5b435de0 | 1942 | |
4754fcee | 1943 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), |
1e023829 JP |
1944 | bus->rxhdr, SDPCM_HDRLEN, |
1945 | "RxHdr:\n"); | |
5b435de0 | 1946 | |
6bc52319 FL |
1947 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, |
1948 | BRCMF_SDIO_FT_NORMAL)) { | |
38b0b0dd | 1949 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1950 | if (!bus->rxpending) |
1951 | break; | |
1952 | else | |
1953 | continue; | |
5b435de0 AS |
1954 | } |
1955 | ||
4754fcee | 1956 | if (rd->channel == SDPCM_CONTROL_CHANNEL) { |
82d7f3c1 AS |
1957 | brcmf_sdio_read_control(bus, bus->rxhdr, |
1958 | rd->len, | |
1959 | rd->dat_offset); | |
4754fcee FL |
1960 | /* prepare the descriptor for the next read */ |
1961 | rd->len = rd->len_nxtfrm << 4; | |
1962 | rd->len_nxtfrm = 0; | |
1963 | /* treat all packet as event if we don't know */ | |
1964 | rd->channel = SDPCM_EVENT_CHANNEL; | |
38b0b0dd | 1965 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1966 | continue; |
1967 | } | |
4754fcee FL |
1968 | rd->len_left = rd->len > BRCMF_FIRSTREAD ? |
1969 | rd->len - BRCMF_FIRSTREAD : 0; | |
1970 | head_read = BRCMF_FIRSTREAD; | |
5b435de0 AS |
1971 | } |
1972 | ||
82d7f3c1 | 1973 | brcmf_sdio_pad(bus, &pad, &rd->len_left); |
5b435de0 | 1974 | |
4754fcee | 1975 | pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + |
9b2d2f2a | 1976 | bus->head_align); |
5b435de0 AS |
1977 | if (!pkt) { |
1978 | /* Give up on data, request rtx of events */ | |
5e8149f5 | 1979 | brcmf_err("brcmu_pkt_buf_get_skb failed\n"); |
82d7f3c1 | 1980 | brcmf_sdio_rxfail(bus, false, |
4754fcee | 1981 | RETRYCHAN(rd->channel)); |
38b0b0dd | 1982 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1983 | continue; |
1984 | } | |
4754fcee | 1985 | skb_pull(pkt, head_read); |
9b2d2f2a | 1986 | pkt_align(pkt, rd->len_left, bus->head_align); |
5b435de0 | 1987 | |
a7cdd821 | 1988 | ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); |
80969836 | 1989 | bus->sdcnt.f2rxdata++; |
38b0b0dd | 1990 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1991 | |
349e7104 | 1992 | if (ret < 0) { |
5e8149f5 | 1993 | brcmf_err("read %d bytes from channel %d failed: %d\n", |
349e7104 | 1994 | rd->len, rd->channel, ret); |
5b435de0 | 1995 | brcmu_pkt_buf_free_skb(pkt); |
38b0b0dd | 1996 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 1997 | brcmf_sdio_rxfail(bus, true, |
4754fcee | 1998 | RETRYCHAN(rd->channel)); |
38b0b0dd | 1999 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2000 | continue; |
2001 | } | |
2002 | ||
4754fcee FL |
2003 | if (head_read) { |
2004 | skb_push(pkt, head_read); | |
2005 | memcpy(pkt->data, bus->rxhdr, head_read); | |
2006 | head_read = 0; | |
2007 | } else { | |
2008 | memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); | |
2009 | rd_new.seq_num = rd->seq_num; | |
38b0b0dd | 2010 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
2011 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, |
2012 | BRCMF_SDIO_FT_NORMAL)) { | |
4754fcee FL |
2013 | rd->len = 0; |
2014 | brcmu_pkt_buf_free_skb(pkt); | |
2015 | } | |
2016 | bus->sdcnt.rx_readahead_cnt++; | |
2017 | if (rd->len != roundup(rd_new.len, 16)) { | |
5e8149f5 | 2018 | brcmf_err("frame length mismatch:read %d, should be %d\n", |
4754fcee FL |
2019 | rd->len, |
2020 | roundup(rd_new.len, 16) >> 4); | |
2021 | rd->len = 0; | |
82d7f3c1 | 2022 | brcmf_sdio_rxfail(bus, true, true); |
38b0b0dd | 2023 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
2024 | brcmu_pkt_buf_free_skb(pkt); |
2025 | continue; | |
2026 | } | |
38b0b0dd | 2027 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
2028 | rd->len_nxtfrm = rd_new.len_nxtfrm; |
2029 | rd->channel = rd_new.channel; | |
2030 | rd->dat_offset = rd_new.dat_offset; | |
2031 | ||
2032 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && | |
2033 | BRCMF_DATA_ON()) && | |
2034 | BRCMF_HDRS_ON(), | |
2035 | bus->rxhdr, SDPCM_HDRLEN, | |
2036 | "RxHdr:\n"); | |
2037 | ||
2038 | if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { | |
5e8149f5 | 2039 | brcmf_err("readahead on control packet %d?\n", |
4754fcee FL |
2040 | rd_new.seq_num); |
2041 | /* Force retry w/normal header read */ | |
2042 | rd->len = 0; | |
38b0b0dd | 2043 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 2044 | brcmf_sdio_rxfail(bus, false, true); |
38b0b0dd | 2045 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
2046 | brcmu_pkt_buf_free_skb(pkt); |
2047 | continue; | |
2048 | } | |
2049 | } | |
5b435de0 | 2050 | |
1e023829 | 2051 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
4754fcee | 2052 | pkt->data, rd->len, "Rx Data:\n"); |
5b435de0 | 2053 | |
5b435de0 | 2054 | /* Save superframe descriptor and allocate packet frame */ |
4754fcee | 2055 | if (rd->channel == SDPCM_GLOM_CHANNEL) { |
6bc52319 | 2056 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { |
5b435de0 | 2057 | brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", |
4754fcee | 2058 | rd->len); |
1e023829 | 2059 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
4754fcee | 2060 | pkt->data, rd->len, |
1e023829 | 2061 | "Glom Data:\n"); |
4754fcee | 2062 | __skb_trim(pkt, rd->len); |
5b435de0 AS |
2063 | skb_pull(pkt, SDPCM_HDRLEN); |
2064 | bus->glomd = pkt; | |
2065 | } else { | |
5e8149f5 | 2066 | brcmf_err("%s: glom superframe w/o " |
5b435de0 | 2067 | "descriptor!\n", __func__); |
38b0b0dd | 2068 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 2069 | brcmf_sdio_rxfail(bus, false, false); |
38b0b0dd | 2070 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 2071 | } |
4754fcee FL |
2072 | /* prepare the descriptor for the next read */ |
2073 | rd->len = rd->len_nxtfrm << 4; | |
2074 | rd->len_nxtfrm = 0; | |
2075 | /* treat all packet as event if we don't know */ | |
2076 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
2077 | continue; |
2078 | } | |
2079 | ||
2080 | /* Fill in packet len and prio, deliver upward */ | |
4754fcee FL |
2081 | __skb_trim(pkt, rd->len); |
2082 | skb_pull(pkt, rd->dat_offset); | |
2083 | ||
2084 | /* prepare the descriptor for the next read */ | |
2085 | rd->len = rd->len_nxtfrm << 4; | |
2086 | rd->len_nxtfrm = 0; | |
2087 | /* treat all packet as event if we don't know */ | |
2088 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
2089 | |
2090 | if (pkt->len == 0) { | |
2091 | brcmu_pkt_buf_free_skb(pkt); | |
2092 | continue; | |
5b435de0 AS |
2093 | } |
2094 | ||
05f3820b | 2095 | brcmf_rx_frame(bus->sdiodev->dev, pkt); |
5b435de0 | 2096 | } |
4754fcee | 2097 | |
5b435de0 | 2098 | rxcount = maxframes - rxleft; |
5b435de0 AS |
2099 | /* Message if we hit the limit */ |
2100 | if (!rxleft) | |
4754fcee | 2101 | brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); |
5b435de0 | 2102 | else |
5b435de0 AS |
2103 | brcmf_dbg(DATA, "processed %d frames\n", rxcount); |
2104 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
2105 | if (bus->rxskip) | |
4754fcee FL |
2106 | rd->seq_num--; |
2107 | bus->rx_seq = rd->seq_num; | |
5b435de0 AS |
2108 | |
2109 | return rxcount; | |
2110 | } | |
2111 | ||
5b435de0 | 2112 | static void |
82d7f3c1 | 2113 | brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) |
5b435de0 AS |
2114 | { |
2115 | if (waitqueue_active(&bus->ctrl_wait)) | |
2116 | wake_up_interruptible(&bus->ctrl_wait); | |
2117 | return; | |
2118 | } | |
2119 | ||
8da9d2c8 FL |
2120 | static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) |
2121 | { | |
e217d1c8 | 2122 | u16 head_pad; |
8da9d2c8 FL |
2123 | u8 *dat_buf; |
2124 | ||
8da9d2c8 FL |
2125 | dat_buf = (u8 *)(pkt->data); |
2126 | ||
2127 | /* Check head padding */ | |
e217d1c8 | 2128 | head_pad = ((unsigned long)dat_buf % bus->head_align); |
8da9d2c8 FL |
2129 | if (head_pad) { |
2130 | if (skb_headroom(pkt) < head_pad) { | |
2131 | bus->sdiodev->bus_if->tx_realloc++; | |
2132 | head_pad = 0; | |
2133 | if (skb_cow(pkt, head_pad)) | |
2134 | return -ENOMEM; | |
2135 | } | |
2136 | skb_push(pkt, head_pad); | |
2137 | dat_buf = (u8 *)(pkt->data); | |
2138 | memset(dat_buf, 0, head_pad + bus->tx_hdrlen); | |
2139 | } | |
2140 | return head_pad; | |
2141 | } | |
2142 | ||
5491c11c FL |
2143 | /** |
2144 | * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for | |
2145 | * bus layer usage. | |
2146 | */ | |
b05e9254 | 2147 | /* flag marking a dummy skb added for DMA alignment requirement */ |
5491c11c | 2148 | #define ALIGN_SKB_FLAG 0x8000 |
b05e9254 | 2149 | /* bit mask of data length chopped from the previous packet */ |
5491c11c FL |
2150 | #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff |
2151 | ||
8da9d2c8 | 2152 | static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, |
a64304f0 | 2153 | struct sk_buff_head *pktq, |
8da9d2c8 | 2154 | struct sk_buff *pkt, u16 total_len) |
a64304f0 | 2155 | { |
8da9d2c8 | 2156 | struct brcmf_sdio_dev *sdiodev; |
a64304f0 | 2157 | struct sk_buff *pkt_pad; |
e217d1c8 | 2158 | u16 tail_pad, tail_chop, chain_pad; |
a64304f0 | 2159 | unsigned int blksize; |
8da9d2c8 FL |
2160 | bool lastfrm; |
2161 | int ntail, ret; | |
a64304f0 | 2162 | |
8da9d2c8 | 2163 | sdiodev = bus->sdiodev; |
a64304f0 | 2164 | blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize; |
a64304f0 | 2165 | /* sg entry alignment should be a divisor of block size */ |
e217d1c8 | 2166 | WARN_ON(blksize % bus->sgentry_align); |
a64304f0 AS |
2167 | |
2168 | /* Check tail padding */ | |
8da9d2c8 FL |
2169 | lastfrm = skb_queue_is_last(pktq, pkt); |
2170 | tail_pad = 0; | |
e217d1c8 | 2171 | tail_chop = pkt->len % bus->sgentry_align; |
8da9d2c8 | 2172 | if (tail_chop) |
e217d1c8 | 2173 | tail_pad = bus->sgentry_align - tail_chop; |
8da9d2c8 FL |
2174 | chain_pad = (total_len + tail_pad) % blksize; |
2175 | if (lastfrm && chain_pad) | |
2176 | tail_pad += blksize - chain_pad; | |
a64304f0 | 2177 | if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { |
1eb43018 AS |
2178 | pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + |
2179 | bus->head_align); | |
a64304f0 AS |
2180 | if (pkt_pad == NULL) |
2181 | return -ENOMEM; | |
8da9d2c8 | 2182 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); |
2dc3a8e0 DJ |
2183 | if (unlikely(ret < 0)) { |
2184 | kfree_skb(pkt_pad); | |
8da9d2c8 | 2185 | return ret; |
2dc3a8e0 | 2186 | } |
a64304f0 AS |
2187 | memcpy(pkt_pad->data, |
2188 | pkt->data + pkt->len - tail_chop, | |
2189 | tail_chop); | |
5aa9f0ea | 2190 | *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; |
a64304f0 | 2191 | skb_trim(pkt, pkt->len - tail_chop); |
1eb43018 | 2192 | skb_trim(pkt_pad, tail_pad + tail_chop); |
a64304f0 AS |
2193 | __skb_queue_after(pktq, pkt, pkt_pad); |
2194 | } else { | |
2195 | ntail = pkt->data_len + tail_pad - | |
2196 | (pkt->end - pkt->tail); | |
2197 | if (skb_cloned(pkt) || ntail > 0) | |
2198 | if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) | |
2199 | return -ENOMEM; | |
2200 | if (skb_linearize(pkt)) | |
2201 | return -ENOMEM; | |
a64304f0 AS |
2202 | __skb_put(pkt, tail_pad); |
2203 | } | |
2204 | ||
8da9d2c8 | 2205 | return tail_pad; |
a64304f0 AS |
2206 | } |
2207 | ||
b05e9254 FL |
2208 | /** |
2209 | * brcmf_sdio_txpkt_prep - packet preparation for transmit | |
2210 | * @bus: brcmf_sdio structure pointer | |
2211 | * @pktq: packet list pointer | |
2212 | * @chan: virtual channel to transmit the packet | |
2213 | * | |
2214 | * Processes to be applied to the packet | |
2215 | * - Align data buffer pointer | |
2216 | * - Align data buffer length | |
2217 | * - Prepare header | |
2218 | * Return: negative value if there is error | |
2219 | */ | |
2220 | static int | |
2221 | brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, | |
2222 | uint chan) | |
5b435de0 | 2223 | { |
8da9d2c8 | 2224 | u16 head_pad, total_len; |
a64304f0 | 2225 | struct sk_buff *pkt_next; |
8da9d2c8 FL |
2226 | u8 txseq; |
2227 | int ret; | |
6bc52319 | 2228 | struct brcmf_sdio_hdrinfo hd_info = {0}; |
b05e9254 | 2229 | |
8da9d2c8 FL |
2230 | txseq = bus->tx_seq; |
2231 | total_len = 0; | |
2232 | skb_queue_walk(pktq, pkt_next) { | |
2233 | /* alignment packet inserted in previous | |
2234 | * loop cycle can be skipped as it is | |
2235 | * already properly aligned and does not | |
2236 | * need an sdpcm header. | |
2237 | */ | |
5aa9f0ea | 2238 | if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) |
8da9d2c8 | 2239 | continue; |
5b435de0 | 2240 | |
8da9d2c8 FL |
2241 | /* align packet data pointer */ |
2242 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); | |
2243 | if (ret < 0) | |
2244 | return ret; | |
2245 | head_pad = (u16)ret; | |
2246 | if (head_pad) | |
1eb43018 | 2247 | memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); |
5b435de0 | 2248 | |
8da9d2c8 | 2249 | total_len += pkt_next->len; |
5b435de0 | 2250 | |
a64304f0 | 2251 | hd_info.len = pkt_next->len; |
8da9d2c8 FL |
2252 | hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); |
2253 | if (bus->txglom && pktq->qlen > 1) { | |
2254 | ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, | |
2255 | pkt_next, total_len); | |
2256 | if (ret < 0) | |
2257 | return ret; | |
2258 | hd_info.tail_pad = (u16)ret; | |
2259 | total_len += (u16)ret; | |
2260 | } | |
5b435de0 | 2261 | |
8da9d2c8 FL |
2262 | hd_info.channel = chan; |
2263 | hd_info.dat_offset = head_pad + bus->tx_hdrlen; | |
2264 | hd_info.seq_num = txseq++; | |
2265 | ||
2266 | /* Now fill the header */ | |
2267 | brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); | |
2268 | ||
2269 | if (BRCMF_BYTES_ON() && | |
2270 | ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || | |
2271 | (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) | |
47ab4cd8 | 2272 | brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, |
8da9d2c8 FL |
2273 | "Tx Frame:\n"); |
2274 | else if (BRCMF_HDRS_ON()) | |
47ab4cd8 | 2275 | brcmf_dbg_hex_dump(true, pkt_next->data, |
8da9d2c8 FL |
2276 | head_pad + bus->tx_hdrlen, |
2277 | "Tx Header:\n"); | |
2278 | } | |
2279 | /* Hardware length tag of the first packet should be total | |
2280 | * length of the chain (including padding) | |
2281 | */ | |
2282 | if (bus->txglom) | |
2283 | brcmf_sdio_update_hwhdr(pktq->next->data, total_len); | |
b05e9254 FL |
2284 | return 0; |
2285 | } | |
5b435de0 | 2286 | |
b05e9254 FL |
2287 | /** |
2288 | * brcmf_sdio_txpkt_postp - packet post processing for transmit | |
2289 | * @bus: brcmf_sdio structure pointer | |
2290 | * @pktq: packet list pointer | |
2291 | * | |
2292 | * Processes to be applied to the packet | |
2293 | * - Remove head padding | |
2294 | * - Remove tail padding | |
2295 | */ | |
2296 | static void | |
2297 | brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) | |
2298 | { | |
2299 | u8 *hdr; | |
2300 | u32 dat_offset; | |
8da9d2c8 | 2301 | u16 tail_pad; |
5aa9f0ea | 2302 | u16 dummy_flags, chop_len; |
b05e9254 FL |
2303 | struct sk_buff *pkt_next, *tmp, *pkt_prev; |
2304 | ||
2305 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
5aa9f0ea | 2306 | dummy_flags = *(u16 *)(pkt_next->cb); |
5491c11c FL |
2307 | if (dummy_flags & ALIGN_SKB_FLAG) { |
2308 | chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; | |
b05e9254 FL |
2309 | if (chop_len) { |
2310 | pkt_prev = pkt_next->prev; | |
b05e9254 FL |
2311 | skb_put(pkt_prev, chop_len); |
2312 | } | |
2313 | __skb_unlink(pkt_next, pktq); | |
2314 | brcmu_pkt_buf_free_skb(pkt_next); | |
2315 | } else { | |
8da9d2c8 | 2316 | hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; |
b05e9254 FL |
2317 | dat_offset = le32_to_cpu(*(__le32 *)hdr); |
2318 | dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> | |
2319 | SDPCM_DOFFSET_SHIFT; | |
2320 | skb_pull(pkt_next, dat_offset); | |
8da9d2c8 FL |
2321 | if (bus->txglom) { |
2322 | tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); | |
2323 | skb_trim(pkt_next, pkt_next->len - tail_pad); | |
2324 | } | |
b05e9254 | 2325 | } |
5b435de0 | 2326 | } |
b05e9254 | 2327 | } |
5b435de0 | 2328 | |
b05e9254 FL |
2329 | /* Writes a HW/SW header into the packet and sends it. */ |
2330 | /* Assumes: (a) header space already there, (b) caller holds lock */ | |
82d7f3c1 AS |
2331 | static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, |
2332 | uint chan) | |
b05e9254 FL |
2333 | { |
2334 | int ret; | |
8da9d2c8 | 2335 | struct sk_buff *pkt_next, *tmp; |
b05e9254 FL |
2336 | |
2337 | brcmf_dbg(TRACE, "Enter\n"); | |
2338 | ||
8da9d2c8 | 2339 | ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); |
b05e9254 FL |
2340 | if (ret) |
2341 | goto done; | |
5b435de0 | 2342 | |
38b0b0dd | 2343 | sdio_claim_host(bus->sdiodev->func[1]); |
a7cdd821 | 2344 | ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); |
80969836 | 2345 | bus->sdcnt.f2txdata++; |
5b435de0 | 2346 | |
81c7883c HM |
2347 | if (ret < 0) |
2348 | brcmf_sdio_txfail(bus); | |
5b435de0 | 2349 | |
38b0b0dd | 2350 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2351 | |
2352 | done: | |
8da9d2c8 FL |
2353 | brcmf_sdio_txpkt_postp(bus, pktq); |
2354 | if (ret == 0) | |
2355 | bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; | |
2356 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
2357 | __skb_unlink(pkt_next, pktq); | |
2358 | brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0); | |
2359 | } | |
5b435de0 AS |
2360 | return ret; |
2361 | } | |
2362 | ||
82d7f3c1 | 2363 | static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 AS |
2364 | { |
2365 | struct sk_buff *pkt; | |
8da9d2c8 | 2366 | struct sk_buff_head pktq; |
5b435de0 | 2367 | u32 intstatus = 0; |
8da9d2c8 | 2368 | int ret = 0, prec_out, i; |
5b435de0 | 2369 | uint cnt = 0; |
8da9d2c8 | 2370 | u8 tx_prec_map, pkt_num; |
5b435de0 | 2371 | |
5b435de0 AS |
2372 | brcmf_dbg(TRACE, "Enter\n"); |
2373 | ||
2374 | tx_prec_map = ~bus->flowcontrol; | |
2375 | ||
2376 | /* Send frames until the limit or some other event */ | |
8da9d2c8 FL |
2377 | for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { |
2378 | pkt_num = 1; | |
8da9d2c8 FL |
2379 | if (bus->txglom) |
2380 | pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, | |
af1fa210 | 2381 | bus->sdiodev->txglomsz); |
8da9d2c8 FL |
2382 | pkt_num = min_t(u32, pkt_num, |
2383 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); | |
fed7ec44 HM |
2384 | __skb_queue_head_init(&pktq); |
2385 | spin_lock_bh(&bus->txq_lock); | |
8da9d2c8 FL |
2386 | for (i = 0; i < pkt_num; i++) { |
2387 | pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, | |
2388 | &prec_out); | |
2389 | if (pkt == NULL) | |
2390 | break; | |
2391 | __skb_queue_tail(&pktq, pkt); | |
5b435de0 | 2392 | } |
fed7ec44 | 2393 | spin_unlock_bh(&bus->txq_lock); |
4dd8b26a | 2394 | if (i == 0) |
8da9d2c8 | 2395 | break; |
5b435de0 | 2396 | |
82d7f3c1 | 2397 | ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); |
fed7ec44 | 2398 | |
8da9d2c8 | 2399 | cnt += i; |
5b435de0 AS |
2400 | |
2401 | /* In poll mode, need to check for other events */ | |
b6a8cf2c | 2402 | if (!bus->intr) { |
5b435de0 | 2403 | /* Check device status, signal pending interrupt */ |
38b0b0dd | 2404 | sdio_claim_host(bus->sdiodev->func[1]); |
5c15c23a FL |
2405 | ret = r_sdreg32(bus, &intstatus, |
2406 | offsetof(struct sdpcmd_regs, | |
2407 | intstatus)); | |
38b0b0dd | 2408 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 2409 | bus->sdcnt.f2txdata++; |
5c15c23a | 2410 | if (ret != 0) |
5b435de0 AS |
2411 | break; |
2412 | if (intstatus & bus->hostintmask) | |
1d382273 | 2413 | atomic_set(&bus->ipend, 1); |
5b435de0 AS |
2414 | } |
2415 | } | |
2416 | ||
2417 | /* Deflow-control stack if needed */ | |
a1ce7a0d | 2418 | if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && |
c8bf3484 | 2419 | bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { |
90d03ff7 HM |
2420 | bus->txoff = false; |
2421 | brcmf_txflowblock(bus->sdiodev->dev, false); | |
c8bf3484 | 2422 | } |
5b435de0 AS |
2423 | |
2424 | return cnt; | |
2425 | } | |
2426 | ||
fed7ec44 HM |
2427 | static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) |
2428 | { | |
2429 | u8 doff; | |
2430 | u16 pad; | |
2431 | uint retries = 0; | |
2432 | struct brcmf_sdio_hdrinfo hd_info = {0}; | |
2433 | int ret; | |
2434 | ||
2435 | brcmf_dbg(TRACE, "Enter\n"); | |
2436 | ||
2437 | /* Back the pointer to make room for bus header */ | |
2438 | frame -= bus->tx_hdrlen; | |
2439 | len += bus->tx_hdrlen; | |
2440 | ||
2441 | /* Add alignment padding (optional for ctl frames) */ | |
2442 | doff = ((unsigned long)frame % bus->head_align); | |
2443 | if (doff) { | |
2444 | frame -= doff; | |
2445 | len += doff; | |
2446 | memset(frame + bus->tx_hdrlen, 0, doff); | |
2447 | } | |
2448 | ||
2449 | /* Round send length to next SDIO block */ | |
2450 | pad = 0; | |
2451 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2452 | pad = bus->blocksize - (len % bus->blocksize); | |
2453 | if ((pad > bus->roundup) || (pad >= bus->blocksize)) | |
2454 | pad = 0; | |
2455 | } else if (len % bus->head_align) { | |
2456 | pad = bus->head_align - (len % bus->head_align); | |
2457 | } | |
2458 | len += pad; | |
2459 | ||
2460 | hd_info.len = len - pad; | |
2461 | hd_info.channel = SDPCM_CONTROL_CHANNEL; | |
2462 | hd_info.dat_offset = doff + bus->tx_hdrlen; | |
2463 | hd_info.seq_num = bus->tx_seq; | |
2464 | hd_info.lastfrm = true; | |
2465 | hd_info.tail_pad = pad; | |
2466 | brcmf_sdio_hdpack(bus, frame, &hd_info); | |
2467 | ||
2468 | if (bus->txglom) | |
2469 | brcmf_sdio_update_hwhdr(frame, len); | |
2470 | ||
2471 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), | |
2472 | frame, len, "Tx Frame:\n"); | |
2473 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && | |
2474 | BRCMF_HDRS_ON(), | |
2475 | frame, min_t(u16, len, 16), "TxHdr:\n"); | |
2476 | ||
2477 | do { | |
2478 | ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); | |
2479 | ||
2480 | if (ret < 0) | |
2481 | brcmf_sdio_txfail(bus); | |
2482 | else | |
2483 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; | |
2484 | } while (ret < 0 && retries++ < TXRETRIES); | |
2485 | ||
2486 | return ret; | |
2487 | } | |
2488 | ||
82d7f3c1 | 2489 | static void brcmf_sdio_bus_stop(struct device *dev) |
a9ffda88 FL |
2490 | { |
2491 | u32 local_hostintmask; | |
2492 | u8 saveclk; | |
a9ffda88 FL |
2493 | int err; |
2494 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
0a332e46 | 2495 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
a9ffda88 FL |
2496 | struct brcmf_sdio *bus = sdiodev->bus; |
2497 | ||
2498 | brcmf_dbg(TRACE, "Enter\n"); | |
2499 | ||
2500 | if (bus->watchdog_tsk) { | |
2501 | send_sig(SIGTERM, bus->watchdog_tsk, 1); | |
2502 | kthread_stop(bus->watchdog_tsk); | |
2503 | bus->watchdog_tsk = NULL; | |
2504 | } | |
2505 | ||
a1ce7a0d | 2506 | if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { |
bb350711 AS |
2507 | sdio_claim_host(sdiodev->func[1]); |
2508 | ||
2509 | /* Enable clock for device interrupts */ | |
2510 | brcmf_sdio_bus_sleep(bus, false, false); | |
2511 | ||
2512 | /* Disable and clear interrupts at the chip level also */ | |
2513 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask)); | |
2514 | local_hostintmask = bus->hostintmask; | |
2515 | bus->hostintmask = 0; | |
2516 | ||
2517 | /* Force backplane clocks to assure F2 interrupt propagates */ | |
2518 | saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
2519 | &err); | |
2520 | if (!err) | |
2521 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
2522 | (saveclk | SBSDIO_FORCE_HT), &err); | |
2523 | if (err) | |
2524 | brcmf_err("Failed to force clock for F2: err %d\n", | |
2525 | err); | |
a9ffda88 | 2526 | |
bb350711 AS |
2527 | /* Turn off the bus (F2), free any pending packets */ |
2528 | brcmf_dbg(INTR, "disable SDIO interrupts\n"); | |
2529 | sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); | |
a9ffda88 | 2530 | |
bb350711 AS |
2531 | /* Clear any pending interrupts now that F2 is disabled */ |
2532 | w_sdreg32(bus, local_hostintmask, | |
2533 | offsetof(struct sdpcmd_regs, intstatus)); | |
a9ffda88 | 2534 | |
bb350711 | 2535 | sdio_release_host(sdiodev->func[1]); |
a9ffda88 | 2536 | } |
a9ffda88 FL |
2537 | /* Clear the data packet queues */ |
2538 | brcmu_pktq_flush(&bus->txq, true, NULL, NULL); | |
2539 | ||
2540 | /* Clear any held glomming stuff */ | |
297540f6 | 2541 | brcmu_pkt_buf_free_skb(bus->glomd); |
82d7f3c1 | 2542 | brcmf_sdio_free_glom(bus); |
a9ffda88 FL |
2543 | |
2544 | /* Clear rx control and wake any waiters */ | |
dd43a01c | 2545 | spin_lock_bh(&bus->rxctl_lock); |
a9ffda88 | 2546 | bus->rxlen = 0; |
dd43a01c | 2547 | spin_unlock_bh(&bus->rxctl_lock); |
82d7f3c1 | 2548 | brcmf_sdio_dcmd_resp_wake(bus); |
a9ffda88 FL |
2549 | |
2550 | /* Reset some F2 state stuff */ | |
2551 | bus->rxskip = false; | |
2552 | bus->tx_seq = bus->rx_seq = 0; | |
a9ffda88 FL |
2553 | } |
2554 | ||
82d7f3c1 | 2555 | static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) |
ba89bf19 FL |
2556 | { |
2557 | unsigned long flags; | |
2558 | ||
668761ac HM |
2559 | if (bus->sdiodev->oob_irq_requested) { |
2560 | spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags); | |
2561 | if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) { | |
2562 | enable_irq(bus->sdiodev->pdata->oob_irq_nr); | |
2563 | bus->sdiodev->irq_en = true; | |
2564 | } | |
2565 | spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags); | |
ba89bf19 | 2566 | } |
ba89bf19 | 2567 | } |
ba89bf19 | 2568 | |
5cbb9c28 HM |
2569 | static void atomic_orr(int val, atomic_t *v) |
2570 | { | |
2571 | int old_val; | |
2572 | ||
2573 | old_val = atomic_read(v); | |
2574 | while (atomic_cmpxchg(v, old_val, val | old_val) != old_val) | |
2575 | old_val = atomic_read(v); | |
2576 | } | |
2577 | ||
4531603a FL |
2578 | static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) |
2579 | { | |
cb7cf7be | 2580 | struct brcmf_core *buscore; |
4531603a FL |
2581 | u32 addr; |
2582 | unsigned long val; | |
5cbb9c28 | 2583 | int ret; |
4531603a | 2584 | |
cb7cf7be AS |
2585 | buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
2586 | addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus); | |
4531603a | 2587 | |
a39be27b | 2588 | val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret); |
4531603a FL |
2589 | bus->sdcnt.f1regdata++; |
2590 | if (ret != 0) | |
5cbb9c28 | 2591 | return ret; |
4531603a FL |
2592 | |
2593 | val &= bus->hostintmask; | |
2594 | atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); | |
2595 | ||
2596 | /* Clear interrupts */ | |
2597 | if (val) { | |
a39be27b | 2598 | brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret); |
4531603a | 2599 | bus->sdcnt.f1regdata++; |
5cbb9c28 | 2600 | atomic_orr(val, &bus->intstatus); |
4531603a FL |
2601 | } |
2602 | ||
2603 | return ret; | |
2604 | } | |
2605 | ||
82d7f3c1 | 2606 | static void brcmf_sdio_dpc(struct brcmf_sdio *bus) |
5b435de0 | 2607 | { |
4531603a FL |
2608 | u32 newstatus = 0; |
2609 | unsigned long intstatus; | |
5b435de0 | 2610 | uint txlimit = bus->txbound; /* Tx frames to send before resched */ |
b6a8cf2c | 2611 | uint framecnt; /* Temporary counter of tx/rx frames */ |
5cbb9c28 | 2612 | int err = 0; |
5b435de0 AS |
2613 | |
2614 | brcmf_dbg(TRACE, "Enter\n"); | |
2615 | ||
38b0b0dd | 2616 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2617 | |
2618 | /* If waiting for HTAVAIL, check status */ | |
4a3da990 | 2619 | if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { |
5b435de0 AS |
2620 | u8 clkctl, devctl = 0; |
2621 | ||
8ae74654 | 2622 | #ifdef DEBUG |
5b435de0 | 2623 | /* Check for inconsistent device control */ |
a39be27b AS |
2624 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
2625 | SBSDIO_DEVICE_CTL, &err); | |
8ae74654 | 2626 | #endif /* DEBUG */ |
5b435de0 AS |
2627 | |
2628 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
a39be27b AS |
2629 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
2630 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 2631 | |
c3203374 | 2632 | brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", |
5b435de0 AS |
2633 | devctl, clkctl); |
2634 | ||
2635 | if (SBSDIO_HTAV(clkctl)) { | |
a39be27b AS |
2636 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
2637 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 2638 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
2639 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
2640 | devctl, &err); | |
5b435de0 | 2641 | bus->clkstate = CLK_AVAIL; |
5b435de0 AS |
2642 | } |
2643 | } | |
2644 | ||
5b435de0 | 2645 | /* Make sure backplane clock is on */ |
82d7f3c1 | 2646 | brcmf_sdio_bus_sleep(bus, false, true); |
5b435de0 AS |
2647 | |
2648 | /* Pending interrupt indicates new device status */ | |
1d382273 FL |
2649 | if (atomic_read(&bus->ipend) > 0) { |
2650 | atomic_set(&bus->ipend, 0); | |
4531603a | 2651 | err = brcmf_sdio_intr_rstatus(bus); |
5b435de0 AS |
2652 | } |
2653 | ||
4531603a FL |
2654 | /* Start with leftover status bits */ |
2655 | intstatus = atomic_xchg(&bus->intstatus, 0); | |
5b435de0 AS |
2656 | |
2657 | /* Handle flow-control change: read new state in case our ack | |
2658 | * crossed another change interrupt. If change still set, assume | |
2659 | * FC ON for safety, let next loop through do the debounce. | |
2660 | */ | |
2661 | if (intstatus & I_HMB_FC_CHANGE) { | |
2662 | intstatus &= ~I_HMB_FC_CHANGE; | |
5c15c23a FL |
2663 | err = w_sdreg32(bus, I_HMB_FC_CHANGE, |
2664 | offsetof(struct sdpcmd_regs, intstatus)); | |
5b435de0 | 2665 | |
5c15c23a FL |
2666 | err = r_sdreg32(bus, &newstatus, |
2667 | offsetof(struct sdpcmd_regs, intstatus)); | |
80969836 | 2668 | bus->sdcnt.f1regdata += 2; |
4531603a FL |
2669 | atomic_set(&bus->fcstate, |
2670 | !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); | |
5b435de0 AS |
2671 | intstatus |= (newstatus & bus->hostintmask); |
2672 | } | |
2673 | ||
2674 | /* Handle host mailbox indication */ | |
2675 | if (intstatus & I_HMB_HOST_INT) { | |
2676 | intstatus &= ~I_HMB_HOST_INT; | |
82d7f3c1 | 2677 | intstatus |= brcmf_sdio_hostmail(bus); |
5b435de0 AS |
2678 | } |
2679 | ||
38b0b0dd | 2680 | sdio_release_host(bus->sdiodev->func[1]); |
7cdf57d3 | 2681 | |
5b435de0 AS |
2682 | /* Generally don't ask for these, can get CRC errors... */ |
2683 | if (intstatus & I_WR_OOSYNC) { | |
5e8149f5 | 2684 | brcmf_err("Dongle reports WR_OOSYNC\n"); |
5b435de0 AS |
2685 | intstatus &= ~I_WR_OOSYNC; |
2686 | } | |
2687 | ||
2688 | if (intstatus & I_RD_OOSYNC) { | |
5e8149f5 | 2689 | brcmf_err("Dongle reports RD_OOSYNC\n"); |
5b435de0 AS |
2690 | intstatus &= ~I_RD_OOSYNC; |
2691 | } | |
2692 | ||
2693 | if (intstatus & I_SBINT) { | |
5e8149f5 | 2694 | brcmf_err("Dongle reports SBINT\n"); |
5b435de0 AS |
2695 | intstatus &= ~I_SBINT; |
2696 | } | |
2697 | ||
2698 | /* Would be active due to wake-wlan in gSPI */ | |
2699 | if (intstatus & I_CHIPACTIVE) { | |
2700 | brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); | |
2701 | intstatus &= ~I_CHIPACTIVE; | |
2702 | } | |
2703 | ||
2704 | /* Ignore frame indications if rxskip is set */ | |
2705 | if (bus->rxskip) | |
2706 | intstatus &= ~I_HMB_FRAME_IND; | |
2707 | ||
2708 | /* On frame indication, read available frames */ | |
b6a8cf2c HM |
2709 | if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { |
2710 | brcmf_sdio_readframes(bus, bus->rxbound); | |
4754fcee | 2711 | if (!bus->rxpending) |
5b435de0 | 2712 | intstatus &= ~I_HMB_FRAME_IND; |
5b435de0 AS |
2713 | } |
2714 | ||
2715 | /* Keep still-pending events for next scheduling */ | |
5cbb9c28 HM |
2716 | if (intstatus) |
2717 | atomic_orr(intstatus, &bus->intstatus); | |
5b435de0 | 2718 | |
82d7f3c1 | 2719 | brcmf_sdio_clrintr(bus); |
ba89bf19 | 2720 | |
fed7ec44 | 2721 | if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && |
4dd8b26a HM |
2722 | data_ok(bus)) { |
2723 | sdio_claim_host(bus->sdiodev->func[1]); | |
2724 | err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, | |
2725 | bus->ctrl_frame_len); | |
2726 | sdio_release_host(bus->sdiodev->func[1]); | |
2727 | bus->ctrl_frame_err = err; | |
2728 | bus->ctrl_frame_stat = false; | |
2729 | brcmf_sdio_wait_event_wakeup(bus); | |
5b435de0 AS |
2730 | } |
2731 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
fed7ec44 HM |
2732 | if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && |
2733 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && | |
2734 | data_ok(bus)) { | |
4754fcee FL |
2735 | framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : |
2736 | txlimit; | |
b6a8cf2c | 2737 | brcmf_sdio_sendfromq(bus, framecnt); |
5b435de0 AS |
2738 | } |
2739 | ||
a1ce7a0d | 2740 | if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { |
5e8149f5 | 2741 | brcmf_err("failed backplane access over SDIO, halting operation\n"); |
4531603a FL |
2742 | atomic_set(&bus->intstatus, 0); |
2743 | } else if (atomic_read(&bus->intstatus) || | |
2744 | atomic_read(&bus->ipend) > 0 || | |
2745 | (!atomic_read(&bus->fcstate) && | |
2746 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
b6a8cf2c | 2747 | data_ok(bus))) { |
fccfe930 | 2748 | atomic_inc(&bus->dpc_tskcnt); |
5b435de0 | 2749 | } |
5b435de0 AS |
2750 | } |
2751 | ||
82d7f3c1 | 2752 | static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) |
e2432b67 AS |
2753 | { |
2754 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
2755 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
2756 | struct brcmf_sdio *bus = sdiodev->bus; | |
2757 | ||
2758 | return &bus->txq; | |
2759 | } | |
2760 | ||
84936626 HM |
2761 | static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) |
2762 | { | |
2763 | struct sk_buff *p; | |
2764 | int eprec = -1; /* precedence to evict from */ | |
2765 | ||
2766 | /* Fast case, precedence queue is not full and we are also not | |
2767 | * exceeding total queue length | |
2768 | */ | |
2769 | if (!pktq_pfull(q, prec) && !pktq_full(q)) { | |
2770 | brcmu_pktq_penq(q, prec, pkt); | |
2771 | return true; | |
2772 | } | |
2773 | ||
2774 | /* Determine precedence from which to evict packet, if any */ | |
2775 | if (pktq_pfull(q, prec)) { | |
2776 | eprec = prec; | |
2777 | } else if (pktq_full(q)) { | |
2778 | p = brcmu_pktq_peek_tail(q, &eprec); | |
2779 | if (eprec > prec) | |
2780 | return false; | |
2781 | } | |
2782 | ||
2783 | /* Evict if needed */ | |
2784 | if (eprec >= 0) { | |
2785 | /* Detect queueing to unconfigured precedence */ | |
2786 | if (eprec == prec) | |
2787 | return false; /* refuse newer (incoming) packet */ | |
2788 | /* Evict packet according to discard policy */ | |
2789 | p = brcmu_pktq_pdeq_tail(q, eprec); | |
2790 | if (p == NULL) | |
2791 | brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); | |
2792 | brcmu_pkt_buf_free_skb(p); | |
2793 | } | |
2794 | ||
2795 | /* Enqueue */ | |
2796 | p = brcmu_pktq_penq(q, prec, pkt); | |
2797 | if (p == NULL) | |
2798 | brcmf_err("brcmu_pktq_penq() failed\n"); | |
2799 | ||
2800 | return p != NULL; | |
2801 | } | |
2802 | ||
82d7f3c1 | 2803 | static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) |
5b435de0 AS |
2804 | { |
2805 | int ret = -EBADE; | |
44ff5660 | 2806 | uint prec; |
bf347bb9 | 2807 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2808 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
bf347bb9 | 2809 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 | 2810 | |
44ff5660 | 2811 | brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); |
5b435de0 AS |
2812 | |
2813 | /* Add space for the header */ | |
706478cb | 2814 | skb_push(pkt, bus->tx_hdrlen); |
5b435de0 AS |
2815 | /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ |
2816 | ||
2817 | prec = prio2prec((pkt->priority & PRIOMASK)); | |
2818 | ||
2819 | /* Check for existing queue, current flow-control, | |
2820 | pending event, or pending clock */ | |
2821 | brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); | |
80969836 | 2822 | bus->sdcnt.fcqueued++; |
5b435de0 AS |
2823 | |
2824 | /* Priority based enq */ | |
fed7ec44 | 2825 | spin_lock_bh(&bus->txq_lock); |
5aa9f0ea AS |
2826 | /* reset bus_flags in packet cb */ |
2827 | *(u16 *)(pkt->cb) = 0; | |
84936626 | 2828 | if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { |
706478cb | 2829 | skb_pull(pkt, bus->tx_hdrlen); |
5e8149f5 | 2830 | brcmf_err("out of bus->txq !!!\n"); |
5b435de0 AS |
2831 | ret = -ENOSR; |
2832 | } else { | |
2833 | ret = 0; | |
2834 | } | |
5b435de0 | 2835 | |
c8bf3484 | 2836 | if (pktq_len(&bus->txq) >= TXHI) { |
90d03ff7 | 2837 | bus->txoff = true; |
84936626 | 2838 | brcmf_txflowblock(dev, true); |
c8bf3484 | 2839 | } |
fed7ec44 | 2840 | spin_unlock_bh(&bus->txq_lock); |
5b435de0 | 2841 | |
8ae74654 | 2842 | #ifdef DEBUG |
5b435de0 AS |
2843 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) |
2844 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2845 | #endif | |
f1e68c2e | 2846 | |
99824643 | 2847 | brcmf_sdio_trigger_dpc(bus); |
5b435de0 AS |
2848 | return ret; |
2849 | } | |
2850 | ||
8ae74654 | 2851 | #ifdef DEBUG |
5b435de0 AS |
2852 | #define CONSOLE_LINE_MAX 192 |
2853 | ||
82d7f3c1 | 2854 | static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) |
5b435de0 AS |
2855 | { |
2856 | struct brcmf_console *c = &bus->console; | |
2857 | u8 line[CONSOLE_LINE_MAX], ch; | |
2858 | u32 n, idx, addr; | |
2859 | int rv; | |
2860 | ||
2861 | /* Don't do anything until FWREADY updates console address */ | |
2862 | if (bus->console_addr == 0) | |
2863 | return 0; | |
2864 | ||
2865 | /* Read console log struct */ | |
2866 | addr = bus->console_addr + offsetof(struct rte_console, log_le); | |
a39be27b AS |
2867 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, |
2868 | sizeof(c->log_le)); | |
5b435de0 AS |
2869 | if (rv < 0) |
2870 | return rv; | |
2871 | ||
2872 | /* Allocate console buffer (one time only) */ | |
2873 | if (c->buf == NULL) { | |
2874 | c->bufsize = le32_to_cpu(c->log_le.buf_size); | |
2875 | c->buf = kmalloc(c->bufsize, GFP_ATOMIC); | |
2876 | if (c->buf == NULL) | |
2877 | return -ENOMEM; | |
2878 | } | |
2879 | ||
2880 | idx = le32_to_cpu(c->log_le.idx); | |
2881 | ||
2882 | /* Protect against corrupt value */ | |
2883 | if (idx > c->bufsize) | |
2884 | return -EBADE; | |
2885 | ||
2886 | /* Skip reading the console buffer if the index pointer | |
2887 | has not moved */ | |
2888 | if (idx == c->last) | |
2889 | return 0; | |
2890 | ||
2891 | /* Read the console buffer */ | |
2892 | addr = le32_to_cpu(c->log_le.buf); | |
a39be27b | 2893 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); |
5b435de0 AS |
2894 | if (rv < 0) |
2895 | return rv; | |
2896 | ||
2897 | while (c->last != idx) { | |
2898 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
2899 | if (c->last == idx) { | |
2900 | /* This would output a partial line. | |
2901 | * Instead, back up | |
2902 | * the buffer pointer and output this | |
2903 | * line next time around. | |
2904 | */ | |
2905 | if (c->last >= n) | |
2906 | c->last -= n; | |
2907 | else | |
2908 | c->last = c->bufsize - n; | |
2909 | goto break2; | |
2910 | } | |
2911 | ch = c->buf[c->last]; | |
2912 | c->last = (c->last + 1) % c->bufsize; | |
2913 | if (ch == '\n') | |
2914 | break; | |
2915 | line[n] = ch; | |
2916 | } | |
2917 | ||
2918 | if (n > 0) { | |
2919 | if (line[n - 1] == '\r') | |
2920 | n--; | |
2921 | line[n] = 0; | |
18aad4f8 | 2922 | pr_debug("CONSOLE: %s\n", line); |
5b435de0 AS |
2923 | } |
2924 | } | |
2925 | break2: | |
2926 | ||
2927 | return 0; | |
2928 | } | |
8ae74654 | 2929 | #endif /* DEBUG */ |
5b435de0 | 2930 | |
fcf094f4 | 2931 | static int |
82d7f3c1 | 2932 | brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 | 2933 | { |
47a1ce78 | 2934 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2935 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
47a1ce78 | 2936 | struct brcmf_sdio *bus = sdiodev->bus; |
4dd8b26a | 2937 | int ret; |
5b435de0 AS |
2938 | |
2939 | brcmf_dbg(TRACE, "Enter\n"); | |
2940 | ||
4dd8b26a HM |
2941 | /* Send from dpc */ |
2942 | bus->ctrl_frame_buf = msg; | |
2943 | bus->ctrl_frame_len = msglen; | |
2944 | bus->ctrl_frame_stat = true; | |
4dd8b26a | 2945 | |
99824643 | 2946 | brcmf_sdio_trigger_dpc(bus); |
4dd8b26a HM |
2947 | wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, |
2948 | msecs_to_jiffies(CTL_DONE_TIMEOUT)); | |
2949 | ||
2950 | if (!bus->ctrl_frame_stat) { | |
2951 | brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", | |
2952 | bus->ctrl_frame_err); | |
2953 | ret = bus->ctrl_frame_err; | |
2954 | } else { | |
2955 | brcmf_dbg(SDIO, "ctrl_frame timeout\n"); | |
2956 | bus->ctrl_frame_stat = false; | |
2957 | ret = -ETIMEDOUT; | |
5b435de0 AS |
2958 | } |
2959 | ||
5b435de0 | 2960 | if (ret) |
80969836 | 2961 | bus->sdcnt.tx_ctlerrs++; |
5b435de0 | 2962 | else |
80969836 | 2963 | bus->sdcnt.tx_ctlpkts++; |
5b435de0 | 2964 | |
4dd8b26a | 2965 | return ret; |
5b435de0 AS |
2966 | } |
2967 | ||
80969836 | 2968 | #ifdef DEBUG |
1b1e4e9e AS |
2969 | static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, |
2970 | struct sdpcm_shared *sh) | |
4fc0d016 AS |
2971 | { |
2972 | u32 addr, console_ptr, console_size, console_index; | |
2973 | char *conbuf = NULL; | |
2974 | __le32 sh_val; | |
2975 | int rv; | |
4fc0d016 AS |
2976 | |
2977 | /* obtain console information from device memory */ | |
2978 | addr = sh->console_addr + offsetof(struct rte_console, log_le); | |
a39be27b AS |
2979 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2980 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2981 | if (rv < 0) |
2982 | return rv; | |
2983 | console_ptr = le32_to_cpu(sh_val); | |
2984 | ||
2985 | addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); | |
a39be27b AS |
2986 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2987 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2988 | if (rv < 0) |
2989 | return rv; | |
2990 | console_size = le32_to_cpu(sh_val); | |
2991 | ||
2992 | addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); | |
a39be27b AS |
2993 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2994 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2995 | if (rv < 0) |
2996 | return rv; | |
2997 | console_index = le32_to_cpu(sh_val); | |
2998 | ||
2999 | /* allocate buffer for console data */ | |
3000 | if (console_size <= CONSOLE_BUFFER_MAX) | |
3001 | conbuf = vzalloc(console_size+1); | |
3002 | ||
3003 | if (!conbuf) | |
3004 | return -ENOMEM; | |
3005 | ||
3006 | /* obtain the console data from device */ | |
3007 | conbuf[console_size] = '\0'; | |
a39be27b AS |
3008 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, |
3009 | console_size); | |
4fc0d016 AS |
3010 | if (rv < 0) |
3011 | goto done; | |
3012 | ||
1b1e4e9e AS |
3013 | rv = seq_write(seq, conbuf + console_index, |
3014 | console_size - console_index); | |
4fc0d016 AS |
3015 | if (rv < 0) |
3016 | goto done; | |
3017 | ||
1b1e4e9e AS |
3018 | if (console_index > 0) |
3019 | rv = seq_write(seq, conbuf, console_index - 1); | |
3020 | ||
4fc0d016 AS |
3021 | done: |
3022 | vfree(conbuf); | |
3023 | return rv; | |
3024 | } | |
3025 | ||
1b1e4e9e AS |
3026 | static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, |
3027 | struct sdpcm_shared *sh) | |
4fc0d016 | 3028 | { |
1b1e4e9e | 3029 | int error; |
4fc0d016 | 3030 | struct brcmf_trap_info tr; |
4fc0d016 | 3031 | |
baa9e609 PH |
3032 | if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { |
3033 | brcmf_dbg(INFO, "no trap in firmware\n"); | |
4fc0d016 | 3034 | return 0; |
baa9e609 | 3035 | } |
4fc0d016 | 3036 | |
a39be27b AS |
3037 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, |
3038 | sizeof(struct brcmf_trap_info)); | |
4fc0d016 AS |
3039 | if (error < 0) |
3040 | return error; | |
3041 | ||
1b1e4e9e AS |
3042 | seq_printf(seq, |
3043 | "dongle trap info: type 0x%x @ epc 0x%08x\n" | |
3044 | " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" | |
3045 | " lr 0x%08x pc 0x%08x offset 0x%x\n" | |
3046 | " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" | |
3047 | " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", | |
3048 | le32_to_cpu(tr.type), le32_to_cpu(tr.epc), | |
3049 | le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), | |
3050 | le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), | |
3051 | le32_to_cpu(tr.pc), sh->trap_addr, | |
3052 | le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), | |
3053 | le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), | |
3054 | le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), | |
3055 | le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); | |
3056 | ||
3057 | return 0; | |
4fc0d016 AS |
3058 | } |
3059 | ||
1b1e4e9e AS |
3060 | static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, |
3061 | struct sdpcm_shared *sh) | |
4fc0d016 AS |
3062 | { |
3063 | int error = 0; | |
4fc0d016 AS |
3064 | char file[80] = "?"; |
3065 | char expr[80] = "<???>"; | |
4fc0d016 AS |
3066 | |
3067 | if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { | |
3068 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3069 | return 0; | |
3070 | } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { | |
3071 | brcmf_dbg(INFO, "no assert in dongle\n"); | |
3072 | return 0; | |
3073 | } | |
3074 | ||
38b0b0dd | 3075 | sdio_claim_host(bus->sdiodev->func[1]); |
4fc0d016 | 3076 | if (sh->assert_file_addr != 0) { |
a39be27b AS |
3077 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, |
3078 | sh->assert_file_addr, (u8 *)file, 80); | |
4fc0d016 AS |
3079 | if (error < 0) |
3080 | return error; | |
3081 | } | |
3082 | if (sh->assert_exp_addr != 0) { | |
a39be27b AS |
3083 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, |
3084 | sh->assert_exp_addr, (u8 *)expr, 80); | |
4fc0d016 AS |
3085 | if (error < 0) |
3086 | return error; | |
3087 | } | |
38b0b0dd | 3088 | sdio_release_host(bus->sdiodev->func[1]); |
4fc0d016 | 3089 | |
1b1e4e9e AS |
3090 | seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", |
3091 | file, sh->assert_line, expr); | |
3092 | return 0; | |
4fc0d016 AS |
3093 | } |
3094 | ||
82d7f3c1 | 3095 | static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) |
4fc0d016 AS |
3096 | { |
3097 | int error; | |
3098 | struct sdpcm_shared sh; | |
3099 | ||
4fc0d016 | 3100 | error = brcmf_sdio_readshared(bus, &sh); |
4fc0d016 AS |
3101 | |
3102 | if (error < 0) | |
3103 | return error; | |
3104 | ||
3105 | if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) | |
3106 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3107 | else if (sh.flags & SDPCM_SHARED_ASSERT) | |
5e8149f5 | 3108 | brcmf_err("assertion in dongle\n"); |
4fc0d016 AS |
3109 | |
3110 | if (sh.flags & SDPCM_SHARED_TRAP) | |
5e8149f5 | 3111 | brcmf_err("firmware trap in dongle\n"); |
4fc0d016 AS |
3112 | |
3113 | return 0; | |
3114 | } | |
3115 | ||
1b1e4e9e | 3116 | static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) |
4fc0d016 AS |
3117 | { |
3118 | int error = 0; | |
3119 | struct sdpcm_shared sh; | |
4fc0d016 | 3120 | |
4fc0d016 AS |
3121 | error = brcmf_sdio_readshared(bus, &sh); |
3122 | if (error < 0) | |
3123 | goto done; | |
3124 | ||
1b1e4e9e | 3125 | error = brcmf_sdio_assert_info(seq, bus, &sh); |
4fc0d016 AS |
3126 | if (error < 0) |
3127 | goto done; | |
baa9e609 | 3128 | |
1b1e4e9e | 3129 | error = brcmf_sdio_trap_info(seq, bus, &sh); |
4fc0d016 AS |
3130 | if (error < 0) |
3131 | goto done; | |
baa9e609 | 3132 | |
1b1e4e9e | 3133 | error = brcmf_sdio_dump_console(seq, bus, &sh); |
4fc0d016 | 3134 | |
4fc0d016 | 3135 | done: |
4fc0d016 AS |
3136 | return error; |
3137 | } | |
3138 | ||
1b1e4e9e | 3139 | static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) |
4fc0d016 | 3140 | { |
82d957e0 AS |
3141 | struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); |
3142 | struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; | |
4fc0d016 | 3143 | |
1b1e4e9e AS |
3144 | return brcmf_sdio_died_dump(seq, bus); |
3145 | } | |
3146 | ||
82d957e0 | 3147 | static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) |
1b1e4e9e | 3148 | { |
82d957e0 AS |
3149 | struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); |
3150 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3151 | struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; | |
4fc0d016 | 3152 | |
82d957e0 AS |
3153 | seq_printf(seq, |
3154 | "intrcount: %u\nlastintrs: %u\n" | |
3155 | "pollcnt: %u\nregfails: %u\n" | |
3156 | "tx_sderrs: %u\nfcqueued: %u\n" | |
3157 | "rxrtx: %u\nrx_toolong: %u\n" | |
3158 | "rxc_errors: %u\nrx_hdrfail: %u\n" | |
3159 | "rx_badhdr: %u\nrx_badseq: %u\n" | |
3160 | "fc_rcvd: %u\nfc_xoff: %u\n" | |
3161 | "fc_xon: %u\nrxglomfail: %u\n" | |
3162 | "rxglomframes: %u\nrxglompkts: %u\n" | |
3163 | "f2rxhdrs: %u\nf2rxdata: %u\n" | |
3164 | "f2txdata: %u\nf1regdata: %u\n" | |
3165 | "tickcnt: %u\ntx_ctlerrs: %lu\n" | |
3166 | "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" | |
3167 | "rx_ctlpkts: %lu\nrx_readahead: %lu\n", | |
3168 | sdcnt->intrcount, sdcnt->lastintrs, | |
3169 | sdcnt->pollcnt, sdcnt->regfails, | |
3170 | sdcnt->tx_sderrs, sdcnt->fcqueued, | |
3171 | sdcnt->rxrtx, sdcnt->rx_toolong, | |
3172 | sdcnt->rxc_errors, sdcnt->rx_hdrfail, | |
3173 | sdcnt->rx_badhdr, sdcnt->rx_badseq, | |
3174 | sdcnt->fc_rcvd, sdcnt->fc_xoff, | |
3175 | sdcnt->fc_xon, sdcnt->rxglomfail, | |
3176 | sdcnt->rxglomframes, sdcnt->rxglompkts, | |
3177 | sdcnt->f2rxhdrs, sdcnt->f2rxdata, | |
3178 | sdcnt->f2txdata, sdcnt->f1regdata, | |
3179 | sdcnt->tickcnt, sdcnt->tx_ctlerrs, | |
3180 | sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, | |
3181 | sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); | |
3182 | ||
3183 | return 0; | |
3184 | } | |
4fc0d016 | 3185 | |
80969836 AS |
3186 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3187 | { | |
3188 | struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; | |
4fc0d016 | 3189 | struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); |
80969836 | 3190 | |
4fc0d016 AS |
3191 | if (IS_ERR_OR_NULL(dentry)) |
3192 | return; | |
3193 | ||
82d957e0 AS |
3194 | brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); |
3195 | brcmf_debugfs_add_entry(drvr, "counters", | |
3196 | brcmf_debugfs_sdio_count_read); | |
0801e6c5 DK |
3197 | debugfs_create_u32("console_interval", 0644, dentry, |
3198 | &bus->console_interval); | |
80969836 AS |
3199 | } |
3200 | #else | |
82d7f3c1 | 3201 | static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) |
4fc0d016 AS |
3202 | { |
3203 | return 0; | |
3204 | } | |
3205 | ||
80969836 AS |
3206 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3207 | { | |
3208 | } | |
3209 | #endif /* DEBUG */ | |
3210 | ||
fcf094f4 | 3211 | static int |
82d7f3c1 | 3212 | brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
3213 | { |
3214 | int timeleft; | |
3215 | uint rxlen = 0; | |
3216 | bool pending; | |
dd43a01c | 3217 | u8 *buf; |
532cdd3b | 3218 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3219 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
532cdd3b | 3220 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
3221 | |
3222 | brcmf_dbg(TRACE, "Enter\n"); | |
3223 | ||
3224 | /* Wait until control frame is available */ | |
82d7f3c1 | 3225 | timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); |
5b435de0 | 3226 | |
dd43a01c | 3227 | spin_lock_bh(&bus->rxctl_lock); |
5b435de0 AS |
3228 | rxlen = bus->rxlen; |
3229 | memcpy(msg, bus->rxctl, min(msglen, rxlen)); | |
dd43a01c FL |
3230 | bus->rxctl = NULL; |
3231 | buf = bus->rxctl_orig; | |
3232 | bus->rxctl_orig = NULL; | |
5b435de0 | 3233 | bus->rxlen = 0; |
dd43a01c FL |
3234 | spin_unlock_bh(&bus->rxctl_lock); |
3235 | vfree(buf); | |
5b435de0 AS |
3236 | |
3237 | if (rxlen) { | |
3238 | brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", | |
3239 | rxlen, msglen); | |
3240 | } else if (timeleft == 0) { | |
5e8149f5 | 3241 | brcmf_err("resumed on timeout\n"); |
82d7f3c1 | 3242 | brcmf_sdio_checkdied(bus); |
23677ce3 | 3243 | } else if (pending) { |
5b435de0 AS |
3244 | brcmf_dbg(CTL, "cancelled\n"); |
3245 | return -ERESTARTSYS; | |
3246 | } else { | |
3247 | brcmf_dbg(CTL, "resumed for unknown reason?\n"); | |
82d7f3c1 | 3248 | brcmf_sdio_checkdied(bus); |
5b435de0 AS |
3249 | } |
3250 | ||
3251 | if (rxlen) | |
80969836 | 3252 | bus->sdcnt.rx_ctlpkts++; |
5b435de0 | 3253 | else |
80969836 | 3254 | bus->sdcnt.rx_ctlerrs++; |
5b435de0 AS |
3255 | |
3256 | return rxlen ? (int)rxlen : -ETIMEDOUT; | |
3257 | } | |
3258 | ||
a74d036f HM |
3259 | #ifdef DEBUG |
3260 | static bool | |
3261 | brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, | |
3262 | u8 *ram_data, uint ram_sz) | |
3263 | { | |
3264 | char *ram_cmp; | |
3265 | int err; | |
3266 | bool ret = true; | |
3267 | int address; | |
3268 | int offset; | |
3269 | int len; | |
3270 | ||
3271 | /* read back and verify */ | |
3272 | brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, | |
3273 | ram_sz); | |
3274 | ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); | |
3275 | /* do not proceed while no memory but */ | |
3276 | if (!ram_cmp) | |
3277 | return true; | |
3278 | ||
3279 | address = ram_addr; | |
3280 | offset = 0; | |
3281 | while (offset < ram_sz) { | |
3282 | len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : | |
3283 | ram_sz - offset; | |
3284 | err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); | |
3285 | if (err) { | |
3286 | brcmf_err("error %d on reading %d membytes at 0x%08x\n", | |
3287 | err, len, address); | |
3288 | ret = false; | |
3289 | break; | |
3290 | } else if (memcmp(ram_cmp, &ram_data[offset], len)) { | |
3291 | brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", | |
3292 | offset, len); | |
3293 | ret = false; | |
3294 | break; | |
3295 | } | |
3296 | offset += len; | |
3297 | address += len; | |
3298 | } | |
3299 | ||
3300 | kfree(ram_cmp); | |
3301 | ||
3302 | return ret; | |
3303 | } | |
3304 | #else /* DEBUG */ | |
3305 | static bool | |
3306 | brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, | |
3307 | u8 *ram_data, uint ram_sz) | |
3308 | { | |
3309 | return true; | |
3310 | } | |
3311 | #endif /* DEBUG */ | |
3312 | ||
3355650c AS |
3313 | static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, |
3314 | const struct firmware *fw) | |
5b435de0 | 3315 | { |
f2c44fe7 | 3316 | int err; |
f2c44fe7 | 3317 | |
a74d036f HM |
3318 | brcmf_dbg(TRACE, "Enter\n"); |
3319 | ||
f9951c13 HM |
3320 | err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, |
3321 | (u8 *)fw->data, fw->size); | |
3322 | if (err) | |
3323 | brcmf_err("error %d on writing %d membytes at 0x%08x\n", | |
3324 | err, (int)fw->size, bus->ci->rambase); | |
3325 | else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, | |
3326 | (u8 *)fw->data, fw->size)) | |
3327 | err = -EIO; | |
5b435de0 | 3328 | |
f2c44fe7 | 3329 | return err; |
5b435de0 AS |
3330 | } |
3331 | ||
3355650c | 3332 | static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, |
bd0e1b1d | 3333 | void *vars, u32 varsz) |
5b435de0 | 3334 | { |
a74d036f HM |
3335 | int address; |
3336 | int err; | |
3337 | ||
3338 | brcmf_dbg(TRACE, "Enter\n"); | |
5b435de0 | 3339 | |
a74d036f HM |
3340 | address = bus->ci->ramsize - varsz + bus->ci->rambase; |
3341 | err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); | |
3342 | if (err) | |
3343 | brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", | |
3344 | err, varsz, address); | |
3345 | else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) | |
3346 | err = -EIO; | |
3347 | ||
a74d036f | 3348 | return err; |
5b435de0 AS |
3349 | } |
3350 | ||
bd0e1b1d AS |
3351 | static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, |
3352 | const struct firmware *fw, | |
3353 | void *nvram, u32 nvlen) | |
5b435de0 | 3354 | { |
82d7f3c1 | 3355 | int bcmerror = -EFAULT; |
3355650c | 3356 | u32 rstvec; |
82d7f3c1 AS |
3357 | |
3358 | sdio_claim_host(bus->sdiodev->func[1]); | |
3359 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
5b435de0 AS |
3360 | |
3361 | /* Keep arm in reset */ | |
cb7cf7be | 3362 | brcmf_chip_enter_download(bus->ci); |
3355650c | 3363 | |
3355650c AS |
3364 | rstvec = get_unaligned_le32(fw->data); |
3365 | brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); | |
3366 | ||
3367 | bcmerror = brcmf_sdio_download_code_file(bus, fw); | |
3368 | release_firmware(fw); | |
3369 | if (bcmerror) { | |
5e8149f5 | 3370 | brcmf_err("dongle image file download failed\n"); |
bd0e1b1d | 3371 | brcmf_fw_nvram_free(nvram); |
5b435de0 AS |
3372 | goto err; |
3373 | } | |
3374 | ||
bd0e1b1d AS |
3375 | bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); |
3376 | brcmf_fw_nvram_free(nvram); | |
3355650c | 3377 | if (bcmerror) { |
5e8149f5 | 3378 | brcmf_err("dongle nvram file download failed\n"); |
3eaa956c FL |
3379 | goto err; |
3380 | } | |
5b435de0 AS |
3381 | |
3382 | /* Take arm out of reset */ | |
cb7cf7be | 3383 | if (!brcmf_chip_exit_download(bus->ci, rstvec)) { |
5e8149f5 | 3384 | brcmf_err("error getting out of ARM core reset\n"); |
5b435de0 AS |
3385 | goto err; |
3386 | } | |
3387 | ||
a1cee865 | 3388 | /* Allow full data communication using DPC from now on. */ |
a1ce7a0d | 3389 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); |
5b435de0 AS |
3390 | bcmerror = 0; |
3391 | ||
3392 | err: | |
82d7f3c1 AS |
3393 | brcmf_sdio_clkctl(bus, CLK_SDONLY, false); |
3394 | sdio_release_host(bus->sdiodev->func[1]); | |
5b435de0 AS |
3395 | return bcmerror; |
3396 | } | |
3397 | ||
82d7f3c1 | 3398 | static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) |
4a3da990 PH |
3399 | { |
3400 | int err = 0; | |
3401 | u8 val; | |
3402 | ||
3403 | brcmf_dbg(TRACE, "Enter\n"); | |
3404 | ||
a39be27b | 3405 | val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); |
4a3da990 PH |
3406 | if (err) { |
3407 | brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3408 | return; | |
3409 | } | |
3410 | ||
3411 | val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; | |
a39be27b | 3412 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); |
4a3da990 PH |
3413 | if (err) { |
3414 | brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3415 | return; | |
3416 | } | |
3417 | ||
3418 | /* Add CMD14 Support */ | |
a39be27b AS |
3419 | brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, |
3420 | (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | | |
3421 | SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), | |
3422 | &err); | |
4a3da990 PH |
3423 | if (err) { |
3424 | brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); | |
3425 | return; | |
3426 | } | |
3427 | ||
a39be27b AS |
3428 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3429 | SBSDIO_FORCE_HT, &err); | |
4a3da990 PH |
3430 | if (err) { |
3431 | brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); | |
3432 | return; | |
3433 | } | |
3434 | ||
3435 | /* set flag */ | |
3436 | bus->sr_enabled = true; | |
3437 | brcmf_dbg(INFO, "SR enabled\n"); | |
3438 | } | |
3439 | ||
3440 | /* enable KSO bit */ | |
82d7f3c1 | 3441 | static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) |
4a3da990 PH |
3442 | { |
3443 | u8 val; | |
3444 | int err = 0; | |
3445 | ||
3446 | brcmf_dbg(TRACE, "Enter\n"); | |
3447 | ||
3448 | /* KSO bit added in SDIO core rev 12 */ | |
cb7cf7be | 3449 | if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) |
4a3da990 PH |
3450 | return 0; |
3451 | ||
a39be27b | 3452 | val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); |
4a3da990 PH |
3453 | if (err) { |
3454 | brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); | |
3455 | return err; | |
3456 | } | |
3457 | ||
3458 | if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { | |
3459 | val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << | |
3460 | SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
a39be27b AS |
3461 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
3462 | val, &err); | |
4a3da990 PH |
3463 | if (err) { |
3464 | brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); | |
3465 | return err; | |
3466 | } | |
3467 | } | |
3468 | ||
3469 | return 0; | |
3470 | } | |
3471 | ||
3472 | ||
82d7f3c1 | 3473 | static int brcmf_sdio_bus_preinit(struct device *dev) |
cf458287 AS |
3474 | { |
3475 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3476 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3477 | struct brcmf_sdio *bus = sdiodev->bus; | |
8da9d2c8 | 3478 | uint pad_size; |
cf458287 | 3479 | u32 value; |
cf458287 AS |
3480 | int err; |
3481 | ||
8da9d2c8 FL |
3482 | /* the commands below use the terms tx and rx from |
3483 | * a device perspective, ie. bus:txglom affects the | |
3484 | * bus transfers from device to host. | |
3485 | */ | |
cb7cf7be | 3486 | if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) { |
cf458287 AS |
3487 | /* for sdio core rev < 12, disable txgloming */ |
3488 | value = 0; | |
3489 | err = brcmf_iovar_data_set(dev, "bus:txglom", &value, | |
3490 | sizeof(u32)); | |
3491 | } else { | |
3492 | /* otherwise, set txglomalign */ | |
3493 | value = 4; | |
3494 | if (sdiodev->pdata) | |
3495 | value = sdiodev->pdata->sd_sgentry_align; | |
3496 | /* SDIO ADMA requires at least 32 bit alignment */ | |
3497 | value = max_t(u32, value, 4); | |
3498 | err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, | |
3499 | sizeof(u32)); | |
3500 | } | |
8da9d2c8 FL |
3501 | |
3502 | if (err < 0) | |
3503 | goto done; | |
3504 | ||
3505 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
3506 | if (sdiodev->sg_support) { | |
3507 | bus->txglom = false; | |
3508 | value = 1; | |
3509 | pad_size = bus->sdiodev->func[2]->cur_blksize << 1; | |
8da9d2c8 FL |
3510 | err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", |
3511 | &value, sizeof(u32)); | |
3512 | if (err < 0) { | |
3513 | /* bus:rxglom is allowed to fail */ | |
3514 | err = 0; | |
3515 | } else { | |
3516 | bus->txglom = true; | |
3517 | bus->tx_hdrlen += SDPCM_HWEXT_LEN; | |
3518 | } | |
3519 | } | |
3520 | brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); | |
3521 | ||
3522 | done: | |
cf458287 AS |
3523 | return err; |
3524 | } | |
3525 | ||
99824643 AS |
3526 | void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) |
3527 | { | |
3528 | if (atomic_read(&bus->dpc_tskcnt) == 0) { | |
3529 | atomic_inc(&bus->dpc_tskcnt); | |
3530 | queue_work(bus->brcmf_wq, &bus->datawork); | |
3531 | } | |
3532 | } | |
3533 | ||
82d7f3c1 | 3534 | void brcmf_sdio_isr(struct brcmf_sdio *bus) |
5b435de0 | 3535 | { |
5b435de0 AS |
3536 | brcmf_dbg(TRACE, "Enter\n"); |
3537 | ||
3538 | if (!bus) { | |
5e8149f5 | 3539 | brcmf_err("bus is null pointer, exiting\n"); |
5b435de0 AS |
3540 | return; |
3541 | } | |
3542 | ||
a1ce7a0d | 3543 | if (bus->sdiodev->state != BRCMF_SDIOD_DATA) { |
5e8149f5 | 3544 | brcmf_err("bus is down. we have nothing to do\n"); |
5b435de0 AS |
3545 | return; |
3546 | } | |
3547 | /* Count the interrupt call */ | |
80969836 | 3548 | bus->sdcnt.intrcount++; |
4531603a FL |
3549 | if (in_interrupt()) |
3550 | atomic_set(&bus->ipend, 1); | |
3551 | else | |
3552 | if (brcmf_sdio_intr_rstatus(bus)) { | |
5e8149f5 | 3553 | brcmf_err("failed backplane access\n"); |
4531603a | 3554 | } |
5b435de0 | 3555 | |
5b435de0 AS |
3556 | /* Disable additional interrupts (is this needed now)? */ |
3557 | if (!bus->intr) | |
5e8149f5 | 3558 | brcmf_err("isr w/o interrupt configured!\n"); |
5b435de0 | 3559 | |
fccfe930 | 3560 | atomic_inc(&bus->dpc_tskcnt); |
f1e68c2e | 3561 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3562 | } |
3563 | ||
82d7f3c1 | 3564 | static bool brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) |
5b435de0 | 3565 | { |
5b435de0 AS |
3566 | brcmf_dbg(TIMER, "Enter\n"); |
3567 | ||
5b435de0 | 3568 | /* Poll period: check device if appropriate. */ |
4a3da990 PH |
3569 | if (!bus->sr_enabled && |
3570 | bus->poll && (++bus->polltick >= bus->pollrate)) { | |
5b435de0 AS |
3571 | u32 intstatus = 0; |
3572 | ||
3573 | /* Reset poll tick */ | |
3574 | bus->polltick = 0; | |
3575 | ||
3576 | /* Check device if no interrupts */ | |
80969836 AS |
3577 | if (!bus->intr || |
3578 | (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { | |
5b435de0 | 3579 | |
fccfe930 | 3580 | if (atomic_read(&bus->dpc_tskcnt) == 0) { |
5b435de0 | 3581 | u8 devpend; |
fccfe930 | 3582 | |
38b0b0dd | 3583 | sdio_claim_host(bus->sdiodev->func[1]); |
a39be27b AS |
3584 | devpend = brcmf_sdiod_regrb(bus->sdiodev, |
3585 | SDIO_CCCR_INTx, | |
3586 | NULL); | |
38b0b0dd | 3587 | sdio_release_host(bus->sdiodev->func[1]); |
99824643 AS |
3588 | intstatus = devpend & (INTR_STATUS_FUNC1 | |
3589 | INTR_STATUS_FUNC2); | |
5b435de0 AS |
3590 | } |
3591 | ||
3592 | /* If there is something, make like the ISR and | |
3593 | schedule the DPC */ | |
3594 | if (intstatus) { | |
80969836 | 3595 | bus->sdcnt.pollcnt++; |
1d382273 | 3596 | atomic_set(&bus->ipend, 1); |
5b435de0 | 3597 | |
fccfe930 | 3598 | atomic_inc(&bus->dpc_tskcnt); |
f1e68c2e | 3599 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3600 | } |
3601 | } | |
3602 | ||
3603 | /* Update interrupt tracking */ | |
80969836 | 3604 | bus->sdcnt.lastintrs = bus->sdcnt.intrcount; |
5b435de0 | 3605 | } |
8ae74654 | 3606 | #ifdef DEBUG |
5b435de0 | 3607 | /* Poll for console output periodically */ |
a1ce7a0d | 3608 | if (bus->sdiodev->state == BRCMF_SDIOD_DATA && |
8d169aa0 | 3609 | bus->console_interval != 0) { |
5b435de0 AS |
3610 | bus->console.count += BRCMF_WD_POLL_MS; |
3611 | if (bus->console.count >= bus->console_interval) { | |
3612 | bus->console.count -= bus->console_interval; | |
38b0b0dd | 3613 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 3614 | /* Make sure backplane clock is on */ |
82d7f3c1 AS |
3615 | brcmf_sdio_bus_sleep(bus, false, false); |
3616 | if (brcmf_sdio_readconsole(bus) < 0) | |
5b435de0 AS |
3617 | /* stop on error */ |
3618 | bus->console_interval = 0; | |
38b0b0dd | 3619 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3620 | } |
3621 | } | |
8ae74654 | 3622 | #endif /* DEBUG */ |
5b435de0 AS |
3623 | |
3624 | /* On idle timeout clear activity flag and/or turn off clock */ | |
3625 | if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) { | |
3626 | if (++bus->idlecount >= bus->idletime) { | |
3627 | bus->idlecount = 0; | |
3628 | if (bus->activity) { | |
3629 | bus->activity = false; | |
82d7f3c1 | 3630 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); |
5b435de0 | 3631 | } else { |
4a3da990 | 3632 | brcmf_dbg(SDIO, "idle\n"); |
38b0b0dd | 3633 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 3634 | brcmf_sdio_bus_sleep(bus, true, false); |
38b0b0dd | 3635 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3636 | } |
3637 | } | |
3638 | } | |
3639 | ||
1d382273 | 3640 | return (atomic_read(&bus->ipend) > 0); |
5b435de0 AS |
3641 | } |
3642 | ||
f1e68c2e FL |
3643 | static void brcmf_sdio_dataworker(struct work_struct *work) |
3644 | { | |
3645 | struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, | |
3646 | datawork); | |
f1e68c2e | 3647 | |
fccfe930 | 3648 | while (atomic_read(&bus->dpc_tskcnt)) { |
71abdc00 | 3649 | atomic_set(&bus->dpc_tskcnt, 0); |
82d7f3c1 | 3650 | brcmf_sdio_dpc(bus); |
f1e68c2e | 3651 | } |
99824643 AS |
3652 | if (brcmf_sdiod_freezing(bus->sdiodev)) { |
3653 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); | |
3654 | brcmf_sdiod_try_freeze(bus->sdiodev); | |
3655 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); | |
3656 | } | |
f1e68c2e FL |
3657 | } |
3658 | ||
65d80d0b AS |
3659 | static void |
3660 | brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, | |
cb7cf7be | 3661 | struct brcmf_chip *ci, u32 drivestrength) |
65d80d0b AS |
3662 | { |
3663 | const struct sdiod_drive_str *str_tab = NULL; | |
3664 | u32 str_mask; | |
3665 | u32 str_shift; | |
cb7cf7be | 3666 | u32 base; |
65d80d0b AS |
3667 | u32 i; |
3668 | u32 drivestrength_sel = 0; | |
3669 | u32 cc_data_temp; | |
3670 | u32 addr; | |
3671 | ||
cb7cf7be | 3672 | if (!(ci->cc_caps & CC_CAP_PMU)) |
65d80d0b AS |
3673 | return; |
3674 | ||
3675 | switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { | |
5779ae6a | 3676 | case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): |
65d80d0b AS |
3677 | str_tab = sdiod_drvstr_tab1_1v8; |
3678 | str_mask = 0x00003800; | |
3679 | str_shift = 11; | |
3680 | break; | |
5779ae6a | 3681 | case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): |
65d80d0b AS |
3682 | str_tab = sdiod_drvstr_tab6_1v8; |
3683 | str_mask = 0x00001800; | |
3684 | str_shift = 11; | |
3685 | break; | |
5779ae6a | 3686 | case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): |
65d80d0b AS |
3687 | /* note: 43143 does not support tristate */ |
3688 | i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; | |
3689 | if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { | |
3690 | str_tab = sdiod_drvstr_tab2_3v3; | |
3691 | str_mask = 0x00000007; | |
3692 | str_shift = 0; | |
3693 | } else | |
3694 | brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", | |
cb7cf7be | 3695 | ci->name, drivestrength); |
65d80d0b | 3696 | break; |
5779ae6a | 3697 | case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): |
65d80d0b AS |
3698 | str_tab = sdiod_drive_strength_tab5_1v8; |
3699 | str_mask = 0x00003800; | |
3700 | str_shift = 11; | |
3701 | break; | |
3702 | default: | |
3703 | brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", | |
cb7cf7be | 3704 | ci->name, ci->chiprev, ci->pmurev); |
65d80d0b AS |
3705 | break; |
3706 | } | |
3707 | ||
3708 | if (str_tab != NULL) { | |
3709 | for (i = 0; str_tab[i].strength != 0; i++) { | |
3710 | if (drivestrength >= str_tab[i].strength) { | |
3711 | drivestrength_sel = str_tab[i].sel; | |
3712 | break; | |
3713 | } | |
3714 | } | |
cb7cf7be | 3715 | base = brcmf_chip_get_chipcommon(ci)->base; |
65d80d0b AS |
3716 | addr = CORE_CC_REG(base, chipcontrol_addr); |
3717 | brcmf_sdiod_regwl(sdiodev, addr, 1, NULL); | |
3718 | cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL); | |
3719 | cc_data_temp &= ~str_mask; | |
3720 | drivestrength_sel <<= str_shift; | |
3721 | cc_data_temp |= drivestrength_sel; | |
3722 | brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL); | |
3723 | ||
3724 | brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", | |
3725 | str_tab[i].strength, drivestrength, cc_data_temp); | |
3726 | } | |
3727 | } | |
3728 | ||
cb7cf7be | 3729 | static int brcmf_sdio_buscoreprep(void *ctx) |
65d80d0b | 3730 | { |
cb7cf7be | 3731 | struct brcmf_sdio_dev *sdiodev = ctx; |
65d80d0b AS |
3732 | int err = 0; |
3733 | u8 clkval, clkset; | |
3734 | ||
3735 | /* Try forcing SDIO core to do ALPAvail request only */ | |
3736 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; | |
3737 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
3738 | if (err) { | |
3739 | brcmf_err("error writing for HT off\n"); | |
3740 | return err; | |
3741 | } | |
3742 | ||
3743 | /* If register supported, wait for ALPAvail and then force ALP */ | |
3744 | /* This may take up to 15 milliseconds */ | |
3745 | clkval = brcmf_sdiod_regrb(sdiodev, | |
3746 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); | |
3747 | ||
3748 | if ((clkval & ~SBSDIO_AVBITS) != clkset) { | |
3749 | brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", | |
3750 | clkset, clkval); | |
3751 | return -EACCES; | |
3752 | } | |
3753 | ||
3754 | SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev, | |
3755 | SBSDIO_FUNC1_CHIPCLKCSR, NULL)), | |
3756 | !SBSDIO_ALPAV(clkval)), | |
3757 | PMU_MAX_TRANSITION_DLY); | |
3758 | if (!SBSDIO_ALPAV(clkval)) { | |
3759 | brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", | |
3760 | clkval); | |
3761 | return -EBUSY; | |
3762 | } | |
3763 | ||
3764 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; | |
3765 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
3766 | udelay(65); | |
3767 | ||
3768 | /* Also, disable the extra SDIO pull-ups */ | |
3769 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); | |
3770 | ||
3771 | return 0; | |
3772 | } | |
3773 | ||
cb7cf7be AS |
3774 | static void brcmf_sdio_buscore_exitdl(void *ctx, struct brcmf_chip *chip, |
3775 | u32 rstvec) | |
3776 | { | |
3777 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3778 | struct brcmf_core *core; | |
3779 | u32 reg_addr; | |
3780 | ||
3781 | /* clear all interrupts */ | |
3782 | core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV); | |
3783 | reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus); | |
3784 | brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL); | |
3785 | ||
3786 | if (rstvec) | |
3787 | /* Write reset vector to address 0 */ | |
3788 | brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, | |
3789 | sizeof(rstvec)); | |
3790 | } | |
3791 | ||
3792 | static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) | |
3793 | { | |
3794 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3795 | u32 val, rev; | |
3796 | ||
3797 | val = brcmf_sdiod_regrl(sdiodev, addr, NULL); | |
8bd61f8d | 3798 | if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 && |
cb7cf7be AS |
3799 | addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) { |
3800 | rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; | |
3801 | if (rev >= 2) { | |
3802 | val &= ~CID_ID_MASK; | |
5779ae6a | 3803 | val |= BRCM_CC_4339_CHIP_ID; |
cb7cf7be AS |
3804 | } |
3805 | } | |
3806 | return val; | |
3807 | } | |
3808 | ||
3809 | static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) | |
3810 | { | |
3811 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3812 | ||
3813 | brcmf_sdiod_regwl(sdiodev, addr, val, NULL); | |
3814 | } | |
3815 | ||
3816 | static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { | |
3817 | .prepare = brcmf_sdio_buscoreprep, | |
3818 | .exit_dl = brcmf_sdio_buscore_exitdl, | |
3819 | .read32 = brcmf_sdio_buscore_read32, | |
3820 | .write32 = brcmf_sdio_buscore_write32, | |
3821 | }; | |
3822 | ||
5b435de0 | 3823 | static bool |
82d7f3c1 | 3824 | brcmf_sdio_probe_attach(struct brcmf_sdio *bus) |
5b435de0 AS |
3825 | { |
3826 | u8 clkctl = 0; | |
3827 | int err = 0; | |
3828 | int reg_addr; | |
3829 | u32 reg_val; | |
668761ac | 3830 | u32 drivestrength; |
5b435de0 | 3831 | |
38b0b0dd FL |
3832 | sdio_claim_host(bus->sdiodev->func[1]); |
3833 | ||
18aad4f8 | 3834 | pr_debug("F1 signature read @0x18000000=0x%4x\n", |
a39be27b | 3835 | brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL)); |
5b435de0 AS |
3836 | |
3837 | /* | |
cb7cf7be | 3838 | * Force PLL off until brcmf_chip_attach() |
5b435de0 AS |
3839 | * programs PLL control regs |
3840 | */ | |
3841 | ||
a39be27b AS |
3842 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3843 | BRCMF_INIT_CLKCTL1, &err); | |
5b435de0 | 3844 | if (!err) |
a39be27b AS |
3845 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
3846 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 AS |
3847 | |
3848 | if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { | |
5e8149f5 | 3849 | brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", |
5b435de0 AS |
3850 | err, BRCMF_INIT_CLKCTL1, clkctl); |
3851 | goto fail; | |
3852 | } | |
3853 | ||
cb7cf7be AS |
3854 | bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops); |
3855 | if (IS_ERR(bus->ci)) { | |
3856 | brcmf_err("brcmf_chip_attach failed!\n"); | |
3857 | bus->ci = NULL; | |
5b435de0 AS |
3858 | goto fail; |
3859 | } | |
3860 | ||
82d7f3c1 | 3861 | if (brcmf_sdio_kso_init(bus)) { |
4a3da990 PH |
3862 | brcmf_err("error enabling KSO\n"); |
3863 | goto fail; | |
3864 | } | |
3865 | ||
668761ac HM |
3866 | if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength)) |
3867 | drivestrength = bus->sdiodev->pdata->drive_strength; | |
3868 | else | |
3869 | drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; | |
65d80d0b | 3870 | brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength); |
5b435de0 | 3871 | |
454d2a88 | 3872 | /* Get info on the SOCRAM cores... */ |
5b435de0 AS |
3873 | bus->ramsize = bus->ci->ramsize; |
3874 | if (!(bus->ramsize)) { | |
5e8149f5 | 3875 | brcmf_err("failed to find SOCRAM memory!\n"); |
5b435de0 AS |
3876 | goto fail; |
3877 | } | |
3878 | ||
1e9ab4dd | 3879 | /* Set card control so an SDIO card reset does a WLAN backplane reset */ |
a39be27b AS |
3880 | reg_val = brcmf_sdiod_regrb(bus->sdiodev, |
3881 | SDIO_CCCR_BRCM_CARDCTRL, &err); | |
1e9ab4dd PH |
3882 | if (err) |
3883 | goto fail; | |
3884 | ||
3885 | reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; | |
3886 | ||
a39be27b AS |
3887 | brcmf_sdiod_regwb(bus->sdiodev, |
3888 | SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); | |
1e9ab4dd PH |
3889 | if (err) |
3890 | goto fail; | |
3891 | ||
3892 | /* set PMUControl so a backplane reset does PMU state reload */ | |
cb7cf7be | 3893 | reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base, |
1e9ab4dd | 3894 | pmucontrol); |
cb7cf7be | 3895 | reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err); |
1e9ab4dd PH |
3896 | if (err) |
3897 | goto fail; | |
3898 | ||
3899 | reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); | |
3900 | ||
cb7cf7be | 3901 | brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err); |
1e9ab4dd PH |
3902 | if (err) |
3903 | goto fail; | |
3904 | ||
38b0b0dd FL |
3905 | sdio_release_host(bus->sdiodev->func[1]); |
3906 | ||
5b435de0 AS |
3907 | brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); |
3908 | ||
9b2d2f2a AS |
3909 | /* allocate header buffer */ |
3910 | bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); | |
3911 | if (!bus->hdrbuf) | |
3912 | return false; | |
5b435de0 AS |
3913 | /* Locate an appropriately-aligned portion of hdrbuf */ |
3914 | bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], | |
9b2d2f2a | 3915 | bus->head_align); |
5b435de0 AS |
3916 | |
3917 | /* Set the poll and/or interrupt flags */ | |
3918 | bus->intr = true; | |
3919 | bus->poll = false; | |
3920 | if (bus->poll) | |
3921 | bus->pollrate = 1; | |
3922 | ||
3923 | return true; | |
3924 | ||
3925 | fail: | |
38b0b0dd | 3926 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3927 | return false; |
3928 | } | |
3929 | ||
5b435de0 | 3930 | static int |
82d7f3c1 | 3931 | brcmf_sdio_watchdog_thread(void *data) |
5b435de0 | 3932 | { |
e92eedf4 | 3933 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
99824643 | 3934 | int wait; |
5b435de0 AS |
3935 | |
3936 | allow_signal(SIGTERM); | |
3937 | /* Run until signal received */ | |
99824643 | 3938 | brcmf_sdiod_freezer_count(bus->sdiodev); |
5b435de0 AS |
3939 | while (1) { |
3940 | if (kthread_should_stop()) | |
3941 | break; | |
99824643 AS |
3942 | brcmf_sdiod_freezer_uncount(bus->sdiodev); |
3943 | wait = wait_for_completion_interruptible(&bus->watchdog_wait); | |
3944 | brcmf_sdiod_freezer_count(bus->sdiodev); | |
3945 | brcmf_sdiod_try_freeze(bus->sdiodev); | |
3946 | if (!wait) { | |
82d7f3c1 | 3947 | brcmf_sdio_bus_watchdog(bus); |
5b435de0 | 3948 | /* Count the tick for reference */ |
80969836 | 3949 | bus->sdcnt.tickcnt++; |
58e9df46 | 3950 | reinit_completion(&bus->watchdog_wait); |
5b435de0 AS |
3951 | } else |
3952 | break; | |
3953 | } | |
3954 | return 0; | |
3955 | } | |
3956 | ||
3957 | static void | |
82d7f3c1 | 3958 | brcmf_sdio_watchdog(unsigned long data) |
5b435de0 | 3959 | { |
e92eedf4 | 3960 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3961 | |
3962 | if (bus->watchdog_tsk) { | |
3963 | complete(&bus->watchdog_wait); | |
3964 | /* Reschedule the watchdog */ | |
3965 | if (bus->wd_timer_valid) | |
3966 | mod_timer(&bus->timer, | |
187d3c33 | 3967 | jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS)); |
5b435de0 AS |
3968 | } |
3969 | } | |
3970 | ||
d9cb2596 | 3971 | static struct brcmf_bus_ops brcmf_sdio_bus_ops = { |
82d7f3c1 AS |
3972 | .stop = brcmf_sdio_bus_stop, |
3973 | .preinit = brcmf_sdio_bus_preinit, | |
82d7f3c1 AS |
3974 | .txdata = brcmf_sdio_bus_txdata, |
3975 | .txctl = brcmf_sdio_bus_txctl, | |
3976 | .rxctl = brcmf_sdio_bus_rxctl, | |
3977 | .gettxq = brcmf_sdio_bus_gettxq, | |
330b4e4b | 3978 | .wowl_config = brcmf_sdio_wowl_config |
d9cb2596 AS |
3979 | }; |
3980 | ||
bd0e1b1d AS |
3981 | static void brcmf_sdio_firmware_callback(struct device *dev, |
3982 | const struct firmware *code, | |
3983 | void *nvram, u32 nvram_len) | |
3984 | { | |
3985 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3986 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3987 | struct brcmf_sdio *bus = sdiodev->bus; | |
3988 | int err = 0; | |
3989 | u8 saveclk; | |
3990 | ||
3991 | brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev)); | |
3992 | ||
bd0e1b1d AS |
3993 | if (!bus_if->drvr) |
3994 | return; | |
3995 | ||
a1cee865 HM |
3996 | /* try to download image and nvram to the dongle */ |
3997 | bus->alp_only = true; | |
3998 | err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); | |
3999 | if (err) | |
4000 | goto fail; | |
4001 | bus->alp_only = false; | |
4002 | ||
bd0e1b1d AS |
4003 | /* Start the watchdog timer */ |
4004 | bus->sdcnt.tickcnt = 0; | |
4005 | brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); | |
4006 | ||
4007 | sdio_claim_host(sdiodev->func[1]); | |
4008 | ||
4009 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
4010 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
4011 | if (bus->clkstate != CLK_AVAIL) | |
4012 | goto release; | |
4013 | ||
4014 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
4015 | saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
4016 | if (!err) { | |
4017 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
4018 | (saveclk | SBSDIO_FORCE_HT), &err); | |
4019 | } | |
4020 | if (err) { | |
4021 | brcmf_err("Failed to force clock for F2: err %d\n", err); | |
4022 | goto release; | |
4023 | } | |
4024 | ||
4025 | /* Enable function 2 (frame transfers) */ | |
4026 | w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, | |
4027 | offsetof(struct sdpcmd_regs, tosbmailboxdata)); | |
4028 | err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]); | |
4029 | ||
4030 | ||
4031 | brcmf_dbg(INFO, "enable F2: err=%d\n", err); | |
4032 | ||
4033 | /* If F2 successfully enabled, set core and enable interrupts */ | |
4034 | if (!err) { | |
4035 | /* Set up the interrupt mask and enable interrupts */ | |
4036 | bus->hostintmask = HOSTINTMASK; | |
4037 | w_sdreg32(bus, bus->hostintmask, | |
4038 | offsetof(struct sdpcmd_regs, hostintmask)); | |
4039 | ||
4040 | brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err); | |
4041 | } else { | |
4042 | /* Disable F2 again */ | |
4043 | sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); | |
4044 | goto release; | |
4045 | } | |
4046 | ||
4047 | if (brcmf_chip_sr_capable(bus->ci)) { | |
4048 | brcmf_sdio_sr_init(bus); | |
4049 | } else { | |
4050 | /* Restore previous clock setting */ | |
4051 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
4052 | saveclk, &err); | |
4053 | } | |
4054 | ||
4055 | if (err == 0) { | |
4056 | err = brcmf_sdiod_intr_register(sdiodev); | |
4057 | if (err != 0) | |
4058 | brcmf_err("intr register failed:%d\n", err); | |
4059 | } | |
4060 | ||
4061 | /* If we didn't come up, turn off backplane clock */ | |
4062 | if (err != 0) | |
4063 | brcmf_sdio_clkctl(bus, CLK_NONE, false); | |
4064 | ||
4065 | sdio_release_host(sdiodev->func[1]); | |
4066 | ||
4067 | err = brcmf_bus_start(dev); | |
4068 | if (err != 0) { | |
4069 | brcmf_err("dongle is not responding\n"); | |
4070 | goto fail; | |
4071 | } | |
4072 | return; | |
4073 | ||
4074 | release: | |
4075 | sdio_release_host(sdiodev->func[1]); | |
4076 | fail: | |
4077 | brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); | |
4078 | device_release_driver(dev); | |
4079 | } | |
4080 | ||
82d7f3c1 | 4081 | struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) |
5b435de0 AS |
4082 | { |
4083 | int ret; | |
e92eedf4 | 4084 | struct brcmf_sdio *bus; |
99824643 | 4085 | struct workqueue_struct *wq; |
5b435de0 | 4086 | |
5b435de0 AS |
4087 | brcmf_dbg(TRACE, "Enter\n"); |
4088 | ||
5b435de0 | 4089 | /* Allocate private bus interface state */ |
e92eedf4 | 4090 | bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); |
5b435de0 AS |
4091 | if (!bus) |
4092 | goto fail; | |
4093 | ||
4094 | bus->sdiodev = sdiodev; | |
4095 | sdiodev->bus = bus; | |
b83db862 | 4096 | skb_queue_head_init(&bus->glom); |
5b435de0 AS |
4097 | bus->txbound = BRCMF_TXBOUND; |
4098 | bus->rxbound = BRCMF_RXBOUND; | |
4099 | bus->txminmax = BRCMF_TXMINMAX; | |
6bc52319 | 4100 | bus->tx_seq = SDPCM_SEQ_WRAP - 1; |
5b435de0 | 4101 | |
e217d1c8 AS |
4102 | /* platform specific configuration: |
4103 | * alignments must be at least 4 bytes for ADMA | |
888bf76e | 4104 | */ |
e217d1c8 AS |
4105 | bus->head_align = ALIGNMENT; |
4106 | bus->sgentry_align = ALIGNMENT; | |
4107 | if (sdiodev->pdata) { | |
4108 | if (sdiodev->pdata->sd_head_align > ALIGNMENT) | |
4109 | bus->head_align = sdiodev->pdata->sd_head_align; | |
4110 | if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT) | |
4111 | bus->sgentry_align = sdiodev->pdata->sd_sgentry_align; | |
4112 | } | |
4113 | ||
99824643 AS |
4114 | /* single-threaded workqueue */ |
4115 | wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM, | |
4116 | dev_name(&sdiodev->func[1]->dev)); | |
4117 | if (!wq) { | |
5e8149f5 | 4118 | brcmf_err("insufficient memory to create txworkqueue\n"); |
37ac5780 HM |
4119 | goto fail; |
4120 | } | |
99824643 AS |
4121 | brcmf_sdiod_freezer_count(sdiodev); |
4122 | INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); | |
4123 | bus->brcmf_wq = wq; | |
37ac5780 | 4124 | |
5b435de0 | 4125 | /* attempt to attach to the dongle */ |
82d7f3c1 AS |
4126 | if (!(brcmf_sdio_probe_attach(bus))) { |
4127 | brcmf_err("brcmf_sdio_probe_attach failed\n"); | |
5b435de0 AS |
4128 | goto fail; |
4129 | } | |
4130 | ||
dd43a01c | 4131 | spin_lock_init(&bus->rxctl_lock); |
fed7ec44 | 4132 | spin_lock_init(&bus->txq_lock); |
5b435de0 AS |
4133 | init_waitqueue_head(&bus->ctrl_wait); |
4134 | init_waitqueue_head(&bus->dcmd_resp_wait); | |
4135 | ||
4136 | /* Set up the watchdog timer */ | |
4137 | init_timer(&bus->timer); | |
4138 | bus->timer.data = (unsigned long)bus; | |
82d7f3c1 | 4139 | bus->timer.function = brcmf_sdio_watchdog; |
5b435de0 | 4140 | |
5b435de0 AS |
4141 | /* Initialize watchdog thread */ |
4142 | init_completion(&bus->watchdog_wait); | |
82d7f3c1 | 4143 | bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, |
99824643 AS |
4144 | bus, "brcmf_wdog/%s", |
4145 | dev_name(&sdiodev->func[1]->dev)); | |
5b435de0 | 4146 | if (IS_ERR(bus->watchdog_tsk)) { |
02f77195 | 4147 | pr_warn("brcmf_watchdog thread failed to start\n"); |
5b435de0 AS |
4148 | bus->watchdog_tsk = NULL; |
4149 | } | |
4150 | /* Initialize DPC thread */ | |
fccfe930 | 4151 | atomic_set(&bus->dpc_tskcnt, 0); |
5b435de0 | 4152 | |
a9ffda88 | 4153 | /* Assign bus interface call back */ |
d9cb2596 AS |
4154 | bus->sdiodev->bus_if->dev = bus->sdiodev->dev; |
4155 | bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops; | |
75d907d3 AS |
4156 | bus->sdiodev->bus_if->chip = bus->ci->chip; |
4157 | bus->sdiodev->bus_if->chiprev = bus->ci->chiprev; | |
d9cb2596 | 4158 | |
706478cb FL |
4159 | /* default sdio bus header length for tx packet */ |
4160 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
4161 | ||
4162 | /* Attach to the common layer, reserve hdr space */ | |
8dee77ba | 4163 | ret = brcmf_attach(bus->sdiodev->dev); |
712ac5b3 | 4164 | if (ret != 0) { |
5e8149f5 | 4165 | brcmf_err("brcmf_attach failed\n"); |
5b435de0 AS |
4166 | goto fail; |
4167 | } | |
4168 | ||
7dd3abc1 DK |
4169 | /* Query the F2 block size, set roundup accordingly */ |
4170 | bus->blocksize = bus->sdiodev->func[2]->cur_blksize; | |
4171 | bus->roundup = min(max_roundup, bus->blocksize); | |
4172 | ||
5b435de0 | 4173 | /* Allocate buffers */ |
fad13228 | 4174 | if (bus->sdiodev->bus_if->maxctl) { |
7dd3abc1 | 4175 | bus->sdiodev->bus_if->maxctl += bus->roundup; |
fad13228 AS |
4176 | bus->rxblen = |
4177 | roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), | |
4178 | ALIGNMENT) + bus->head_align; | |
4179 | bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); | |
4180 | if (!(bus->rxbuf)) { | |
4181 | brcmf_err("rxbuf allocation failed\n"); | |
4182 | goto fail; | |
4183 | } | |
5b435de0 AS |
4184 | } |
4185 | ||
fad13228 AS |
4186 | sdio_claim_host(bus->sdiodev->func[1]); |
4187 | ||
4188 | /* Disable F2 to clear any intermediate frame state on the dongle */ | |
4189 | sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]); | |
4190 | ||
fad13228 AS |
4191 | bus->rxflow = false; |
4192 | ||
4193 | /* Done with backplane-dependent accesses, can drop clock... */ | |
4194 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
4195 | ||
4196 | sdio_release_host(bus->sdiodev->func[1]); | |
4197 | ||
4198 | /* ...and initialize clock/power states */ | |
4199 | bus->clkstate = CLK_SDONLY; | |
4200 | bus->idletime = BRCMF_IDLE_INTERVAL; | |
4201 | bus->idleclock = BRCMF_IDLE_ACTIVE; | |
4202 | ||
fad13228 | 4203 | /* SR state */ |
fad13228 | 4204 | bus->sr_enabled = false; |
5b435de0 | 4205 | |
80969836 | 4206 | brcmf_sdio_debugfs_create(bus); |
5b435de0 AS |
4207 | brcmf_dbg(INFO, "completed!!\n"); |
4208 | ||
c1b20532 DK |
4209 | ret = brcmf_sdio_get_fwnames(bus->ci, sdiodev); |
4210 | if (ret) | |
4211 | goto fail; | |
4212 | ||
bd0e1b1d | 4213 | ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM, |
c1b20532 | 4214 | sdiodev->fw_name, sdiodev->nvram_name, |
bd0e1b1d | 4215 | brcmf_sdio_firmware_callback); |
5b435de0 | 4216 | if (ret != 0) { |
bd0e1b1d | 4217 | brcmf_err("async firmware request failed: %d\n", ret); |
1799ddf1 | 4218 | goto fail; |
5b435de0 | 4219 | } |
15d45b6f | 4220 | |
5b435de0 AS |
4221 | return bus; |
4222 | ||
4223 | fail: | |
9fbe2a6d | 4224 | brcmf_sdio_remove(bus); |
5b435de0 AS |
4225 | return NULL; |
4226 | } | |
4227 | ||
9fbe2a6d AS |
4228 | /* Detach and free everything */ |
4229 | void brcmf_sdio_remove(struct brcmf_sdio *bus) | |
5b435de0 | 4230 | { |
5b435de0 AS |
4231 | brcmf_dbg(TRACE, "Enter\n"); |
4232 | ||
9fbe2a6d AS |
4233 | if (bus) { |
4234 | /* De-register interrupt handler */ | |
4235 | brcmf_sdiod_intr_unregister(bus->sdiodev); | |
4236 | ||
4faf28b7 | 4237 | brcmf_detach(bus->sdiodev->dev); |
bfad4a04 | 4238 | |
e0c180ec HM |
4239 | cancel_work_sync(&bus->datawork); |
4240 | if (bus->brcmf_wq) | |
4241 | destroy_workqueue(bus->brcmf_wq); | |
4242 | ||
bfad4a04 | 4243 | if (bus->ci) { |
a1ce7a0d | 4244 | if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { |
bb350711 AS |
4245 | sdio_claim_host(bus->sdiodev->func[1]); |
4246 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
4247 | /* Leave the device in state where it is | |
4248 | * 'quiet'. This is done by putting it in | |
4249 | * download_state which essentially resets | |
4250 | * all necessary cores. | |
4251 | */ | |
4252 | msleep(20); | |
cb7cf7be | 4253 | brcmf_chip_enter_download(bus->ci); |
bb350711 AS |
4254 | brcmf_sdio_clkctl(bus, CLK_NONE, false); |
4255 | sdio_release_host(bus->sdiodev->func[1]); | |
4256 | } | |
cb7cf7be | 4257 | brcmf_chip_detach(bus->ci); |
9fbe2a6d AS |
4258 | } |
4259 | ||
bfad4a04 | 4260 | kfree(bus->rxbuf); |
9fbe2a6d AS |
4261 | kfree(bus->hdrbuf); |
4262 | kfree(bus); | |
4263 | } | |
5b435de0 AS |
4264 | |
4265 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4266 | } | |
4267 | ||
82d7f3c1 | 4268 | void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick) |
5b435de0 | 4269 | { |
5b435de0 | 4270 | /* Totally stop the timer */ |
23677ce3 | 4271 | if (!wdtick && bus->wd_timer_valid) { |
5b435de0 AS |
4272 | del_timer_sync(&bus->timer); |
4273 | bus->wd_timer_valid = false; | |
4274 | bus->save_ms = wdtick; | |
4275 | return; | |
4276 | } | |
4277 | ||
ece960ea | 4278 | /* don't start the wd until fw is loaded */ |
a1ce7a0d | 4279 | if (bus->sdiodev->state != BRCMF_SDIOD_DATA) |
ece960ea FL |
4280 | return; |
4281 | ||
5b435de0 AS |
4282 | if (wdtick) { |
4283 | if (bus->save_ms != BRCMF_WD_POLL_MS) { | |
23677ce3 | 4284 | if (bus->wd_timer_valid) |
5b435de0 AS |
4285 | /* Stop timer and restart at new value */ |
4286 | del_timer_sync(&bus->timer); | |
4287 | ||
4288 | /* Create timer again when watchdog period is | |
4289 | dynamically changed or in the first instance | |
4290 | */ | |
4291 | bus->timer.expires = | |
187d3c33 | 4292 | jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS); |
5b435de0 AS |
4293 | add_timer(&bus->timer); |
4294 | ||
4295 | } else { | |
4296 | /* Re arm the timer, at last watchdog period */ | |
4297 | mod_timer(&bus->timer, | |
187d3c33 | 4298 | jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS)); |
5b435de0 AS |
4299 | } |
4300 | ||
4301 | bus->wd_timer_valid = true; | |
4302 | bus->save_ms = wdtick; | |
4303 | } | |
4304 | } | |
99824643 AS |
4305 | |
4306 | int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) | |
4307 | { | |
4308 | int ret; | |
4309 | ||
4310 | sdio_claim_host(bus->sdiodev->func[1]); | |
4311 | ret = brcmf_sdio_bus_sleep(bus, sleep, false); | |
4312 | sdio_release_host(bus->sdiodev->func[1]); | |
4313 | ||
4314 | return ret; | |
4315 | } | |
4316 |