[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / brcm80211 / brcmfmac / sdio_host.h

/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	_BRCM_SDH_H_
#define	_BRCM_SDH_H_

#include <linux/skbuff.h>

#define SDIO_FUNC_0		0
#define SDIO_FUNC_1		1
#define SDIO_FUNC_2		2

#define SDIOD_FBR_SIZE		0x100

/* io_en */
#define SDIO_FUNC_ENABLE_1	0x02
#define SDIO_FUNC_ENABLE_2	0x04

/* io_rdys */
#define SDIO_FUNC_READY_1	0x02
#define SDIO_FUNC_READY_2	0x04

/* intr_status */
#define INTR_STATUS_FUNC1	0x2
#define INTR_STATUS_FUNC2	0x4

/* Maximum number of I/O funcs */
#define SDIOD_MAX_IOFUNCS	7

/* mask of register map */
#define REG_F0_REG_MASK		0x7FF
#define REG_F1_MISC_MASK	0x1FFFF

/* as of sdiod rev 0, supports 3 functions */
#define SBSDIO_NUM_FUNCTION		3

/* function 0 vendor specific CCCR registers */
#define SDIO_CCCR_BRCM_CARDCAP			0xf0
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT	0x02
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT	0x04
#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC	0x08
#define SDIO_CCCR_BRCM_CARDCTRL		0xf1
#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET	0x02
#define SDIO_CCCR_BRCM_SEPINT			0xf2

#define  SDIO_SEPINT_MASK		0x01
#define  SDIO_SEPINT_OE			0x02
#define  SDIO_SEPINT_ACT_HI		0x04

/* function 1 miscellaneous registers */

/* sprom command and status */
#define SBSDIO_SPROM_CS			0x10000
/* sprom info register */
#define SBSDIO_SPROM_INFO		0x10001
/* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_LOW		0x10002
/* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_DATA_HIGH		0x10003
/* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_LOW		0x10004
/* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_HIGH		0x10005
/* xtal_pu (gpio) output */
#define SBSDIO_CHIP_CTRL_DATA		0x10006
/* xtal_pu (gpio) enable */
#define SBSDIO_CHIP_CTRL_EN		0x10007
/* rev < 7, watermark for sdio device */
#define SBSDIO_WATERMARK		0x10008
/* control busy signal generation */
#define SBSDIO_DEVICE_CTL		0x10009

/* SB Address Window Low (b15) */
#define SBSDIO_FUNC1_SBADDRLOW		0x1000A
/* SB Address Window Mid (b23:b16) */
#define SBSDIO_FUNC1_SBADDRMID		0x1000B
/* SB Address Window High (b31:b24)    */
#define SBSDIO_FUNC1_SBADDRHIGH		0x1000C
/* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_FRAMECTRL		0x1000D
/* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_CHIPCLKCSR		0x1000E
/* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_SDIOPULLUP		0x1000F
/* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCLO		0x10019
/* Write Frame Byte Count High */
#define SBSDIO_FUNC1_WFRAMEBCHI		0x1001A
/* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCLO		0x1001B
/* Read Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCHI		0x1001C
/* MesBusyCtl (rev 11) */
#define SBSDIO_FUNC1_MESBUSYCTRL	0x1001D
/* Sdio Core Rev 12 */
#define SBSDIO_FUNC1_WAKEUPCTRL		0x1001E
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK		0x1
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT	0
#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK		0x2
#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT		1
#define SBSDIO_FUNC1_SLEEPCSR		0x1001F
#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK		0x1
#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT		0
#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN		1
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK	0x2
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT	1

#define SBSDIO_FUNC1_MISC_REG_START	0x10000	/* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT	0x1001F	/* f1 misc register end */

/* function 1 OCP space */

/* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_MASK		0x07FFF
#define SBSDIO_SB_OFT_ADDR_LIMIT	0x08000
/* with b15, maps to 32-bit SB access */
#define SBSDIO_SB_ACCESS_2_4B_FLAG	0x08000

/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */

#define SBSDIO_SBADDRLOW_MASK		0x80	/* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK		0xff	/* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK		0xffU	/* Valid bits in SBADDRHIGH */
/* Address bits from SBADDR regs */
#define SBSDIO_SBWINDOW_MASK		0xffff8000

#define SDIOH_READ              0	/* Read request */
#define SDIOH_WRITE             1	/* Write request */

#define SDIOH_DATA_FIX          0	/* Fixed addressing */
#define SDIOH_DATA_INC          1	/* Incremental addressing */

/* internal return code */
#define SUCCESS	0
#define ERROR	1

/* Packet alignment for most efficient SDIO (can change based on platform) */
#define BRCMF_SDALIGN	(1 << 6)

/* watchdog polling interval in ms */
#define BRCMF_WD_POLL_MS	10

struct brcmf_sdreg {
	int func;
	int offset;
	int value;
};

struct brcmf_sdio;

struct brcmf_sdio_dev {
	struct sdio_func *func[SDIO_MAX_FUNCS];
	u8 num_funcs;			/* Supported funcs on client */
	u32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
	u32 sbwad;			/* Save backplane window address */
	void *bus;
	atomic_t suspend;		/* suspend flag */
	wait_queue_head_t request_byte_wait;
	wait_queue_head_t request_word_wait;
	wait_queue_head_t request_buffer_wait;
	struct device *dev;
	struct brcmf_bus *bus_if;
	struct brcmfmac_sdio_platform_data *pdata;
	bool oob_irq_requested;
	bool irq_en;			/* irq enable flags */
	spinlock_t irq_en_lock;
	bool irq_wake;			/* irq wake enable flags */
	bool sg_support;
	uint max_request_size;
	ushort max_segment_count;
	uint max_segment_size;
};

/* Register/deregister interrupt handler. */
extern int brcmf_sdio_intr_register(struct brcmf_sdio_dev *sdiodev);
extern int brcmf_sdio_intr_unregister(struct brcmf_sdio_dev *sdiodev);

/* sdio device register access interface */
extern u8 brcmf_sdio_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
extern u32 brcmf_sdio_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
extern void brcmf_sdio_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr,
			     u8 data, int *ret);
extern void brcmf_sdio_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr,
			     u32 data, int *ret);
extern int brcmf_sdio_regrw_helper(struct brcmf_sdio_dev *sdiodev, u32 addr,
				   void *data, bool write);

/* Buffer transfer to/from device (client) core via cmd53.
 *   fn:       function number
 *   addr:     backplane address (i.e. >= regsva from attach)
 *   flags:    backplane width, address increment, sync/async
 *   buf:      pointer to memory data buffer
 *   nbytes:   number of bytes to transfer to/from buf
 *   pkt:      pointer to packet associated with buf (if any)
 *   complete: callback function for command completion (async only)
 *   handle:   handle for completion callback (first arg in callback)
 * Returns 0 or error code.
 * NOTE: Async operation is not currently supported.
 */
extern int
brcmf_sdcard_send_pkt(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
		      uint flags, struct sk_buff_head *pktq);
extern int
brcmf_sdcard_send_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
		      uint flags, u8 *buf, uint nbytes);

extern int
brcmf_sdcard_recv_pkt(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
		      uint flags, struct sk_buff *pkt);
extern int
brcmf_sdcard_recv_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
		      uint flags, u8 *buf, uint nbytes);
extern int
brcmf_sdcard_recv_chain(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
			uint flags, struct sk_buff_head *pktq);

/* Flags bits */

/* Four-byte target (backplane) width (vs. two-byte) */
#define SDIO_REQ_4BYTE	0x1
/* Fixed address (FIFO) (vs. incrementing address) */
#define SDIO_REQ_FIXED	0x2

/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
 *   rw:       read or write (0/1)
 *   addr:     direct SDIO address
 *   buf:      pointer to memory data buffer
 *   nbytes:   number of bytes to transfer to/from buf
 * Returns 0 or error code.
 */
extern int brcmf_sdcard_rwdata(struct brcmf_sdio_dev *sdiodev, uint rw,
			       u32 addr, u8 *buf, uint nbytes);
extern int brcmf_sdio_ramrw(struct brcmf_sdio_dev *sdiodev, bool write,
			    u32 address, u8 *data, uint size);

/* Issue an abort to the specified function */
extern int brcmf_sdcard_abort(struct brcmf_sdio_dev *sdiodev, uint fn);

/* platform specific/high level functions */
extern int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
extern int brcmf_sdio_remove(struct brcmf_sdio_dev *sdiodev);

/* attach, return handler on success, NULL if failed.
 *  The handler shall be provided by all subsequent calls. No local cache
 *  cfghdl points to the starting address of pci device mapped memory
 */
extern int brcmf_sdioh_attach(struct brcmf_sdio_dev *sdiodev);
extern void brcmf_sdioh_detach(struct brcmf_sdio_dev *sdiodev);

/* read or write one byte using cmd52 */
extern int brcmf_sdioh_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw,
				    uint fnc, uint addr, u8 *byte);

/* read or write 2/4 bytes using cmd53 */
extern int
brcmf_sdioh_request_word(struct brcmf_sdio_dev *sdiodev,
			 uint rw, uint fnc, uint addr,
			 u32 *word, uint nbyte);

/* Watchdog timer interface for pm ops */
extern void brcmf_sdio_wdtmr_enable(struct brcmf_sdio_dev *sdiodev,
				    bool enable);

extern void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev);
extern void brcmf_sdbrcm_disconnect(void *ptr);
extern void brcmf_sdbrcm_isr(void *arg);

extern void brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick);

extern void brcmf_pm_resume_wait(struct brcmf_sdio_dev *sdiodev,
				 wait_queue_head_t *wq);
extern bool brcmf_pm_resume_error(struct brcmf_sdio_dev *sdiodev);
#endif				/* _BRCM_SDH_H_ */
Commit	Line	Data
5b435de0 AS	1	/*
	2	* Copyright (c) 2010 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef _BRCM_SDH_H_
	18	#define _BRCM_SDH_H_
	19
	20	#include <linux/skbuff.h>
	21
	22	#define SDIO_FUNC_0 0
	23	#define SDIO_FUNC_1 1
	24	#define SDIO_FUNC_2 2
	25
	26	#define SDIOD_FBR_SIZE 0x100
	27
	28	/* io_en */
	29	#define SDIO_FUNC_ENABLE_1 0x02
	30	#define SDIO_FUNC_ENABLE_2 0x04
	31
	32	/* io_rdys */
	33	#define SDIO_FUNC_READY_1 0x02
	34	#define SDIO_FUNC_READY_2 0x04
	35
	36	/* intr_status */
	37	#define INTR_STATUS_FUNC1 0x2
	38	#define INTR_STATUS_FUNC2 0x4
	39
	40	/* Maximum number of I/O funcs */
	41	#define SDIOD_MAX_IOFUNCS 7
	42
e9b8d91d	43	/* mask of register map */
d8b3fc59	44	#define REG_F0_REG_MASK 0x7FF
e9b8d91d FL	45	#define REG_F1_MISC_MASK 0x1FFFF
e9b8d91d FL	46
5b435de0 AS	47	/* as of sdiod rev 0, supports 3 functions */
	48	#define SBSDIO_NUM_FUNCTION 3
	49
ba89bf19	50	/* function 0 vendor specific CCCR registers */
4a3da990 PH	51	#define SDIO_CCCR_BRCM_CARDCAP 0xf0
	52	#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
	53	#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
	54	#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
1e9ab4dd PH	55	#define SDIO_CCCR_BRCM_CARDCTRL 0xf1
1e9ab4dd PH	56	#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02
4a3da990	57	#define SDIO_CCCR_BRCM_SEPINT 0xf2
ba89bf19 FL	58
	59	#define SDIO_SEPINT_MASK 0x01
	60	#define SDIO_SEPINT_OE 0x02
	61	#define SDIO_SEPINT_ACT_HI 0x04
	62
5b435de0 AS	63	/* function 1 miscellaneous registers */
	64
	65	/* sprom command and status */
	66	#define SBSDIO_SPROM_CS 0x10000
	67	/* sprom info register */
	68	#define SBSDIO_SPROM_INFO 0x10001
	69	/* sprom indirect access data byte 0 */
	70	#define SBSDIO_SPROM_DATA_LOW 0x10002
	71	/* sprom indirect access data byte 1 */
	72	#define SBSDIO_SPROM_DATA_HIGH 0x10003
	73	/* sprom indirect access addr byte 0 */
	74	#define SBSDIO_SPROM_ADDR_LOW 0x10004
	75	/* sprom indirect access addr byte 0 */
	76	#define SBSDIO_SPROM_ADDR_HIGH 0x10005
	77	/* xtal_pu (gpio) output */
	78	#define SBSDIO_CHIP_CTRL_DATA 0x10006
	79	/* xtal_pu (gpio) enable */
	80	#define SBSDIO_CHIP_CTRL_EN 0x10007
	81	/* rev < 7, watermark for sdio device */
	82	#define SBSDIO_WATERMARK 0x10008
	83	/* control busy signal generation */
	84	#define SBSDIO_DEVICE_CTL 0x10009
	85
	86	/* SB Address Window Low (b15) */
	87	#define SBSDIO_FUNC1_SBADDRLOW 0x1000A
	88	/* SB Address Window Mid (b23:b16) */
	89	#define SBSDIO_FUNC1_SBADDRMID 0x1000B
	90	/* SB Address Window High (b31:b24) */
	91	#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
	92	/* Frame Control (frame term/abort) */
	93	#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
	94	/* ChipClockCSR (ALP/HT ctl/status) */
	95	#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
	96	/* SdioPullUp (on cmd, d0-d2) */
	97	#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
	98	/* Write Frame Byte Count Low */
	99	#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
	100	/* Write Frame Byte Count High */
	101	#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
	102	/* Read Frame Byte Count Low */
	103	#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
	104	/* Read Frame Byte Count High */
	105	#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
4a3da990 PH	106	/* MesBusyCtl (rev 11) */
	107	#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
	108	/* Sdio Core Rev 12 */
	109	#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
	110	#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
	111	#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
	112	#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
	113	#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
	114	#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
	115	#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
	116	#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
	117	#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
	118	#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
	119	#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
5b435de0 AS	120
5b435de0 AS	121	#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
4a3da990	122	#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
5b435de0 AS	123
	124	/* function 1 OCP space */
	125
	126	/* sb offset addr is <= 15 bits, 32k */
	127	#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
	128	#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
	129	/* with b15, maps to 32-bit SB access */
	130	#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
	131
	132	/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
	133
	134	#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
	135	#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
	136	#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
	137	/* Address bits from SBADDR regs */
	138	#define SBSDIO_SBWINDOW_MASK 0xffff8000
	139
	140	#define SDIOH_READ 0 /* Read request */
	141	#define SDIOH_WRITE 1 /* Write request */
	142
	143	#define SDIOH_DATA_FIX 0 /* Fixed addressing */
	144	#define SDIOH_DATA_INC 1 /* Incremental addressing */
	145
	146	/* internal return code */
	147	#define SUCCESS 0
	148	#define ERROR 1
	149
6e3c7128 FL	150	/* Packet alignment for most efficient SDIO (can change based on platform) */
	151	#define BRCMF_SDALIGN (1 << 6)
	152
	153	/* watchdog polling interval in ms */
	154	#define BRCMF_WD_POLL_MS 10
	155
5b435de0 AS	156	struct brcmf_sdreg {
	157	int func;
	158	int offset;
	159	int value;
	160	};
	161
2447ffb0 FL	162	struct brcmf_sdio;
2447ffb0 FL	163
5b435de0 AS	164	struct brcmf_sdio_dev {
	165	struct sdio_func *func[SDIO_MAX_FUNCS];
	166	u8 num_funcs; /* Supported funcs on client */
	167	u32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
	168	u32 sbwad; /* Save backplane window address */
5b435de0 AS	169	void *bus;
	170	atomic_t suspend; /* suspend flag */
	171	wait_queue_head_t request_byte_wait;
	172	wait_queue_head_t request_word_wait;
5b435de0	173	wait_queue_head_t request_buffer_wait;
655713be	174	struct device *dev;
d76d1c8c	175	struct brcmf_bus *bus_if;
668761ac HM	176	struct brcmfmac_sdio_platform_data *pdata;
668761ac HM	177	bool oob_irq_requested;
ba89bf19 FL	178	bool irq_en; /* irq enable flags */
	179	spinlock_t irq_en_lock;
	180	bool irq_wake; /* irq wake enable flags */
71201496 AS	181	bool sg_support;
	182	uint max_request_size;
	183	ushort max_segment_count;
	184	uint max_segment_size;
5b435de0 AS	185	};
5b435de0 AS	186
ba89bf19 FL	187	/* Register/deregister interrupt handler. */
	188	extern int brcmf_sdio_intr_register(struct brcmf_sdio_dev *sdiodev);
	189	extern int brcmf_sdio_intr_unregister(struct brcmf_sdio_dev *sdiodev);
5b435de0	190
e9b8d91d FL	191	/* sdio device register access interface */
	192	extern u8 brcmf_sdio_regrb(struct brcmf_sdio_dev sdiodev, u32 addr, int ret);
	193	extern u32 brcmf_sdio_regrl(struct brcmf_sdio_dev sdiodev, u32 addr, int ret);
	194	extern void brcmf_sdio_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr,
	195	u8 data, int *ret);
	196	extern void brcmf_sdio_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr,
	197	u32 data, int *ret);
4531603a FL	198	extern int brcmf_sdio_regrw_helper(struct brcmf_sdio_dev *sdiodev, u32 addr,
4531603a FL	199	void *data, bool write);
e9b8d91d	200
5b435de0 AS	201	/* Buffer transfer to/from device (client) core via cmd53.
	202	* fn: function number
	203	* addr: backplane address (i.e. >= regsva from attach)
	204	* flags: backplane width, address increment, sync/async
	205	* buf: pointer to memory data buffer
	206	* nbytes: number of bytes to transfer to/from buf
	207	* pkt: pointer to packet associated with buf (if any)
	208	* complete: callback function for command completion (async only)
	209	* handle: handle for completion callback (first arg in callback)
	210	* Returns 0 or error code.
	211	* NOTE: Async operation is not currently supported.
	212	*/
	213	extern int
5adfeb63	214	brcmf_sdcard_send_pkt(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
b05e9254	215	uint flags, struct sk_buff_head *pktq);
5adfeb63	216	extern int
5b435de0	217	brcmf_sdcard_send_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
5adfeb63 AS	218	uint flags, u8 *buf, uint nbytes);
	219
	220	extern int
	221	brcmf_sdcard_recv_pkt(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
	222	uint flags, struct sk_buff *pkt);
5b435de0 AS	223	extern int
5b435de0 AS	224	brcmf_sdcard_recv_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
5adfeb63 AS	225	uint flags, u8 *buf, uint nbytes);
	226	extern int
	227	brcmf_sdcard_recv_chain(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
	228	uint flags, struct sk_buff_head *pktq);
5b435de0 AS	229
	230	/* Flags bits */
	231
	232	/* Four-byte target (backplane) width (vs. two-byte) */
	233	#define SDIO_REQ_4BYTE 0x1
	234	/* Fixed address (FIFO) (vs. incrementing address) */
	235	#define SDIO_REQ_FIXED 0x2
5b435de0 AS	236
	237	/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
	238	* rw: read or write (0/1)
	239	* addr: direct SDIO address
	240	* buf: pointer to memory data buffer
	241	* nbytes: number of bytes to transfer to/from buf
	242	* Returns 0 or error code.
	243	*/
	244	extern int brcmf_sdcard_rwdata(struct brcmf_sdio_dev *sdiodev, uint rw,
	245	u32 addr, u8 *buf, uint nbytes);
ba540b01 FL	246	extern int brcmf_sdio_ramrw(struct brcmf_sdio_dev *sdiodev, bool write,
ba540b01 FL	247	u32 address, u8 *data, uint size);
5b435de0 AS	248
	249	/* Issue an abort to the specified function */
	250	extern int brcmf_sdcard_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
	251
	252	/* platform specific/high level functions */
	253	extern int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
	254	extern int brcmf_sdio_remove(struct brcmf_sdio_dev *sdiodev);
	255
5b435de0 AS	256	/* attach, return handler on success, NULL if failed.
	257	* The handler shall be provided by all subsequent calls. No local cache
	258	* cfghdl points to the starting address of pci device mapped memory
	259	*/
	260	extern int brcmf_sdioh_attach(struct brcmf_sdio_dev *sdiodev);
	261	extern void brcmf_sdioh_detach(struct brcmf_sdio_dev *sdiodev);
	262
	263	/* read or write one byte using cmd52 */
	264	extern int brcmf_sdioh_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw,
	265	uint fnc, uint addr, u8 *byte);
	266
	267	/* read or write 2/4 bytes using cmd53 */
	268	extern int
	269	brcmf_sdioh_request_word(struct brcmf_sdio_dev *sdiodev,
	270	uint rw, uint fnc, uint addr,
	271	u32 *word, uint nbyte);
	272
5b435de0 AS	273	/* Watchdog timer interface for pm ops */
	274	extern void brcmf_sdio_wdtmr_enable(struct brcmf_sdio_dev *sdiodev,
	275	bool enable);
	276
4175b88b	277	extern void brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev sdiodev);
5b435de0 AS	278	extern void brcmf_sdbrcm_disconnect(void *ptr);
5b435de0 AS	279	extern void brcmf_sdbrcm_isr(void *arg);
2447ffb0 FL	280
2447ffb0 FL	281	extern void brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick);
78b3f1c5 FL	282
	283	extern void brcmf_pm_resume_wait(struct brcmf_sdio_dev *sdiodev,
	284	wait_queue_head_t *wq);
	285	extern bool brcmf_pm_resume_error(struct brcmf_sdio_dev *sdiodev);
5b435de0	286	#endif /* _BRCM_SDH_H_ */