[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / brcm80211 / brcmsmac / pmu.c

/*
 * Copyright (c) 2011 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/delay.h>
#include <linux/io.h>

#include <brcm_hw_ids.h>
#include <chipcommon.h>
#include <brcmu_utils.h>
#include "pub.h"
#include "aiutils.h"
#include "pmu.h"
#include "soc.h"

/*
 * external LPO crystal frequency
 */
#define EXT_ILP_HZ 32768

/*
 * Duration for ILP clock frequency measurment in milliseconds
 *
 * remark: 1000 must be an integer multiple of this duration
 */
#define ILP_CALC_DUR	10

/* Fields in pmucontrol */
#define	PCTL_ILP_DIV_MASK	0xffff0000
#define	PCTL_ILP_DIV_SHIFT	16
#define PCTL_PLL_PLLCTL_UPD	0x00000400	/* rev 2 */
#define PCTL_NOILP_ON_WAIT	0x00000200	/* rev 1 */
#define	PCTL_HT_REQ_EN		0x00000100
#define	PCTL_ALP_REQ_EN		0x00000080
#define	PCTL_XTALFREQ_MASK	0x0000007c
#define	PCTL_XTALFREQ_SHIFT	2
#define	PCTL_ILP_DIV_EN		0x00000002
#define	PCTL_LPO_SEL		0x00000001

/* ILP clock */
#define	ILP_CLOCK		32000

/* ALP clock on pre-PMU chips */
#define	ALP_CLOCK		20000000

/* pmustatus */
#define PST_EXTLPOAVAIL	0x0100
#define PST_WDRESET	0x0080
#define	PST_INTPEND	0x0040
#define	PST_SBCLKST	0x0030
#define	PST_SBCLKST_ILP	0x0010
#define	PST_SBCLKST_ALP	0x0020
#define	PST_SBCLKST_HT	0x0030
#define	PST_ALPAVAIL	0x0008
#define	PST_HTAVAIL	0x0004
#define	PST_RESINIT	0x0003

/* PMU resource bit position */
#define PMURES_BIT(bit)	(1 << (bit))

/* PMU corerev and chip specific PLL controls.
 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
 * number to differentiate different PLLs controlled by the same PMU rev.
 */
/* pllcontrol registers:
 * ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>,
 * p1div, p2div, _bypass_sdmod
 */
#define PMU1_PLL0_PLLCTL0		0
#define PMU1_PLL0_PLLCTL1		1
#define PMU1_PLL0_PLLCTL2		2
#define PMU1_PLL0_PLLCTL3		3
#define PMU1_PLL0_PLLCTL4		4
#define PMU1_PLL0_PLLCTL5		5

/* pmu XtalFreqRatio */
#define	PMU_XTALFREQ_REG_ILPCTR_MASK	0x00001FFF
#define	PMU_XTALFREQ_REG_MEASURE_MASK	0x80000000
#define	PMU_XTALFREQ_REG_MEASURE_SHIFT	31

/* 4313 resources */
#define	RES4313_BB_PU_RSRC		0
#define	RES4313_ILP_REQ_RSRC		1
#define	RES4313_XTAL_PU_RSRC		2
#define	RES4313_ALP_AVAIL_RSRC		3
#define	RES4313_RADIO_PU_RSRC		4
#define	RES4313_BG_PU_RSRC		5
#define	RES4313_VREG1P4_PU_RSRC		6
#define	RES4313_AFE_PWRSW_RSRC		7
#define	RES4313_RX_PWRSW_RSRC		8
#define	RES4313_TX_PWRSW_RSRC		9
#define	RES4313_BB_PWRSW_RSRC		10
#define	RES4313_SYNTH_PWRSW_RSRC	11
#define	RES4313_MISC_PWRSW_RSRC		12
#define	RES4313_BB_PLL_PWRSW_RSRC	13
#define	RES4313_HT_AVAIL_RSRC		14
#define	RES4313_MACPHY_CLK_AVAIL_RSRC	15

/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
{
	u32 min_mask = 0, max_mask = 0;
	uint rsrcs;

	/* # resources */
	rsrcs = (ai_get_pmucaps(sih) & PCAP_RC_MASK) >> PCAP_RC_SHIFT;

	/* determine min/max rsrc masks */
	switch (ai_get_chip_id(sih)) {
	case BCM43224_CHIP_ID:
	case BCM43225_CHIP_ID:
		/* ??? */
		break;

	case BCM4313_CHIP_ID:
		min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
		    PMURES_BIT(RES4313_XTAL_PU_RSRC) |
		    PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
		    PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
		max_mask = 0xffff;
		break;
	default:
		break;
	}

	*pmin = min_mask;
	*pmax = max_mask;
}

static void
si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct bcma_device *core,
			   u8 spuravoid)
{
	u32 tmp = 0;

	switch (ai_get_chip_id(sih)) {
	case BCM43224_CHIP_ID:
	case BCM43225_CHIP_ID:
		if (spuravoid == 1) {
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL0);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x11500010);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL1);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x000C0C06);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL2);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x0F600a08);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL3);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x00000000);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL4);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x2001E920);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL5);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x88888815);
		} else {
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL0);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x11100010);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL1);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x000c0c06);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL2);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x03000a08);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL3);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x00000000);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL4);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x200005c0);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
				     PMU1_PLL0_PLLCTL5);
			bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
				     0x88888815);
		}
		tmp = 1 << 10;
		break;

	default:
		/* bail out */
		return;
	}

	bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp);
}

u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
{
	uint delay = PMU_MAX_TRANSITION_DLY;

	switch (ai_get_chip_id(sih)) {
	case BCM43224_CHIP_ID:
	case BCM43225_CHIP_ID:
	case BCM4313_CHIP_ID:
		delay = 3700;
		break;
	default:
		break;
	}

	return (u16) delay;
}

void si_pmu_sprom_enable(struct si_pub *sih, bool enable)
{
	struct chipcregs __iomem *cc;
	uint origidx;

	/* Remember original core before switch to chipc */
	origidx = ai_coreidx(sih);
	cc = ai_setcoreidx(sih, SI_CC_IDX);

	/* Return to original core */
	ai_setcoreidx(sih, origidx);
}

/* Read/write a chipcontrol reg */
u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
	ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_addr), ~0, reg);
	return ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_data),
			 mask, val);
}

/* Read/write a regcontrol reg */
u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
	ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_addr), ~0, reg);
	return ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_data),
			 mask, val);
}

/* Read/write a pllcontrol reg */
u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
	ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_addr), ~0, reg);
	return ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_data),
			 mask, val);
}

/* PMU PLL update */
void si_pmu_pllupd(struct si_pub *sih)
{
	ai_cc_reg(sih, offsetof(struct chipcregs, pmucontrol),
		  PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
}

/* query alp/xtal clock frequency */
u32 si_pmu_alp_clock(struct si_pub *sih)
{
	u32 clock = ALP_CLOCK;

	/* bail out with default */
	if (!(ai_get_cccaps(sih) & CC_CAP_PMU))
		return clock;

	switch (ai_get_chip_id(sih)) {
	case BCM43224_CHIP_ID:
	case BCM43225_CHIP_ID:
	case BCM4313_CHIP_ID:
		/* always 20Mhz */
		clock = 20000 * 1000;
		break;
	default:
		break;
	}

	return clock;
}

void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
{
	struct bcma_device *cc;
	uint origidx, intr_val;

	/* switch to chipc */
	cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
	ai_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);

	/* update the pll changes */
	si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);

	/* Return to original core */
	ai_restore_core(sih, origidx, intr_val);
}

/* initialize PMU */
void si_pmu_init(struct si_pub *sih)
{
	struct bcma_device *core;

	/* select chipc */
	core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);

	if (ai_get_pmurev(sih) == 1)
		bcma_mask32(core, CHIPCREGOFFS(pmucontrol),
			    ~PCTL_NOILP_ON_WAIT);
	else if (ai_get_pmurev(sih) >= 2)
		bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT);
}

/* initialize PMU chip controls and other chip level stuff */
void si_pmu_chip_init(struct si_pub *sih)
{
	uint origidx;

	/* Gate off SPROM clock and chip select signals */
	si_pmu_sprom_enable(sih, false);

	/* Remember original core */
	origidx = ai_coreidx(sih);

	/* Return to original core */
	ai_setcoreidx(sih, origidx);
}

/* initialize PMU switch/regulators */
void si_pmu_swreg_init(struct si_pub *sih)
{
}

/* initialize PLL */
void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
{
	struct chipcregs __iomem *cc;
	uint origidx;

	/* Remember original core before switch to chipc */
	origidx = ai_coreidx(sih);
	cc = ai_setcoreidx(sih, SI_CC_IDX);

	switch (ai_get_chip_id(sih)) {
	case BCM4313_CHIP_ID:
	case BCM43224_CHIP_ID:
	case BCM43225_CHIP_ID:
		/* ??? */
		break;
	default:
		break;
	}

	/* Return to original core */
	ai_setcoreidx(sih, origidx);
}

/* initialize PMU resources */
void si_pmu_res_init(struct si_pub *sih)
{
	struct bcma_device *core;
	u32 min_mask = 0, max_mask = 0;

	/* select to chipc */
	core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);

	/* Determine min/max rsrc masks */
	si_pmu_res_masks(sih, &min_mask, &max_mask);

	/* It is required to program max_mask first and then min_mask */

	/* Program max resource mask */

	if (max_mask)
		bcma_write32(core, CHIPCREGOFFS(max_res_mask), max_mask);

	/* Program min resource mask */

	if (min_mask)
		bcma_write32(core, CHIPCREGOFFS(min_res_mask), min_mask);

	/* Add some delay; allow resources to come up and settle. */
	mdelay(2);
}

u32 si_pmu_measure_alpclk(struct si_pub *sih)
{
	struct bcma_device *core;
	u32 alp_khz;

	if (ai_get_pmurev(sih) < 10)
		return 0;

	/* Remember original core before switch to chipc */
	core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);

	if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
		u32 ilp_ctr, alp_hz;

		/*
		 * Enable the reg to measure the freq,
		 * in case it was disabled before
		 */
		bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
			    1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);

		/* Delay for well over 4 ILP clocks */
		udelay(1000);

		/* Read the latched number of ALP ticks per 4 ILP ticks */
		ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
			  PMU_XTALFREQ_REG_ILPCTR_MASK;

		/*
		 * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
		 * bit to save power
		 */
		bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);

		/* Calculate ALP frequency */
		alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;

		/*
		 * Round to nearest 100KHz, and at
		 * the same time convert to KHz
		 */
		alp_khz = (alp_hz + 50000) / 100000 * 100;
	} else
		alp_khz = 0;

	return alp_khz;
}
Commit	Line	Data
5b435de0 AS	1	/*
	2	* Copyright (c) 2011 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/delay.h>
	18	#include <linux/io.h>
	19
	20	#include <brcm_hw_ids.h>
	21	#include <chipcommon.h>
	22	#include <brcmu_utils.h>
	23	#include "pub.h"
	24	#include "aiutils.h"
	25	#include "pmu.h"
23038214	26	#include "soc.h"
5b435de0 AS	27
	28	/*
	29	* external LPO crystal frequency
	30	*/
	31	#define EXT_ILP_HZ 32768
	32
	33	/*
	34	* Duration for ILP clock frequency measurment in milliseconds
	35	*
	36	* remark: 1000 must be an integer multiple of this duration
	37	*/
	38	#define ILP_CALC_DUR 10
	39
	40	/* Fields in pmucontrol */
	41	#define PCTL_ILP_DIV_MASK 0xffff0000
	42	#define PCTL_ILP_DIV_SHIFT 16
	43	#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
	44	#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
	45	#define PCTL_HT_REQ_EN 0x00000100
	46	#define PCTL_ALP_REQ_EN 0x00000080
	47	#define PCTL_XTALFREQ_MASK 0x0000007c
	48	#define PCTL_XTALFREQ_SHIFT 2
	49	#define PCTL_ILP_DIV_EN 0x00000002
	50	#define PCTL_LPO_SEL 0x00000001
	51
	52	/* ILP clock */
	53	#define ILP_CLOCK 32000
	54
	55	/* ALP clock on pre-PMU chips */
	56	#define ALP_CLOCK 20000000
	57
	58	/* pmustatus */
	59	#define PST_EXTLPOAVAIL 0x0100
	60	#define PST_WDRESET 0x0080
	61	#define PST_INTPEND 0x0040
	62	#define PST_SBCLKST 0x0030
	63	#define PST_SBCLKST_ILP 0x0010
	64	#define PST_SBCLKST_ALP 0x0020
	65	#define PST_SBCLKST_HT 0x0030
	66	#define PST_ALPAVAIL 0x0008
	67	#define PST_HTAVAIL 0x0004
	68	#define PST_RESINIT 0x0003
	69
	70	/* PMU resource bit position */
	71	#define PMURES_BIT(bit) (1 << (bit))
	72
	73	/* PMU corerev and chip specific PLL controls.
	74	* PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
	75	* number to differentiate different PLLs controlled by the same PMU rev.
	76	*/
	77	/* pllcontrol registers:
	78	* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>,
	79	* p1div, p2div, _bypass_sdmod
	80	*/
	81	#define PMU1_PLL0_PLLCTL0 0
	82	#define PMU1_PLL0_PLLCTL1 1
	83	#define PMU1_PLL0_PLLCTL2 2
	84	#define PMU1_PLL0_PLLCTL3 3
	85	#define PMU1_PLL0_PLLCTL4 4
	86	#define PMU1_PLL0_PLLCTL5 5
	87
	88	/* pmu XtalFreqRatio */
	89	#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
	90	#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
91	#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
92
93	/* 4313 resources */
94	#define RES4313_BB_PU_RSRC 0
95	#define RES4313_ILP_REQ_RSRC 1
96	#define RES4313_XTAL_PU_RSRC 2
97	#define RES4313_ALP_AVAIL_RSRC 3
98	#define RES4313_RADIO_PU_RSRC 4
99	#define RES4313_BG_PU_RSRC 5
100	#define RES4313_VREG1P4_PU_RSRC 6
101	#define RES4313_AFE_PWRSW_RSRC 7
102	#define RES4313_RX_PWRSW_RSRC 8
103	#define RES4313_TX_PWRSW_RSRC 9
104	#define RES4313_BB_PWRSW_RSRC 10
105	#define RES4313_SYNTH_PWRSW_RSRC 11
106	#define RES4313_MISC_PWRSW_RSRC 12
107	#define RES4313_BB_PLL_PWRSW_RSRC 13
108	#define RES4313_HT_AVAIL_RSRC 14
109	#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
110
111	/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
112	static void si_pmu_res_masks(struct si_pub sih, u32 pmin, u32 * pmax)
113	{
114	u32 min_mask = 0, max_mask = 0;
115	uint rsrcs;
116
117	/* # resources */
b2ffec46	118	rsrcs = (ai_get_pmucaps(sih) & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
5b435de0 AS	119
5b435de0 AS	120	/* determine min/max rsrc masks */
b2ffec46	121	switch (ai_get_chip_id(sih)) {
5b435de0 AS	122	case BCM43224_CHIP_ID:
	123	case BCM43225_CHIP_ID:
	124	/* ??? */
	125	break;
	126
	127	case BCM4313_CHIP_ID:
	128	min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) \|
	129	PMURES_BIT(RES4313_XTAL_PU_RSRC) \|
	130	PMURES_BIT(RES4313_ALP_AVAIL_RSRC) \|
	131	PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
	132	max_mask = 0xffff;
	133	break;
	134	default:
	135	break;
	136	}
	137
	138	*pmin = min_mask;
	139	*pmax = max_mask;
	140	}
	141
	142	static void
8d30b708	143	si_pmu_spuravoid_pllupdate(struct si_pub sih, struct bcma_device core,
5b435de0 AS	144	u8 spuravoid)
	145	{
	146	u32 tmp = 0;
	147
b2ffec46	148	switch (ai_get_chip_id(sih)) {
5b435de0 AS	149	case BCM43224_CHIP_ID:
	150	case BCM43225_CHIP_ID:
	151	if (spuravoid == 1) {
8d30b708 AS	152	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	153	PMU1_PLL0_PLLCTL0);
	154	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	155	0x11500010);
	156	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	157	PMU1_PLL0_PLLCTL1);
	158	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	159	0x000C0C06);
	160	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	161	PMU1_PLL0_PLLCTL2);
	162	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	163	0x0F600a08);
	164	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	165	PMU1_PLL0_PLLCTL3);
	166	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	167	0x00000000);
	168	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	169	PMU1_PLL0_PLLCTL4);
	170	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	171	0x2001E920);
	172	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	173	PMU1_PLL0_PLLCTL5);
	174	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	175	0x88888815);
5b435de0	176	} else {
8d30b708 AS	177	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	178	PMU1_PLL0_PLLCTL0);
	179	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	180	0x11100010);
	181	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	182	PMU1_PLL0_PLLCTL1);
	183	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	184	0x000c0c06);
	185	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	186	PMU1_PLL0_PLLCTL2);
	187	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	188	0x03000a08);
	189	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	190	PMU1_PLL0_PLLCTL3);
	191	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	192	0x00000000);
	193	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	194	PMU1_PLL0_PLLCTL4);
	195	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	196	0x200005c0);
	197	bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
	198	PMU1_PLL0_PLLCTL5);
	199	bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
	200	0x88888815);
5b435de0 AS	201	}
	202	tmp = 1 << 10;
	203	break;
	204
5b435de0 AS	205	default:
	206	/* bail out */
	207	return;
	208	}
	209
8d30b708	210	bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp);
5b435de0 AS	211	}
	212
	213	u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
	214	{
	215	uint delay = PMU_MAX_TRANSITION_DLY;
	216
b2ffec46	217	switch (ai_get_chip_id(sih)) {
5b435de0 AS	218	case BCM43224_CHIP_ID:
	219	case BCM43225_CHIP_ID:
	220	case BCM4313_CHIP_ID:
	221	delay = 3700;
	222	break;
	223	default:
	224	break;
	225	}
	226
	227	return (u16) delay;
	228	}
	229
	230	void si_pmu_sprom_enable(struct si_pub *sih, bool enable)
	231	{
	232	struct chipcregs __iomem *cc;
	233	uint origidx;
	234
	235	/* Remember original core before switch to chipc */
	236	origidx = ai_coreidx(sih);
	237	cc = ai_setcoreidx(sih, SI_CC_IDX);
	238
	239	/* Return to original core */
	240	ai_setcoreidx(sih, origidx);
	241	}
	242
	243	/* Read/write a chipcontrol reg */
	244	u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
	245	{
7d8e18e4 AS	246	ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_addr), ~0, reg);
	247	return ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_data),
	248	mask, val);
5b435de0 AS	249	}
	250
	251	/* Read/write a regcontrol reg */
	252	u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
	253	{
7d8e18e4 AS	254	ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_addr), ~0, reg);
	255	return ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_data),
	256	mask, val);
5b435de0 AS	257	}
	258
	259	/* Read/write a pllcontrol reg */
	260	u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
	261	{
7d8e18e4 AS	262	ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_addr), ~0, reg);
	263	return ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_data),
	264	mask, val);
5b435de0 AS	265	}
	266
	267	/* PMU PLL update */
	268	void si_pmu_pllupd(struct si_pub *sih)
	269	{
7d8e18e4 AS	270	ai_cc_reg(sih, offsetof(struct chipcregs, pmucontrol),
7d8e18e4 AS	271	PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
5b435de0 AS	272	}
	273
	274	/* query alp/xtal clock frequency */
	275	u32 si_pmu_alp_clock(struct si_pub *sih)
	276	{
	277	u32 clock = ALP_CLOCK;
	278
	279	/* bail out with default */
b2ffec46	280	if (!(ai_get_cccaps(sih) & CC_CAP_PMU))
5b435de0 AS	281	return clock;
5b435de0 AS	282
b2ffec46	283	switch (ai_get_chip_id(sih)) {
5b435de0 AS	284	case BCM43224_CHIP_ID:
	285	case BCM43225_CHIP_ID:
	286	case BCM4313_CHIP_ID:
	287	/* always 20Mhz */
	288	clock = 20000 * 1000;
	289	break;
	290	default:
	291	break;
	292	}
	293
	294	return clock;
	295	}
	296
	297	void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
	298	{
8d30b708	299	struct bcma_device *cc;
5b435de0 AS	300	uint origidx, intr_val;
5b435de0 AS	301
8d30b708 AS	302	/* switch to chipc */
	303	cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
	304	ai_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
5b435de0 AS	305
	306	/* update the pll changes */
	307	si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
	308
	309	/* Return to original core */
	310	ai_restore_core(sih, origidx, intr_val);
	311	}
	312
	313	/* initialize PMU */
	314	void si_pmu_init(struct si_pub *sih)
	315	{
8d30b708	316	struct bcma_device *core;
5b435de0	317
8d30b708 AS	318	/* select chipc */
8d30b708 AS	319	core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
5b435de0	320
b2ffec46	321	if (ai_get_pmurev(sih) == 1)
8d30b708 AS	322	bcma_mask32(core, CHIPCREGOFFS(pmucontrol),
8d30b708 AS	323	~PCTL_NOILP_ON_WAIT);
b2ffec46	324	else if (ai_get_pmurev(sih) >= 2)
8d30b708	325	bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT);
5b435de0 AS	326	}
	327
	328	/* initialize PMU chip controls and other chip level stuff */
	329	void si_pmu_chip_init(struct si_pub *sih)
	330	{
	331	uint origidx;
	332
	333	/* Gate off SPROM clock and chip select signals */
	334	si_pmu_sprom_enable(sih, false);
	335
	336	/* Remember original core */
	337	origidx = ai_coreidx(sih);
	338
	339	/* Return to original core */
	340	ai_setcoreidx(sih, origidx);
	341	}
	342
	343	/* initialize PMU switch/regulators */
	344	void si_pmu_swreg_init(struct si_pub *sih)
	345	{
	346	}
	347
	348	/* initialize PLL */
	349	void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
	350	{
	351	struct chipcregs __iomem *cc;
	352	uint origidx;
	353
	354	/* Remember original core before switch to chipc */
	355	origidx = ai_coreidx(sih);
	356	cc = ai_setcoreidx(sih, SI_CC_IDX);
	357
b2ffec46	358	switch (ai_get_chip_id(sih)) {
5b435de0 AS	359	case BCM4313_CHIP_ID:
	360	case BCM43224_CHIP_ID:
	361	case BCM43225_CHIP_ID:
	362	/* ??? */
	363	break;
	364	default:
	365	break;
	366	}
	367
	368	/* Return to original core */
	369	ai_setcoreidx(sih, origidx);
	370	}
	371
	372	/* initialize PMU resources */
	373	void si_pmu_res_init(struct si_pub *sih)
	374	{
8d30b708	375	struct bcma_device *core;
5b435de0 AS	376	u32 min_mask = 0, max_mask = 0;
5b435de0 AS	377
8d30b708 AS	378	/* select to chipc */
8d30b708 AS	379	core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
5b435de0 AS	380
	381	/* Determine min/max rsrc masks */
	382	si_pmu_res_masks(sih, &min_mask, &max_mask);
	383
	384	/* It is required to program max_mask first and then min_mask */
	385
	386	/* Program max resource mask */
	387
	388	if (max_mask)
8d30b708	389	bcma_write32(core, CHIPCREGOFFS(max_res_mask), max_mask);
5b435de0 AS	390
	391	/* Program min resource mask */
	392
	393	if (min_mask)
8d30b708	394	bcma_write32(core, CHIPCREGOFFS(min_res_mask), min_mask);
5b435de0 AS	395
	396	/* Add some delay; allow resources to come up and settle. */
	397	mdelay(2);
5b435de0 AS	398	}
	399
	400	u32 si_pmu_measure_alpclk(struct si_pub *sih)
	401	{
8d30b708	402	struct bcma_device *core;
5b435de0 AS	403	u32 alp_khz;
5b435de0 AS	404
b2ffec46	405	if (ai_get_pmurev(sih) < 10)
5b435de0 AS	406	return 0;
	407
	408	/* Remember original core before switch to chipc */
8d30b708	409	core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
5b435de0	410
8d30b708	411	if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
5b435de0 AS	412	u32 ilp_ctr, alp_hz;
	413
	414	/*
	415	* Enable the reg to measure the freq,
	416	* in case it was disabled before
	417	*/
8d30b708 AS	418	bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
8d30b708 AS	419	1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
5b435de0 AS	420
	421	/* Delay for well over 4 ILP clocks */
	422	udelay(1000);
	423
	424	/* Read the latched number of ALP ticks per 4 ILP ticks */
8d30b708 AS	425	ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
8d30b708 AS	426	PMU_XTALFREQ_REG_ILPCTR_MASK;
5b435de0 AS	427
	428	/*
	429	* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
	430	* bit to save power
	431	*/
8d30b708	432	bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);
5b435de0 AS	433
	434	/* Calculate ALP frequency */
	435	alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
	436
	437	/*
	438	* Round to nearest 100KHz, and at
	439	* the same time convert to KHz
	440	*/
	441	alp_khz = (alp_hz + 50000) / 100000 * 100;
	442	} else
	443	alp_khz = 0;
	444
5b435de0 AS	445	return alp_khz;
5b435de0 AS	446	}