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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
a32be017 | 18 | #include <linux/atomic.h> |
5b435de0 AS |
19 | #include <linux/kernel.h> |
20 | #include <linux/kthread.h> | |
21 | #include <linux/printk.h> | |
22 | #include <linux/pci_ids.h> | |
23 | #include <linux/netdevice.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/mmc/sdio.h> | |
cb7cf7be | 27 | #include <linux/mmc/sdio_ids.h> |
5b435de0 AS |
28 | #include <linux/mmc/sdio_func.h> |
29 | #include <linux/mmc/card.h> | |
30 | #include <linux/semaphore.h> | |
31 | #include <linux/firmware.h> | |
b7a57e76 | 32 | #include <linux/module.h> |
99ba15cd | 33 | #include <linux/bcma/bcma.h> |
4fc0d016 | 34 | #include <linux/debugfs.h> |
8dc01811 | 35 | #include <linux/vmalloc.h> |
5b435de0 AS |
36 | #include <asm/unaligned.h> |
37 | #include <defs.h> | |
38 | #include <brcmu_wifi.h> | |
39 | #include <brcmu_utils.h> | |
40 | #include <brcm_hw_ids.h> | |
41 | #include <soc.h> | |
888bf76e | 42 | #include "sdio.h" |
20c9c9bc | 43 | #include "chip.h" |
dabedab9 | 44 | #include "firmware.h" |
4d792895 HM |
45 | #include "core.h" |
46 | #include "common.h" | |
5b435de0 | 47 | |
97f1a171 SS |
48 | #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500) |
49 | #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500) | |
5b435de0 | 50 | |
8ae74654 | 51 | #ifdef DEBUG |
5b435de0 AS |
52 | |
53 | #define BRCMF_TRAP_INFO_SIZE 80 | |
54 | ||
55 | #define CBUF_LEN (128) | |
56 | ||
4fc0d016 AS |
57 | /* Device console log buffer state */ |
58 | #define CONSOLE_BUFFER_MAX 2024 | |
59 | ||
5b435de0 AS |
60 | struct rte_log_le { |
61 | __le32 buf; /* Can't be pointer on (64-bit) hosts */ | |
62 | __le32 buf_size; | |
63 | __le32 idx; | |
64 | char *_buf_compat; /* Redundant pointer for backward compat. */ | |
65 | }; | |
66 | ||
67 | struct rte_console { | |
68 | /* Virtual UART | |
69 | * When there is no UART (e.g. Quickturn), | |
70 | * the host should write a complete | |
71 | * input line directly into cbuf and then write | |
72 | * the length into vcons_in. | |
73 | * This may also be used when there is a real UART | |
74 | * (at risk of conflicting with | |
75 | * the real UART). vcons_out is currently unused. | |
76 | */ | |
77 | uint vcons_in; | |
78 | uint vcons_out; | |
79 | ||
80 | /* Output (logging) buffer | |
81 | * Console output is written to a ring buffer log_buf at index log_idx. | |
82 | * The host may read the output when it sees log_idx advance. | |
83 | * Output will be lost if the output wraps around faster than the host | |
84 | * polls. | |
85 | */ | |
86 | struct rte_log_le log_le; | |
87 | ||
88 | /* Console input line buffer | |
89 | * Characters are read one at a time into cbuf | |
90 | * until <CR> is received, then | |
91 | * the buffer is processed as a command line. | |
92 | * Also used for virtual UART. | |
93 | */ | |
94 | uint cbuf_idx; | |
95 | char cbuf[CBUF_LEN]; | |
96 | }; | |
97 | ||
8ae74654 | 98 | #endif /* DEBUG */ |
5b435de0 AS |
99 | #include <chipcommon.h> |
100 | ||
d14f78b9 | 101 | #include "bus.h" |
a8e8ed34 | 102 | #include "debug.h" |
40c1c249 | 103 | #include "tracepoint.h" |
5b435de0 AS |
104 | |
105 | #define TXQLEN 2048 /* bulk tx queue length */ | |
106 | #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ | |
107 | #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ | |
108 | #define PRIOMASK 7 | |
109 | ||
110 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
111 | ||
112 | #define BRCMF_RXBOUND 50 /* Default for max rx frames in | |
113 | one scheduling */ | |
114 | ||
115 | #define BRCMF_TXBOUND 20 /* Default for max tx frames in | |
116 | one scheduling */ | |
117 | ||
118 | #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ | |
119 | ||
120 | #define MEMBLOCK 2048 /* Block size used for downloading | |
121 | of dongle image */ | |
122 | #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold | |
123 | biggest possible glom */ | |
124 | ||
125 | #define BRCMF_FIRSTREAD (1 << 6) | |
126 | ||
9d6c1dc4 | 127 | #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */ |
5b435de0 AS |
128 | |
129 | /* SBSDIO_DEVICE_CTL */ | |
130 | ||
131 | /* 1: device will assert busy signal when receiving CMD53 */ | |
132 | #define SBSDIO_DEVCTL_SETBUSY 0x01 | |
133 | /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ | |
134 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 | |
135 | /* 1: mask all interrupts to host except the chipActive (rev 8) */ | |
136 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 | |
137 | /* 1: isolate internal sdio signals, put external pads in tri-state; requires | |
138 | * sdio bus power cycle to clear (rev 9) */ | |
139 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 | |
140 | /* Force SD->SB reset mapping (rev 11) */ | |
141 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 | |
142 | /* Determined by CoreControl bit */ | |
143 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 | |
144 | /* Force backplane reset */ | |
145 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 | |
146 | /* Force no backplane reset */ | |
147 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 | |
148 | ||
5b435de0 AS |
149 | /* direct(mapped) cis space */ |
150 | ||
151 | /* MAPPED common CIS address */ | |
152 | #define SBSDIO_CIS_BASE_COMMON 0x1000 | |
153 | /* maximum bytes in one CIS */ | |
154 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 | |
155 | /* cis offset addr is < 17 bits */ | |
156 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF | |
157 | ||
158 | /* manfid tuple length, include tuple, link bytes */ | |
159 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 | |
160 | ||
cb7cf7be AS |
161 | #define CORE_BUS_REG(base, field) \ |
162 | (base + offsetof(struct sdpcmd_regs, field)) | |
163 | ||
164 | /* SDIO function 1 register CHIPCLKCSR */ | |
165 | /* Force ALP request to backplane */ | |
166 | #define SBSDIO_FORCE_ALP 0x01 | |
167 | /* Force HT request to backplane */ | |
168 | #define SBSDIO_FORCE_HT 0x02 | |
169 | /* Force ILP request to backplane */ | |
170 | #define SBSDIO_FORCE_ILP 0x04 | |
171 | /* Make ALP ready (power up xtal) */ | |
172 | #define SBSDIO_ALP_AVAIL_REQ 0x08 | |
173 | /* Make HT ready (power up PLL) */ | |
174 | #define SBSDIO_HT_AVAIL_REQ 0x10 | |
175 | /* Squelch clock requests from HW */ | |
176 | #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 | |
177 | /* Status: ALP is ready */ | |
178 | #define SBSDIO_ALP_AVAIL 0x40 | |
179 | /* Status: HT is ready */ | |
180 | #define SBSDIO_HT_AVAIL 0x80 | |
8a385ba5 | 181 | #define SBSDIO_CSR_MASK 0x1F |
cb7cf7be AS |
182 | #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) |
183 | #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) | |
184 | #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) | |
185 | #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) | |
186 | #define SBSDIO_CLKAV(regval, alponly) \ | |
187 | (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) | |
188 | ||
5b435de0 AS |
189 | /* intstatus */ |
190 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | |
191 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | |
192 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | |
193 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | |
194 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | |
195 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | |
196 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | |
197 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | |
198 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | |
199 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | |
200 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | |
201 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | |
202 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | |
203 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | |
204 | #define I_PC (1 << 10) /* descriptor error */ | |
205 | #define I_PD (1 << 11) /* data error */ | |
206 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | |
207 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | |
208 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | |
209 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | |
210 | #define I_RI (1 << 16) /* Receive Interrupt */ | |
211 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | |
212 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | |
213 | #define I_XI (1 << 24) /* Transmit Interrupt */ | |
214 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | |
215 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | |
216 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | |
217 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | |
218 | #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ | |
219 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | |
220 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | |
221 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) | |
222 | #define I_DMA (I_RI | I_XI | I_ERRORS) | |
223 | ||
224 | /* corecontrol */ | |
225 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | |
226 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ | |
227 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | |
228 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ | |
229 | #define CC_XMTDATAAVAIL_MODE (1 << 4) | |
230 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) | |
231 | ||
232 | /* SDA_FRAMECTRL */ | |
233 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | |
234 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | |
235 | #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ | |
236 | #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ | |
237 | ||
5b435de0 AS |
238 | /* |
239 | * Software allocation of To SB Mailbox resources | |
240 | */ | |
241 | ||
242 | /* tosbmailbox bits corresponding to intstatus bits */ | |
243 | #define SMB_NAK (1 << 0) /* Frame NAK */ | |
244 | #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ | |
245 | #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ | |
246 | #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ | |
247 | ||
248 | /* tosbmailboxdata */ | |
249 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ | |
250 | ||
251 | /* | |
252 | * Software allocation of To Host Mailbox resources | |
253 | */ | |
254 | ||
255 | /* intstatus bits */ | |
256 | #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ | |
257 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ | |
258 | #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ | |
259 | #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ | |
260 | ||
261 | /* tohostmailboxdata */ | |
262 | #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ | |
263 | #define HMB_DATA_DEVREADY 2 /* talk to host after enable */ | |
264 | #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ | |
265 | #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ | |
266 | ||
267 | #define HMB_DATA_FCDATA_MASK 0xff000000 | |
268 | #define HMB_DATA_FCDATA_SHIFT 24 | |
269 | ||
270 | #define HMB_DATA_VERSION_MASK 0x00ff0000 | |
271 | #define HMB_DATA_VERSION_SHIFT 16 | |
272 | ||
273 | /* | |
274 | * Software-defined protocol header | |
275 | */ | |
276 | ||
277 | /* Current protocol version */ | |
278 | #define SDPCM_PROT_VERSION 4 | |
279 | ||
5b435de0 AS |
280 | /* |
281 | * Shared structure between dongle and the host. | |
282 | * The structure contains pointers to trap or assert information. | |
283 | */ | |
4fc0d016 | 284 | #define SDPCM_SHARED_VERSION 0x0003 |
5b435de0 AS |
285 | #define SDPCM_SHARED_VERSION_MASK 0x00FF |
286 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | |
287 | #define SDPCM_SHARED_ASSERT 0x0200 | |
288 | #define SDPCM_SHARED_TRAP 0x0400 | |
289 | ||
290 | /* Space for header read, limit for data packets */ | |
291 | #define MAX_HDR_READ (1 << 6) | |
292 | #define MAX_RX_DATASZ 2048 | |
293 | ||
5b435de0 AS |
294 | /* Bump up limit on waiting for HT to account for first startup; |
295 | * if the image is doing a CRC calculation before programming the PMU | |
296 | * for HT availability, it could take a couple hundred ms more, so | |
297 | * max out at a 1 second (1000000us). | |
298 | */ | |
299 | #undef PMU_MAX_TRANSITION_DLY | |
300 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
301 | ||
302 | /* Value for ChipClockCSR during initial setup */ | |
303 | #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ | |
304 | SBSDIO_ALP_AVAIL_REQ) | |
305 | ||
306 | /* Flags for SDH calls */ | |
307 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
308 | ||
382a9e0f FL |
309 | #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change |
310 | * when idle | |
311 | */ | |
312 | #define BRCMF_IDLE_INTERVAL 1 | |
313 | ||
4a3da990 PH |
314 | #define KSO_WAIT_US 50 |
315 | #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) | |
316 | ||
5b435de0 AS |
317 | /* |
318 | * Conversion of 802.1D priority to precedence level | |
319 | */ | |
320 | static uint prio2prec(u32 prio) | |
321 | { | |
322 | return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? | |
323 | (prio^2) : prio; | |
324 | } | |
325 | ||
8ae74654 | 326 | #ifdef DEBUG |
5b435de0 AS |
327 | /* Device console log buffer state */ |
328 | struct brcmf_console { | |
329 | uint count; /* Poll interval msec counter */ | |
330 | uint log_addr; /* Log struct address (fixed) */ | |
331 | struct rte_log_le log_le; /* Log struct (host copy) */ | |
332 | uint bufsize; /* Size of log buffer */ | |
333 | u8 *buf; /* Log buffer (host copy) */ | |
334 | uint last; /* Last buffer read index */ | |
335 | }; | |
4fc0d016 AS |
336 | |
337 | struct brcmf_trap_info { | |
338 | __le32 type; | |
339 | __le32 epc; | |
340 | __le32 cpsr; | |
341 | __le32 spsr; | |
342 | __le32 r0; /* a1 */ | |
343 | __le32 r1; /* a2 */ | |
344 | __le32 r2; /* a3 */ | |
345 | __le32 r3; /* a4 */ | |
346 | __le32 r4; /* v1 */ | |
347 | __le32 r5; /* v2 */ | |
348 | __le32 r6; /* v3 */ | |
349 | __le32 r7; /* v4 */ | |
350 | __le32 r8; /* v5 */ | |
351 | __le32 r9; /* sb/v6 */ | |
352 | __le32 r10; /* sl/v7 */ | |
353 | __le32 r11; /* fp/v8 */ | |
354 | __le32 r12; /* ip */ | |
355 | __le32 r13; /* sp */ | |
356 | __le32 r14; /* lr */ | |
357 | __le32 pc; /* r15 */ | |
358 | }; | |
8ae74654 | 359 | #endif /* DEBUG */ |
5b435de0 AS |
360 | |
361 | struct sdpcm_shared { | |
362 | u32 flags; | |
363 | u32 trap_addr; | |
364 | u32 assert_exp_addr; | |
365 | u32 assert_file_addr; | |
366 | u32 assert_line; | |
367 | u32 console_addr; /* Address of struct rte_console */ | |
368 | u32 msgtrace_addr; | |
369 | u8 tag[32]; | |
4fc0d016 | 370 | u32 brpt_addr; |
5b435de0 AS |
371 | }; |
372 | ||
373 | struct sdpcm_shared_le { | |
374 | __le32 flags; | |
375 | __le32 trap_addr; | |
376 | __le32 assert_exp_addr; | |
377 | __le32 assert_file_addr; | |
378 | __le32 assert_line; | |
379 | __le32 console_addr; /* Address of struct rte_console */ | |
380 | __le32 msgtrace_addr; | |
381 | u8 tag[32]; | |
4fc0d016 | 382 | __le32 brpt_addr; |
5b435de0 AS |
383 | }; |
384 | ||
6bc52319 FL |
385 | /* dongle SDIO bus specific header info */ |
386 | struct brcmf_sdio_hdrinfo { | |
4754fcee FL |
387 | u8 seq_num; |
388 | u8 channel; | |
389 | u16 len; | |
390 | u16 len_left; | |
391 | u16 len_nxtfrm; | |
392 | u8 dat_offset; | |
8da9d2c8 FL |
393 | bool lastfrm; |
394 | u16 tail_pad; | |
4754fcee | 395 | }; |
5b435de0 | 396 | |
82d957e0 AS |
397 | /* |
398 | * hold counter variables | |
399 | */ | |
400 | struct brcmf_sdio_count { | |
401 | uint intrcount; /* Count of device interrupt callbacks */ | |
402 | uint lastintrs; /* Count as of last watchdog timer */ | |
403 | uint pollcnt; /* Count of active polls */ | |
404 | uint regfails; /* Count of R_REG failures */ | |
405 | uint tx_sderrs; /* Count of tx attempts with sd errors */ | |
406 | uint fcqueued; /* Tx packets that got queued */ | |
407 | uint rxrtx; /* Count of rtx requests (NAK to dongle) */ | |
408 | uint rx_toolong; /* Receive frames too long to receive */ | |
409 | uint rxc_errors; /* SDIO errors when reading control frames */ | |
410 | uint rx_hdrfail; /* SDIO errors on header reads */ | |
411 | uint rx_badhdr; /* Bad received headers (roosync?) */ | |
412 | uint rx_badseq; /* Mismatched rx sequence number */ | |
413 | uint fc_rcvd; /* Number of flow-control events received */ | |
414 | uint fc_xoff; /* Number which turned on flow-control */ | |
415 | uint fc_xon; /* Number which turned off flow-control */ | |
416 | uint rxglomfail; /* Failed deglom attempts */ | |
417 | uint rxglomframes; /* Number of glom frames (superframes) */ | |
418 | uint rxglompkts; /* Number of packets from glom frames */ | |
419 | uint f2rxhdrs; /* Number of header reads */ | |
420 | uint f2rxdata; /* Number of frame data reads */ | |
421 | uint f2txdata; /* Number of f2 frame writes */ | |
422 | uint f1regdata; /* Number of f1 register accesses */ | |
423 | uint tickcnt; /* Number of watchdog been schedule */ | |
424 | ulong tx_ctlerrs; /* Err of sending ctrl frames */ | |
425 | ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ | |
426 | ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ | |
427 | ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ | |
428 | ulong rx_readahead_cnt; /* packets where header read-ahead was used */ | |
429 | }; | |
430 | ||
5b435de0 | 431 | /* misc chip info needed by some of the routines */ |
5b435de0 | 432 | /* Private data for SDIO bus interaction */ |
e92eedf4 | 433 | struct brcmf_sdio { |
5b435de0 | 434 | struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ |
9cf218fc | 435 | struct brcmf_chip *ci; /* Chip info struct */ |
5b435de0 | 436 | |
5b435de0 | 437 | u32 hostintmask; /* Copy of Host Interrupt Mask */ |
4531603a FL |
438 | atomic_t intstatus; /* Intstatus bits (events) pending */ |
439 | atomic_t fcstate; /* State of dongle flow-control */ | |
5b435de0 AS |
440 | |
441 | uint blocksize; /* Block size of SDIO transfers */ | |
442 | uint roundup; /* Max roundup limit */ | |
443 | ||
444 | struct pktq txq; /* Queue length used for flow-control */ | |
445 | u8 flowcontrol; /* per prio flow control bitmask */ | |
446 | u8 tx_seq; /* Transmit sequence number (next) */ | |
447 | u8 tx_max; /* Maximum transmit sequence allowed */ | |
448 | ||
9b2d2f2a | 449 | u8 *hdrbuf; /* buffer for handling rx frame */ |
5b435de0 | 450 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ |
5b435de0 | 451 | u8 rx_seq; /* Receive sequence number (expected) */ |
6bc52319 | 452 | struct brcmf_sdio_hdrinfo cur_read; |
4754fcee | 453 | /* info of current read frame */ |
5b435de0 | 454 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ |
4754fcee | 455 | bool rxpending; /* Data frame pending in dongle */ |
5b435de0 AS |
456 | |
457 | uint rxbound; /* Rx frames to read before resched */ | |
458 | uint txbound; /* Tx frames to send before resched */ | |
459 | uint txminmax; | |
460 | ||
461 | struct sk_buff *glomd; /* Packet containing glomming descriptor */ | |
b83db862 | 462 | struct sk_buff_head glom; /* Packet list for glommed superframe */ |
5b435de0 AS |
463 | |
464 | u8 *rxbuf; /* Buffer for receiving control packets */ | |
465 | uint rxblen; /* Allocated length of rxbuf */ | |
466 | u8 *rxctl; /* Aligned pointer into rxbuf */ | |
dd43a01c | 467 | u8 *rxctl_orig; /* pointer for freeing rxctl */ |
5b435de0 | 468 | uint rxlen; /* Length of valid data in buffer */ |
dd43a01c | 469 | spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ |
5b435de0 AS |
470 | |
471 | u8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
472 | ||
473 | bool intr; /* Use interrupts */ | |
474 | bool poll; /* Use polling */ | |
1d382273 | 475 | atomic_t ipend; /* Device interrupt is pending */ |
5b435de0 AS |
476 | uint spurious; /* Count of spurious interrupts */ |
477 | uint pollrate; /* Ticks between device polls */ | |
478 | uint polltick; /* Tick counter */ | |
5b435de0 | 479 | |
8ae74654 | 480 | #ifdef DEBUG |
5b435de0 AS |
481 | uint console_interval; |
482 | struct brcmf_console console; /* Console output polling support */ | |
483 | uint console_addr; /* Console address from shared struct */ | |
8ae74654 | 484 | #endif /* DEBUG */ |
5b435de0 | 485 | |
5b435de0 | 486 | uint clkstate; /* State of sd and backplane clock(s) */ |
5b435de0 | 487 | s32 idletime; /* Control for activity timeout */ |
b441ba8d HM |
488 | s32 idlecount; /* Activity timeout counter */ |
489 | s32 idleclock; /* How to set bus driver when idle */ | |
5b435de0 AS |
490 | bool rxflow_mode; /* Rx flow control mode */ |
491 | bool rxflow; /* Is rx flow control on */ | |
492 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
5b435de0 | 493 | |
5b435de0 | 494 | u8 *ctrl_frame_buf; |
fed7ec44 | 495 | u16 ctrl_frame_len; |
5b435de0 | 496 | bool ctrl_frame_stat; |
4dd8b26a | 497 | int ctrl_frame_err; |
5b435de0 | 498 | |
fed7ec44 | 499 | spinlock_t txq_lock; /* protect bus->txq */ |
5b435de0 AS |
500 | wait_queue_head_t ctrl_wait; |
501 | wait_queue_head_t dcmd_resp_wait; | |
502 | ||
503 | struct timer_list timer; | |
504 | struct completion watchdog_wait; | |
505 | struct task_struct *watchdog_tsk; | |
4011fc49 | 506 | bool wd_active; |
5b435de0 | 507 | |
f1e68c2e FL |
508 | struct workqueue_struct *brcmf_wq; |
509 | struct work_struct datawork; | |
2c64e16d HM |
510 | bool dpc_triggered; |
511 | bool dpc_running; | |
5b435de0 | 512 | |
c8bf3484 | 513 | bool txoff; /* Transmit flow-controlled */ |
80969836 | 514 | struct brcmf_sdio_count sdcnt; |
4a3da990 | 515 | bool sr_enabled; /* SaveRestore enabled */ |
99824643 | 516 | bool sleeping; |
706478cb FL |
517 | |
518 | u8 tx_hdrlen; /* sdio bus header length for tx packet */ | |
8da9d2c8 | 519 | bool txglom; /* host tx glomming enable flag */ |
e217d1c8 AS |
520 | u16 head_align; /* buffer pointer alignment */ |
521 | u16 sgentry_align; /* scatter-gather buffer alignment */ | |
5b435de0 AS |
522 | }; |
523 | ||
5b435de0 AS |
524 | /* clkstate */ |
525 | #define CLK_NONE 0 | |
526 | #define CLK_SDONLY 1 | |
4a3da990 | 527 | #define CLK_PENDING 2 |
5b435de0 AS |
528 | #define CLK_AVAIL 3 |
529 | ||
8ae74654 | 530 | #ifdef DEBUG |
5b435de0 | 531 | static int qcount[NUMPRIO]; |
8ae74654 | 532 | #endif /* DEBUG */ |
5b435de0 | 533 | |
668761ac | 534 | #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ |
5b435de0 AS |
535 | |
536 | #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) | |
537 | ||
5b435de0 AS |
538 | /* Limit on rounding up frames */ |
539 | static const uint max_roundup = 512; | |
540 | ||
541 | #define ALIGNMENT 4 | |
542 | ||
9d7d6f95 FL |
543 | enum brcmf_sdio_frmtype { |
544 | BRCMF_SDIO_FT_NORMAL, | |
545 | BRCMF_SDIO_FT_SUPER, | |
546 | BRCMF_SDIO_FT_SUB, | |
547 | }; | |
548 | ||
65d80d0b AS |
549 | #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) |
550 | ||
551 | /* SDIO Pad drive strength to select value mappings */ | |
552 | struct sdiod_drive_str { | |
553 | u8 strength; /* Pad Drive Strength in mA */ | |
554 | u8 sel; /* Chip-specific select value */ | |
555 | }; | |
556 | ||
557 | /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ | |
558 | static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { | |
559 | {32, 0x6}, | |
560 | {26, 0x7}, | |
561 | {22, 0x4}, | |
562 | {16, 0x5}, | |
563 | {12, 0x2}, | |
564 | {8, 0x3}, | |
565 | {4, 0x0}, | |
566 | {0, 0x1} | |
567 | }; | |
568 | ||
569 | /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ | |
570 | static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { | |
571 | {6, 0x7}, | |
572 | {5, 0x6}, | |
573 | {4, 0x5}, | |
574 | {3, 0x4}, | |
575 | {2, 0x2}, | |
576 | {1, 0x1}, | |
577 | {0, 0x0} | |
578 | }; | |
579 | ||
580 | /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ | |
581 | static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { | |
582 | {3, 0x3}, | |
583 | {2, 0x2}, | |
584 | {1, 0x1}, | |
585 | {0, 0x0} }; | |
586 | ||
587 | /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ | |
588 | static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { | |
589 | {16, 0x7}, | |
590 | {12, 0x5}, | |
591 | {8, 0x3}, | |
592 | {4, 0x1} | |
593 | }; | |
594 | ||
46d703a7 HM |
595 | BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt"); |
596 | BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin", | |
597 | "brcmfmac43241b0-sdio.txt"); | |
598 | BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin", | |
599 | "brcmfmac43241b4-sdio.txt"); | |
600 | BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin", | |
601 | "brcmfmac43241b5-sdio.txt"); | |
602 | BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt"); | |
603 | BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt"); | |
604 | BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt"); | |
605 | BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt"); | |
606 | BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt"); | |
607 | BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt"); | |
608 | BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt"); | |
609 | BRCMF_FW_NVRAM_DEF(43430, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt"); | |
610 | BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt"); | |
611 | BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt"); | |
612 | ||
613 | static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { | |
614 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143), | |
615 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0), | |
616 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4), | |
617 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5), | |
618 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329), | |
619 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330), | |
620 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334), | |
621 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340), | |
622 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335), | |
623 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362), | |
624 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), | |
625 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, 43430), | |
626 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455), | |
627 | BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354) | |
f2c44fe7 HM |
628 | }; |
629 | ||
5b435de0 AS |
630 | static void pkt_align(struct sk_buff *p, int len, int align) |
631 | { | |
632 | uint datalign; | |
633 | datalign = (unsigned long)(p->data); | |
634 | datalign = roundup(datalign, (align)) - datalign; | |
635 | if (datalign) | |
636 | skb_pull(p, datalign); | |
637 | __skb_trim(p, len); | |
638 | } | |
639 | ||
640 | /* To check if there's window offered */ | |
e92eedf4 | 641 | static bool data_ok(struct brcmf_sdio *bus) |
5b435de0 AS |
642 | { |
643 | return (u8)(bus->tx_max - bus->tx_seq) != 0 && | |
644 | ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; | |
645 | } | |
646 | ||
647 | /* | |
648 | * Reads a register in the SDIO hardware block. This block occupies a series of | |
649 | * adresses on the 32 bit backplane bus. | |
650 | */ | |
cb7cf7be | 651 | static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset) |
5b435de0 | 652 | { |
cb7cf7be | 653 | struct brcmf_core *core; |
79ae3957 | 654 | int ret; |
58692750 | 655 | |
cb7cf7be AS |
656 | core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
657 | *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret); | |
58692750 FL |
658 | |
659 | return ret; | |
5b435de0 AS |
660 | } |
661 | ||
cb7cf7be | 662 | static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) |
5b435de0 | 663 | { |
cb7cf7be | 664 | struct brcmf_core *core; |
e13ce26b | 665 | int ret; |
58692750 | 666 | |
cb7cf7be AS |
667 | core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
668 | brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret); | |
58692750 FL |
669 | |
670 | return ret; | |
5b435de0 AS |
671 | } |
672 | ||
4a3da990 | 673 | static int |
82d7f3c1 | 674 | brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) |
4a3da990 PH |
675 | { |
676 | u8 wr_val = 0, rd_val, cmp_val, bmask; | |
677 | int err = 0; | |
678 | int try_cnt = 0; | |
679 | ||
8a385ba5 | 680 | brcmf_dbg(TRACE, "Enter: on=%d\n", on); |
4a3da990 PH |
681 | |
682 | wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
683 | /* 1st KSO write goes to AOS wake up core if device is asleep */ | |
a39be27b AS |
684 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
685 | wr_val, &err); | |
4a3da990 PH |
686 | |
687 | if (on) { | |
688 | /* device WAKEUP through KSO: | |
689 | * write bit 0 & read back until | |
690 | * both bits 0 (kso bit) & 1 (dev on status) are set | |
691 | */ | |
692 | cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | | |
693 | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; | |
694 | bmask = cmp_val; | |
695 | usleep_range(2000, 3000); | |
696 | } else { | |
697 | /* Put device to sleep, turn off KSO */ | |
698 | cmp_val = 0; | |
699 | /* only check for bit0, bit1(dev on status) may not | |
700 | * get cleared right away | |
701 | */ | |
702 | bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; | |
703 | } | |
704 | ||
705 | do { | |
706 | /* reliable KSO bit set/clr: | |
707 | * the sdiod sleep write access is synced to PMU 32khz clk | |
708 | * just one write attempt may fail, | |
709 | * read it back until it matches written value | |
710 | */ | |
a39be27b AS |
711 | rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
712 | &err); | |
4a3da990 PH |
713 | if (((rd_val & bmask) == cmp_val) && !err) |
714 | break; | |
8a385ba5 | 715 | |
4a3da990 | 716 | udelay(KSO_WAIT_US); |
a39be27b AS |
717 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
718 | wr_val, &err); | |
4a3da990 PH |
719 | } while (try_cnt++ < MAX_KSO_ATTEMPTS); |
720 | ||
8a385ba5 AS |
721 | if (try_cnt > 2) |
722 | brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, | |
723 | rd_val, err); | |
724 | ||
725 | if (try_cnt > MAX_KSO_ATTEMPTS) | |
726 | brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); | |
727 | ||
4a3da990 PH |
728 | return err; |
729 | } | |
730 | ||
5b435de0 AS |
731 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) |
732 | ||
5b435de0 | 733 | /* Turn backplane clock on or off */ |
82d7f3c1 | 734 | static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) |
5b435de0 AS |
735 | { |
736 | int err; | |
737 | u8 clkctl, clkreq, devctl; | |
738 | unsigned long timeout; | |
739 | ||
c3203374 | 740 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
741 | |
742 | clkctl = 0; | |
743 | ||
4a3da990 PH |
744 | if (bus->sr_enabled) { |
745 | bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); | |
746 | return 0; | |
747 | } | |
748 | ||
5b435de0 AS |
749 | if (on) { |
750 | /* Request HT Avail */ | |
751 | clkreq = | |
752 | bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
753 | ||
a39be27b AS |
754 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
755 | clkreq, &err); | |
5b435de0 | 756 | if (err) { |
5e8149f5 | 757 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
758 | return -EBADE; |
759 | } | |
760 | ||
5b435de0 | 761 | /* Check current status */ |
a39be27b AS |
762 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
763 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 764 | if (err) { |
5e8149f5 | 765 | brcmf_err("HT Avail read error: %d\n", err); |
5b435de0 AS |
766 | return -EBADE; |
767 | } | |
768 | ||
769 | /* Go to pending and await interrupt if appropriate */ | |
770 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
771 | /* Allow only clock-available interrupt */ | |
a39be27b AS |
772 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
773 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 774 | if (err) { |
5e8149f5 | 775 | brcmf_err("Devctl error setting CA: %d\n", |
5b435de0 AS |
776 | err); |
777 | return -EBADE; | |
778 | } | |
779 | ||
780 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
a39be27b AS |
781 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
782 | devctl, &err); | |
c3203374 | 783 | brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); |
5b435de0 AS |
784 | bus->clkstate = CLK_PENDING; |
785 | ||
786 | return 0; | |
787 | } else if (bus->clkstate == CLK_PENDING) { | |
788 | /* Cancel CA-only interrupt filter */ | |
a39be27b AS |
789 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
790 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 791 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
792 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
793 | devctl, &err); | |
5b435de0 AS |
794 | } |
795 | ||
796 | /* Otherwise, wait here (polling) for HT Avail */ | |
797 | timeout = jiffies + | |
798 | msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); | |
799 | while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
a39be27b AS |
800 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
801 | SBSDIO_FUNC1_CHIPCLKCSR, | |
802 | &err); | |
5b435de0 AS |
803 | if (time_after(jiffies, timeout)) |
804 | break; | |
805 | else | |
806 | usleep_range(5000, 10000); | |
807 | } | |
808 | if (err) { | |
5e8149f5 | 809 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
810 | return -EBADE; |
811 | } | |
812 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
5e8149f5 | 813 | brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", |
5b435de0 AS |
814 | PMU_MAX_TRANSITION_DLY, clkctl); |
815 | return -EBADE; | |
816 | } | |
817 | ||
818 | /* Mark clock available */ | |
819 | bus->clkstate = CLK_AVAIL; | |
c3203374 | 820 | brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); |
5b435de0 | 821 | |
8ae74654 | 822 | #if defined(DEBUG) |
23677ce3 | 823 | if (!bus->alp_only) { |
5b435de0 | 824 | if (SBSDIO_ALPONLY(clkctl)) |
5e8149f5 | 825 | brcmf_err("HT Clock should be on\n"); |
5b435de0 | 826 | } |
8ae74654 | 827 | #endif /* defined (DEBUG) */ |
5b435de0 | 828 | |
5b435de0 AS |
829 | } else { |
830 | clkreq = 0; | |
831 | ||
832 | if (bus->clkstate == CLK_PENDING) { | |
833 | /* Cancel CA-only interrupt filter */ | |
a39be27b AS |
834 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
835 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 836 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
837 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
838 | devctl, &err); | |
5b435de0 AS |
839 | } |
840 | ||
841 | bus->clkstate = CLK_SDONLY; | |
a39be27b AS |
842 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
843 | clkreq, &err); | |
c3203374 | 844 | brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); |
5b435de0 | 845 | if (err) { |
5e8149f5 | 846 | brcmf_err("Failed access turning clock off: %d\n", |
5b435de0 AS |
847 | err); |
848 | return -EBADE; | |
849 | } | |
850 | } | |
851 | return 0; | |
852 | } | |
853 | ||
854 | /* Change idle/active SD state */ | |
82d7f3c1 | 855 | static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) |
5b435de0 | 856 | { |
c3203374 | 857 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
858 | |
859 | if (on) | |
860 | bus->clkstate = CLK_SDONLY; | |
861 | else | |
862 | bus->clkstate = CLK_NONE; | |
863 | ||
864 | return 0; | |
865 | } | |
866 | ||
867 | /* Transition SD and backplane clock readiness */ | |
82d7f3c1 | 868 | static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) |
5b435de0 | 869 | { |
8ae74654 | 870 | #ifdef DEBUG |
5b435de0 | 871 | uint oldstate = bus->clkstate; |
8ae74654 | 872 | #endif /* DEBUG */ |
5b435de0 | 873 | |
c3203374 | 874 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
875 | |
876 | /* Early exit if we're already there */ | |
b441ba8d | 877 | if (bus->clkstate == target) |
5b435de0 | 878 | return 0; |
5b435de0 AS |
879 | |
880 | switch (target) { | |
881 | case CLK_AVAIL: | |
882 | /* Make sure SD clock is available */ | |
883 | if (bus->clkstate == CLK_NONE) | |
82d7f3c1 | 884 | brcmf_sdio_sdclk(bus, true); |
5b435de0 | 885 | /* Now request HT Avail on the backplane */ |
82d7f3c1 | 886 | brcmf_sdio_htclk(bus, true, pendok); |
5b435de0 AS |
887 | break; |
888 | ||
889 | case CLK_SDONLY: | |
890 | /* Remove HT request, or bring up SD clock */ | |
891 | if (bus->clkstate == CLK_NONE) | |
82d7f3c1 | 892 | brcmf_sdio_sdclk(bus, true); |
5b435de0 | 893 | else if (bus->clkstate == CLK_AVAIL) |
82d7f3c1 | 894 | brcmf_sdio_htclk(bus, false, false); |
5b435de0 | 895 | else |
5e8149f5 | 896 | brcmf_err("request for %d -> %d\n", |
5b435de0 | 897 | bus->clkstate, target); |
5b435de0 AS |
898 | break; |
899 | ||
900 | case CLK_NONE: | |
901 | /* Make sure to remove HT request */ | |
902 | if (bus->clkstate == CLK_AVAIL) | |
82d7f3c1 | 903 | brcmf_sdio_htclk(bus, false, false); |
5b435de0 | 904 | /* Now remove the SD clock */ |
82d7f3c1 | 905 | brcmf_sdio_sdclk(bus, false); |
5b435de0 AS |
906 | break; |
907 | } | |
8ae74654 | 908 | #ifdef DEBUG |
c3203374 | 909 | brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); |
8ae74654 | 910 | #endif /* DEBUG */ |
5b435de0 AS |
911 | |
912 | return 0; | |
913 | } | |
914 | ||
4a3da990 | 915 | static int |
82d7f3c1 | 916 | brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) |
4a3da990 PH |
917 | { |
918 | int err = 0; | |
8a385ba5 | 919 | u8 clkcsr; |
82030d6d AS |
920 | |
921 | brcmf_dbg(SDIO, "Enter: request %s currently %s\n", | |
4a3da990 | 922 | (sleep ? "SLEEP" : "WAKE"), |
99824643 | 923 | (bus->sleeping ? "SLEEP" : "WAKE")); |
4a3da990 PH |
924 | |
925 | /* If SR is enabled control bus state with KSO */ | |
926 | if (bus->sr_enabled) { | |
927 | /* Done if we're already in the requested state */ | |
99824643 | 928 | if (sleep == bus->sleeping) |
4a3da990 PH |
929 | goto end; |
930 | ||
931 | /* Going to sleep */ | |
932 | if (sleep) { | |
8a385ba5 AS |
933 | clkcsr = brcmf_sdiod_regrb(bus->sdiodev, |
934 | SBSDIO_FUNC1_CHIPCLKCSR, | |
935 | &err); | |
936 | if ((clkcsr & SBSDIO_CSR_MASK) == 0) { | |
937 | brcmf_dbg(SDIO, "no clock, set ALP\n"); | |
938 | brcmf_sdiod_regwb(bus->sdiodev, | |
939 | SBSDIO_FUNC1_CHIPCLKCSR, | |
940 | SBSDIO_ALP_AVAIL_REQ, &err); | |
941 | } | |
82d7f3c1 | 942 | err = brcmf_sdio_kso_control(bus, false); |
4a3da990 | 943 | } else { |
82d7f3c1 | 944 | err = brcmf_sdio_kso_control(bus, true); |
4a3da990 | 945 | } |
8982cd40 | 946 | if (err) { |
4a3da990 PH |
947 | brcmf_err("error while changing bus sleep state %d\n", |
948 | err); | |
8a385ba5 | 949 | goto done; |
4a3da990 PH |
950 | } |
951 | } | |
952 | ||
953 | end: | |
954 | /* control clocks */ | |
955 | if (sleep) { | |
956 | if (!bus->sr_enabled) | |
82d7f3c1 | 957 | brcmf_sdio_clkctl(bus, CLK_NONE, pendok); |
4a3da990 | 958 | } else { |
82d7f3c1 | 959 | brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); |
4011fc49 | 960 | brcmf_sdio_wd_timer(bus, true); |
4a3da990 | 961 | } |
99824643 | 962 | bus->sleeping = sleep; |
8982cd40 AS |
963 | brcmf_dbg(SDIO, "new state %s\n", |
964 | (sleep ? "SLEEP" : "WAKE")); | |
8a385ba5 AS |
965 | done: |
966 | brcmf_dbg(SDIO, "Exit: err=%d\n", err); | |
4a3da990 PH |
967 | return err; |
968 | ||
969 | } | |
970 | ||
0801e6c5 DK |
971 | #ifdef DEBUG |
972 | static inline bool brcmf_sdio_valid_shared_address(u32 addr) | |
973 | { | |
974 | return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); | |
975 | } | |
976 | ||
977 | static int brcmf_sdio_readshared(struct brcmf_sdio *bus, | |
978 | struct sdpcm_shared *sh) | |
979 | { | |
9819a902 | 980 | u32 addr = 0; |
0801e6c5 DK |
981 | int rv; |
982 | u32 shaddr = 0; | |
983 | struct sdpcm_shared_le sh_le; | |
984 | __le32 addr_le; | |
985 | ||
9819a902 AS |
986 | sdio_claim_host(bus->sdiodev->func[1]); |
987 | brcmf_sdio_bus_sleep(bus, false, false); | |
0801e6c5 DK |
988 | |
989 | /* | |
990 | * Read last word in socram to determine | |
991 | * address of sdpcm_shared structure | |
992 | */ | |
9819a902 AS |
993 | shaddr = bus->ci->rambase + bus->ci->ramsize - 4; |
994 | if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci)) | |
995 | shaddr -= bus->ci->srsize; | |
996 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, | |
997 | (u8 *)&addr_le, 4); | |
0801e6c5 | 998 | if (rv < 0) |
9819a902 | 999 | goto fail; |
0801e6c5 DK |
1000 | |
1001 | /* | |
1002 | * Check if addr is valid. | |
1003 | * NVRAM length at the end of memory should have been overwritten. | |
1004 | */ | |
9819a902 | 1005 | addr = le32_to_cpu(addr_le); |
0801e6c5 | 1006 | if (!brcmf_sdio_valid_shared_address(addr)) { |
9819a902 AS |
1007 | brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr); |
1008 | rv = -EINVAL; | |
1009 | goto fail; | |
0801e6c5 DK |
1010 | } |
1011 | ||
9819a902 AS |
1012 | brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr); |
1013 | ||
0801e6c5 DK |
1014 | /* Read hndrte_shared structure */ |
1015 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, | |
1016 | sizeof(struct sdpcm_shared_le)); | |
1017 | if (rv < 0) | |
9819a902 AS |
1018 | goto fail; |
1019 | ||
1020 | sdio_release_host(bus->sdiodev->func[1]); | |
0801e6c5 DK |
1021 | |
1022 | /* Endianness */ | |
1023 | sh->flags = le32_to_cpu(sh_le.flags); | |
1024 | sh->trap_addr = le32_to_cpu(sh_le.trap_addr); | |
1025 | sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); | |
1026 | sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); | |
1027 | sh->assert_line = le32_to_cpu(sh_le.assert_line); | |
1028 | sh->console_addr = le32_to_cpu(sh_le.console_addr); | |
1029 | sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); | |
1030 | ||
1031 | if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { | |
1032 | brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", | |
1033 | SDPCM_SHARED_VERSION, | |
1034 | sh->flags & SDPCM_SHARED_VERSION_MASK); | |
1035 | return -EPROTO; | |
1036 | } | |
0801e6c5 | 1037 | return 0; |
9819a902 AS |
1038 | |
1039 | fail: | |
1040 | brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n", | |
1041 | rv, addr); | |
1042 | sdio_release_host(bus->sdiodev->func[1]); | |
1043 | return rv; | |
0801e6c5 DK |
1044 | } |
1045 | ||
1046 | static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) | |
1047 | { | |
1048 | struct sdpcm_shared sh; | |
1049 | ||
1050 | if (brcmf_sdio_readshared(bus, &sh) == 0) | |
1051 | bus->console_addr = sh.console_addr; | |
1052 | } | |
1053 | #else | |
1054 | static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) | |
1055 | { | |
1056 | } | |
1057 | #endif /* DEBUG */ | |
1058 | ||
82d7f3c1 | 1059 | static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) |
5b435de0 AS |
1060 | { |
1061 | u32 intstatus = 0; | |
1062 | u32 hmb_data; | |
1063 | u8 fcbits; | |
58692750 | 1064 | int ret; |
5b435de0 | 1065 | |
c3203374 | 1066 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
1067 | |
1068 | /* Read mailbox data and ack that we did so */ | |
58692750 FL |
1069 | ret = r_sdreg32(bus, &hmb_data, |
1070 | offsetof(struct sdpcmd_regs, tohostmailboxdata)); | |
5b435de0 | 1071 | |
58692750 | 1072 | if (ret == 0) |
5b435de0 | 1073 | w_sdreg32(bus, SMB_INT_ACK, |
58692750 | 1074 | offsetof(struct sdpcmd_regs, tosbmailbox)); |
80969836 | 1075 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1076 | |
1077 | /* Dongle recomposed rx frames, accept them again */ | |
1078 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
c3203374 | 1079 | brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", |
5b435de0 AS |
1080 | bus->rx_seq); |
1081 | if (!bus->rxskip) | |
5e8149f5 | 1082 | brcmf_err("unexpected NAKHANDLED!\n"); |
5b435de0 AS |
1083 | |
1084 | bus->rxskip = false; | |
1085 | intstatus |= I_HMB_FRAME_IND; | |
1086 | } | |
1087 | ||
1088 | /* | |
1089 | * DEVREADY does not occur with gSPI. | |
1090 | */ | |
1091 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
1092 | bus->sdpcm_ver = | |
1093 | (hmb_data & HMB_DATA_VERSION_MASK) >> | |
1094 | HMB_DATA_VERSION_SHIFT; | |
1095 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
5e8149f5 | 1096 | brcmf_err("Version mismatch, dongle reports %d, " |
5b435de0 AS |
1097 | "expecting %d\n", |
1098 | bus->sdpcm_ver, SDPCM_PROT_VERSION); | |
1099 | else | |
c3203374 | 1100 | brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", |
5b435de0 | 1101 | bus->sdpcm_ver); |
0801e6c5 DK |
1102 | |
1103 | /* | |
1104 | * Retrieve console state address now that firmware should have | |
1105 | * updated it. | |
1106 | */ | |
1107 | brcmf_sdio_get_console_addr(bus); | |
5b435de0 AS |
1108 | } |
1109 | ||
1110 | /* | |
1111 | * Flow Control has been moved into the RX headers and this out of band | |
1112 | * method isn't used any more. | |
1113 | * remaining backward compatible with older dongles. | |
1114 | */ | |
1115 | if (hmb_data & HMB_DATA_FC) { | |
1116 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> | |
1117 | HMB_DATA_FCDATA_SHIFT; | |
1118 | ||
1119 | if (fcbits & ~bus->flowcontrol) | |
80969836 | 1120 | bus->sdcnt.fc_xoff++; |
5b435de0 AS |
1121 | |
1122 | if (bus->flowcontrol & ~fcbits) | |
80969836 | 1123 | bus->sdcnt.fc_xon++; |
5b435de0 | 1124 | |
80969836 | 1125 | bus->sdcnt.fc_rcvd++; |
5b435de0 AS |
1126 | bus->flowcontrol = fcbits; |
1127 | } | |
1128 | ||
1129 | /* Shouldn't be any others */ | |
1130 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
1131 | HMB_DATA_NAKHANDLED | | |
1132 | HMB_DATA_FC | | |
1133 | HMB_DATA_FWREADY | | |
1134 | HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) | |
5e8149f5 | 1135 | brcmf_err("Unknown mailbox data content: 0x%02x\n", |
5b435de0 AS |
1136 | hmb_data); |
1137 | ||
1138 | return intstatus; | |
1139 | } | |
1140 | ||
82d7f3c1 | 1141 | static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) |
5b435de0 AS |
1142 | { |
1143 | uint retries = 0; | |
1144 | u16 lastrbc; | |
1145 | u8 hi, lo; | |
1146 | int err; | |
1147 | ||
5e8149f5 | 1148 | brcmf_err("%sterminate frame%s\n", |
5b435de0 AS |
1149 | abort ? "abort command, " : "", |
1150 | rtx ? ", send NAK" : ""); | |
1151 | ||
1152 | if (abort) | |
a39be27b | 1153 | brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2); |
5b435de0 | 1154 | |
a39be27b AS |
1155 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
1156 | SFC_RF_TERM, &err); | |
80969836 | 1157 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
1158 | |
1159 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
1160 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
a39be27b AS |
1161 | hi = brcmf_sdiod_regrb(bus->sdiodev, |
1162 | SBSDIO_FUNC1_RFRAMEBCHI, &err); | |
1163 | lo = brcmf_sdiod_regrb(bus->sdiodev, | |
1164 | SBSDIO_FUNC1_RFRAMEBCLO, &err); | |
80969836 | 1165 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1166 | |
1167 | if ((hi == 0) && (lo == 0)) | |
1168 | break; | |
1169 | ||
1170 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
5e8149f5 | 1171 | brcmf_err("count growing: last 0x%04x now 0x%04x\n", |
5b435de0 AS |
1172 | lastrbc, (hi << 8) + lo); |
1173 | } | |
1174 | lastrbc = (hi << 8) + lo; | |
1175 | } | |
1176 | ||
1177 | if (!retries) | |
5e8149f5 | 1178 | brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); |
5b435de0 | 1179 | else |
c3203374 | 1180 | brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); |
5b435de0 AS |
1181 | |
1182 | if (rtx) { | |
80969836 | 1183 | bus->sdcnt.rxrtx++; |
58692750 FL |
1184 | err = w_sdreg32(bus, SMB_NAK, |
1185 | offsetof(struct sdpcmd_regs, tosbmailbox)); | |
5b435de0 | 1186 | |
80969836 | 1187 | bus->sdcnt.f1regdata++; |
58692750 | 1188 | if (err == 0) |
5b435de0 AS |
1189 | bus->rxskip = true; |
1190 | } | |
1191 | ||
1192 | /* Clear partial in any case */ | |
4754fcee | 1193 | bus->cur_read.len = 0; |
5b435de0 AS |
1194 | } |
1195 | ||
81c7883c HM |
1196 | static void brcmf_sdio_txfail(struct brcmf_sdio *bus) |
1197 | { | |
1198 | struct brcmf_sdio_dev *sdiodev = bus->sdiodev; | |
1199 | u8 i, hi, lo; | |
1200 | ||
1201 | /* On failure, abort the command and terminate the frame */ | |
1202 | brcmf_err("sdio error, abort command and terminate frame\n"); | |
1203 | bus->sdcnt.tx_sderrs++; | |
1204 | ||
1205 | brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2); | |
1206 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); | |
1207 | bus->sdcnt.f1regdata++; | |
1208 | ||
1209 | for (i = 0; i < 3; i++) { | |
1210 | hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); | |
1211 | lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); | |
1212 | bus->sdcnt.f1regdata += 2; | |
1213 | if ((hi == 0) && (lo == 0)) | |
1214 | break; | |
1215 | } | |
1216 | } | |
1217 | ||
9a95e60e | 1218 | /* return total length of buffer chain */ |
82d7f3c1 | 1219 | static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) |
9a95e60e AS |
1220 | { |
1221 | struct sk_buff *p; | |
1222 | uint total; | |
1223 | ||
1224 | total = 0; | |
1225 | skb_queue_walk(&bus->glom, p) | |
1226 | total += p->len; | |
1227 | return total; | |
1228 | } | |
1229 | ||
82d7f3c1 | 1230 | static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) |
046808da AS |
1231 | { |
1232 | struct sk_buff *cur, *next; | |
1233 | ||
1234 | skb_queue_walk_safe(&bus->glom, cur, next) { | |
1235 | skb_unlink(cur, &bus->glom); | |
1236 | brcmu_pkt_buf_free_skb(cur); | |
1237 | } | |
1238 | } | |
1239 | ||
6bc52319 FL |
1240 | /** |
1241 | * brcmfmac sdio bus specific header | |
1242 | * This is the lowest layer header wrapped on the packets transmitted between | |
1243 | * host and WiFi dongle which contains information needed for SDIO core and | |
1244 | * firmware | |
1245 | * | |
8da9d2c8 FL |
1246 | * It consists of 3 parts: hardware header, hardware extension header and |
1247 | * software header | |
6bc52319 FL |
1248 | * hardware header (frame tag) - 4 bytes |
1249 | * Byte 0~1: Frame length | |
1250 | * Byte 2~3: Checksum, bit-wise inverse of frame length | |
8da9d2c8 FL |
1251 | * hardware extension header - 8 bytes |
1252 | * Tx glom mode only, N/A for Rx or normal Tx | |
1253 | * Byte 0~1: Packet length excluding hw frame tag | |
1254 | * Byte 2: Reserved | |
1255 | * Byte 3: Frame flags, bit 0: last frame indication | |
1256 | * Byte 4~5: Reserved | |
1257 | * Byte 6~7: Tail padding length | |
6bc52319 FL |
1258 | * software header - 8 bytes |
1259 | * Byte 0: Rx/Tx sequence number | |
1260 | * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag | |
1261 | * Byte 2: Length of next data frame, reserved for Tx | |
1262 | * Byte 3: Data offset | |
1263 | * Byte 4: Flow control bits, reserved for Tx | |
1264 | * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet | |
1265 | * Byte 6~7: Reserved | |
1266 | */ | |
1267 | #define SDPCM_HWHDR_LEN 4 | |
8da9d2c8 | 1268 | #define SDPCM_HWEXT_LEN 8 |
6bc52319 FL |
1269 | #define SDPCM_SWHDR_LEN 8 |
1270 | #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) | |
6bc52319 FL |
1271 | /* software header */ |
1272 | #define SDPCM_SEQ_MASK 0x000000ff | |
1273 | #define SDPCM_SEQ_WRAP 256 | |
1274 | #define SDPCM_CHANNEL_MASK 0x00000f00 | |
1275 | #define SDPCM_CHANNEL_SHIFT 8 | |
1276 | #define SDPCM_CONTROL_CHANNEL 0 /* Control */ | |
1277 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ | |
1278 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ | |
1279 | #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ | |
1280 | #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ | |
1281 | #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) | |
1282 | #define SDPCM_NEXTLEN_MASK 0x00ff0000 | |
1283 | #define SDPCM_NEXTLEN_SHIFT 16 | |
1284 | #define SDPCM_DOFFSET_MASK 0xff000000 | |
1285 | #define SDPCM_DOFFSET_SHIFT 24 | |
1286 | #define SDPCM_FCMASK_MASK 0x000000ff | |
1287 | #define SDPCM_WINDOW_MASK 0x0000ff00 | |
1288 | #define SDPCM_WINDOW_SHIFT 8 | |
1289 | ||
1290 | static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) | |
1291 | { | |
1292 | u32 hdrvalue; | |
1293 | hdrvalue = *(u32 *)swheader; | |
1294 | return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); | |
1295 | } | |
1296 | ||
c56caa9d FL |
1297 | static inline bool brcmf_sdio_fromevntchan(u8 *swheader) |
1298 | { | |
1299 | u32 hdrvalue; | |
1300 | u8 ret; | |
1301 | ||
1302 | hdrvalue = *(u32 *)swheader; | |
1303 | ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT); | |
1304 | ||
1305 | return (ret == SDPCM_EVENT_CHANNEL); | |
1306 | } | |
1307 | ||
6bc52319 FL |
1308 | static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, |
1309 | struct brcmf_sdio_hdrinfo *rd, | |
1310 | enum brcmf_sdio_frmtype type) | |
4754fcee FL |
1311 | { |
1312 | u16 len, checksum; | |
1313 | u8 rx_seq, fc, tx_seq_max; | |
6bc52319 | 1314 | u32 swheader; |
4754fcee | 1315 | |
4b776961 | 1316 | trace_brcmf_sdpcm_hdr(SDPCM_RX, header); |
76584ece | 1317 | |
6bc52319 | 1318 | /* hw header */ |
4754fcee FL |
1319 | len = get_unaligned_le16(header); |
1320 | checksum = get_unaligned_le16(header + sizeof(u16)); | |
1321 | /* All zero means no more to read */ | |
1322 | if (!(len | checksum)) { | |
1323 | bus->rxpending = false; | |
10510589 | 1324 | return -ENODATA; |
4754fcee FL |
1325 | } |
1326 | if ((u16)(~(len ^ checksum))) { | |
5e8149f5 | 1327 | brcmf_err("HW header checksum error\n"); |
4754fcee | 1328 | bus->sdcnt.rx_badhdr++; |
82d7f3c1 | 1329 | brcmf_sdio_rxfail(bus, false, false); |
10510589 | 1330 | return -EIO; |
4754fcee FL |
1331 | } |
1332 | if (len < SDPCM_HDRLEN) { | |
5e8149f5 | 1333 | brcmf_err("HW header length error\n"); |
10510589 | 1334 | return -EPROTO; |
4754fcee | 1335 | } |
9d7d6f95 FL |
1336 | if (type == BRCMF_SDIO_FT_SUPER && |
1337 | (roundup(len, bus->blocksize) != rd->len)) { | |
5e8149f5 | 1338 | brcmf_err("HW superframe header length error\n"); |
10510589 | 1339 | return -EPROTO; |
9d7d6f95 FL |
1340 | } |
1341 | if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { | |
5e8149f5 | 1342 | brcmf_err("HW subframe header length error\n"); |
10510589 | 1343 | return -EPROTO; |
9d7d6f95 | 1344 | } |
4754fcee FL |
1345 | rd->len = len; |
1346 | ||
6bc52319 FL |
1347 | /* software header */ |
1348 | header += SDPCM_HWHDR_LEN; | |
1349 | swheader = le32_to_cpu(*(__le32 *)header); | |
1350 | if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { | |
5e8149f5 | 1351 | brcmf_err("Glom descriptor found in superframe head\n"); |
9d7d6f95 | 1352 | rd->len = 0; |
10510589 | 1353 | return -EINVAL; |
9d7d6f95 | 1354 | } |
6bc52319 FL |
1355 | rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); |
1356 | rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; | |
9d7d6f95 FL |
1357 | if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && |
1358 | type != BRCMF_SDIO_FT_SUPER) { | |
5e8149f5 | 1359 | brcmf_err("HW header length too long\n"); |
4754fcee | 1360 | bus->sdcnt.rx_toolong++; |
82d7f3c1 | 1361 | brcmf_sdio_rxfail(bus, false, false); |
4754fcee | 1362 | rd->len = 0; |
10510589 | 1363 | return -EPROTO; |
4754fcee | 1364 | } |
9d7d6f95 | 1365 | if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { |
5e8149f5 | 1366 | brcmf_err("Wrong channel for superframe\n"); |
9d7d6f95 | 1367 | rd->len = 0; |
10510589 | 1368 | return -EINVAL; |
9d7d6f95 FL |
1369 | } |
1370 | if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && | |
1371 | rd->channel != SDPCM_EVENT_CHANNEL) { | |
5e8149f5 | 1372 | brcmf_err("Wrong channel for subframe\n"); |
9d7d6f95 | 1373 | rd->len = 0; |
10510589 | 1374 | return -EINVAL; |
9d7d6f95 | 1375 | } |
6bc52319 | 1376 | rd->dat_offset = brcmf_sdio_getdatoffset(header); |
4754fcee | 1377 | if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { |
5e8149f5 | 1378 | brcmf_err("seq %d: bad data offset\n", rx_seq); |
4754fcee | 1379 | bus->sdcnt.rx_badhdr++; |
82d7f3c1 | 1380 | brcmf_sdio_rxfail(bus, false, false); |
4754fcee | 1381 | rd->len = 0; |
10510589 | 1382 | return -ENXIO; |
4754fcee FL |
1383 | } |
1384 | if (rd->seq_num != rx_seq) { | |
5e8149f5 | 1385 | brcmf_err("seq %d: sequence number error, expect %d\n", |
4754fcee FL |
1386 | rx_seq, rd->seq_num); |
1387 | bus->sdcnt.rx_badseq++; | |
1388 | rd->seq_num = rx_seq; | |
1389 | } | |
9d7d6f95 FL |
1390 | /* no need to check the reset for subframe */ |
1391 | if (type == BRCMF_SDIO_FT_SUB) | |
10510589 | 1392 | return 0; |
6bc52319 | 1393 | rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; |
4754fcee FL |
1394 | if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { |
1395 | /* only warm for NON glom packet */ | |
1396 | if (rd->channel != SDPCM_GLOM_CHANNEL) | |
5e8149f5 | 1397 | brcmf_err("seq %d: next length error\n", rx_seq); |
4754fcee FL |
1398 | rd->len_nxtfrm = 0; |
1399 | } | |
6bc52319 FL |
1400 | swheader = le32_to_cpu(*(__le32 *)(header + 4)); |
1401 | fc = swheader & SDPCM_FCMASK_MASK; | |
4754fcee FL |
1402 | if (bus->flowcontrol != fc) { |
1403 | if (~bus->flowcontrol & fc) | |
1404 | bus->sdcnt.fc_xoff++; | |
1405 | if (bus->flowcontrol & ~fc) | |
1406 | bus->sdcnt.fc_xon++; | |
1407 | bus->sdcnt.fc_rcvd++; | |
1408 | bus->flowcontrol = fc; | |
1409 | } | |
6bc52319 | 1410 | tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; |
4754fcee | 1411 | if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { |
5e8149f5 | 1412 | brcmf_err("seq %d: max tx seq number error\n", rx_seq); |
4754fcee FL |
1413 | tx_seq_max = bus->tx_seq + 2; |
1414 | } | |
1415 | bus->tx_max = tx_seq_max; | |
1416 | ||
10510589 | 1417 | return 0; |
4754fcee FL |
1418 | } |
1419 | ||
6bc52319 FL |
1420 | static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) |
1421 | { | |
1422 | *(__le16 *)header = cpu_to_le16(frm_length); | |
1423 | *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); | |
1424 | } | |
1425 | ||
1426 | static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, | |
1427 | struct brcmf_sdio_hdrinfo *hd_info) | |
1428 | { | |
8da9d2c8 FL |
1429 | u32 hdrval; |
1430 | u8 hdr_offset; | |
6bc52319 FL |
1431 | |
1432 | brcmf_sdio_update_hwhdr(header, hd_info->len); | |
8da9d2c8 FL |
1433 | hdr_offset = SDPCM_HWHDR_LEN; |
1434 | ||
1435 | if (bus->txglom) { | |
1436 | hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); | |
1437 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1438 | hdrval = (u16)hd_info->tail_pad << 16; | |
1439 | *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); | |
1440 | hdr_offset += SDPCM_HWEXT_LEN; | |
1441 | } | |
6bc52319 | 1442 | |
8da9d2c8 FL |
1443 | hdrval = hd_info->seq_num; |
1444 | hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & | |
1445 | SDPCM_CHANNEL_MASK; | |
1446 | hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & | |
1447 | SDPCM_DOFFSET_MASK; | |
1448 | *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); | |
1449 | *(((__le32 *)(header + hdr_offset)) + 1) = 0; | |
1450 | trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); | |
6bc52319 FL |
1451 | } |
1452 | ||
82d7f3c1 | 1453 | static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) |
5b435de0 AS |
1454 | { |
1455 | u16 dlen, totlen; | |
1456 | u8 *dptr, num = 0; | |
9d7d6f95 | 1457 | u16 sublen; |
0b45bf74 | 1458 | struct sk_buff *pfirst, *pnext; |
5b435de0 AS |
1459 | |
1460 | int errcode; | |
9d7d6f95 | 1461 | u8 doff, sfdoff; |
5b435de0 | 1462 | |
6bc52319 | 1463 | struct brcmf_sdio_hdrinfo rd_new; |
5b435de0 AS |
1464 | |
1465 | /* If packets, issue read(s) and send up packet chain */ | |
1466 | /* Return sequence numbers consumed? */ | |
1467 | ||
c3203374 | 1468 | brcmf_dbg(SDIO, "start: glomd %p glom %p\n", |
b83db862 | 1469 | bus->glomd, skb_peek(&bus->glom)); |
5b435de0 AS |
1470 | |
1471 | /* If there's a descriptor, generate the packet chain */ | |
1472 | if (bus->glomd) { | |
0b45bf74 | 1473 | pfirst = pnext = NULL; |
5b435de0 AS |
1474 | dlen = (u16) (bus->glomd->len); |
1475 | dptr = bus->glomd->data; | |
1476 | if (!dlen || (dlen & 1)) { | |
5e8149f5 | 1477 | brcmf_err("bad glomd len(%d), ignore descriptor\n", |
5b435de0 AS |
1478 | dlen); |
1479 | dlen = 0; | |
1480 | } | |
1481 | ||
1482 | for (totlen = num = 0; dlen; num++) { | |
1483 | /* Get (and move past) next length */ | |
1484 | sublen = get_unaligned_le16(dptr); | |
1485 | dlen -= sizeof(u16); | |
1486 | dptr += sizeof(u16); | |
1487 | if ((sublen < SDPCM_HDRLEN) || | |
1488 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
5e8149f5 | 1489 | brcmf_err("descriptor len %d bad: %d\n", |
5b435de0 AS |
1490 | num, sublen); |
1491 | pnext = NULL; | |
1492 | break; | |
1493 | } | |
e217d1c8 | 1494 | if (sublen % bus->sgentry_align) { |
5e8149f5 | 1495 | brcmf_err("sublen %d not multiple of %d\n", |
e217d1c8 | 1496 | sublen, bus->sgentry_align); |
5b435de0 AS |
1497 | } |
1498 | totlen += sublen; | |
1499 | ||
1500 | /* For last frame, adjust read len so total | |
1501 | is a block multiple */ | |
1502 | if (!dlen) { | |
1503 | sublen += | |
1504 | (roundup(totlen, bus->blocksize) - totlen); | |
1505 | totlen = roundup(totlen, bus->blocksize); | |
1506 | } | |
1507 | ||
1508 | /* Allocate/chain packet for next subframe */ | |
e217d1c8 | 1509 | pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); |
5b435de0 | 1510 | if (pnext == NULL) { |
5e8149f5 | 1511 | brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", |
5b435de0 AS |
1512 | num, sublen); |
1513 | break; | |
1514 | } | |
b83db862 | 1515 | skb_queue_tail(&bus->glom, pnext); |
5b435de0 AS |
1516 | |
1517 | /* Adhere to start alignment requirements */ | |
e217d1c8 | 1518 | pkt_align(pnext, sublen, bus->sgentry_align); |
5b435de0 AS |
1519 | } |
1520 | ||
1521 | /* If all allocations succeeded, save packet chain | |
1522 | in bus structure */ | |
1523 | if (pnext) { | |
1524 | brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", | |
1525 | totlen, num); | |
4754fcee FL |
1526 | if (BRCMF_GLOM_ON() && bus->cur_read.len && |
1527 | totlen != bus->cur_read.len) { | |
5b435de0 | 1528 | brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", |
4754fcee | 1529 | bus->cur_read.len, totlen, rxseq); |
5b435de0 | 1530 | } |
5b435de0 AS |
1531 | pfirst = pnext = NULL; |
1532 | } else { | |
82d7f3c1 | 1533 | brcmf_sdio_free_glom(bus); |
5b435de0 AS |
1534 | num = 0; |
1535 | } | |
1536 | ||
1537 | /* Done with descriptor packet */ | |
1538 | brcmu_pkt_buf_free_skb(bus->glomd); | |
1539 | bus->glomd = NULL; | |
4754fcee | 1540 | bus->cur_read.len = 0; |
5b435de0 AS |
1541 | } |
1542 | ||
1543 | /* Ok -- either we just generated a packet chain, | |
1544 | or had one from before */ | |
b83db862 | 1545 | if (!skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1546 | if (BRCMF_GLOM_ON()) { |
1547 | brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); | |
b83db862 | 1548 | skb_queue_walk(&bus->glom, pnext) { |
5b435de0 AS |
1549 | brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", |
1550 | pnext, (u8 *) (pnext->data), | |
1551 | pnext->len, pnext->len); | |
1552 | } | |
1553 | } | |
1554 | ||
b83db862 | 1555 | pfirst = skb_peek(&bus->glom); |
82d7f3c1 | 1556 | dlen = (u16) brcmf_sdio_glom_len(bus); |
5b435de0 AS |
1557 | |
1558 | /* Do an SDIO read for the superframe. Configurable iovar to | |
1559 | * read directly into the chained packet, or allocate a large | |
1560 | * packet and and copy into the chain. | |
1561 | */ | |
38b0b0dd | 1562 | sdio_claim_host(bus->sdiodev->func[1]); |
a39be27b | 1563 | errcode = brcmf_sdiod_recv_chain(bus->sdiodev, |
a39be27b | 1564 | &bus->glom, dlen); |
38b0b0dd | 1565 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 1566 | bus->sdcnt.f2rxdata++; |
5b435de0 | 1567 | |
64d66c30 | 1568 | /* On failure, kill the superframe */ |
5b435de0 | 1569 | if (errcode < 0) { |
5e8149f5 | 1570 | brcmf_err("glom read of %d bytes failed: %d\n", |
5b435de0 | 1571 | dlen, errcode); |
5b435de0 | 1572 | |
38b0b0dd | 1573 | sdio_claim_host(bus->sdiodev->func[1]); |
64d66c30 FL |
1574 | brcmf_sdio_rxfail(bus, true, false); |
1575 | bus->sdcnt.rxglomfail++; | |
1576 | brcmf_sdio_free_glom(bus); | |
38b0b0dd | 1577 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1578 | return 0; |
1579 | } | |
1e023829 JP |
1580 | |
1581 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), | |
1582 | pfirst->data, min_t(int, pfirst->len, 48), | |
1583 | "SUPERFRAME:\n"); | |
5b435de0 | 1584 | |
9d7d6f95 FL |
1585 | rd_new.seq_num = rxseq; |
1586 | rd_new.len = dlen; | |
38b0b0dd | 1587 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1588 | errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, |
1589 | BRCMF_SDIO_FT_SUPER); | |
38b0b0dd | 1590 | sdio_release_host(bus->sdiodev->func[1]); |
9d7d6f95 | 1591 | bus->cur_read.len = rd_new.len_nxtfrm << 4; |
5b435de0 AS |
1592 | |
1593 | /* Remove superframe header, remember offset */ | |
9d7d6f95 FL |
1594 | skb_pull(pfirst, rd_new.dat_offset); |
1595 | sfdoff = rd_new.dat_offset; | |
0b45bf74 | 1596 | num = 0; |
5b435de0 AS |
1597 | |
1598 | /* Validate all the subframe headers */ | |
0b45bf74 AS |
1599 | skb_queue_walk(&bus->glom, pnext) { |
1600 | /* leave when invalid subframe is found */ | |
1601 | if (errcode) | |
1602 | break; | |
1603 | ||
9d7d6f95 FL |
1604 | rd_new.len = pnext->len; |
1605 | rd_new.seq_num = rxseq++; | |
38b0b0dd | 1606 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1607 | errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, |
1608 | BRCMF_SDIO_FT_SUB); | |
38b0b0dd | 1609 | sdio_release_host(bus->sdiodev->func[1]); |
1e023829 | 1610 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
9d7d6f95 | 1611 | pnext->data, 32, "subframe:\n"); |
5b435de0 | 1612 | |
0b45bf74 | 1613 | num++; |
5b435de0 AS |
1614 | } |
1615 | ||
1616 | if (errcode) { | |
64d66c30 | 1617 | /* Terminate frame on error */ |
38b0b0dd | 1618 | sdio_claim_host(bus->sdiodev->func[1]); |
64d66c30 FL |
1619 | brcmf_sdio_rxfail(bus, true, false); |
1620 | bus->sdcnt.rxglomfail++; | |
1621 | brcmf_sdio_free_glom(bus); | |
38b0b0dd | 1622 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee | 1623 | bus->cur_read.len = 0; |
5b435de0 AS |
1624 | return 0; |
1625 | } | |
1626 | ||
1627 | /* Basic SD framing looks ok - process each packet (header) */ | |
5b435de0 | 1628 | |
0b45bf74 | 1629 | skb_queue_walk_safe(&bus->glom, pfirst, pnext) { |
5b435de0 AS |
1630 | dptr = (u8 *) (pfirst->data); |
1631 | sublen = get_unaligned_le16(dptr); | |
6bc52319 | 1632 | doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); |
5b435de0 | 1633 | |
1e023829 | 1634 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
9d7d6f95 FL |
1635 | dptr, pfirst->len, |
1636 | "Rx Subframe Data:\n"); | |
5b435de0 AS |
1637 | |
1638 | __skb_trim(pfirst, sublen); | |
1639 | skb_pull(pfirst, doff); | |
1640 | ||
1641 | if (pfirst->len == 0) { | |
0b45bf74 | 1642 | skb_unlink(pfirst, &bus->glom); |
5b435de0 | 1643 | brcmu_pkt_buf_free_skb(pfirst); |
5b435de0 | 1644 | continue; |
5b435de0 AS |
1645 | } |
1646 | ||
1e023829 JP |
1647 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
1648 | pfirst->data, | |
1649 | min_t(int, pfirst->len, 32), | |
1650 | "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", | |
1651 | bus->glom.qlen, pfirst, pfirst->data, | |
1652 | pfirst->len, pfirst->next, | |
1653 | pfirst->prev); | |
05f3820b | 1654 | skb_unlink(pfirst, &bus->glom); |
c56caa9d FL |
1655 | if (brcmf_sdio_fromevntchan(pfirst->data)) |
1656 | brcmf_rx_event(bus->sdiodev->dev, pfirst); | |
1657 | else | |
1658 | brcmf_rx_frame(bus->sdiodev->dev, pfirst, | |
1659 | false); | |
05f3820b | 1660 | bus->sdcnt.rxglompkts++; |
5b435de0 | 1661 | } |
5b435de0 | 1662 | |
80969836 | 1663 | bus->sdcnt.rxglomframes++; |
5b435de0 AS |
1664 | } |
1665 | return num; | |
1666 | } | |
1667 | ||
82d7f3c1 AS |
1668 | static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, |
1669 | bool *pending) | |
5b435de0 AS |
1670 | { |
1671 | DECLARE_WAITQUEUE(wait, current); | |
63ce3d5d | 1672 | int timeout = DCMD_RESP_TIMEOUT; |
5b435de0 AS |
1673 | |
1674 | /* Wait until control frame is available */ | |
1675 | add_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1676 | set_current_state(TASK_INTERRUPTIBLE); | |
1677 | ||
1678 | while (!(*condition) && (!signal_pending(current) && timeout)) | |
1679 | timeout = schedule_timeout(timeout); | |
1680 | ||
1681 | if (signal_pending(current)) | |
1682 | *pending = true; | |
1683 | ||
1684 | set_current_state(TASK_RUNNING); | |
1685 | remove_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1686 | ||
1687 | return timeout; | |
1688 | } | |
1689 | ||
82d7f3c1 | 1690 | static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) |
5b435de0 | 1691 | { |
a7decc44 | 1692 | wake_up_interruptible(&bus->dcmd_resp_wait); |
5b435de0 AS |
1693 | |
1694 | return 0; | |
1695 | } | |
1696 | static void | |
82d7f3c1 | 1697 | brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) |
5b435de0 AS |
1698 | { |
1699 | uint rdlen, pad; | |
dd43a01c | 1700 | u8 *buf = NULL, *rbuf; |
5b435de0 AS |
1701 | int sdret; |
1702 | ||
1703 | brcmf_dbg(TRACE, "Enter\n"); | |
1704 | ||
dd43a01c FL |
1705 | if (bus->rxblen) |
1706 | buf = vzalloc(bus->rxblen); | |
14f8dc49 | 1707 | if (!buf) |
dd43a01c | 1708 | goto done; |
14f8dc49 | 1709 | |
dd43a01c | 1710 | rbuf = bus->rxbuf; |
9b2d2f2a | 1711 | pad = ((unsigned long)rbuf % bus->head_align); |
5b435de0 | 1712 | if (pad) |
9b2d2f2a | 1713 | rbuf += (bus->head_align - pad); |
5b435de0 AS |
1714 | |
1715 | /* Copy the already-read portion over */ | |
dd43a01c | 1716 | memcpy(buf, hdr, BRCMF_FIRSTREAD); |
5b435de0 AS |
1717 | if (len <= BRCMF_FIRSTREAD) |
1718 | goto gotpkt; | |
1719 | ||
1720 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
1721 | rdlen = len - BRCMF_FIRSTREAD; | |
1722 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
1723 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1724 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
b01a6b3c | 1725 | ((len + pad) < bus->sdiodev->bus_if->maxctl)) |
5b435de0 | 1726 | rdlen += pad; |
9b2d2f2a AS |
1727 | } else if (rdlen % bus->head_align) { |
1728 | rdlen += bus->head_align - (rdlen % bus->head_align); | |
5b435de0 AS |
1729 | } |
1730 | ||
5b435de0 | 1731 | /* Drop if the read is too big or it exceeds our maximum */ |
b01a6b3c | 1732 | if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1733 | brcmf_err("%d-byte control read exceeds %d-byte buffer\n", |
b01a6b3c | 1734 | rdlen, bus->sdiodev->bus_if->maxctl); |
82d7f3c1 | 1735 | brcmf_sdio_rxfail(bus, false, false); |
5b435de0 AS |
1736 | goto done; |
1737 | } | |
1738 | ||
b01a6b3c | 1739 | if ((len - doff) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1740 | brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", |
b01a6b3c | 1741 | len, len - doff, bus->sdiodev->bus_if->maxctl); |
80969836 | 1742 | bus->sdcnt.rx_toolong++; |
82d7f3c1 | 1743 | brcmf_sdio_rxfail(bus, false, false); |
5b435de0 AS |
1744 | goto done; |
1745 | } | |
1746 | ||
dd43a01c | 1747 | /* Read remain of frame body */ |
a7cdd821 | 1748 | sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); |
80969836 | 1749 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1750 | |
1751 | /* Control frame failures need retransmission */ | |
1752 | if (sdret < 0) { | |
5e8149f5 | 1753 | brcmf_err("read %d control bytes failed: %d\n", |
5b435de0 | 1754 | rdlen, sdret); |
80969836 | 1755 | bus->sdcnt.rxc_errors++; |
82d7f3c1 | 1756 | brcmf_sdio_rxfail(bus, true, true); |
5b435de0 | 1757 | goto done; |
dd43a01c FL |
1758 | } else |
1759 | memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); | |
5b435de0 AS |
1760 | |
1761 | gotpkt: | |
1762 | ||
1e023829 | 1763 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
dd43a01c | 1764 | buf, len, "RxCtrl:\n"); |
5b435de0 AS |
1765 | |
1766 | /* Point to valid data and indicate its length */ | |
dd43a01c FL |
1767 | spin_lock_bh(&bus->rxctl_lock); |
1768 | if (bus->rxctl) { | |
5e8149f5 | 1769 | brcmf_err("last control frame is being processed.\n"); |
dd43a01c FL |
1770 | spin_unlock_bh(&bus->rxctl_lock); |
1771 | vfree(buf); | |
1772 | goto done; | |
1773 | } | |
1774 | bus->rxctl = buf + doff; | |
1775 | bus->rxctl_orig = buf; | |
5b435de0 | 1776 | bus->rxlen = len - doff; |
dd43a01c | 1777 | spin_unlock_bh(&bus->rxctl_lock); |
5b435de0 AS |
1778 | |
1779 | done: | |
1780 | /* Awake any waiters */ | |
82d7f3c1 | 1781 | brcmf_sdio_dcmd_resp_wake(bus); |
5b435de0 AS |
1782 | } |
1783 | ||
1784 | /* Pad read to blocksize for efficiency */ | |
82d7f3c1 | 1785 | static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) |
5b435de0 AS |
1786 | { |
1787 | if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { | |
1788 | *pad = bus->blocksize - (*rdlen % bus->blocksize); | |
1789 | if (*pad <= bus->roundup && *pad < bus->blocksize && | |
1790 | *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) | |
1791 | *rdlen += *pad; | |
9b2d2f2a AS |
1792 | } else if (*rdlen % bus->head_align) { |
1793 | *rdlen += bus->head_align - (*rdlen % bus->head_align); | |
5b435de0 AS |
1794 | } |
1795 | } | |
1796 | ||
4754fcee | 1797 | static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 | 1798 | { |
5b435de0 AS |
1799 | struct sk_buff *pkt; /* Packet for event or data frames */ |
1800 | u16 pad; /* Number of pad bytes to read */ | |
5b435de0 | 1801 | uint rxleft = 0; /* Remaining number of frames allowed */ |
349e7104 | 1802 | int ret; /* Return code from calls */ |
5b435de0 | 1803 | uint rxcount = 0; /* Total frames read */ |
6bc52319 | 1804 | struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; |
4754fcee | 1805 | u8 head_read = 0; |
5b435de0 AS |
1806 | |
1807 | brcmf_dbg(TRACE, "Enter\n"); | |
1808 | ||
1809 | /* Not finished unless we encounter no more frames indication */ | |
4754fcee | 1810 | bus->rxpending = true; |
5b435de0 | 1811 | |
4754fcee | 1812 | for (rd->seq_num = bus->rx_seq, rxleft = maxframes; |
a1ce7a0d | 1813 | !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; |
4754fcee | 1814 | rd->seq_num++, rxleft--) { |
5b435de0 AS |
1815 | |
1816 | /* Handle glomming separately */ | |
b83db862 | 1817 | if (bus->glomd || !skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1818 | u8 cnt; |
1819 | brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", | |
b83db862 | 1820 | bus->glomd, skb_peek(&bus->glom)); |
82d7f3c1 | 1821 | cnt = brcmf_sdio_rxglom(bus, rd->seq_num); |
5b435de0 | 1822 | brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); |
4754fcee | 1823 | rd->seq_num += cnt - 1; |
5b435de0 AS |
1824 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; |
1825 | continue; | |
1826 | } | |
1827 | ||
4754fcee FL |
1828 | rd->len_left = rd->len; |
1829 | /* read header first for unknow frame length */ | |
38b0b0dd | 1830 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee | 1831 | if (!rd->len) { |
a39be27b | 1832 | ret = brcmf_sdiod_recv_buf(bus->sdiodev, |
a39be27b | 1833 | bus->rxhdr, BRCMF_FIRSTREAD); |
4754fcee | 1834 | bus->sdcnt.f2rxhdrs++; |
349e7104 | 1835 | if (ret < 0) { |
5e8149f5 | 1836 | brcmf_err("RXHEADER FAILED: %d\n", |
349e7104 | 1837 | ret); |
4754fcee | 1838 | bus->sdcnt.rx_hdrfail++; |
82d7f3c1 | 1839 | brcmf_sdio_rxfail(bus, true, true); |
38b0b0dd | 1840 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1841 | continue; |
5b435de0 | 1842 | } |
5b435de0 | 1843 | |
4754fcee | 1844 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), |
1e023829 JP |
1845 | bus->rxhdr, SDPCM_HDRLEN, |
1846 | "RxHdr:\n"); | |
5b435de0 | 1847 | |
6bc52319 FL |
1848 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, |
1849 | BRCMF_SDIO_FT_NORMAL)) { | |
38b0b0dd | 1850 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1851 | if (!bus->rxpending) |
1852 | break; | |
1853 | else | |
1854 | continue; | |
5b435de0 AS |
1855 | } |
1856 | ||
4754fcee | 1857 | if (rd->channel == SDPCM_CONTROL_CHANNEL) { |
82d7f3c1 AS |
1858 | brcmf_sdio_read_control(bus, bus->rxhdr, |
1859 | rd->len, | |
1860 | rd->dat_offset); | |
4754fcee FL |
1861 | /* prepare the descriptor for the next read */ |
1862 | rd->len = rd->len_nxtfrm << 4; | |
1863 | rd->len_nxtfrm = 0; | |
1864 | /* treat all packet as event if we don't know */ | |
1865 | rd->channel = SDPCM_EVENT_CHANNEL; | |
38b0b0dd | 1866 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1867 | continue; |
1868 | } | |
4754fcee FL |
1869 | rd->len_left = rd->len > BRCMF_FIRSTREAD ? |
1870 | rd->len - BRCMF_FIRSTREAD : 0; | |
1871 | head_read = BRCMF_FIRSTREAD; | |
5b435de0 AS |
1872 | } |
1873 | ||
82d7f3c1 | 1874 | brcmf_sdio_pad(bus, &pad, &rd->len_left); |
5b435de0 | 1875 | |
4754fcee | 1876 | pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + |
9b2d2f2a | 1877 | bus->head_align); |
5b435de0 AS |
1878 | if (!pkt) { |
1879 | /* Give up on data, request rtx of events */ | |
5e8149f5 | 1880 | brcmf_err("brcmu_pkt_buf_get_skb failed\n"); |
82d7f3c1 | 1881 | brcmf_sdio_rxfail(bus, false, |
4754fcee | 1882 | RETRYCHAN(rd->channel)); |
38b0b0dd | 1883 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1884 | continue; |
1885 | } | |
4754fcee | 1886 | skb_pull(pkt, head_read); |
9b2d2f2a | 1887 | pkt_align(pkt, rd->len_left, bus->head_align); |
5b435de0 | 1888 | |
a7cdd821 | 1889 | ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); |
80969836 | 1890 | bus->sdcnt.f2rxdata++; |
38b0b0dd | 1891 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1892 | |
349e7104 | 1893 | if (ret < 0) { |
5e8149f5 | 1894 | brcmf_err("read %d bytes from channel %d failed: %d\n", |
349e7104 | 1895 | rd->len, rd->channel, ret); |
5b435de0 | 1896 | brcmu_pkt_buf_free_skb(pkt); |
38b0b0dd | 1897 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 1898 | brcmf_sdio_rxfail(bus, true, |
4754fcee | 1899 | RETRYCHAN(rd->channel)); |
38b0b0dd | 1900 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1901 | continue; |
1902 | } | |
1903 | ||
4754fcee FL |
1904 | if (head_read) { |
1905 | skb_push(pkt, head_read); | |
1906 | memcpy(pkt->data, bus->rxhdr, head_read); | |
1907 | head_read = 0; | |
1908 | } else { | |
1909 | memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); | |
1910 | rd_new.seq_num = rd->seq_num; | |
38b0b0dd | 1911 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1912 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, |
1913 | BRCMF_SDIO_FT_NORMAL)) { | |
4754fcee FL |
1914 | rd->len = 0; |
1915 | brcmu_pkt_buf_free_skb(pkt); | |
1916 | } | |
1917 | bus->sdcnt.rx_readahead_cnt++; | |
1918 | if (rd->len != roundup(rd_new.len, 16)) { | |
5e8149f5 | 1919 | brcmf_err("frame length mismatch:read %d, should be %d\n", |
4754fcee FL |
1920 | rd->len, |
1921 | roundup(rd_new.len, 16) >> 4); | |
1922 | rd->len = 0; | |
82d7f3c1 | 1923 | brcmf_sdio_rxfail(bus, true, true); |
38b0b0dd | 1924 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1925 | brcmu_pkt_buf_free_skb(pkt); |
1926 | continue; | |
1927 | } | |
38b0b0dd | 1928 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1929 | rd->len_nxtfrm = rd_new.len_nxtfrm; |
1930 | rd->channel = rd_new.channel; | |
1931 | rd->dat_offset = rd_new.dat_offset; | |
1932 | ||
1933 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && | |
1934 | BRCMF_DATA_ON()) && | |
1935 | BRCMF_HDRS_ON(), | |
1936 | bus->rxhdr, SDPCM_HDRLEN, | |
1937 | "RxHdr:\n"); | |
1938 | ||
1939 | if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { | |
5e8149f5 | 1940 | brcmf_err("readahead on control packet %d?\n", |
4754fcee FL |
1941 | rd_new.seq_num); |
1942 | /* Force retry w/normal header read */ | |
1943 | rd->len = 0; | |
38b0b0dd | 1944 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 1945 | brcmf_sdio_rxfail(bus, false, true); |
38b0b0dd | 1946 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1947 | brcmu_pkt_buf_free_skb(pkt); |
1948 | continue; | |
1949 | } | |
1950 | } | |
5b435de0 | 1951 | |
1e023829 | 1952 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
4754fcee | 1953 | pkt->data, rd->len, "Rx Data:\n"); |
5b435de0 | 1954 | |
5b435de0 | 1955 | /* Save superframe descriptor and allocate packet frame */ |
4754fcee | 1956 | if (rd->channel == SDPCM_GLOM_CHANNEL) { |
6bc52319 | 1957 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { |
5b435de0 | 1958 | brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", |
4754fcee | 1959 | rd->len); |
1e023829 | 1960 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
4754fcee | 1961 | pkt->data, rd->len, |
1e023829 | 1962 | "Glom Data:\n"); |
4754fcee | 1963 | __skb_trim(pkt, rd->len); |
5b435de0 AS |
1964 | skb_pull(pkt, SDPCM_HDRLEN); |
1965 | bus->glomd = pkt; | |
1966 | } else { | |
5e8149f5 | 1967 | brcmf_err("%s: glom superframe w/o " |
5b435de0 | 1968 | "descriptor!\n", __func__); |
38b0b0dd | 1969 | sdio_claim_host(bus->sdiodev->func[1]); |
82d7f3c1 | 1970 | brcmf_sdio_rxfail(bus, false, false); |
38b0b0dd | 1971 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1972 | } |
4754fcee FL |
1973 | /* prepare the descriptor for the next read */ |
1974 | rd->len = rd->len_nxtfrm << 4; | |
1975 | rd->len_nxtfrm = 0; | |
1976 | /* treat all packet as event if we don't know */ | |
1977 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
1978 | continue; |
1979 | } | |
1980 | ||
1981 | /* Fill in packet len and prio, deliver upward */ | |
4754fcee FL |
1982 | __skb_trim(pkt, rd->len); |
1983 | skb_pull(pkt, rd->dat_offset); | |
1984 | ||
c56caa9d FL |
1985 | if (pkt->len == 0) |
1986 | brcmu_pkt_buf_free_skb(pkt); | |
1987 | else if (rd->channel == SDPCM_EVENT_CHANNEL) | |
1988 | brcmf_rx_event(bus->sdiodev->dev, pkt); | |
1989 | else | |
1990 | brcmf_rx_frame(bus->sdiodev->dev, pkt, | |
1991 | false); | |
1992 | ||
4754fcee FL |
1993 | /* prepare the descriptor for the next read */ |
1994 | rd->len = rd->len_nxtfrm << 4; | |
1995 | rd->len_nxtfrm = 0; | |
1996 | /* treat all packet as event if we don't know */ | |
1997 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 | 1998 | } |
4754fcee | 1999 | |
5b435de0 | 2000 | rxcount = maxframes - rxleft; |
5b435de0 AS |
2001 | /* Message if we hit the limit */ |
2002 | if (!rxleft) | |
4754fcee | 2003 | brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); |
5b435de0 | 2004 | else |
5b435de0 AS |
2005 | brcmf_dbg(DATA, "processed %d frames\n", rxcount); |
2006 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
2007 | if (bus->rxskip) | |
4754fcee FL |
2008 | rd->seq_num--; |
2009 | bus->rx_seq = rd->seq_num; | |
5b435de0 AS |
2010 | |
2011 | return rxcount; | |
2012 | } | |
2013 | ||
5b435de0 | 2014 | static void |
82d7f3c1 | 2015 | brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) |
5b435de0 | 2016 | { |
a7decc44 | 2017 | wake_up_interruptible(&bus->ctrl_wait); |
5b435de0 AS |
2018 | return; |
2019 | } | |
2020 | ||
8da9d2c8 FL |
2021 | static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) |
2022 | { | |
e217d1c8 | 2023 | u16 head_pad; |
8da9d2c8 FL |
2024 | u8 *dat_buf; |
2025 | ||
8da9d2c8 FL |
2026 | dat_buf = (u8 *)(pkt->data); |
2027 | ||
2028 | /* Check head padding */ | |
e217d1c8 | 2029 | head_pad = ((unsigned long)dat_buf % bus->head_align); |
8da9d2c8 FL |
2030 | if (head_pad) { |
2031 | if (skb_headroom(pkt) < head_pad) { | |
2032 | bus->sdiodev->bus_if->tx_realloc++; | |
2033 | head_pad = 0; | |
2034 | if (skb_cow(pkt, head_pad)) | |
2035 | return -ENOMEM; | |
2036 | } | |
2037 | skb_push(pkt, head_pad); | |
2038 | dat_buf = (u8 *)(pkt->data); | |
2039 | memset(dat_buf, 0, head_pad + bus->tx_hdrlen); | |
2040 | } | |
2041 | return head_pad; | |
2042 | } | |
2043 | ||
5491c11c FL |
2044 | /** |
2045 | * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for | |
2046 | * bus layer usage. | |
2047 | */ | |
b05e9254 | 2048 | /* flag marking a dummy skb added for DMA alignment requirement */ |
5491c11c | 2049 | #define ALIGN_SKB_FLAG 0x8000 |
b05e9254 | 2050 | /* bit mask of data length chopped from the previous packet */ |
5491c11c FL |
2051 | #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff |
2052 | ||
8da9d2c8 | 2053 | static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, |
a64304f0 | 2054 | struct sk_buff_head *pktq, |
8da9d2c8 | 2055 | struct sk_buff *pkt, u16 total_len) |
a64304f0 | 2056 | { |
8da9d2c8 | 2057 | struct brcmf_sdio_dev *sdiodev; |
a64304f0 | 2058 | struct sk_buff *pkt_pad; |
e217d1c8 | 2059 | u16 tail_pad, tail_chop, chain_pad; |
a64304f0 | 2060 | unsigned int blksize; |
8da9d2c8 FL |
2061 | bool lastfrm; |
2062 | int ntail, ret; | |
a64304f0 | 2063 | |
8da9d2c8 | 2064 | sdiodev = bus->sdiodev; |
a64304f0 | 2065 | blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize; |
a64304f0 | 2066 | /* sg entry alignment should be a divisor of block size */ |
e217d1c8 | 2067 | WARN_ON(blksize % bus->sgentry_align); |
a64304f0 AS |
2068 | |
2069 | /* Check tail padding */ | |
8da9d2c8 FL |
2070 | lastfrm = skb_queue_is_last(pktq, pkt); |
2071 | tail_pad = 0; | |
e217d1c8 | 2072 | tail_chop = pkt->len % bus->sgentry_align; |
8da9d2c8 | 2073 | if (tail_chop) |
e217d1c8 | 2074 | tail_pad = bus->sgentry_align - tail_chop; |
8da9d2c8 FL |
2075 | chain_pad = (total_len + tail_pad) % blksize; |
2076 | if (lastfrm && chain_pad) | |
2077 | tail_pad += blksize - chain_pad; | |
a64304f0 | 2078 | if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { |
1eb43018 AS |
2079 | pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + |
2080 | bus->head_align); | |
a64304f0 AS |
2081 | if (pkt_pad == NULL) |
2082 | return -ENOMEM; | |
8da9d2c8 | 2083 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); |
2dc3a8e0 DJ |
2084 | if (unlikely(ret < 0)) { |
2085 | kfree_skb(pkt_pad); | |
8da9d2c8 | 2086 | return ret; |
2dc3a8e0 | 2087 | } |
a64304f0 AS |
2088 | memcpy(pkt_pad->data, |
2089 | pkt->data + pkt->len - tail_chop, | |
2090 | tail_chop); | |
5aa9f0ea | 2091 | *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; |
a64304f0 | 2092 | skb_trim(pkt, pkt->len - tail_chop); |
1eb43018 | 2093 | skb_trim(pkt_pad, tail_pad + tail_chop); |
a64304f0 AS |
2094 | __skb_queue_after(pktq, pkt, pkt_pad); |
2095 | } else { | |
2096 | ntail = pkt->data_len + tail_pad - | |
2097 | (pkt->end - pkt->tail); | |
2098 | if (skb_cloned(pkt) || ntail > 0) | |
2099 | if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) | |
2100 | return -ENOMEM; | |
2101 | if (skb_linearize(pkt)) | |
2102 | return -ENOMEM; | |
a64304f0 AS |
2103 | __skb_put(pkt, tail_pad); |
2104 | } | |
2105 | ||
8da9d2c8 | 2106 | return tail_pad; |
a64304f0 AS |
2107 | } |
2108 | ||
b05e9254 FL |
2109 | /** |
2110 | * brcmf_sdio_txpkt_prep - packet preparation for transmit | |
2111 | * @bus: brcmf_sdio structure pointer | |
2112 | * @pktq: packet list pointer | |
2113 | * @chan: virtual channel to transmit the packet | |
2114 | * | |
2115 | * Processes to be applied to the packet | |
2116 | * - Align data buffer pointer | |
2117 | * - Align data buffer length | |
2118 | * - Prepare header | |
2119 | * Return: negative value if there is error | |
2120 | */ | |
2121 | static int | |
2122 | brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, | |
2123 | uint chan) | |
5b435de0 | 2124 | { |
8da9d2c8 | 2125 | u16 head_pad, total_len; |
a64304f0 | 2126 | struct sk_buff *pkt_next; |
8da9d2c8 FL |
2127 | u8 txseq; |
2128 | int ret; | |
6bc52319 | 2129 | struct brcmf_sdio_hdrinfo hd_info = {0}; |
b05e9254 | 2130 | |
8da9d2c8 FL |
2131 | txseq = bus->tx_seq; |
2132 | total_len = 0; | |
2133 | skb_queue_walk(pktq, pkt_next) { | |
2134 | /* alignment packet inserted in previous | |
2135 | * loop cycle can be skipped as it is | |
2136 | * already properly aligned and does not | |
2137 | * need an sdpcm header. | |
2138 | */ | |
5aa9f0ea | 2139 | if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) |
8da9d2c8 | 2140 | continue; |
5b435de0 | 2141 | |
8da9d2c8 FL |
2142 | /* align packet data pointer */ |
2143 | ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); | |
2144 | if (ret < 0) | |
2145 | return ret; | |
2146 | head_pad = (u16)ret; | |
2147 | if (head_pad) | |
1eb43018 | 2148 | memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); |
5b435de0 | 2149 | |
8da9d2c8 | 2150 | total_len += pkt_next->len; |
5b435de0 | 2151 | |
a64304f0 | 2152 | hd_info.len = pkt_next->len; |
8da9d2c8 FL |
2153 | hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); |
2154 | if (bus->txglom && pktq->qlen > 1) { | |
2155 | ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, | |
2156 | pkt_next, total_len); | |
2157 | if (ret < 0) | |
2158 | return ret; | |
2159 | hd_info.tail_pad = (u16)ret; | |
2160 | total_len += (u16)ret; | |
2161 | } | |
5b435de0 | 2162 | |
8da9d2c8 FL |
2163 | hd_info.channel = chan; |
2164 | hd_info.dat_offset = head_pad + bus->tx_hdrlen; | |
2165 | hd_info.seq_num = txseq++; | |
2166 | ||
2167 | /* Now fill the header */ | |
2168 | brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); | |
2169 | ||
2170 | if (BRCMF_BYTES_ON() && | |
2171 | ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || | |
2172 | (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) | |
47ab4cd8 | 2173 | brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, |
8da9d2c8 FL |
2174 | "Tx Frame:\n"); |
2175 | else if (BRCMF_HDRS_ON()) | |
47ab4cd8 | 2176 | brcmf_dbg_hex_dump(true, pkt_next->data, |
8da9d2c8 FL |
2177 | head_pad + bus->tx_hdrlen, |
2178 | "Tx Header:\n"); | |
2179 | } | |
2180 | /* Hardware length tag of the first packet should be total | |
2181 | * length of the chain (including padding) | |
2182 | */ | |
2183 | if (bus->txglom) | |
2184 | brcmf_sdio_update_hwhdr(pktq->next->data, total_len); | |
b05e9254 FL |
2185 | return 0; |
2186 | } | |
5b435de0 | 2187 | |
b05e9254 FL |
2188 | /** |
2189 | * brcmf_sdio_txpkt_postp - packet post processing for transmit | |
2190 | * @bus: brcmf_sdio structure pointer | |
2191 | * @pktq: packet list pointer | |
2192 | * | |
2193 | * Processes to be applied to the packet | |
2194 | * - Remove head padding | |
2195 | * - Remove tail padding | |
2196 | */ | |
2197 | static void | |
2198 | brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) | |
2199 | { | |
2200 | u8 *hdr; | |
2201 | u32 dat_offset; | |
8da9d2c8 | 2202 | u16 tail_pad; |
5aa9f0ea | 2203 | u16 dummy_flags, chop_len; |
b05e9254 FL |
2204 | struct sk_buff *pkt_next, *tmp, *pkt_prev; |
2205 | ||
2206 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
5aa9f0ea | 2207 | dummy_flags = *(u16 *)(pkt_next->cb); |
5491c11c FL |
2208 | if (dummy_flags & ALIGN_SKB_FLAG) { |
2209 | chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; | |
b05e9254 FL |
2210 | if (chop_len) { |
2211 | pkt_prev = pkt_next->prev; | |
b05e9254 FL |
2212 | skb_put(pkt_prev, chop_len); |
2213 | } | |
2214 | __skb_unlink(pkt_next, pktq); | |
2215 | brcmu_pkt_buf_free_skb(pkt_next); | |
2216 | } else { | |
8da9d2c8 | 2217 | hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; |
b05e9254 FL |
2218 | dat_offset = le32_to_cpu(*(__le32 *)hdr); |
2219 | dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> | |
2220 | SDPCM_DOFFSET_SHIFT; | |
2221 | skb_pull(pkt_next, dat_offset); | |
8da9d2c8 FL |
2222 | if (bus->txglom) { |
2223 | tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); | |
2224 | skb_trim(pkt_next, pkt_next->len - tail_pad); | |
2225 | } | |
b05e9254 | 2226 | } |
5b435de0 | 2227 | } |
b05e9254 | 2228 | } |
5b435de0 | 2229 | |
b05e9254 FL |
2230 | /* Writes a HW/SW header into the packet and sends it. */ |
2231 | /* Assumes: (a) header space already there, (b) caller holds lock */ | |
82d7f3c1 AS |
2232 | static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, |
2233 | uint chan) | |
b05e9254 FL |
2234 | { |
2235 | int ret; | |
8da9d2c8 | 2236 | struct sk_buff *pkt_next, *tmp; |
b05e9254 FL |
2237 | |
2238 | brcmf_dbg(TRACE, "Enter\n"); | |
2239 | ||
8da9d2c8 | 2240 | ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); |
b05e9254 FL |
2241 | if (ret) |
2242 | goto done; | |
5b435de0 | 2243 | |
38b0b0dd | 2244 | sdio_claim_host(bus->sdiodev->func[1]); |
a7cdd821 | 2245 | ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); |
80969836 | 2246 | bus->sdcnt.f2txdata++; |
5b435de0 | 2247 | |
81c7883c HM |
2248 | if (ret < 0) |
2249 | brcmf_sdio_txfail(bus); | |
5b435de0 | 2250 | |
38b0b0dd | 2251 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2252 | |
2253 | done: | |
8da9d2c8 FL |
2254 | brcmf_sdio_txpkt_postp(bus, pktq); |
2255 | if (ret == 0) | |
2256 | bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; | |
2257 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
2258 | __skb_unlink(pkt_next, pktq); | |
2259 | brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0); | |
2260 | } | |
5b435de0 AS |
2261 | return ret; |
2262 | } | |
2263 | ||
82d7f3c1 | 2264 | static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 AS |
2265 | { |
2266 | struct sk_buff *pkt; | |
8da9d2c8 | 2267 | struct sk_buff_head pktq; |
5b435de0 | 2268 | u32 intstatus = 0; |
8da9d2c8 | 2269 | int ret = 0, prec_out, i; |
5b435de0 | 2270 | uint cnt = 0; |
8da9d2c8 | 2271 | u8 tx_prec_map, pkt_num; |
5b435de0 | 2272 | |
5b435de0 AS |
2273 | brcmf_dbg(TRACE, "Enter\n"); |
2274 | ||
2275 | tx_prec_map = ~bus->flowcontrol; | |
2276 | ||
2277 | /* Send frames until the limit or some other event */ | |
8da9d2c8 FL |
2278 | for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { |
2279 | pkt_num = 1; | |
8da9d2c8 FL |
2280 | if (bus->txglom) |
2281 | pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, | |
af1fa210 | 2282 | bus->sdiodev->txglomsz); |
8da9d2c8 FL |
2283 | pkt_num = min_t(u32, pkt_num, |
2284 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); | |
fed7ec44 HM |
2285 | __skb_queue_head_init(&pktq); |
2286 | spin_lock_bh(&bus->txq_lock); | |
8da9d2c8 FL |
2287 | for (i = 0; i < pkt_num; i++) { |
2288 | pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, | |
2289 | &prec_out); | |
2290 | if (pkt == NULL) | |
2291 | break; | |
2292 | __skb_queue_tail(&pktq, pkt); | |
5b435de0 | 2293 | } |
fed7ec44 | 2294 | spin_unlock_bh(&bus->txq_lock); |
4dd8b26a | 2295 | if (i == 0) |
8da9d2c8 | 2296 | break; |
5b435de0 | 2297 | |
82d7f3c1 | 2298 | ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); |
fed7ec44 | 2299 | |
8da9d2c8 | 2300 | cnt += i; |
5b435de0 AS |
2301 | |
2302 | /* In poll mode, need to check for other events */ | |
b6a8cf2c | 2303 | if (!bus->intr) { |
5b435de0 | 2304 | /* Check device status, signal pending interrupt */ |
38b0b0dd | 2305 | sdio_claim_host(bus->sdiodev->func[1]); |
5c15c23a FL |
2306 | ret = r_sdreg32(bus, &intstatus, |
2307 | offsetof(struct sdpcmd_regs, | |
2308 | intstatus)); | |
38b0b0dd | 2309 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 2310 | bus->sdcnt.f2txdata++; |
5c15c23a | 2311 | if (ret != 0) |
5b435de0 AS |
2312 | break; |
2313 | if (intstatus & bus->hostintmask) | |
1d382273 | 2314 | atomic_set(&bus->ipend, 1); |
5b435de0 AS |
2315 | } |
2316 | } | |
2317 | ||
2318 | /* Deflow-control stack if needed */ | |
a1ce7a0d | 2319 | if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && |
c8bf3484 | 2320 | bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { |
90d03ff7 HM |
2321 | bus->txoff = false; |
2322 | brcmf_txflowblock(bus->sdiodev->dev, false); | |
c8bf3484 | 2323 | } |
5b435de0 AS |
2324 | |
2325 | return cnt; | |
2326 | } | |
2327 | ||
fed7ec44 HM |
2328 | static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) |
2329 | { | |
2330 | u8 doff; | |
2331 | u16 pad; | |
2332 | uint retries = 0; | |
2333 | struct brcmf_sdio_hdrinfo hd_info = {0}; | |
2334 | int ret; | |
2335 | ||
2336 | brcmf_dbg(TRACE, "Enter\n"); | |
2337 | ||
2338 | /* Back the pointer to make room for bus header */ | |
2339 | frame -= bus->tx_hdrlen; | |
2340 | len += bus->tx_hdrlen; | |
2341 | ||
2342 | /* Add alignment padding (optional for ctl frames) */ | |
2343 | doff = ((unsigned long)frame % bus->head_align); | |
2344 | if (doff) { | |
2345 | frame -= doff; | |
2346 | len += doff; | |
2347 | memset(frame + bus->tx_hdrlen, 0, doff); | |
2348 | } | |
2349 | ||
2350 | /* Round send length to next SDIO block */ | |
2351 | pad = 0; | |
2352 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2353 | pad = bus->blocksize - (len % bus->blocksize); | |
2354 | if ((pad > bus->roundup) || (pad >= bus->blocksize)) | |
2355 | pad = 0; | |
2356 | } else if (len % bus->head_align) { | |
2357 | pad = bus->head_align - (len % bus->head_align); | |
2358 | } | |
2359 | len += pad; | |
2360 | ||
2361 | hd_info.len = len - pad; | |
2362 | hd_info.channel = SDPCM_CONTROL_CHANNEL; | |
2363 | hd_info.dat_offset = doff + bus->tx_hdrlen; | |
2364 | hd_info.seq_num = bus->tx_seq; | |
2365 | hd_info.lastfrm = true; | |
2366 | hd_info.tail_pad = pad; | |
2367 | brcmf_sdio_hdpack(bus, frame, &hd_info); | |
2368 | ||
2369 | if (bus->txglom) | |
2370 | brcmf_sdio_update_hwhdr(frame, len); | |
2371 | ||
2372 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), | |
2373 | frame, len, "Tx Frame:\n"); | |
2374 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && | |
2375 | BRCMF_HDRS_ON(), | |
2376 | frame, min_t(u16, len, 16), "TxHdr:\n"); | |
2377 | ||
2378 | do { | |
2379 | ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); | |
2380 | ||
2381 | if (ret < 0) | |
2382 | brcmf_sdio_txfail(bus); | |
2383 | else | |
2384 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; | |
2385 | } while (ret < 0 && retries++ < TXRETRIES); | |
2386 | ||
2387 | return ret; | |
2388 | } | |
2389 | ||
82d7f3c1 | 2390 | static void brcmf_sdio_bus_stop(struct device *dev) |
a9ffda88 FL |
2391 | { |
2392 | u32 local_hostintmask; | |
2393 | u8 saveclk; | |
a9ffda88 FL |
2394 | int err; |
2395 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
0a332e46 | 2396 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
a9ffda88 FL |
2397 | struct brcmf_sdio *bus = sdiodev->bus; |
2398 | ||
2399 | brcmf_dbg(TRACE, "Enter\n"); | |
2400 | ||
2401 | if (bus->watchdog_tsk) { | |
2402 | send_sig(SIGTERM, bus->watchdog_tsk, 1); | |
2403 | kthread_stop(bus->watchdog_tsk); | |
2404 | bus->watchdog_tsk = NULL; | |
2405 | } | |
2406 | ||
a1ce7a0d | 2407 | if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { |
bb350711 AS |
2408 | sdio_claim_host(sdiodev->func[1]); |
2409 | ||
2410 | /* Enable clock for device interrupts */ | |
2411 | brcmf_sdio_bus_sleep(bus, false, false); | |
2412 | ||
2413 | /* Disable and clear interrupts at the chip level also */ | |
2414 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask)); | |
2415 | local_hostintmask = bus->hostintmask; | |
2416 | bus->hostintmask = 0; | |
2417 | ||
2418 | /* Force backplane clocks to assure F2 interrupt propagates */ | |
2419 | saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
2420 | &err); | |
2421 | if (!err) | |
2422 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
2423 | (saveclk | SBSDIO_FORCE_HT), &err); | |
2424 | if (err) | |
2425 | brcmf_err("Failed to force clock for F2: err %d\n", | |
2426 | err); | |
a9ffda88 | 2427 | |
bb350711 AS |
2428 | /* Turn off the bus (F2), free any pending packets */ |
2429 | brcmf_dbg(INTR, "disable SDIO interrupts\n"); | |
2430 | sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); | |
a9ffda88 | 2431 | |
bb350711 AS |
2432 | /* Clear any pending interrupts now that F2 is disabled */ |
2433 | w_sdreg32(bus, local_hostintmask, | |
2434 | offsetof(struct sdpcmd_regs, intstatus)); | |
a9ffda88 | 2435 | |
bb350711 | 2436 | sdio_release_host(sdiodev->func[1]); |
a9ffda88 | 2437 | } |
a9ffda88 FL |
2438 | /* Clear the data packet queues */ |
2439 | brcmu_pktq_flush(&bus->txq, true, NULL, NULL); | |
2440 | ||
2441 | /* Clear any held glomming stuff */ | |
297540f6 | 2442 | brcmu_pkt_buf_free_skb(bus->glomd); |
82d7f3c1 | 2443 | brcmf_sdio_free_glom(bus); |
a9ffda88 FL |
2444 | |
2445 | /* Clear rx control and wake any waiters */ | |
dd43a01c | 2446 | spin_lock_bh(&bus->rxctl_lock); |
a9ffda88 | 2447 | bus->rxlen = 0; |
dd43a01c | 2448 | spin_unlock_bh(&bus->rxctl_lock); |
82d7f3c1 | 2449 | brcmf_sdio_dcmd_resp_wake(bus); |
a9ffda88 FL |
2450 | |
2451 | /* Reset some F2 state stuff */ | |
2452 | bus->rxskip = false; | |
2453 | bus->tx_seq = bus->rx_seq = 0; | |
a9ffda88 FL |
2454 | } |
2455 | ||
82d7f3c1 | 2456 | static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) |
ba89bf19 | 2457 | { |
af5b5e62 | 2458 | struct brcmf_sdio_dev *sdiodev; |
ba89bf19 FL |
2459 | unsigned long flags; |
2460 | ||
af5b5e62 HM |
2461 | sdiodev = bus->sdiodev; |
2462 | if (sdiodev->oob_irq_requested) { | |
2463 | spin_lock_irqsave(&sdiodev->irq_en_lock, flags); | |
2464 | if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) { | |
2465 | enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr); | |
2466 | sdiodev->irq_en = true; | |
668761ac | 2467 | } |
af5b5e62 | 2468 | spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags); |
ba89bf19 | 2469 | } |
ba89bf19 | 2470 | } |
ba89bf19 | 2471 | |
4531603a FL |
2472 | static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) |
2473 | { | |
cb7cf7be | 2474 | struct brcmf_core *buscore; |
4531603a FL |
2475 | u32 addr; |
2476 | unsigned long val; | |
5cbb9c28 | 2477 | int ret; |
4531603a | 2478 | |
cb7cf7be AS |
2479 | buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); |
2480 | addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus); | |
4531603a | 2481 | |
a39be27b | 2482 | val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret); |
4531603a FL |
2483 | bus->sdcnt.f1regdata++; |
2484 | if (ret != 0) | |
5cbb9c28 | 2485 | return ret; |
4531603a FL |
2486 | |
2487 | val &= bus->hostintmask; | |
2488 | atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); | |
2489 | ||
2490 | /* Clear interrupts */ | |
2491 | if (val) { | |
a39be27b | 2492 | brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret); |
4531603a | 2493 | bus->sdcnt.f1regdata++; |
d3928d09 | 2494 | atomic_or(val, &bus->intstatus); |
4531603a FL |
2495 | } |
2496 | ||
2497 | return ret; | |
2498 | } | |
2499 | ||
82d7f3c1 | 2500 | static void brcmf_sdio_dpc(struct brcmf_sdio *bus) |
5b435de0 | 2501 | { |
4531603a FL |
2502 | u32 newstatus = 0; |
2503 | unsigned long intstatus; | |
5b435de0 | 2504 | uint txlimit = bus->txbound; /* Tx frames to send before resched */ |
b6a8cf2c | 2505 | uint framecnt; /* Temporary counter of tx/rx frames */ |
5cbb9c28 | 2506 | int err = 0; |
5b435de0 AS |
2507 | |
2508 | brcmf_dbg(TRACE, "Enter\n"); | |
2509 | ||
38b0b0dd | 2510 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2511 | |
2512 | /* If waiting for HTAVAIL, check status */ | |
4a3da990 | 2513 | if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { |
5b435de0 AS |
2514 | u8 clkctl, devctl = 0; |
2515 | ||
8ae74654 | 2516 | #ifdef DEBUG |
5b435de0 | 2517 | /* Check for inconsistent device control */ |
a39be27b AS |
2518 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
2519 | SBSDIO_DEVICE_CTL, &err); | |
8ae74654 | 2520 | #endif /* DEBUG */ |
5b435de0 AS |
2521 | |
2522 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
a39be27b AS |
2523 | clkctl = brcmf_sdiod_regrb(bus->sdiodev, |
2524 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 2525 | |
c3203374 | 2526 | brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", |
5b435de0 AS |
2527 | devctl, clkctl); |
2528 | ||
2529 | if (SBSDIO_HTAV(clkctl)) { | |
a39be27b AS |
2530 | devctl = brcmf_sdiod_regrb(bus->sdiodev, |
2531 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 2532 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
a39be27b AS |
2533 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
2534 | devctl, &err); | |
5b435de0 | 2535 | bus->clkstate = CLK_AVAIL; |
5b435de0 AS |
2536 | } |
2537 | } | |
2538 | ||
5b435de0 | 2539 | /* Make sure backplane clock is on */ |
82d7f3c1 | 2540 | brcmf_sdio_bus_sleep(bus, false, true); |
5b435de0 AS |
2541 | |
2542 | /* Pending interrupt indicates new device status */ | |
1d382273 FL |
2543 | if (atomic_read(&bus->ipend) > 0) { |
2544 | atomic_set(&bus->ipend, 0); | |
4531603a | 2545 | err = brcmf_sdio_intr_rstatus(bus); |
5b435de0 AS |
2546 | } |
2547 | ||
4531603a FL |
2548 | /* Start with leftover status bits */ |
2549 | intstatus = atomic_xchg(&bus->intstatus, 0); | |
5b435de0 AS |
2550 | |
2551 | /* Handle flow-control change: read new state in case our ack | |
2552 | * crossed another change interrupt. If change still set, assume | |
2553 | * FC ON for safety, let next loop through do the debounce. | |
2554 | */ | |
2555 | if (intstatus & I_HMB_FC_CHANGE) { | |
2556 | intstatus &= ~I_HMB_FC_CHANGE; | |
5c15c23a FL |
2557 | err = w_sdreg32(bus, I_HMB_FC_CHANGE, |
2558 | offsetof(struct sdpcmd_regs, intstatus)); | |
5b435de0 | 2559 | |
5c15c23a FL |
2560 | err = r_sdreg32(bus, &newstatus, |
2561 | offsetof(struct sdpcmd_regs, intstatus)); | |
80969836 | 2562 | bus->sdcnt.f1regdata += 2; |
4531603a FL |
2563 | atomic_set(&bus->fcstate, |
2564 | !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); | |
5b435de0 AS |
2565 | intstatus |= (newstatus & bus->hostintmask); |
2566 | } | |
2567 | ||
2568 | /* Handle host mailbox indication */ | |
2569 | if (intstatus & I_HMB_HOST_INT) { | |
2570 | intstatus &= ~I_HMB_HOST_INT; | |
82d7f3c1 | 2571 | intstatus |= brcmf_sdio_hostmail(bus); |
5b435de0 AS |
2572 | } |
2573 | ||
38b0b0dd | 2574 | sdio_release_host(bus->sdiodev->func[1]); |
7cdf57d3 | 2575 | |
5b435de0 AS |
2576 | /* Generally don't ask for these, can get CRC errors... */ |
2577 | if (intstatus & I_WR_OOSYNC) { | |
5e8149f5 | 2578 | brcmf_err("Dongle reports WR_OOSYNC\n"); |
5b435de0 AS |
2579 | intstatus &= ~I_WR_OOSYNC; |
2580 | } | |
2581 | ||
2582 | if (intstatus & I_RD_OOSYNC) { | |
5e8149f5 | 2583 | brcmf_err("Dongle reports RD_OOSYNC\n"); |
5b435de0 AS |
2584 | intstatus &= ~I_RD_OOSYNC; |
2585 | } | |
2586 | ||
2587 | if (intstatus & I_SBINT) { | |
5e8149f5 | 2588 | brcmf_err("Dongle reports SBINT\n"); |
5b435de0 AS |
2589 | intstatus &= ~I_SBINT; |
2590 | } | |
2591 | ||
2592 | /* Would be active due to wake-wlan in gSPI */ | |
2593 | if (intstatus & I_CHIPACTIVE) { | |
2594 | brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); | |
2595 | intstatus &= ~I_CHIPACTIVE; | |
2596 | } | |
2597 | ||
2598 | /* Ignore frame indications if rxskip is set */ | |
2599 | if (bus->rxskip) | |
2600 | intstatus &= ~I_HMB_FRAME_IND; | |
2601 | ||
2602 | /* On frame indication, read available frames */ | |
b6a8cf2c HM |
2603 | if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { |
2604 | brcmf_sdio_readframes(bus, bus->rxbound); | |
4754fcee | 2605 | if (!bus->rxpending) |
5b435de0 | 2606 | intstatus &= ~I_HMB_FRAME_IND; |
5b435de0 AS |
2607 | } |
2608 | ||
2609 | /* Keep still-pending events for next scheduling */ | |
5cbb9c28 | 2610 | if (intstatus) |
d3928d09 | 2611 | atomic_or(intstatus, &bus->intstatus); |
5b435de0 | 2612 | |
82d7f3c1 | 2613 | brcmf_sdio_clrintr(bus); |
ba89bf19 | 2614 | |
fed7ec44 | 2615 | if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && |
4dd8b26a HM |
2616 | data_ok(bus)) { |
2617 | sdio_claim_host(bus->sdiodev->func[1]); | |
449e58b8 HM |
2618 | if (bus->ctrl_frame_stat) { |
2619 | err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, | |
2620 | bus->ctrl_frame_len); | |
2621 | bus->ctrl_frame_err = err; | |
2c64e16d | 2622 | wmb(); |
449e58b8 HM |
2623 | bus->ctrl_frame_stat = false; |
2624 | } | |
4dd8b26a | 2625 | sdio_release_host(bus->sdiodev->func[1]); |
4dd8b26a | 2626 | brcmf_sdio_wait_event_wakeup(bus); |
5b435de0 AS |
2627 | } |
2628 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
fed7ec44 HM |
2629 | if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && |
2630 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && | |
2631 | data_ok(bus)) { | |
4754fcee FL |
2632 | framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : |
2633 | txlimit; | |
b6a8cf2c | 2634 | brcmf_sdio_sendfromq(bus, framecnt); |
5b435de0 AS |
2635 | } |
2636 | ||
a1ce7a0d | 2637 | if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { |
5e8149f5 | 2638 | brcmf_err("failed backplane access over SDIO, halting operation\n"); |
4531603a | 2639 | atomic_set(&bus->intstatus, 0); |
de6878c8 | 2640 | if (bus->ctrl_frame_stat) { |
449e58b8 HM |
2641 | sdio_claim_host(bus->sdiodev->func[1]); |
2642 | if (bus->ctrl_frame_stat) { | |
2643 | bus->ctrl_frame_err = -ENODEV; | |
2c64e16d | 2644 | wmb(); |
449e58b8 HM |
2645 | bus->ctrl_frame_stat = false; |
2646 | brcmf_sdio_wait_event_wakeup(bus); | |
2647 | } | |
2648 | sdio_release_host(bus->sdiodev->func[1]); | |
de6878c8 | 2649 | } |
4531603a FL |
2650 | } else if (atomic_read(&bus->intstatus) || |
2651 | atomic_read(&bus->ipend) > 0 || | |
2652 | (!atomic_read(&bus->fcstate) && | |
2653 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
b6a8cf2c | 2654 | data_ok(bus))) { |
2c64e16d | 2655 | bus->dpc_triggered = true; |
5b435de0 | 2656 | } |
5b435de0 AS |
2657 | } |
2658 | ||
82d7f3c1 | 2659 | static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) |
e2432b67 AS |
2660 | { |
2661 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
2662 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
2663 | struct brcmf_sdio *bus = sdiodev->bus; | |
2664 | ||
2665 | return &bus->txq; | |
2666 | } | |
2667 | ||
84936626 HM |
2668 | static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) |
2669 | { | |
2670 | struct sk_buff *p; | |
2671 | int eprec = -1; /* precedence to evict from */ | |
2672 | ||
2673 | /* Fast case, precedence queue is not full and we are also not | |
2674 | * exceeding total queue length | |
2675 | */ | |
2676 | if (!pktq_pfull(q, prec) && !pktq_full(q)) { | |
2677 | brcmu_pktq_penq(q, prec, pkt); | |
2678 | return true; | |
2679 | } | |
2680 | ||
2681 | /* Determine precedence from which to evict packet, if any */ | |
2682 | if (pktq_pfull(q, prec)) { | |
2683 | eprec = prec; | |
2684 | } else if (pktq_full(q)) { | |
2685 | p = brcmu_pktq_peek_tail(q, &eprec); | |
2686 | if (eprec > prec) | |
2687 | return false; | |
2688 | } | |
2689 | ||
2690 | /* Evict if needed */ | |
2691 | if (eprec >= 0) { | |
2692 | /* Detect queueing to unconfigured precedence */ | |
2693 | if (eprec == prec) | |
2694 | return false; /* refuse newer (incoming) packet */ | |
2695 | /* Evict packet according to discard policy */ | |
2696 | p = brcmu_pktq_pdeq_tail(q, eprec); | |
2697 | if (p == NULL) | |
2698 | brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); | |
2699 | brcmu_pkt_buf_free_skb(p); | |
2700 | } | |
2701 | ||
2702 | /* Enqueue */ | |
2703 | p = brcmu_pktq_penq(q, prec, pkt); | |
2704 | if (p == NULL) | |
2705 | brcmf_err("brcmu_pktq_penq() failed\n"); | |
2706 | ||
2707 | return p != NULL; | |
2708 | } | |
2709 | ||
82d7f3c1 | 2710 | static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) |
5b435de0 AS |
2711 | { |
2712 | int ret = -EBADE; | |
44ff5660 | 2713 | uint prec; |
bf347bb9 | 2714 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2715 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
bf347bb9 | 2716 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 | 2717 | |
44ff5660 | 2718 | brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); |
5768f31e AS |
2719 | if (sdiodev->state != BRCMF_SDIOD_DATA) |
2720 | return -EIO; | |
5b435de0 AS |
2721 | |
2722 | /* Add space for the header */ | |
706478cb | 2723 | skb_push(pkt, bus->tx_hdrlen); |
5b435de0 AS |
2724 | /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ |
2725 | ||
2726 | prec = prio2prec((pkt->priority & PRIOMASK)); | |
2727 | ||
2728 | /* Check for existing queue, current flow-control, | |
2729 | pending event, or pending clock */ | |
2730 | brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); | |
80969836 | 2731 | bus->sdcnt.fcqueued++; |
5b435de0 AS |
2732 | |
2733 | /* Priority based enq */ | |
fed7ec44 | 2734 | spin_lock_bh(&bus->txq_lock); |
5aa9f0ea AS |
2735 | /* reset bus_flags in packet cb */ |
2736 | *(u16 *)(pkt->cb) = 0; | |
84936626 | 2737 | if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { |
706478cb | 2738 | skb_pull(pkt, bus->tx_hdrlen); |
5e8149f5 | 2739 | brcmf_err("out of bus->txq !!!\n"); |
5b435de0 AS |
2740 | ret = -ENOSR; |
2741 | } else { | |
2742 | ret = 0; | |
2743 | } | |
5b435de0 | 2744 | |
c8bf3484 | 2745 | if (pktq_len(&bus->txq) >= TXHI) { |
90d03ff7 | 2746 | bus->txoff = true; |
84936626 | 2747 | brcmf_txflowblock(dev, true); |
c8bf3484 | 2748 | } |
fed7ec44 | 2749 | spin_unlock_bh(&bus->txq_lock); |
5b435de0 | 2750 | |
8ae74654 | 2751 | #ifdef DEBUG |
5b435de0 AS |
2752 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) |
2753 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2754 | #endif | |
f1e68c2e | 2755 | |
99824643 | 2756 | brcmf_sdio_trigger_dpc(bus); |
5b435de0 AS |
2757 | return ret; |
2758 | } | |
2759 | ||
8ae74654 | 2760 | #ifdef DEBUG |
5b435de0 AS |
2761 | #define CONSOLE_LINE_MAX 192 |
2762 | ||
82d7f3c1 | 2763 | static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) |
5b435de0 AS |
2764 | { |
2765 | struct brcmf_console *c = &bus->console; | |
2766 | u8 line[CONSOLE_LINE_MAX], ch; | |
2767 | u32 n, idx, addr; | |
2768 | int rv; | |
2769 | ||
2770 | /* Don't do anything until FWREADY updates console address */ | |
2771 | if (bus->console_addr == 0) | |
2772 | return 0; | |
2773 | ||
2774 | /* Read console log struct */ | |
2775 | addr = bus->console_addr + offsetof(struct rte_console, log_le); | |
a39be27b AS |
2776 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, |
2777 | sizeof(c->log_le)); | |
5b435de0 AS |
2778 | if (rv < 0) |
2779 | return rv; | |
2780 | ||
2781 | /* Allocate console buffer (one time only) */ | |
2782 | if (c->buf == NULL) { | |
2783 | c->bufsize = le32_to_cpu(c->log_le.buf_size); | |
2784 | c->buf = kmalloc(c->bufsize, GFP_ATOMIC); | |
2785 | if (c->buf == NULL) | |
2786 | return -ENOMEM; | |
2787 | } | |
2788 | ||
2789 | idx = le32_to_cpu(c->log_le.idx); | |
2790 | ||
2791 | /* Protect against corrupt value */ | |
2792 | if (idx > c->bufsize) | |
2793 | return -EBADE; | |
2794 | ||
2795 | /* Skip reading the console buffer if the index pointer | |
2796 | has not moved */ | |
2797 | if (idx == c->last) | |
2798 | return 0; | |
2799 | ||
2800 | /* Read the console buffer */ | |
2801 | addr = le32_to_cpu(c->log_le.buf); | |
a39be27b | 2802 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); |
5b435de0 AS |
2803 | if (rv < 0) |
2804 | return rv; | |
2805 | ||
2806 | while (c->last != idx) { | |
2807 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
2808 | if (c->last == idx) { | |
2809 | /* This would output a partial line. | |
2810 | * Instead, back up | |
2811 | * the buffer pointer and output this | |
2812 | * line next time around. | |
2813 | */ | |
2814 | if (c->last >= n) | |
2815 | c->last -= n; | |
2816 | else | |
2817 | c->last = c->bufsize - n; | |
2818 | goto break2; | |
2819 | } | |
2820 | ch = c->buf[c->last]; | |
2821 | c->last = (c->last + 1) % c->bufsize; | |
2822 | if (ch == '\n') | |
2823 | break; | |
2824 | line[n] = ch; | |
2825 | } | |
2826 | ||
2827 | if (n > 0) { | |
2828 | if (line[n - 1] == '\r') | |
2829 | n--; | |
2830 | line[n] = 0; | |
18aad4f8 | 2831 | pr_debug("CONSOLE: %s\n", line); |
5b435de0 AS |
2832 | } |
2833 | } | |
2834 | break2: | |
2835 | ||
2836 | return 0; | |
2837 | } | |
8ae74654 | 2838 | #endif /* DEBUG */ |
5b435de0 | 2839 | |
fcf094f4 | 2840 | static int |
82d7f3c1 | 2841 | brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 | 2842 | { |
47a1ce78 | 2843 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2844 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
47a1ce78 | 2845 | struct brcmf_sdio *bus = sdiodev->bus; |
4dd8b26a | 2846 | int ret; |
5b435de0 AS |
2847 | |
2848 | brcmf_dbg(TRACE, "Enter\n"); | |
5768f31e AS |
2849 | if (sdiodev->state != BRCMF_SDIOD_DATA) |
2850 | return -EIO; | |
5b435de0 | 2851 | |
4dd8b26a HM |
2852 | /* Send from dpc */ |
2853 | bus->ctrl_frame_buf = msg; | |
2854 | bus->ctrl_frame_len = msglen; | |
2c64e16d | 2855 | wmb(); |
4dd8b26a | 2856 | bus->ctrl_frame_stat = true; |
4dd8b26a | 2857 | |
99824643 | 2858 | brcmf_sdio_trigger_dpc(bus); |
4dd8b26a | 2859 | wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, |
63ce3d5d | 2860 | CTL_DONE_TIMEOUT); |
449e58b8 HM |
2861 | ret = 0; |
2862 | if (bus->ctrl_frame_stat) { | |
2863 | sdio_claim_host(bus->sdiodev->func[1]); | |
2864 | if (bus->ctrl_frame_stat) { | |
2865 | brcmf_dbg(SDIO, "ctrl_frame timeout\n"); | |
2866 | bus->ctrl_frame_stat = false; | |
2867 | ret = -ETIMEDOUT; | |
2868 | } | |
2869 | sdio_release_host(bus->sdiodev->func[1]); | |
2870 | } | |
2871 | if (!ret) { | |
4dd8b26a HM |
2872 | brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", |
2873 | bus->ctrl_frame_err); | |
2c64e16d | 2874 | rmb(); |
4dd8b26a | 2875 | ret = bus->ctrl_frame_err; |
5b435de0 AS |
2876 | } |
2877 | ||
5b435de0 | 2878 | if (ret) |
80969836 | 2879 | bus->sdcnt.tx_ctlerrs++; |
5b435de0 | 2880 | else |
80969836 | 2881 | bus->sdcnt.tx_ctlpkts++; |
5b435de0 | 2882 | |
4dd8b26a | 2883 | return ret; |
5b435de0 AS |
2884 | } |
2885 | ||
80969836 | 2886 | #ifdef DEBUG |
1b1e4e9e AS |
2887 | static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, |
2888 | struct sdpcm_shared *sh) | |
4fc0d016 AS |
2889 | { |
2890 | u32 addr, console_ptr, console_size, console_index; | |
2891 | char *conbuf = NULL; | |
2892 | __le32 sh_val; | |
2893 | int rv; | |
4fc0d016 AS |
2894 | |
2895 | /* obtain console information from device memory */ | |
2896 | addr = sh->console_addr + offsetof(struct rte_console, log_le); | |
a39be27b AS |
2897 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2898 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2899 | if (rv < 0) |
2900 | return rv; | |
2901 | console_ptr = le32_to_cpu(sh_val); | |
2902 | ||
2903 | addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); | |
a39be27b AS |
2904 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2905 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2906 | if (rv < 0) |
2907 | return rv; | |
2908 | console_size = le32_to_cpu(sh_val); | |
2909 | ||
2910 | addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); | |
a39be27b AS |
2911 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, |
2912 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2913 | if (rv < 0) |
2914 | return rv; | |
2915 | console_index = le32_to_cpu(sh_val); | |
2916 | ||
2917 | /* allocate buffer for console data */ | |
2918 | if (console_size <= CONSOLE_BUFFER_MAX) | |
2919 | conbuf = vzalloc(console_size+1); | |
2920 | ||
2921 | if (!conbuf) | |
2922 | return -ENOMEM; | |
2923 | ||
2924 | /* obtain the console data from device */ | |
2925 | conbuf[console_size] = '\0'; | |
a39be27b AS |
2926 | rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, |
2927 | console_size); | |
4fc0d016 AS |
2928 | if (rv < 0) |
2929 | goto done; | |
2930 | ||
1b1e4e9e AS |
2931 | rv = seq_write(seq, conbuf + console_index, |
2932 | console_size - console_index); | |
4fc0d016 AS |
2933 | if (rv < 0) |
2934 | goto done; | |
2935 | ||
1b1e4e9e AS |
2936 | if (console_index > 0) |
2937 | rv = seq_write(seq, conbuf, console_index - 1); | |
2938 | ||
4fc0d016 AS |
2939 | done: |
2940 | vfree(conbuf); | |
2941 | return rv; | |
2942 | } | |
2943 | ||
1b1e4e9e AS |
2944 | static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, |
2945 | struct sdpcm_shared *sh) | |
4fc0d016 | 2946 | { |
1b1e4e9e | 2947 | int error; |
4fc0d016 | 2948 | struct brcmf_trap_info tr; |
4fc0d016 | 2949 | |
baa9e609 PH |
2950 | if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { |
2951 | brcmf_dbg(INFO, "no trap in firmware\n"); | |
4fc0d016 | 2952 | return 0; |
baa9e609 | 2953 | } |
4fc0d016 | 2954 | |
a39be27b AS |
2955 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, |
2956 | sizeof(struct brcmf_trap_info)); | |
4fc0d016 AS |
2957 | if (error < 0) |
2958 | return error; | |
2959 | ||
1b1e4e9e AS |
2960 | seq_printf(seq, |
2961 | "dongle trap info: type 0x%x @ epc 0x%08x\n" | |
2962 | " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" | |
2963 | " lr 0x%08x pc 0x%08x offset 0x%x\n" | |
2964 | " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" | |
2965 | " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", | |
2966 | le32_to_cpu(tr.type), le32_to_cpu(tr.epc), | |
2967 | le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), | |
2968 | le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), | |
2969 | le32_to_cpu(tr.pc), sh->trap_addr, | |
2970 | le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), | |
2971 | le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), | |
2972 | le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), | |
2973 | le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); | |
2974 | ||
2975 | return 0; | |
4fc0d016 AS |
2976 | } |
2977 | ||
1b1e4e9e AS |
2978 | static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, |
2979 | struct sdpcm_shared *sh) | |
4fc0d016 AS |
2980 | { |
2981 | int error = 0; | |
4fc0d016 AS |
2982 | char file[80] = "?"; |
2983 | char expr[80] = "<???>"; | |
4fc0d016 AS |
2984 | |
2985 | if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { | |
2986 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
2987 | return 0; | |
2988 | } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { | |
2989 | brcmf_dbg(INFO, "no assert in dongle\n"); | |
2990 | return 0; | |
2991 | } | |
2992 | ||
38b0b0dd | 2993 | sdio_claim_host(bus->sdiodev->func[1]); |
4fc0d016 | 2994 | if (sh->assert_file_addr != 0) { |
a39be27b AS |
2995 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, |
2996 | sh->assert_file_addr, (u8 *)file, 80); | |
4fc0d016 AS |
2997 | if (error < 0) |
2998 | return error; | |
2999 | } | |
3000 | if (sh->assert_exp_addr != 0) { | |
a39be27b AS |
3001 | error = brcmf_sdiod_ramrw(bus->sdiodev, false, |
3002 | sh->assert_exp_addr, (u8 *)expr, 80); | |
4fc0d016 AS |
3003 | if (error < 0) |
3004 | return error; | |
3005 | } | |
38b0b0dd | 3006 | sdio_release_host(bus->sdiodev->func[1]); |
4fc0d016 | 3007 | |
1b1e4e9e AS |
3008 | seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", |
3009 | file, sh->assert_line, expr); | |
3010 | return 0; | |
4fc0d016 AS |
3011 | } |
3012 | ||
82d7f3c1 | 3013 | static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) |
4fc0d016 AS |
3014 | { |
3015 | int error; | |
3016 | struct sdpcm_shared sh; | |
3017 | ||
4fc0d016 | 3018 | error = brcmf_sdio_readshared(bus, &sh); |
4fc0d016 AS |
3019 | |
3020 | if (error < 0) | |
3021 | return error; | |
3022 | ||
3023 | if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) | |
3024 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
3025 | else if (sh.flags & SDPCM_SHARED_ASSERT) | |
5e8149f5 | 3026 | brcmf_err("assertion in dongle\n"); |
4fc0d016 AS |
3027 | |
3028 | if (sh.flags & SDPCM_SHARED_TRAP) | |
5e8149f5 | 3029 | brcmf_err("firmware trap in dongle\n"); |
4fc0d016 AS |
3030 | |
3031 | return 0; | |
3032 | } | |
3033 | ||
1b1e4e9e | 3034 | static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) |
4fc0d016 AS |
3035 | { |
3036 | int error = 0; | |
3037 | struct sdpcm_shared sh; | |
4fc0d016 | 3038 | |
4fc0d016 AS |
3039 | error = brcmf_sdio_readshared(bus, &sh); |
3040 | if (error < 0) | |
3041 | goto done; | |
3042 | ||
1b1e4e9e | 3043 | error = brcmf_sdio_assert_info(seq, bus, &sh); |
4fc0d016 AS |
3044 | if (error < 0) |
3045 | goto done; | |
baa9e609 | 3046 | |
1b1e4e9e | 3047 | error = brcmf_sdio_trap_info(seq, bus, &sh); |
4fc0d016 AS |
3048 | if (error < 0) |
3049 | goto done; | |
baa9e609 | 3050 | |
1b1e4e9e | 3051 | error = brcmf_sdio_dump_console(seq, bus, &sh); |
4fc0d016 | 3052 | |
4fc0d016 | 3053 | done: |
4fc0d016 AS |
3054 | return error; |
3055 | } | |
3056 | ||
1b1e4e9e | 3057 | static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) |
4fc0d016 | 3058 | { |
82d957e0 AS |
3059 | struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); |
3060 | struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; | |
4fc0d016 | 3061 | |
1b1e4e9e AS |
3062 | return brcmf_sdio_died_dump(seq, bus); |
3063 | } | |
3064 | ||
82d957e0 | 3065 | static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) |
1b1e4e9e | 3066 | { |
82d957e0 AS |
3067 | struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); |
3068 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3069 | struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; | |
4fc0d016 | 3070 | |
82d957e0 AS |
3071 | seq_printf(seq, |
3072 | "intrcount: %u\nlastintrs: %u\n" | |
3073 | "pollcnt: %u\nregfails: %u\n" | |
3074 | "tx_sderrs: %u\nfcqueued: %u\n" | |
3075 | "rxrtx: %u\nrx_toolong: %u\n" | |
3076 | "rxc_errors: %u\nrx_hdrfail: %u\n" | |
3077 | "rx_badhdr: %u\nrx_badseq: %u\n" | |
3078 | "fc_rcvd: %u\nfc_xoff: %u\n" | |
3079 | "fc_xon: %u\nrxglomfail: %u\n" | |
3080 | "rxglomframes: %u\nrxglompkts: %u\n" | |
3081 | "f2rxhdrs: %u\nf2rxdata: %u\n" | |
3082 | "f2txdata: %u\nf1regdata: %u\n" | |
3083 | "tickcnt: %u\ntx_ctlerrs: %lu\n" | |
3084 | "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" | |
3085 | "rx_ctlpkts: %lu\nrx_readahead: %lu\n", | |
3086 | sdcnt->intrcount, sdcnt->lastintrs, | |
3087 | sdcnt->pollcnt, sdcnt->regfails, | |
3088 | sdcnt->tx_sderrs, sdcnt->fcqueued, | |
3089 | sdcnt->rxrtx, sdcnt->rx_toolong, | |
3090 | sdcnt->rxc_errors, sdcnt->rx_hdrfail, | |
3091 | sdcnt->rx_badhdr, sdcnt->rx_badseq, | |
3092 | sdcnt->fc_rcvd, sdcnt->fc_xoff, | |
3093 | sdcnt->fc_xon, sdcnt->rxglomfail, | |
3094 | sdcnt->rxglomframes, sdcnt->rxglompkts, | |
3095 | sdcnt->f2rxhdrs, sdcnt->f2rxdata, | |
3096 | sdcnt->f2txdata, sdcnt->f1regdata, | |
3097 | sdcnt->tickcnt, sdcnt->tx_ctlerrs, | |
3098 | sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, | |
3099 | sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); | |
3100 | ||
3101 | return 0; | |
3102 | } | |
4fc0d016 | 3103 | |
80969836 AS |
3104 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3105 | { | |
3106 | struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; | |
4fc0d016 | 3107 | struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); |
80969836 | 3108 | |
4fc0d016 AS |
3109 | if (IS_ERR_OR_NULL(dentry)) |
3110 | return; | |
3111 | ||
9d6c1dc4 AS |
3112 | bus->console_interval = BRCMF_CONSOLE; |
3113 | ||
82d957e0 AS |
3114 | brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); |
3115 | brcmf_debugfs_add_entry(drvr, "counters", | |
3116 | brcmf_debugfs_sdio_count_read); | |
0801e6c5 DK |
3117 | debugfs_create_u32("console_interval", 0644, dentry, |
3118 | &bus->console_interval); | |
80969836 AS |
3119 | } |
3120 | #else | |
82d7f3c1 | 3121 | static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) |
4fc0d016 AS |
3122 | { |
3123 | return 0; | |
3124 | } | |
3125 | ||
80969836 AS |
3126 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3127 | { | |
3128 | } | |
3129 | #endif /* DEBUG */ | |
3130 | ||
fcf094f4 | 3131 | static int |
82d7f3c1 | 3132 | brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
3133 | { |
3134 | int timeleft; | |
3135 | uint rxlen = 0; | |
3136 | bool pending; | |
dd43a01c | 3137 | u8 *buf; |
532cdd3b | 3138 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3139 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
532cdd3b | 3140 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
3141 | |
3142 | brcmf_dbg(TRACE, "Enter\n"); | |
5768f31e AS |
3143 | if (sdiodev->state != BRCMF_SDIOD_DATA) |
3144 | return -EIO; | |
5b435de0 AS |
3145 | |
3146 | /* Wait until control frame is available */ | |
82d7f3c1 | 3147 | timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); |
5b435de0 | 3148 | |
dd43a01c | 3149 | spin_lock_bh(&bus->rxctl_lock); |
5b435de0 AS |
3150 | rxlen = bus->rxlen; |
3151 | memcpy(msg, bus->rxctl, min(msglen, rxlen)); | |
dd43a01c FL |
3152 | bus->rxctl = NULL; |
3153 | buf = bus->rxctl_orig; | |
3154 | bus->rxctl_orig = NULL; | |
5b435de0 | 3155 | bus->rxlen = 0; |
dd43a01c FL |
3156 | spin_unlock_bh(&bus->rxctl_lock); |
3157 | vfree(buf); | |
5b435de0 AS |
3158 | |
3159 | if (rxlen) { | |
3160 | brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", | |
3161 | rxlen, msglen); | |
3162 | } else if (timeleft == 0) { | |
5e8149f5 | 3163 | brcmf_err("resumed on timeout\n"); |
82d7f3c1 | 3164 | brcmf_sdio_checkdied(bus); |
23677ce3 | 3165 | } else if (pending) { |
5b435de0 AS |
3166 | brcmf_dbg(CTL, "cancelled\n"); |
3167 | return -ERESTARTSYS; | |
3168 | } else { | |
3169 | brcmf_dbg(CTL, "resumed for unknown reason?\n"); | |
82d7f3c1 | 3170 | brcmf_sdio_checkdied(bus); |
5b435de0 AS |
3171 | } |
3172 | ||
3173 | if (rxlen) | |
80969836 | 3174 | bus->sdcnt.rx_ctlpkts++; |
5b435de0 | 3175 | else |
80969836 | 3176 | bus->sdcnt.rx_ctlerrs++; |
5b435de0 AS |
3177 | |
3178 | return rxlen ? (int)rxlen : -ETIMEDOUT; | |
3179 | } | |
3180 | ||
a74d036f HM |
3181 | #ifdef DEBUG |
3182 | static bool | |
3183 | brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, | |
3184 | u8 *ram_data, uint ram_sz) | |
3185 | { | |
3186 | char *ram_cmp; | |
3187 | int err; | |
3188 | bool ret = true; | |
3189 | int address; | |
3190 | int offset; | |
3191 | int len; | |
3192 | ||
3193 | /* read back and verify */ | |
3194 | brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, | |
3195 | ram_sz); | |
3196 | ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); | |
3197 | /* do not proceed while no memory but */ | |
3198 | if (!ram_cmp) | |
3199 | return true; | |
3200 | ||
3201 | address = ram_addr; | |
3202 | offset = 0; | |
3203 | while (offset < ram_sz) { | |
3204 | len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : | |
3205 | ram_sz - offset; | |
3206 | err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); | |
3207 | if (err) { | |
3208 | brcmf_err("error %d on reading %d membytes at 0x%08x\n", | |
3209 | err, len, address); | |
3210 | ret = false; | |
3211 | break; | |
3212 | } else if (memcmp(ram_cmp, &ram_data[offset], len)) { | |
3213 | brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", | |
3214 | offset, len); | |
3215 | ret = false; | |
3216 | break; | |
3217 | } | |
3218 | offset += len; | |
3219 | address += len; | |
3220 | } | |
3221 | ||
3222 | kfree(ram_cmp); | |
3223 | ||
3224 | return ret; | |
3225 | } | |
3226 | #else /* DEBUG */ | |
3227 | static bool | |
3228 | brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, | |
3229 | u8 *ram_data, uint ram_sz) | |
3230 | { | |
3231 | return true; | |
3232 | } | |
3233 | #endif /* DEBUG */ | |
3234 | ||
3355650c AS |
3235 | static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, |
3236 | const struct firmware *fw) | |
5b435de0 | 3237 | { |
f2c44fe7 | 3238 | int err; |
f2c44fe7 | 3239 | |
a74d036f HM |
3240 | brcmf_dbg(TRACE, "Enter\n"); |
3241 | ||
f9951c13 HM |
3242 | err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, |
3243 | (u8 *)fw->data, fw->size); | |
3244 | if (err) | |
3245 | brcmf_err("error %d on writing %d membytes at 0x%08x\n", | |
3246 | err, (int)fw->size, bus->ci->rambase); | |
3247 | else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, | |
3248 | (u8 *)fw->data, fw->size)) | |
3249 | err = -EIO; | |
5b435de0 | 3250 | |
f2c44fe7 | 3251 | return err; |
5b435de0 AS |
3252 | } |
3253 | ||
3355650c | 3254 | static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, |
bd0e1b1d | 3255 | void *vars, u32 varsz) |
5b435de0 | 3256 | { |
a74d036f HM |
3257 | int address; |
3258 | int err; | |
3259 | ||
3260 | brcmf_dbg(TRACE, "Enter\n"); | |
5b435de0 | 3261 | |
a74d036f HM |
3262 | address = bus->ci->ramsize - varsz + bus->ci->rambase; |
3263 | err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); | |
3264 | if (err) | |
3265 | brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", | |
3266 | err, varsz, address); | |
3267 | else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) | |
3268 | err = -EIO; | |
3269 | ||
a74d036f | 3270 | return err; |
5b435de0 AS |
3271 | } |
3272 | ||
bd0e1b1d AS |
3273 | static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, |
3274 | const struct firmware *fw, | |
3275 | void *nvram, u32 nvlen) | |
5b435de0 | 3276 | { |
9e12904a | 3277 | int bcmerror; |
3355650c | 3278 | u32 rstvec; |
82d7f3c1 AS |
3279 | |
3280 | sdio_claim_host(bus->sdiodev->func[1]); | |
3281 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
5b435de0 | 3282 | |
3355650c AS |
3283 | rstvec = get_unaligned_le32(fw->data); |
3284 | brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); | |
3285 | ||
3286 | bcmerror = brcmf_sdio_download_code_file(bus, fw); | |
3287 | release_firmware(fw); | |
3288 | if (bcmerror) { | |
5e8149f5 | 3289 | brcmf_err("dongle image file download failed\n"); |
bd0e1b1d | 3290 | brcmf_fw_nvram_free(nvram); |
5b435de0 AS |
3291 | goto err; |
3292 | } | |
3293 | ||
bd0e1b1d AS |
3294 | bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); |
3295 | brcmf_fw_nvram_free(nvram); | |
3355650c | 3296 | if (bcmerror) { |
5e8149f5 | 3297 | brcmf_err("dongle nvram file download failed\n"); |
3eaa956c FL |
3298 | goto err; |
3299 | } | |
5b435de0 AS |
3300 | |
3301 | /* Take arm out of reset */ | |
d380ebc9 | 3302 | if (!brcmf_chip_set_active(bus->ci, rstvec)) { |
5e8149f5 | 3303 | brcmf_err("error getting out of ARM core reset\n"); |
5b435de0 AS |
3304 | goto err; |
3305 | } | |
3306 | ||
a1cee865 | 3307 | /* Allow full data communication using DPC from now on. */ |
a1ce7a0d | 3308 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); |
5b435de0 AS |
3309 | bcmerror = 0; |
3310 | ||
3311 | err: | |
82d7f3c1 AS |
3312 | brcmf_sdio_clkctl(bus, CLK_SDONLY, false); |
3313 | sdio_release_host(bus->sdiodev->func[1]); | |
5b435de0 AS |
3314 | return bcmerror; |
3315 | } | |
3316 | ||
82d7f3c1 | 3317 | static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) |
4a3da990 PH |
3318 | { |
3319 | int err = 0; | |
3320 | u8 val; | |
3321 | ||
3322 | brcmf_dbg(TRACE, "Enter\n"); | |
3323 | ||
a39be27b | 3324 | val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); |
4a3da990 PH |
3325 | if (err) { |
3326 | brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3327 | return; | |
3328 | } | |
3329 | ||
3330 | val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; | |
a39be27b | 3331 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); |
4a3da990 PH |
3332 | if (err) { |
3333 | brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3334 | return; | |
3335 | } | |
3336 | ||
3337 | /* Add CMD14 Support */ | |
a39be27b AS |
3338 | brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, |
3339 | (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | | |
3340 | SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), | |
3341 | &err); | |
4a3da990 PH |
3342 | if (err) { |
3343 | brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); | |
3344 | return; | |
3345 | } | |
3346 | ||
a39be27b AS |
3347 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3348 | SBSDIO_FORCE_HT, &err); | |
4a3da990 PH |
3349 | if (err) { |
3350 | brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); | |
3351 | return; | |
3352 | } | |
3353 | ||
3354 | /* set flag */ | |
3355 | bus->sr_enabled = true; | |
3356 | brcmf_dbg(INFO, "SR enabled\n"); | |
3357 | } | |
3358 | ||
3359 | /* enable KSO bit */ | |
82d7f3c1 | 3360 | static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) |
4a3da990 PH |
3361 | { |
3362 | u8 val; | |
3363 | int err = 0; | |
3364 | ||
3365 | brcmf_dbg(TRACE, "Enter\n"); | |
3366 | ||
3367 | /* KSO bit added in SDIO core rev 12 */ | |
cb7cf7be | 3368 | if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) |
4a3da990 PH |
3369 | return 0; |
3370 | ||
a39be27b | 3371 | val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); |
4a3da990 PH |
3372 | if (err) { |
3373 | brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); | |
3374 | return err; | |
3375 | } | |
3376 | ||
3377 | if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { | |
3378 | val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << | |
3379 | SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
a39be27b AS |
3380 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, |
3381 | val, &err); | |
4a3da990 PH |
3382 | if (err) { |
3383 | brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); | |
3384 | return err; | |
3385 | } | |
3386 | } | |
3387 | ||
3388 | return 0; | |
3389 | } | |
3390 | ||
3391 | ||
82d7f3c1 | 3392 | static int brcmf_sdio_bus_preinit(struct device *dev) |
cf458287 AS |
3393 | { |
3394 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3395 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3396 | struct brcmf_sdio *bus = sdiodev->bus; | |
8da9d2c8 | 3397 | uint pad_size; |
cf458287 | 3398 | u32 value; |
cf458287 AS |
3399 | int err; |
3400 | ||
8da9d2c8 FL |
3401 | /* the commands below use the terms tx and rx from |
3402 | * a device perspective, ie. bus:txglom affects the | |
3403 | * bus transfers from device to host. | |
3404 | */ | |
cb7cf7be | 3405 | if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) { |
cf458287 AS |
3406 | /* for sdio core rev < 12, disable txgloming */ |
3407 | value = 0; | |
3408 | err = brcmf_iovar_data_set(dev, "bus:txglom", &value, | |
3409 | sizeof(u32)); | |
3410 | } else { | |
3411 | /* otherwise, set txglomalign */ | |
af5b5e62 | 3412 | value = sdiodev->settings->bus.sdio.sd_sgentry_align; |
cf458287 AS |
3413 | /* SDIO ADMA requires at least 32 bit alignment */ |
3414 | value = max_t(u32, value, 4); | |
3415 | err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, | |
3416 | sizeof(u32)); | |
3417 | } | |
8da9d2c8 FL |
3418 | |
3419 | if (err < 0) | |
3420 | goto done; | |
3421 | ||
3422 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
3423 | if (sdiodev->sg_support) { | |
3424 | bus->txglom = false; | |
3425 | value = 1; | |
3426 | pad_size = bus->sdiodev->func[2]->cur_blksize << 1; | |
8da9d2c8 FL |
3427 | err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", |
3428 | &value, sizeof(u32)); | |
3429 | if (err < 0) { | |
3430 | /* bus:rxglom is allowed to fail */ | |
3431 | err = 0; | |
3432 | } else { | |
3433 | bus->txglom = true; | |
3434 | bus->tx_hdrlen += SDPCM_HWEXT_LEN; | |
3435 | } | |
3436 | } | |
3437 | brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); | |
3438 | ||
3439 | done: | |
cf458287 AS |
3440 | return err; |
3441 | } | |
3442 | ||
ff4445a8 AS |
3443 | static size_t brcmf_sdio_bus_get_ramsize(struct device *dev) |
3444 | { | |
3445 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3446 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3447 | struct brcmf_sdio *bus = sdiodev->bus; | |
3448 | ||
3449 | return bus->ci->ramsize - bus->ci->srsize; | |
3450 | } | |
3451 | ||
3452 | static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data, | |
3453 | size_t mem_size) | |
3454 | { | |
3455 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3456 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3457 | struct brcmf_sdio *bus = sdiodev->bus; | |
3458 | int err; | |
3459 | int address; | |
3460 | int offset; | |
3461 | int len; | |
3462 | ||
3463 | brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase, | |
3464 | mem_size); | |
3465 | ||
3466 | address = bus->ci->rambase; | |
3467 | offset = err = 0; | |
3468 | sdio_claim_host(sdiodev->func[1]); | |
3469 | while (offset < mem_size) { | |
3470 | len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK : | |
3471 | mem_size - offset; | |
3472 | err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len); | |
3473 | if (err) { | |
3474 | brcmf_err("error %d on reading %d membytes at 0x%08x\n", | |
3475 | err, len, address); | |
3476 | goto done; | |
3477 | } | |
3478 | data += len; | |
3479 | offset += len; | |
3480 | address += len; | |
3481 | } | |
3482 | ||
3483 | done: | |
3484 | sdio_release_host(sdiodev->func[1]); | |
3485 | return err; | |
3486 | } | |
3487 | ||
99824643 AS |
3488 | void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) |
3489 | { | |
2c64e16d HM |
3490 | if (!bus->dpc_triggered) { |
3491 | bus->dpc_triggered = true; | |
99824643 AS |
3492 | queue_work(bus->brcmf_wq, &bus->datawork); |
3493 | } | |
3494 | } | |
3495 | ||
82d7f3c1 | 3496 | void brcmf_sdio_isr(struct brcmf_sdio *bus) |
5b435de0 | 3497 | { |
5b435de0 AS |
3498 | brcmf_dbg(TRACE, "Enter\n"); |
3499 | ||
3500 | if (!bus) { | |
5e8149f5 | 3501 | brcmf_err("bus is null pointer, exiting\n"); |
5b435de0 AS |
3502 | return; |
3503 | } | |
3504 | ||
5b435de0 | 3505 | /* Count the interrupt call */ |
80969836 | 3506 | bus->sdcnt.intrcount++; |
4531603a FL |
3507 | if (in_interrupt()) |
3508 | atomic_set(&bus->ipend, 1); | |
3509 | else | |
3510 | if (brcmf_sdio_intr_rstatus(bus)) { | |
5e8149f5 | 3511 | brcmf_err("failed backplane access\n"); |
4531603a | 3512 | } |
5b435de0 | 3513 | |
5b435de0 AS |
3514 | /* Disable additional interrupts (is this needed now)? */ |
3515 | if (!bus->intr) | |
5e8149f5 | 3516 | brcmf_err("isr w/o interrupt configured!\n"); |
5b435de0 | 3517 | |
2c64e16d | 3518 | bus->dpc_triggered = true; |
f1e68c2e | 3519 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3520 | } |
3521 | ||
b441ba8d | 3522 | static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) |
5b435de0 | 3523 | { |
5b435de0 AS |
3524 | brcmf_dbg(TIMER, "Enter\n"); |
3525 | ||
5b435de0 | 3526 | /* Poll period: check device if appropriate. */ |
4a3da990 PH |
3527 | if (!bus->sr_enabled && |
3528 | bus->poll && (++bus->polltick >= bus->pollrate)) { | |
5b435de0 AS |
3529 | u32 intstatus = 0; |
3530 | ||
3531 | /* Reset poll tick */ | |
3532 | bus->polltick = 0; | |
3533 | ||
3534 | /* Check device if no interrupts */ | |
80969836 AS |
3535 | if (!bus->intr || |
3536 | (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { | |
5b435de0 | 3537 | |
2c64e16d | 3538 | if (!bus->dpc_triggered) { |
5b435de0 | 3539 | u8 devpend; |
fccfe930 | 3540 | |
38b0b0dd | 3541 | sdio_claim_host(bus->sdiodev->func[1]); |
a39be27b AS |
3542 | devpend = brcmf_sdiod_regrb(bus->sdiodev, |
3543 | SDIO_CCCR_INTx, | |
3544 | NULL); | |
38b0b0dd | 3545 | sdio_release_host(bus->sdiodev->func[1]); |
99824643 AS |
3546 | intstatus = devpend & (INTR_STATUS_FUNC1 | |
3547 | INTR_STATUS_FUNC2); | |
5b435de0 AS |
3548 | } |
3549 | ||
3550 | /* If there is something, make like the ISR and | |
3551 | schedule the DPC */ | |
3552 | if (intstatus) { | |
80969836 | 3553 | bus->sdcnt.pollcnt++; |
1d382273 | 3554 | atomic_set(&bus->ipend, 1); |
5b435de0 | 3555 | |
2c64e16d | 3556 | bus->dpc_triggered = true; |
f1e68c2e | 3557 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3558 | } |
3559 | } | |
3560 | ||
3561 | /* Update interrupt tracking */ | |
80969836 | 3562 | bus->sdcnt.lastintrs = bus->sdcnt.intrcount; |
5b435de0 | 3563 | } |
8ae74654 | 3564 | #ifdef DEBUG |
5b435de0 | 3565 | /* Poll for console output periodically */ |
9d6c1dc4 | 3566 | if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() && |
8d169aa0 | 3567 | bus->console_interval != 0) { |
63ce3d5d | 3568 | bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL); |
5b435de0 AS |
3569 | if (bus->console.count >= bus->console_interval) { |
3570 | bus->console.count -= bus->console_interval; | |
38b0b0dd | 3571 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 3572 | /* Make sure backplane clock is on */ |
82d7f3c1 AS |
3573 | brcmf_sdio_bus_sleep(bus, false, false); |
3574 | if (brcmf_sdio_readconsole(bus) < 0) | |
5b435de0 AS |
3575 | /* stop on error */ |
3576 | bus->console_interval = 0; | |
38b0b0dd | 3577 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3578 | } |
3579 | } | |
8ae74654 | 3580 | #endif /* DEBUG */ |
5b435de0 AS |
3581 | |
3582 | /* On idle timeout clear activity flag and/or turn off clock */ | |
2c64e16d HM |
3583 | if (!bus->dpc_triggered) { |
3584 | rmb(); | |
3585 | if ((!bus->dpc_running) && (bus->idletime > 0) && | |
3586 | (bus->clkstate == CLK_AVAIL)) { | |
3587 | bus->idlecount++; | |
3588 | if (bus->idlecount > bus->idletime) { | |
3589 | brcmf_dbg(SDIO, "idle\n"); | |
3590 | sdio_claim_host(bus->sdiodev->func[1]); | |
4011fc49 | 3591 | brcmf_sdio_wd_timer(bus, false); |
2c64e16d HM |
3592 | bus->idlecount = 0; |
3593 | brcmf_sdio_bus_sleep(bus, true, false); | |
3594 | sdio_release_host(bus->sdiodev->func[1]); | |
3595 | } | |
3596 | } else { | |
5b435de0 | 3597 | bus->idlecount = 0; |
5b435de0 | 3598 | } |
b441ba8d HM |
3599 | } else { |
3600 | bus->idlecount = 0; | |
5b435de0 | 3601 | } |
5b435de0 AS |
3602 | } |
3603 | ||
f1e68c2e FL |
3604 | static void brcmf_sdio_dataworker(struct work_struct *work) |
3605 | { | |
3606 | struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, | |
3607 | datawork); | |
f1e68c2e | 3608 | |
2c64e16d HM |
3609 | bus->dpc_running = true; |
3610 | wmb(); | |
3611 | while (ACCESS_ONCE(bus->dpc_triggered)) { | |
3612 | bus->dpc_triggered = false; | |
82d7f3c1 | 3613 | brcmf_sdio_dpc(bus); |
b441ba8d | 3614 | bus->idlecount = 0; |
f1e68c2e | 3615 | } |
2c64e16d | 3616 | bus->dpc_running = false; |
99824643 AS |
3617 | if (brcmf_sdiod_freezing(bus->sdiodev)) { |
3618 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); | |
3619 | brcmf_sdiod_try_freeze(bus->sdiodev); | |
3620 | brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); | |
3621 | } | |
f1e68c2e FL |
3622 | } |
3623 | ||
65d80d0b AS |
3624 | static void |
3625 | brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, | |
cb7cf7be | 3626 | struct brcmf_chip *ci, u32 drivestrength) |
65d80d0b AS |
3627 | { |
3628 | const struct sdiod_drive_str *str_tab = NULL; | |
3629 | u32 str_mask; | |
3630 | u32 str_shift; | |
65d80d0b AS |
3631 | u32 i; |
3632 | u32 drivestrength_sel = 0; | |
3633 | u32 cc_data_temp; | |
3634 | u32 addr; | |
3635 | ||
cb7cf7be | 3636 | if (!(ci->cc_caps & CC_CAP_PMU)) |
65d80d0b AS |
3637 | return; |
3638 | ||
3639 | switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { | |
5779ae6a | 3640 | case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): |
65d80d0b AS |
3641 | str_tab = sdiod_drvstr_tab1_1v8; |
3642 | str_mask = 0x00003800; | |
3643 | str_shift = 11; | |
3644 | break; | |
5779ae6a | 3645 | case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): |
65d80d0b AS |
3646 | str_tab = sdiod_drvstr_tab6_1v8; |
3647 | str_mask = 0x00001800; | |
3648 | str_shift = 11; | |
3649 | break; | |
5779ae6a | 3650 | case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): |
65d80d0b AS |
3651 | /* note: 43143 does not support tristate */ |
3652 | i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; | |
3653 | if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { | |
3654 | str_tab = sdiod_drvstr_tab2_3v3; | |
3655 | str_mask = 0x00000007; | |
3656 | str_shift = 0; | |
3657 | } else | |
3658 | brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", | |
cb7cf7be | 3659 | ci->name, drivestrength); |
65d80d0b | 3660 | break; |
5779ae6a | 3661 | case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): |
65d80d0b AS |
3662 | str_tab = sdiod_drive_strength_tab5_1v8; |
3663 | str_mask = 0x00003800; | |
3664 | str_shift = 11; | |
3665 | break; | |
3666 | default: | |
3667 | brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", | |
cb7cf7be | 3668 | ci->name, ci->chiprev, ci->pmurev); |
65d80d0b AS |
3669 | break; |
3670 | } | |
3671 | ||
3672 | if (str_tab != NULL) { | |
e2b397f1 RM |
3673 | struct brcmf_core *pmu = brcmf_chip_get_pmu(ci); |
3674 | ||
65d80d0b AS |
3675 | for (i = 0; str_tab[i].strength != 0; i++) { |
3676 | if (drivestrength >= str_tab[i].strength) { | |
3677 | drivestrength_sel = str_tab[i].sel; | |
3678 | break; | |
3679 | } | |
3680 | } | |
e2b397f1 | 3681 | addr = CORE_CC_REG(pmu->base, chipcontrol_addr); |
65d80d0b AS |
3682 | brcmf_sdiod_regwl(sdiodev, addr, 1, NULL); |
3683 | cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL); | |
3684 | cc_data_temp &= ~str_mask; | |
3685 | drivestrength_sel <<= str_shift; | |
3686 | cc_data_temp |= drivestrength_sel; | |
3687 | brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL); | |
3688 | ||
3689 | brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", | |
3690 | str_tab[i].strength, drivestrength, cc_data_temp); | |
3691 | } | |
3692 | } | |
3693 | ||
cb7cf7be | 3694 | static int brcmf_sdio_buscoreprep(void *ctx) |
65d80d0b | 3695 | { |
cb7cf7be | 3696 | struct brcmf_sdio_dev *sdiodev = ctx; |
65d80d0b AS |
3697 | int err = 0; |
3698 | u8 clkval, clkset; | |
3699 | ||
3700 | /* Try forcing SDIO core to do ALPAvail request only */ | |
3701 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; | |
3702 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
3703 | if (err) { | |
3704 | brcmf_err("error writing for HT off\n"); | |
3705 | return err; | |
3706 | } | |
3707 | ||
3708 | /* If register supported, wait for ALPAvail and then force ALP */ | |
3709 | /* This may take up to 15 milliseconds */ | |
3710 | clkval = brcmf_sdiod_regrb(sdiodev, | |
3711 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); | |
3712 | ||
3713 | if ((clkval & ~SBSDIO_AVBITS) != clkset) { | |
3714 | brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", | |
3715 | clkset, clkval); | |
3716 | return -EACCES; | |
3717 | } | |
3718 | ||
3719 | SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev, | |
3720 | SBSDIO_FUNC1_CHIPCLKCSR, NULL)), | |
3721 | !SBSDIO_ALPAV(clkval)), | |
3722 | PMU_MAX_TRANSITION_DLY); | |
3723 | if (!SBSDIO_ALPAV(clkval)) { | |
3724 | brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", | |
3725 | clkval); | |
3726 | return -EBUSY; | |
3727 | } | |
3728 | ||
3729 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; | |
3730 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); | |
3731 | udelay(65); | |
3732 | ||
3733 | /* Also, disable the extra SDIO pull-ups */ | |
3734 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); | |
3735 | ||
3736 | return 0; | |
3737 | } | |
3738 | ||
d380ebc9 AS |
3739 | static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, |
3740 | u32 rstvec) | |
cb7cf7be AS |
3741 | { |
3742 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3743 | struct brcmf_core *core; | |
3744 | u32 reg_addr; | |
3745 | ||
3746 | /* clear all interrupts */ | |
3747 | core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV); | |
3748 | reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus); | |
3749 | brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL); | |
3750 | ||
3751 | if (rstvec) | |
3752 | /* Write reset vector to address 0 */ | |
3753 | brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, | |
3754 | sizeof(rstvec)); | |
3755 | } | |
3756 | ||
3757 | static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) | |
3758 | { | |
3759 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3760 | u32 val, rev; | |
3761 | ||
3762 | val = brcmf_sdiod_regrl(sdiodev, addr, NULL); | |
8bd61f8d | 3763 | if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 && |
cb7cf7be AS |
3764 | addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) { |
3765 | rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; | |
3766 | if (rev >= 2) { | |
3767 | val &= ~CID_ID_MASK; | |
5779ae6a | 3768 | val |= BRCM_CC_4339_CHIP_ID; |
cb7cf7be AS |
3769 | } |
3770 | } | |
3771 | return val; | |
3772 | } | |
3773 | ||
3774 | static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) | |
3775 | { | |
3776 | struct brcmf_sdio_dev *sdiodev = ctx; | |
3777 | ||
3778 | brcmf_sdiod_regwl(sdiodev, addr, val, NULL); | |
3779 | } | |
3780 | ||
3781 | static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { | |
3782 | .prepare = brcmf_sdio_buscoreprep, | |
d380ebc9 | 3783 | .activate = brcmf_sdio_buscore_activate, |
cb7cf7be AS |
3784 | .read32 = brcmf_sdio_buscore_read32, |
3785 | .write32 = brcmf_sdio_buscore_write32, | |
3786 | }; | |
3787 | ||
5b435de0 | 3788 | static bool |
82d7f3c1 | 3789 | brcmf_sdio_probe_attach(struct brcmf_sdio *bus) |
5b435de0 | 3790 | { |
4d792895 | 3791 | struct brcmf_sdio_dev *sdiodev; |
5b435de0 AS |
3792 | u8 clkctl = 0; |
3793 | int err = 0; | |
3794 | int reg_addr; | |
3795 | u32 reg_val; | |
668761ac | 3796 | u32 drivestrength; |
5b435de0 | 3797 | |
4d792895 HM |
3798 | sdiodev = bus->sdiodev; |
3799 | sdio_claim_host(sdiodev->func[1]); | |
38b0b0dd | 3800 | |
18aad4f8 | 3801 | pr_debug("F1 signature read @0x18000000=0x%4x\n", |
4d792895 | 3802 | brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL)); |
5b435de0 AS |
3803 | |
3804 | /* | |
cb7cf7be | 3805 | * Force PLL off until brcmf_chip_attach() |
5b435de0 AS |
3806 | * programs PLL control regs |
3807 | */ | |
3808 | ||
4d792895 | 3809 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
a39be27b | 3810 | BRCMF_INIT_CLKCTL1, &err); |
5b435de0 | 3811 | if (!err) |
4d792895 | 3812 | clkctl = brcmf_sdiod_regrb(sdiodev, |
a39be27b | 3813 | SBSDIO_FUNC1_CHIPCLKCSR, &err); |
5b435de0 AS |
3814 | |
3815 | if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { | |
5e8149f5 | 3816 | brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", |
5b435de0 AS |
3817 | err, BRCMF_INIT_CLKCTL1, clkctl); |
3818 | goto fail; | |
3819 | } | |
3820 | ||
4d792895 | 3821 | bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops); |
cb7cf7be AS |
3822 | if (IS_ERR(bus->ci)) { |
3823 | brcmf_err("brcmf_chip_attach failed!\n"); | |
3824 | bus->ci = NULL; | |
5b435de0 AS |
3825 | goto fail; |
3826 | } | |
af5b5e62 | 3827 | sdiodev->settings = brcmf_get_module_param(sdiodev->dev, |
4d792895 HM |
3828 | BRCMF_BUSTYPE_SDIO, |
3829 | bus->ci->chip, | |
3830 | bus->ci->chiprev); | |
af5b5e62 HM |
3831 | if (!sdiodev->settings) { |
3832 | brcmf_err("Failed to get device parameters\n"); | |
3833 | goto fail; | |
3834 | } | |
4d792895 HM |
3835 | /* platform specific configuration: |
3836 | * alignments must be at least 4 bytes for ADMA | |
3837 | */ | |
3838 | bus->head_align = ALIGNMENT; | |
3839 | bus->sgentry_align = ALIGNMENT; | |
af5b5e62 HM |
3840 | if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT) |
3841 | bus->head_align = sdiodev->settings->bus.sdio.sd_head_align; | |
3842 | if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT) | |
3843 | bus->sgentry_align = | |
3844 | sdiodev->settings->bus.sdio.sd_sgentry_align; | |
3845 | ||
4d792895 HM |
3846 | /* allocate scatter-gather table. sg support |
3847 | * will be disabled upon allocation failure. | |
3848 | */ | |
3849 | brcmf_sdiod_sgtable_alloc(sdiodev); | |
3850 | ||
3851 | #ifdef CONFIG_PM_SLEEP | |
3852 | /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ | |
3853 | * is true or when platform data OOB irq is true). | |
3854 | */ | |
3855 | if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) && | |
3856 | ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) || | |
af5b5e62 | 3857 | (sdiodev->settings->bus.sdio.oob_irq_supported))) |
4d792895 HM |
3858 | sdiodev->bus_if->wowl_supported = true; |
3859 | #endif | |
5b435de0 | 3860 | |
82d7f3c1 | 3861 | if (brcmf_sdio_kso_init(bus)) { |
4a3da990 PH |
3862 | brcmf_err("error enabling KSO\n"); |
3863 | goto fail; | |
3864 | } | |
3865 | ||
af5b5e62 HM |
3866 | if (sdiodev->settings->bus.sdio.drive_strength) |
3867 | drivestrength = sdiodev->settings->bus.sdio.drive_strength; | |
668761ac HM |
3868 | else |
3869 | drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; | |
4d792895 | 3870 | brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength); |
5b435de0 | 3871 | |
1e9ab4dd | 3872 | /* Set card control so an SDIO card reset does a WLAN backplane reset */ |
4d792895 | 3873 | reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err); |
1e9ab4dd PH |
3874 | if (err) |
3875 | goto fail; | |
3876 | ||
3877 | reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; | |
3878 | ||
4d792895 | 3879 | brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); |
1e9ab4dd PH |
3880 | if (err) |
3881 | goto fail; | |
3882 | ||
3883 | /* set PMUControl so a backplane reset does PMU state reload */ | |
e2b397f1 | 3884 | reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol); |
4d792895 | 3885 | reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err); |
1e9ab4dd PH |
3886 | if (err) |
3887 | goto fail; | |
3888 | ||
3889 | reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); | |
3890 | ||
4d792895 | 3891 | brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err); |
1e9ab4dd PH |
3892 | if (err) |
3893 | goto fail; | |
3894 | ||
4d792895 | 3895 | sdio_release_host(sdiodev->func[1]); |
38b0b0dd | 3896 | |
5b435de0 AS |
3897 | brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); |
3898 | ||
9b2d2f2a AS |
3899 | /* allocate header buffer */ |
3900 | bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); | |
3901 | if (!bus->hdrbuf) | |
3902 | return false; | |
5b435de0 AS |
3903 | /* Locate an appropriately-aligned portion of hdrbuf */ |
3904 | bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], | |
9b2d2f2a | 3905 | bus->head_align); |
5b435de0 AS |
3906 | |
3907 | /* Set the poll and/or interrupt flags */ | |
3908 | bus->intr = true; | |
3909 | bus->poll = false; | |
3910 | if (bus->poll) | |
3911 | bus->pollrate = 1; | |
3912 | ||
3913 | return true; | |
3914 | ||
3915 | fail: | |
4d792895 | 3916 | sdio_release_host(sdiodev->func[1]); |
5b435de0 AS |
3917 | return false; |
3918 | } | |
3919 | ||
5b435de0 | 3920 | static int |
82d7f3c1 | 3921 | brcmf_sdio_watchdog_thread(void *data) |
5b435de0 | 3922 | { |
e92eedf4 | 3923 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
99824643 | 3924 | int wait; |
5b435de0 AS |
3925 | |
3926 | allow_signal(SIGTERM); | |
3927 | /* Run until signal received */ | |
99824643 | 3928 | brcmf_sdiod_freezer_count(bus->sdiodev); |
5b435de0 AS |
3929 | while (1) { |
3930 | if (kthread_should_stop()) | |
3931 | break; | |
99824643 AS |
3932 | brcmf_sdiod_freezer_uncount(bus->sdiodev); |
3933 | wait = wait_for_completion_interruptible(&bus->watchdog_wait); | |
3934 | brcmf_sdiod_freezer_count(bus->sdiodev); | |
3935 | brcmf_sdiod_try_freeze(bus->sdiodev); | |
3936 | if (!wait) { | |
82d7f3c1 | 3937 | brcmf_sdio_bus_watchdog(bus); |
5b435de0 | 3938 | /* Count the tick for reference */ |
80969836 | 3939 | bus->sdcnt.tickcnt++; |
58e9df46 | 3940 | reinit_completion(&bus->watchdog_wait); |
5b435de0 AS |
3941 | } else |
3942 | break; | |
3943 | } | |
3944 | return 0; | |
3945 | } | |
3946 | ||
3947 | static void | |
82d7f3c1 | 3948 | brcmf_sdio_watchdog(unsigned long data) |
5b435de0 | 3949 | { |
e92eedf4 | 3950 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3951 | |
3952 | if (bus->watchdog_tsk) { | |
3953 | complete(&bus->watchdog_wait); | |
3954 | /* Reschedule the watchdog */ | |
4011fc49 | 3955 | if (bus->wd_active) |
5b435de0 | 3956 | mod_timer(&bus->timer, |
63ce3d5d | 3957 | jiffies + BRCMF_WD_POLL); |
5b435de0 AS |
3958 | } |
3959 | } | |
3960 | ||
6866a64a | 3961 | static const struct brcmf_bus_ops brcmf_sdio_bus_ops = { |
82d7f3c1 AS |
3962 | .stop = brcmf_sdio_bus_stop, |
3963 | .preinit = brcmf_sdio_bus_preinit, | |
82d7f3c1 AS |
3964 | .txdata = brcmf_sdio_bus_txdata, |
3965 | .txctl = brcmf_sdio_bus_txctl, | |
3966 | .rxctl = brcmf_sdio_bus_rxctl, | |
3967 | .gettxq = brcmf_sdio_bus_gettxq, | |
ff4445a8 AS |
3968 | .wowl_config = brcmf_sdio_wowl_config, |
3969 | .get_ramsize = brcmf_sdio_bus_get_ramsize, | |
3970 | .get_memdump = brcmf_sdio_bus_get_memdump, | |
d9cb2596 AS |
3971 | }; |
3972 | ||
bd0e1b1d AS |
3973 | static void brcmf_sdio_firmware_callback(struct device *dev, |
3974 | const struct firmware *code, | |
3975 | void *nvram, u32 nvram_len) | |
3976 | { | |
3977 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
3978 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
3979 | struct brcmf_sdio *bus = sdiodev->bus; | |
3980 | int err = 0; | |
3981 | u8 saveclk; | |
3982 | ||
3983 | brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev)); | |
3984 | ||
bd0e1b1d AS |
3985 | if (!bus_if->drvr) |
3986 | return; | |
3987 | ||
a1cee865 HM |
3988 | /* try to download image and nvram to the dongle */ |
3989 | bus->alp_only = true; | |
3990 | err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); | |
3991 | if (err) | |
3992 | goto fail; | |
3993 | bus->alp_only = false; | |
3994 | ||
bd0e1b1d AS |
3995 | /* Start the watchdog timer */ |
3996 | bus->sdcnt.tickcnt = 0; | |
4011fc49 | 3997 | brcmf_sdio_wd_timer(bus, true); |
bd0e1b1d AS |
3998 | |
3999 | sdio_claim_host(sdiodev->func[1]); | |
4000 | ||
4001 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
4002 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); | |
4003 | if (bus->clkstate != CLK_AVAIL) | |
4004 | goto release; | |
4005 | ||
4006 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
4007 | saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
4008 | if (!err) { | |
4009 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
4010 | (saveclk | SBSDIO_FORCE_HT), &err); | |
4011 | } | |
4012 | if (err) { | |
4013 | brcmf_err("Failed to force clock for F2: err %d\n", err); | |
4014 | goto release; | |
4015 | } | |
4016 | ||
4017 | /* Enable function 2 (frame transfers) */ | |
4018 | w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, | |
4019 | offsetof(struct sdpcmd_regs, tosbmailboxdata)); | |
4020 | err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]); | |
4021 | ||
4022 | ||
4023 | brcmf_dbg(INFO, "enable F2: err=%d\n", err); | |
4024 | ||
4025 | /* If F2 successfully enabled, set core and enable interrupts */ | |
4026 | if (!err) { | |
4027 | /* Set up the interrupt mask and enable interrupts */ | |
4028 | bus->hostintmask = HOSTINTMASK; | |
4029 | w_sdreg32(bus, bus->hostintmask, | |
4030 | offsetof(struct sdpcmd_regs, hostintmask)); | |
4031 | ||
4032 | brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err); | |
4033 | } else { | |
4034 | /* Disable F2 again */ | |
4035 | sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); | |
4036 | goto release; | |
4037 | } | |
4038 | ||
4039 | if (brcmf_chip_sr_capable(bus->ci)) { | |
4040 | brcmf_sdio_sr_init(bus); | |
4041 | } else { | |
4042 | /* Restore previous clock setting */ | |
4043 | brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
4044 | saveclk, &err); | |
4045 | } | |
4046 | ||
4047 | if (err == 0) { | |
4048 | err = brcmf_sdiod_intr_register(sdiodev); | |
4049 | if (err != 0) | |
4050 | brcmf_err("intr register failed:%d\n", err); | |
4051 | } | |
4052 | ||
4053 | /* If we didn't come up, turn off backplane clock */ | |
4054 | if (err != 0) | |
4055 | brcmf_sdio_clkctl(bus, CLK_NONE, false); | |
4056 | ||
4057 | sdio_release_host(sdiodev->func[1]); | |
4058 | ||
4059 | err = brcmf_bus_start(dev); | |
4060 | if (err != 0) { | |
4061 | brcmf_err("dongle is not responding\n"); | |
4062 | goto fail; | |
4063 | } | |
4064 | return; | |
4065 | ||
4066 | release: | |
4067 | sdio_release_host(sdiodev->func[1]); | |
4068 | fail: | |
4069 | brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); | |
4070 | device_release_driver(dev); | |
4071 | } | |
4072 | ||
82d7f3c1 | 4073 | struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) |
5b435de0 AS |
4074 | { |
4075 | int ret; | |
e92eedf4 | 4076 | struct brcmf_sdio *bus; |
99824643 | 4077 | struct workqueue_struct *wq; |
5b435de0 | 4078 | |
5b435de0 AS |
4079 | brcmf_dbg(TRACE, "Enter\n"); |
4080 | ||
5b435de0 | 4081 | /* Allocate private bus interface state */ |
e92eedf4 | 4082 | bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); |
5b435de0 AS |
4083 | if (!bus) |
4084 | goto fail; | |
4085 | ||
4086 | bus->sdiodev = sdiodev; | |
4087 | sdiodev->bus = bus; | |
b83db862 | 4088 | skb_queue_head_init(&bus->glom); |
5b435de0 AS |
4089 | bus->txbound = BRCMF_TXBOUND; |
4090 | bus->rxbound = BRCMF_RXBOUND; | |
4091 | bus->txminmax = BRCMF_TXMINMAX; | |
6bc52319 | 4092 | bus->tx_seq = SDPCM_SEQ_WRAP - 1; |
5b435de0 | 4093 | |
99824643 AS |
4094 | /* single-threaded workqueue */ |
4095 | wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM, | |
4096 | dev_name(&sdiodev->func[1]->dev)); | |
4097 | if (!wq) { | |
5e8149f5 | 4098 | brcmf_err("insufficient memory to create txworkqueue\n"); |
37ac5780 HM |
4099 | goto fail; |
4100 | } | |
99824643 AS |
4101 | brcmf_sdiod_freezer_count(sdiodev); |
4102 | INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); | |
4103 | bus->brcmf_wq = wq; | |
37ac5780 | 4104 | |
5b435de0 | 4105 | /* attempt to attach to the dongle */ |
82d7f3c1 AS |
4106 | if (!(brcmf_sdio_probe_attach(bus))) { |
4107 | brcmf_err("brcmf_sdio_probe_attach failed\n"); | |
5b435de0 AS |
4108 | goto fail; |
4109 | } | |
4110 | ||
dd43a01c | 4111 | spin_lock_init(&bus->rxctl_lock); |
fed7ec44 | 4112 | spin_lock_init(&bus->txq_lock); |
5b435de0 AS |
4113 | init_waitqueue_head(&bus->ctrl_wait); |
4114 | init_waitqueue_head(&bus->dcmd_resp_wait); | |
4115 | ||
4116 | /* Set up the watchdog timer */ | |
4117 | init_timer(&bus->timer); | |
4118 | bus->timer.data = (unsigned long)bus; | |
82d7f3c1 | 4119 | bus->timer.function = brcmf_sdio_watchdog; |
5b435de0 | 4120 | |
5b435de0 AS |
4121 | /* Initialize watchdog thread */ |
4122 | init_completion(&bus->watchdog_wait); | |
82d7f3c1 | 4123 | bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, |
99824643 AS |
4124 | bus, "brcmf_wdog/%s", |
4125 | dev_name(&sdiodev->func[1]->dev)); | |
5b435de0 | 4126 | if (IS_ERR(bus->watchdog_tsk)) { |
02f77195 | 4127 | pr_warn("brcmf_watchdog thread failed to start\n"); |
5b435de0 AS |
4128 | bus->watchdog_tsk = NULL; |
4129 | } | |
4130 | /* Initialize DPC thread */ | |
2c64e16d HM |
4131 | bus->dpc_triggered = false; |
4132 | bus->dpc_running = false; | |
5b435de0 | 4133 | |
a9ffda88 | 4134 | /* Assign bus interface call back */ |
d9cb2596 AS |
4135 | bus->sdiodev->bus_if->dev = bus->sdiodev->dev; |
4136 | bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops; | |
75d907d3 AS |
4137 | bus->sdiodev->bus_if->chip = bus->ci->chip; |
4138 | bus->sdiodev->bus_if->chiprev = bus->ci->chiprev; | |
d9cb2596 | 4139 | |
706478cb FL |
4140 | /* default sdio bus header length for tx packet */ |
4141 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
4142 | ||
4143 | /* Attach to the common layer, reserve hdr space */ | |
af5b5e62 | 4144 | ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings); |
712ac5b3 | 4145 | if (ret != 0) { |
5e8149f5 | 4146 | brcmf_err("brcmf_attach failed\n"); |
5b435de0 AS |
4147 | goto fail; |
4148 | } | |
4149 | ||
e0045bf8 HM |
4150 | /* allocate scatter-gather table. sg support |
4151 | * will be disabled upon allocation failure. | |
4152 | */ | |
4153 | brcmf_sdiod_sgtable_alloc(bus->sdiodev); | |
4154 | ||
7dd3abc1 DK |
4155 | /* Query the F2 block size, set roundup accordingly */ |
4156 | bus->blocksize = bus->sdiodev->func[2]->cur_blksize; | |
4157 | bus->roundup = min(max_roundup, bus->blocksize); | |
4158 | ||
5b435de0 | 4159 | /* Allocate buffers */ |
fad13228 | 4160 | if (bus->sdiodev->bus_if->maxctl) { |
7dd3abc1 | 4161 | bus->sdiodev->bus_if->maxctl += bus->roundup; |
fad13228 AS |
4162 | bus->rxblen = |
4163 | roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), | |
4164 | ALIGNMENT) + bus->head_align; | |
4165 | bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); | |
4166 | if (!(bus->rxbuf)) { | |
4167 | brcmf_err("rxbuf allocation failed\n"); | |
4168 | goto fail; | |
4169 | } | |
5b435de0 AS |
4170 | } |
4171 | ||
fad13228 AS |
4172 | sdio_claim_host(bus->sdiodev->func[1]); |
4173 | ||
4174 | /* Disable F2 to clear any intermediate frame state on the dongle */ | |
4175 | sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]); | |
4176 | ||
fad13228 AS |
4177 | bus->rxflow = false; |
4178 | ||
4179 | /* Done with backplane-dependent accesses, can drop clock... */ | |
4180 | brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
4181 | ||
4182 | sdio_release_host(bus->sdiodev->func[1]); | |
4183 | ||
4184 | /* ...and initialize clock/power states */ | |
4185 | bus->clkstate = CLK_SDONLY; | |
4186 | bus->idletime = BRCMF_IDLE_INTERVAL; | |
4187 | bus->idleclock = BRCMF_IDLE_ACTIVE; | |
4188 | ||
fad13228 | 4189 | /* SR state */ |
fad13228 | 4190 | bus->sr_enabled = false; |
5b435de0 | 4191 | |
80969836 | 4192 | brcmf_sdio_debugfs_create(bus); |
5b435de0 AS |
4193 | brcmf_dbg(INFO, "completed!!\n"); |
4194 | ||
46d703a7 HM |
4195 | ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev, |
4196 | brcmf_sdio_fwnames, | |
4197 | ARRAY_SIZE(brcmf_sdio_fwnames), | |
4198 | sdiodev->fw_name, sdiodev->nvram_name); | |
c1b20532 DK |
4199 | if (ret) |
4200 | goto fail; | |
4201 | ||
bd0e1b1d | 4202 | ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM, |
c1b20532 | 4203 | sdiodev->fw_name, sdiodev->nvram_name, |
bd0e1b1d | 4204 | brcmf_sdio_firmware_callback); |
5b435de0 | 4205 | if (ret != 0) { |
bd0e1b1d | 4206 | brcmf_err("async firmware request failed: %d\n", ret); |
1799ddf1 | 4207 | goto fail; |
5b435de0 | 4208 | } |
15d45b6f | 4209 | |
5b435de0 AS |
4210 | return bus; |
4211 | ||
4212 | fail: | |
9fbe2a6d | 4213 | brcmf_sdio_remove(bus); |
5b435de0 AS |
4214 | return NULL; |
4215 | } | |
4216 | ||
9fbe2a6d AS |
4217 | /* Detach and free everything */ |
4218 | void brcmf_sdio_remove(struct brcmf_sdio *bus) | |
5b435de0 | 4219 | { |
5b435de0 AS |
4220 | brcmf_dbg(TRACE, "Enter\n"); |
4221 | ||
9fbe2a6d AS |
4222 | if (bus) { |
4223 | /* De-register interrupt handler */ | |
4224 | brcmf_sdiod_intr_unregister(bus->sdiodev); | |
4225 | ||
4faf28b7 | 4226 | brcmf_detach(bus->sdiodev->dev); |
bfad4a04 | 4227 | |
e0c180ec HM |
4228 | cancel_work_sync(&bus->datawork); |
4229 | if (bus->brcmf_wq) | |
4230 | destroy_workqueue(bus->brcmf_wq); | |
4231 | ||
bfad4a04 | 4232 | if (bus->ci) { |
a1ce7a0d | 4233 | if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { |
bb350711 | 4234 | sdio_claim_host(bus->sdiodev->func[1]); |
4011fc49 | 4235 | brcmf_sdio_wd_timer(bus, false); |
bb350711 AS |
4236 | brcmf_sdio_clkctl(bus, CLK_AVAIL, false); |
4237 | /* Leave the device in state where it is | |
d380ebc9 AS |
4238 | * 'passive'. This is done by resetting all |
4239 | * necessary cores. | |
bb350711 AS |
4240 | */ |
4241 | msleep(20); | |
d380ebc9 | 4242 | brcmf_chip_set_passive(bus->ci); |
bb350711 AS |
4243 | brcmf_sdio_clkctl(bus, CLK_NONE, false); |
4244 | sdio_release_host(bus->sdiodev->func[1]); | |
4245 | } | |
cb7cf7be | 4246 | brcmf_chip_detach(bus->ci); |
9fbe2a6d | 4247 | } |
af5b5e62 HM |
4248 | if (bus->sdiodev->settings) |
4249 | brcmf_release_module_param(bus->sdiodev->settings); | |
9fbe2a6d | 4250 | |
bfad4a04 | 4251 | kfree(bus->rxbuf); |
9fbe2a6d AS |
4252 | kfree(bus->hdrbuf); |
4253 | kfree(bus); | |
4254 | } | |
5b435de0 AS |
4255 | |
4256 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4257 | } | |
4258 | ||
4011fc49 | 4259 | void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active) |
5b435de0 | 4260 | { |
5b435de0 | 4261 | /* Totally stop the timer */ |
4011fc49 | 4262 | if (!active && bus->wd_active) { |
5b435de0 | 4263 | del_timer_sync(&bus->timer); |
4011fc49 | 4264 | bus->wd_active = false; |
5b435de0 AS |
4265 | return; |
4266 | } | |
4267 | ||
ece960ea | 4268 | /* don't start the wd until fw is loaded */ |
a1ce7a0d | 4269 | if (bus->sdiodev->state != BRCMF_SDIOD_DATA) |
ece960ea FL |
4270 | return; |
4271 | ||
4011fc49 AS |
4272 | if (active) { |
4273 | if (!bus->wd_active) { | |
5b435de0 AS |
4274 | /* Create timer again when watchdog period is |
4275 | dynamically changed or in the first instance | |
4276 | */ | |
63ce3d5d | 4277 | bus->timer.expires = jiffies + BRCMF_WD_POLL; |
5b435de0 | 4278 | add_timer(&bus->timer); |
4011fc49 | 4279 | bus->wd_active = true; |
5b435de0 AS |
4280 | } else { |
4281 | /* Re arm the timer, at last watchdog period */ | |
63ce3d5d | 4282 | mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL); |
5b435de0 | 4283 | } |
5b435de0 AS |
4284 | } |
4285 | } | |
99824643 AS |
4286 | |
4287 | int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) | |
4288 | { | |
4289 | int ret; | |
4290 | ||
4291 | sdio_claim_host(bus->sdiodev->func[1]); | |
4292 | ret = brcmf_sdio_bus_sleep(bus, sleep, false); | |
4293 | sdio_release_host(bus->sdiodev->func[1]); | |
4294 | ||
4295 | return ret; | |
4296 | } | |
4297 |