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iwlwifi: track current firmware image in common code
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw-dbg.c
CommitLineData
2f89a5d7
GBA		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
fa1f2b61 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
2f89a5d7
GBA		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program;
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
26 *
27 * Contact Information:
d01c5366 28 * Intel Linux Wireless <linuxwifi@intel.com>
2f89a5d7
GBA		 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
34 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
fa1f2b61 35 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
2f89a5d7
GBA		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65#include <linux/devcoredump.h>
66
67#include "fw-dbg.h"
68#include "iwl-io.h"
69#include "mvm.h"
70#include "iwl-prph.h"
71#include "iwl-csr.h"
72
976f15a8
EG		 73#define RADIO_REG_MAX_READ 0x2ad
74static void iwl_mvm_read_radio_reg(struct iwl_mvm *mvm,
75 struct iwl_fw_error_dump_data **dump_data)
76{
77 u8 *pos = (void *)(*dump_data)->data;
78 unsigned long flags;
79 int i;
80
81 if (!iwl_trans_grab_nic_access(mvm->trans, &flags))
82 return;
83
84 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
85 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
86
87 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
88 u32 rd_cmd = RADIO_RSP_RD_CMD;
89
90 rd_cmd |= i << RADIO_RSP_ADDR_POS;
91 iwl_write_prph_no_grab(mvm->trans, RSP_RADIO_CMD, rd_cmd);
92 *pos = (u8)iwl_read_prph_no_grab(mvm->trans, RSP_RADIO_RDDAT);
93
94 pos++;
95 }
96
97 *dump_data = iwl_fw_error_next_data(*dump_data);
98
99 iwl_trans_release_nic_access(mvm->trans, &flags);
100}
101
fa1f2b61
SS		 102static void iwl_mvm_dump_rxf(struct iwl_mvm *mvm,
103 struct iwl_fw_error_dump_data **dump_data,
104 int size, u32 offset, int fifo_num)
105{
106 struct iwl_fw_error_dump_fifo *fifo_hdr;
107 u32 *fifo_data;
108 u32 fifo_len;
109 int i;
110
111 fifo_hdr = (void *)(*dump_data)->data;
112 fifo_data = (void *)fifo_hdr->data;
113 fifo_len = size;
114
115 /* No need to try to read the data if the length is 0 */
116 if (fifo_len == 0)
117 return;
118
119 /* Add a TLV for the RXF */
120 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
121 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
122
123 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
124 fifo_hdr->available_bytes =
125 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
126 RXF_RD_D_SPACE + offset));
127 fifo_hdr->wr_ptr =
128 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
129 RXF_RD_WR_PTR + offset));
130 fifo_hdr->rd_ptr =
131 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
132 RXF_RD_RD_PTR + offset));
133 fifo_hdr->fence_ptr =
134 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
135 RXF_RD_FENCE_PTR + offset));
136 fifo_hdr->fence_mode =
137 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
138 RXF_SET_FENCE_MODE + offset));
139
140 /* Lock fence */
141 iwl_trans_write_prph(mvm->trans, RXF_SET_FENCE_MODE + offset, 0x1);
142 /* Set fence pointer to the same place like WR pointer */
143 iwl_trans_write_prph(mvm->trans, RXF_LD_WR2FENCE + offset, 0x1);
144 /* Set fence offset */
145 iwl_trans_write_prph(mvm->trans,
146 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
147
148 /* Read FIFO */
149 fifo_len /= sizeof(u32); /* Size in DWORDS */
150 for (i = 0; i < fifo_len; i++)
151 fifo_data[i] = iwl_trans_read_prph(mvm->trans,
152 RXF_FIFO_RD_FENCE_INC +
153 offset);
154 *dump_data = iwl_fw_error_next_data(*dump_data);
155}
156
157static void iwl_mvm_dump_txf(struct iwl_mvm *mvm,
158 struct iwl_fw_error_dump_data **dump_data,
159 int size, u32 offset, int fifo_num)
160{
161 struct iwl_fw_error_dump_fifo *fifo_hdr;
162 u32 *fifo_data;
163 u32 fifo_len;
164 int i;
165
166 fifo_hdr = (void *)(*dump_data)->data;
167 fifo_data = (void *)fifo_hdr->data;
168 fifo_len = size;
169
170 /* No need to try to read the data if the length is 0 */
171 if (fifo_len == 0)
172 return;
173
174 /* Add a TLV for the FIFO */
175 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
176 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
177
178 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
179 fifo_hdr->available_bytes =
180 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
181 TXF_FIFO_ITEM_CNT + offset));
182 fifo_hdr->wr_ptr =
183 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
184 TXF_WR_PTR + offset));
185 fifo_hdr->rd_ptr =
186 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
187 TXF_RD_PTR + offset));
188 fifo_hdr->fence_ptr =
189 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
190 TXF_FENCE_PTR + offset));
191 fifo_hdr->fence_mode =
192 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
193 TXF_LOCK_FENCE + offset));
194
195 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
196 iwl_trans_write_prph(mvm->trans, TXF_READ_MODIFY_ADDR + offset,
197 TXF_WR_PTR + offset);
198
199 /* Dummy-read to advance the read pointer to the head */
200 iwl_trans_read_prph(mvm->trans, TXF_READ_MODIFY_DATA + offset);
201
202 /* Read FIFO */
203 fifo_len /= sizeof(u32); /* Size in DWORDS */
204 for (i = 0; i < fifo_len; i++)
205 fifo_data[i] = iwl_trans_read_prph(mvm->trans,
206 TXF_READ_MODIFY_DATA +
207 offset);
208 *dump_data = iwl_fw_error_next_data(*dump_data);
209}
210
2f89a5d7
GBA		 211static void iwl_mvm_dump_fifos(struct iwl_mvm *mvm,
212 struct iwl_fw_error_dump_data **dump_data)
213{
214 struct iwl_fw_error_dump_fifo *fifo_hdr;
d0b813fc 215 struct iwl_fwrt_shared_mem_cfg *cfg = &mvm->fwrt.smem_cfg;
2f89a5d7
GBA		 216 u32 *fifo_data;
217 u32 fifo_len;
218 unsigned long flags;
219 int i, j;
220
23ba9340 221 if (!iwl_trans_grab_nic_access(mvm->trans, &flags))
2f89a5d7
GBA		 222 return;
223
fa1f2b61
SS		 224 /* Pull RXF1 */
225 iwl_mvm_dump_rxf(mvm, dump_data, cfg->lmac[0].rxfifo1_size, 0, 0);
226 /* Pull RXF2 */
227 iwl_mvm_dump_rxf(mvm, dump_data, cfg->rxfifo2_size,
228 RXF_DIFF_FROM_PREV, 1);
229 /* Pull LMAC2 RXF1 */
d0b813fc 230 if (mvm->fwrt.smem_cfg.num_lmacs > 1)
fa1f2b61
SS		 231 iwl_mvm_dump_rxf(mvm, dump_data, cfg->lmac[1].rxfifo1_size,
232 LMAC2_PRPH_OFFSET, 2);
233
234 /* Pull TXF data from LMAC1 */
d0b813fc 235 for (i = 0; i < mvm->fwrt.smem_cfg.num_txfifo_entries; i++) {
2f89a5d7
GBA		 236 /* Mark the number of TXF we're pulling now */
237 iwl_trans_write_prph(mvm->trans, TXF_LARC_NUM, i);
fa1f2b61
SS		 238 iwl_mvm_dump_txf(mvm, dump_data, cfg->lmac[0].txfifo_size[i],
239 0, i);
240 }
2f89a5d7 241
fa1f2b61 242 /* Pull TXF data from LMAC2 */
d0b813fc
JB		 243 if (mvm->fwrt.smem_cfg.num_lmacs > 1) {
244 for (i = 0; i < mvm->fwrt.smem_cfg.num_txfifo_entries; i++) {
fa1f2b61
SS		 245 /* Mark the number of TXF we're pulling now */
246 iwl_trans_write_prph(mvm->trans,
247 TXF_LARC_NUM + LMAC2_PRPH_OFFSET,
248 i);
249 iwl_mvm_dump_txf(mvm, dump_data,
250 cfg->lmac[1].txfifo_size[i],
251 LMAC2_PRPH_OFFSET,
252 i + cfg->num_txfifo_entries);
253 }
2f89a5d7
GBA		 254 }
255
5b086414
GBA		 256 if (fw_has_capa(&mvm->fw->ucode_capa,
257 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
258 /* Pull UMAC internal TXF data from all TXFs */
259 for (i = 0;
d0b813fc 260 i < ARRAY_SIZE(mvm->fwrt.smem_cfg.internal_txfifo_size);
5b086414 261 i++) {
5b086414
GBA		 262 fifo_hdr = (void *)(*dump_data)->data;
263 fifo_data = (void *)fifo_hdr->data;
d0b813fc 264 fifo_len = mvm->fwrt.smem_cfg.internal_txfifo_size[i];
5b086414
GBA		 265
266 /* No need to try to read the data if the length is 0 */
267 if (fifo_len == 0)
268 continue;
269
270 /* Add a TLV for the internal FIFOs */
271 (*dump_data)->type =
272 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
273 (*dump_data)->len =
274 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
275
276 fifo_hdr->fifo_num = cpu_to_le32(i);
39654cb3
EG		 277
278 /* Mark the number of TXF we're pulling now */
e7c9bd1c 279 iwl_trans_write_prph(mvm->trans, TXF_CPU2_NUM, i +
d0b813fc 280 mvm->fwrt.smem_cfg.num_txfifo_entries);
39654cb3 281
5b086414
GBA		 282 fifo_hdr->available_bytes =
283 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
284 TXF_CPU2_FIFO_ITEM_CNT));
285 fifo_hdr->wr_ptr =
286 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
287 TXF_CPU2_WR_PTR));
288 fifo_hdr->rd_ptr =
289 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
290 TXF_CPU2_RD_PTR));
291 fifo_hdr->fence_ptr =
292 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
293 TXF_CPU2_FENCE_PTR));
294 fifo_hdr->fence_mode =
295 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
296 TXF_CPU2_LOCK_FENCE));
297
298 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
299 iwl_trans_write_prph(mvm->trans,
300 TXF_CPU2_READ_MODIFY_ADDR,
301 TXF_CPU2_WR_PTR);
302
303 /* Dummy-read to advance the read pointer to head */
304 iwl_trans_read_prph(mvm->trans,
305 TXF_CPU2_READ_MODIFY_DATA);
306
307 /* Read FIFO */
308 fifo_len /= sizeof(u32); /* Size in DWORDS */
309 for (j = 0; j < fifo_len; j++)
310 fifo_data[j] =
311 iwl_trans_read_prph(mvm->trans,
312 TXF_CPU2_READ_MODIFY_DATA);
313 *dump_data = iwl_fw_error_next_data(*dump_data);
314 }
315 }
316
2f89a5d7
GBA		 317 iwl_trans_release_nic_access(mvm->trans, &flags);
318}
319
320void iwl_mvm_free_fw_dump_desc(struct iwl_mvm *mvm)
321{
a509a248
EG		 322 if (mvm->fw_dump_desc != &iwl_mvm_dump_desc_assert)
323 kfree(mvm->fw_dump_desc);
2f89a5d7
GBA		 324 mvm->fw_dump_desc = NULL;
325}
326
327#define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
328#define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
329
e87e2639 330struct iwl_prph_range {
2f89a5d7 331 u32 start, end;
e87e2639
GBA		 332};
333
334static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
2f89a5d7
GBA		 335 { .start = 0x00a00000, .end = 0x00a00000 },
336 { .start = 0x00a0000c, .end = 0x00a00024 },
337 { .start = 0x00a0002c, .end = 0x00a0003c },
338 { .start = 0x00a00410, .end = 0x00a00418 },
339 { .start = 0x00a00420, .end = 0x00a00420 },
340 { .start = 0x00a00428, .end = 0x00a00428 },
341 { .start = 0x00a00430, .end = 0x00a0043c },
342 { .start = 0x00a00444, .end = 0x00a00444 },
343 { .start = 0x00a004c0, .end = 0x00a004cc },
344 { .start = 0x00a004d8, .end = 0x00a004d8 },
345 { .start = 0x00a004e0, .end = 0x00a004f0 },
346 { .start = 0x00a00840, .end = 0x00a00840 },
347 { .start = 0x00a00850, .end = 0x00a00858 },
348 { .start = 0x00a01004, .end = 0x00a01008 },
349 { .start = 0x00a01010, .end = 0x00a01010 },
350 { .start = 0x00a01018, .end = 0x00a01018 },
351 { .start = 0x00a01024, .end = 0x00a01024 },
352 { .start = 0x00a0102c, .end = 0x00a01034 },
353 { .start = 0x00a0103c, .end = 0x00a01040 },
354 { .start = 0x00a01048, .end = 0x00a01094 },
355 { .start = 0x00a01c00, .end = 0x00a01c20 },
356 { .start = 0x00a01c58, .end = 0x00a01c58 },
357 { .start = 0x00a01c7c, .end = 0x00a01c7c },
358 { .start = 0x00a01c28, .end = 0x00a01c54 },
359 { .start = 0x00a01c5c, .end = 0x00a01c5c },
360 { .start = 0x00a01c60, .end = 0x00a01cdc },
361 { .start = 0x00a01ce0, .end = 0x00a01d0c },
362 { .start = 0x00a01d18, .end = 0x00a01d20 },
363 { .start = 0x00a01d2c, .end = 0x00a01d30 },
364 { .start = 0x00a01d40, .end = 0x00a01d5c },
365 { .start = 0x00a01d80, .end = 0x00a01d80 },
366 { .start = 0x00a01d98, .end = 0x00a01d9c },
367 { .start = 0x00a01da8, .end = 0x00a01da8 },
368 { .start = 0x00a01db8, .end = 0x00a01df4 },
369 { .start = 0x00a01dc0, .end = 0x00a01dfc },
370 { .start = 0x00a01e00, .end = 0x00a01e2c },
371 { .start = 0x00a01e40, .end = 0x00a01e60 },
372 { .start = 0x00a01e68, .end = 0x00a01e6c },
373 { .start = 0x00a01e74, .end = 0x00a01e74 },
374 { .start = 0x00a01e84, .end = 0x00a01e90 },
375 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
376 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
377 { .start = 0x00a01f00, .end = 0x00a01f1c },
378 { .start = 0x00a01f44, .end = 0x00a01ffc },
379 { .start = 0x00a02000, .end = 0x00a02048 },
380 { .start = 0x00a02068, .end = 0x00a020f0 },
381 { .start = 0x00a02100, .end = 0x00a02118 },
382 { .start = 0x00a02140, .end = 0x00a0214c },
383 { .start = 0x00a02168, .end = 0x00a0218c },
384 { .start = 0x00a021c0, .end = 0x00a021c0 },
385 { .start = 0x00a02400, .end = 0x00a02410 },
386 { .start = 0x00a02418, .end = 0x00a02420 },
387 { .start = 0x00a02428, .end = 0x00a0242c },
388 { .start = 0x00a02434, .end = 0x00a02434 },
389 { .start = 0x00a02440, .end = 0x00a02460 },
390 { .start = 0x00a02468, .end = 0x00a024b0 },
391 { .start = 0x00a024c8, .end = 0x00a024cc },
392 { .start = 0x00a02500, .end = 0x00a02504 },
393 { .start = 0x00a0250c, .end = 0x00a02510 },
394 { .start = 0x00a02540, .end = 0x00a02554 },
395 { .start = 0x00a02580, .end = 0x00a025f4 },
396 { .start = 0x00a02600, .end = 0x00a0260c },
397 { .start = 0x00a02648, .end = 0x00a02650 },
398 { .start = 0x00a02680, .end = 0x00a02680 },
399 { .start = 0x00a026c0, .end = 0x00a026d0 },
400 { .start = 0x00a02700, .end = 0x00a0270c },
401 { .start = 0x00a02804, .end = 0x00a02804 },
402 { .start = 0x00a02818, .end = 0x00a0281c },
403 { .start = 0x00a02c00, .end = 0x00a02db4 },
404 { .start = 0x00a02df4, .end = 0x00a02fb0 },
405 { .start = 0x00a03000, .end = 0x00a03014 },
406 { .start = 0x00a0301c, .end = 0x00a0302c },
407 { .start = 0x00a03034, .end = 0x00a03038 },
408 { .start = 0x00a03040, .end = 0x00a03048 },
409 { .start = 0x00a03060, .end = 0x00a03068 },
410 { .start = 0x00a03070, .end = 0x00a03074 },
411 { .start = 0x00a0307c, .end = 0x00a0307c },
412 { .start = 0x00a03080, .end = 0x00a03084 },
413 { .start = 0x00a0308c, .end = 0x00a03090 },
414 { .start = 0x00a03098, .end = 0x00a03098 },
415 { .start = 0x00a030a0, .end = 0x00a030a0 },
416 { .start = 0x00a030a8, .end = 0x00a030b4 },
417 { .start = 0x00a030bc, .end = 0x00a030bc },
418 { .start = 0x00a030c0, .end = 0x00a0312c },
419 { .start = 0x00a03c00, .end = 0x00a03c5c },
420 { .start = 0x00a04400, .end = 0x00a04454 },
421 { .start = 0x00a04460, .end = 0x00a04474 },
422 { .start = 0x00a044c0, .end = 0x00a044ec },
423 { .start = 0x00a04500, .end = 0x00a04504 },
424 { .start = 0x00a04510, .end = 0x00a04538 },
425 { .start = 0x00a04540, .end = 0x00a04548 },
426 { .start = 0x00a04560, .end = 0x00a0457c },
427 { .start = 0x00a04590, .end = 0x00a04598 },
428 { .start = 0x00a045c0, .end = 0x00a045f4 },
429};
430
e87e2639
GBA		 431static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
432 { .start = 0x00a05c00, .end = 0x00a05c18 },
433 { .start = 0x00a05400, .end = 0x00a056e8 },
434 { .start = 0x00a08000, .end = 0x00a098bc },
e87e2639
GBA		 435 { .start = 0x00a02400, .end = 0x00a02758 },
436};
437
5bdaa0ef
JB		 438static void _iwl_read_prph_block(struct iwl_trans *trans, u32 start,
439 u32 len_bytes, __le32 *data)
440{
441 u32 i;
442
443 for (i = 0; i < len_bytes; i += 4)
444 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
445}
446
447static bool iwl_read_prph_block(struct iwl_trans *trans, u32 start,
448 u32 len_bytes, __le32 *data)
449{
450 unsigned long flags;
451 bool success = false;
452
453 if (iwl_trans_grab_nic_access(trans, &flags)) {
454 success = true;
455 _iwl_read_prph_block(trans, start, len_bytes, data);
456 iwl_trans_release_nic_access(trans, &flags);
457 }
458
459 return success;
460}
461
1110f8e3
JB		 462static void iwl_dump_prph(struct iwl_trans *trans,
463 struct iwl_fw_error_dump_data **data,
464 const struct iwl_prph_range *iwl_prph_dump_addr,
465 u32 range_len)
2f89a5d7
GBA		 466{
467 struct iwl_fw_error_dump_prph *prph;
468 unsigned long flags;
1110f8e3 469 u32 i;
2f89a5d7 470
23ba9340 471 if (!iwl_trans_grab_nic_access(trans, &flags))
1110f8e3 472 return;
2f89a5d7 473
e87e2639 474 for (i = 0; i < range_len; i++) {
2f89a5d7
GBA		 475 /* The range includes both boundaries */
476 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
477 iwl_prph_dump_addr[i].start + 4;
2f89a5d7 478
2f89a5d7
GBA		 479 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
480 (*data)->len = cpu_to_le32(sizeof(*prph) +
481 num_bytes_in_chunk);
482 prph = (void *)(*data)->data;
483 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2f89a5d7 484
5bdaa0ef
JB		 485 _iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
486 /* our range is inclusive, hence + 4 */
487 iwl_prph_dump_addr[i].end -
488 iwl_prph_dump_addr[i].start + 4,
489 (void *)prph->data);
2f89a5d7 490
95a451c5 491 *data = iwl_fw_error_next_data(*data);
2f89a5d7
GBA		 492 }
493
494 iwl_trans_release_nic_access(trans, &flags);
2f89a5d7
GBA		 495}
496
7e62a699
AE		 497/*
498 * alloc_sgtable - allocates scallerlist table in the given size,
499 * fills it with pages and returns it
500 * @size: the size (in bytes) of the table
501*/
502static struct scatterlist *alloc_sgtable(int size)
503{
504 int alloc_size, nents, i;
505 struct page *new_page;
506 struct scatterlist *iter;
507 struct scatterlist *table;
508
509 nents = DIV_ROUND_UP(size, PAGE_SIZE);
510 table = kcalloc(nents, sizeof(*table), GFP_KERNEL);
511 if (!table)
512 return NULL;
513 sg_init_table(table, nents);
514 iter = table;
515 for_each_sg(table, iter, sg_nents(table), i) {
516 new_page = alloc_page(GFP_KERNEL);
517 if (!new_page) {
518 /* release all previous allocated pages in the table */
519 iter = table;
520 for_each_sg(table, iter, sg_nents(table), i) {
521 new_page = sg_page(iter);
522 if (new_page)
523 __free_page(new_page);
524 }
525 return NULL;
526 }
527 alloc_size = min_t(int, size, PAGE_SIZE);
528 size -= PAGE_SIZE;
529 sg_set_page(iter, new_page, alloc_size, 0);
530 }
531 return table;
532}
533
2f89a5d7
GBA		 534void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
535{
536 struct iwl_fw_error_dump_file *dump_file;
537 struct iwl_fw_error_dump_data *dump_data;
538 struct iwl_fw_error_dump_info *dump_info;
539 struct iwl_fw_error_dump_mem *dump_mem;
540 struct iwl_fw_error_dump_trigger_desc *dump_trig;
541 struct iwl_mvm_dump_ptrs *fw_error_dump;
7e62a699 542 struct scatterlist *sg_dump_data;
2f89a5d7 543 u32 sram_len, sram_ofs;
2ed1e019 544 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = mvm->fw->dbg_mem_tlv;
976f15a8 545 u32 file_len, fifo_data_len = 0, prph_len = 0, radio_len = 0;
2ed1e019
JB		 546 u32 smem_len = mvm->fw->n_dbg_mem_tlv ? 0 : mvm->cfg->smem_len;
547 u32 sram2_len = mvm->fw->n_dbg_mem_tlv ? 0 : mvm->cfg->dccm2_len;
2f89a5d7
GBA		 548 bool monitor_dump_only = false;
549 int i;
550
33efe947
GBA		 551 if (!IWL_MVM_COLLECT_FW_ERR_DUMP &&
552 !mvm->trans->dbg_dest_tlv)
553 return;
554
2f89a5d7
GBA		 555 lockdep_assert_held(&mvm->mutex);
556
557 /* there's no point in fw dump if the bus is dead */
558 if (test_bit(STATUS_TRANS_DEAD, &mvm->trans->status)) {
559 IWL_ERR(mvm, "Skip fw error dump since bus is dead\n");
9fb7807c 560 goto out;
2f89a5d7
GBA		 561 }
562
563 if (mvm->fw_dump_trig &&
564 mvm->fw_dump_trig->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)
565 monitor_dump_only = true;
566
567 fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL);
568 if (!fw_error_dump)
9fb7807c 569 goto out;
2f89a5d7
GBA		 570
571 /* SRAM - include stack CCM if driver knows the values for it */
572 if (!mvm->cfg->dccm_offset || !mvm->cfg->dccm_len) {
573 const struct fw_img *img;
574
702e975d 575 img = &mvm->fw->img[mvm->fwrt.cur_fw_img];
2f89a5d7
GBA		 576 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
577 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
578 } else {
579 sram_ofs = mvm->cfg->dccm_offset;
580 sram_len = mvm->cfg->dccm_len;
581 }
582
583 /* reading RXF/TXF sizes */
584 if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) {
d0b813fc 585 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &mvm->fwrt.smem_cfg;
2f89a5d7
GBA		 586
587 fifo_data_len = 0;
588
fa1f2b61
SS		 589 /* Count RXF2 size */
590 if (mem_cfg->rxfifo2_size) {
2f89a5d7 591 /* Add header info */
fa1f2b61 592 fifo_data_len += mem_cfg->rxfifo2_size +
2f89a5d7
GBA		 593 sizeof(*dump_data) +
594 sizeof(struct iwl_fw_error_dump_fifo);
595 }
596
fa1f2b61
SS		 597 /* Count RXF1 sizes */
598 for (i = 0; i < mem_cfg->num_lmacs; i++) {
599 if (!mem_cfg->lmac[i].rxfifo1_size)
2f89a5d7
GBA		 600 continue;
601
602 /* Add header info */
fa1f2b61 603 fifo_data_len += mem_cfg->lmac[i].rxfifo1_size +
2f89a5d7
GBA		 604 sizeof(*dump_data) +
605 sizeof(struct iwl_fw_error_dump_fifo);
606 }
e8f0c4d8 607
fa1f2b61
SS		 608 /* Count TXF sizes */
609 for (i = 0; i < mem_cfg->num_lmacs; i++) {
610 int j;
611
612 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) {
613 if (!mem_cfg->lmac[i].txfifo_size[j])
614 continue;
615
616 /* Add header info */
617 fifo_data_len +=
618 mem_cfg->lmac[i].txfifo_size[j] +
619 sizeof(*dump_data) +
620 sizeof(struct iwl_fw_error_dump_fifo);
621 }
622 }
623
5b086414
GBA		 624 if (fw_has_capa(&mvm->fw->ucode_capa,
625 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
626 for (i = 0;
627 i < ARRAY_SIZE(mem_cfg->internal_txfifo_size);
628 i++) {
629 if (!mem_cfg->internal_txfifo_size[i])
630 continue;
631
632 /* Add header info */
633 fifo_data_len +=
634 mem_cfg->internal_txfifo_size[i] +
635 sizeof(*dump_data) +
636 sizeof(struct iwl_fw_error_dump_fifo);
637 }
638 }
639
e8f0c4d8 640 /* Make room for PRPH registers */
9eca702c
LK		 641 if (!mvm->trans->cfg->gen2) {
642 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr_comm);
643 i++) {
644 /* The range includes both boundaries */
645 int num_bytes_in_chunk =
646 iwl_prph_dump_addr_comm[i].end -
647 iwl_prph_dump_addr_comm[i].start + 4;
648
649 prph_len += sizeof(*dump_data) +
650 sizeof(struct iwl_fw_error_dump_prph) +
651 num_bytes_in_chunk;
652 }
e8f0c4d8 653 }
976f15a8 654
9eca702c 655 if (!mvm->trans->cfg->gen2 && mvm->cfg->mq_rx_supported) {
e87e2639
GBA		 656 for (i = 0; i <
657 ARRAY_SIZE(iwl_prph_dump_addr_9000); i++) {
658 /* The range includes both boundaries */
659 int num_bytes_in_chunk =
660 iwl_prph_dump_addr_9000[i].end -
661 iwl_prph_dump_addr_9000[i].start + 4;
662
663 prph_len += sizeof(*dump_data) +
664 sizeof(struct iwl_fw_error_dump_prph) +
665 num_bytes_in_chunk;
666 }
667 }
668
976f15a8
EG		 669 if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
670 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
2f89a5d7
GBA		 671 }
672
673 file_len = sizeof(*dump_file) +
674 sizeof(*dump_data) * 2 +
2f89a5d7 675 fifo_data_len +
e8f0c4d8 676 prph_len +
976f15a8 677 radio_len +
2f89a5d7
GBA		 678 sizeof(*dump_info);
679
680 /* Make room for the SMEM, if it exists */
681 if (smem_len)
682 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + smem_len;
683
684 /* Make room for the secondary SRAM, if it exists */
685 if (sram2_len)
686 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + sram2_len;
687
a6017b90 688 /* Make room for MEM segments */
2ed1e019
JB		 689 for (i = 0; i < mvm->fw->n_dbg_mem_tlv; i++) {
690 file_len += sizeof(*dump_data) + sizeof(*dump_mem) +
691 le32_to_cpu(fw_dbg_mem[i].len);
a6017b90
GBA		 692 }
693
2f89a5d7 694 /* Make room for fw's virtual image pages, if it exists */
2ba57c8b 695 if (!mvm->trans->cfg->gen2 &&
702e975d 696 mvm->fw->img[mvm->fwrt.cur_fw_img].paging_mem_size &&
235acb18
JB		 697 mvm->fwrt.fw_paging_db[0].fw_paging_block)
698 file_len += mvm->fwrt.num_of_paging_blk *
2f89a5d7
GBA		 699 (sizeof(*dump_data) +
700 sizeof(struct iwl_fw_error_dump_paging) +
701 PAGING_BLOCK_SIZE);
702
703 /* If we only want a monitor dump, reset the file length */
704 if (monitor_dump_only) {
705 file_len = sizeof(*dump_file) + sizeof(*dump_data) +
706 sizeof(*dump_info);
707 }
708
2f89a5d7
GBA		 709 if (mvm->fw_dump_desc)
710 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
711 mvm->fw_dump_desc->len;
712
2ed1e019 713 if (!mvm->fw->n_dbg_mem_tlv)
a6017b90
GBA		 714 file_len += sram_len + sizeof(*dump_mem);
715
2f89a5d7
GBA		 716 dump_file = vzalloc(file_len);
717 if (!dump_file) {
718 kfree(fw_error_dump);
9fb7807c 719 goto out;
2f89a5d7
GBA		 720 }
721
722 fw_error_dump->op_mode_ptr = dump_file;
723
724 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
725 dump_data = (void *)dump_file->data;
726
727 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
728 dump_data->len = cpu_to_le32(sizeof(*dump_info));
729 dump_info = (void *)dump_data->data;
730 dump_info->device_family =
731 mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000 ?
732 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) :
733 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8);
734 dump_info->hw_step = cpu_to_le32(CSR_HW_REV_STEP(mvm->trans->hw_rev));
735 memcpy(dump_info->fw_human_readable, mvm->fw->human_readable,
736 sizeof(dump_info->fw_human_readable));
737 strncpy(dump_info->dev_human_readable, mvm->cfg->name,
738 sizeof(dump_info->dev_human_readable));
739 strncpy(dump_info->bus_human_readable, mvm->dev->bus->name,
740 sizeof(dump_info->bus_human_readable));
741
742 dump_data = iwl_fw_error_next_data(dump_data);
743 /* We only dump the FIFOs if the FW is in error state */
976f15a8 744 if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) {
2f89a5d7 745 iwl_mvm_dump_fifos(mvm, &dump_data);
976f15a8
EG		 746 if (radio_len)
747 iwl_mvm_read_radio_reg(mvm, &dump_data);
748 }
2f89a5d7
GBA		 749
750 if (mvm->fw_dump_desc) {
751 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
752 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
753 mvm->fw_dump_desc->len);
754 dump_trig = (void *)dump_data->data;
755 memcpy(dump_trig, &mvm->fw_dump_desc->trig_desc,
756 sizeof(*dump_trig) + mvm->fw_dump_desc->len);
757
2f89a5d7
GBA		 758 dump_data = iwl_fw_error_next_data(dump_data);
759 }
760
761 /* In case we only want monitor dump, skip to dump trasport data */
762 if (monitor_dump_only)
763 goto dump_trans_data;
764
2ed1e019 765 if (!mvm->fw->n_dbg_mem_tlv) {
a6017b90
GBA		 766 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
767 dump_data->len = cpu_to_le32(sram_len + sizeof(*dump_mem));
768 dump_mem = (void *)dump_data->data;
769 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
770 dump_mem->offset = cpu_to_le32(sram_ofs);
771 iwl_trans_read_mem_bytes(mvm->trans, sram_ofs, dump_mem->data,
772 sram_len);
773 dump_data = iwl_fw_error_next_data(dump_data);
774 }
775
2ed1e019
JB		 776 for (i = 0; i < mvm->fw->n_dbg_mem_tlv; i++) {
777 u32 len = le32_to_cpu(fw_dbg_mem[i].len);
778 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
5bdaa0ef 779 bool success;
2ed1e019
JB		 780
781 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
782 dump_data->len = cpu_to_le32(len + sizeof(*dump_mem));
783 dump_mem = (void *)dump_data->data;
784 dump_mem->type = fw_dbg_mem[i].data_type;
785 dump_mem->offset = cpu_to_le32(ofs);
5bdaa0ef
JB		 786
787 switch (dump_mem->type & cpu_to_le32(FW_DBG_MEM_TYPE_MASK)) {
788 case cpu_to_le32(FW_DBG_MEM_TYPE_REGULAR):
789 iwl_trans_read_mem_bytes(mvm->trans, ofs,
790 dump_mem->data,
791 len);
792 success = true;
793 break;
794 case cpu_to_le32(FW_DBG_MEM_TYPE_PRPH):
795 success = iwl_read_prph_block(mvm->trans, ofs, len,
796 (void *)dump_mem->data);
797 break;
798 default:
799 /*
800 * shouldn't get here, we ignored this kind
801 * of TLV earlier during the TLV parsing?!
802 */
803 WARN_ON(1);
804 success = false;
805 }
806
807 if (success)
808 dump_data = iwl_fw_error_next_data(dump_data);
a6017b90 809 }
2f89a5d7
GBA		 810
811 if (smem_len) {
2f89a5d7
GBA		 812 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
813 dump_data->len = cpu_to_le32(smem_len + sizeof(*dump_mem));
814 dump_mem = (void *)dump_data->data;
815 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SMEM);
816 dump_mem->offset = cpu_to_le32(mvm->cfg->smem_offset);
817 iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->smem_offset,
818 dump_mem->data, smem_len);
a6017b90 819 dump_data = iwl_fw_error_next_data(dump_data);
2f89a5d7
GBA		 820 }
821
822 if (sram2_len) {
2f89a5d7
GBA		 823 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
824 dump_data->len = cpu_to_le32(sram2_len + sizeof(*dump_mem));
825 dump_mem = (void *)dump_data->data;
826 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
827 dump_mem->offset = cpu_to_le32(mvm->cfg->dccm2_offset);
828 iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->dccm2_offset,
829 dump_mem->data, sram2_len);
a6017b90 830 dump_data = iwl_fw_error_next_data(dump_data);
2f89a5d7
GBA		 831 }
832
2f89a5d7 833 /* Dump fw's virtual image */
2ba57c8b 834 if (!mvm->trans->cfg->gen2 &&
702e975d 835 mvm->fw->img[mvm->fwrt.cur_fw_img].paging_mem_size &&
235acb18
JB		 836 mvm->fwrt.fw_paging_db[0].fw_paging_block) {
837 for (i = 1; i < mvm->fwrt.num_of_paging_blk + 1; i++) {
2f89a5d7
GBA		 838 struct iwl_fw_error_dump_paging *paging;
839 struct page *pages =
235acb18
JB		 840 mvm->fwrt.fw_paging_db[i].fw_paging_block;
841 dma_addr_t addr = mvm->fwrt.fw_paging_db[i].fw_paging_phys;
2f89a5d7 842
2f89a5d7
GBA		 843 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
844 dump_data->len = cpu_to_le32(sizeof(*paging) +
845 PAGING_BLOCK_SIZE);
846 paging = (void *)dump_data->data;
847 paging->index = cpu_to_le32(i);
4b70f076
SS		 848 dma_sync_single_for_cpu(mvm->trans->dev, addr,
849 PAGING_BLOCK_SIZE,
850 DMA_BIDIRECTIONAL);
2f89a5d7
GBA		 851 memcpy(paging->data, page_address(pages),
852 PAGING_BLOCK_SIZE);
a6017b90 853 dump_data = iwl_fw_error_next_data(dump_data);
2f89a5d7
GBA		 854 }
855 }
856
e87e2639
GBA		 857 if (prph_len) {
858 iwl_dump_prph(mvm->trans, &dump_data,
859 iwl_prph_dump_addr_comm,
860 ARRAY_SIZE(iwl_prph_dump_addr_comm));
861
862 if (mvm->cfg->mq_rx_supported)
863 iwl_dump_prph(mvm->trans, &dump_data,
864 iwl_prph_dump_addr_9000,
865 ARRAY_SIZE(iwl_prph_dump_addr_9000));
866 }
2f89a5d7
GBA		 867
868dump_trans_data:
869 fw_error_dump->trans_ptr = iwl_trans_dump_data(mvm->trans,
870 mvm->fw_dump_trig);
871 fw_error_dump->op_mode_len = file_len;
872 if (fw_error_dump->trans_ptr)
873 file_len += fw_error_dump->trans_ptr->len;
874 dump_file->file_len = cpu_to_le32(file_len);
875
7e62a699
AE		 876 sg_dump_data = alloc_sgtable(file_len);
877 if (sg_dump_data) {
878 sg_pcopy_from_buffer(sg_dump_data,
879 sg_nents(sg_dump_data),
880 fw_error_dump->op_mode_ptr,
881 fw_error_dump->op_mode_len, 0);
c2e27e16
JB		 882 if (fw_error_dump->trans_ptr)
883 sg_pcopy_from_buffer(sg_dump_data,
884 sg_nents(sg_dump_data),
885 fw_error_dump->trans_ptr->data,
886 fw_error_dump->trans_ptr->len,
887 fw_error_dump->op_mode_len);
7e62a699
AE		 888 dev_coredumpsg(mvm->trans->dev, sg_dump_data, file_len,
889 GFP_KERNEL);
890 }
891 vfree(fw_error_dump->op_mode_ptr);
892 vfree(fw_error_dump->trans_ptr);
893 kfree(fw_error_dump);
2f89a5d7 894
9fb7807c
EG		 895out:
896 iwl_mvm_free_fw_dump_desc(mvm);
2f89a5d7
GBA		 897 mvm->fw_dump_trig = NULL;
898 clear_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status);
899}
900
a80c7a69 901const struct iwl_mvm_dump_desc iwl_mvm_dump_desc_assert = {
2f89a5d7
GBA		 902 .trig_desc = {
903 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
904 },
905};
906
907int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm,
a80c7a69
EG		 908 const struct iwl_mvm_dump_desc *desc,
909 const struct iwl_fw_dbg_trigger_tlv *trigger)
2f89a5d7
GBA		 910{
911 unsigned int delay = 0;
912
913 if (trigger)
914 delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay));
915
f45f979d
LK		 916 if (WARN(mvm->trans->state == IWL_TRANS_NO_FW,
917 "Can't collect dbg data when FW isn't alive\n"))
918 return -EIO;
919
2f89a5d7
GBA		 920 if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status))
921 return -EBUSY;
922
923 if (WARN_ON(mvm->fw_dump_desc))
924 iwl_mvm_free_fw_dump_desc(mvm);
925
926 IWL_WARN(mvm, "Collecting data: trigger %d fired.\n",
927 le32_to_cpu(desc->trig_desc.type));
928
929 mvm->fw_dump_desc = desc;
930 mvm->fw_dump_trig = trigger;
931
86bbb1e1 932 schedule_delayed_work(&mvm->fw_dump_wk, delay);
2f89a5d7
GBA		 933
934 return 0;
935}
936
937int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig,
938 const char *str, size_t len,
a80c7a69 939 const struct iwl_fw_dbg_trigger_tlv *trigger)
2f89a5d7
GBA		 940{
941 struct iwl_mvm_dump_desc *desc;
942
943 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
944 if (!desc)
945 return -ENOMEM;
946
947 desc->len = len;
948 desc->trig_desc.type = cpu_to_le32(trig);
949 memcpy(desc->trig_desc.data, str, len);
950
951 return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger);
952}
953
954int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm,
955 struct iwl_fw_dbg_trigger_tlv *trigger,
956 const char *fmt, ...)
957{
958 u16 occurrences = le16_to_cpu(trigger->occurrences);
959 int ret, len = 0;
960 char buf[64];
961
962 if (!occurrences)
963 return 0;
964
965 if (fmt) {
966 va_list ap;
967
968 buf[sizeof(buf) - 1] = '\0';
969
970 va_start(ap, fmt);
971 vsnprintf(buf, sizeof(buf), fmt, ap);
972 va_end(ap);
973
974 /* check for truncation */
975 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
976 buf[sizeof(buf) - 1] = '\0';
977
978 len = strlen(buf) + 1;
979 }
980
981 ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len,
982 trigger);
983
984 if (ret)
985 return ret;
986
987 trigger->occurrences = cpu_to_le16(occurrences - 1);
988 return 0;
989}
990
2f89a5d7
GBA		 991int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id)
992{
993 u8 *ptr;
994 int ret;
995 int i;
996
997 if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv),
998 "Invalid configuration %d\n", conf_id))
999 return -EINVAL;
1000
1001 /* EARLY START - firmware's configuration is hard coded */
1002 if ((!mvm->fw->dbg_conf_tlv[conf_id] ||
1003 !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
addce854 1004 conf_id == FW_DBG_START_FROM_ALIVE)
2f89a5d7 1005 return 0;
2f89a5d7
GBA		 1006
1007 if (!mvm->fw->dbg_conf_tlv[conf_id])
1008 return -EINVAL;
1009
1010 if (mvm->fw_dbg_conf != FW_DBG_INVALID)
1011 IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n",
1012 mvm->fw_dbg_conf);
1013
1014 /* Send all HCMDs for configuring the FW debug */
1015 ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd;
1016 for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) {
1017 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
1018
1019 ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0,
1020 le16_to_cpu(cmd->len), cmd->data);
1021 if (ret)
1022 return ret;
1023
1024 ptr += sizeof(*cmd);
1025 ptr += le16_to_cpu(cmd->len);
1026 }
1027
1028 mvm->fw_dbg_conf = conf_id;
ff6e58e6
EG		 1029
1030 return 0;
2f89a5d7 1031}
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