projects / mirror_ubuntu-hirsute-kernel.git / blame
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1 | /****************************************************************************** |
| 2 | * | |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
| 4 | * redistributing this file, you may do so under either license. | |
| 5 | * | |
| 6 | * GPL LICENSE SUMMARY | |
| 7 | * | |
| 8 | * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. | |
| 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
| 10 | * Copyright(c) 2015 Intel Deutschland GmbH | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of version 2 of the GNU General Public License as | |
| 14 | * published by the Free Software Foundation. | |
| 15 | * | |
| 16 | * This program is distributed in the hope that it will be useful, but | |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 19 | * General Public License for more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License | |
| 22 | * along with this program; | |
| 23 | * | |
| 24 | * The full GNU General Public License is included in this distribution | |
| 25 | * in the file called COPYING. | |
| 26 | * | |
| 27 | * Contact Information: | |
| d01c5366 | 28 | * Intel Linux Wireless <linuxwifi@intel.com> |
| 2f89a5d7 GBA |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 30 | * | |
| 31 | * BSD LICENSE | |
| 32 | * | |
| 33 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. | |
| 34 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
| 35 | * Copyright(c) 2015 Intel Deutschland GmbH | |
| 36 | * All rights reserved. | |
| 37 | * | |
| 38 | * Redistribution and use in source and binary forms, with or without | |
| 39 | * modification, are permitted provided that the following conditions | |
| 40 | * are met: | |
| 41 | * | |
| 42 | * * Redistributions of source code must retain the above copyright | |
| 43 | * notice, this list of conditions and the following disclaimer. | |
| 44 | * * Redistributions in binary form must reproduce the above copyright | |
| 45 | * notice, this list of conditions and the following disclaimer in | |
| 46 | * the documentation and/or other materials provided with the | |
| 47 | * distribution. | |
| 48 | * * Neither the name Intel Corporation nor the names of its | |
| 49 | * contributors may be used to endorse or promote products derived | |
| 50 | * from this software without specific prior written permission. | |
| 51 | * | |
| 52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 63 | * | |
| 64 | *****************************************************************************/ | |
| 65 | #include <linux/devcoredump.h> | |
| 66 | ||
| 67 | #include "fw-dbg.h" | |
| 68 | #include "iwl-io.h" | |
| 69 | #include "mvm.h" | |
| 70 | #include "iwl-prph.h" | |
| 71 | #include "iwl-csr.h" | |
| 72 | ||
| 73 | static ssize_t iwl_mvm_read_coredump(char *buffer, loff_t offset, size_t count, | |
| 74 | const void *data, size_t datalen) | |
| 75 | { | |
| 76 | const struct iwl_mvm_dump_ptrs *dump_ptrs = data; | |
| 77 | ssize_t bytes_read; | |
| 78 | ssize_t bytes_read_trans; | |
| 79 | ||
| 80 | if (offset < dump_ptrs->op_mode_len) { | |
| 81 | bytes_read = min_t(ssize_t, count, | |
| 82 | dump_ptrs->op_mode_len - offset); | |
| 83 | memcpy(buffer, (u8 *)dump_ptrs->op_mode_ptr + offset, | |
| 84 | bytes_read); | |
| 85 | offset += bytes_read; | |
| 86 | count -= bytes_read; | |
| 87 | ||
| 88 | if (count == 0) | |
| 89 | return bytes_read; | |
| 90 | } else { | |
| 91 | bytes_read = 0; | |
| 92 | } | |
| 93 | ||
| 94 | if (!dump_ptrs->trans_ptr) | |
| 95 | return bytes_read; | |
| 96 | ||
| 97 | offset -= dump_ptrs->op_mode_len; | |
| 98 | bytes_read_trans = min_t(ssize_t, count, | |
| 99 | dump_ptrs->trans_ptr->len - offset); | |
| 100 | memcpy(buffer + bytes_read, | |
| 101 | (u8 *)dump_ptrs->trans_ptr->data + offset, | |
| 102 | bytes_read_trans); | |
| 103 | ||
| 104 | return bytes_read + bytes_read_trans; | |
| 105 | } | |
| 106 | ||
| 107 | static void iwl_mvm_free_coredump(const void *data) | |
| 108 | { | |
| 109 | const struct iwl_mvm_dump_ptrs *fw_error_dump = data; | |
| 110 | ||
| 111 | vfree(fw_error_dump->op_mode_ptr); | |
| 112 | vfree(fw_error_dump->trans_ptr); | |
| 113 | kfree(fw_error_dump); | |
| 114 | } | |
| 115 | ||
| 116 | static void iwl_mvm_dump_fifos(struct iwl_mvm *mvm, | |
| 117 | struct iwl_fw_error_dump_data **dump_data) | |
| 118 | { | |
| 119 | struct iwl_fw_error_dump_fifo *fifo_hdr; | |
| 120 | u32 *fifo_data; | |
| 121 | u32 fifo_len; | |
| 122 | unsigned long flags; | |
| 123 | int i, j; | |
| 124 | ||
| 23ba9340 | 125 | if (!iwl_trans_grab_nic_access(mvm->trans, &flags)) |
| 2f89a5d7 GBA |
126 | return; |
| 127 | ||
| 128 | /* Pull RXF data from all RXFs */ | |
| 129 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) { | |
| 130 | /* | |
| 131 | * Keep aside the additional offset that might be needed for | |
| 132 | * next RXF | |
| 133 | */ | |
| 134 | u32 offset_diff = RXF_DIFF_FROM_PREV * i; | |
| 135 | ||
| 136 | fifo_hdr = (void *)(*dump_data)->data; | |
| 137 | fifo_data = (void *)fifo_hdr->data; | |
| 138 | fifo_len = mvm->shared_mem_cfg.rxfifo_size[i]; | |
| 139 | ||
| 140 | /* No need to try to read the data if the length is 0 */ | |
| 141 | if (fifo_len == 0) | |
| 142 | continue; | |
| 143 | ||
| 144 | /* Add a TLV for the RXF */ | |
| 145 | (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); | |
| 146 | (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); | |
| 147 | ||
| 148 | fifo_hdr->fifo_num = cpu_to_le32(i); | |
| 149 | fifo_hdr->available_bytes = | |
| 150 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 151 | RXF_RD_D_SPACE + | |
| 152 | offset_diff)); | |
| 153 | fifo_hdr->wr_ptr = | |
| 154 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 155 | RXF_RD_WR_PTR + | |
| 156 | offset_diff)); | |
| 157 | fifo_hdr->rd_ptr = | |
| 158 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 159 | RXF_RD_RD_PTR + | |
| 160 | offset_diff)); | |
| 161 | fifo_hdr->fence_ptr = | |
| 162 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 163 | RXF_RD_FENCE_PTR + | |
| 164 | offset_diff)); | |
| 165 | fifo_hdr->fence_mode = | |
| 166 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 167 | RXF_SET_FENCE_MODE + | |
| 168 | offset_diff)); | |
| 169 | ||
| 170 | /* Lock fence */ | |
| 171 | iwl_trans_write_prph(mvm->trans, | |
| 172 | RXF_SET_FENCE_MODE + offset_diff, 0x1); | |
| 173 | /* Set fence pointer to the same place like WR pointer */ | |
| 174 | iwl_trans_write_prph(mvm->trans, | |
| 175 | RXF_LD_WR2FENCE + offset_diff, 0x1); | |
| 176 | /* Set fence offset */ | |
| 177 | iwl_trans_write_prph(mvm->trans, | |
| 178 | RXF_LD_FENCE_OFFSET_ADDR + offset_diff, | |
| 179 | 0x0); | |
| 180 | ||
| 181 | /* Read FIFO */ | |
| 182 | fifo_len /= sizeof(u32); /* Size in DWORDS */ | |
| 183 | for (j = 0; j < fifo_len; j++) | |
| 184 | fifo_data[j] = iwl_trans_read_prph(mvm->trans, | |
| 185 | RXF_FIFO_RD_FENCE_INC + | |
| 186 | offset_diff); | |
| 187 | *dump_data = iwl_fw_error_next_data(*dump_data); | |
| 188 | } | |
| 189 | ||
| 190 | /* Pull TXF data from all TXFs */ | |
| 191 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) { | |
| 192 | /* Mark the number of TXF we're pulling now */ | |
| 193 | iwl_trans_write_prph(mvm->trans, TXF_LARC_NUM, i); | |
| 194 | ||
| 195 | fifo_hdr = (void *)(*dump_data)->data; | |
| 196 | fifo_data = (void *)fifo_hdr->data; | |
| 197 | fifo_len = mvm->shared_mem_cfg.txfifo_size[i]; | |
| 198 | ||
| 199 | /* No need to try to read the data if the length is 0 */ | |
| 200 | if (fifo_len == 0) | |
| 201 | continue; | |
| 202 | ||
| 203 | /* Add a TLV for the FIFO */ | |
| 204 | (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); | |
| 205 | (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); | |
| 206 | ||
| 207 | fifo_hdr->fifo_num = cpu_to_le32(i); | |
| 208 | fifo_hdr->available_bytes = | |
| 209 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 210 | TXF_FIFO_ITEM_CNT)); | |
| 211 | fifo_hdr->wr_ptr = | |
| 212 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 213 | TXF_WR_PTR)); | |
| 214 | fifo_hdr->rd_ptr = | |
| 215 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 216 | TXF_RD_PTR)); | |
| 217 | fifo_hdr->fence_ptr = | |
| 218 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 219 | TXF_FENCE_PTR)); | |
| 220 | fifo_hdr->fence_mode = | |
| 221 | cpu_to_le32(iwl_trans_read_prph(mvm->trans, | |
| 222 | TXF_LOCK_FENCE)); | |
| 223 | ||
| 224 | /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ | |
| 225 | iwl_trans_write_prph(mvm->trans, TXF_READ_MODIFY_ADDR, | |
| 226 | TXF_WR_PTR); | |
| 227 | ||
| 228 | /* Dummy-read to advance the read pointer to the head */ | |
| 229 | iwl_trans_read_prph(mvm->trans, TXF_READ_MODIFY_DATA); | |
| 230 | ||
| 231 | /* Read FIFO */ | |
| 232 | fifo_len /= sizeof(u32); /* Size in DWORDS */ | |
| 233 | for (j = 0; j < fifo_len; j++) | |
| 234 | fifo_data[j] = iwl_trans_read_prph(mvm->trans, | |
| 235 | TXF_READ_MODIFY_DATA); | |
| 236 | *dump_data = iwl_fw_error_next_data(*dump_data); | |
| 237 | } | |
| 238 | ||
| 239 | iwl_trans_release_nic_access(mvm->trans, &flags); | |
| 240 | } | |
| 241 | ||
| 242 | void iwl_mvm_free_fw_dump_desc(struct iwl_mvm *mvm) | |
| 243 | { | |
| 244 | if (mvm->fw_dump_desc == &iwl_mvm_dump_desc_assert || | |
| 245 | !mvm->fw_dump_desc) | |
| 246 | return; | |
| 247 | ||
| 248 | kfree(mvm->fw_dump_desc); | |
| 249 | mvm->fw_dump_desc = NULL; | |
| 250 | } | |
| 251 | ||
| 252 | #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ | |
| 253 | #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ | |
| 254 | ||
| 255 | static const struct { | |
| 256 | u32 start, end; | |
| 257 | } iwl_prph_dump_addr[] = { | |
| 258 | { .start = 0x00a00000, .end = 0x00a00000 }, | |
| 259 | { .start = 0x00a0000c, .end = 0x00a00024 }, | |
| 260 | { .start = 0x00a0002c, .end = 0x00a0003c }, | |
| 261 | { .start = 0x00a00410, .end = 0x00a00418 }, | |
| 262 | { .start = 0x00a00420, .end = 0x00a00420 }, | |
| 263 | { .start = 0x00a00428, .end = 0x00a00428 }, | |
| 264 | { .start = 0x00a00430, .end = 0x00a0043c }, | |
| 265 | { .start = 0x00a00444, .end = 0x00a00444 }, | |
| 266 | { .start = 0x00a004c0, .end = 0x00a004cc }, | |
| 267 | { .start = 0x00a004d8, .end = 0x00a004d8 }, | |
| 268 | { .start = 0x00a004e0, .end = 0x00a004f0 }, | |
| 269 | { .start = 0x00a00840, .end = 0x00a00840 }, | |
| 270 | { .start = 0x00a00850, .end = 0x00a00858 }, | |
| 271 | { .start = 0x00a01004, .end = 0x00a01008 }, | |
| 272 | { .start = 0x00a01010, .end = 0x00a01010 }, | |
| 273 | { .start = 0x00a01018, .end = 0x00a01018 }, | |
| 274 | { .start = 0x00a01024, .end = 0x00a01024 }, | |
| 275 | { .start = 0x00a0102c, .end = 0x00a01034 }, | |
| 276 | { .start = 0x00a0103c, .end = 0x00a01040 }, | |
| 277 | { .start = 0x00a01048, .end = 0x00a01094 }, | |
| 278 | { .start = 0x00a01c00, .end = 0x00a01c20 }, | |
| 279 | { .start = 0x00a01c58, .end = 0x00a01c58 }, | |
| 280 | { .start = 0x00a01c7c, .end = 0x00a01c7c }, | |
| 281 | { .start = 0x00a01c28, .end = 0x00a01c54 }, | |
| 282 | { .start = 0x00a01c5c, .end = 0x00a01c5c }, | |
| 283 | { .start = 0x00a01c60, .end = 0x00a01cdc }, | |
| 284 | { .start = 0x00a01ce0, .end = 0x00a01d0c }, | |
| 285 | { .start = 0x00a01d18, .end = 0x00a01d20 }, | |
| 286 | { .start = 0x00a01d2c, .end = 0x00a01d30 }, | |
| 287 | { .start = 0x00a01d40, .end = 0x00a01d5c }, | |
| 288 | { .start = 0x00a01d80, .end = 0x00a01d80 }, | |
| 289 | { .start = 0x00a01d98, .end = 0x00a01d9c }, | |
| 290 | { .start = 0x00a01da8, .end = 0x00a01da8 }, | |
| 291 | { .start = 0x00a01db8, .end = 0x00a01df4 }, | |
| 292 | { .start = 0x00a01dc0, .end = 0x00a01dfc }, | |
| 293 | { .start = 0x00a01e00, .end = 0x00a01e2c }, | |
| 294 | { .start = 0x00a01e40, .end = 0x00a01e60 }, | |
| 295 | { .start = 0x00a01e68, .end = 0x00a01e6c }, | |
| 296 | { .start = 0x00a01e74, .end = 0x00a01e74 }, | |
| 297 | { .start = 0x00a01e84, .end = 0x00a01e90 }, | |
| 298 | { .start = 0x00a01e9c, .end = 0x00a01ec4 }, | |
| 299 | { .start = 0x00a01ed0, .end = 0x00a01ee0 }, | |
| 300 | { .start = 0x00a01f00, .end = 0x00a01f1c }, | |
| 301 | { .start = 0x00a01f44, .end = 0x00a01ffc }, | |
| 302 | { .start = 0x00a02000, .end = 0x00a02048 }, | |
| 303 | { .start = 0x00a02068, .end = 0x00a020f0 }, | |
| 304 | { .start = 0x00a02100, .end = 0x00a02118 }, | |
| 305 | { .start = 0x00a02140, .end = 0x00a0214c }, | |
| 306 | { .start = 0x00a02168, .end = 0x00a0218c }, | |
| 307 | { .start = 0x00a021c0, .end = 0x00a021c0 }, | |
| 308 | { .start = 0x00a02400, .end = 0x00a02410 }, | |
| 309 | { .start = 0x00a02418, .end = 0x00a02420 }, | |
| 310 | { .start = 0x00a02428, .end = 0x00a0242c }, | |
| 311 | { .start = 0x00a02434, .end = 0x00a02434 }, | |
| 312 | { .start = 0x00a02440, .end = 0x00a02460 }, | |
| 313 | { .start = 0x00a02468, .end = 0x00a024b0 }, | |
| 314 | { .start = 0x00a024c8, .end = 0x00a024cc }, | |
| 315 | { .start = 0x00a02500, .end = 0x00a02504 }, | |
| 316 | { .start = 0x00a0250c, .end = 0x00a02510 }, | |
| 317 | { .start = 0x00a02540, .end = 0x00a02554 }, | |
| 318 | { .start = 0x00a02580, .end = 0x00a025f4 }, | |
| 319 | { .start = 0x00a02600, .end = 0x00a0260c }, | |
| 320 | { .start = 0x00a02648, .end = 0x00a02650 }, | |
| 321 | { .start = 0x00a02680, .end = 0x00a02680 }, | |
| 322 | { .start = 0x00a026c0, .end = 0x00a026d0 }, | |
| 323 | { .start = 0x00a02700, .end = 0x00a0270c }, | |
| 324 | { .start = 0x00a02804, .end = 0x00a02804 }, | |
| 325 | { .start = 0x00a02818, .end = 0x00a0281c }, | |
| 326 | { .start = 0x00a02c00, .end = 0x00a02db4 }, | |
| 327 | { .start = 0x00a02df4, .end = 0x00a02fb0 }, | |
| 328 | { .start = 0x00a03000, .end = 0x00a03014 }, | |
| 329 | { .start = 0x00a0301c, .end = 0x00a0302c }, | |
| 330 | { .start = 0x00a03034, .end = 0x00a03038 }, | |
| 331 | { .start = 0x00a03040, .end = 0x00a03048 }, | |
| 332 | { .start = 0x00a03060, .end = 0x00a03068 }, | |
| 333 | { .start = 0x00a03070, .end = 0x00a03074 }, | |
| 334 | { .start = 0x00a0307c, .end = 0x00a0307c }, | |
| 335 | { .start = 0x00a03080, .end = 0x00a03084 }, | |
| 336 | { .start = 0x00a0308c, .end = 0x00a03090 }, | |
| 337 | { .start = 0x00a03098, .end = 0x00a03098 }, | |
| 338 | { .start = 0x00a030a0, .end = 0x00a030a0 }, | |
| 339 | { .start = 0x00a030a8, .end = 0x00a030b4 }, | |
| 340 | { .start = 0x00a030bc, .end = 0x00a030bc }, | |
| 341 | { .start = 0x00a030c0, .end = 0x00a0312c }, | |
| 342 | { .start = 0x00a03c00, .end = 0x00a03c5c }, | |
| 343 | { .start = 0x00a04400, .end = 0x00a04454 }, | |
| 344 | { .start = 0x00a04460, .end = 0x00a04474 }, | |
| 345 | { .start = 0x00a044c0, .end = 0x00a044ec }, | |
| 346 | { .start = 0x00a04500, .end = 0x00a04504 }, | |
| 347 | { .start = 0x00a04510, .end = 0x00a04538 }, | |
| 348 | { .start = 0x00a04540, .end = 0x00a04548 }, | |
| 349 | { .start = 0x00a04560, .end = 0x00a0457c }, | |
| 350 | { .start = 0x00a04590, .end = 0x00a04598 }, | |
| 351 | { .start = 0x00a045c0, .end = 0x00a045f4 }, | |
| e8f0c4d8 | 352 | { .start = 0x00a44000, .end = 0x00a7bf80 }, |
| 2f89a5d7 GBA |
353 | }; |
| 354 | ||
| 355 | static u32 iwl_dump_prph(struct iwl_trans *trans, | |
| 356 | struct iwl_fw_error_dump_data **data) | |
| 357 | { | |
| 358 | struct iwl_fw_error_dump_prph *prph; | |
| 359 | unsigned long flags; | |
| 360 | u32 prph_len = 0, i; | |
| 361 | ||
| 23ba9340 | 362 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
| 2f89a5d7 GBA |
363 | return 0; |
| 364 | ||
| 365 | for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) { | |
| 366 | /* The range includes both boundaries */ | |
| 367 | int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - | |
| 368 | iwl_prph_dump_addr[i].start + 4; | |
| 369 | int reg; | |
| 370 | __le32 *val; | |
| 371 | ||
| 372 | prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk; | |
| 373 | ||
| 374 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); | |
| 375 | (*data)->len = cpu_to_le32(sizeof(*prph) + | |
| 376 | num_bytes_in_chunk); | |
| 377 | prph = (void *)(*data)->data; | |
| 378 | prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); | |
| 379 | val = (void *)prph->data; | |
| 380 | ||
| 381 | for (reg = iwl_prph_dump_addr[i].start; | |
| 382 | reg <= iwl_prph_dump_addr[i].end; | |
| 383 | reg += 4) | |
| 384 | *val++ = cpu_to_le32(iwl_read_prph_no_grab(trans, | |
| 385 | reg)); | |
| 386 | ||
| 95a451c5 | 387 | *data = iwl_fw_error_next_data(*data); |
| 2f89a5d7 GBA |
388 | } |
| 389 | ||
| 390 | iwl_trans_release_nic_access(trans, &flags); | |
| 391 | ||
| 392 | return prph_len; | |
| 393 | } | |
| 394 | ||
| 395 | void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm) | |
| 396 | { | |
| 397 | struct iwl_fw_error_dump_file *dump_file; | |
| 398 | struct iwl_fw_error_dump_data *dump_data; | |
| 399 | struct iwl_fw_error_dump_info *dump_info; | |
| 400 | struct iwl_fw_error_dump_mem *dump_mem; | |
| 401 | struct iwl_fw_error_dump_trigger_desc *dump_trig; | |
| 402 | struct iwl_mvm_dump_ptrs *fw_error_dump; | |
| 403 | u32 sram_len, sram_ofs; | |
| e8f0c4d8 | 404 | u32 file_len, fifo_data_len = 0, prph_len = 0; |
| 2f89a5d7 GBA |
405 | u32 smem_len = mvm->cfg->smem_len; |
| 406 | u32 sram2_len = mvm->cfg->dccm2_len; | |
| 407 | bool monitor_dump_only = false; | |
| 408 | int i; | |
| 409 | ||
| 410 | lockdep_assert_held(&mvm->mutex); | |
| 411 | ||
| 412 | /* there's no point in fw dump if the bus is dead */ | |
| 413 | if (test_bit(STATUS_TRANS_DEAD, &mvm->trans->status)) { | |
| 414 | IWL_ERR(mvm, "Skip fw error dump since bus is dead\n"); | |
| 415 | return; | |
| 416 | } | |
| 417 | ||
| 418 | if (mvm->fw_dump_trig && | |
| 419 | mvm->fw_dump_trig->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY) | |
| 420 | monitor_dump_only = true; | |
| 421 | ||
| 422 | fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL); | |
| 423 | if (!fw_error_dump) | |
| 424 | return; | |
| 425 | ||
| 426 | /* SRAM - include stack CCM if driver knows the values for it */ | |
| 427 | if (!mvm->cfg->dccm_offset || !mvm->cfg->dccm_len) { | |
| 428 | const struct fw_img *img; | |
| 429 | ||
| 430 | img = &mvm->fw->img[mvm->cur_ucode]; | |
| 431 | sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; | |
| 432 | sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; | |
| 433 | } else { | |
| 434 | sram_ofs = mvm->cfg->dccm_offset; | |
| 435 | sram_len = mvm->cfg->dccm_len; | |
| 436 | } | |
| 437 | ||
| 438 | /* reading RXF/TXF sizes */ | |
| 439 | if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) { | |
| 440 | struct iwl_mvm_shared_mem_cfg *mem_cfg = &mvm->shared_mem_cfg; | |
| 441 | ||
| 442 | fifo_data_len = 0; | |
| 443 | ||
| 444 | /* Count RXF size */ | |
| 445 | for (i = 0; i < ARRAY_SIZE(mem_cfg->rxfifo_size); i++) { | |
| 446 | if (!mem_cfg->rxfifo_size[i]) | |
| 447 | continue; | |
| 448 | ||
| 449 | /* Add header info */ | |
| 450 | fifo_data_len += mem_cfg->rxfifo_size[i] + | |
| 451 | sizeof(*dump_data) + | |
| 452 | sizeof(struct iwl_fw_error_dump_fifo); | |
| 453 | } | |
| 454 | ||
| 455 | for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++) { | |
| 456 | if (!mem_cfg->txfifo_size[i]) | |
| 457 | continue; | |
| 458 | ||
| 459 | /* Add header info */ | |
| 460 | fifo_data_len += mem_cfg->txfifo_size[i] + | |
| 461 | sizeof(*dump_data) + | |
| 462 | sizeof(struct iwl_fw_error_dump_fifo); | |
| 463 | } | |
| e8f0c4d8 EG |
464 | |
| 465 | /* Make room for PRPH registers */ | |
| 466 | for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) { | |
| 467 | /* The range includes both boundaries */ | |
| 468 | int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - | |
| 469 | iwl_prph_dump_addr[i].start + 4; | |
| 470 | ||
| 471 | prph_len += sizeof(*dump_data) + | |
| 472 | sizeof(struct iwl_fw_error_dump_prph) + | |
| 473 | num_bytes_in_chunk; | |
| 474 | } | |
| 2f89a5d7 GBA |
475 | } |
| 476 | ||
| 477 | file_len = sizeof(*dump_file) + | |
| 478 | sizeof(*dump_data) * 2 + | |
| 479 | sram_len + sizeof(*dump_mem) + | |
| 480 | fifo_data_len + | |
| e8f0c4d8 | 481 | prph_len + |
| 2f89a5d7 GBA |
482 | sizeof(*dump_info); |
| 483 | ||
| 484 | /* Make room for the SMEM, if it exists */ | |
| 485 | if (smem_len) | |
| 486 | file_len += sizeof(*dump_data) + sizeof(*dump_mem) + smem_len; | |
| 487 | ||
| 488 | /* Make room for the secondary SRAM, if it exists */ | |
| 489 | if (sram2_len) | |
| 490 | file_len += sizeof(*dump_data) + sizeof(*dump_mem) + sram2_len; | |
| 491 | ||
| 492 | /* Make room for fw's virtual image pages, if it exists */ | |
| 493 | if (mvm->fw->img[mvm->cur_ucode].paging_mem_size) | |
| 494 | file_len += mvm->num_of_paging_blk * | |
| 495 | (sizeof(*dump_data) + | |
| 496 | sizeof(struct iwl_fw_error_dump_paging) + | |
| 497 | PAGING_BLOCK_SIZE); | |
| 498 | ||
| 499 | /* If we only want a monitor dump, reset the file length */ | |
| 500 | if (monitor_dump_only) { | |
| 501 | file_len = sizeof(*dump_file) + sizeof(*dump_data) + | |
| 502 | sizeof(*dump_info); | |
| 503 | } | |
| 504 | ||
| 2f89a5d7 GBA |
505 | /* |
| 506 | * In 8000 HW family B-step include the ICCM (which resides separately) | |
| 507 | */ | |
| 508 | if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000 && | |
| 509 | CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP) | |
| 510 | file_len += sizeof(*dump_data) + sizeof(*dump_mem) + | |
| 511 | IWL8260_ICCM_LEN; | |
| 512 | ||
| 513 | if (mvm->fw_dump_desc) | |
| 514 | file_len += sizeof(*dump_data) + sizeof(*dump_trig) + | |
| 515 | mvm->fw_dump_desc->len; | |
| 516 | ||
| 517 | dump_file = vzalloc(file_len); | |
| 518 | if (!dump_file) { | |
| 519 | kfree(fw_error_dump); | |
| 520 | iwl_mvm_free_fw_dump_desc(mvm); | |
| 521 | return; | |
| 522 | } | |
| 523 | ||
| 524 | fw_error_dump->op_mode_ptr = dump_file; | |
| 525 | ||
| 526 | dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); | |
| 527 | dump_data = (void *)dump_file->data; | |
| 528 | ||
| 529 | dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); | |
| 530 | dump_data->len = cpu_to_le32(sizeof(*dump_info)); | |
| 531 | dump_info = (void *)dump_data->data; | |
| 532 | dump_info->device_family = | |
| 533 | mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000 ? | |
| 534 | cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) : | |
| 535 | cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8); | |
| 536 | dump_info->hw_step = cpu_to_le32(CSR_HW_REV_STEP(mvm->trans->hw_rev)); | |
| 537 | memcpy(dump_info->fw_human_readable, mvm->fw->human_readable, | |
| 538 | sizeof(dump_info->fw_human_readable)); | |
| 539 | strncpy(dump_info->dev_human_readable, mvm->cfg->name, | |
| 540 | sizeof(dump_info->dev_human_readable)); | |
| 541 | strncpy(dump_info->bus_human_readable, mvm->dev->bus->name, | |
| 542 | sizeof(dump_info->bus_human_readable)); | |
| 543 | ||
| 544 | dump_data = iwl_fw_error_next_data(dump_data); | |
| 545 | /* We only dump the FIFOs if the FW is in error state */ | |
| 546 | if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) | |
| 547 | iwl_mvm_dump_fifos(mvm, &dump_data); | |
| 548 | ||
| 549 | if (mvm->fw_dump_desc) { | |
| 550 | dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); | |
| 551 | dump_data->len = cpu_to_le32(sizeof(*dump_trig) + | |
| 552 | mvm->fw_dump_desc->len); | |
| 553 | dump_trig = (void *)dump_data->data; | |
| 554 | memcpy(dump_trig, &mvm->fw_dump_desc->trig_desc, | |
| 555 | sizeof(*dump_trig) + mvm->fw_dump_desc->len); | |
| 556 | ||
| 557 | /* now we can free this copy */ | |
| 558 | iwl_mvm_free_fw_dump_desc(mvm); | |
| 559 | dump_data = iwl_fw_error_next_data(dump_data); | |
| 560 | } | |
| 561 | ||
| 562 | /* In case we only want monitor dump, skip to dump trasport data */ | |
| 563 | if (monitor_dump_only) | |
| 564 | goto dump_trans_data; | |
| 565 | ||
| 566 | dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); | |
| 567 | dump_data->len = cpu_to_le32(sram_len + sizeof(*dump_mem)); | |
| 568 | dump_mem = (void *)dump_data->data; | |
| 569 | dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM); | |
| 570 | dump_mem->offset = cpu_to_le32(sram_ofs); | |
| 571 | iwl_trans_read_mem_bytes(mvm->trans, sram_ofs, dump_mem->data, | |
| 572 | sram_len); | |
| 573 | ||
| 574 | if (smem_len) { | |
| 575 | dump_data = iwl_fw_error_next_data(dump_data); | |
| 576 | dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); | |
| 577 | dump_data->len = cpu_to_le32(smem_len + sizeof(*dump_mem)); | |
| 578 | dump_mem = (void *)dump_data->data; | |
| 579 | dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SMEM); | |
| 580 | dump_mem->offset = cpu_to_le32(mvm->cfg->smem_offset); | |
| 581 | iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->smem_offset, | |
| 582 | dump_mem->data, smem_len); | |
| 583 | } | |
| 584 | ||
| 585 | if (sram2_len) { | |
| 586 | dump_data = iwl_fw_error_next_data(dump_data); | |
| 587 | dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); | |
| 588 | dump_data->len = cpu_to_le32(sram2_len + sizeof(*dump_mem)); | |
| 589 | dump_mem = (void *)dump_data->data; | |
| 590 | dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM); | |
| 591 | dump_mem->offset = cpu_to_le32(mvm->cfg->dccm2_offset); | |
| 592 | iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->dccm2_offset, | |
| 593 | dump_mem->data, sram2_len); | |
| 594 | } | |
| 595 | ||
| 596 | if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000 && | |
| 597 | CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP) { | |
| 598 | dump_data = iwl_fw_error_next_data(dump_data); | |
| 599 | dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); | |
| 600 | dump_data->len = cpu_to_le32(IWL8260_ICCM_LEN + | |
| 601 | sizeof(*dump_mem)); | |
| 602 | dump_mem = (void *)dump_data->data; | |
| 603 | dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM); | |
| 604 | dump_mem->offset = cpu_to_le32(IWL8260_ICCM_OFFSET); | |
| 605 | iwl_trans_read_mem_bytes(mvm->trans, IWL8260_ICCM_OFFSET, | |
| 606 | dump_mem->data, IWL8260_ICCM_LEN); | |
| 607 | } | |
| 608 | ||
| 609 | /* Dump fw's virtual image */ | |
| 610 | if (mvm->fw->img[mvm->cur_ucode].paging_mem_size) { | |
| 611 | u32 i; | |
| 612 | ||
| 613 | for (i = 1; i < mvm->num_of_paging_blk + 1; i++) { | |
| 614 | struct iwl_fw_error_dump_paging *paging; | |
| 615 | struct page *pages = | |
| 616 | mvm->fw_paging_db[i].fw_paging_block; | |
| 617 | ||
| 618 | dump_data = iwl_fw_error_next_data(dump_data); | |
| 619 | dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); | |
| 620 | dump_data->len = cpu_to_le32(sizeof(*paging) + | |
| 621 | PAGING_BLOCK_SIZE); | |
| 622 | paging = (void *)dump_data->data; | |
| 623 | paging->index = cpu_to_le32(i); | |
| 624 | memcpy(paging->data, page_address(pages), | |
| 625 | PAGING_BLOCK_SIZE); | |
| 626 | } | |
| 627 | } | |
| 628 | ||
| 629 | dump_data = iwl_fw_error_next_data(dump_data); | |
| e8f0c4d8 EG |
630 | if (prph_len) |
| 631 | iwl_dump_prph(mvm->trans, &dump_data); | |
| 2f89a5d7 GBA |
632 | |
| 633 | dump_trans_data: | |
| 634 | fw_error_dump->trans_ptr = iwl_trans_dump_data(mvm->trans, | |
| 635 | mvm->fw_dump_trig); | |
| 636 | fw_error_dump->op_mode_len = file_len; | |
| 637 | if (fw_error_dump->trans_ptr) | |
| 638 | file_len += fw_error_dump->trans_ptr->len; | |
| 639 | dump_file->file_len = cpu_to_le32(file_len); | |
| 640 | ||
| 641 | dev_coredumpm(mvm->trans->dev, THIS_MODULE, fw_error_dump, 0, | |
| 642 | GFP_KERNEL, iwl_mvm_read_coredump, iwl_mvm_free_coredump); | |
| 643 | ||
| 644 | mvm->fw_dump_trig = NULL; | |
| 645 | clear_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status); | |
| 646 | } | |
| 647 | ||
| 648 | struct iwl_mvm_dump_desc iwl_mvm_dump_desc_assert = { | |
| 649 | .trig_desc = { | |
| 650 | .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), | |
| 651 | }, | |
| 652 | }; | |
| 653 | ||
| 654 | int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm, | |
| 655 | struct iwl_mvm_dump_desc *desc, | |
| 656 | struct iwl_fw_dbg_trigger_tlv *trigger) | |
| 657 | { | |
| 658 | unsigned int delay = 0; | |
| 659 | ||
| 660 | if (trigger) | |
| 661 | delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay)); | |
| 662 | ||
| 663 | if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status)) | |
| 664 | return -EBUSY; | |
| 665 | ||
| 666 | if (WARN_ON(mvm->fw_dump_desc)) | |
| 667 | iwl_mvm_free_fw_dump_desc(mvm); | |
| 668 | ||
| 669 | IWL_WARN(mvm, "Collecting data: trigger %d fired.\n", | |
| 670 | le32_to_cpu(desc->trig_desc.type)); | |
| 671 | ||
| 672 | mvm->fw_dump_desc = desc; | |
| 673 | mvm->fw_dump_trig = trigger; | |
| 674 | ||
| 675 | queue_delayed_work(system_wq, &mvm->fw_dump_wk, delay); | |
| 676 | ||
| 677 | return 0; | |
| 678 | } | |
| 679 | ||
| 680 | int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig, | |
| 681 | const char *str, size_t len, | |
| 682 | struct iwl_fw_dbg_trigger_tlv *trigger) | |
| 683 | { | |
| 684 | struct iwl_mvm_dump_desc *desc; | |
| 685 | ||
| 686 | desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); | |
| 687 | if (!desc) | |
| 688 | return -ENOMEM; | |
| 689 | ||
| 690 | desc->len = len; | |
| 691 | desc->trig_desc.type = cpu_to_le32(trig); | |
| 692 | memcpy(desc->trig_desc.data, str, len); | |
| 693 | ||
| 694 | return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger); | |
| 695 | } | |
| 696 | ||
| 697 | int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm, | |
| 698 | struct iwl_fw_dbg_trigger_tlv *trigger, | |
| 699 | const char *fmt, ...) | |
| 700 | { | |
| 701 | u16 occurrences = le16_to_cpu(trigger->occurrences); | |
| 702 | int ret, len = 0; | |
| 703 | char buf[64]; | |
| 704 | ||
| 705 | if (!occurrences) | |
| 706 | return 0; | |
| 707 | ||
| 708 | if (fmt) { | |
| 709 | va_list ap; | |
| 710 | ||
| 711 | buf[sizeof(buf) - 1] = '\0'; | |
| 712 | ||
| 713 | va_start(ap, fmt); | |
| 714 | vsnprintf(buf, sizeof(buf), fmt, ap); | |
| 715 | va_end(ap); | |
| 716 | ||
| 717 | /* check for truncation */ | |
| 718 | if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) | |
| 719 | buf[sizeof(buf) - 1] = '\0'; | |
| 720 | ||
| 721 | len = strlen(buf) + 1; | |
| 722 | } | |
| 723 | ||
| 724 | ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len, | |
| 725 | trigger); | |
| 726 | ||
| 727 | if (ret) | |
| 728 | return ret; | |
| 729 | ||
| 730 | trigger->occurrences = cpu_to_le16(occurrences - 1); | |
| 731 | return 0; | |
| 732 | } | |
| 733 | ||
| 734 | static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm) | |
| 735 | { | |
| 736 | if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000) | |
| 737 | iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100); | |
| 738 | else | |
| 739 | iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1); | |
| 740 | } | |
| 741 | ||
| 742 | int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id) | |
| 743 | { | |
| 744 | u8 *ptr; | |
| 745 | int ret; | |
| 746 | int i; | |
| 747 | ||
| 748 | if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv), | |
| 749 | "Invalid configuration %d\n", conf_id)) | |
| 750 | return -EINVAL; | |
| 751 | ||
| 752 | /* EARLY START - firmware's configuration is hard coded */ | |
| 753 | if ((!mvm->fw->dbg_conf_tlv[conf_id] || | |
| 754 | !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) && | |
| 755 | conf_id == FW_DBG_START_FROM_ALIVE) { | |
| 756 | iwl_mvm_restart_early_start(mvm); | |
| 757 | return 0; | |
| 758 | } | |
| 759 | ||
| 760 | if (!mvm->fw->dbg_conf_tlv[conf_id]) | |
| 761 | return -EINVAL; | |
| 762 | ||
| 763 | if (mvm->fw_dbg_conf != FW_DBG_INVALID) | |
| 764 | IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n", | |
| 765 | mvm->fw_dbg_conf); | |
| 766 | ||
| 767 | /* Send all HCMDs for configuring the FW debug */ | |
| 768 | ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd; | |
| 769 | for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) { | |
| 770 | struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; | |
| 771 | ||
| 772 | ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0, | |
| 773 | le16_to_cpu(cmd->len), cmd->data); | |
| 774 | if (ret) | |
| 775 | return ret; | |
| 776 | ||
| 777 | ptr += sizeof(*cmd); | |
| 778 | ptr += le16_to_cpu(cmd->len); | |
| 779 | } | |
| 780 | ||
| 781 | mvm->fw_dbg_conf = conf_id; | |
| 782 | return ret; | |
| 783 | } |