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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
8ca151b5 JB |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
8ca151b5 JB |
27 | * |
28 | * Contact Information: | |
cb2f8277 | 29 | * Intel Linux Wireless <linuxwifi@intel.com> |
8ca151b5 JB |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 35 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
8ca151b5 JB |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
65 | #include <net/mac80211.h> | |
66 | ||
67 | #include "iwl-trans.h" | |
68 | #include "iwl-op-mode.h" | |
69 | #include "iwl-fw.h" | |
70 | #include "iwl-debug.h" | |
71 | #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ | |
72 | #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ | |
8c23f95c | 73 | #include "iwl-prph.h" |
8ca151b5 JB |
74 | #include "iwl-eeprom-parse.h" |
75 | ||
76 | #include "mvm.h" | |
2f89a5d7 | 77 | #include "fw-dbg.h" |
8ca151b5 JB |
78 | #include "iwl-phy-db.h" |
79 | ||
80 | #define MVM_UCODE_ALIVE_TIMEOUT HZ | |
81 | #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) | |
82 | ||
83 | #define UCODE_VALID_OK cpu_to_le32(0x1) | |
84 | ||
8ca151b5 JB |
85 | struct iwl_mvm_alive_data { |
86 | bool valid; | |
87 | u32 scd_base_addr; | |
88 | }; | |
89 | ||
90 | static inline const struct fw_img * | |
91 | iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type) | |
92 | { | |
93 | if (ucode_type >= IWL_UCODE_TYPE_MAX) | |
94 | return NULL; | |
95 | ||
96 | return &mvm->fw->img[ucode_type]; | |
97 | } | |
98 | ||
99 | static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) | |
100 | { | |
101 | struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { | |
102 | .valid = cpu_to_le32(valid_tx_ant), | |
103 | }; | |
104 | ||
33223542 | 105 | IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); |
a1022927 | 106 | return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
107 | sizeof(tx_ant_cmd), &tx_ant_cmd); |
108 | } | |
109 | ||
905e36ae | 110 | void iwl_free_fw_paging(struct iwl_mvm *mvm) |
a6c4fb44 MG |
111 | { |
112 | int i; | |
113 | ||
114 | if (!mvm->fw_paging_db[0].fw_paging_block) | |
115 | return; | |
116 | ||
117 | for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) { | |
118 | if (!mvm->fw_paging_db[i].fw_paging_block) { | |
119 | IWL_DEBUG_FW(mvm, | |
120 | "Paging: block %d already freed, continue to next page\n", | |
121 | i); | |
122 | ||
123 | continue; | |
124 | } | |
125 | ||
126 | __free_pages(mvm->fw_paging_db[i].fw_paging_block, | |
127 | get_order(mvm->fw_paging_db[i].fw_paging_size)); | |
128 | } | |
e1120187 | 129 | kfree(mvm->trans->paging_download_buf); |
905e36ae MG |
130 | mvm->trans->paging_download_buf = NULL; |
131 | ||
a6c4fb44 MG |
132 | memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db)); |
133 | } | |
134 | ||
135 | static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image) | |
136 | { | |
137 | int sec_idx, idx; | |
138 | u32 offset = 0; | |
139 | ||
140 | /* | |
141 | * find where is the paging image start point: | |
142 | * if CPU2 exist and it's in paging format, then the image looks like: | |
143 | * CPU1 sections (2 or more) | |
144 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2 | |
145 | * CPU2 sections (not paged) | |
146 | * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2 | |
147 | * non paged to CPU2 paging sec | |
148 | * CPU2 paging CSS | |
149 | * CPU2 paging image (including instruction and data) | |
150 | */ | |
151 | for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) { | |
152 | if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) { | |
153 | sec_idx++; | |
154 | break; | |
155 | } | |
156 | } | |
157 | ||
158 | if (sec_idx >= IWL_UCODE_SECTION_MAX) { | |
159 | IWL_ERR(mvm, "driver didn't find paging image\n"); | |
160 | iwl_free_fw_paging(mvm); | |
161 | return -EINVAL; | |
162 | } | |
163 | ||
164 | /* copy the CSS block to the dram */ | |
165 | IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n", | |
166 | sec_idx); | |
167 | ||
168 | memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block), | |
169 | image->sec[sec_idx].data, | |
170 | mvm->fw_paging_db[0].fw_paging_size); | |
171 | ||
172 | IWL_DEBUG_FW(mvm, | |
173 | "Paging: copied %d CSS bytes to first block\n", | |
174 | mvm->fw_paging_db[0].fw_paging_size); | |
175 | ||
176 | sec_idx++; | |
177 | ||
178 | /* | |
179 | * copy the paging blocks to the dram | |
180 | * loop index start from 1 since that CSS block already copied to dram | |
181 | * and CSS index is 0. | |
182 | * loop stop at num_of_paging_blk since that last block is not full. | |
183 | */ | |
184 | for (idx = 1; idx < mvm->num_of_paging_blk; idx++) { | |
185 | memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), | |
186 | image->sec[sec_idx].data + offset, | |
187 | mvm->fw_paging_db[idx].fw_paging_size); | |
188 | ||
189 | IWL_DEBUG_FW(mvm, | |
190 | "Paging: copied %d paging bytes to block %d\n", | |
191 | mvm->fw_paging_db[idx].fw_paging_size, | |
192 | idx); | |
193 | ||
194 | offset += mvm->fw_paging_db[idx].fw_paging_size; | |
195 | } | |
196 | ||
197 | /* copy the last paging block */ | |
198 | if (mvm->num_of_pages_in_last_blk > 0) { | |
199 | memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), | |
200 | image->sec[sec_idx].data + offset, | |
201 | FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk); | |
202 | ||
203 | IWL_DEBUG_FW(mvm, | |
204 | "Paging: copied %d pages in the last block %d\n", | |
205 | mvm->num_of_pages_in_last_blk, idx); | |
206 | } | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm, | |
212 | const struct fw_img *image) | |
213 | { | |
214 | struct page *block; | |
215 | dma_addr_t phys = 0; | |
216 | int blk_idx = 0; | |
217 | int order, num_of_pages; | |
218 | int dma_enabled; | |
219 | ||
220 | if (mvm->fw_paging_db[0].fw_paging_block) | |
221 | return 0; | |
222 | ||
223 | dma_enabled = is_device_dma_capable(mvm->trans->dev); | |
224 | ||
225 | /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */ | |
226 | BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE); | |
227 | ||
228 | num_of_pages = image->paging_mem_size / FW_PAGING_SIZE; | |
229 | mvm->num_of_paging_blk = ((num_of_pages - 1) / | |
230 | NUM_OF_PAGE_PER_GROUP) + 1; | |
231 | ||
232 | mvm->num_of_pages_in_last_blk = | |
233 | num_of_pages - | |
234 | NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1); | |
235 | ||
236 | IWL_DEBUG_FW(mvm, | |
237 | "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n", | |
238 | mvm->num_of_paging_blk, | |
239 | mvm->num_of_pages_in_last_blk); | |
240 | ||
241 | /* allocate block of 4Kbytes for paging CSS */ | |
242 | order = get_order(FW_PAGING_SIZE); | |
243 | block = alloc_pages(GFP_KERNEL, order); | |
244 | if (!block) { | |
245 | /* free all the previous pages since we failed */ | |
246 | iwl_free_fw_paging(mvm); | |
247 | return -ENOMEM; | |
248 | } | |
249 | ||
250 | mvm->fw_paging_db[blk_idx].fw_paging_block = block; | |
251 | mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE; | |
252 | ||
253 | if (dma_enabled) { | |
254 | phys = dma_map_page(mvm->trans->dev, block, 0, | |
255 | PAGE_SIZE << order, DMA_BIDIRECTIONAL); | |
256 | if (dma_mapping_error(mvm->trans->dev, phys)) { | |
257 | /* | |
258 | * free the previous pages and the current one since | |
259 | * we failed to map_page. | |
260 | */ | |
261 | iwl_free_fw_paging(mvm); | |
262 | return -ENOMEM; | |
263 | } | |
264 | mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; | |
e1120187 MG |
265 | } else { |
266 | mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG | | |
267 | blk_idx << BLOCK_2_EXP_SIZE; | |
a6c4fb44 MG |
268 | } |
269 | ||
270 | IWL_DEBUG_FW(mvm, | |
271 | "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n", | |
272 | order); | |
273 | ||
274 | /* | |
275 | * allocate blocks in dram. | |
276 | * since that CSS allocated in fw_paging_db[0] loop start from index 1 | |
277 | */ | |
278 | for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { | |
279 | /* allocate block of PAGING_BLOCK_SIZE (32K) */ | |
280 | order = get_order(PAGING_BLOCK_SIZE); | |
281 | block = alloc_pages(GFP_KERNEL, order); | |
282 | if (!block) { | |
283 | /* free all the previous pages since we failed */ | |
284 | iwl_free_fw_paging(mvm); | |
285 | return -ENOMEM; | |
286 | } | |
287 | ||
288 | mvm->fw_paging_db[blk_idx].fw_paging_block = block; | |
289 | mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE; | |
290 | ||
291 | if (dma_enabled) { | |
292 | phys = dma_map_page(mvm->trans->dev, block, 0, | |
293 | PAGE_SIZE << order, | |
294 | DMA_BIDIRECTIONAL); | |
295 | if (dma_mapping_error(mvm->trans->dev, phys)) { | |
296 | /* | |
297 | * free the previous pages and the current one | |
298 | * since we failed to map_page. | |
299 | */ | |
300 | iwl_free_fw_paging(mvm); | |
301 | return -ENOMEM; | |
302 | } | |
303 | mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; | |
e1120187 MG |
304 | } else { |
305 | mvm->fw_paging_db[blk_idx].fw_paging_phys = | |
306 | PAGING_ADDR_SIG | | |
307 | blk_idx << BLOCK_2_EXP_SIZE; | |
a6c4fb44 MG |
308 | } |
309 | ||
310 | IWL_DEBUG_FW(mvm, | |
311 | "Paging: allocated 32K bytes (order %d) for firmware paging.\n", | |
312 | order); | |
313 | } | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static int iwl_save_fw_paging(struct iwl_mvm *mvm, | |
319 | const struct fw_img *fw) | |
320 | { | |
321 | int ret; | |
322 | ||
323 | ret = iwl_alloc_fw_paging_mem(mvm, fw); | |
324 | if (ret) | |
325 | return ret; | |
326 | ||
327 | return iwl_fill_paging_mem(mvm, fw); | |
328 | } | |
329 | ||
330 | /* send paging cmd to FW in case CPU2 has paging image */ | |
331 | static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw) | |
332 | { | |
333 | int blk_idx; | |
334 | __le32 dev_phy_addr; | |
335 | struct iwl_fw_paging_cmd fw_paging_cmd = { | |
336 | .flags = | |
337 | cpu_to_le32(PAGING_CMD_IS_SECURED | | |
338 | PAGING_CMD_IS_ENABLED | | |
339 | (mvm->num_of_pages_in_last_blk << | |
340 | PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)), | |
341 | .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE), | |
342 | .block_num = cpu_to_le32(mvm->num_of_paging_blk), | |
343 | }; | |
344 | ||
345 | /* loop for for all paging blocks + CSS block */ | |
346 | for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { | |
347 | dev_phy_addr = | |
348 | cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >> | |
349 | PAGE_2_EXP_SIZE); | |
350 | fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr; | |
351 | } | |
352 | ||
353 | return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD, | |
354 | IWL_ALWAYS_LONG_GROUP, 0), | |
355 | 0, sizeof(fw_paging_cmd), &fw_paging_cmd); | |
356 | } | |
357 | ||
e1120187 MG |
358 | /* |
359 | * Send paging item cmd to FW in case CPU2 has paging image | |
360 | */ | |
361 | static int iwl_trans_get_paging_item(struct iwl_mvm *mvm) | |
362 | { | |
363 | int ret; | |
364 | struct iwl_fw_get_item_cmd fw_get_item_cmd = { | |
365 | .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING), | |
366 | }; | |
367 | ||
368 | struct iwl_fw_get_item_resp *item_resp; | |
369 | struct iwl_host_cmd cmd = { | |
370 | .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0), | |
371 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, | |
372 | .data = { &fw_get_item_cmd, }, | |
373 | }; | |
374 | ||
375 | cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd); | |
376 | ||
377 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
378 | if (ret) { | |
379 | IWL_ERR(mvm, | |
380 | "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n", | |
381 | ret); | |
382 | return ret; | |
383 | } | |
384 | ||
385 | item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data; | |
386 | if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) { | |
387 | IWL_ERR(mvm, | |
388 | "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n", | |
389 | le32_to_cpu(item_resp->item_id)); | |
390 | ret = -EIO; | |
391 | goto exit; | |
392 | } | |
393 | ||
394 | mvm->trans->paging_download_buf = kzalloc(MAX_PAGING_IMAGE_SIZE, | |
395 | GFP_KERNEL); | |
396 | if (!mvm->trans->paging_download_buf) { | |
397 | ret = -ENOMEM; | |
398 | goto exit; | |
399 | } | |
400 | mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val); | |
401 | mvm->trans->paging_db = mvm->fw_paging_db; | |
402 | IWL_DEBUG_FW(mvm, | |
403 | "Paging: got paging request address (paging_req_addr 0x%08x)\n", | |
404 | mvm->trans->paging_req_addr); | |
405 | ||
406 | exit: | |
407 | iwl_free_resp(&cmd); | |
408 | ||
409 | return ret; | |
410 | } | |
411 | ||
8ca151b5 JB |
412 | static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
413 | struct iwl_rx_packet *pkt, void *data) | |
414 | { | |
415 | struct iwl_mvm *mvm = | |
416 | container_of(notif_wait, struct iwl_mvm, notif_wait); | |
417 | struct iwl_mvm_alive_data *alive_data = data; | |
7e1223b5 | 418 | struct mvm_alive_resp_ver1 *palive1; |
01a9ca51 | 419 | struct mvm_alive_resp_ver2 *palive2; |
7e1223b5 | 420 | struct mvm_alive_resp *palive; |
01a9ca51 | 421 | |
7e1223b5 EG |
422 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) { |
423 | palive1 = (void *)pkt->data; | |
01a9ca51 EH |
424 | |
425 | mvm->support_umac_log = false; | |
426 | mvm->error_event_table = | |
7e1223b5 EG |
427 | le32_to_cpu(palive1->error_event_table_ptr); |
428 | mvm->log_event_table = | |
429 | le32_to_cpu(palive1->log_event_table_ptr); | |
430 | alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr); | |
01a9ca51 | 431 | |
7e1223b5 | 432 | alive_data->valid = le16_to_cpu(palive1->status) == |
01a9ca51 EH |
433 | IWL_ALIVE_STATUS_OK; |
434 | IWL_DEBUG_FW(mvm, | |
435 | "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
7e1223b5 EG |
436 | le16_to_cpu(palive1->status), palive1->ver_type, |
437 | palive1->ver_subtype, palive1->flags); | |
438 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) { | |
01a9ca51 EH |
439 | palive2 = (void *)pkt->data; |
440 | ||
01a9ca51 EH |
441 | mvm->error_event_table = |
442 | le32_to_cpu(palive2->error_event_table_ptr); | |
443 | mvm->log_event_table = | |
444 | le32_to_cpu(palive2->log_event_table_ptr); | |
445 | alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr); | |
446 | mvm->umac_error_event_table = | |
447 | le32_to_cpu(palive2->error_info_addr); | |
91479b64 EH |
448 | mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr); |
449 | mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size); | |
01a9ca51 EH |
450 | |
451 | alive_data->valid = le16_to_cpu(palive2->status) == | |
452 | IWL_ALIVE_STATUS_OK; | |
ffa70264 EG |
453 | if (mvm->umac_error_event_table) |
454 | mvm->support_umac_log = true; | |
455 | ||
01a9ca51 EH |
456 | IWL_DEBUG_FW(mvm, |
457 | "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
458 | le16_to_cpu(palive2->status), palive2->ver_type, | |
459 | palive2->ver_subtype, palive2->flags); | |
460 | ||
461 | IWL_DEBUG_FW(mvm, | |
462 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
463 | palive2->umac_major, palive2->umac_minor); | |
7e1223b5 EG |
464 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { |
465 | palive = (void *)pkt->data; | |
466 | ||
467 | mvm->error_event_table = | |
468 | le32_to_cpu(palive->error_event_table_ptr); | |
469 | mvm->log_event_table = | |
470 | le32_to_cpu(palive->log_event_table_ptr); | |
471 | alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr); | |
472 | mvm->umac_error_event_table = | |
473 | le32_to_cpu(palive->error_info_addr); | |
474 | mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr); | |
475 | mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size); | |
476 | ||
477 | alive_data->valid = le16_to_cpu(palive->status) == | |
478 | IWL_ALIVE_STATUS_OK; | |
479 | if (mvm->umac_error_event_table) | |
480 | mvm->support_umac_log = true; | |
481 | ||
482 | IWL_DEBUG_FW(mvm, | |
483 | "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
484 | le16_to_cpu(palive->status), palive->ver_type, | |
485 | palive->ver_subtype, palive->flags); | |
486 | ||
487 | IWL_DEBUG_FW(mvm, | |
488 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
489 | le32_to_cpu(palive->umac_major), | |
490 | le32_to_cpu(palive->umac_minor)); | |
01a9ca51 | 491 | } |
8ca151b5 JB |
492 | |
493 | return true; | |
494 | } | |
495 | ||
496 | static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, | |
497 | struct iwl_rx_packet *pkt, void *data) | |
498 | { | |
499 | struct iwl_phy_db *phy_db = data; | |
500 | ||
501 | if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { | |
502 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
503 | return true; | |
504 | } | |
505 | ||
506 | WARN_ON(iwl_phy_db_set_section(phy_db, pkt, GFP_ATOMIC)); | |
507 | ||
508 | return false; | |
509 | } | |
510 | ||
511 | static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, | |
512 | enum iwl_ucode_type ucode_type) | |
513 | { | |
514 | struct iwl_notification_wait alive_wait; | |
515 | struct iwl_mvm_alive_data alive_data; | |
516 | const struct fw_img *fw; | |
517 | int ret, i; | |
518 | enum iwl_ucode_type old_type = mvm->cur_ucode; | |
6eb031d2 | 519 | static const u16 alive_cmd[] = { MVM_ALIVE }; |
91479b64 | 520 | struct iwl_sf_region st_fwrd_space; |
8ca151b5 | 521 | |
61df750c | 522 | if (ucode_type == IWL_UCODE_REGULAR && |
d2709ad7 | 523 | iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE)) |
61df750c EH |
524 | fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER); |
525 | else | |
526 | fw = iwl_get_ucode_image(mvm, ucode_type); | |
befe9b6f | 527 | if (WARN_ON(!fw)) |
8ca151b5 | 528 | return -EINVAL; |
befe9b6f JB |
529 | mvm->cur_ucode = ucode_type; |
530 | mvm->ucode_loaded = false; | |
8ca151b5 JB |
531 | |
532 | iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, | |
533 | alive_cmd, ARRAY_SIZE(alive_cmd), | |
534 | iwl_alive_fn, &alive_data); | |
535 | ||
536 | ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT); | |
537 | if (ret) { | |
538 | mvm->cur_ucode = old_type; | |
539 | iwl_remove_notification(&mvm->notif_wait, &alive_wait); | |
540 | return ret; | |
541 | } | |
542 | ||
543 | /* | |
544 | * Some things may run in the background now, but we | |
545 | * just wait for the ALIVE notification here. | |
546 | */ | |
547 | ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, | |
548 | MVM_UCODE_ALIVE_TIMEOUT); | |
549 | if (ret) { | |
192de2b4 DS |
550 | if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
551 | IWL_ERR(mvm, | |
552 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
553 | iwl_read_prph(mvm->trans, SB_CPU_1_STATUS), | |
554 | iwl_read_prph(mvm->trans, SB_CPU_2_STATUS)); | |
8ca151b5 JB |
555 | mvm->cur_ucode = old_type; |
556 | return ret; | |
557 | } | |
558 | ||
559 | if (!alive_data.valid) { | |
560 | IWL_ERR(mvm, "Loaded ucode is not valid!\n"); | |
561 | mvm->cur_ucode = old_type; | |
562 | return -EIO; | |
563 | } | |
564 | ||
91479b64 EH |
565 | /* |
566 | * update the sdio allocation according to the pointer we get in the | |
567 | * alive notification. | |
568 | */ | |
569 | st_fwrd_space.addr = mvm->sf_space.addr; | |
570 | st_fwrd_space.size = mvm->sf_space.size; | |
571 | ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space); | |
82e8aea0 ES |
572 | if (ret) { |
573 | IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret); | |
574 | return ret; | |
575 | } | |
91479b64 | 576 | |
8ca151b5 JB |
577 | iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); |
578 | ||
a6c4fb44 MG |
579 | /* |
580 | * configure and operate fw paging mechanism. | |
581 | * driver configures the paging flow only once, CPU2 paging image | |
582 | * included in the IWL_UCODE_INIT image. | |
583 | */ | |
584 | if (fw->paging_mem_size) { | |
e1120187 MG |
585 | /* |
586 | * When dma is not enabled, the driver needs to copy / write | |
587 | * the downloaded / uploaded page to / from the smem. | |
588 | * This gets the location of the place were the pages are | |
589 | * stored. | |
590 | */ | |
591 | if (!is_device_dma_capable(mvm->trans->dev)) { | |
592 | ret = iwl_trans_get_paging_item(mvm); | |
593 | if (ret) { | |
594 | IWL_ERR(mvm, "failed to get FW paging item\n"); | |
595 | return ret; | |
596 | } | |
597 | } | |
598 | ||
a6c4fb44 MG |
599 | ret = iwl_save_fw_paging(mvm, fw); |
600 | if (ret) { | |
601 | IWL_ERR(mvm, "failed to save the FW paging image\n"); | |
602 | return ret; | |
603 | } | |
604 | ||
605 | ret = iwl_send_paging_cmd(mvm, fw); | |
606 | if (ret) { | |
607 | IWL_ERR(mvm, "failed to send the paging cmd\n"); | |
608 | iwl_free_fw_paging(mvm); | |
609 | return ret; | |
610 | } | |
611 | } | |
612 | ||
8ca151b5 JB |
613 | /* |
614 | * Note: all the queues are enabled as part of the interface | |
615 | * initialization, but in firmware restart scenarios they | |
616 | * could be stopped, so wake them up. In firmware restart, | |
617 | * mac80211 will have the queues stopped as well until the | |
618 | * reconfiguration completes. During normal startup, they | |
619 | * will be empty. | |
620 | */ | |
621 | ||
4ecafae9 LK |
622 | memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); |
623 | mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1; | |
8ca151b5 | 624 | |
df197c00 JB |
625 | for (i = 0; i < IEEE80211_MAX_QUEUES; i++) |
626 | atomic_set(&mvm->mac80211_queue_stop_count[i], 0); | |
8ca151b5 JB |
627 | |
628 | mvm->ucode_loaded = true; | |
629 | ||
630 | return 0; | |
631 | } | |
8ca151b5 JB |
632 | |
633 | static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) | |
634 | { | |
635 | struct iwl_phy_cfg_cmd phy_cfg_cmd; | |
636 | enum iwl_ucode_type ucode_type = mvm->cur_ucode; | |
637 | ||
638 | /* Set parameters */ | |
a0544272 | 639 | phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); |
8ca151b5 JB |
640 | phy_cfg_cmd.calib_control.event_trigger = |
641 | mvm->fw->default_calib[ucode_type].event_trigger; | |
642 | phy_cfg_cmd.calib_control.flow_trigger = | |
643 | mvm->fw->default_calib[ucode_type].flow_trigger; | |
644 | ||
645 | IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", | |
646 | phy_cfg_cmd.phy_cfg); | |
647 | ||
a1022927 | 648 | return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
649 | sizeof(phy_cfg_cmd), &phy_cfg_cmd); |
650 | } | |
651 | ||
8ca151b5 JB |
652 | int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) |
653 | { | |
654 | struct iwl_notification_wait calib_wait; | |
6eb031d2 | 655 | static const u16 init_complete[] = { |
8ca151b5 JB |
656 | INIT_COMPLETE_NOTIF, |
657 | CALIB_RES_NOTIF_PHY_DB | |
658 | }; | |
659 | int ret; | |
660 | ||
661 | lockdep_assert_held(&mvm->mutex); | |
662 | ||
8d193ca2 | 663 | if (WARN_ON_ONCE(mvm->calibrating)) |
8ca151b5 JB |
664 | return 0; |
665 | ||
666 | iwl_init_notification_wait(&mvm->notif_wait, | |
667 | &calib_wait, | |
668 | init_complete, | |
669 | ARRAY_SIZE(init_complete), | |
670 | iwl_wait_phy_db_entry, | |
671 | mvm->phy_db); | |
672 | ||
673 | /* Will also start the device */ | |
674 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); | |
675 | if (ret) { | |
676 | IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); | |
677 | goto error; | |
678 | } | |
679 | ||
ae397472 | 680 | ret = iwl_send_bt_init_conf(mvm); |
931d4160 EG |
681 | if (ret) |
682 | goto error; | |
683 | ||
81a67e32 | 684 | /* Read the NVM only at driver load time, no need to do this twice */ |
8ca151b5 JB |
685 | if (read_nvm) { |
686 | /* Read nvm */ | |
14b485f0 | 687 | ret = iwl_nvm_init(mvm, true); |
8ca151b5 JB |
688 | if (ret) { |
689 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
690 | goto error; | |
691 | } | |
692 | } | |
693 | ||
81a67e32 | 694 | /* In case we read the NVM from external file, load it to the NIC */ |
e02a9d60 | 695 | if (mvm->nvm_file_name) |
81a67e32 EL |
696 | iwl_mvm_load_nvm_to_nic(mvm); |
697 | ||
8ca151b5 JB |
698 | ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans); |
699 | WARN_ON(ret); | |
700 | ||
4f59334b EH |
701 | /* |
702 | * abort after reading the nvm in case RF Kill is on, we will complete | |
703 | * the init seq later when RF kill will switch to off | |
704 | */ | |
1a3fe0b2 | 705 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
4f59334b EH |
706 | IWL_DEBUG_RF_KILL(mvm, |
707 | "jump over all phy activities due to RF kill\n"); | |
708 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); | |
a4082843 AN |
709 | ret = 1; |
710 | goto out; | |
4f59334b EH |
711 | } |
712 | ||
31b8b343 EG |
713 | mvm->calibrating = true; |
714 | ||
e07cbb53 | 715 | /* Send TX valid antennas before triggering calibrations */ |
a0544272 | 716 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
e07cbb53 DS |
717 | if (ret) |
718 | goto error; | |
719 | ||
8ca151b5 JB |
720 | /* |
721 | * Send phy configurations command to init uCode | |
722 | * to start the 16.0 uCode init image internal calibrations. | |
723 | */ | |
724 | ret = iwl_send_phy_cfg_cmd(mvm); | |
725 | if (ret) { | |
726 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
727 | ret); | |
728 | goto error; | |
729 | } | |
730 | ||
731 | /* | |
732 | * Some things may run in the background now, but we | |
733 | * just wait for the calibration complete notification. | |
734 | */ | |
735 | ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, | |
736 | MVM_UCODE_CALIB_TIMEOUT); | |
31b8b343 | 737 | |
1a3fe0b2 | 738 | if (ret && iwl_mvm_is_radio_hw_killed(mvm)) { |
31b8b343 EG |
739 | IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); |
740 | ret = 1; | |
741 | } | |
8ca151b5 JB |
742 | goto out; |
743 | ||
744 | error: | |
745 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); | |
746 | out: | |
31b8b343 | 747 | mvm->calibrating = false; |
a4082843 | 748 | if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { |
8ca151b5 JB |
749 | /* we want to debug INIT and we have no NVM - fake */ |
750 | mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + | |
751 | sizeof(struct ieee80211_channel) + | |
752 | sizeof(struct ieee80211_rate), | |
753 | GFP_KERNEL); | |
754 | if (!mvm->nvm_data) | |
755 | return -ENOMEM; | |
8ca151b5 JB |
756 | mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; |
757 | mvm->nvm_data->bands[0].n_channels = 1; | |
758 | mvm->nvm_data->bands[0].n_bitrates = 1; | |
759 | mvm->nvm_data->bands[0].bitrates = | |
760 | (void *)mvm->nvm_data->channels + 1; | |
761 | mvm->nvm_data->bands[0].bitrates->hw_value = 10; | |
762 | } | |
763 | ||
764 | return ret; | |
765 | } | |
766 | ||
04fd2c28 LK |
767 | static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm) |
768 | { | |
769 | struct iwl_host_cmd cmd = { | |
770 | .id = SHARED_MEM_CFG, | |
771 | .flags = CMD_WANT_SKB, | |
772 | .data = { NULL, }, | |
773 | .len = { 0, }, | |
774 | }; | |
775 | struct iwl_rx_packet *pkt; | |
776 | struct iwl_shared_mem_cfg *mem_cfg; | |
777 | u32 i; | |
778 | ||
779 | lockdep_assert_held(&mvm->mutex); | |
780 | ||
781 | if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd))) | |
782 | return; | |
783 | ||
784 | pkt = cmd.resp_pkt; | |
04fd2c28 LK |
785 | mem_cfg = (void *)pkt->data; |
786 | ||
787 | mvm->shared_mem_cfg.shared_mem_addr = | |
788 | le32_to_cpu(mem_cfg->shared_mem_addr); | |
789 | mvm->shared_mem_cfg.shared_mem_size = | |
790 | le32_to_cpu(mem_cfg->shared_mem_size); | |
791 | mvm->shared_mem_cfg.sample_buff_addr = | |
792 | le32_to_cpu(mem_cfg->sample_buff_addr); | |
793 | mvm->shared_mem_cfg.sample_buff_size = | |
794 | le32_to_cpu(mem_cfg->sample_buff_size); | |
795 | mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr); | |
796 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) | |
797 | mvm->shared_mem_cfg.txfifo_size[i] = | |
798 | le32_to_cpu(mem_cfg->txfifo_size[i]); | |
799 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) | |
800 | mvm->shared_mem_cfg.rxfifo_size[i] = | |
801 | le32_to_cpu(mem_cfg->rxfifo_size[i]); | |
802 | mvm->shared_mem_cfg.page_buff_addr = | |
803 | le32_to_cpu(mem_cfg->page_buff_addr); | |
804 | mvm->shared_mem_cfg.page_buff_size = | |
805 | le32_to_cpu(mem_cfg->page_buff_size); | |
806 | IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n"); | |
807 | ||
04fd2c28 LK |
808 | iwl_free_resp(&cmd); |
809 | } | |
810 | ||
84bfffa9 EG |
811 | static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) |
812 | { | |
813 | struct iwl_ltr_config_cmd cmd = { | |
814 | .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), | |
815 | }; | |
816 | ||
817 | if (!mvm->trans->ltr_enabled) | |
818 | return 0; | |
819 | ||
84bfffa9 EG |
820 | return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, |
821 | sizeof(cmd), &cmd); | |
822 | } | |
823 | ||
8ca151b5 JB |
824 | int iwl_mvm_up(struct iwl_mvm *mvm) |
825 | { | |
826 | int ret, i; | |
53a9d61e IP |
827 | struct ieee80211_channel *chan; |
828 | struct cfg80211_chan_def chandef; | |
8ca151b5 JB |
829 | |
830 | lockdep_assert_held(&mvm->mutex); | |
831 | ||
832 | ret = iwl_trans_start_hw(mvm->trans); | |
833 | if (ret) | |
834 | return ret; | |
835 | ||
ff116373 EL |
836 | /* |
837 | * If we haven't completed the run of the init ucode during | |
838 | * module loading, load init ucode now | |
839 | * (for example, if we were in RFKILL) | |
840 | */ | |
8d193ca2 EH |
841 | ret = iwl_run_init_mvm_ucode(mvm, false); |
842 | if (ret && !iwlmvm_mod_params.init_dbg) { | |
843 | IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); | |
844 | /* this can't happen */ | |
845 | if (WARN_ON(ret > 0)) | |
846 | ret = -ERFKILL; | |
847 | goto error; | |
848 | } | |
849 | if (!iwlmvm_mod_params.init_dbg) { | |
850 | /* | |
851 | * Stop and start the transport without entering low power | |
852 | * mode. This will save the state of other components on the | |
853 | * device that are triggered by the INIT firwmare (MFUART). | |
854 | */ | |
855 | _iwl_trans_stop_device(mvm->trans, false); | |
d643c432 | 856 | ret = _iwl_trans_start_hw(mvm->trans, false); |
8d193ca2 | 857 | if (ret) |
d643c432 | 858 | goto error; |
8ca151b5 JB |
859 | } |
860 | ||
861 | if (iwlmvm_mod_params.init_dbg) | |
862 | return 0; | |
863 | ||
864 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); | |
865 | if (ret) { | |
866 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
867 | goto error; | |
868 | } | |
869 | ||
6c7d32cf | 870 | iwl_mvm_get_shared_mem_conf(mvm); |
04fd2c28 | 871 | |
1f3b0ff8 LE |
872 | ret = iwl_mvm_sf_update(mvm, NULL, false); |
873 | if (ret) | |
874 | IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); | |
875 | ||
6a951267 | 876 | mvm->fw_dbg_conf = FW_DBG_INVALID; |
945d4202 EG |
877 | /* if we have a destination, assume EARLY START */ |
878 | if (mvm->fw->dbg_dest_tlv) | |
879 | mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE; | |
d2709ad7 | 880 | iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE); |
6a951267 | 881 | |
a0544272 | 882 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
883 | if (ret) |
884 | goto error; | |
885 | ||
931d4160 EG |
886 | ret = iwl_send_bt_init_conf(mvm); |
887 | if (ret) | |
888 | goto error; | |
889 | ||
8ca151b5 JB |
890 | /* Send phy db control command and then phy db calibration*/ |
891 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
892 | if (ret) | |
893 | goto error; | |
894 | ||
895 | ret = iwl_send_phy_cfg_cmd(mvm); | |
896 | if (ret) | |
897 | goto error; | |
898 | ||
899 | /* init the fw <-> mac80211 STA mapping */ | |
900 | for (i = 0; i < IWL_MVM_STATION_COUNT; i++) | |
901 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); | |
902 | ||
1d3c3f63 AN |
903 | mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT; |
904 | ||
b2b7875b JB |
905 | /* reset quota debouncing buffer - 0xff will yield invalid data */ |
906 | memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); | |
907 | ||
8ca151b5 JB |
908 | /* Add auxiliary station for scanning */ |
909 | ret = iwl_mvm_add_aux_sta(mvm); | |
910 | if (ret) | |
911 | goto error; | |
912 | ||
53a9d61e IP |
913 | /* Add all the PHY contexts */ |
914 | chan = &mvm->hw->wiphy->bands[IEEE80211_BAND_2GHZ]->channels[0]; | |
915 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); | |
916 | for (i = 0; i < NUM_PHY_CTX; i++) { | |
917 | /* | |
918 | * The channel used here isn't relevant as it's | |
919 | * going to be overwritten in the other flows. | |
920 | * For now use the first channel we have. | |
921 | */ | |
922 | ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], | |
923 | &chandef, 1, 1); | |
924 | if (ret) | |
925 | goto error; | |
926 | } | |
8ca151b5 | 927 | |
0c0e2c71 IY |
928 | /* Initialize tx backoffs to the minimal possible */ |
929 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
930 | ||
84bfffa9 | 931 | WARN_ON(iwl_mvm_config_ltr(mvm)); |
9180ac50 | 932 | |
c1cb92fc | 933 | ret = iwl_mvm_power_update_device(mvm); |
64b928c4 AB |
934 | if (ret) |
935 | goto error; | |
936 | ||
35af15d1 AN |
937 | /* |
938 | * RTNL is not taken during Ct-kill, but we don't need to scan/Tx | |
939 | * anyway, so don't init MCC. | |
940 | */ | |
941 | if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { | |
942 | ret = iwl_mvm_init_mcc(mvm); | |
943 | if (ret) | |
944 | goto error; | |
945 | } | |
90d4f7db | 946 | |
859d914c | 947 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { |
4ca87a5f | 948 | mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; |
d2496221 DS |
949 | ret = iwl_mvm_config_scan(mvm); |
950 | if (ret) | |
951 | goto error; | |
952 | } | |
953 | ||
93190fb0 AA |
954 | if (iwl_mvm_is_csum_supported(mvm) && |
955 | mvm->cfg->features & NETIF_F_RXCSUM) | |
956 | iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3); | |
957 | ||
7498cf4c EP |
958 | /* allow FW/transport low power modes if not during restart */ |
959 | if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) | |
960 | iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN); | |
961 | ||
53a9d61e | 962 | IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); |
8ca151b5 JB |
963 | return 0; |
964 | error: | |
965 | iwl_trans_stop_device(mvm->trans); | |
966 | return ret; | |
967 | } | |
968 | ||
969 | int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) | |
970 | { | |
971 | int ret, i; | |
972 | ||
973 | lockdep_assert_held(&mvm->mutex); | |
974 | ||
975 | ret = iwl_trans_start_hw(mvm->trans); | |
976 | if (ret) | |
977 | return ret; | |
978 | ||
979 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); | |
980 | if (ret) { | |
981 | IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); | |
982 | goto error; | |
983 | } | |
984 | ||
a0544272 | 985 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
986 | if (ret) |
987 | goto error; | |
988 | ||
989 | /* Send phy db control command and then phy db calibration*/ | |
990 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
991 | if (ret) | |
992 | goto error; | |
993 | ||
994 | ret = iwl_send_phy_cfg_cmd(mvm); | |
995 | if (ret) | |
996 | goto error; | |
997 | ||
998 | /* init the fw <-> mac80211 STA mapping */ | |
999 | for (i = 0; i < IWL_MVM_STATION_COUNT; i++) | |
1000 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); | |
1001 | ||
1002 | /* Add auxiliary station for scanning */ | |
1003 | ret = iwl_mvm_add_aux_sta(mvm); | |
1004 | if (ret) | |
1005 | goto error; | |
1006 | ||
1007 | return 0; | |
1008 | error: | |
1009 | iwl_trans_stop_device(mvm->trans); | |
1010 | return ret; | |
1011 | } | |
1012 | ||
0416841d JB |
1013 | void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, |
1014 | struct iwl_rx_cmd_buffer *rxb) | |
8ca151b5 JB |
1015 | { |
1016 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1017 | struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; | |
1018 | u32 flags = le32_to_cpu(card_state_notif->flags); | |
1019 | ||
1020 | IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", | |
1021 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
1022 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
1023 | (flags & CT_KILL_CARD_DISABLED) ? | |
1024 | "Reached" : "Not reached"); | |
8ca151b5 JB |
1025 | } |
1026 | ||
0416841d JB |
1027 | void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, |
1028 | struct iwl_rx_cmd_buffer *rxb) | |
30269c12 CRI |
1029 | { |
1030 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1031 | struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; | |
1032 | ||
1033 | IWL_DEBUG_INFO(mvm, | |
1034 | "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", | |
1035 | le32_to_cpu(mfuart_notif->installed_ver), | |
1036 | le32_to_cpu(mfuart_notif->external_ver), | |
1037 | le32_to_cpu(mfuart_notif->status), | |
1038 | le32_to_cpu(mfuart_notif->duration)); | |
30269c12 | 1039 | } |