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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
4fb06283 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
d4a7e708 | 10 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
8ca151b5 JB |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of version 2 of the GNU General Public License as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
24 | * USA | |
25 | * | |
26 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 27 | * in the file called COPYING. |
8ca151b5 JB |
28 | * |
29 | * Contact Information: | |
cb2f8277 | 30 | * Intel Linux Wireless <linuxwifi@intel.com> |
8ca151b5 JB |
31 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
32 | * | |
33 | * BSD LICENSE | |
34 | * | |
51368bf7 | 35 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
4fb06283 | 36 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
d4a7e708 | 37 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
8ca151b5 JB |
38 | * All rights reserved. |
39 | * | |
40 | * Redistribution and use in source and binary forms, with or without | |
41 | * modification, are permitted provided that the following conditions | |
42 | * are met: | |
43 | * | |
44 | * * Redistributions of source code must retain the above copyright | |
45 | * notice, this list of conditions and the following disclaimer. | |
46 | * * Redistributions in binary form must reproduce the above copyright | |
47 | * notice, this list of conditions and the following disclaimer in | |
48 | * the documentation and/or other materials provided with the | |
49 | * distribution. | |
50 | * * Neither the name Intel Corporation nor the names of its | |
51 | * contributors may be used to endorse or promote products derived | |
52 | * from this software without specific prior written permission. | |
53 | * | |
54 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
55 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
56 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
57 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
58 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
59 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
60 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
61 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
62 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
63 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
64 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
65 | * | |
66 | *****************************************************************************/ | |
1214755c | 67 | #include <linux/firmware.h> |
90d4f7db | 68 | #include <linux/rtnetlink.h> |
8ca151b5 | 69 | #include "iwl-trans.h" |
c2a2b28b | 70 | #include "iwl-csr.h" |
8ca151b5 JB |
71 | #include "mvm.h" |
72 | #include "iwl-eeprom-parse.h" | |
73 | #include "iwl-eeprom-read.h" | |
74 | #include "iwl-nvm-parse.h" | |
8ba2d7a1 | 75 | #include "iwl-prph.h" |
45f65569 | 76 | #include "fw/acpi.h" |
8ca151b5 | 77 | |
1fd4afe2 | 78 | /* Default NVM size to read */ |
1214755c | 79 | #define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024) |
f251c07c | 80 | #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 |
7042678d | 81 | #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc |
1fd4afe2 | 82 | |
1214755c EH |
83 | #define NVM_WRITE_OPCODE 1 |
84 | #define NVM_READ_OPCODE 0 | |
85 | ||
d6aeb354 EH |
86 | /* load nvm chunk response */ |
87 | enum { | |
88 | READ_NVM_CHUNK_SUCCEED = 0, | |
89 | READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 | |
90 | }; | |
91 | ||
1214755c EH |
92 | /* |
93 | * prepare the NVM host command w/ the pointers to the nvm buffer | |
94 | * and send it to fw | |
95 | */ | |
96 | static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section, | |
97 | u16 offset, u16 length, const u8 *data) | |
8ca151b5 | 98 | { |
1214755c EH |
99 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
100 | .offset = cpu_to_le16(offset), | |
101 | .length = cpu_to_le16(length), | |
102 | .type = cpu_to_le16(section), | |
103 | .op_code = NVM_WRITE_OPCODE, | |
104 | }; | |
105 | struct iwl_host_cmd cmd = { | |
106 | .id = NVM_ACCESS_CMD, | |
107 | .len = { sizeof(struct iwl_nvm_access_cmd), length }, | |
9a57f650 | 108 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
1214755c EH |
109 | .data = { &nvm_access_cmd, data }, |
110 | /* data may come from vmalloc, so use _DUP */ | |
111 | .dataflags = { 0, IWL_HCMD_DFL_DUP }, | |
112 | }; | |
9a57f650 MG |
113 | struct iwl_rx_packet *pkt; |
114 | struct iwl_nvm_access_resp *nvm_resp; | |
115 | int ret; | |
1214755c | 116 | |
9a57f650 MG |
117 | ret = iwl_mvm_send_cmd(mvm, &cmd); |
118 | if (ret) | |
119 | return ret; | |
120 | ||
121 | pkt = cmd.resp_pkt; | |
9a57f650 MG |
122 | /* Extract & check NVM write response */ |
123 | nvm_resp = (void *)pkt->data; | |
124 | if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) { | |
125 | IWL_ERR(mvm, | |
126 | "NVM access write command failed for section %u (status = 0x%x)\n", | |
127 | section, le16_to_cpu(nvm_resp->status)); | |
128 | ret = -EIO; | |
129 | } | |
130 | ||
131 | iwl_free_resp(&cmd); | |
132 | return ret; | |
8ca151b5 JB |
133 | } |
134 | ||
135 | static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section, | |
136 | u16 offset, u16 length, u8 *data) | |
137 | { | |
1214755c EH |
138 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
139 | .offset = cpu_to_le16(offset), | |
140 | .length = cpu_to_le16(length), | |
141 | .type = cpu_to_le16(section), | |
142 | .op_code = NVM_READ_OPCODE, | |
143 | }; | |
b9545b48 | 144 | struct iwl_nvm_access_resp *nvm_resp; |
8ca151b5 JB |
145 | struct iwl_rx_packet *pkt; |
146 | struct iwl_host_cmd cmd = { | |
147 | .id = NVM_ACCESS_CMD, | |
a1022927 | 148 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
8ca151b5 JB |
149 | .data = { &nvm_access_cmd, }, |
150 | }; | |
151 | int ret, bytes_read, offset_read; | |
152 | u8 *resp_data; | |
153 | ||
b9545b48 | 154 | cmd.len[0] = sizeof(struct iwl_nvm_access_cmd); |
8ca151b5 JB |
155 | |
156 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
157 | if (ret) | |
158 | return ret; | |
159 | ||
160 | pkt = cmd.resp_pkt; | |
8ca151b5 JB |
161 | |
162 | /* Extract NVM response */ | |
163 | nvm_resp = (void *)pkt->data; | |
b9545b48 EG |
164 | ret = le16_to_cpu(nvm_resp->status); |
165 | bytes_read = le16_to_cpu(nvm_resp->length); | |
166 | offset_read = le16_to_cpu(nvm_resp->offset); | |
167 | resp_data = nvm_resp->data; | |
8ca151b5 | 168 | if (ret) { |
d6aeb354 EH |
169 | if ((offset != 0) && |
170 | (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { | |
171 | /* | |
172 | * meaning of NOT_VALID_ADDRESS: | |
173 | * driver try to read chunk from address that is | |
174 | * multiple of 2K and got an error since addr is empty. | |
175 | * meaning of (offset != 0): driver already | |
176 | * read valid data from another chunk so this case | |
177 | * is not an error. | |
178 | */ | |
179 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
180 | "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", | |
181 | offset); | |
182 | ret = 0; | |
183 | } else { | |
184 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
185 | "NVM access command failed with status %d (device: %s)\n", | |
186 | ret, mvm->cfg->name); | |
187 | ret = -EIO; | |
188 | } | |
8ca151b5 JB |
189 | goto exit; |
190 | } | |
191 | ||
192 | if (offset_read != offset) { | |
193 | IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n", | |
194 | offset_read); | |
195 | ret = -EINVAL; | |
196 | goto exit; | |
197 | } | |
198 | ||
199 | /* Write data to NVM */ | |
200 | memcpy(data + offset, resp_data, bytes_read); | |
201 | ret = bytes_read; | |
202 | ||
203 | exit: | |
204 | iwl_free_resp(&cmd); | |
205 | return ret; | |
206 | } | |
207 | ||
1214755c EH |
208 | static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section, |
209 | const u8 *data, u16 length) | |
210 | { | |
211 | int offset = 0; | |
212 | ||
213 | /* copy data in chunks of 2k (and remainder if any) */ | |
214 | ||
215 | while (offset < length) { | |
216 | int chunk_size, ret; | |
217 | ||
218 | chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE, | |
219 | length - offset); | |
220 | ||
221 | ret = iwl_nvm_write_chunk(mvm, section, offset, | |
222 | chunk_size, data + offset); | |
223 | if (ret < 0) | |
224 | return ret; | |
225 | ||
226 | offset += chunk_size; | |
227 | } | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
7d162045 JB |
232 | static void iwl_mvm_nvm_fixups(struct iwl_mvm *mvm, unsigned int section, |
233 | u8 *data, unsigned int len) | |
234 | { | |
235 | #define IWL_4165_DEVICE_ID 0x5501 | |
236 | #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) | |
237 | ||
238 | if (section == NVM_SECTION_TYPE_PHY_SKU && | |
239 | mvm->trans->hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && | |
240 | (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) | |
241 | /* OTP 0x52 bug work around: it's a 1x1 device */ | |
242 | data[3] = ANT_B | (ANT_B << 4); | |
243 | } | |
244 | ||
8ca151b5 JB |
245 | /* |
246 | * Reads an NVM section completely. | |
247 | * NICs prior to 7000 family doesn't have a real NVM, but just read | |
248 | * section 0 which is the EEPROM. Because the EEPROM reading is unlimited | |
249 | * by uCode, we need to manually check in this case that we don't | |
250 | * overflow and try to read more than the EEPROM size. | |
251 | * For 7000 family NICs, we supply the maximal size we can read, and | |
252 | * the uCode fills the response with as much data as we can, | |
253 | * without overflowing, so no check is needed. | |
254 | */ | |
255 | static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section, | |
5daddc99 | 256 | u8 *data, u32 size_read) |
8ca151b5 JB |
257 | { |
258 | u16 length, offset = 0; | |
259 | int ret; | |
8ca151b5 | 260 | |
1fd4afe2 DS |
261 | /* Set nvm section read length */ |
262 | length = IWL_NVM_DEFAULT_CHUNK_SIZE; | |
263 | ||
8ca151b5 JB |
264 | ret = length; |
265 | ||
266 | /* Read the NVM until exhausted (reading less than requested) */ | |
267 | while (ret == length) { | |
5daddc99 LK |
268 | /* Check no memory assumptions fail and cause an overflow */ |
269 | if ((size_read + offset + length) > | |
270 | mvm->cfg->base_params->eeprom_size) { | |
271 | IWL_ERR(mvm, "EEPROM size is too small for NVM\n"); | |
272 | return -ENOBUFS; | |
273 | } | |
274 | ||
8ca151b5 JB |
275 | ret = iwl_nvm_read_chunk(mvm, section, offset, length, data); |
276 | if (ret < 0) { | |
d6aeb354 EH |
277 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
278 | "Cannot read NVM from section %d offset %d, length %d\n", | |
279 | section, offset, length); | |
8ca151b5 JB |
280 | return ret; |
281 | } | |
282 | offset += ret; | |
8ca151b5 JB |
283 | } |
284 | ||
7d162045 JB |
285 | iwl_mvm_nvm_fixups(mvm, section, data, offset); |
286 | ||
07fd7d28 JB |
287 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
288 | "NVM section %d read completed\n", section); | |
8ca151b5 JB |
289 | return offset; |
290 | } | |
291 | ||
292 | static struct iwl_nvm_data * | |
293 | iwl_parse_nvm_sections(struct iwl_mvm *mvm) | |
294 | { | |
295 | struct iwl_nvm_section *sections = mvm->nvm_sections; | |
8fe34b06 LC |
296 | const __be16 *hw; |
297 | const __le16 *sw, *calib, *regulatory, *mac_override, *phy_sku; | |
5dd9c68a | 298 | bool lar_enabled; |
44fd09da | 299 | int regulatory_type; |
8ca151b5 JB |
300 | |
301 | /* Checking for required sections */ | |
030a4ccd | 302 | if (mvm->trans->cfg->nvm_type == IWL_NVM) { |
77db0a3c EH |
303 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || |
304 | !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) { | |
abf09c56 | 305 | IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n"); |
77db0a3c EH |
306 | return NULL; |
307 | } | |
308 | } else { | |
44fd09da CRI |
309 | if (mvm->trans->cfg->nvm_type == IWL_NVM_SDP) |
310 | regulatory_type = NVM_SECTION_TYPE_REGULATORY_SDP; | |
311 | else | |
312 | regulatory_type = NVM_SECTION_TYPE_REGULATORY; | |
313 | ||
9f32e017 | 314 | /* SW and REGULATORY sections are mandatory */ |
77db0a3c | 315 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || |
44fd09da | 316 | !mvm->nvm_sections[regulatory_type].data) { |
77db0a3c | 317 | IWL_ERR(mvm, |
abf09c56 | 318 | "Can't parse empty family 8000 OTP/NVM sections\n"); |
77db0a3c EH |
319 | return NULL; |
320 | } | |
9f32e017 | 321 | /* MAC_OVERRIDE or at least HW section must exist */ |
bb926924 | 322 | if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data && |
9f32e017 EH |
323 | !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) { |
324 | IWL_ERR(mvm, | |
325 | "Can't parse mac_address, empty sections\n"); | |
326 | return NULL; | |
327 | } | |
ce500071 | 328 | |
ce500071 | 329 | /* PHY_SKU section is mandatory in B0 */ |
5dd9c68a | 330 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) { |
ce500071 EH |
331 | IWL_ERR(mvm, |
332 | "Can't parse phy_sku in B0, empty sections\n"); | |
333 | return NULL; | |
334 | } | |
8ca151b5 JB |
335 | } |
336 | ||
8fe34b06 | 337 | hw = (const __be16 *)sections[mvm->cfg->nvm_hw_section_num].data; |
8ca151b5 JB |
338 | sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data; |
339 | calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data; | |
77db0a3c EH |
340 | mac_override = |
341 | (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data; | |
ce500071 | 342 | phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data; |
77db0a3c | 343 | |
44fd09da CRI |
344 | regulatory = mvm->trans->cfg->nvm_type == IWL_NVM_SDP ? |
345 | (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY_SDP].data : | |
346 | (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data; | |
347 | ||
5711cac4 | 348 | lar_enabled = !iwlwifi_mod_params.lar_disable && |
859d914c JB |
349 | fw_has_capa(&mvm->fw->ucode_capa, |
350 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT); | |
5711cac4 | 351 | |
afd5b170 | 352 | return iwl_parse_nvm_data(mvm->trans, mvm->cfg, hw, sw, calib, |
ce500071 | 353 | regulatory, mac_override, phy_sku, |
5711cac4 | 354 | mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant, |
afd5b170 | 355 | lar_enabled); |
8ca151b5 JB |
356 | } |
357 | ||
1214755c EH |
358 | #define MAX_NVM_FILE_LEN 16384 |
359 | ||
360 | /* | |
81a67e32 EL |
361 | * Reads external NVM from a file into mvm->nvm_sections |
362 | * | |
1214755c EH |
363 | * HOW TO CREATE THE NVM FILE FORMAT: |
364 | * ------------------------------ | |
365 | * 1. create hex file, format: | |
366 | * 3800 -> header | |
367 | * 0000 -> header | |
368 | * 5a40 -> data | |
369 | * | |
370 | * rev - 6 bit (word1) | |
371 | * len - 10 bit (word1) | |
372 | * id - 4 bit (word2) | |
373 | * rsv - 12 bit (word2) | |
374 | * | |
375 | * 2. flip 8bits with 8 bits per line to get the right NVM file format | |
376 | * | |
377 | * 3. create binary file from the hex file | |
378 | * | |
379 | * 4. save as "iNVM_xxx.bin" under /lib/firmware | |
380 | */ | |
e9e1ba3d | 381 | int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm) |
1214755c | 382 | { |
81a67e32 EL |
383 | int ret, section_size; |
384 | u16 section_id; | |
1214755c EH |
385 | const struct firmware *fw_entry; |
386 | const struct { | |
387 | __le16 word1; | |
388 | __le16 word2; | |
389 | u8 data[]; | |
390 | } *file_sec; | |
7d162045 JB |
391 | const u8 *eof; |
392 | u8 *temp; | |
f251c07c | 393 | int max_section_size; |
a4e5df28 | 394 | const __le32 *dword_buff; |
1214755c EH |
395 | |
396 | #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) | |
397 | #define NVM_WORD2_ID(x) (x >> 12) | |
7042678d SS |
398 | #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) |
399 | #define EXT_NVM_WORD1_ID(x) ((x) >> 4) | |
a4e5df28 IK |
400 | #define NVM_HEADER_0 (0x2A504C54) |
401 | #define NVM_HEADER_1 (0x4E564D2A) | |
402 | #define NVM_HEADER_SIZE (4 * sizeof(u32)) | |
1214755c | 403 | |
81a67e32 EL |
404 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n"); |
405 | ||
7042678d | 406 | /* Maximal size depends on NVM version */ |
44fd09da | 407 | if (mvm->trans->cfg->nvm_type != IWL_NVM_EXT) |
f251c07c | 408 | max_section_size = IWL_MAX_NVM_SECTION_SIZE; |
5dd9c68a | 409 | else |
7042678d | 410 | max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; |
f251c07c | 411 | |
1214755c EH |
412 | /* |
413 | * Obtain NVM image via request_firmware. Since we already used | |
414 | * request_firmware_nowait() for the firmware binary load and only | |
415 | * get here after that we assume the NVM request can be satisfied | |
416 | * synchronously. | |
417 | */ | |
e02a9d60 | 418 | ret = request_firmware(&fw_entry, mvm->nvm_file_name, |
1214755c EH |
419 | mvm->trans->dev); |
420 | if (ret) { | |
421 | IWL_ERR(mvm, "ERROR: %s isn't available %d\n", | |
e02a9d60 | 422 | mvm->nvm_file_name, ret); |
1214755c EH |
423 | return ret; |
424 | } | |
425 | ||
426 | IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n", | |
e02a9d60 | 427 | mvm->nvm_file_name, fw_entry->size); |
1214755c | 428 | |
1214755c EH |
429 | if (fw_entry->size > MAX_NVM_FILE_LEN) { |
430 | IWL_ERR(mvm, "NVM file too large\n"); | |
431 | ret = -EINVAL; | |
432 | goto out; | |
433 | } | |
434 | ||
435 | eof = fw_entry->data + fw_entry->size; | |
a4e5df28 IK |
436 | dword_buff = (__le32 *)fw_entry->data; |
437 | ||
438 | /* some NVM file will contain a header. | |
439 | * The header is identified by 2 dwords header as follow: | |
440 | * dword[0] = 0x2A504C54 | |
441 | * dword[1] = 0x4E564D2A | |
442 | * | |
443 | * This header must be skipped when providing the NVM data to the FW. | |
444 | */ | |
445 | if (fw_entry->size > NVM_HEADER_SIZE && | |
446 | dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && | |
447 | dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { | |
448 | file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); | |
449 | IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); | |
450 | IWL_INFO(mvm, "NVM Manufacturing date %08X\n", | |
451 | le32_to_cpu(dword_buff[3])); | |
d383c740 EH |
452 | |
453 | /* nvm file validation, dword_buff[2] holds the file version */ | |
6e584873 SS |
454 | if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 && |
455 | CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_C_STEP && | |
456 | le32_to_cpu(dword_buff[2]) < 0xE4A) { | |
d383c740 EH |
457 | ret = -EFAULT; |
458 | goto out; | |
459 | } | |
a4e5df28 IK |
460 | } else { |
461 | file_sec = (void *)fw_entry->data; | |
462 | } | |
1214755c EH |
463 | |
464 | while (true) { | |
465 | if (file_sec->data > eof) { | |
466 | IWL_ERR(mvm, | |
467 | "ERROR - NVM file too short for section header\n"); | |
468 | ret = -EINVAL; | |
469 | break; | |
470 | } | |
471 | ||
472 | /* check for EOF marker */ | |
473 | if (!file_sec->word1 && !file_sec->word2) { | |
474 | ret = 0; | |
475 | break; | |
476 | } | |
477 | ||
44fd09da | 478 | if (mvm->trans->cfg->nvm_type != IWL_NVM_EXT) { |
77db0a3c EH |
479 | section_size = |
480 | 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); | |
481 | section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); | |
482 | } else { | |
7042678d | 483 | section_size = 2 * EXT_NVM_WORD2_LEN( |
77db0a3c | 484 | le16_to_cpu(file_sec->word2)); |
7042678d | 485 | section_id = EXT_NVM_WORD1_ID( |
77db0a3c EH |
486 | le16_to_cpu(file_sec->word1)); |
487 | } | |
1214755c | 488 | |
f251c07c | 489 | if (section_size > max_section_size) { |
1214755c EH |
490 | IWL_ERR(mvm, "ERROR - section too large (%d)\n", |
491 | section_size); | |
492 | ret = -EINVAL; | |
493 | break; | |
494 | } | |
495 | ||
496 | if (!section_size) { | |
497 | IWL_ERR(mvm, "ERROR - section empty\n"); | |
498 | ret = -EINVAL; | |
499 | break; | |
500 | } | |
501 | ||
502 | if (file_sec->data + section_size > eof) { | |
503 | IWL_ERR(mvm, | |
504 | "ERROR - NVM file too short for section (%d bytes)\n", | |
505 | section_size); | |
506 | ret = -EINVAL; | |
507 | break; | |
508 | } | |
509 | ||
ae2b21b0 | 510 | if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, |
a4a12478 EL |
511 | "Invalid NVM section ID %d\n", section_id)) { |
512 | ret = -EINVAL; | |
513 | break; | |
514 | } | |
515 | ||
81a67e32 EL |
516 | temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); |
517 | if (!temp) { | |
518 | ret = -ENOMEM; | |
519 | break; | |
520 | } | |
7d162045 JB |
521 | |
522 | iwl_mvm_nvm_fixups(mvm, section_id, temp, section_size); | |
523 | ||
2edb7a33 | 524 | kfree(mvm->nvm_sections[section_id].data); |
81a67e32 EL |
525 | mvm->nvm_sections[section_id].data = temp; |
526 | mvm->nvm_sections[section_id].length = section_size; | |
1214755c EH |
527 | |
528 | /* advance to the next section */ | |
529 | file_sec = (void *)(file_sec->data + section_size); | |
530 | } | |
531 | out: | |
532 | release_firmware(fw_entry); | |
533 | return ret; | |
534 | } | |
535 | ||
81a67e32 EL |
536 | /* Loads the NVM data stored in mvm->nvm_sections into the NIC */ |
537 | int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm) | |
538 | { | |
05159fcc | 539 | int i, ret = 0; |
81a67e32 EL |
540 | struct iwl_nvm_section *sections = mvm->nvm_sections; |
541 | ||
542 | IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n"); | |
543 | ||
099d8f20 EG |
544 | for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) { |
545 | if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length) | |
546 | continue; | |
547 | ret = iwl_nvm_write_section(mvm, i, sections[i].data, | |
548 | sections[i].length); | |
81a67e32 EL |
549 | if (ret < 0) { |
550 | IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret); | |
551 | break; | |
552 | } | |
553 | } | |
554 | return ret; | |
555 | } | |
556 | ||
5bd1d2c1 | 557 | int iwl_nvm_init(struct iwl_mvm *mvm) |
8ca151b5 | 558 | { |
d6aeb354 | 559 | int ret, section; |
5daddc99 | 560 | u32 size_read = 0; |
8ca151b5 | 561 | u8 *nvm_buffer, *temp; |
d383c740 | 562 | const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step; |
8ca151b5 | 563 | |
ae2b21b0 EH |
564 | if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS)) |
565 | return -EINVAL; | |
566 | ||
26481bf4 | 567 | /* load NVM values from nic */ |
5bd1d2c1 LC |
568 | /* Read From FW NVM */ |
569 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n"); | |
570 | ||
571 | nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size, | |
572 | GFP_KERNEL); | |
573 | if (!nvm_buffer) | |
574 | return -ENOMEM; | |
575 | for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) { | |
576 | /* we override the constness for initial read */ | |
577 | ret = iwl_nvm_read_section(mvm, section, nvm_buffer, | |
578 | size_read); | |
579 | if (ret < 0) | |
580 | continue; | |
581 | size_read += ret; | |
582 | temp = kmemdup(nvm_buffer, ret, GFP_KERNEL); | |
583 | if (!temp) { | |
584 | ret = -ENOMEM; | |
585 | break; | |
586 | } | |
7d162045 | 587 | |
5bd1d2c1 | 588 | iwl_mvm_nvm_fixups(mvm, section, temp, ret); |
7d162045 | 589 | |
5bd1d2c1 LC |
590 | mvm->nvm_sections[section].data = temp; |
591 | mvm->nvm_sections[section].length = ret; | |
086f7368 EG |
592 | |
593 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
5bd1d2c1 LC |
594 | switch (section) { |
595 | case NVM_SECTION_TYPE_SW: | |
596 | mvm->nvm_sw_blob.data = temp; | |
597 | mvm->nvm_sw_blob.size = ret; | |
598 | break; | |
599 | case NVM_SECTION_TYPE_CALIBRATION: | |
600 | mvm->nvm_calib_blob.data = temp; | |
601 | mvm->nvm_calib_blob.size = ret; | |
602 | break; | |
603 | case NVM_SECTION_TYPE_PRODUCTION: | |
604 | mvm->nvm_prod_blob.data = temp; | |
605 | mvm->nvm_prod_blob.size = ret; | |
606 | break; | |
607 | case NVM_SECTION_TYPE_PHY_SKU: | |
608 | mvm->nvm_phy_sku_blob.data = temp; | |
609 | mvm->nvm_phy_sku_blob.size = ret; | |
610 | break; | |
611 | default: | |
612 | if (section == mvm->cfg->nvm_hw_section_num) { | |
613 | mvm->nvm_hw_blob.data = temp; | |
614 | mvm->nvm_hw_blob.size = ret; | |
91fac940 | 615 | break; |
086f7368 | 616 | } |
8ca151b5 | 617 | } |
5bd1d2c1 | 618 | #endif |
8ca151b5 | 619 | } |
5bd1d2c1 LC |
620 | if (!size_read) |
621 | IWL_ERR(mvm, "OTP is blank\n"); | |
622 | kfree(nvm_buffer); | |
8ca151b5 | 623 | |
4fb06283 | 624 | /* Only if PNVM selected in the mod param - load external NVM */ |
e02a9d60 | 625 | if (mvm->nvm_file_name) { |
4fb06283 | 626 | /* read External NVM file from the mod param */ |
26481bf4 | 627 | ret = iwl_mvm_read_external_nvm(mvm); |
d383c740 | 628 | if (ret) { |
8b4d6495 | 629 | mvm->nvm_file_name = nvm_file_C; |
d383c740 | 630 | |
488c28e1 OG |
631 | if ((ret == -EFAULT || ret == -ENOENT) && |
632 | mvm->nvm_file_name) { | |
d383c740 EH |
633 | /* in case nvm file was failed try again */ |
634 | ret = iwl_mvm_read_external_nvm(mvm); | |
635 | if (ret) | |
636 | return ret; | |
637 | } else { | |
638 | return ret; | |
639 | } | |
640 | } | |
26481bf4 EH |
641 | } |
642 | ||
643 | /* parse the relevant nvm sections */ | |
b9545b48 | 644 | mvm->nvm_data = iwl_parse_nvm_sections(mvm); |
82598b4f JB |
645 | if (!mvm->nvm_data) |
646 | return -ENODATA; | |
2a831e08 EH |
647 | IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n", |
648 | mvm->nvm_data->nvm_version); | |
8ca151b5 | 649 | |
82598b4f | 650 | return 0; |
8ca151b5 | 651 | } |
dcaf9f5e AN |
652 | |
653 | struct iwl_mcc_update_resp * | |
8ba2d7a1 EH |
654 | iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2, |
655 | enum iwl_mcc_source src_id) | |
dcaf9f5e AN |
656 | { |
657 | struct iwl_mcc_update_cmd mcc_update_cmd = { | |
658 | .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]), | |
8ba2d7a1 | 659 | .source_id = (u8)src_id, |
dcaf9f5e | 660 | }; |
5a7d87da | 661 | struct iwl_mcc_update_resp *resp_cp; |
dcaf9f5e AN |
662 | struct iwl_rx_packet *pkt; |
663 | struct iwl_host_cmd cmd = { | |
664 | .id = MCC_UPDATE_CMD, | |
665 | .flags = CMD_WANT_SKB, | |
666 | .data = { &mcc_update_cmd }, | |
667 | }; | |
668 | ||
669 | int ret; | |
670 | u32 status; | |
671 | int resp_len, n_channels; | |
672 | u16 mcc; | |
6fa52430 MG |
673 | bool resp_v2 = fw_has_capa(&mvm->fw->ucode_capa, |
674 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V2); | |
dcaf9f5e AN |
675 | |
676 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
677 | return ERR_PTR(-EOPNOTSUPP); | |
678 | ||
679 | cmd.len[0] = sizeof(struct iwl_mcc_update_cmd); | |
6fa52430 MG |
680 | if (!resp_v2) |
681 | cmd.len[0] = sizeof(struct iwl_mcc_update_cmd_v1); | |
dcaf9f5e | 682 | |
8ba2d7a1 EH |
683 | IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n", |
684 | alpha2[0], alpha2[1], src_id); | |
dcaf9f5e AN |
685 | |
686 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
687 | if (ret) | |
688 | return ERR_PTR(ret); | |
689 | ||
690 | pkt = cmd.resp_pkt; | |
dcaf9f5e AN |
691 | |
692 | /* Extract MCC response */ | |
6fa52430 | 693 | if (resp_v2) { |
5a7d87da AB |
694 | struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data; |
695 | ||
6fa52430 | 696 | n_channels = __le32_to_cpu(mcc_resp->n_channels); |
5a7d87da AB |
697 | resp_len = sizeof(struct iwl_mcc_update_resp) + |
698 | n_channels * sizeof(__le32); | |
699 | resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL); | |
28269897 JB |
700 | if (!resp_cp) { |
701 | resp_cp = ERR_PTR(-ENOMEM); | |
702 | goto exit; | |
703 | } | |
6fa52430 | 704 | } else { |
5a7d87da AB |
705 | struct iwl_mcc_update_resp_v1 *mcc_resp_v1 = (void *)pkt->data; |
706 | ||
6fa52430 | 707 | n_channels = __le32_to_cpu(mcc_resp_v1->n_channels); |
5a7d87da AB |
708 | resp_len = sizeof(struct iwl_mcc_update_resp) + |
709 | n_channels * sizeof(__le32); | |
710 | resp_cp = kzalloc(resp_len, GFP_KERNEL); | |
28269897 JB |
711 | if (!resp_cp) { |
712 | resp_cp = ERR_PTR(-ENOMEM); | |
713 | goto exit; | |
5a7d87da | 714 | } |
dcaf9f5e | 715 | |
28269897 JB |
716 | resp_cp->status = mcc_resp_v1->status; |
717 | resp_cp->mcc = mcc_resp_v1->mcc; | |
718 | resp_cp->cap = mcc_resp_v1->cap; | |
719 | resp_cp->source_id = mcc_resp_v1->source_id; | |
720 | resp_cp->n_channels = mcc_resp_v1->n_channels; | |
721 | memcpy(resp_cp->channels, mcc_resp_v1->channels, | |
722 | n_channels * sizeof(__le32)); | |
6fa52430 MG |
723 | } |
724 | ||
6fa52430 MG |
725 | status = le32_to_cpu(resp_cp->status); |
726 | ||
727 | mcc = le16_to_cpu(resp_cp->mcc); | |
dcaf9f5e AN |
728 | |
729 | /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ | |
730 | if (mcc == 0) { | |
731 | mcc = 0x3030; /* "00" - world */ | |
6fa52430 | 732 | resp_cp->mcc = cpu_to_le16(mcc); |
dcaf9f5e AN |
733 | } |
734 | ||
dcaf9f5e | 735 | IWL_DEBUG_LAR(mvm, |
3e5648bb EG |
736 | "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') n_chans: %d\n", |
737 | status, mcc, mcc >> 8, mcc & 0xff, n_channels); | |
dcaf9f5e | 738 | |
dcaf9f5e AN |
739 | exit: |
740 | iwl_free_resp(&cmd); | |
dcaf9f5e AN |
741 | return resp_cp; |
742 | } | |
90d4f7db AN |
743 | |
744 | int iwl_mvm_init_mcc(struct iwl_mvm *mvm) | |
745 | { | |
d0d15197 MG |
746 | bool tlv_lar; |
747 | bool nvm_lar; | |
8ba2d7a1 EH |
748 | int retval; |
749 | struct ieee80211_regdomain *regd; | |
7f0344c2 | 750 | char mcc[3]; |
d0d15197 | 751 | |
44fd09da | 752 | if (mvm->cfg->nvm_type == IWL_NVM_EXT) { |
859d914c JB |
753 | tlv_lar = fw_has_capa(&mvm->fw->ucode_capa, |
754 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT); | |
d0d15197 MG |
755 | nvm_lar = mvm->nvm_data->lar_enabled; |
756 | if (tlv_lar != nvm_lar) | |
757 | IWL_INFO(mvm, | |
758 | "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n", | |
759 | tlv_lar ? "enabled" : "disabled", | |
760 | nvm_lar ? "enabled" : "disabled"); | |
761 | } | |
762 | ||
90d4f7db AN |
763 | if (!iwl_mvm_is_lar_supported(mvm)) |
764 | return 0; | |
765 | ||
766 | /* | |
b6e160ab | 767 | * try to replay the last set MCC to FW. If it doesn't exist, |
90d4f7db AN |
768 | * queue an update to cfg80211 to retrieve the default alpha2 from FW. |
769 | */ | |
b6e160ab AN |
770 | retval = iwl_mvm_init_fw_regd(mvm); |
771 | if (retval != -ENOENT) | |
772 | return retval; | |
90d4f7db AN |
773 | |
774 | /* | |
8ba2d7a1 EH |
775 | * Driver regulatory hint for initial update, this also informs the |
776 | * firmware we support wifi location updates. | |
88931cc9 AN |
777 | * Disallow scans that might crash the FW while the LAR regdomain |
778 | * is not set. | |
90d4f7db | 779 | */ |
88931cc9 | 780 | mvm->lar_regdom_set = false; |
8ba2d7a1 | 781 | |
47c8b154 | 782 | regd = iwl_mvm_get_current_regdomain(mvm, NULL); |
8ba2d7a1 EH |
783 | if (IS_ERR_OR_NULL(regd)) |
784 | return -EIO; | |
785 | ||
7f0344c2 | 786 | if (iwl_mvm_is_wifi_mcc_supported(mvm) && |
45f65569 | 787 | !iwl_acpi_get_mcc(mvm->dev, mcc)) { |
7f0344c2 JD |
788 | kfree(regd); |
789 | regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, | |
47c8b154 | 790 | MCC_SOURCE_BIOS, NULL); |
7f0344c2 JD |
791 | if (IS_ERR_OR_NULL(regd)) |
792 | return -EIO; | |
793 | } | |
794 | ||
8ba2d7a1 EH |
795 | retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd); |
796 | kfree(regd); | |
797 | return retval; | |
88931cc9 AN |
798 | } |
799 | ||
0416841d JB |
800 | void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm, |
801 | struct iwl_rx_cmd_buffer *rxb) | |
88931cc9 AN |
802 | { |
803 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
804 | struct iwl_mcc_chub_notif *notif = (void *)pkt->data; | |
8ba2d7a1 | 805 | enum iwl_mcc_source src; |
88931cc9 | 806 | char mcc[3]; |
8ba2d7a1 EH |
807 | struct ieee80211_regdomain *regd; |
808 | ||
809 | lockdep_assert_held(&mvm->mutex); | |
88931cc9 | 810 | |
d4a7e708 HD |
811 | if (iwl_mvm_is_vif_assoc(mvm) && notif->source_id == MCC_SOURCE_WIFI) { |
812 | IWL_DEBUG_LAR(mvm, "Ignore mcc update while associated\n"); | |
813 | return; | |
814 | } | |
815 | ||
88931cc9 | 816 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) |
0416841d | 817 | return; |
88931cc9 | 818 | |
56c1f3c4 JB |
819 | mcc[0] = le16_to_cpu(notif->mcc) >> 8; |
820 | mcc[1] = le16_to_cpu(notif->mcc) & 0xff; | |
88931cc9 | 821 | mcc[2] = '\0'; |
8ba2d7a1 | 822 | src = notif->source_id; |
88931cc9 AN |
823 | |
824 | IWL_DEBUG_LAR(mvm, | |
8ba2d7a1 EH |
825 | "RX: received chub update mcc cmd (mcc '%s' src %d)\n", |
826 | mcc, src); | |
47c8b154 | 827 | regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL); |
8ba2d7a1 | 828 | if (IS_ERR_OR_NULL(regd)) |
0416841d | 829 | return; |
8ba2d7a1 EH |
830 | |
831 | regulatory_set_wiphy_regd(mvm->hw->wiphy, regd); | |
832 | kfree(regd); | |
90d4f7db | 833 | } |