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8ca151b5
JB
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8b4139dc 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
87d0e1af 10 * Copyright (C) 2015 - 2017 Intel Deutschland GmbH
8ca151b5
JB
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
8ca151b5
JB
28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
8ca151b5
JB
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
51368bf7 35 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8b4139dc 36 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
87d0e1af 37 * Copyright (C) 2015 - 2017 Intel Deutschland GmbH
8ca151b5
JB
38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
67#include <net/mac80211.h>
68
69#include "iwl-debug.h"
70#include "iwl-io.h"
7b445f35 71#include "iwl-prph.h"
6b54ebf7 72#include "iwl-csr.h"
8ca151b5 73#include "mvm.h"
d172a5ef 74#include "fw/api/rs.h"
8ca151b5
JB
75
76/*
77 * Will return 0 even if the cmd failed when RFKILL is asserted unless
78 * CMD_WANT_SKB is set in cmd->flags.
79 */
80int iwl_mvm_send_cmd(struct iwl_mvm *mvm, struct iwl_host_cmd *cmd)
81{
82 int ret;
83
debff618
JB
84#if defined(CONFIG_IWLWIFI_DEBUGFS) && defined(CONFIG_PM_SLEEP)
85 if (WARN_ON(mvm->d3_test_active))
86 return -EIO;
87#endif
88
8ca151b5
JB
89 /*
90 * Synchronous commands from this op-mode must hold
91 * the mutex, this ensures we don't try to send two
92 * (or more) synchronous commands at a time.
93 */
71b1230c 94 if (!(cmd->flags & CMD_ASYNC)) {
8ca151b5 95 lockdep_assert_held(&mvm->mutex);
71b1230c
LC
96 if (!(cmd->flags & CMD_SEND_IN_IDLE))
97 iwl_mvm_ref(mvm, IWL_MVM_REF_SENDING_CMD);
98 }
8ca151b5
JB
99
100 ret = iwl_trans_send_cmd(mvm->trans, cmd);
101
71b1230c
LC
102 if (!(cmd->flags & (CMD_ASYNC | CMD_SEND_IN_IDLE)))
103 iwl_mvm_unref(mvm, IWL_MVM_REF_SENDING_CMD);
104
8ca151b5
JB
105 /*
106 * If the caller wants the SKB, then don't hide any problems, the
107 * caller might access the response buffer which will be NULL if
108 * the command failed.
109 */
110 if (cmd->flags & CMD_WANT_SKB)
111 return ret;
112
113 /* Silently ignore failures if RFKILL is asserted */
114 if (!ret || ret == -ERFKILL)
115 return 0;
116 return ret;
117}
118
ab02165c 119int iwl_mvm_send_cmd_pdu(struct iwl_mvm *mvm, u32 id,
8ca151b5
JB
120 u32 flags, u16 len, const void *data)
121{
122 struct iwl_host_cmd cmd = {
123 .id = id,
124 .len = { len, },
125 .data = { data, },
126 .flags = flags,
127 };
128
129 return iwl_mvm_send_cmd(mvm, &cmd);
130}
131
132/*
0d365ae5 133 * We assume that the caller set the status to the success value
8ca151b5
JB
134 */
135int iwl_mvm_send_cmd_status(struct iwl_mvm *mvm, struct iwl_host_cmd *cmd,
136 u32 *status)
137{
138 struct iwl_rx_packet *pkt;
139 struct iwl_cmd_response *resp;
140 int ret, resp_len;
141
142 lockdep_assert_held(&mvm->mutex);
143
debff618
JB
144#if defined(CONFIG_IWLWIFI_DEBUGFS) && defined(CONFIG_PM_SLEEP)
145 if (WARN_ON(mvm->d3_test_active))
146 return -EIO;
147#endif
148
8ca151b5
JB
149 /*
150 * Only synchronous commands can wait for status,
151 * we use WANT_SKB so the caller can't.
152 */
153 if (WARN_ONCE(cmd->flags & (CMD_ASYNC | CMD_WANT_SKB),
154 "cmd flags %x", cmd->flags))
155 return -EINVAL;
156
a1022927 157 cmd->flags |= CMD_WANT_SKB;
8ca151b5
JB
158
159 ret = iwl_trans_send_cmd(mvm->trans, cmd);
160 if (ret == -ERFKILL) {
161 /*
162 * The command failed because of RFKILL, don't update
163 * the status, leave it as success and return 0.
164 */
165 return 0;
166 } else if (ret) {
167 return ret;
168 }
169
170 pkt = cmd->resp_pkt;
8ca151b5 171
65b30348
JB
172 resp_len = iwl_rx_packet_payload_len(pkt);
173 if (WARN_ON_ONCE(resp_len != sizeof(*resp))) {
8ca151b5
JB
174 ret = -EIO;
175 goto out_free_resp;
176 }
177
178 resp = (void *)pkt->data;
179 *status = le32_to_cpu(resp->status);
180 out_free_resp:
181 iwl_free_resp(cmd);
182 return ret;
183}
184
185/*
186 * We assume that the caller set the status to the sucess value
187 */
ab02165c 188int iwl_mvm_send_cmd_pdu_status(struct iwl_mvm *mvm, u32 id, u16 len,
8ca151b5
JB
189 const void *data, u32 *status)
190{
191 struct iwl_host_cmd cmd = {
192 .id = id,
193 .len = { len, },
194 .data = { data, },
195 };
196
197 return iwl_mvm_send_cmd_status(mvm, &cmd, status);
198}
199
200#define IWL_DECLARE_RATE_INFO(r) \
201 [IWL_RATE_##r##M_INDEX] = IWL_RATE_##r##M_PLCP
202
203/*
204 * Translate from fw_rate_index (IWL_RATE_XXM_INDEX) to PLCP
205 */
206static const u8 fw_rate_idx_to_plcp[IWL_RATE_COUNT] = {
207 IWL_DECLARE_RATE_INFO(1),
208 IWL_DECLARE_RATE_INFO(2),
209 IWL_DECLARE_RATE_INFO(5),
210 IWL_DECLARE_RATE_INFO(11),
211 IWL_DECLARE_RATE_INFO(6),
212 IWL_DECLARE_RATE_INFO(9),
213 IWL_DECLARE_RATE_INFO(12),
214 IWL_DECLARE_RATE_INFO(18),
215 IWL_DECLARE_RATE_INFO(24),
216 IWL_DECLARE_RATE_INFO(36),
217 IWL_DECLARE_RATE_INFO(48),
218 IWL_DECLARE_RATE_INFO(54),
219};
220
221int iwl_mvm_legacy_rate_to_mac80211_idx(u32 rate_n_flags,
57fbcce3 222 enum nl80211_band band)
8ca151b5
JB
223{
224 int rate = rate_n_flags & RATE_LEGACY_RATE_MSK;
225 int idx;
226 int band_offset = 0;
227
228 /* Legacy rate format, search for match in table */
57fbcce3 229 if (band == NL80211_BAND_5GHZ)
8ca151b5
JB
230 band_offset = IWL_FIRST_OFDM_RATE;
231 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
232 if (fw_rate_idx_to_plcp[idx] == rate)
233 return idx - band_offset;
234
235 return -1;
236}
237
238u8 iwl_mvm_mac80211_idx_to_hwrate(int rate_idx)
239{
240 /* Get PLCP rate for tx_cmd->rate_n_flags */
241 return fw_rate_idx_to_plcp[rate_idx];
242}
243
0416841d 244void iwl_mvm_rx_fw_error(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb)
8ca151b5
JB
245{
246 struct iwl_rx_packet *pkt = rxb_addr(rxb);
247 struct iwl_error_resp *err_resp = (void *)pkt->data;
248
249 IWL_ERR(mvm, "FW Error notification: type 0x%08X cmd_id 0x%02X\n",
250 le32_to_cpu(err_resp->error_type), err_resp->cmd_id);
251 IWL_ERR(mvm, "FW Error notification: seq 0x%04X service 0x%08X\n",
252 le16_to_cpu(err_resp->bad_cmd_seq_num),
253 le32_to_cpu(err_resp->error_service));
254 IWL_ERR(mvm, "FW Error notification: timestamp 0x%16llX\n",
255 le64_to_cpu(err_resp->timestamp));
8ca151b5
JB
256}
257
258/*
259 * Returns the first antenna as ANT_[ABC], as defined in iwl-config.h.
260 * The parameter should also be a combination of ANT_[ABC].
261 */
262u8 first_antenna(u8 mask)
263{
264 BUILD_BUG_ON(ANT_A != BIT(0)); /* using ffs is wrong if not */
d7dad550
EG
265 if (WARN_ON_ONCE(!mask)) /* ffs will return 0 if mask is zeroed */
266 return BIT(0);
267 return BIT(ffs(mask) - 1);
8ca151b5
JB
268}
269
270/*
271 * Toggles between TX antennas to send the probe request on.
272 * Receives the bitmask of valid TX antennas and the *index* used
273 * for the last TX, and returns the next valid *index* to use.
274 * In order to set it in the tx_cmd, must do BIT(idx).
275 */
276u8 iwl_mvm_next_antenna(struct iwl_mvm *mvm, u8 valid, u8 last_idx)
277{
278 u8 ind = last_idx;
279 int i;
280
281 for (i = 0; i < RATE_MCS_ANT_NUM; i++) {
282 ind = (ind + 1) % RATE_MCS_ANT_NUM;
283 if (valid & BIT(ind))
284 return ind;
285 }
286
287 WARN_ONCE(1, "Failed to toggle between antennas 0x%x", valid);
288 return last_idx;
289}
290
e5209263
JB
291static const struct {
292 const char *name;
8ca151b5
JB
293 u8 num;
294} advanced_lookup[] = {
295 { "NMI_INTERRUPT_WDG", 0x34 },
296 { "SYSASSERT", 0x35 },
297 { "UCODE_VERSION_MISMATCH", 0x37 },
298 { "BAD_COMMAND", 0x38 },
299 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
300 { "FATAL_ERROR", 0x3D },
301 { "NMI_TRM_HW_ERR", 0x46 },
302 { "NMI_INTERRUPT_TRM", 0x4C },
303 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
304 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
305 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
306 { "NMI_INTERRUPT_HOST", 0x66 },
307 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
308 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
309 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
310 { "ADVANCED_SYSASSERT", 0 },
311};
312
313static const char *desc_lookup(u32 num)
314{
315 int i;
316
317 for (i = 0; i < ARRAY_SIZE(advanced_lookup) - 1; i++)
318 if (advanced_lookup[i].num == num)
319 return advanced_lookup[i].name;
320
321 /* No entry matches 'num', so it is the last: ADVANCED_SYSASSERT */
322 return advanced_lookup[i].name;
323}
324
325/*
326 * Note: This structure is read from the device with IO accesses,
327 * and the reading already does the endian conversion. As it is
328 * read with u32-sized accesses, any members with a different size
329 * need to be ordered correctly though!
330 */
7e1223b5 331struct iwl_error_event_table_v1 {
8ca151b5
JB
332 u32 valid; /* (nonzero) valid, (0) log is empty */
333 u32 error_id; /* type of error */
334 u32 pc; /* program counter */
335 u32 blink1; /* branch link */
336 u32 blink2; /* branch link */
337 u32 ilink1; /* interrupt link */
338 u32 ilink2; /* interrupt link */
339 u32 data1; /* error-specific data */
340 u32 data2; /* error-specific data */
341 u32 data3; /* error-specific data */
342 u32 bcon_time; /* beacon timer */
343 u32 tsf_low; /* network timestamp function timer */
344 u32 tsf_hi; /* network timestamp function timer */
345 u32 gp1; /* GP1 timer register */
346 u32 gp2; /* GP2 timer register */
347 u32 gp3; /* GP3 timer register */
348 u32 ucode_ver; /* uCode version */
349 u32 hw_ver; /* HW Silicon version */
350 u32 brd_ver; /* HW board version */
351 u32 log_pc; /* log program counter */
352 u32 frame_ptr; /* frame pointer */
353 u32 stack_ptr; /* stack pointer */
354 u32 hcmd; /* last host command header */
355 u32 isr0; /* isr status register LMPM_NIC_ISR0:
356 * rxtx_flag */
357 u32 isr1; /* isr status register LMPM_NIC_ISR1:
358 * host_flag */
359 u32 isr2; /* isr status register LMPM_NIC_ISR2:
360 * enc_flag */
361 u32 isr3; /* isr status register LMPM_NIC_ISR3:
362 * time_flag */
363 u32 isr4; /* isr status register LMPM_NIC_ISR4:
364 * wico interrupt */
365 u32 isr_pref; /* isr status register LMPM_NIC_PREF_STAT */
366 u32 wait_event; /* wait event() caller address */
367 u32 l2p_control; /* L2pControlField */
368 u32 l2p_duration; /* L2pDurationField */
369 u32 l2p_mhvalid; /* L2pMhValidBits */
370 u32 l2p_addr_match; /* L2pAddrMatchStat */
371 u32 lmpm_pmg_sel; /* indicate which clocks are turned on
372 * (LMPM_PMG_SEL) */
373 u32 u_timestamp; /* indicate when the date and time of the
374 * compilation */
375 u32 flow_handler; /* FH read/write pointers, RX credit */
7e1223b5
EG
376} __packed /* LOG_ERROR_TABLE_API_S_VER_1 */;
377
378struct iwl_error_event_table {
379 u32 valid; /* (nonzero) valid, (0) log is empty */
380 u32 error_id; /* type of error */
7d3ca7f4
EG
381 u32 trm_hw_status0; /* TRM HW status */
382 u32 trm_hw_status1; /* TRM HW status */
7e1223b5
EG
383 u32 blink2; /* branch link */
384 u32 ilink1; /* interrupt link */
385 u32 ilink2; /* interrupt link */
386 u32 data1; /* error-specific data */
387 u32 data2; /* error-specific data */
388 u32 data3; /* error-specific data */
389 u32 bcon_time; /* beacon timer */
390 u32 tsf_low; /* network timestamp function timer */
391 u32 tsf_hi; /* network timestamp function timer */
392 u32 gp1; /* GP1 timer register */
393 u32 gp2; /* GP2 timer register */
7d3ca7f4 394 u32 fw_rev_type; /* firmware revision type */
7e1223b5
EG
395 u32 major; /* uCode version major */
396 u32 minor; /* uCode version minor */
397 u32 hw_ver; /* HW Silicon version */
398 u32 brd_ver; /* HW board version */
399 u32 log_pc; /* log program counter */
400 u32 frame_ptr; /* frame pointer */
401 u32 stack_ptr; /* stack pointer */
402 u32 hcmd; /* last host command header */
403 u32 isr0; /* isr status register LMPM_NIC_ISR0:
404 * rxtx_flag */
405 u32 isr1; /* isr status register LMPM_NIC_ISR1:
406 * host_flag */
407 u32 isr2; /* isr status register LMPM_NIC_ISR2:
408 * enc_flag */
409 u32 isr3; /* isr status register LMPM_NIC_ISR3:
410 * time_flag */
411 u32 isr4; /* isr status register LMPM_NIC_ISR4:
412 * wico interrupt */
7d3ca7f4 413 u32 last_cmd_id; /* last HCMD id handled by the firmware */
7e1223b5
EG
414 u32 wait_event; /* wait event() caller address */
415 u32 l2p_control; /* L2pControlField */
416 u32 l2p_duration; /* L2pDurationField */
417 u32 l2p_mhvalid; /* L2pMhValidBits */
418 u32 l2p_addr_match; /* L2pAddrMatchStat */
419 u32 lmpm_pmg_sel; /* indicate which clocks are turned on
420 * (LMPM_PMG_SEL) */
421 u32 u_timestamp; /* indicate when the date and time of the
422 * compilation */
423 u32 flow_handler; /* FH read/write pointers, RX credit */
7d3ca7f4 424} __packed /* LOG_ERROR_TABLE_API_S_VER_3 */;
8ca151b5 425
01a9ca51
EH
426/*
427 * UMAC error struct - relevant starting from family 8000 chip.
428 * Note: This structure is read from the device with IO accesses,
429 * and the reading already does the endian conversion. As it is
430 * read with u32-sized accesses, any members with a different size
431 * need to be ordered correctly though!
432 */
433struct iwl_umac_error_event_table {
434 u32 valid; /* (nonzero) valid, (0) log is empty */
435 u32 error_id; /* type of error */
01a9ca51
EH
436 u32 blink1; /* branch link */
437 u32 blink2; /* branch link */
438 u32 ilink1; /* interrupt link */
439 u32 ilink2; /* interrupt link */
440 u32 data1; /* error-specific data */
441 u32 data2; /* error-specific data */
32be1a83 442 u32 data3; /* error-specific data */
7e1223b5
EG
443 u32 umac_major;
444 u32 umac_minor;
32be1a83
EH
445 u32 frame_pointer; /* core register 27*/
446 u32 stack_pointer; /* core register 28 */
7e1223b5 447 u32 cmd_header; /* latest host cmd sent to UMAC */
32be1a83 448 u32 nic_isr_pref; /* ISR status register */
01a9ca51
EH
449} __packed;
450
8ca151b5
JB
451#define ERROR_START_OFFSET (1 * sizeof(u32))
452#define ERROR_ELEM_SIZE (7 * sizeof(u32))
453
01a9ca51
EH
454static void iwl_mvm_dump_umac_error_log(struct iwl_mvm *mvm)
455{
456 struct iwl_trans *trans = mvm->trans;
457 struct iwl_umac_error_event_table table;
01a9ca51 458
fb5b2846 459 if (!mvm->support_umac_log)
01a9ca51 460 return;
01a9ca51 461
fb5b2846
LC
462 iwl_trans_read_mem_bytes(trans, mvm->umac_error_event_table, &table,
463 sizeof(table));
01a9ca51
EH
464
465 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
466 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
467 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
468 mvm->status, table.valid);
469 }
470
edbad051 471 IWL_ERR(mvm, "0x%08X | %s\n", table.error_id,
01a9ca51 472 desc_lookup(table.error_id));
01a9ca51
EH
473 IWL_ERR(mvm, "0x%08X | umac branchlink1\n", table.blink1);
474 IWL_ERR(mvm, "0x%08X | umac branchlink2\n", table.blink2);
475 IWL_ERR(mvm, "0x%08X | umac interruptlink1\n", table.ilink1);
476 IWL_ERR(mvm, "0x%08X | umac interruptlink2\n", table.ilink2);
477 IWL_ERR(mvm, "0x%08X | umac data1\n", table.data1);
478 IWL_ERR(mvm, "0x%08X | umac data2\n", table.data2);
32be1a83 479 IWL_ERR(mvm, "0x%08X | umac data3\n", table.data3);
7e1223b5
EG
480 IWL_ERR(mvm, "0x%08X | umac major\n", table.umac_major);
481 IWL_ERR(mvm, "0x%08X | umac minor\n", table.umac_minor);
32be1a83
EH
482 IWL_ERR(mvm, "0x%08X | frame pointer\n", table.frame_pointer);
483 IWL_ERR(mvm, "0x%08X | stack pointer\n", table.stack_pointer);
484 IWL_ERR(mvm, "0x%08X | last host cmd\n", table.cmd_header);
485 IWL_ERR(mvm, "0x%08X | isr status reg\n", table.nic_isr_pref);
01a9ca51
EH
486}
487
5c228d63 488static void iwl_mvm_dump_lmac_error_log(struct iwl_mvm *mvm, u32 base)
7e1223b5
EG
489{
490 struct iwl_trans *trans = mvm->trans;
491 struct iwl_error_event_table table;
6b54ebf7 492 u32 val;
7e1223b5 493
702e975d 494 if (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) {
7e1223b5
EG
495 if (!base)
496 base = mvm->fw->init_errlog_ptr;
497 } else {
498 if (!base)
499 base = mvm->fw->inst_errlog_ptr;
500 }
501
3ac37d01 502 if (base < 0x400000) {
7e1223b5
EG
503 IWL_ERR(mvm,
504 "Not valid error log pointer 0x%08X for %s uCode\n",
505 base,
702e975d
JB
506 (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT)
507 ? "Init" : "RT");
7e1223b5
EG
508 return;
509 }
510
6b54ebf7
LC
511 /* check if there is a HW error */
512 val = iwl_trans_read_mem32(trans, base);
513 if (((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50)) {
514 int err;
515
516 IWL_ERR(trans, "HW error, resetting before reading\n");
517
518 /* reset the device */
519 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
099a628b 520 usleep_range(5000, 6000);
6b54ebf7
LC
521
522 /* set INIT_DONE flag */
523 iwl_set_bit(trans, CSR_GP_CNTRL,
524 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
525
526 /* and wait for clock stabilization */
527 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
528 udelay(2);
529
530 err = iwl_poll_bit(trans, CSR_GP_CNTRL,
531 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
532 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
533 25000);
534 if (err < 0) {
535 IWL_DEBUG_INFO(trans,
536 "Failed to reset the card for the dump\n");
537 return;
538 }
539 }
540
7e1223b5
EG
541 iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
542
543 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
544 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
545 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
546 mvm->status, table.valid);
547 }
548
549 /* Do not change this output - scripts rely on it */
550
551 IWL_ERR(mvm, "Loaded firmware version: %s\n", mvm->fw->fw_version);
552
553 trace_iwlwifi_dev_ucode_error(trans->dev, table.error_id, table.tsf_low,
554 table.data1, table.data2, table.data3,
7d3ca7f4 555 table.blink2, table.ilink1,
7e1223b5 556 table.ilink2, table.bcon_time, table.gp1,
7d3ca7f4 557 table.gp2, table.fw_rev_type, table.major,
7e1223b5
EG
558 table.minor, table.hw_ver, table.brd_ver);
559 IWL_ERR(mvm, "0x%08X | %-28s\n", table.error_id,
560 desc_lookup(table.error_id));
7d3ca7f4
EG
561 IWL_ERR(mvm, "0x%08X | trm_hw_status0\n", table.trm_hw_status0);
562 IWL_ERR(mvm, "0x%08X | trm_hw_status1\n", table.trm_hw_status1);
7e1223b5
EG
563 IWL_ERR(mvm, "0x%08X | branchlink2\n", table.blink2);
564 IWL_ERR(mvm, "0x%08X | interruptlink1\n", table.ilink1);
565 IWL_ERR(mvm, "0x%08X | interruptlink2\n", table.ilink2);
566 IWL_ERR(mvm, "0x%08X | data1\n", table.data1);
567 IWL_ERR(mvm, "0x%08X | data2\n", table.data2);
568 IWL_ERR(mvm, "0x%08X | data3\n", table.data3);
569 IWL_ERR(mvm, "0x%08X | beacon time\n", table.bcon_time);
570 IWL_ERR(mvm, "0x%08X | tsf low\n", table.tsf_low);
571 IWL_ERR(mvm, "0x%08X | tsf hi\n", table.tsf_hi);
572 IWL_ERR(mvm, "0x%08X | time gp1\n", table.gp1);
573 IWL_ERR(mvm, "0x%08X | time gp2\n", table.gp2);
7d3ca7f4 574 IWL_ERR(mvm, "0x%08X | uCode revision type\n", table.fw_rev_type);
7e1223b5
EG
575 IWL_ERR(mvm, "0x%08X | uCode version major\n", table.major);
576 IWL_ERR(mvm, "0x%08X | uCode version minor\n", table.minor);
577 IWL_ERR(mvm, "0x%08X | hw version\n", table.hw_ver);
578 IWL_ERR(mvm, "0x%08X | board version\n", table.brd_ver);
579 IWL_ERR(mvm, "0x%08X | hcmd\n", table.hcmd);
580 IWL_ERR(mvm, "0x%08X | isr0\n", table.isr0);
581 IWL_ERR(mvm, "0x%08X | isr1\n", table.isr1);
582 IWL_ERR(mvm, "0x%08X | isr2\n", table.isr2);
583 IWL_ERR(mvm, "0x%08X | isr3\n", table.isr3);
584 IWL_ERR(mvm, "0x%08X | isr4\n", table.isr4);
7d3ca7f4 585 IWL_ERR(mvm, "0x%08X | last cmd Id\n", table.last_cmd_id);
7e1223b5
EG
586 IWL_ERR(mvm, "0x%08X | wait_event\n", table.wait_event);
587 IWL_ERR(mvm, "0x%08X | l2p_control\n", table.l2p_control);
588 IWL_ERR(mvm, "0x%08X | l2p_duration\n", table.l2p_duration);
589 IWL_ERR(mvm, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
590 IWL_ERR(mvm, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
591 IWL_ERR(mvm, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
592 IWL_ERR(mvm, "0x%08X | timestamp\n", table.u_timestamp);
593 IWL_ERR(mvm, "0x%08X | flow_handler\n", table.flow_handler);
5c228d63
SS
594}
595
596void iwl_mvm_dump_nic_error_log(struct iwl_mvm *mvm)
597{
598 iwl_mvm_dump_lmac_error_log(mvm, mvm->error_event_table[0]);
599
600 if (mvm->error_event_table[1])
601 iwl_mvm_dump_lmac_error_log(mvm, mvm->error_event_table[1]);
7e1223b5 602
fb5b2846 603 iwl_mvm_dump_umac_error_log(mvm);
7e1223b5 604}
4ecafae9 605
9794c64f 606int iwl_mvm_find_free_queue(struct iwl_mvm *mvm, u8 sta_id, u8 minq, u8 maxq)
4ecafae9
LK
607{
608 int i;
609
610 lockdep_assert_held(&mvm->queue_info_lock);
611
396952ee
SS
612 /* This should not be hit with new TX path */
613 if (WARN_ON(iwl_mvm_has_new_tx_api(mvm)))
614 return -ENOSPC;
615
9794c64f 616 /* Start by looking for a free queue */
4ecafae9
LK
617 for (i = minq; i <= maxq; i++)
618 if (mvm->queue_info[i].hw_queue_refcount == 0 &&
cf961e16 619 mvm->queue_info[i].status == IWL_MVM_QUEUE_FREE)
4ecafae9
LK
620 return i;
621
9794c64f
LK
622 /*
623 * If no free queue found - settle for an inactive one to reconfigure
624 * Make sure that the inactive queue either already belongs to this STA,
625 * or that if it belongs to another one - it isn't the reserved queue
626 */
627 for (i = minq; i <= maxq; i++)
628 if (mvm->queue_info[i].status == IWL_MVM_QUEUE_INACTIVE &&
629 (sta_id == mvm->queue_info[i].ra_sta_id ||
630 !mvm->queue_info[i].reserved))
631 return i;
632
4ecafae9
LK
633 return -ENOSPC;
634}
635
cf961e16
LK
636int iwl_mvm_reconfig_scd(struct iwl_mvm *mvm, int queue, int fifo, int sta_id,
637 int tid, int frame_limit, u16 ssn)
638{
639 struct iwl_scd_txq_cfg_cmd cmd = {
640 .scd_queue = queue,
f7c692de 641 .action = SCD_CFG_ENABLE_QUEUE,
cf961e16
LK
642 .window = frame_limit,
643 .sta_id = sta_id,
644 .ssn = cpu_to_le16(ssn),
645 .tx_fifo = fifo,
646 .aggregate = (queue >= IWL_MVM_DQA_MIN_DATA_QUEUE ||
647 queue == IWL_MVM_DQA_BSS_CLIENT_QUEUE),
648 .tid = tid,
649 };
650 int ret;
651
bb49701b
SS
652 if (WARN_ON(iwl_mvm_has_new_tx_api(mvm)))
653 return -EINVAL;
654
cf961e16
LK
655 spin_lock_bh(&mvm->queue_info_lock);
656 if (WARN(mvm->queue_info[queue].hw_queue_refcount == 0,
657 "Trying to reconfig unallocated queue %d\n", queue)) {
658 spin_unlock_bh(&mvm->queue_info_lock);
659 return -ENXIO;
660 }
661 spin_unlock_bh(&mvm->queue_info_lock);
662
663 IWL_DEBUG_TX_QUEUES(mvm, "Reconfig SCD for TXQ #%d\n", queue);
664
665 ret = iwl_mvm_send_cmd_pdu(mvm, SCD_QUEUE_CFG, 0, sizeof(cmd), &cmd);
666 WARN_ONCE(ret, "Failed to re-configure queue %d on FIFO %d, ret=%d\n",
667 queue, fifo, ret);
668
669 return ret;
670}
671
87d0e1af
SS
672static bool iwl_mvm_update_txq_mapping(struct iwl_mvm *mvm, int queue,
673 int mac80211_queue, u8 sta_id, u8 tid)
3edf8ff6 674{
4ecafae9
LK
675 bool enable_queue = true;
676
677 spin_lock_bh(&mvm->queue_info_lock);
0294d9ee 678
4ecafae9 679 /* Make sure this TID isn't already enabled */
87d0e1af 680 if (mvm->queue_info[queue].tid_bitmap & BIT(tid)) {
4ecafae9 681 spin_unlock_bh(&mvm->queue_info_lock);
df88c08d 682 IWL_ERR(mvm, "Trying to enable TXQ %d with existing TID %d\n",
87d0e1af
SS
683 queue, tid);
684 return false;
4ecafae9
LK
685 }
686
687 /* Update mappings and refcounts */
42db09c1
LK
688 if (mvm->queue_info[queue].hw_queue_refcount > 0)
689 enable_queue = false;
690
37e474ac
JB
691 if (mac80211_queue != IEEE80211_INVAL_HW_QUEUE) {
692 WARN(mac80211_queue >=
693 BITS_PER_BYTE * sizeof(mvm->hw_queue_to_mac80211[0]),
694 "cannot track mac80211 queue %d (queue %d, sta %d, tid %d)\n",
695 mac80211_queue, queue, sta_id, tid);
696 mvm->hw_queue_to_mac80211[queue] |= BIT(mac80211_queue);
697 }
34e10860 698
4ecafae9 699 mvm->queue_info[queue].hw_queue_refcount++;
87d0e1af
SS
700 mvm->queue_info[queue].tid_bitmap |= BIT(tid);
701 mvm->queue_info[queue].ra_sta_id = sta_id;
4ecafae9 702
42db09c1 703 if (enable_queue) {
87d0e1af 704 if (tid != IWL_MAX_TID_COUNT)
42db09c1 705 mvm->queue_info[queue].mac80211_ac =
87d0e1af 706 tid_to_mac80211_ac[tid];
42db09c1
LK
707 else
708 mvm->queue_info[queue].mac80211_ac = IEEE80211_AC_VO;
edbe961c 709
87d0e1af 710 mvm->queue_info[queue].txq_tid = tid;
42db09c1
LK
711 }
712
4ecafae9
LK
713 IWL_DEBUG_TX_QUEUES(mvm,
714 "Enabling TXQ #%d refcount=%d (mac80211 map:0x%x)\n",
715 queue, mvm->queue_info[queue].hw_queue_refcount,
34e10860 716 mvm->hw_queue_to_mac80211[queue]);
4ecafae9
LK
717
718 spin_unlock_bh(&mvm->queue_info_lock);
719
87d0e1af
SS
720 return enable_queue;
721}
722
310181ec
SS
723int iwl_mvm_tvqm_enable_txq(struct iwl_mvm *mvm, int mac80211_queue,
724 u8 sta_id, u8 tid, unsigned int timeout)
725{
726 struct iwl_tx_queue_cfg_cmd cmd = {
727 .flags = cpu_to_le16(TX_QUEUE_CFG_ENABLE_QUEUE),
728 .sta_id = sta_id,
729 .tid = tid,
730 };
731 int queue;
732
733 if (cmd.tid == IWL_MAX_TID_COUNT)
734 cmd.tid = IWL_MGMT_TID;
735 queue = iwl_trans_txq_alloc(mvm->trans, (void *)&cmd,
736 SCD_QUEUE_CFG, timeout);
737
738 if (queue < 0) {
739 IWL_DEBUG_TX_QUEUES(mvm,
740 "Failed allocating TXQ for sta %d tid %d, ret: %d\n",
741 sta_id, tid, queue);
742 return queue;
743 }
744
745 IWL_DEBUG_TX_QUEUES(mvm, "Enabling TXQ #%d for sta %d tid %d\n",
746 queue, sta_id, tid);
747
34e10860
SS
748 mvm->hw_queue_to_mac80211[queue] |= BIT(mac80211_queue);
749 IWL_DEBUG_TX_QUEUES(mvm,
750 "Enabling TXQ #%d (mac80211 map:0x%x)\n",
751 queue, mvm->hw_queue_to_mac80211[queue]);
310181ec
SS
752
753 return queue;
754}
755
dcfbd67b 756bool iwl_mvm_enable_txq(struct iwl_mvm *mvm, int queue, int mac80211_queue,
87d0e1af
SS
757 u16 ssn, const struct iwl_trans_txq_scd_cfg *cfg,
758 unsigned int wdg_timeout)
759{
dcfbd67b
EG
760 struct iwl_scd_txq_cfg_cmd cmd = {
761 .scd_queue = queue,
762 .action = SCD_CFG_ENABLE_QUEUE,
763 .window = cfg->frame_limit,
764 .sta_id = cfg->sta_id,
765 .ssn = cpu_to_le16(ssn),
766 .tx_fifo = cfg->fifo,
767 .aggregate = cfg->aggregate,
768 .tid = cfg->tid,
769 };
770 bool inc_ssn;
771
310181ec 772 if (WARN_ON(iwl_mvm_has_new_tx_api(mvm)))
dcfbd67b 773 return false;
310181ec 774
4ecafae9 775 /* Send the enabling command if we need to */
dcfbd67b
EG
776 if (!iwl_mvm_update_txq_mapping(mvm, queue, mac80211_queue,
777 cfg->sta_id, cfg->tid))
778 return false;
779
780 inc_ssn = iwl_trans_txq_enable_cfg(mvm->trans, queue, ssn,
781 NULL, wdg_timeout);
782 if (inc_ssn)
783 le16_add_cpu(&cmd.ssn, 1);
784
785 WARN(iwl_mvm_send_cmd_pdu(mvm, SCD_QUEUE_CFG, 0, sizeof(cmd), &cmd),
786 "Failed to configure queue %d on FIFO %d\n", queue, cfg->fifo);
787
788 return inc_ssn;
3edf8ff6
AA
789}
790
cf90da35
SS
791int iwl_mvm_disable_txq(struct iwl_mvm *mvm, int queue, int mac80211_queue,
792 u8 tid, u8 flags)
3edf8ff6 793{
310181ec 794 struct iwl_scd_txq_cfg_cmd cmd = {
0294d9ee 795 .scd_queue = queue,
f7c692de 796 .action = SCD_CFG_DISABLE_QUEUE,
0294d9ee 797 };
4ecafae9 798 bool remove_mac_queue = true;
34e10860
SS
799 int ret;
800
801 if (iwl_mvm_has_new_tx_api(mvm)) {
802 spin_lock_bh(&mvm->queue_info_lock);
803 mvm->hw_queue_to_mac80211[queue] &= ~BIT(mac80211_queue);
804 spin_unlock_bh(&mvm->queue_info_lock);
805
806 iwl_trans_txq_free(mvm->trans, queue);
807
808 return 0;
809 }
0294d9ee 810
4ecafae9
LK
811 spin_lock_bh(&mvm->queue_info_lock);
812
813 if (WARN_ON(mvm->queue_info[queue].hw_queue_refcount == 0)) {
814 spin_unlock_bh(&mvm->queue_info_lock);
cf90da35 815 return 0;
4ecafae9
LK
816 }
817
818 mvm->queue_info[queue].tid_bitmap &= ~BIT(tid);
819
820 /*
821 * If there is another TID with the same AC - don't remove the MAC queue
822 * from the mapping
823 */
824 if (tid < IWL_MAX_TID_COUNT) {
825 unsigned long tid_bitmap =
826 mvm->queue_info[queue].tid_bitmap;
827 int ac = tid_to_mac80211_ac[tid];
828 int i;
829
830 for_each_set_bit(i, &tid_bitmap, IWL_MAX_TID_COUNT) {
831 if (tid_to_mac80211_ac[i] == ac)
832 remove_mac_queue = false;
833 }
834 }
835
836 if (remove_mac_queue)
34e10860 837 mvm->hw_queue_to_mac80211[queue] &=
4ecafae9
LK
838 ~BIT(mac80211_queue);
839 mvm->queue_info[queue].hw_queue_refcount--;
840
f7c692de
LK
841 cmd.action = mvm->queue_info[queue].hw_queue_refcount ?
842 SCD_CFG_ENABLE_QUEUE : SCD_CFG_DISABLE_QUEUE;
843 if (cmd.action == SCD_CFG_DISABLE_QUEUE)
cf961e16 844 mvm->queue_info[queue].status = IWL_MVM_QUEUE_FREE;
4ecafae9
LK
845
846 IWL_DEBUG_TX_QUEUES(mvm,
847 "Disabling TXQ #%d refcount=%d (mac80211 map:0x%x)\n",
848 queue,
849 mvm->queue_info[queue].hw_queue_refcount,
34e10860 850 mvm->hw_queue_to_mac80211[queue]);
4ecafae9
LK
851
852 /* If the queue is still enabled - nothing left to do in this func */
f7c692de 853 if (cmd.action == SCD_CFG_ENABLE_QUEUE) {
4ecafae9 854 spin_unlock_bh(&mvm->queue_info_lock);
cf90da35 855 return 0;
4ecafae9
LK
856 }
857
f02669be 858 cmd.sta_id = mvm->queue_info[queue].ra_sta_id;
edbe961c 859 cmd.tid = mvm->queue_info[queue].txq_tid;
f02669be 860
4ecafae9
LK
861 /* Make sure queue info is correct even though we overwrite it */
862 WARN(mvm->queue_info[queue].hw_queue_refcount ||
863 mvm->queue_info[queue].tid_bitmap ||
34e10860 864 mvm->hw_queue_to_mac80211[queue],
4ecafae9
LK
865 "TXQ #%d info out-of-sync - refcount=%d, mac map=0x%x, tid=0x%x\n",
866 queue, mvm->queue_info[queue].hw_queue_refcount,
34e10860 867 mvm->hw_queue_to_mac80211[queue],
4ecafae9
LK
868 mvm->queue_info[queue].tid_bitmap);
869
870 /* If we are here - the queue is freed and we can zero out these vals */
871 mvm->queue_info[queue].hw_queue_refcount = 0;
872 mvm->queue_info[queue].tid_bitmap = 0;
34e10860 873 mvm->hw_queue_to_mac80211[queue] = 0;
4ecafae9 874
9794c64f
LK
875 /* Regardless if this is a reserved TXQ for a STA - mark it as false */
876 mvm->queue_info[queue].reserved = false;
877
4ecafae9
LK
878 spin_unlock_bh(&mvm->queue_info_lock);
879
34e10860
SS
880 iwl_trans_txq_disable(mvm->trans, queue, false);
881 ret = iwl_mvm_send_cmd_pdu(mvm, SCD_QUEUE_CFG, flags,
882 sizeof(struct iwl_scd_txq_cfg_cmd), &cmd);
cf90da35 883
34e10860
SS
884 if (ret)
885 IWL_ERR(mvm, "Failed to disable queue %d (ret=%d)\n",
886 queue, ret);
887 return ret;
3edf8ff6
AA
888}
889
8ca151b5
JB
890/**
891 * iwl_mvm_send_lq_cmd() - Send link quality command
892 * @init: This command is sent as part of station initialization right
893 * after station has been added.
894 *
895 * The link quality command is sent as the last step of station creation.
896 * This is the special case in which init is set and we call a callback in
897 * this case to clear the state indicating that station creation is in
898 * progress.
899 */
9e680946 900int iwl_mvm_send_lq_cmd(struct iwl_mvm *mvm, struct iwl_lq_cmd *lq, bool init)
8ca151b5
JB
901{
902 struct iwl_host_cmd cmd = {
903 .id = LQ_CMD,
904 .len = { sizeof(struct iwl_lq_cmd), },
a1022927 905 .flags = init ? 0 : CMD_ASYNC,
8ca151b5
JB
906 .data = { lq, },
907 };
908
0ae98812 909 if (WARN_ON(lq->sta_id == IWL_MVM_INVALID_STA))
8ca151b5
JB
910 return -EINVAL;
911
8ca151b5
JB
912 return iwl_mvm_send_cmd(mvm, &cmd);
913}
9ee718aa
EL
914
915/**
0d365ae5 916 * iwl_mvm_update_smps - Get a request to change the SMPS mode
9ee718aa
EL
917 * @req_type: The part of the driver who call for a change.
918 * @smps_requests: The request to change the SMPS mode.
919 *
920 * Get a requst to change the SMPS mode,
921 * and change it according to all other requests in the driver.
922 */
923void iwl_mvm_update_smps(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
924 enum iwl_mvm_smps_type_request req_type,
925 enum ieee80211_smps_mode smps_request)
926{
927 struct iwl_mvm_vif *mvmvif;
f6415f6b 928 enum ieee80211_smps_mode smps_mode;
9ee718aa
EL
929 int i;
930
931 lockdep_assert_held(&mvm->mutex);
710e4d08
EG
932
933 /* SMPS is irrelevant for NICs that don't have at least 2 RX antenna */
a0544272 934 if (num_of_ant(iwl_mvm_get_valid_rx_ant(mvm)) == 1)
710e4d08
EG
935 return;
936
f6415f6b
EG
937 if (vif->type == NL80211_IFTYPE_AP)
938 smps_mode = IEEE80211_SMPS_OFF;
939 else
940 smps_mode = IEEE80211_SMPS_AUTOMATIC;
941
9ee718aa
EL
942 mvmvif = iwl_mvm_vif_from_mac80211(vif);
943 mvmvif->smps_requests[req_type] = smps_request;
944 for (i = 0; i < NUM_IWL_MVM_SMPS_REQ; i++) {
945 if (mvmvif->smps_requests[i] == IEEE80211_SMPS_STATIC) {
946 smps_mode = IEEE80211_SMPS_STATIC;
947 break;
948 }
949 if (mvmvif->smps_requests[i] == IEEE80211_SMPS_DYNAMIC)
950 smps_mode = IEEE80211_SMPS_DYNAMIC;
951 }
952
953 ieee80211_request_smps(vif, smps_mode);
954}
a21d7bcb 955
33cef925 956int iwl_mvm_request_statistics(struct iwl_mvm *mvm, bool clear)
91a8bcde 957{
33cef925
JB
958 struct iwl_statistics_cmd scmd = {
959 .flags = clear ? cpu_to_le32(IWL_STATISTICS_FLG_CLEAR) : 0,
960 };
91a8bcde
JB
961 struct iwl_host_cmd cmd = {
962 .id = STATISTICS_CMD,
963 .len[0] = sizeof(scmd),
964 .data[0] = &scmd,
965 .flags = CMD_WANT_SKB,
966 };
967 int ret;
968
969 ret = iwl_mvm_send_cmd(mvm, &cmd);
970 if (ret)
971 return ret;
972
973 iwl_mvm_handle_rx_statistics(mvm, cmd.resp_pkt);
974 iwl_free_resp(&cmd);
975
33cef925
JB
976 if (clear)
977 iwl_mvm_accu_radio_stats(mvm);
978
91a8bcde
JB
979 return 0;
980}
981
982void iwl_mvm_accu_radio_stats(struct iwl_mvm *mvm)
983{
984 mvm->accu_radio_stats.rx_time += mvm->radio_stats.rx_time;
985 mvm->accu_radio_stats.tx_time += mvm->radio_stats.tx_time;
986 mvm->accu_radio_stats.on_time_rf += mvm->radio_stats.on_time_rf;
987 mvm->accu_radio_stats.on_time_scan += mvm->radio_stats.on_time_scan;
988}
989
5c904224
EG
990static void iwl_mvm_diversity_iter(void *_data, u8 *mac,
991 struct ieee80211_vif *vif)
992{
993 struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
994 bool *result = _data;
995 int i;
996
997 for (i = 0; i < NUM_IWL_MVM_SMPS_REQ; i++) {
998 if (mvmvif->smps_requests[i] == IEEE80211_SMPS_STATIC ||
999 mvmvif->smps_requests[i] == IEEE80211_SMPS_DYNAMIC)
1000 *result = false;
1001 }
1002}
1003
1004bool iwl_mvm_rx_diversity_allowed(struct iwl_mvm *mvm)
1005{
1006 bool result = true;
1007
1008 lockdep_assert_held(&mvm->mutex);
1009
a0544272 1010 if (num_of_ant(iwl_mvm_get_valid_rx_ant(mvm)) == 1)
5c904224
EG
1011 return false;
1012
c93edc63 1013 if (mvm->cfg->rx_with_siso_diversity)
5c904224
EG
1014 return false;
1015
1016 ieee80211_iterate_active_interfaces_atomic(
1017 mvm->hw, IEEE80211_IFACE_ITER_NORMAL,
1018 iwl_mvm_diversity_iter, &result);
1019
1020 return result;
1021}
1022
a21d7bcb 1023int iwl_mvm_update_low_latency(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
b525d081 1024 bool prev)
a21d7bcb
JB
1025{
1026 struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
e03f9bef 1027 int res;
a21d7bcb
JB
1028
1029 lockdep_assert_held(&mvm->mutex);
1030
b525d081 1031 if (iwl_mvm_vif_low_latency(mvmvif) == prev)
3510aea4
JB
1032 return 0;
1033
7754ae79 1034 res = iwl_mvm_update_quotas(mvm, false, NULL);
e03f9bef
JB
1035 if (res)
1036 return res;
0ee5bcdd
EG
1037
1038 iwl_mvm_bt_coex_vif_change(mvm);
1039
999609f1 1040 return iwl_mvm_power_update_mac(mvm);
a21d7bcb 1041}
50df8a30
AB
1042
1043static void iwl_mvm_ll_iter(void *_data, u8 *mac, struct ieee80211_vif *vif)
1044{
1045 bool *result = _data;
1046
1047 if (iwl_mvm_vif_low_latency(iwl_mvm_vif_from_mac80211(vif)))
1048 *result = true;
1049}
1050
1051bool iwl_mvm_low_latency(struct iwl_mvm *mvm)
1052{
1053 bool result = false;
1054
1055 ieee80211_iterate_active_interfaces_atomic(
1056 mvm->hw, IEEE80211_IFACE_ITER_NORMAL,
1057 iwl_mvm_ll_iter, &result);
1058
1059 return result;
1060}
bd5e4744 1061
7f549e2c
LC
1062struct iwl_bss_iter_data {
1063 struct ieee80211_vif *vif;
1064 bool error;
1065};
1066
1067static void iwl_mvm_bss_iface_iterator(void *_data, u8 *mac,
1068 struct ieee80211_vif *vif)
1069{
1070 struct iwl_bss_iter_data *data = _data;
1071
1072 if (vif->type != NL80211_IFTYPE_STATION || vif->p2p)
1073 return;
1074
1075 if (data->vif) {
1076 data->error = true;
1077 return;
1078 }
1079
1080 data->vif = vif;
1081}
1082
1083struct ieee80211_vif *iwl_mvm_get_bss_vif(struct iwl_mvm *mvm)
1084{
1085 struct iwl_bss_iter_data bss_iter_data = {};
1086
1087 ieee80211_iterate_active_interfaces_atomic(
1088 mvm->hw, IEEE80211_IFACE_ITER_NORMAL,
1089 iwl_mvm_bss_iface_iterator, &bss_iter_data);
1090
1091 if (bss_iter_data.error) {
1092 IWL_ERR(mvm, "More than one managed interface active!\n");
1093 return ERR_PTR(-EINVAL);
1094 }
1095
1096 return bss_iter_data.vif;
1097}
5d42e7b2 1098
d4a7e708
HD
1099struct iwl_sta_iter_data {
1100 bool assoc;
1101};
1102
1103static void iwl_mvm_sta_iface_iterator(void *_data, u8 *mac,
1104 struct ieee80211_vif *vif)
1105{
1106 struct iwl_sta_iter_data *data = _data;
1107
1108 if (vif->type != NL80211_IFTYPE_STATION)
1109 return;
1110
1111 if (vif->bss_conf.assoc)
1112 data->assoc = true;
1113}
1114
1115bool iwl_mvm_is_vif_assoc(struct iwl_mvm *mvm)
1116{
1117 struct iwl_sta_iter_data data = {
1118 .assoc = false,
1119 };
1120
1121 ieee80211_iterate_active_interfaces_atomic(mvm->hw,
1122 IEEE80211_IFACE_ITER_NORMAL,
1123 iwl_mvm_sta_iface_iterator,
1124 &data);
1125 return data.assoc;
1126}
1127
5d42e7b2
EG
1128unsigned int iwl_mvm_get_wd_timeout(struct iwl_mvm *mvm,
1129 struct ieee80211_vif *vif,
1130 bool tdls, bool cmd_q)
1131{
1132 struct iwl_fw_dbg_trigger_tlv *trigger;
1133 struct iwl_fw_dbg_trigger_txq_timer *txq_timer;
1134 unsigned int default_timeout =
1135 cmd_q ? IWL_DEF_WD_TIMEOUT : mvm->cfg->base_params->wd_timeout;
1136
0b9832b7
EG
1137 if (!iwl_fw_dbg_trigger_enabled(mvm->fw, FW_DBG_TRIGGER_TXQ_TIMERS)) {
1138 /*
1139 * We can't know when the station is asleep or awake, so we
1140 * must disable the queue hang detection.
1141 */
1142 if (fw_has_capa(&mvm->fw->ucode_capa,
1143 IWL_UCODE_TLV_CAPA_STA_PM_NOTIF) &&
1144 vif && vif->type == NL80211_IFTYPE_AP)
1145 return IWL_WATCHDOG_DISABLED;
5d42e7b2
EG
1146 return iwlmvm_mod_params.tfd_q_hang_detect ?
1147 default_timeout : IWL_WATCHDOG_DISABLED;
0b9832b7 1148 }
5d42e7b2
EG
1149
1150 trigger = iwl_fw_dbg_get_trigger(mvm->fw, FW_DBG_TRIGGER_TXQ_TIMERS);
1151 txq_timer = (void *)trigger->data;
1152
1153 if (tdls)
1154 return le32_to_cpu(txq_timer->tdls);
1155
1156 if (cmd_q)
1157 return le32_to_cpu(txq_timer->command_queue);
1158
1159 if (WARN_ON(!vif))
1160 return default_timeout;
1161
1162 switch (ieee80211_vif_type_p2p(vif)) {
1163 case NL80211_IFTYPE_ADHOC:
1164 return le32_to_cpu(txq_timer->ibss);
1165 case NL80211_IFTYPE_STATION:
1166 return le32_to_cpu(txq_timer->bss);
1167 case NL80211_IFTYPE_AP:
1168 return le32_to_cpu(txq_timer->softap);
1169 case NL80211_IFTYPE_P2P_CLIENT:
1170 return le32_to_cpu(txq_timer->p2p_client);
1171 case NL80211_IFTYPE_P2P_GO:
1172 return le32_to_cpu(txq_timer->p2p_go);
1173 case NL80211_IFTYPE_P2P_DEVICE:
1174 return le32_to_cpu(txq_timer->p2p_device);
d1b275ff
EG
1175 case NL80211_IFTYPE_MONITOR:
1176 return default_timeout;
5d42e7b2
EG
1177 default:
1178 WARN_ON(1);
1179 return mvm->cfg->base_params->wd_timeout;
1180 }
1181}
31755207
EG
1182
1183void iwl_mvm_connection_loss(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
1184 const char *errmsg)
1185{
1186 struct iwl_fw_dbg_trigger_tlv *trig;
1187 struct iwl_fw_dbg_trigger_mlme *trig_mlme;
1188
1189 if (!iwl_fw_dbg_trigger_enabled(mvm->fw, FW_DBG_TRIGGER_MLME))
1190 goto out;
1191
1192 trig = iwl_fw_dbg_get_trigger(mvm->fw, FW_DBG_TRIGGER_MLME);
1193 trig_mlme = (void *)trig->data;
7174beb6
JB
1194 if (!iwl_fw_dbg_trigger_check_stop(&mvm->fwrt,
1195 ieee80211_vif_to_wdev(vif), trig))
31755207
EG
1196 goto out;
1197
1198 if (trig_mlme->stop_connection_loss &&
1199 --trig_mlme->stop_connection_loss)
1200 goto out;
1201
7174beb6 1202 iwl_fw_dbg_collect_trig(&mvm->fwrt, trig, "%s", errmsg);
31755207
EG
1203
1204out:
1205 ieee80211_connection_loss(vif);
1206}
03098268 1207
9794c64f
LK
1208/*
1209 * Remove inactive TIDs of a given queue.
1210 * If all queue TIDs are inactive - mark the queue as inactive
1211 * If only some the queue TIDs are inactive - unmap them from the queue
1212 */
1213static void iwl_mvm_remove_inactive_tids(struct iwl_mvm *mvm,
1214 struct iwl_mvm_sta *mvmsta, int queue,
1215 unsigned long tid_bitmap)
1216{
1217 int tid;
1218
1219 lockdep_assert_held(&mvmsta->lock);
1220 lockdep_assert_held(&mvm->queue_info_lock);
1221
bb49701b
SS
1222 if (WARN_ON(iwl_mvm_has_new_tx_api(mvm)))
1223 return;
1224
9794c64f
LK
1225 /* Go over all non-active TIDs, incl. IWL_MAX_TID_COUNT (for mgmt) */
1226 for_each_set_bit(tid, &tid_bitmap, IWL_MAX_TID_COUNT + 1) {
1227 /* If some TFDs are still queued - don't mark TID as inactive */
dd32162d 1228 if (iwl_mvm_tid_queued(mvm, &mvmsta->tid_data[tid]))
9794c64f 1229 tid_bitmap &= ~BIT(tid);
59df97f7
EG
1230
1231 /* Don't mark as inactive any TID that has an active BA */
1232 if (mvmsta->tid_data[tid].state != IWL_AGG_OFF)
1233 tid_bitmap &= ~BIT(tid);
9794c64f
LK
1234 }
1235
1236 /* If all TIDs in the queue are inactive - mark queue as inactive. */
1237 if (tid_bitmap == mvm->queue_info[queue].tid_bitmap) {
1238 mvm->queue_info[queue].status = IWL_MVM_QUEUE_INACTIVE;
1239
1240 for_each_set_bit(tid, &tid_bitmap, IWL_MAX_TID_COUNT + 1)
1241 mvmsta->tid_data[tid].is_tid_active = false;
1242
1243 IWL_DEBUG_TX_QUEUES(mvm, "Queue %d marked as inactive\n",
1244 queue);
1245 return;
1246 }
1247
1248 /*
1249 * If we are here, this is a shared queue and not all TIDs timed-out.
1250 * Remove the ones that did.
1251 */
1252 for_each_set_bit(tid, &tid_bitmap, IWL_MAX_TID_COUNT + 1) {
1253 int mac_queue = mvmsta->vif->hw_queue[tid_to_mac80211_ac[tid]];
1254
6862fcee 1255 mvmsta->tid_data[tid].txq_id = IWL_MVM_INVALID_QUEUE;
34e10860 1256 mvm->hw_queue_to_mac80211[queue] &= ~BIT(mac_queue);
9794c64f
LK
1257 mvm->queue_info[queue].hw_queue_refcount--;
1258 mvm->queue_info[queue].tid_bitmap &= ~BIT(tid);
1259 mvmsta->tid_data[tid].is_tid_active = false;
1260
1261 IWL_DEBUG_TX_QUEUES(mvm,
1262 "Removing inactive TID %d from shared Q:%d\n",
1263 tid, queue);
1264 }
1265
1266 IWL_DEBUG_TX_QUEUES(mvm,
1267 "TXQ #%d left with tid bitmap 0x%x\n", queue,
1268 mvm->queue_info[queue].tid_bitmap);
1269
1270 /*
1271 * There may be different TIDs with the same mac queues, so make
1272 * sure all TIDs have existing corresponding mac queues enabled
1273 */
1274 tid_bitmap = mvm->queue_info[queue].tid_bitmap;
1275 for_each_set_bit(tid, &tid_bitmap, IWL_MAX_TID_COUNT + 1) {
34e10860 1276 mvm->hw_queue_to_mac80211[queue] |=
9794c64f
LK
1277 BIT(mvmsta->vif->hw_queue[tid_to_mac80211_ac[tid]]);
1278 }
1279
9f9af3d7
LK
1280 /* If the queue is marked as shared - "unshare" it */
1281 if (mvm->queue_info[queue].hw_queue_refcount == 1 &&
1282 mvm->queue_info[queue].status == IWL_MVM_QUEUE_SHARED) {
1283 mvm->queue_info[queue].status = IWL_MVM_QUEUE_RECONFIGURING;
1284 IWL_DEBUG_TX_QUEUES(mvm, "Marking Q:%d for reconfig\n",
1285 queue);
1286 }
9794c64f
LK
1287}
1288
1289void iwl_mvm_inactivity_check(struct iwl_mvm *mvm)
1290{
1291 unsigned long timeout_queues_map = 0;
1292 unsigned long now = jiffies;
1293 int i;
1294
bb49701b
SS
1295 if (iwl_mvm_has_new_tx_api(mvm))
1296 return;
1297
9794c64f
LK
1298 spin_lock_bh(&mvm->queue_info_lock);
1299 for (i = 0; i < IWL_MAX_HW_QUEUES; i++)
1300 if (mvm->queue_info[i].hw_queue_refcount > 0)
1301 timeout_queues_map |= BIT(i);
1302 spin_unlock_bh(&mvm->queue_info_lock);
1303
1304 rcu_read_lock();
1305
1306 /*
1307 * If a queue time outs - mark it as INACTIVE (don't remove right away
1308 * if we don't have to.) This is an optimization in case traffic comes
1309 * later, and we don't HAVE to use a currently-inactive queue
1310 */
1311 for_each_set_bit(i, &timeout_queues_map, IWL_MAX_HW_QUEUES) {
1312 struct ieee80211_sta *sta;
1313 struct iwl_mvm_sta *mvmsta;
1314 u8 sta_id;
1315 int tid;
1316 unsigned long inactive_tid_bitmap = 0;
1317 unsigned long queue_tid_bitmap;
1318
1319 spin_lock_bh(&mvm->queue_info_lock);
1320 queue_tid_bitmap = mvm->queue_info[i].tid_bitmap;
1321
1322 /* If TXQ isn't in active use anyway - nothing to do here... */
42db09c1
LK
1323 if (mvm->queue_info[i].status != IWL_MVM_QUEUE_READY &&
1324 mvm->queue_info[i].status != IWL_MVM_QUEUE_SHARED) {
9794c64f
LK
1325 spin_unlock_bh(&mvm->queue_info_lock);
1326 continue;
1327 }
1328
1329 /* Check to see if there are inactive TIDs on this queue */
1330 for_each_set_bit(tid, &queue_tid_bitmap,
1331 IWL_MAX_TID_COUNT + 1) {
1332 if (time_after(mvm->queue_info[i].last_frame_time[tid] +
1333 IWL_MVM_DQA_QUEUE_TIMEOUT, now))
1334 continue;
1335
1336 inactive_tid_bitmap |= BIT(tid);
1337 }
1338 spin_unlock_bh(&mvm->queue_info_lock);
1339
1340 /* If all TIDs are active - finish check on this queue */
1341 if (!inactive_tid_bitmap)
1342 continue;
1343
1344 /*
1345 * If we are here - the queue hadn't been served recently and is
1346 * in use
1347 */
1348
1349 sta_id = mvm->queue_info[i].ra_sta_id;
1350 sta = rcu_dereference(mvm->fw_id_to_mac_id[sta_id]);
1351
1352 /*
1353 * If the STA doesn't exist anymore, it isn't an error. It could
1354 * be that it was removed since getting the queues, and in this
1355 * case it should've inactivated its queues anyway.
1356 */
1357 if (IS_ERR_OR_NULL(sta))
1358 continue;
1359
1360 mvmsta = iwl_mvm_sta_from_mac80211(sta);
1361
1362 spin_lock_bh(&mvmsta->lock);
1363 spin_lock(&mvm->queue_info_lock);
1364 iwl_mvm_remove_inactive_tids(mvm, mvmsta, i,
1365 inactive_tid_bitmap);
1366 spin_unlock(&mvm->queue_info_lock);
1367 spin_unlock_bh(&mvmsta->lock);
1368 }
1369
1370 rcu_read_unlock();
1371}
1372
528a542a
EG
1373void iwl_mvm_event_frame_timeout_callback(struct iwl_mvm *mvm,
1374 struct ieee80211_vif *vif,
1375 const struct ieee80211_sta *sta,
1376 u16 tid)
1377{
1378 struct iwl_fw_dbg_trigger_tlv *trig;
1379 struct iwl_fw_dbg_trigger_ba *ba_trig;
1380
1381 if (!iwl_fw_dbg_trigger_enabled(mvm->fw, FW_DBG_TRIGGER_BA))
1382 return;
1383
1384 trig = iwl_fw_dbg_get_trigger(mvm->fw, FW_DBG_TRIGGER_BA);
1385 ba_trig = (void *)trig->data;
1386 if (!iwl_fw_dbg_trigger_check_stop(&mvm->fwrt,
1387 ieee80211_vif_to_wdev(vif), trig))
1388 return;
1389
1390 if (!(le16_to_cpu(ba_trig->frame_timeout) & BIT(tid)))
1391 return;
1392
1393 iwl_fw_dbg_collect_trig(&mvm->fwrt, trig,
1394 "Frame from %pM timed out, tid %d",
1395 sta->addr, tid);
1396}
1397
b3bee580
RZ
1398void iwl_mvm_get_sync_time(struct iwl_mvm *mvm, u32 *gp2, u64 *boottime)
1399{
1400 bool ps_disabled;
1401
1402 lockdep_assert_held(&mvm->mutex);
1403
1404 /* Disable power save when reading GP2 */
1405 ps_disabled = mvm->ps_disabled;
1406 if (!ps_disabled) {
1407 mvm->ps_disabled = true;
1408 iwl_mvm_power_update_device(mvm);
1409 }
1410
1411 *gp2 = iwl_read_prph(mvm->trans, DEVICE_SYSTEM_TIME_REG);
1412 *boottime = ktime_get_boot_ns();
1413
1414 if (!ps_disabled) {
1415 mvm->ps_disabled = ps_disabled;
1416 iwl_mvm_power_update_device(mvm);
1417 }
1418}