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Merge remote-tracking branches 'asoc/topic/atmel', 'asoc/topic/bcm2835' and 'asoc...
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 10 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
62d7476d 37 * Copyright(c) 2016 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
e6bb4c9c 75
82575102 76#include "iwl-drv.h"
c85eb619 77#include "iwl-trans.h"
522376d2
EG		 78#include "iwl-csr.h"
79#include "iwl-prph.h"
cb6bb128 80#include "iwl-scd.h"
7a10e3e4 81#include "iwl-agn-hw.h"
4d075007 82#include "iwl-fw-error-dump.h"
6468a01a 83#include "internal.h"
06d51e0d 84#include "iwl-fh.h"
0439bb62 85
fe45773b
AN		 86/* extended range in FW SRAM */
87#define IWL_FW_MEM_EXTENDED_START 0x40000
88#define IWL_FW_MEM_EXTENDED_END 0x57FFF
89
c2d20201
EG		 90static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
91{
92 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
93
94 if (!trans_pcie->fw_mon_page)
95 return;
96
97 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
98 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
99 __free_pages(trans_pcie->fw_mon_page,
100 get_order(trans_pcie->fw_mon_size));
101 trans_pcie->fw_mon_page = NULL;
102 trans_pcie->fw_mon_phys = 0;
103 trans_pcie->fw_mon_size = 0;
104}
105
96c285da 106static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 107{
108 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 109 struct page *page = NULL;
c2d20201 110 dma_addr_t phys;
96c285da 111 u32 size = 0;
c2d20201
EG		 112 u8 power;
113
96c285da
EG		 114 if (!max_power) {
115 /* default max_power is maximum */
116 max_power = 26;
117 } else {
118 max_power += 11;
119 }
120
121 if (WARN(max_power > 26,
122 "External buffer size for monitor is too big %d, check the FW TLV\n",
123 max_power))
124 return;
125
c2d20201
EG		 126 if (trans_pcie->fw_mon_page) {
127 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
128 trans_pcie->fw_mon_size,
129 DMA_FROM_DEVICE);
130 return;
131 }
132
133 phys = 0;
96c285da 134 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 135 int order;
136
137 size = BIT(power);
138 order = get_order(size);
139 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
140 order);
141 if (!page)
142 continue;
143
144 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
145 DMA_FROM_DEVICE);
146 if (dma_mapping_error(trans->dev, phys)) {
147 __free_pages(page, order);
553452e5 148 page = NULL;
c2d20201
EG		 149 continue;
150 }
151 IWL_INFO(trans,
152 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
153 size, order);
154 break;
155 }
156
40a76905 157 if (WARN_ON_ONCE(!page))
c2d20201
EG		 158 return;
159
96c285da
EG		 160 if (power != max_power)
161 IWL_ERR(trans,
162 "Sorry - debug buffer is only %luK while you requested %luK\n",
163 (unsigned long)BIT(power - 10),
164 (unsigned long)BIT(max_power - 10));
165
c2d20201
EG		 166 trans_pcie->fw_mon_page = page;
167 trans_pcie->fw_mon_phys = phys;
168 trans_pcie->fw_mon_size = size;
169}
170
a812cba9
AB		 171static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
172{
173 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
174 ((reg & 0x0000ffff) | (2 << 28)));
175 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
176}
177
178static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
179{
180 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
182 ((reg & 0x0000ffff) | (3 << 28)));
183}
184
ddaf5a5b 185static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 186{
66337b7c 187 if (trans->cfg->apmg_not_supported)
95411d04
AA		 188 return;
189
ddaf5a5b
JB		 190 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
191 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
192 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
193 ~APMG_PS_CTRL_MSK_PWR_SRC);
194 else
195 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
196 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
197 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 198}
199
af634bee
EG		 200/* PCI registers */
201#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 202
7afe3705 203static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 204{
20d3b647 205 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 206 u16 lctl;
9180ac50 207 u16 cap;
af634bee 208
af634bee
EG		 209 /*
210 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
211 * Check if BIOS (or OS) enabled L1-ASPM on this device.
212 * If so (likely), disable L0S, so device moves directly L0->L1;
213 * costs negligible amount of power savings.
214 * If not (unlikely), enable L0S, so there is at least some
215 * power savings, even without L1.
216 */
7afe3705 217 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 218 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 219 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 220 else
af634bee 221 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 222 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 223
224 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
225 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
226 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
227 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
228 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 229}
230
a6c684ee
EG		 231/*
232 * Start up NIC's basic functionality after it has been reset
7afe3705 233 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 234 * NOTE: This does not load uCode nor start the embedded processor
235 */
7afe3705 236static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 237{
238 int ret = 0;
239 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
240
241 /*
242 * Use "set_bit" below rather than "write", to preserve any hardware
243 * bits already set by default after reset.
244 */
245
246 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 247 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
248 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
249 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 250
251 /*
252 * Disable L0s without affecting L1;
253 * don't wait for ICH L0s (ICH bug W/A)
254 */
255 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 256 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 257
258 /* Set FH wait threshold to maximum (HW error during stress W/A) */
259 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
260
261 /*
262 * Enable HAP INTA (interrupt from management bus) to
263 * wake device's PCI Express link L1a -> L0s
264 */
265 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 266 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 267
7afe3705 268 iwl_pcie_apm_config(trans);
a6c684ee
EG		 269
270 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 271 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 272 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 273 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
2d93aee1
EG		 294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
a6c684ee
EG		 316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
3073d8c0
EH		 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 322 */
95411d04 323 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
889b1696 336
eb7ff77e 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 338
339out:
340 return ret;
341}
342
a812cba9
AB		 343/*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
350static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351{
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
363
364 udelay(10);
365
366 /*
367 * Set "initialization complete" bit to move adapter from
368 * D0U* --> D0A* (powered-up active) state.
369 */
370 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
371
372 /*
373 * Wait for clock stabilization; once stabilized, access to
374 * device-internal resources is possible.
375 */
376 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
379 25000);
380 if (WARN_ON(ret < 0)) {
381 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
382 /* Release XTAL ON request */
383 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
384 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
385 return;
386 }
387
388 /*
389 * Clear "disable persistence" to avoid LP XTAL resetting when
390 * SHRD_HW_RST is applied in S3.
391 */
392 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
393 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
394
395 /*
396 * Force APMG XTAL to be active to prevent its disabling by HW
397 * caused by APMG idle state.
398 */
399 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
400 SHR_APMG_XTAL_CFG_REG);
401 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
402 apmg_xtal_cfg_reg |
403 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
404
405 /*
406 * Reset entire device again - do controller reset (results in
407 * SHRD_HW_RST). Turn MAC off before proceeding.
408 */
409 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
410
411 udelay(10);
412
413 /* Enable LP XTAL by indirect access through CSR */
414 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
415 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
416 SHR_APMG_GP1_WF_XTAL_LP_EN |
417 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
418
419 /* Clear delay line clock power up */
420 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
421 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
422 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
423
424 /*
425 * Enable persistence mode to avoid LP XTAL resetting when
426 * SHRD_HW_RST is applied in S3.
427 */
428 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
429 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
430
431 /*
432 * Clear "initialization complete" bit to move adapter from
433 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
434 */
435 iwl_clear_bit(trans, CSR_GP_CNTRL,
436 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
437
438 /* Activates XTAL resources monitor */
439 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
440 CSR_MONITOR_XTAL_RESOURCES);
441
442 /* Release XTAL ON request */
443 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
444 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
445 udelay(10);
446
447 /* Release APMG XTAL */
448 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
449 apmg_xtal_cfg_reg &
450 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
451}
452
7afe3705 453static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 454{
455 int ret = 0;
456
457 /* stop device's busmaster DMA activity */
458 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
459
460 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 461 CSR_RESET_REG_FLAG_MASTER_DISABLED,
462 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 463 if (ret < 0)
cc56feb2
EG		 464 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
465
466 IWL_DEBUG_INFO(trans, "stop master\n");
467
468 return ret;
469}
470
b7aaeae4 471static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 472{
473 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
474
b7aaeae4
EG		 475 if (op_mode_leave) {
476 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
477 iwl_pcie_apm_init(trans);
478
479 /* inform ME that we are leaving */
480 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
481 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
482 APMG_PCIDEV_STT_VAL_WAKE_ME);
c9fdec9f
EG		 483 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
484 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
485 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 486 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
487 CSR_HW_IF_CONFIG_REG_PREPARE |
488 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 489 mdelay(1);
490 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
491 CSR_RESET_LINK_PWR_MGMT_DISABLED);
492 }
b7aaeae4
EG		 493 mdelay(5);
494 }
495
eb7ff77e 496 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 497
498 /* Stop device's DMA activity */
7afe3705 499 iwl_pcie_apm_stop_master(trans);
cc56feb2 500
a812cba9
AB		 501 if (trans->cfg->lp_xtal_workaround) {
502 iwl_pcie_apm_lp_xtal_enable(trans);
503 return;
504 }
505
cc56feb2
EG		 506 /* Reset the entire device */
507 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
508
509 udelay(10);
510
511 /*
512 * Clear "initialization complete" bit to move adapter from
513 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
514 */
515 iwl_clear_bit(trans, CSR_GP_CNTRL,
516 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
517}
518
7afe3705 519static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 520{
7b11488f 521 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 522
523 /* nic_init */
7b70bd63 524 spin_lock(&trans_pcie->irq_lock);
7afe3705 525 iwl_pcie_apm_init(trans);
392f8b78 526
7b70bd63 527 spin_unlock(&trans_pcie->irq_lock);
392f8b78 528
95411d04 529 iwl_pcie_set_pwr(trans, false);
392f8b78 530
ecdb975c 531 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 532
533 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 534 iwl_pcie_rx_init(trans);
392f8b78
EG		 535
536 /* Allocate or reset and init all Tx and Command queues */
f02831be 537 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 538 return -ENOMEM;
539
035f7ff2 540 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 541 /* enable shadow regs in HW */
20d3b647 542 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 543 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 544 }
545
392f8b78
EG		 546 return 0;
547}
548
549#define HW_READY_TIMEOUT (50)
550
551/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 552static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 553{
554 int ret;
555
1042db2a 556 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 557 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 558
559 /* See if we got it */
1042db2a 560 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 561 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
562 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
563 HW_READY_TIMEOUT);
392f8b78 564
6a08f514
EG		 565 if (ret >= 0)
566 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
567
6d8f6eeb 568 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 569 return ret;
570}
571
572/* Note: returns standard 0/-ERROR code */
7afe3705 573static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 574{
575 int ret;
289e5501 576 int t = 0;
501fd989 577 int iter;
392f8b78 578
6d8f6eeb 579 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 580
7afe3705 581 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 582 /* If the card is ready, exit 0 */
392f8b78
EG		 583 if (ret >= 0)
584 return 0;
585
c9fdec9f
EG		 586 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
587 CSR_RESET_LINK_PWR_MGMT_DISABLED);
588 msleep(1);
589
501fd989
EG		 590 for (iter = 0; iter < 10; iter++) {
591 /* If HW is not ready, prepare the conditions to check again */
592 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
593 CSR_HW_IF_CONFIG_REG_PREPARE);
594
595 do {
596 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 597 if (ret >= 0)
598 return 0;
392f8b78 599
501fd989
EG		 600 usleep_range(200, 1000);
601 t += 200;
602 } while (t < 150000);
603 msleep(25);
604 }
392f8b78 605
7f2ac8fb 606 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 607
392f8b78
EG		 608 return ret;
609}
610
cf614297
EG		 611/*
612 * ucode
613 */
7afe3705 614static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 615 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 616{
13df1aab 617 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 618 int ret;
619
13df1aab 620 trans_pcie->ucode_write_complete = false;
cf614297
EG		 621
622 iwl_write_direct32(trans,
20d3b647
JB		 623 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
624 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 625
626 iwl_write_direct32(trans,
20d3b647
JB		 627 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
628 dst_addr);
cf614297
EG		 629
630 iwl_write_direct32(trans,
83f84d7b
JB		 631 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
632 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 633
634 iwl_write_direct32(trans,
20d3b647
JB		 635 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
636 (iwl_get_dma_hi_addr(phy_addr)
637 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 638
639 iwl_write_direct32(trans,
20d3b647
JB		 640 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
641 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
642 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
643 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 644
645 iwl_write_direct32(trans,
20d3b647
JB		 646 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
647 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
648 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
649 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 650
13df1aab
JB		 651 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
652 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 653 if (!ret) {
83f84d7b 654 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 655 return -ETIMEDOUT;
656 }
657
658 return 0;
659}
660
7afe3705 661static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 662 const struct fw_desc *section)
cf614297 663{
83f84d7b
JB		 664 u8 *v_addr;
665 dma_addr_t p_addr;
baa21e83 666 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 667 int ret = 0;
668
83f84d7b
JB		 669 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
670 section_num);
671
c571573a
EG		 672 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
673 GFP_KERNEL | __GFP_NOWARN);
674 if (!v_addr) {
675 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
676 chunk_sz = PAGE_SIZE;
677 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
678 &p_addr, GFP_KERNEL);
679 if (!v_addr)
680 return -ENOMEM;
681 }
83f84d7b 682
c571573a 683 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 684 u32 copy_size, dst_addr;
685 bool extended_addr = false;
83f84d7b 686
c571573a 687 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 688 dst_addr = section->offset + offset;
689
690 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
691 dst_addr <= IWL_FW_MEM_EXTENDED_END)
692 extended_addr = true;
693
694 if (extended_addr)
695 iwl_set_bits_prph(trans, LMPM_CHICK,
696 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 697
83f84d7b 698 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 699 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
700 copy_size);
701
702 if (extended_addr)
703 iwl_clear_bits_prph(trans, LMPM_CHICK,
704 LMPM_CHICK_EXTENDED_ADDR_SPACE);
705
83f84d7b
JB		 706 if (ret) {
707 IWL_ERR(trans,
708 "Could not load the [%d] uCode section\n",
709 section_num);
710 break;
6dfa8d01 711 }
83f84d7b
JB		 712 }
713
c571573a 714 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 715 return ret;
716}
717
16bc119b
EH		 718/*
719 * Driver Takes the ownership on secure machine before FW load
720 * and prevent race with the BT load.
721 * W/A for ROM bug. (should be remove in the next Si step)
722 */
723static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
724{
725 u32 val, loop = 1000;
726
1e167071
EH		 727 /*
728 * Check the RSA semaphore is accessible.
729 * If the HW isn't locked and the rsa semaphore isn't accessible,
730 * we are in trouble.
731 */
16bc119b
EH		 732 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
733 if (val & (BIT(1) | BIT(17))) {
1e167071
EH		 734 IWL_INFO(trans,
735 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 736 return 0;
737 }
738
739 /* take ownership on the AUX IF */
740 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
741 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
742
743 do {
744 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
745 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
746 if (val == 0x1) {
747 iwl_write_prph(trans, RSA_ENABLE, 0);
748 return 0;
749 }
750
751 udelay(10);
752 loop--;
753 } while (loop > 0);
754
755 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
756 return -EIO;
757}
758
5dd9c68a
EG		 759static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
760 const struct fw_img *image,
761 int cpu,
762 int *first_ucode_section)
e2d6f4e7
EH		 763{
764 int shift_param;
dcab8ecd
EH		 765 int i, ret = 0, sec_num = 0x1;
766 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 767
768 if (cpu == 1) {
769 shift_param = 0;
034846cf 770 *first_ucode_section = 0;
e2d6f4e7
EH		 771 } else {
772 shift_param = 16;
034846cf 773 (*first_ucode_section)++;
e2d6f4e7
EH		 774 }
775
034846cf
EH		 776 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
777 last_read_idx = i;
778
a6c4fb44
MG		 779 /*
780 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
781 * CPU1 to CPU2.
782 * PAGING_SEPARATOR_SECTION delimiter - separate between
783 * CPU2 non paged to CPU2 paging sec.
784 */
034846cf 785 if (!image->sec[i].data ||
a6c4fb44
MG		 786 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
787 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 788 IWL_DEBUG_FW(trans,
789 "Break since Data not valid or Empty section, sec = %d\n",
790 i);
189fa2fa 791 break;
034846cf
EH		 792 }
793
189fa2fa
EH		 794 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
795 if (ret)
796 return ret;
dcab8ecd
EH		 797
798 /* Notify the ucode of the loaded section number and status */
799 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
800 val = val | (sec_num << shift_param);
801 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
802 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 803 }
804
034846cf
EH		 805 *first_ucode_section = last_read_idx;
806
afb88917
EH		 807 if (cpu == 1)
808 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
809 else
810 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
811
189fa2fa
EH		 812 return 0;
813}
e2d6f4e7 814
189fa2fa
EH		 815static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
816 const struct fw_img *image,
034846cf
EH		 817 int cpu,
818 int *first_ucode_section)
189fa2fa
EH		 819{
820 int shift_param;
189fa2fa 821 int i, ret = 0;
034846cf 822 u32 last_read_idx = 0;
189fa2fa
EH		 823
824 if (cpu == 1) {
825 shift_param = 0;
034846cf 826 *first_ucode_section = 0;
189fa2fa
EH		 827 } else {
828 shift_param = 16;
034846cf 829 (*first_ucode_section)++;
189fa2fa
EH		 830 }
831
034846cf
EH		 832 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
833 last_read_idx = i;
834
a6c4fb44
MG		 835 /*
836 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
837 * CPU1 to CPU2.
838 * PAGING_SEPARATOR_SECTION delimiter - separate between
839 * CPU2 non paged to CPU2 paging sec.
840 */
034846cf 841 if (!image->sec[i].data ||
a6c4fb44
MG		 842 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
843 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 844 IWL_DEBUG_FW(trans,
845 "Break since Data not valid or Empty section, sec = %d\n",
846 i);
189fa2fa 847 break;
034846cf
EH		 848 }
849
189fa2fa
EH		 850 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
851 if (ret)
852 return ret;
e2d6f4e7
EH		 853 }
854
189fa2fa
EH		 855 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
856 iwl_set_bits_prph(trans,
857 CSR_UCODE_LOAD_STATUS_ADDR,
858 (LMPM_CPU_UCODE_LOADING_COMPLETED |
859 LMPM_CPU_HDRS_LOADING_COMPLETED |
860 LMPM_CPU_UCODE_LOADING_STARTED) <<
861 shift_param);
862
034846cf
EH		 863 *first_ucode_section = last_read_idx;
864
e2d6f4e7
EH		 865 return 0;
866}
867
09e350f7
LK		 868static void iwl_pcie_apply_destination(struct iwl_trans *trans)
869{
870 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
871 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
872 int i;
873
874 if (dest->version)
875 IWL_ERR(trans,
876 "DBG DEST version is %d - expect issues\n",
877 dest->version);
878
879 IWL_INFO(trans, "Applying debug destination %s\n",
880 get_fw_dbg_mode_string(dest->monitor_mode));
881
882 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 883 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 884 else
885 IWL_WARN(trans, "PCI should have external buffer debug\n");
886
887 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
888 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
889 u32 val = le32_to_cpu(dest->reg_ops[i].val);
890
891 switch (dest->reg_ops[i].op) {
892 case CSR_ASSIGN:
893 iwl_write32(trans, addr, val);
894 break;
895 case CSR_SETBIT:
896 iwl_set_bit(trans, addr, BIT(val));
897 break;
898 case CSR_CLEARBIT:
899 iwl_clear_bit(trans, addr, BIT(val));
900 break;
901 case PRPH_ASSIGN:
902 iwl_write_prph(trans, addr, val);
903 break;
904 case PRPH_SETBIT:
905 iwl_set_bits_prph(trans, addr, BIT(val));
906 break;
907 case PRPH_CLEARBIT:
908 iwl_clear_bits_prph(trans, addr, BIT(val));
909 break;
869f3b15
HD		 910 case PRPH_BLOCKBIT:
911 if (iwl_read_prph(trans, addr) & BIT(val)) {
912 IWL_ERR(trans,
913 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
914 val, addr);
915 goto monitor;
916 }
917 break;
09e350f7
LK		 918 default:
919 IWL_ERR(trans, "FW debug - unknown OP %d\n",
920 dest->reg_ops[i].op);
921 break;
922 }
923 }
924
869f3b15 925monitor:
09e350f7
LK		 926 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
927 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
928 trans_pcie->fw_mon_phys >> dest->base_shift);
62d7476d
EG		 929 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
930 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
931 (trans_pcie->fw_mon_phys +
932 trans_pcie->fw_mon_size - 256) >>
933 dest->end_shift);
934 else
935 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
936 (trans_pcie->fw_mon_phys +
937 trans_pcie->fw_mon_size) >>
938 dest->end_shift);
09e350f7
LK		 939 }
940}
941
7afe3705 942static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 943 const struct fw_img *image)
cf614297 944{
c2d20201 945 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 946 int ret = 0;
034846cf 947 int first_ucode_section;
cf614297 948
dcab8ecd 949 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 950 image->is_dual_cpus ? "Dual" : "Single");
951
dcab8ecd
EH		 952 /* load to FW the binary non secured sections of CPU1 */
953 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
954 if (ret)
955 return ret;
e2d6f4e7
EH		 956
957 if (image->is_dual_cpus) {
189fa2fa
EH		 958 /* set CPU2 header address */
959 iwl_write_prph(trans,
960 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
961 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 962
189fa2fa 963 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 964 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
965 &first_ucode_section);
189fa2fa
EH		 966 if (ret)
967 return ret;
e2d6f4e7 968 }
cf614297 969
c2d20201
EG		 970 /* supported for 7000 only for the moment */
971 if (iwlwifi_mod_params.fw_monitor &&
972 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 973 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 974
975 if (trans_pcie->fw_mon_size) {
976 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
977 trans_pcie->fw_mon_phys >> 4);
978 iwl_write_prph(trans, MON_BUFF_END_ADDR,
979 (trans_pcie->fw_mon_phys +
980 trans_pcie->fw_mon_size) >> 4);
981 }
09e350f7
LK		 982 } else if (trans->dbg_dest_tlv) {
983 iwl_pcie_apply_destination(trans);
c2d20201
EG		 984 }
985
e12ba844 986 /* release CPU reset */
5dd9c68a 987 iwl_write32(trans, CSR_RESET, 0);
e12ba844 988
dcab8ecd
EH		 989 return 0;
990}
189fa2fa 991
5dd9c68a
EG		 992static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
993 const struct fw_img *image)
dcab8ecd
EH		 994{
995 int ret = 0;
996 int first_ucode_section;
dcab8ecd
EH		 997
998 IWL_DEBUG_FW(trans, "working with %s CPU\n",
999 image->is_dual_cpus ? "Dual" : "Single");
1000
a2227ce2
EG		 1001 if (trans->dbg_dest_tlv)
1002 iwl_pcie_apply_destination(trans);
1003
16bc119b
EH		 1004 /* TODO: remove in the next Si step */
1005 ret = iwl_pcie_rsa_race_bug_wa(trans);
1006 if (ret)
1007 return ret;
1008
dcab8ecd
EH		 1009 /* configure the ucode to be ready to get the secured image */
1010 /* release CPU reset */
1011 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1012
1013 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1014 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1015 &first_ucode_section);
dcab8ecd
EH		 1016 if (ret)
1017 return ret;
1018
1019 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1020 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1021 &first_ucode_section);
cf614297
EG		 1022}
1023
fa9f3281 1024static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1025{
43e58856 1026 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1027 bool hw_rfkill, was_hw_rfkill;
1028
fa9f3281
EG		 1029 lockdep_assert_held(&trans_pcie->mutex);
1030
1031 if (trans_pcie->is_down)
1032 return;
1033
1034 trans_pcie->is_down = true;
1035
3dc3374f 1036 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1037
43e58856 1038 /* tell the device to stop sending interrupts */
7b70bd63 1039 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1040 iwl_disable_interrupts(trans);
7b70bd63 1041 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1042
ab6cf8e8 1043 /* device going down, Stop using ICT table */
990aa6d7 1044 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1045
1046 /*
1047 * If a HW restart happens during firmware loading,
1048 * then the firmware loading might call this function
1049 * and later it might be called again due to the
1050 * restart. So don't process again if the device is
1051 * already dead.
1052 */
31b8b343 1053 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1054 IWL_DEBUG_INFO(trans,
1055 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1056 iwl_pcie_tx_stop(trans);
9805c446 1057 iwl_pcie_rx_stop(trans);
6379103e 1058
ab6cf8e8 1059 /* Power-down device's busmaster DMA clocks */
95411d04 1060 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1061 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1062 APMG_CLK_VAL_DMA_CLK_RQT);
1063 udelay(5);
1064 }
ab6cf8e8
EG		 1065 }
1066
1067 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1068 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1069 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1070
1071 /* Stop the device, and put it in low power state */
b7aaeae4 1072 iwl_pcie_apm_stop(trans, false);
43e58856 1073
03d6c3b0
EG		 1074 /* stop and reset the on-board processor */
1075 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1076 udelay(20);
1077
1078 /*
1079 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1080 * This is a bug in certain verions of the hardware.
1081 * Certain devices also keep sending HW RF kill interrupt all
1082 * the time, unless the interrupt is ACKed even if the interrupt
1083 * should be masked. Re-ACK all the interrupts here.
43e58856 1084 */
7b70bd63 1085 spin_lock(&trans_pcie->irq_lock);
43e58856 1086 iwl_disable_interrupts(trans);
7b70bd63 1087 spin_unlock(&trans_pcie->irq_lock);
43e58856 1088
74fda971 1089 /* clear all status bits */
eb7ff77e
AN		 1090 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1091 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1092 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1093 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1094
1095 /*
1096 * Even if we stop the HW, we still want the RF kill
1097 * interrupt
1098 */
1099 iwl_enable_rfkill_int(trans);
1100
1101 /*
1102 * Check again since the RF kill state may have changed while
1103 * all the interrupts were disabled, in this case we couldn't
1104 * receive the RF kill interrupt and update the state in the
1105 * op_mode.
3dc3374f
EG		 1106 * Don't call the op_mode if the rkfill state hasn't changed.
1107 * This allows the op_mode to call stop_device from the rfkill
1108 * notification without endless recursion. Under very rare
1109 * circumstances, we might have a small recursion if the rfkill
1110 * state changed exactly now while we were called from stop_device.
1111 * This is very unlikely but can happen and is supported.
a4082843
AN		 1112 */
1113 hw_rfkill = iwl_is_rfkill_set(trans);
1114 if (hw_rfkill)
eb7ff77e 1115 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1116 else
eb7ff77e 1117 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1118 if (hw_rfkill != was_hw_rfkill)
14cfca71 1119 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0 1120
a6bd005f 1121 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1122 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1123}
1124
a6bd005f
EG		 1125static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1126 const struct fw_img *fw, bool run_in_rfkill)
1127{
1128 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1129 bool hw_rfkill;
1130 int ret;
1131
1132 /* This may fail if AMT took ownership of the device */
1133 if (iwl_pcie_prepare_card_hw(trans)) {
1134 IWL_WARN(trans, "Exit HW not ready\n");
1135 ret = -EIO;
1136 goto out;
1137 }
1138
1139 iwl_enable_rfkill_int(trans);
1140
1141 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1142
1143 /*
1144 * We enabled the RF-Kill interrupt and the handler may very
1145 * well be running. Disable the interrupts to make sure no other
1146 * interrupt can be fired.
1147 */
1148 iwl_disable_interrupts(trans);
1149
1150 /* Make sure it finished running */
1151 synchronize_irq(trans_pcie->pci_dev->irq);
1152
1153 mutex_lock(&trans_pcie->mutex);
1154
1155 /* If platform's RF_KILL switch is NOT set to KILL */
1156 hw_rfkill = iwl_is_rfkill_set(trans);
1157 if (hw_rfkill)
1158 set_bit(STATUS_RFKILL, &trans->status);
1159 else
1160 clear_bit(STATUS_RFKILL, &trans->status);
1161 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1162 if (hw_rfkill && !run_in_rfkill) {
1163 ret = -ERFKILL;
1164 goto out;
1165 }
1166
1167 /* Someone called stop_device, don't try to start_fw */
1168 if (trans_pcie->is_down) {
1169 IWL_WARN(trans,
1170 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1171 ret = -EIO;
a6bd005f
EG		 1172 goto out;
1173 }
1174
1175 /* make sure rfkill handshake bits are cleared */
1176 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1177 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1178 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1179
1180 /* clear (again), then enable host interrupts */
1181 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1182
1183 ret = iwl_pcie_nic_init(trans);
1184 if (ret) {
1185 IWL_ERR(trans, "Unable to init nic\n");
1186 goto out;
1187 }
1188
1189 /*
1190 * Now, we load the firmware and don't want to be interrupted, even
1191 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1192 * FH_TX interrupt which is needed to load the firmware). If the
1193 * RF-Kill switch is toggled, we will find out after having loaded
1194 * the firmware and return the proper value to the caller.
1195 */
1196 iwl_enable_fw_load_int(trans);
1197
1198 /* really make sure rfkill handshake bits are cleared */
1199 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1200 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1201
1202 /* Load the given image to the HW */
1203 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1204 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1205 else
1206 ret = iwl_pcie_load_given_ucode(trans, fw);
1207 iwl_enable_interrupts(trans);
1208
1209 /* re-check RF-Kill state since we may have missed the interrupt */
1210 hw_rfkill = iwl_is_rfkill_set(trans);
1211 if (hw_rfkill)
1212 set_bit(STATUS_RFKILL, &trans->status);
1213 else
1214 clear_bit(STATUS_RFKILL, &trans->status);
1215
1216 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1217 if (hw_rfkill && !run_in_rfkill)
1218 ret = -ERFKILL;
1219
1220out:
1221 mutex_unlock(&trans_pcie->mutex);
1222 return ret;
1223}
1224
1225static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1226{
1227 iwl_pcie_reset_ict(trans);
1228 iwl_pcie_tx_start(trans, scd_addr);
1229}
1230
fa9f3281
EG		 1231static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1232{
1233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1234
1235 mutex_lock(&trans_pcie->mutex);
1236 _iwl_trans_pcie_stop_device(trans, low_power);
1237 mutex_unlock(&trans_pcie->mutex);
1238}
1239
14cfca71
JB		 1240void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1241{
fa9f3281
EG		 1242 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1243 IWL_TRANS_GET_PCIE_TRANS(trans);
1244
1245 lockdep_assert_held(&trans_pcie->mutex);
1246
14cfca71 1247 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1248 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1249}
1250
debff618 1251static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1252{
33b56af1
EG		 1253 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1254
b7282643 1255 if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3) {
6dfb36c8
EP		 1256 /* Enable persistence mode to avoid reset */
1257 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1258 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1259 }
1260
2dd4f9f7 1261 iwl_disable_interrupts(trans);
debff618
JB		 1262
1263 /*
1264 * in testing mode, the host stays awake and the
1265 * hardware won't be reset (not even partially)
1266 */
1267 if (test)
1268 return;
1269
ddaf5a5b
JB		 1270 iwl_pcie_disable_ict(trans);
1271
33b56af1
EG		 1272 synchronize_irq(trans_pcie->pci_dev->irq);
1273
2dd4f9f7
JB		 1274 iwl_clear_bit(trans, CSR_GP_CNTRL,
1275 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1276 iwl_clear_bit(trans, CSR_GP_CNTRL,
1277 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1278
b7282643 1279 if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D3) {
6dfb36c8
EP		 1280 /*
1281 * reset TX queues -- some of their registers reset during S3
1282 * so if we don't reset everything here the D3 image would try
1283 * to execute some invalid memory upon resume
1284 */
1285 iwl_trans_pcie_tx_reset(trans);
1286 }
ddaf5a5b
JB		 1287
1288 iwl_pcie_set_pwr(trans, true);
1289}
1290
1291static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1292 enum iwl_d3_status *status,
1293 bool test)
ddaf5a5b
JB		 1294{
1295 u32 val;
1296 int ret;
1297
debff618
JB		 1298 if (test) {
1299 iwl_enable_interrupts(trans);
1300 *status = IWL_D3_STATUS_ALIVE;
1301 return 0;
1302 }
1303
ddaf5a5b
JB		 1304 /*
1305 * Also enables interrupts - none will happen as the device doesn't
1306 * know we're waking it up, only when the opmode actually tells it
1307 * after this call.
1308 */
1309 iwl_pcie_reset_ict(trans);
1310
1311 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1312 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1313
01e58a28
EG		 1314 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1315 udelay(2);
1316
ddaf5a5b
JB		 1317 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1318 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1319 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1320 25000);
7f2ac8fb 1321 if (ret < 0) {
ddaf5a5b
JB		 1322 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1323 return ret;
1324 }
1325
a3ead656
EG		 1326 iwl_pcie_set_pwr(trans, false);
1327
b7282643 1328 if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3) {
6dfb36c8
EP		 1329 iwl_clear_bit(trans, CSR_GP_CNTRL,
1330 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1331 } else {
1332 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1333
6dfb36c8
EP		 1334 ret = iwl_pcie_rx_init(trans);
1335 if (ret) {
1336 IWL_ERR(trans,
1337 "Failed to resume the device (RX reset)\n");
1338 return ret;
1339 }
ddaf5a5b
JB		 1340 }
1341
a3ead656
EG		 1342 val = iwl_read32(trans, CSR_RESET);
1343 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1344 *status = IWL_D3_STATUS_RESET;
1345 else
1346 *status = IWL_D3_STATUS_ALIVE;
1347
ddaf5a5b 1348 return 0;
2dd4f9f7
JB		 1349}
1350
fa9f3281 1351static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1352{
fa9f3281 1353 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
c9eec95c 1354 bool hw_rfkill;
a8b691e6 1355 int err;
e6bb4c9c 1356
fa9f3281
EG		 1357 lockdep_assert_held(&trans_pcie->mutex);
1358
7afe3705 1359 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1360 if (err) {
d6f1c316 1361 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1362 return err;
ebb7678d 1363 }
a6c684ee 1364
2997494f 1365 /* Reset the entire device */
ce836c76 1366 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1367
1368 usleep_range(10, 15);
1369
7afe3705 1370 iwl_pcie_apm_init(trans);
a6c684ee 1371
226c02ca
EG		 1372 /* From now on, the op_mode will be kept updated about RF kill state */
1373 iwl_enable_rfkill_int(trans);
1374
fa9f3281
EG		 1375 /* Set is_down to false here so that...*/
1376 trans_pcie->is_down = false;
1377
8d425517 1378 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1379 if (hw_rfkill)
eb7ff77e 1380 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1381 else
eb7ff77e 1382 clear_bit(STATUS_RFKILL, &trans->status);
fa9f3281 1383 /* ... rfkill can call stop_device and set it false if needed */
14cfca71 1384 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1385
a8b691e6 1386 return 0;
e6bb4c9c
EG		 1387}
1388
fa9f3281
EG		 1389static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1390{
1391 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1392 int ret;
1393
1394 mutex_lock(&trans_pcie->mutex);
1395 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1396 mutex_unlock(&trans_pcie->mutex);
1397
1398 return ret;
1399}
1400
a4082843 1401static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1402{
20d3b647 1403 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1404
fa9f3281
EG		 1405 mutex_lock(&trans_pcie->mutex);
1406
a4082843 1407 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1408 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1409 iwl_disable_interrupts(trans);
7b70bd63 1410 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1411
b7aaeae4 1412 iwl_pcie_apm_stop(trans, true);
cc56feb2 1413
7b70bd63 1414 spin_lock(&trans_pcie->irq_lock);
218733cf 1415 iwl_disable_interrupts(trans);
7b70bd63 1416 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1417
8d96bb61 1418 iwl_pcie_disable_ict(trans);
33b56af1 1419
fa9f3281 1420 mutex_unlock(&trans_pcie->mutex);
33b56af1
EG		 1421
1422 synchronize_irq(trans_pcie->pci_dev->irq);
cc56feb2
EG		 1423}
1424
03905495
EG		 1425static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1426{
05f5b97e 1427 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1428}
1429
1430static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1431{
05f5b97e 1432 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1433}
1434
1435static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1436{
05f5b97e 1437 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1438}
1439
6a06b6c1
EG		 1440static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1441{
f9477c17
AP		 1442 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1443 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1444 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1445}
1446
1447static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1448 u32 val)
1449{
1450 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1451 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1452 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1453}
1454
f14d6b39
JB		 1455static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1456{
1457 WARN_ON(1);
1458 return 0;
1459}
1460
c6f600fc 1461static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1462 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1463{
1464 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1465
1466 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1467 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1468 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1469 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1470 trans_pcie->n_no_reclaim_cmds = 0;
1471 else
1472 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1473 if (trans_pcie->n_no_reclaim_cmds)
1474 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1475 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1476
6c4fbcbc
EG		 1477 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1478 trans_pcie->rx_page_order =
1479 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1480
ab02165c 1481 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
046db346 1482 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1483 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1484 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1485
39bdb17e
SD		 1486 trans->command_groups = trans_cfg->command_groups;
1487 trans->command_groups_size = trans_cfg->command_groups_size;
1488
483f3ab1
EP		 1489 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1490 trans_pcie->ref_count = 1;
1491
f14d6b39
JB		 1492 /* Initialize NAPI here - it should be before registering to mac80211
1493 * in the opmode but after the HW struct is allocated.
1494 * As this function may be called again in some corner cases don't
1495 * do anything if NAPI was already initialized.
1496 */
1be5d8cc 1497 if (!trans_pcie->napi.poll) {
f14d6b39 1498 init_dummy_netdev(&trans_pcie->napi_dev);
1be5d8cc
JB		 1499 netif_napi_add(&trans_pcie->napi_dev, &trans_pcie->napi,
1500 iwl_pcie_dummy_napi_poll, 64);
f14d6b39 1501 }
c6f600fc
MV		 1502}
1503
d1ff5253 1504void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1505{
20d3b647 1506 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1507 int i;
a42a1844 1508
0aa86df6 1509 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1510
f02831be 1511 iwl_pcie_tx_free(trans);
9805c446 1512 iwl_pcie_rx_free(trans);
6379103e 1513
a8b691e6
JB		 1514 free_irq(trans_pcie->pci_dev->irq, trans);
1515 iwl_pcie_free_ict(trans);
a42a1844
EG		 1516
1517 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1518 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1519 pci_release_regions(trans_pcie->pci_dev);
1520 pci_disable_device(trans_pcie->pci_dev);
1521
f14d6b39
JB		 1522 if (trans_pcie->napi.poll)
1523 netif_napi_del(&trans_pcie->napi);
1524
c2d20201
EG		 1525 iwl_pcie_free_fw_monitor(trans);
1526
6eb5e529
EG		 1527 for_each_possible_cpu(i) {
1528 struct iwl_tso_hdr_page *p =
1529 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1530
1531 if (p->page)
1532 __free_page(p->page);
1533 }
1534
1535 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 1536 iwl_trans_free(trans);
34c1b7ba
EG		 1537}
1538
47107e84
DF		 1539static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1540{
47107e84 1541 if (state)
eb7ff77e 1542 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1543 else
eb7ff77e 1544 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1545}
1546
23ba9340
EG		 1547static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1548 unsigned long *flags)
7a65d170
EG		 1549{
1550 int ret;
cfb4e624
JB		 1551 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1552
1553 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1554
fc8a350d 1555 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1556 goto out;
1557
7a65d170 1558 /* this bit wakes up the NIC */
e139dc4a
LE		 1559 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1560 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1561 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1562 udelay(2);
7a65d170
EG		 1563
1564 /*
1565 * These bits say the device is running, and should keep running for
1566 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1567 * but they do not indicate that embedded SRAM is restored yet;
1568 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1569 * to/from host DRAM when sleeping/waking for power-saving.
1570 * Each direction takes approximately 1/4 millisecond; with this
1571 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1572 * series of register accesses are expected (e.g. reading Event Log),
1573 * to keep device from sleeping.
1574 *
1575 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1576 * SRAM is okay/restored. We don't check that here because this call
1577 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1578 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1579 *
1580 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1581 * and do not save/restore SRAM when power cycling.
1582 */
1583 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1584 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1585 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1586 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1587 if (unlikely(ret < 0)) {
1588 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1589 WARN_ONCE(1,
1590 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1591 iwl_read32(trans, CSR_GP_CNTRL));
1592 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1593 return false;
7a65d170
EG		 1594 }
1595
b9439491 1596out:
e56b04ef
LE		 1597 /*
1598 * Fool sparse by faking we release the lock - sparse will
1599 * track nic_access anyway.
1600 */
cfb4e624 1601 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1602 return true;
1603}
1604
e56b04ef
LE		 1605static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1606 unsigned long *flags)
7a65d170 1607{
cfb4e624 1608 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1609
cfb4e624 1610 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1611
1612 /*
1613 * Fool sparse by faking we acquiring the lock - sparse will
1614 * track nic_access anyway.
1615 */
cfb4e624 1616 __acquire(&trans_pcie->reg_lock);
e56b04ef 1617
fc8a350d 1618 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1619 goto out;
1620
e139dc4a
LE		 1621 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1622 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1623 /*
1624 * Above we read the CSR_GP_CNTRL register, which will flush
1625 * any previous writes, but we need the write that clears the
1626 * MAC_ACCESS_REQ bit to be performed before any other writes
1627 * scheduled on different CPUs (after we drop reg_lock).
1628 */
1629 mmiowb();
b9439491 1630out:
cfb4e624 1631 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1632}
1633
4fd442db
EG		 1634static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1635 void *buf, int dwords)
1636{
1637 unsigned long flags;
1638 int offs, ret = 0;
1639 u32 *vals = buf;
1640
23ba9340 1641 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1642 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1643 for (offs = 0; offs < dwords; offs++)
1644 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1645 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1646 } else {
1647 ret = -EBUSY;
1648 }
4fd442db
EG		 1649 return ret;
1650}
1651
1652static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1653 const void *buf, int dwords)
4fd442db
EG		 1654{
1655 unsigned long flags;
1656 int offs, ret = 0;
bf0fd5da 1657 const u32 *vals = buf;
4fd442db 1658
23ba9340 1659 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1660 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1661 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1662 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1663 vals ? vals[offs] : 0);
e56b04ef 1664 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1665 } else {
1666 ret = -EBUSY;
1667 }
4fd442db
EG		 1668 return ret;
1669}
7a65d170 1670
e0b8d405
EG		 1671static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1672 unsigned long txqs,
1673 bool freeze)
1674{
1675 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1676 int queue;
1677
1678 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1679 struct iwl_txq *txq = &trans_pcie->txq[queue];
1680 unsigned long now;
1681
1682 spin_lock_bh(&txq->lock);
1683
1684 now = jiffies;
1685
1686 if (txq->frozen == freeze)
1687 goto next_queue;
1688
1689 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1690 freeze ? "Freezing" : "Waking", queue);
1691
1692 txq->frozen = freeze;
1693
1694 if (txq->q.read_ptr == txq->q.write_ptr)
1695 goto next_queue;
1696
1697 if (freeze) {
1698 if (unlikely(time_after(now,
1699 txq->stuck_timer.expires))) {
1700 /*
1701 * The timer should have fired, maybe it is
1702 * spinning right now on the lock.
1703 */
1704 goto next_queue;
1705 }
1706 /* remember how long until the timer fires */
1707 txq->frozen_expiry_remainder =
1708 txq->stuck_timer.expires - now;
1709 del_timer(&txq->stuck_timer);
1710 goto next_queue;
1711 }
1712
1713 /*
1714 * Wake a non-empty queue -> arm timer with the
1715 * remainder before it froze
1716 */
1717 mod_timer(&txq->stuck_timer,
1718 now + txq->frozen_expiry_remainder);
1719
1720next_queue:
1721 spin_unlock_bh(&txq->lock);
1722 }
1723}
1724
0cd58eaa
EG		 1725static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1726{
1727 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1728 int i;
1729
1730 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1731 struct iwl_txq *txq = &trans_pcie->txq[i];
1732
1733 if (i == trans_pcie->cmd_queue)
1734 continue;
1735
1736 spin_lock_bh(&txq->lock);
1737
1738 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1739 txq->block--;
1740 if (!txq->block) {
1741 iwl_write32(trans, HBUS_TARG_WRPTR,
1742 txq->q.write_ptr | (i << 8));
1743 }
1744 } else if (block) {
1745 txq->block++;
1746 }
1747
1748 spin_unlock_bh(&txq->lock);
1749 }
1750}
1751
5f178cd2
EG		 1752#define IWL_FLUSH_WAIT_MS 2000
1753
3cafdbe6 1754static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1755{
8ad71bef 1756 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1757 struct iwl_txq *txq;
5f178cd2
EG		 1758 struct iwl_queue *q;
1759 int cnt;
1760 unsigned long now = jiffies;
1c3fea82
EG		 1761 u32 scd_sram_addr;
1762 u8 buf[16];
5f178cd2
EG		 1763 int ret = 0;
1764
1765 /* waiting for all the tx frames complete might take a while */
035f7ff2 1766 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1767 u8 wr_ptr;
1768
9ba1947a 1769 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1770 continue;
3cafdbe6
EG		 1771 if (!test_bit(cnt, trans_pcie->queue_used))
1772 continue;
1773 if (!(BIT(cnt) & txq_bm))
1774 continue;
748fa67c
EG		 1775
1776 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1777 txq = &trans_pcie->txq[cnt];
5f178cd2 1778 q = &txq->q;
fa1a91fd
EG		 1779 wr_ptr = ACCESS_ONCE(q->write_ptr);
1780
1781 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1782 !time_after(jiffies,
1783 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1784 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1785
1786 if (WARN_ONCE(wr_ptr != write_ptr,
1787 "WR pointer moved while flushing %d -> %d\n",
1788 wr_ptr, write_ptr))
1789 return -ETIMEDOUT;
5f178cd2 1790 msleep(1);
fa1a91fd 1791 }
5f178cd2
EG		 1792
1793 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1794 IWL_ERR(trans,
1795 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1796 ret = -ETIMEDOUT;
1797 break;
1798 }
748fa67c 1799 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1800 }
1c3fea82
EG		 1801
1802 if (!ret)
1803 return 0;
1804
1805 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1806 txq->q.read_ptr, txq->q.write_ptr);
1807
1808 scd_sram_addr = trans_pcie->scd_base_addr +
1809 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1810 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1811
1812 iwl_print_hex_error(trans, buf, sizeof(buf));
1813
1814 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1815 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1816 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1817
1818 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1819 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1820 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1821 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1822 u32 tbl_dw =
1823 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1824 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1825
1826 if (cnt & 0x1)
1827 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1828 else
1829 tbl_dw = tbl_dw & 0x0000FFFF;
1830
1831 IWL_ERR(trans,
1832 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1833 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1834 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1835 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1836 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1837 }
1838
5f178cd2
EG		 1839 return ret;
1840}
1841
e139dc4a
LE		 1842static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1843 u32 mask, u32 value)
1844{
e56b04ef 1845 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1846 unsigned long flags;
1847
e56b04ef 1848 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1849 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1850 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1851}
1852
7616f334
EP		 1853void iwl_trans_pcie_ref(struct iwl_trans *trans)
1854{
1855 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1856 unsigned long flags;
1857
1858 if (iwlwifi_mod_params.d0i3_disable)
1859 return;
1860
1861 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1862 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1863 trans_pcie->ref_count++;
1864 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1865}
1866
1867void iwl_trans_pcie_unref(struct iwl_trans *trans)
1868{
1869 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1870 unsigned long flags;
1871
1872 if (iwlwifi_mod_params.d0i3_disable)
1873 return;
1874
1875 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1876 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1877 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1878 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1879 return;
1880 }
1881 trans_pcie->ref_count--;
1882 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1883}
1884
ff620849
EG		 1885static const char *get_csr_string(int cmd)
1886{
d9fb6465 1887#define IWL_CMD(x) case x: return #x
ff620849
EG		 1888 switch (cmd) {
1889 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1890 IWL_CMD(CSR_INT_COALESCING);
1891 IWL_CMD(CSR_INT);
1892 IWL_CMD(CSR_INT_MASK);
1893 IWL_CMD(CSR_FH_INT_STATUS);
1894 IWL_CMD(CSR_GPIO_IN);
1895 IWL_CMD(CSR_RESET);
1896 IWL_CMD(CSR_GP_CNTRL);
1897 IWL_CMD(CSR_HW_REV);
1898 IWL_CMD(CSR_EEPROM_REG);
1899 IWL_CMD(CSR_EEPROM_GP);
1900 IWL_CMD(CSR_OTP_GP_REG);
1901 IWL_CMD(CSR_GIO_REG);
1902 IWL_CMD(CSR_GP_UCODE_REG);
1903 IWL_CMD(CSR_GP_DRIVER_REG);
1904 IWL_CMD(CSR_UCODE_DRV_GP1);
1905 IWL_CMD(CSR_UCODE_DRV_GP2);
1906 IWL_CMD(CSR_LED_REG);
1907 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1908 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1909 IWL_CMD(CSR_ANA_PLL_CFG);
1910 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1911 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1912 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1913 default:
1914 return "UNKNOWN";
1915 }
d9fb6465 1916#undef IWL_CMD
ff620849
EG		 1917}
1918
990aa6d7 1919void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1920{
1921 int i;
1922 static const u32 csr_tbl[] = {
1923 CSR_HW_IF_CONFIG_REG,
1924 CSR_INT_COALESCING,
1925 CSR_INT,
1926 CSR_INT_MASK,
1927 CSR_FH_INT_STATUS,
1928 CSR_GPIO_IN,
1929 CSR_RESET,
1930 CSR_GP_CNTRL,
1931 CSR_HW_REV,
1932 CSR_EEPROM_REG,
1933 CSR_EEPROM_GP,
1934 CSR_OTP_GP_REG,
1935 CSR_GIO_REG,
1936 CSR_GP_UCODE_REG,
1937 CSR_GP_DRIVER_REG,
1938 CSR_UCODE_DRV_GP1,
1939 CSR_UCODE_DRV_GP2,
1940 CSR_LED_REG,
1941 CSR_DRAM_INT_TBL_REG,
1942 CSR_GIO_CHICKEN_BITS,
1943 CSR_ANA_PLL_CFG,
a812cba9 1944 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1945 CSR_HW_REV_WA_REG,
1946 CSR_DBG_HPET_MEM_REG
1947 };
1948 IWL_ERR(trans, "CSR values:\n");
1949 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1950 "CSR_INT_PERIODIC_REG)\n");
1951 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1952 IWL_ERR(trans, " %25s: 0X%08x\n",
1953 get_csr_string(csr_tbl[i]),
1042db2a 1954 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1955 }
1956}
1957
87e5666c
EG		 1958#ifdef CONFIG_IWLWIFI_DEBUGFS
1959/* create and remove of files */
1960#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1961 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1962 &iwl_dbgfs_##name##_ops)) \
9da987ac 1963 goto err; \
87e5666c
EG		 1964} while (0)
1965
1966/* file operation */
87e5666c 1967#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1968static const struct file_operations iwl_dbgfs_##name##_ops = { \
1969 .read = iwl_dbgfs_##name##_read, \
234e3405 1970 .open = simple_open, \
87e5666c
EG		 1971 .llseek = generic_file_llseek, \
1972};
1973
16db88ba 1974#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1975static const struct file_operations iwl_dbgfs_##name##_ops = { \
1976 .write = iwl_dbgfs_##name##_write, \
234e3405 1977 .open = simple_open, \
16db88ba
EG		 1978 .llseek = generic_file_llseek, \
1979};
1980
87e5666c 1981#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1982static const struct file_operations iwl_dbgfs_##name##_ops = { \
1983 .write = iwl_dbgfs_##name##_write, \
1984 .read = iwl_dbgfs_##name##_read, \
234e3405 1985 .open = simple_open, \
87e5666c
EG		 1986 .llseek = generic_file_llseek, \
1987};
1988
87e5666c 1989static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1990 char __user *user_buf,
1991 size_t count, loff_t *ppos)
8ad71bef 1992{
5a878bf6 1993 struct iwl_trans *trans = file->private_data;
8ad71bef 1994 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1995 struct iwl_txq *txq;
87e5666c
EG		 1996 struct iwl_queue *q;
1997 char *buf;
1998 int pos = 0;
1999 int cnt;
2000 int ret;
1745e440
WYG		 2001 size_t bufsz;
2002
e0b8d405 2003 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2004
f9e75447 2005 if (!trans_pcie->txq)
87e5666c 2006 return -EAGAIN;
f9e75447 2007
87e5666c
EG		 2008 buf = kzalloc(bufsz, GFP_KERNEL);
2009 if (!buf)
2010 return -ENOMEM;
2011
035f7ff2 2012 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 2013 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 2014 q = &txq->q;
2015 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2016 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
87e5666c 2017 cnt, q->read_ptr, q->write_ptr,
9eae88fa 2018 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2019 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2020 txq->need_update, txq->frozen,
f40faf62 2021 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2022 }
2023 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2024 kfree(buf);
2025 return ret;
2026}
2027
2028static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2029 char __user *user_buf,
2030 size_t count, loff_t *ppos)
2031{
5a878bf6 2032 struct iwl_trans *trans = file->private_data;
20d3b647 2033 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2034 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 2035 char buf[256];
2036 int pos = 0;
2037 const size_t bufsz = sizeof(buf);
2038
2039 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
2040 rxq->read);
2041 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
2042 rxq->write);
f40faf62
AL		 2043 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
2044 rxq->write_actual);
2045 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
2046 rxq->need_update);
87e5666c
EG		 2047 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
2048 rxq->free_count);
2049 if (rxq->rb_stts) {
2050 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
2051 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
2052 } else {
2053 pos += scnprintf(buf + pos, bufsz - pos,
2054 "closed_rb_num: Not Allocated\n");
2055 }
2056 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2057}
2058
1f7b6172
EG		 2059static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2060 char __user *user_buf,
20d3b647
JB		 2061 size_t count, loff_t *ppos)
2062{
1f7b6172 2063 struct iwl_trans *trans = file->private_data;
20d3b647 2064 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2065 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2066
2067 int pos = 0;
2068 char *buf;
2069 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2070 ssize_t ret;
2071
2072 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2073 if (!buf)
1f7b6172 2074 return -ENOMEM;
1f7b6172
EG		 2075
2076 pos += scnprintf(buf + pos, bufsz - pos,
2077 "Interrupt Statistics Report:\n");
2078
2079 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2080 isr_stats->hw);
2081 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2082 isr_stats->sw);
2083 if (isr_stats->sw || isr_stats->hw) {
2084 pos += scnprintf(buf + pos, bufsz - pos,
2085 "\tLast Restarting Code: 0x%X\n",
2086 isr_stats->err_code);
2087 }
2088#ifdef CONFIG_IWLWIFI_DEBUG
2089 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2090 isr_stats->sch);
2091 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2092 isr_stats->alive);
2093#endif
2094 pos += scnprintf(buf + pos, bufsz - pos,
2095 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2096
2097 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2098 isr_stats->ctkill);
2099
2100 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2101 isr_stats->wakeup);
2102
2103 pos += scnprintf(buf + pos, bufsz - pos,
2104 "Rx command responses:\t\t %u\n", isr_stats->rx);
2105
2106 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2107 isr_stats->tx);
2108
2109 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2110 isr_stats->unhandled);
2111
2112 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2113 kfree(buf);
2114 return ret;
2115}
2116
2117static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2118 const char __user *user_buf,
2119 size_t count, loff_t *ppos)
2120{
2121 struct iwl_trans *trans = file->private_data;
20d3b647 2122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2123 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2124
2125 char buf[8];
2126 int buf_size;
2127 u32 reset_flag;
2128
2129 memset(buf, 0, sizeof(buf));
2130 buf_size = min(count, sizeof(buf) - 1);
2131 if (copy_from_user(buf, user_buf, buf_size))
2132 return -EFAULT;
2133 if (sscanf(buf, "%x", &reset_flag) != 1)
2134 return -EFAULT;
2135 if (reset_flag == 0)
2136 memset(isr_stats, 0, sizeof(*isr_stats));
2137
2138 return count;
2139}
2140
16db88ba 2141static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2142 const char __user *user_buf,
2143 size_t count, loff_t *ppos)
16db88ba
EG		 2144{
2145 struct iwl_trans *trans = file->private_data;
2146 char buf[8];
2147 int buf_size;
2148 int csr;
2149
2150 memset(buf, 0, sizeof(buf));
2151 buf_size = min(count, sizeof(buf) - 1);
2152 if (copy_from_user(buf, user_buf, buf_size))
2153 return -EFAULT;
2154 if (sscanf(buf, "%d", &csr) != 1)
2155 return -EFAULT;
2156
990aa6d7 2157 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2158
2159 return count;
2160}
2161
16db88ba 2162static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2163 char __user *user_buf,
2164 size_t count, loff_t *ppos)
16db88ba
EG		 2165{
2166 struct iwl_trans *trans = file->private_data;
94543a8d 2167 char *buf = NULL;
56c2477f 2168 ssize_t ret;
16db88ba 2169
56c2477f
JB		 2170 ret = iwl_dump_fh(trans, &buf);
2171 if (ret < 0)
2172 return ret;
2173 if (!buf)
2174 return -EINVAL;
2175 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2176 kfree(buf);
16db88ba
EG		 2177 return ret;
2178}
2179
1f7b6172 2180DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2181DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2182DEBUGFS_READ_FILE_OPS(rx_queue);
2183DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2184DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c 2185
f8a1edb7
JB		 2186/* Create the debugfs files and directories */
2187int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2188{
f8a1edb7
JB		 2189 struct dentry *dir = trans->dbgfs_dir;
2190
87e5666c
EG		 2191 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2192 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2193 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2194 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2195 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2196 return 0;
9da987ac
MV		 2197
2198err:
2199 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2200 return -ENOMEM;
87e5666c 2201}
aadede6e 2202#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 2203
2204static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2205{
2206 u32 cmdlen = 0;
2207 int i;
2208
2209 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2210 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2211
2212 return cmdlen;
2213}
2214
bd7fc617
EG		 2215static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2216 struct iwl_fw_error_dump_data **data,
2217 int allocated_rb_nums)
2218{
2219 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2220 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2221 struct iwl_rxq *rxq = &trans_pcie->rxq;
2222 u32 i, r, j, rb_len = 0;
2223
2224 spin_lock(&rxq->lock);
2225
2226 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2227
2228 for (i = rxq->read, j = 0;
2229 i != r && j < allocated_rb_nums;
2230 i = (i + 1) & RX_QUEUE_MASK, j++) {
2231 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2232 struct iwl_fw_error_dump_rb *rb;
2233
2234 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2235 DMA_FROM_DEVICE);
2236
2237 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2238
2239 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2240 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2241 rb = (void *)(*data)->data;
2242 rb->index = cpu_to_le32(i);
2243 memcpy(rb->data, page_address(rxb->page), max_len);
2244 /* remap the page for the free benefit */
2245 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2246 max_len,
2247 DMA_FROM_DEVICE);
2248
2249 *data = iwl_fw_error_next_data(*data);
2250 }
2251
2252 spin_unlock(&rxq->lock);
2253
2254 return rb_len;
2255}
473ad712
EG		 2256#define IWL_CSR_TO_DUMP (0x250)
2257
2258static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2259 struct iwl_fw_error_dump_data **data)
2260{
2261 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2262 __le32 *val;
2263 int i;
2264
2265 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2266 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2267 val = (void *)(*data)->data;
2268
2269 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2270 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2271
2272 *data = iwl_fw_error_next_data(*data);
2273
2274 return csr_len;
2275}
2276
06d51e0d
LK		 2277static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2278 struct iwl_fw_error_dump_data **data)
2279{
2280 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2281 unsigned long flags;
2282 __le32 *val;
2283 int i;
2284
23ba9340 2285 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2286 return 0;
2287
2288 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2289 (*data)->len = cpu_to_le32(fh_regs_len);
2290 val = (void *)(*data)->data;
2291
2292 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2293 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2294
2295 iwl_trans_release_nic_access(trans, &flags);
2296
2297 *data = iwl_fw_error_next_data(*data);
2298
2299 return sizeof(**data) + fh_regs_len;
2300}
2301
cc79ef66
LK		 2302static u32
2303iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2304 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2305 u32 monitor_len)
2306{
2307 u32 buf_size_in_dwords = (monitor_len >> 2);
2308 u32 *buffer = (u32 *)fw_mon_data->data;
2309 unsigned long flags;
2310 u32 i;
2311
23ba9340 2312 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2313 return 0;
2314
14ef1b43 2315 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2316 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2317 buffer[i] = iwl_read_prph_no_grab(trans,
2318 MON_DMARB_RD_DATA_ADDR);
2319 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2320
2321 iwl_trans_release_nic_access(trans, &flags);
2322
2323 return monitor_len;
2324}
2325
36fb9017
OG		 2326static u32
2327iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2328 struct iwl_fw_error_dump_data **data,
2329 u32 monitor_len)
2330{
2331 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2332 u32 len = 0;
2333
2334 if ((trans_pcie->fw_mon_page &&
2335 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2336 trans->dbg_dest_tlv) {
2337 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2338 u32 base, write_ptr, wrap_cnt;
2339
2340 /* If there was a dest TLV - use the values from there */
2341 if (trans->dbg_dest_tlv) {
2342 write_ptr =
2343 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2344 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2345 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2346 } else {
2347 base = MON_BUFF_BASE_ADDR;
2348 write_ptr = MON_BUFF_WRPTR;
2349 wrap_cnt = MON_BUFF_CYCLE_CNT;
2350 }
2351
2352 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2353 fw_mon_data = (void *)(*data)->data;
2354 fw_mon_data->fw_mon_wr_ptr =
2355 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2356 fw_mon_data->fw_mon_cycle_cnt =
2357 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2358 fw_mon_data->fw_mon_base_ptr =
2359 cpu_to_le32(iwl_read_prph(trans, base));
2360
2361 len += sizeof(**data) + sizeof(*fw_mon_data);
2362 if (trans_pcie->fw_mon_page) {
2363 /*
2364 * The firmware is now asserted, it won't write anything
2365 * to the buffer. CPU can take ownership to fetch the
2366 * data. The buffer will be handed back to the device
2367 * before the firmware will be restarted.
2368 */
2369 dma_sync_single_for_cpu(trans->dev,
2370 trans_pcie->fw_mon_phys,
2371 trans_pcie->fw_mon_size,
2372 DMA_FROM_DEVICE);
2373 memcpy(fw_mon_data->data,
2374 page_address(trans_pcie->fw_mon_page),
2375 trans_pcie->fw_mon_size);
2376
2377 monitor_len = trans_pcie->fw_mon_size;
2378 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2379 /*
2380 * Update pointers to reflect actual values after
2381 * shifting
2382 */
2383 base = iwl_read_prph(trans, base) <<
2384 trans->dbg_dest_tlv->base_shift;
2385 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2386 monitor_len / sizeof(u32));
2387 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2388 monitor_len =
2389 iwl_trans_pci_dump_marbh_monitor(trans,
2390 fw_mon_data,
2391 monitor_len);
2392 } else {
2393 /* Didn't match anything - output no monitor data */
2394 monitor_len = 0;
2395 }
2396
2397 len += monitor_len;
2398 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2399 }
2400
2401 return len;
2402}
2403
2404static struct iwl_trans_dump_data
2405*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2406 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2407{
2408 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2409 struct iwl_fw_error_dump_data *data;
2410 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2411 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2412 struct iwl_trans_dump_data *dump_data;
bd7fc617 2413 u32 len, num_rbs;
99684ae3 2414 u32 monitor_len;
4d075007 2415 int i, ptr;
bd7fc617 2416 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status);
4d075007 2417
473ad712
EG		 2418 /* transport dump header */
2419 len = sizeof(*dump_data);
2420
2421 /* host commands */
2422 len += sizeof(*data) +
c2d20201
EG		 2423 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2424
473ad712 2425 /* FW monitor */
99684ae3 2426 if (trans_pcie->fw_mon_page) {
c544e9c4 2427 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2428 trans_pcie->fw_mon_size;
2429 monitor_len = trans_pcie->fw_mon_size;
2430 } else if (trans->dbg_dest_tlv) {
2431 u32 base, end;
2432
2433 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2434 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2435
2436 base = iwl_read_prph(trans, base) <<
2437 trans->dbg_dest_tlv->base_shift;
2438 end = iwl_read_prph(trans, end) <<
2439 trans->dbg_dest_tlv->end_shift;
2440
2441 /* Make "end" point to the actual end */
cc79ef66
LK		 2442 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2443 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2444 end += (1 << trans->dbg_dest_tlv->end_shift);
2445 monitor_len = end - base;
2446 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2447 monitor_len;
2448 } else {
2449 monitor_len = 0;
2450 }
c2d20201 2451
36fb9017
OG		 2452 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2453 dump_data = vzalloc(len);
2454 if (!dump_data)
2455 return NULL;
2456
2457 data = (void *)dump_data->data;
2458 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2459 dump_data->len = len;
2460
2461 return dump_data;
2462 }
2463
2464 /* CSR registers */
2465 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2466
36fb9017
OG		 2467 /* FH registers */
2468 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2469
2470 if (dump_rbs) {
2471 /* RBs */
2472 num_rbs = le16_to_cpu(ACCESS_ONCE(
2473 trans_pcie->rxq.rb_stts->closed_rb_num))
2474 & 0x0FFF;
2475 num_rbs = (num_rbs - trans_pcie->rxq.read) & RX_QUEUE_MASK;
2476 len += num_rbs * (sizeof(*data) +
2477 sizeof(struct iwl_fw_error_dump_rb) +
2478 (PAGE_SIZE << trans_pcie->rx_page_order));
2479 }
2480
48eb7b34
EG		 2481 dump_data = vzalloc(len);
2482 if (!dump_data)
2483 return NULL;
4d075007
JB		 2484
2485 len = 0;
48eb7b34 2486 data = (void *)dump_data->data;
4d075007
JB		 2487 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2488 txcmd = (void *)data->data;
2489 spin_lock_bh(&cmdq->lock);
2490 ptr = cmdq->q.write_ptr;
2491 for (i = 0; i < cmdq->q.n_window; i++) {
2492 u8 idx = get_cmd_index(&cmdq->q, ptr);
2493 u32 caplen, cmdlen;
2494
2495 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2496 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2497
2498 if (cmdlen) {
2499 len += sizeof(*txcmd) + caplen;
2500 txcmd->cmdlen = cpu_to_le32(cmdlen);
2501 txcmd->caplen = cpu_to_le32(caplen);
2502 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2503 txcmd = (void *)((u8 *)txcmd->data + caplen);
2504 }
2505
2506 ptr = iwl_queue_dec_wrap(ptr);
2507 }
2508 spin_unlock_bh(&cmdq->lock);
2509
2510 data->len = cpu_to_le32(len);
c2d20201 2511 len += sizeof(*data);
67c65f2c
EG		 2512 data = iwl_fw_error_next_data(data);
2513
473ad712 2514 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2515 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2516 if (dump_rbs)
2517 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2518
36fb9017 2519 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2520
48eb7b34
EG		 2521 dump_data->len = len;
2522
2523 return dump_data;
4d075007 2524}
87e5666c 2525
d1ff5253 2526static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2527 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2528 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2529 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2530 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2531 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2532
ddaf5a5b
JB		 2533 .d3_suspend = iwl_trans_pcie_d3_suspend,
2534 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2535
f02831be 2536 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2537
e6bb4c9c 2538 .tx = iwl_trans_pcie_tx,
a0eaad71 2539 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2540
d0624be6 2541 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2542 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2543
990aa6d7 2544 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2545 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
0cd58eaa 2546 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
5f178cd2 2547
03905495
EG		 2548 .write8 = iwl_trans_pcie_write8,
2549 .write32 = iwl_trans_pcie_write32,
2550 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2551 .read_prph = iwl_trans_pcie_read_prph,
2552 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2553 .read_mem = iwl_trans_pcie_read_mem,
2554 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2555 .configure = iwl_trans_pcie_configure,
47107e84 2556 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2557 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2558 .release_nic_access = iwl_trans_pcie_release_nic_access,
2559 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2560
7616f334
EP		 2561 .ref = iwl_trans_pcie_ref,
2562 .unref = iwl_trans_pcie_unref,
2563
4d075007 2564 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2565};
a42a1844 2566
87ce05a2 2567struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2568 const struct pci_device_id *ent,
2569 const struct iwl_cfg *cfg)
a42a1844 2570{
a42a1844
EG		 2571 struct iwl_trans_pcie *trans_pcie;
2572 struct iwl_trans *trans;
2573 u16 pci_cmd;
af3f2f74 2574 int ret;
a42a1844 2575
7b501d10
JB		 2576 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2577 &pdev->dev, cfg, &trans_ops_pcie, 0);
2578 if (!trans)
2579 return ERR_PTR(-ENOMEM);
a42a1844 2580
206eea78
JB		 2581 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2582
a42a1844
EG		 2583 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2584
a42a1844 2585 trans_pcie->trans = trans;
7b11488f 2586 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2587 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2588 spin_lock_init(&trans_pcie->ref_lock);
fa9f3281 2589 mutex_init(&trans_pcie->mutex);
13df1aab 2590 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 2591 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2592 if (!trans_pcie->tso_hdr_page) {
2593 ret = -ENOMEM;
2594 goto out_no_pci;
2595 }
a42a1844 2596
af3f2f74
EG		 2597 ret = pci_enable_device(pdev);
2598 if (ret)
d819c6cf
JB		 2599 goto out_no_pci;
2600
f2532b04
EG		 2601 if (!cfg->base_params->pcie_l1_allowed) {
2602 /*
2603 * W/A - seems to solve weird behavior. We need to remove this
2604 * if we don't want to stay in L1 all the time. This wastes a
2605 * lot of power.
2606 */
2607 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2608 PCIE_LINK_STATE_L1 |
2609 PCIE_LINK_STATE_CLKPM);
2610 }
a42a1844 2611
a42a1844
EG		 2612 pci_set_master(pdev);
2613
af3f2f74
EG		 2614 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2615 if (!ret)
2616 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2617 if (ret) {
2618 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2619 if (!ret)
2620 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2621 DMA_BIT_MASK(32));
a42a1844 2622 /* both attempts failed: */
af3f2f74 2623 if (ret) {
6a4b09f8 2624 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2625 goto out_pci_disable_device;
2626 }
2627 }
2628
af3f2f74
EG		 2629 ret = pci_request_regions(pdev, DRV_NAME);
2630 if (ret) {
6a4b09f8 2631 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2632 goto out_pci_disable_device;
2633 }
2634
05f5b97e 2635 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2636 if (!trans_pcie->hw_base) {
6a4b09f8 2637 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
af3f2f74 2638 ret = -ENODEV;
a42a1844
EG		 2639 goto out_pci_release_regions;
2640 }
2641
a42a1844
EG		 2642 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2643 * PCI Tx retries from interfering with C3 CPU state */
2644 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2645
83f7a85f
EG		 2646 trans->dev = &pdev->dev;
2647 trans_pcie->pci_dev = pdev;
2648 iwl_disable_interrupts(trans);
2649
af3f2f74
EG		 2650 ret = pci_enable_msi(pdev);
2651 if (ret) {
2652 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
9f904b38
EG		 2653 /* enable rfkill interrupt: hw bug w/a */
2654 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2655 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2656 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2657 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2658 }
2659 }
a42a1844 2660
08079a49 2661 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2662 /*
2663 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2664 * changed, and now the revision step also includes bit 0-1 (no more
2665 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2666 * in the old format.
2667 */
7a42baa6
EH		 2668 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2669 unsigned long flags;
7a42baa6 2670
b513ee7f 2671 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2672 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2673
f9e5554c
EG		 2674 ret = iwl_pcie_prepare_card_hw(trans);
2675 if (ret) {
2676 IWL_WARN(trans, "Exit HW not ready\n");
2677 goto out_pci_disable_msi;
2678 }
2679
7a42baa6
EH		 2680 /*
2681 * in-order to recognize C step driver should read chip version
2682 * id located at the AUX bus MISC address space.
2683 */
2684 iwl_set_bit(trans, CSR_GP_CNTRL,
2685 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2686 udelay(2);
2687
2688 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2689 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2690 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2691 25000);
2692 if (ret < 0) {
2693 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2694 goto out_pci_disable_msi;
2695 }
2696
23ba9340 2697 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 2698 u32 hw_step;
2699
14ef1b43 2700 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 2701 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 2702 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2703 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 2704 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2705 if (hw_step == 0x3)
2706 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2707 (SILICON_C_STEP << 2);
2708 iwl_trans_release_nic_access(trans, &flags);
2709 }
2710 }
2711
99673ee5 2712 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2713 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2714 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2715
69a10b29 2716 /* Initialize the wait queue for commands */
f946b529 2717 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2718
af3f2f74
EG		 2719 ret = iwl_pcie_alloc_ict(trans);
2720 if (ret)
7b501d10 2721 goto out_pci_disable_msi;
a8b691e6 2722
af3f2f74 2723 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2724 iwl_pcie_irq_handler,
2725 IRQF_SHARED, DRV_NAME, trans);
af3f2f74 2726 if (ret) {
a8b691e6
JB		 2727 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2728 goto out_free_ict;
2729 }
2730
83f7a85f
EG		 2731 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2732
a42a1844
EG		 2733 return trans;
2734
a8b691e6
JB		 2735out_free_ict:
2736 iwl_pcie_free_ict(trans);
59c647b6
EG		 2737out_pci_disable_msi:
2738 pci_disable_msi(pdev);
a42a1844
EG		 2739out_pci_release_regions:
2740 pci_release_regions(pdev);
2741out_pci_disable_device:
2742 pci_disable_device(pdev);
2743out_no_pci:
6eb5e529 2744 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 2745 iwl_trans_free(trans);
af3f2f74 2746 return ERR_PTR(ret);
a42a1844 2747}
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