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Merge remote-tracking branches 'asoc/topic/msm8916', 'asoc/topic/mtk', 'asoc/topic...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
b3ff1270 75#include <linux/pm_runtime.h>
e6bb4c9c 76
82575102 77#include "iwl-drv.h"
c85eb619 78#include "iwl-trans.h"
522376d2
EG		 79#include "iwl-csr.h"
80#include "iwl-prph.h"
cb6bb128 81#include "iwl-scd.h"
7a10e3e4 82#include "iwl-agn-hw.h"
4d075007 83#include "iwl-fw-error-dump.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
c2d20201
EG		 91static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92{
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105}
106
96c285da 107static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 108{
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 110 struct page *page = NULL;
c2d20201 111 dma_addr_t phys;
96c285da 112 u32 size = 0;
c2d20201
EG		 113 u8 power;
114
96c285da
EG		 115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
c2d20201
EG		 127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
96c285da 135 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
553452e5 149 page = NULL;
c2d20201
EG		 150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
40a76905 158 if (WARN_ON_ONCE(!page))
c2d20201
EG		 159 return;
160
96c285da
EG		 161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
c2d20201
EG		 167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170}
171
a812cba9
AB		 172static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173{
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177}
178
179static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180{
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184}
185
ddaf5a5b 186static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 187{
66337b7c 188 if (trans->cfg->apmg_not_supported)
95411d04
AA		 189 return;
190
ddaf5a5b
JB		 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 199}
200
af634bee
EG		 201/* PCI registers */
202#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 203
eda50cde 204void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 205{
20d3b647 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 207 u16 lctl;
9180ac50 208 u16 cap;
af634bee 209
af634bee
EG		 210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
7afe3705 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 221 else
af634bee 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 230}
231
a6c684ee
EG		 232/*
233 * Start up NIC's basic functionality after it has been reset
7afe3705 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 235 * NOTE: This does not load uCode nor start the embedded processor
236 */
7afe3705 237static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 238{
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 268
7afe3705 269 iwl_pcie_apm_config(trans);
a6c684ee
EG		 270
271 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 272 if (trans->cfg->base_params->pll_cfg)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
2d93aee1
EG		 294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
a6c684ee
EG		 316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
3073d8c0
EH		 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 322 */
95411d04 323 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
889b1696 336
eb7ff77e 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 338
339out:
340 return ret;
341}
342
a812cba9
AB		 343/*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
350static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351{
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 363 usleep_range(1000, 2000);
a812cba9
AB		 364
365 /*
366 * Set "initialization complete" bit to move adapter from
367 * D0U* --> D0A* (powered-up active) state.
368 */
369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
370
371 /*
372 * Wait for clock stabilization; once stabilized, access to
373 * device-internal resources is possible.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 25000);
379 if (WARN_ON(ret < 0)) {
380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
381 /* Release XTAL ON request */
382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
384 return;
385 }
386
387 /*
388 * Clear "disable persistence" to avoid LP XTAL resetting when
389 * SHRD_HW_RST is applied in S3.
390 */
391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
392 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
393
394 /*
395 * Force APMG XTAL to be active to prevent its disabling by HW
396 * caused by APMG idle state.
397 */
398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
399 SHR_APMG_XTAL_CFG_REG);
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
401 apmg_xtal_cfg_reg |
402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
403
404 /*
405 * Reset entire device again - do controller reset (results in
406 * SHRD_HW_RST). Turn MAC off before proceeding.
407 */
408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 409 usleep_range(1000, 2000);
a812cba9
AB		 410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
77c09bc8 451int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
b7aaeae4 469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
b7aaeae4
EG		 473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
c9fdec9f
EG		 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
483 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PREPARE |
486 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 487 mdelay(1);
488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
489 CSR_RESET_LINK_PWR_MGMT_DISABLED);
490 }
b7aaeae4
EG		 491 mdelay(5);
492 }
493
eb7ff77e 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 495
496 /* Stop device's DMA activity */
7afe3705 497 iwl_pcie_apm_stop_master(trans);
cc56feb2 498
a812cba9
AB		 499 if (trans->cfg->lp_xtal_workaround) {
500 iwl_pcie_apm_lp_xtal_enable(trans);
501 return;
502 }
503
cc56feb2
EG		 504 /* Reset the entire device */
505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 506 usleep_range(1000, 2000);
cc56feb2
EG		 507
508 /*
509 * Clear "initialization complete" bit to move adapter from
510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
511 */
512 iwl_clear_bit(trans, CSR_GP_CNTRL,
513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
514}
515
7afe3705 516static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 517{
7b11488f 518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 519
520 /* nic_init */
7b70bd63 521 spin_lock(&trans_pcie->irq_lock);
7afe3705 522 iwl_pcie_apm_init(trans);
392f8b78 523
7b70bd63 524 spin_unlock(&trans_pcie->irq_lock);
392f8b78 525
95411d04 526 iwl_pcie_set_pwr(trans, false);
392f8b78 527
ecdb975c 528 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 529
530 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 531 iwl_pcie_rx_init(trans);
392f8b78
EG		 532
533 /* Allocate or reset and init all Tx and Command queues */
f02831be 534 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 535 return -ENOMEM;
536
035f7ff2 537 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 538 /* enable shadow regs in HW */
20d3b647 539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 541 }
542
392f8b78
EG		 543 return 0;
544}
545
546#define HW_READY_TIMEOUT (50)
547
548/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 549static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 550{
551 int ret;
552
1042db2a 553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 555
556 /* See if we got it */
1042db2a 557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
560 HW_READY_TIMEOUT);
392f8b78 561
6a08f514
EG		 562 if (ret >= 0)
563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
564
6d8f6eeb 565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 566 return ret;
567}
568
569/* Note: returns standard 0/-ERROR code */
eda50cde 570int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 571{
572 int ret;
289e5501 573 int t = 0;
501fd989 574 int iter;
392f8b78 575
6d8f6eeb 576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 577
7afe3705 578 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 579 /* If the card is ready, exit 0 */
392f8b78
EG		 580 if (ret >= 0)
581 return 0;
582
c9fdec9f
EG		 583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
584 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 585 usleep_range(1000, 2000);
c9fdec9f 586
501fd989
EG		 587 for (iter = 0; iter < 10; iter++) {
588 /* If HW is not ready, prepare the conditions to check again */
589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
590 CSR_HW_IF_CONFIG_REG_PREPARE);
591
592 do {
593 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 594 if (ret >= 0)
595 return 0;
392f8b78 596
501fd989
EG		 597 usleep_range(200, 1000);
598 t += 200;
599 } while (t < 150000);
600 msleep(25);
601 }
392f8b78 602
7f2ac8fb 603 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 604
392f8b78
EG		 605 return ret;
606}
607
cf614297
EG		 608/*
609 * ucode
610 */
564cdce7
SS		 611static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
612 u32 dst_addr, dma_addr_t phy_addr,
613 u32 byte_cnt)
cf614297 614{
bac842da
EG		 615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
617
618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
619 dst_addr);
620
621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
623
624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
625 (iwl_get_dma_hi_addr(phy_addr)
626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
627
628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
632
633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 637}
638
564cdce7
SS		 639static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
640 u32 dst_addr, dma_addr_t phy_addr,
641 u32 byte_cnt)
642{
643 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
644 unsigned long flags;
645 int ret;
646
647 trans_pcie->ucode_write_complete = false;
648
649 if (!iwl_trans_grab_nic_access(trans, &flags))
650 return -EIO;
651
eda50cde
SS		 652 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
653 byte_cnt);
bac842da 654 iwl_trans_release_nic_access(trans, &flags);
cf614297 655
13df1aab
JB		 656 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
657 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 658 if (!ret) {
83f84d7b 659 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 660 return -ETIMEDOUT;
661 }
662
663 return 0;
664}
665
7afe3705 666static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 667 const struct fw_desc *section)
cf614297 668{
83f84d7b
JB		 669 u8 *v_addr;
670 dma_addr_t p_addr;
baa21e83 671 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 672 int ret = 0;
673
83f84d7b
JB		 674 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
675 section_num);
676
c571573a
EG		 677 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
678 GFP_KERNEL | __GFP_NOWARN);
679 if (!v_addr) {
680 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
681 chunk_sz = PAGE_SIZE;
682 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
683 &p_addr, GFP_KERNEL);
684 if (!v_addr)
685 return -ENOMEM;
686 }
83f84d7b 687
c571573a 688 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 689 u32 copy_size, dst_addr;
690 bool extended_addr = false;
83f84d7b 691
c571573a 692 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 693 dst_addr = section->offset + offset;
694
695 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
696 dst_addr <= IWL_FW_MEM_EXTENDED_END)
697 extended_addr = true;
698
699 if (extended_addr)
700 iwl_set_bits_prph(trans, LMPM_CHICK,
701 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 702
83f84d7b 703 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 704 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
705 copy_size);
706
707 if (extended_addr)
708 iwl_clear_bits_prph(trans, LMPM_CHICK,
709 LMPM_CHICK_EXTENDED_ADDR_SPACE);
710
83f84d7b
JB		 711 if (ret) {
712 IWL_ERR(trans,
713 "Could not load the [%d] uCode section\n",
714 section_num);
715 break;
6dfa8d01 716 }
83f84d7b
JB		 717 }
718
c571573a 719 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 720 return ret;
721}
722
5dd9c68a
EG		 723static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
724 const struct fw_img *image,
725 int cpu,
726 int *first_ucode_section)
e2d6f4e7
EH		 727{
728 int shift_param;
dcab8ecd
EH		 729 int i, ret = 0, sec_num = 0x1;
730 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 731
732 if (cpu == 1) {
733 shift_param = 0;
034846cf 734 *first_ucode_section = 0;
e2d6f4e7
EH		 735 } else {
736 shift_param = 16;
034846cf 737 (*first_ucode_section)++;
e2d6f4e7
EH		 738 }
739
eef187a7 740 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 741 last_read_idx = i;
742
a6c4fb44
MG		 743 /*
744 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
745 * CPU1 to CPU2.
746 * PAGING_SEPARATOR_SECTION delimiter - separate between
747 * CPU2 non paged to CPU2 paging sec.
748 */
034846cf 749 if (!image->sec[i].data ||
a6c4fb44
MG		 750 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
751 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 752 IWL_DEBUG_FW(trans,
753 "Break since Data not valid or Empty section, sec = %d\n",
754 i);
189fa2fa 755 break;
034846cf
EH		 756 }
757
189fa2fa
EH		 758 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
759 if (ret)
760 return ret;
dcab8ecd 761
d6a2c5c7 762 /* Notify ucode of loaded section number and status */
eda50cde
SS		 763 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
764 val = val | (sec_num << shift_param);
765 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
766
dcab8ecd 767 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 768 }
769
034846cf
EH		 770 *first_ucode_section = last_read_idx;
771
2aabdbdc
EG		 772 iwl_enable_interrupts(trans);
773
d6a2c5c7
SS		 774 if (trans->cfg->use_tfh) {
775 if (cpu == 1)
776 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
777 0xFFFF);
778 else
779 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
780 0xFFFFFFFF);
781 } else {
782 if (cpu == 1)
783 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
784 0xFFFF);
785 else
786 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
787 0xFFFFFFFF);
788 }
afb88917 789
189fa2fa
EH		 790 return 0;
791}
e2d6f4e7 792
189fa2fa
EH		 793static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
794 const struct fw_img *image,
034846cf
EH		 795 int cpu,
796 int *first_ucode_section)
189fa2fa 797{
189fa2fa 798 int i, ret = 0;
034846cf 799 u32 last_read_idx = 0;
189fa2fa 800
3ce4a038 801 if (cpu == 1)
034846cf 802 *first_ucode_section = 0;
3ce4a038 803 else
034846cf 804 (*first_ucode_section)++;
189fa2fa 805
eef187a7 806 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 807 last_read_idx = i;
808
a6c4fb44
MG		 809 /*
810 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
811 * CPU1 to CPU2.
812 * PAGING_SEPARATOR_SECTION delimiter - separate between
813 * CPU2 non paged to CPU2 paging sec.
814 */
034846cf 815 if (!image->sec[i].data ||
a6c4fb44
MG		 816 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
817 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 818 IWL_DEBUG_FW(trans,
819 "Break since Data not valid or Empty section, sec = %d\n",
820 i);
189fa2fa 821 break;
034846cf
EH		 822 }
823
189fa2fa
EH		 824 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
825 if (ret)
826 return ret;
e2d6f4e7
EH		 827 }
828
034846cf
EH		 829 *first_ucode_section = last_read_idx;
830
e2d6f4e7
EH		 831 return 0;
832}
833
c9be849d 834void iwl_pcie_apply_destination(struct iwl_trans *trans)
09e350f7
LK		 835{
836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
837 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
838 int i;
839
840 if (dest->version)
841 IWL_ERR(trans,
842 "DBG DEST version is %d - expect issues\n",
843 dest->version);
844
845 IWL_INFO(trans, "Applying debug destination %s\n",
846 get_fw_dbg_mode_string(dest->monitor_mode));
847
848 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 849 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 850 else
851 IWL_WARN(trans, "PCI should have external buffer debug\n");
852
853 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
854 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
855 u32 val = le32_to_cpu(dest->reg_ops[i].val);
856
857 switch (dest->reg_ops[i].op) {
858 case CSR_ASSIGN:
859 iwl_write32(trans, addr, val);
860 break;
861 case CSR_SETBIT:
862 iwl_set_bit(trans, addr, BIT(val));
863 break;
864 case CSR_CLEARBIT:
865 iwl_clear_bit(trans, addr, BIT(val));
866 break;
867 case PRPH_ASSIGN:
868 iwl_write_prph(trans, addr, val);
869 break;
870 case PRPH_SETBIT:
871 iwl_set_bits_prph(trans, addr, BIT(val));
872 break;
873 case PRPH_CLEARBIT:
874 iwl_clear_bits_prph(trans, addr, BIT(val));
875 break;
869f3b15
HD		 876 case PRPH_BLOCKBIT:
877 if (iwl_read_prph(trans, addr) & BIT(val)) {
878 IWL_ERR(trans,
879 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
880 val, addr);
881 goto monitor;
882 }
883 break;
09e350f7
LK		 884 default:
885 IWL_ERR(trans, "FW debug - unknown OP %d\n",
886 dest->reg_ops[i].op);
887 break;
888 }
889 }
890
869f3b15 891monitor:
09e350f7
LK		 892 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
893 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
894 trans_pcie->fw_mon_phys >> dest->base_shift);
62d7476d
EG		 895 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
896 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
897 (trans_pcie->fw_mon_phys +
898 trans_pcie->fw_mon_size - 256) >>
899 dest->end_shift);
900 else
901 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
902 (trans_pcie->fw_mon_phys +
903 trans_pcie->fw_mon_size) >>
904 dest->end_shift);
09e350f7
LK		 905 }
906}
907
7afe3705 908static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 909 const struct fw_img *image)
cf614297 910{
c2d20201 911 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 912 int ret = 0;
034846cf 913 int first_ucode_section;
cf614297 914
dcab8ecd 915 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 916 image->is_dual_cpus ? "Dual" : "Single");
917
dcab8ecd
EH		 918 /* load to FW the binary non secured sections of CPU1 */
919 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
920 if (ret)
921 return ret;
e2d6f4e7
EH		 922
923 if (image->is_dual_cpus) {
189fa2fa
EH		 924 /* set CPU2 header address */
925 iwl_write_prph(trans,
926 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
927 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 928
189fa2fa 929 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 930 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
931 &first_ucode_section);
189fa2fa
EH		 932 if (ret)
933 return ret;
e2d6f4e7 934 }
cf614297 935
c2d20201
EG		 936 /* supported for 7000 only for the moment */
937 if (iwlwifi_mod_params.fw_monitor &&
938 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 939 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 940
941 if (trans_pcie->fw_mon_size) {
942 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
943 trans_pcie->fw_mon_phys >> 4);
944 iwl_write_prph(trans, MON_BUFF_END_ADDR,
945 (trans_pcie->fw_mon_phys +
946 trans_pcie->fw_mon_size) >> 4);
947 }
09e350f7
LK		 948 } else if (trans->dbg_dest_tlv) {
949 iwl_pcie_apply_destination(trans);
c2d20201
EG		 950 }
951
2aabdbdc
EG		 952 iwl_enable_interrupts(trans);
953
e12ba844 954 /* release CPU reset */
5dd9c68a 955 iwl_write32(trans, CSR_RESET, 0);
e12ba844 956
dcab8ecd
EH		 957 return 0;
958}
189fa2fa 959
5dd9c68a
EG		 960static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
961 const struct fw_img *image)
dcab8ecd
EH		 962{
963 int ret = 0;
964 int first_ucode_section;
dcab8ecd
EH		 965
966 IWL_DEBUG_FW(trans, "working with %s CPU\n",
967 image->is_dual_cpus ? "Dual" : "Single");
968
a2227ce2
EG		 969 if (trans->dbg_dest_tlv)
970 iwl_pcie_apply_destination(trans);
971
82ea7966
SS		 972 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
973 iwl_read_prph(trans, WFPM_GP2));
974
975 /*
976 * Set default value. On resume reading the values that were
977 * zeored can provide debug data on the resume flow.
978 * This is for debugging only and has no functional impact.
979 */
980 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
981
dcab8ecd
EH		 982 /* configure the ucode to be ready to get the secured image */
983 /* release CPU reset */
984 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
985
986 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 987 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
988 &first_ucode_section);
dcab8ecd
EH		 989 if (ret)
990 return ret;
991
992 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 993 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
994 &first_ucode_section);
cf614297
EG		 995}
996
eda50cde 997bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans)
727c02df
SS		 998{
999 bool hw_rfkill = iwl_is_rfkill_set(trans);
1000
1001 if (hw_rfkill)
1002 set_bit(STATUS_RFKILL, &trans->status);
1003 else
1004 clear_bit(STATUS_RFKILL, &trans->status);
1005
1006 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1007
1008 return hw_rfkill;
1009}
1010
7ca00409
HD		 1011struct iwl_causes_list {
1012 u32 cause_num;
1013 u32 mask_reg;
1014 u8 addr;
1015};
1016
1017static struct iwl_causes_list causes_list[] = {
1018 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1019 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1020 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1021 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1022 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1023 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1024 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1025 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1026 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1027 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1028 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1029 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1030 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1031 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1032};
1033
1034static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1035{
1036 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1037 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1038 int i;
1039
1040 /*
1041 * Access all non RX causes and map them to the default irq.
1042 * In case we are missing at least one interrupt vector,
1043 * the first interrupt vector will serve non-RX and FBQ causes.
1044 */
1045 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1046 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1047 iwl_clear_bit(trans, causes_list[i].mask_reg,
1048 causes_list[i].cause_num);
1049 }
1050}
1051
1052static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1053{
1054 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1055 u32 offset =
1056 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1057 u32 val, idx;
1058
1059 /*
1060 * The first RX queue - fallback queue, which is designated for
1061 * management frame, command responses etc, is always mapped to the
1062 * first interrupt vector. The other RX queues are mapped to
1063 * the other (N - 2) interrupt vectors.
1064 */
1065 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1066 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1067 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1068 MSIX_FH_INT_CAUSES_Q(idx - offset));
1069 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1070 }
1071 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1072
1073 val = MSIX_FH_INT_CAUSES_Q(0);
1074 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1075 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1076 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1077
1078 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1079 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1080}
1081
77c09bc8 1082void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1083{
1084 struct iwl_trans *trans = trans_pcie->trans;
1085
1086 if (!trans_pcie->msix_enabled) {
d7270d61
HD		 1087 if (trans->cfg->mq_rx_supported &&
1088 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
7ca00409
HD		 1089 iwl_write_prph(trans, UREG_CHICK,
1090 UREG_CHICK_MSI_ENABLE);
1091 return;
1092 }
d7270d61
HD		 1093 /*
1094 * The IVAR table needs to be configured again after reset,
1095 * but if the device is disabled, we can't write to
1096 * prph.
1097 */
1098 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1099 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1100
1101 /*
1102 * Each cause from the causes list above and the RX causes is
1103 * represented as a byte in the IVAR table. The first nibble
1104 * represents the bound interrupt vector of the cause, the second
1105 * represents no auto clear for this cause. This will be set if its
1106 * interrupt vector is bound to serve other causes.
1107 */
1108 iwl_pcie_map_rx_causes(trans);
1109
1110 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1111}
1112
1113static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1114{
1115 struct iwl_trans *trans = trans_pcie->trans;
1116
1117 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1118
83730058
HD		 1119 if (!trans_pcie->msix_enabled)
1120 return;
1121
1122 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1123 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1124 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1125 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1126}
1127
fa9f3281 1128static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1129{
43e58856 1130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1131 bool hw_rfkill, was_hw_rfkill;
1132
fa9f3281
EG		 1133 lockdep_assert_held(&trans_pcie->mutex);
1134
1135 if (trans_pcie->is_down)
1136 return;
1137
1138 trans_pcie->is_down = true;
1139
3dc3374f 1140 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1141
43e58856 1142 /* tell the device to stop sending interrupts */
ae2c30bf 1143 iwl_disable_interrupts(trans);
ae2c30bf 1144
ab6cf8e8 1145 /* device going down, Stop using ICT table */
990aa6d7 1146 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1147
1148 /*
1149 * If a HW restart happens during firmware loading,
1150 * then the firmware loading might call this function
1151 * and later it might be called again due to the
1152 * restart. So don't process again if the device is
1153 * already dead.
1154 */
31b8b343 1155 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1156 IWL_DEBUG_INFO(trans,
1157 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1158 iwl_pcie_tx_stop(trans);
9805c446 1159 iwl_pcie_rx_stop(trans);
6379103e 1160
ab6cf8e8 1161 /* Power-down device's busmaster DMA clocks */
95411d04 1162 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1163 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1164 APMG_CLK_VAL_DMA_CLK_RQT);
1165 udelay(5);
1166 }
ab6cf8e8
EG		 1167 }
1168
1169 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1170 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1171 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1172
1173 /* Stop the device, and put it in low power state */
b7aaeae4 1174 iwl_pcie_apm_stop(trans, false);
43e58856 1175
03d6c3b0
EG		 1176 /* stop and reset the on-board processor */
1177 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1178 usleep_range(1000, 2000);
03d6c3b0 1179
f4a1f04a
GBA		 1180 /*
1181 * Upon stop, the IVAR table gets erased, so msi-x won't
1182 * work. This causes a bug in RF-KILL flows, since the interrupt
1183 * that enables radio won't fire on the correct irq, and the
1184 * driver won't be able to handle the interrupt.
1185 * Configure the IVAR table again after reset.
1186 */
1187 iwl_pcie_conf_msix_hw(trans_pcie);
1188
03d6c3b0
EG		 1189 /*
1190 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1191 * This is a bug in certain verions of the hardware.
1192 * Certain devices also keep sending HW RF kill interrupt all
1193 * the time, unless the interrupt is ACKed even if the interrupt
1194 * should be masked. Re-ACK all the interrupts here.
43e58856 1195 */
43e58856 1196 iwl_disable_interrupts(trans);
43e58856 1197
74fda971 1198 /* clear all status bits */
eb7ff77e
AN		 1199 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1200 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1201 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1202 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1203
1204 /*
1205 * Even if we stop the HW, we still want the RF kill
1206 * interrupt
1207 */
1208 iwl_enable_rfkill_int(trans);
1209
1210 /*
1211 * Check again since the RF kill state may have changed while
1212 * all the interrupts were disabled, in this case we couldn't
1213 * receive the RF kill interrupt and update the state in the
1214 * op_mode.
3dc3374f
EG		 1215 * Don't call the op_mode if the rkfill state hasn't changed.
1216 * This allows the op_mode to call stop_device from the rfkill
1217 * notification without endless recursion. Under very rare
1218 * circumstances, we might have a small recursion if the rfkill
1219 * state changed exactly now while we were called from stop_device.
1220 * This is very unlikely but can happen and is supported.
a4082843
AN		 1221 */
1222 hw_rfkill = iwl_is_rfkill_set(trans);
1223 if (hw_rfkill)
eb7ff77e 1224 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1225 else
eb7ff77e 1226 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1227 if (hw_rfkill != was_hw_rfkill)
14cfca71 1228 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0 1229
a6bd005f 1230 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1231 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1232}
1233
eda50cde 1234void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
2e5d4a8f
HD		 1235{
1236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1237
1238 if (trans_pcie->msix_enabled) {
1239 int i;
1240
496d83ca 1241 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1242 synchronize_irq(trans_pcie->msix_entries[i].vector);
1243 } else {
1244 synchronize_irq(trans_pcie->pci_dev->irq);
1245 }
1246}
1247
a6bd005f
EG		 1248static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1249 const struct fw_img *fw, bool run_in_rfkill)
1250{
1251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1252 bool hw_rfkill;
1253 int ret;
1254
1255 /* This may fail if AMT took ownership of the device */
1256 if (iwl_pcie_prepare_card_hw(trans)) {
1257 IWL_WARN(trans, "Exit HW not ready\n");
1258 ret = -EIO;
1259 goto out;
1260 }
1261
1262 iwl_enable_rfkill_int(trans);
1263
1264 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1265
1266 /*
1267 * We enabled the RF-Kill interrupt and the handler may very
1268 * well be running. Disable the interrupts to make sure no other
1269 * interrupt can be fired.
1270 */
1271 iwl_disable_interrupts(trans);
1272
1273 /* Make sure it finished running */
2e5d4a8f 1274 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1275
1276 mutex_lock(&trans_pcie->mutex);
1277
1278 /* If platform's RF_KILL switch is NOT set to KILL */
727c02df 1279 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
a6bd005f
EG		 1280 if (hw_rfkill && !run_in_rfkill) {
1281 ret = -ERFKILL;
1282 goto out;
1283 }
1284
1285 /* Someone called stop_device, don't try to start_fw */
1286 if (trans_pcie->is_down) {
1287 IWL_WARN(trans,
1288 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1289 ret = -EIO;
a6bd005f
EG		 1290 goto out;
1291 }
1292
1293 /* make sure rfkill handshake bits are cleared */
1294 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1295 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1296 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1297
1298 /* clear (again), then enable host interrupts */
1299 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1300
1301 ret = iwl_pcie_nic_init(trans);
1302 if (ret) {
1303 IWL_ERR(trans, "Unable to init nic\n");
1304 goto out;
1305 }
1306
1307 /*
1308 * Now, we load the firmware and don't want to be interrupted, even
1309 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1310 * FH_TX interrupt which is needed to load the firmware). If the
1311 * RF-Kill switch is toggled, we will find out after having loaded
1312 * the firmware and return the proper value to the caller.
1313 */
1314 iwl_enable_fw_load_int(trans);
1315
1316 /* really make sure rfkill handshake bits are cleared */
1317 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1318 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1319
1320 /* Load the given image to the HW */
1321 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1322 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1323 else
1324 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1325
1326 /* re-check RF-Kill state since we may have missed the interrupt */
727c02df 1327 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
a6bd005f
EG		 1328 if (hw_rfkill && !run_in_rfkill)
1329 ret = -ERFKILL;
1330
1331out:
1332 mutex_unlock(&trans_pcie->mutex);
1333 return ret;
1334}
1335
1336static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1337{
1338 iwl_pcie_reset_ict(trans);
1339 iwl_pcie_tx_start(trans, scd_addr);
1340}
1341
fa9f3281
EG		 1342static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1343{
1344 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1345
1346 mutex_lock(&trans_pcie->mutex);
1347 _iwl_trans_pcie_stop_device(trans, low_power);
1348 mutex_unlock(&trans_pcie->mutex);
1349}
1350
14cfca71
JB		 1351void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1352{
fa9f3281
EG		 1353 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1354 IWL_TRANS_GET_PCIE_TRANS(trans);
1355
1356 lockdep_assert_held(&trans_pcie->mutex);
1357
77c09bc8
SS		 1358 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1359 if (trans->cfg->gen2)
1360 _iwl_trans_pcie_gen2_stop_device(trans, true);
1361 else
1362 _iwl_trans_pcie_stop_device(trans, true);
1363 }
ab6cf8e8
EG		 1364}
1365
23ae6128
MG		 1366static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1367 bool reset)
2dd4f9f7 1368{
23ae6128 1369 if (!reset) {
6dfb36c8
EP		 1370 /* Enable persistence mode to avoid reset */
1371 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1372 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1373 }
1374
2dd4f9f7 1375 iwl_disable_interrupts(trans);
debff618
JB		 1376
1377 /*
1378 * in testing mode, the host stays awake and the
1379 * hardware won't be reset (not even partially)
1380 */
1381 if (test)
1382 return;
1383
ddaf5a5b
JB		 1384 iwl_pcie_disable_ict(trans);
1385
2e5d4a8f 1386 iwl_pcie_synchronize_irqs(trans);
33b56af1 1387
2dd4f9f7
JB		 1388 iwl_clear_bit(trans, CSR_GP_CNTRL,
1389 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1390 iwl_clear_bit(trans, CSR_GP_CNTRL,
1391 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1392
1316d595
SS		 1393 iwl_pcie_enable_rx_wake(trans, false);
1394
23ae6128 1395 if (reset) {
6dfb36c8
EP		 1396 /*
1397 * reset TX queues -- some of their registers reset during S3
1398 * so if we don't reset everything here the D3 image would try
1399 * to execute some invalid memory upon resume
1400 */
1401 iwl_trans_pcie_tx_reset(trans);
1402 }
ddaf5a5b
JB		 1403
1404 iwl_pcie_set_pwr(trans, true);
1405}
1406
1407static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1408 enum iwl_d3_status *status,
23ae6128 1409 bool test, bool reset)
ddaf5a5b 1410{
d7270d61 1411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1412 u32 val;
1413 int ret;
1414
debff618
JB		 1415 if (test) {
1416 iwl_enable_interrupts(trans);
1417 *status = IWL_D3_STATUS_ALIVE;
1418 return 0;
1419 }
1420
1316d595
SS		 1421 iwl_pcie_enable_rx_wake(trans, true);
1422
ddaf5a5b 1423 /*
d7270d61
HD		 1424 * Reconfigure IVAR table in case of MSIX or reset ict table in
1425 * MSI mode since HW reset erased it.
1426 * Also enables interrupts - none will happen as
1427 * the device doesn't know we're waking it up, only when
1428 * the opmode actually tells it after this call.
ddaf5a5b 1429 */
d7270d61
HD		 1430 iwl_pcie_conf_msix_hw(trans_pcie);
1431 if (!trans_pcie->msix_enabled)
1432 iwl_pcie_reset_ict(trans);
18dcb9a9 1433 iwl_enable_interrupts(trans);
ddaf5a5b
JB		 1434
1435 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1436 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1437
01e58a28
EG		 1438 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1439 udelay(2);
1440
ddaf5a5b
JB		 1441 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1442 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1443 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1444 25000);
7f2ac8fb 1445 if (ret < 0) {
ddaf5a5b
JB		 1446 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1447 return ret;
1448 }
1449
a3ead656
EG		 1450 iwl_pcie_set_pwr(trans, false);
1451
23ae6128 1452 if (!reset) {
6dfb36c8
EP		 1453 iwl_clear_bit(trans, CSR_GP_CNTRL,
1454 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1455 } else {
1456 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1457
6dfb36c8
EP		 1458 ret = iwl_pcie_rx_init(trans);
1459 if (ret) {
1460 IWL_ERR(trans,
1461 "Failed to resume the device (RX reset)\n");
1462 return ret;
1463 }
ddaf5a5b
JB		 1464 }
1465
82ea7966
SS		 1466 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1467 iwl_read_prph(trans, WFPM_GP2));
1468
a3ead656
EG		 1469 val = iwl_read32(trans, CSR_RESET);
1470 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1471 *status = IWL_D3_STATUS_RESET;
1472 else
1473 *status = IWL_D3_STATUS_ALIVE;
1474
ddaf5a5b 1475 return 0;
2dd4f9f7
JB		 1476}
1477
2e5d4a8f
HD		 1478static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1479 struct iwl_trans *trans)
1480{
1481 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
9fb064df 1482 int max_irqs, num_irqs, i, ret, nr_online_cpus;
2e5d4a8f 1483 u16 pci_cmd;
2e5d4a8f 1484
06f4b081
SS		 1485 if (!trans->cfg->mq_rx_supported)
1486 goto enable_msi;
1487
9fb064df
HD		 1488 nr_online_cpus = num_online_cpus();
1489 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1490 for (i = 0; i < max_irqs; i++)
1491 trans_pcie->msix_entries[i].entry = i;
496d83ca 1492
06f4b081
SS		 1493 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1494 MSIX_MIN_INTERRUPT_VECTORS,
1495 max_irqs);
1496 if (num_irqs < 0) {
2e5d4a8f 1497 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1498 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1499 num_irqs);
1500 goto enable_msi;
1501 }
1502 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1503
06f4b081
SS		 1504 IWL_DEBUG_INFO(trans,
1505 "MSI-X enabled. %d interrupt vectors were allocated\n",
1506 num_irqs);
1507
1508 /*
1509 * In case the OS provides fewer interrupts than requested, different
1510 * causes will share the same interrupt vector as follows:
1511 * One interrupt less: non rx causes shared with FBQ.
1512 * Two interrupts less: non rx causes shared with FBQ and RSS.
1513 * More than two interrupts: we will use fewer RSS queues.
1514 */
9fb064df 1515 if (num_irqs <= nr_online_cpus) {
06f4b081
SS		 1516 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1517 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1518 IWL_SHARED_IRQ_FIRST_RSS;
9fb064df 1519 } else if (num_irqs == nr_online_cpus + 1) {
06f4b081
SS		 1520 trans_pcie->trans->num_rx_queues = num_irqs;
1521 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1522 } else {
1523 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f
HD		 1524 }
1525
06f4b081
SS		 1526 trans_pcie->alloc_vecs = num_irqs;
1527 trans_pcie->msix_enabled = true;
1528 return;
1529
1530enable_msi:
1531 ret = pci_enable_msi(pdev);
1532 if (ret) {
1533 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1534 /* enable rfkill interrupt: hw bug w/a */
1535 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1536 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1537 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1538 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1539 }
1540 }
1541}
1542
7c8d91eb
HD		 1543static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1544{
1545 int iter_rx_q, i, ret, cpu, offset;
1546 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1547
1548 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1549 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1550 offset = 1 + i;
1551 for (; i < iter_rx_q ; i++) {
1552 /*
1553 * Get the cpu prior to the place to search
1554 * (i.e. return will be > i - 1).
1555 */
1556 cpu = cpumask_next(i - offset, cpu_online_mask);
1557 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1558 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1559 &trans_pcie->affinity_mask[i]);
1560 if (ret)
1561 IWL_ERR(trans_pcie->trans,
1562 "Failed to set affinity mask for IRQ %d\n",
1563 i);
1564 }
1565}
1566
64fa3aff
SD		 1567static const char *queue_name(struct device *dev,
1568 struct iwl_trans_pcie *trans_p, int i)
1569{
1570 if (trans_p->shared_vec_mask) {
1571 int vec = trans_p->shared_vec_mask &
1572 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1573
1574 if (i == 0)
1575 return DRV_NAME ": shared IRQ";
1576
1577 return devm_kasprintf(dev, GFP_KERNEL,
1578 DRV_NAME ": queue %d", i + vec);
1579 }
1580 if (i == 0)
1581 return DRV_NAME ": default queue";
1582
1583 if (i == trans_p->alloc_vecs - 1)
1584 return DRV_NAME ": exception";
1585
1586 return devm_kasprintf(dev, GFP_KERNEL,
1587 DRV_NAME ": queue %d", i);
1588}
1589
2e5d4a8f
HD		 1590static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1591 struct iwl_trans_pcie *trans_pcie)
1592{
496d83ca 1593 int i;
2e5d4a8f 1594
496d83ca 1595 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1596 int ret;
5a41a86c 1597 struct msix_entry *msix_entry;
64fa3aff
SD		 1598 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1599
1600 if (!qname)
1601 return -ENOMEM;
5a41a86c
SD		 1602
1603 msix_entry = &trans_pcie->msix_entries[i];
1604 ret = devm_request_threaded_irq(&pdev->dev,
1605 msix_entry->vector,
1606 iwl_pcie_msix_isr,
1607 (i == trans_pcie->def_irq) ?
1608 iwl_pcie_irq_msix_handler :
1609 iwl_pcie_irq_rx_msix_handler,
1610 IRQF_SHARED,
64fa3aff 1611 qname,
5a41a86c 1612 msix_entry);
2e5d4a8f 1613 if (ret) {
2e5d4a8f
HD		 1614 IWL_ERR(trans_pcie->trans,
1615 "Error allocating IRQ %d\n", i);
5a41a86c 1616
2e5d4a8f
HD		 1617 return ret;
1618 }
1619 }
7c8d91eb 1620 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1621
1622 return 0;
1623}
1624
fa9f3281 1625static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1626{
fa9f3281 1627 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a8b691e6 1628 int err;
e6bb4c9c 1629
fa9f3281
EG		 1630 lockdep_assert_held(&trans_pcie->mutex);
1631
7afe3705 1632 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1633 if (err) {
d6f1c316 1634 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1635 return err;
ebb7678d 1636 }
a6c684ee 1637
2997494f 1638 /* Reset the entire device */
ce836c76 1639 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1640 usleep_range(1000, 2000);
2997494f 1641
7afe3705 1642 iwl_pcie_apm_init(trans);
a6c684ee 1643
2e5d4a8f 1644 iwl_pcie_init_msix(trans_pcie);
83730058 1645
226c02ca
EG		 1646 /* From now on, the op_mode will be kept updated about RF kill state */
1647 iwl_enable_rfkill_int(trans);
1648
fa9f3281
EG		 1649 /* Set is_down to false here so that...*/
1650 trans_pcie->is_down = false;
1651
727c02df
SS		 1652 /* ...rfkill can call stop_device and set it false if needed */
1653 iwl_trans_check_hw_rf_kill(trans);
d48e2074 1654
4cbb8e50
LC		 1655 /* Make sure we sync here, because we'll need full access later */
1656 if (low_power)
1657 pm_runtime_resume(trans->dev);
1658
a8b691e6 1659 return 0;
e6bb4c9c
EG		 1660}
1661
fa9f3281
EG		 1662static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1663{
1664 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1665 int ret;
1666
1667 mutex_lock(&trans_pcie->mutex);
1668 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1669 mutex_unlock(&trans_pcie->mutex);
1670
1671 return ret;
1672}
1673
a4082843 1674static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1675{
20d3b647 1676 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1677
fa9f3281
EG		 1678 mutex_lock(&trans_pcie->mutex);
1679
a4082843 1680 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1681 iwl_disable_interrupts(trans);
ee7d737c 1682
b7aaeae4 1683 iwl_pcie_apm_stop(trans, true);
cc56feb2 1684
218733cf 1685 iwl_disable_interrupts(trans);
1df06bdc 1686
8d96bb61 1687 iwl_pcie_disable_ict(trans);
33b56af1 1688
fa9f3281 1689 mutex_unlock(&trans_pcie->mutex);
33b56af1 1690
2e5d4a8f 1691 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1692}
1693
03905495
EG		 1694static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1695{
05f5b97e 1696 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1697}
1698
1699static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1700{
05f5b97e 1701 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1702}
1703
1704static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1705{
05f5b97e 1706 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1707}
1708
6a06b6c1
EG		 1709static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1710{
f9477c17
AP		 1711 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1712 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1713 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1714}
1715
1716static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1717 u32 val)
1718{
1719 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1720 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1721 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1722}
1723
c6f600fc 1724static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1725 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1726{
1727 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1728
1729 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1730 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1731 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1732 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1733 trans_pcie->n_no_reclaim_cmds = 0;
1734 else
1735 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1736 if (trans_pcie->n_no_reclaim_cmds)
1737 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1738 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1739
6c4fbcbc
EG		 1740 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1741 trans_pcie->rx_page_order =
1742 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1743
046db346 1744 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1745 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1746 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1747
21cb3222
JB		 1748 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1749 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1750
39bdb17e
SD		 1751 trans->command_groups = trans_cfg->command_groups;
1752 trans->command_groups_size = trans_cfg->command_groups_size;
1753
f14d6b39
JB		 1754 /* Initialize NAPI here - it should be before registering to mac80211
1755 * in the opmode but after the HW struct is allocated.
1756 * As this function may be called again in some corner cases don't
1757 * do anything if NAPI was already initialized.
1758 */
bce97731 1759 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1760 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1761}
1762
d1ff5253 1763void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1764{
20d3b647 1765 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1766 int i;
a42a1844 1767
2e5d4a8f 1768 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1769
13a3a390
SS		 1770 if (trans->cfg->gen2)
1771 iwl_pcie_gen2_tx_free(trans);
1772 else
1773 iwl_pcie_tx_free(trans);
9805c446 1774 iwl_pcie_rx_free(trans);
6379103e 1775
2e5d4a8f 1776 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1777 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1778 irq_set_affinity_hint(
1779 trans_pcie->msix_entries[i].vector,
1780 NULL);
7c8d91eb 1781 }
2e5d4a8f 1782
2e5d4a8f
HD		 1783 trans_pcie->msix_enabled = false;
1784 } else {
2e5d4a8f 1785 iwl_pcie_free_ict(trans);
2e5d4a8f 1786 }
a42a1844 1787
c2d20201
EG		 1788 iwl_pcie_free_fw_monitor(trans);
1789
6eb5e529
EG		 1790 for_each_possible_cpu(i) {
1791 struct iwl_tso_hdr_page *p =
1792 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1793
1794 if (p->page)
1795 __free_page(p->page);
1796 }
1797
1798 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1799 mutex_destroy(&trans_pcie->mutex);
7b501d10 1800 iwl_trans_free(trans);
34c1b7ba
EG		 1801}
1802
47107e84
DF		 1803static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1804{
47107e84 1805 if (state)
eb7ff77e 1806 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1807 else
eb7ff77e 1808 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1809}
1810
23ba9340
EG		 1811static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1812 unsigned long *flags)
7a65d170
EG		 1813{
1814 int ret;
cfb4e624
JB		 1815 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1816
1817 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1818
fc8a350d 1819 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1820 goto out;
1821
7a65d170 1822 /* this bit wakes up the NIC */
e139dc4a
LE		 1823 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1824 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1825 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1826 udelay(2);
7a65d170
EG		 1827
1828 /*
1829 * These bits say the device is running, and should keep running for
1830 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1831 * but they do not indicate that embedded SRAM is restored yet;
1832 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1833 * to/from host DRAM when sleeping/waking for power-saving.
1834 * Each direction takes approximately 1/4 millisecond; with this
1835 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1836 * series of register accesses are expected (e.g. reading Event Log),
1837 * to keep device from sleeping.
1838 *
1839 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1840 * SRAM is okay/restored. We don't check that here because this call
1841 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1842 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1843 *
1844 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1845 * and do not save/restore SRAM when power cycling.
1846 */
1847 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1848 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1849 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1850 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1851 if (unlikely(ret < 0)) {
1852 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1853 WARN_ONCE(1,
1854 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1855 iwl_read32(trans, CSR_GP_CNTRL));
1856 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1857 return false;
7a65d170
EG		 1858 }
1859
b9439491 1860out:
e56b04ef
LE		 1861 /*
1862 * Fool sparse by faking we release the lock - sparse will
1863 * track nic_access anyway.
1864 */
cfb4e624 1865 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1866 return true;
1867}
1868
e56b04ef
LE		 1869static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1870 unsigned long *flags)
7a65d170 1871{
cfb4e624 1872 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1873
cfb4e624 1874 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1875
1876 /*
1877 * Fool sparse by faking we acquiring the lock - sparse will
1878 * track nic_access anyway.
1879 */
cfb4e624 1880 __acquire(&trans_pcie->reg_lock);
e56b04ef 1881
fc8a350d 1882 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1883 goto out;
1884
e139dc4a
LE		 1885 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1886 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1887 /*
1888 * Above we read the CSR_GP_CNTRL register, which will flush
1889 * any previous writes, but we need the write that clears the
1890 * MAC_ACCESS_REQ bit to be performed before any other writes
1891 * scheduled on different CPUs (after we drop reg_lock).
1892 */
1893 mmiowb();
b9439491 1894out:
cfb4e624 1895 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1896}
1897
4fd442db
EG		 1898static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1899 void *buf, int dwords)
1900{
1901 unsigned long flags;
1902 int offs, ret = 0;
1903 u32 *vals = buf;
1904
23ba9340 1905 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1906 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1907 for (offs = 0; offs < dwords; offs++)
1908 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1909 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1910 } else {
1911 ret = -EBUSY;
1912 }
4fd442db
EG		 1913 return ret;
1914}
1915
1916static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1917 const void *buf, int dwords)
4fd442db
EG		 1918{
1919 unsigned long flags;
1920 int offs, ret = 0;
bf0fd5da 1921 const u32 *vals = buf;
4fd442db 1922
23ba9340 1923 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1924 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1925 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1926 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1927 vals ? vals[offs] : 0);
e56b04ef 1928 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1929 } else {
1930 ret = -EBUSY;
1931 }
4fd442db
EG		 1932 return ret;
1933}
7a65d170 1934
e0b8d405
EG		 1935static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1936 unsigned long txqs,
1937 bool freeze)
1938{
1939 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1940 int queue;
1941
1942 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
b2a3b1c1 1943 struct iwl_txq *txq = trans_pcie->txq[queue];
e0b8d405
EG		 1944 unsigned long now;
1945
1946 spin_lock_bh(&txq->lock);
1947
1948 now = jiffies;
1949
1950 if (txq->frozen == freeze)
1951 goto next_queue;
1952
1953 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1954 freeze ? "Freezing" : "Waking", queue);
1955
1956 txq->frozen = freeze;
1957
bb98ecd4 1958 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 1959 goto next_queue;
1960
1961 if (freeze) {
1962 if (unlikely(time_after(now,
1963 txq->stuck_timer.expires))) {
1964 /*
1965 * The timer should have fired, maybe it is
1966 * spinning right now on the lock.
1967 */
1968 goto next_queue;
1969 }
1970 /* remember how long until the timer fires */
1971 txq->frozen_expiry_remainder =
1972 txq->stuck_timer.expires - now;
1973 del_timer(&txq->stuck_timer);
1974 goto next_queue;
1975 }
1976
1977 /*
1978 * Wake a non-empty queue -> arm timer with the
1979 * remainder before it froze
1980 */
1981 mod_timer(&txq->stuck_timer,
1982 now + txq->frozen_expiry_remainder);
1983
1984next_queue:
1985 spin_unlock_bh(&txq->lock);
1986 }
1987}
1988
0cd58eaa
EG		 1989static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1990{
1991 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1992 int i;
1993
1994 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
b2a3b1c1 1995 struct iwl_txq *txq = trans_pcie->txq[i];
0cd58eaa
EG		 1996
1997 if (i == trans_pcie->cmd_queue)
1998 continue;
1999
2000 spin_lock_bh(&txq->lock);
2001
2002 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2003 txq->block--;
2004 if (!txq->block) {
2005 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2006 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2007 }
2008 } else if (block) {
2009 txq->block++;
2010 }
2011
2012 spin_unlock_bh(&txq->lock);
2013 }
2014}
2015
5f178cd2
EG		 2016#define IWL_FLUSH_WAIT_MS 2000
2017
38398efb
SS		 2018void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2019{
afb84431
EG		 2020 u32 txq_id = txq->id;
2021 u32 status;
2022 bool active;
2023 u8 fifo;
38398efb 2024
afb84431
EG		 2025 if (trans->cfg->use_tfh) {
2026 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2027 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2028 /* TODO: access new SCD registers and dump them */
2029 return;
38398efb 2030 }
afb84431
EG		 2031
2032 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2033 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2034 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2035
2036 IWL_ERR(trans,
2037 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2038 txq_id, active ? "" : "in", fifo,
2039 jiffies_to_msecs(txq->wd_timeout),
2040 txq->read_ptr, txq->write_ptr,
2041 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2042 (TFD_QUEUE_SIZE_MAX - 1),
2043 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2044 (TFD_QUEUE_SIZE_MAX - 1),
2045 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2046}
2047
3cafdbe6 2048static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 2049{
8ad71bef 2050 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2051 struct iwl_txq *txq;
5f178cd2
EG		 2052 int cnt;
2053 unsigned long now = jiffies;
2054 int ret = 0;
2055
2056 /* waiting for all the tx frames complete might take a while */
035f7ff2 2057 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 2058 u8 wr_ptr;
2059
9ba1947a 2060 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2061 continue;
3cafdbe6
EG		 2062 if (!test_bit(cnt, trans_pcie->queue_used))
2063 continue;
2064 if (!(BIT(cnt) & txq_bm))
2065 continue;
748fa67c
EG		 2066
2067 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
b2a3b1c1 2068 txq = trans_pcie->txq[cnt];
bb98ecd4 2069 wr_ptr = ACCESS_ONCE(txq->write_ptr);
fa1a91fd 2070
bb98ecd4 2071 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
fa1a91fd
EG		 2072 !time_after(jiffies,
2073 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
bb98ecd4 2074 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
fa1a91fd
EG		 2075
2076 if (WARN_ONCE(wr_ptr != write_ptr,
2077 "WR pointer moved while flushing %d -> %d\n",
2078 wr_ptr, write_ptr))
2079 return -ETIMEDOUT;
192185d6 2080 usleep_range(1000, 2000);
fa1a91fd 2081 }
5f178cd2 2082
bb98ecd4 2083 if (txq->read_ptr != txq->write_ptr) {
1c3fea82
EG		 2084 IWL_ERR(trans,
2085 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 2086 ret = -ETIMEDOUT;
2087 break;
2088 }
748fa67c 2089 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 2090 }
1c3fea82 2091
38398efb
SS		 2092 if (ret)
2093 iwl_trans_pcie_log_scd_error(trans, txq);
1c3fea82 2094
5f178cd2
EG		 2095 return ret;
2096}
2097
e139dc4a
LE		 2098static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2099 u32 mask, u32 value)
2100{
e56b04ef 2101 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2102 unsigned long flags;
2103
e56b04ef 2104 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2105 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2106 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2107}
2108
c24c7f58 2109static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2110{
2111 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2112
2113 if (iwlwifi_mod_params.d0i3_disable)
2114 return;
2115
b3ff1270 2116 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2117
2118#ifdef CONFIG_PM
2119 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2120 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2121#endif /* CONFIG_PM */
7616f334
EP		 2122}
2123
c24c7f58 2124static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2125{
2126 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2127
2128 if (iwlwifi_mod_params.d0i3_disable)
2129 return;
2130
b3ff1270
LC		 2131 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2132 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2133
5d93f3a2
LC		 2134#ifdef CONFIG_PM
2135 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2136 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2137#endif /* CONFIG_PM */
7616f334
EP		 2138}
2139
ff620849
EG		 2140static const char *get_csr_string(int cmd)
2141{
d9fb6465 2142#define IWL_CMD(x) case x: return #x
ff620849
EG		 2143 switch (cmd) {
2144 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2145 IWL_CMD(CSR_INT_COALESCING);
2146 IWL_CMD(CSR_INT);
2147 IWL_CMD(CSR_INT_MASK);
2148 IWL_CMD(CSR_FH_INT_STATUS);
2149 IWL_CMD(CSR_GPIO_IN);
2150 IWL_CMD(CSR_RESET);
2151 IWL_CMD(CSR_GP_CNTRL);
2152 IWL_CMD(CSR_HW_REV);
2153 IWL_CMD(CSR_EEPROM_REG);
2154 IWL_CMD(CSR_EEPROM_GP);
2155 IWL_CMD(CSR_OTP_GP_REG);
2156 IWL_CMD(CSR_GIO_REG);
2157 IWL_CMD(CSR_GP_UCODE_REG);
2158 IWL_CMD(CSR_GP_DRIVER_REG);
2159 IWL_CMD(CSR_UCODE_DRV_GP1);
2160 IWL_CMD(CSR_UCODE_DRV_GP2);
2161 IWL_CMD(CSR_LED_REG);
2162 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2163 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2164 IWL_CMD(CSR_ANA_PLL_CFG);
2165 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2166 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2167 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2168 default:
2169 return "UNKNOWN";
2170 }
d9fb6465 2171#undef IWL_CMD
ff620849
EG		 2172}
2173
990aa6d7 2174void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2175{
2176 int i;
2177 static const u32 csr_tbl[] = {
2178 CSR_HW_IF_CONFIG_REG,
2179 CSR_INT_COALESCING,
2180 CSR_INT,
2181 CSR_INT_MASK,
2182 CSR_FH_INT_STATUS,
2183 CSR_GPIO_IN,
2184 CSR_RESET,
2185 CSR_GP_CNTRL,
2186 CSR_HW_REV,
2187 CSR_EEPROM_REG,
2188 CSR_EEPROM_GP,
2189 CSR_OTP_GP_REG,
2190 CSR_GIO_REG,
2191 CSR_GP_UCODE_REG,
2192 CSR_GP_DRIVER_REG,
2193 CSR_UCODE_DRV_GP1,
2194 CSR_UCODE_DRV_GP2,
2195 CSR_LED_REG,
2196 CSR_DRAM_INT_TBL_REG,
2197 CSR_GIO_CHICKEN_BITS,
2198 CSR_ANA_PLL_CFG,
a812cba9 2199 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2200 CSR_HW_REV_WA_REG,
2201 CSR_DBG_HPET_MEM_REG
2202 };
2203 IWL_ERR(trans, "CSR values:\n");
2204 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2205 "CSR_INT_PERIODIC_REG)\n");
2206 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2207 IWL_ERR(trans, " %25s: 0X%08x\n",
2208 get_csr_string(csr_tbl[i]),
1042db2a 2209 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2210 }
2211}
2212
87e5666c
EG		 2213#ifdef CONFIG_IWLWIFI_DEBUGFS
2214/* create and remove of files */
2215#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2216 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2217 &iwl_dbgfs_##name##_ops)) \
9da987ac 2218 goto err; \
87e5666c
EG		 2219} while (0)
2220
2221/* file operation */
87e5666c 2222#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2223static const struct file_operations iwl_dbgfs_##name##_ops = { \
2224 .read = iwl_dbgfs_##name##_read, \
234e3405 2225 .open = simple_open, \
87e5666c
EG		 2226 .llseek = generic_file_llseek, \
2227};
2228
16db88ba 2229#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2230static const struct file_operations iwl_dbgfs_##name##_ops = { \
2231 .write = iwl_dbgfs_##name##_write, \
234e3405 2232 .open = simple_open, \
16db88ba
EG		 2233 .llseek = generic_file_llseek, \
2234};
2235
87e5666c 2236#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2237static const struct file_operations iwl_dbgfs_##name##_ops = { \
2238 .write = iwl_dbgfs_##name##_write, \
2239 .read = iwl_dbgfs_##name##_read, \
234e3405 2240 .open = simple_open, \
87e5666c
EG		 2241 .llseek = generic_file_llseek, \
2242};
2243
87e5666c 2244static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2245 char __user *user_buf,
2246 size_t count, loff_t *ppos)
8ad71bef 2247{
5a878bf6 2248 struct iwl_trans *trans = file->private_data;
8ad71bef 2249 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2250 struct iwl_txq *txq;
87e5666c
EG		 2251 char *buf;
2252 int pos = 0;
2253 int cnt;
2254 int ret;
1745e440
WYG		 2255 size_t bufsz;
2256
e0b8d405 2257 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2258
b2a3b1c1 2259 if (!trans_pcie->txq_memory)
87e5666c 2260 return -EAGAIN;
f9e75447 2261
87e5666c
EG		 2262 buf = kzalloc(bufsz, GFP_KERNEL);
2263 if (!buf)
2264 return -ENOMEM;
2265
035f7ff2 2266 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
b2a3b1c1 2267 txq = trans_pcie->txq[cnt];
87e5666c 2268 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2269 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2270 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2271 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2272 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2273 txq->need_update, txq->frozen,
f40faf62 2274 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2275 }
2276 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2277 kfree(buf);
2278 return ret;
2279}
2280
2281static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2282 char __user *user_buf,
2283 size_t count, loff_t *ppos)
2284{
5a878bf6 2285 struct iwl_trans *trans = file->private_data;
20d3b647 2286 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2287 char *buf;
2288 int pos = 0, i, ret;
2289 size_t bufsz = sizeof(buf);
2290
2291 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2292
2293 if (!trans_pcie->rxq)
2294 return -EAGAIN;
2295
2296 buf = kzalloc(bufsz, GFP_KERNEL);
2297 if (!buf)
2298 return -ENOMEM;
2299
2300 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2301 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2302
2303 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2304 i);
2305 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2306 rxq->read);
2307 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2308 rxq->write);
2309 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2310 rxq->write_actual);
2311 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2312 rxq->need_update);
2313 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2314 rxq->free_count);
2315 if (rxq->rb_stts) {
2316 pos += scnprintf(buf + pos, bufsz - pos,
2317 "\tclosed_rb_num: %u\n",
2318 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2319 0x0FFF);
2320 } else {
2321 pos += scnprintf(buf + pos, bufsz - pos,
2322 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2323 }
87e5666c 2324 }
78485054
SS		 2325 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2326 kfree(buf);
2327
2328 return ret;
87e5666c
EG		 2329}
2330
1f7b6172
EG		 2331static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2332 char __user *user_buf,
20d3b647
JB		 2333 size_t count, loff_t *ppos)
2334{
1f7b6172 2335 struct iwl_trans *trans = file->private_data;
20d3b647 2336 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2337 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2338
2339 int pos = 0;
2340 char *buf;
2341 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2342 ssize_t ret;
2343
2344 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2345 if (!buf)
1f7b6172 2346 return -ENOMEM;
1f7b6172
EG		 2347
2348 pos += scnprintf(buf + pos, bufsz - pos,
2349 "Interrupt Statistics Report:\n");
2350
2351 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2352 isr_stats->hw);
2353 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2354 isr_stats->sw);
2355 if (isr_stats->sw || isr_stats->hw) {
2356 pos += scnprintf(buf + pos, bufsz - pos,
2357 "\tLast Restarting Code: 0x%X\n",
2358 isr_stats->err_code);
2359 }
2360#ifdef CONFIG_IWLWIFI_DEBUG
2361 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2362 isr_stats->sch);
2363 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2364 isr_stats->alive);
2365#endif
2366 pos += scnprintf(buf + pos, bufsz - pos,
2367 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2368
2369 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2370 isr_stats->ctkill);
2371
2372 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2373 isr_stats->wakeup);
2374
2375 pos += scnprintf(buf + pos, bufsz - pos,
2376 "Rx command responses:\t\t %u\n", isr_stats->rx);
2377
2378 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2379 isr_stats->tx);
2380
2381 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2382 isr_stats->unhandled);
2383
2384 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2385 kfree(buf);
2386 return ret;
2387}
2388
2389static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2390 const char __user *user_buf,
2391 size_t count, loff_t *ppos)
2392{
2393 struct iwl_trans *trans = file->private_data;
20d3b647 2394 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2395 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2396
2397 char buf[8];
2398 int buf_size;
2399 u32 reset_flag;
2400
2401 memset(buf, 0, sizeof(buf));
2402 buf_size = min(count, sizeof(buf) - 1);
2403 if (copy_from_user(buf, user_buf, buf_size))
2404 return -EFAULT;
2405 if (sscanf(buf, "%x", &reset_flag) != 1)
2406 return -EFAULT;
2407 if (reset_flag == 0)
2408 memset(isr_stats, 0, sizeof(*isr_stats));
2409
2410 return count;
2411}
2412
16db88ba 2413static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2414 const char __user *user_buf,
2415 size_t count, loff_t *ppos)
16db88ba
EG		 2416{
2417 struct iwl_trans *trans = file->private_data;
2418 char buf[8];
2419 int buf_size;
2420 int csr;
2421
2422 memset(buf, 0, sizeof(buf));
2423 buf_size = min(count, sizeof(buf) - 1);
2424 if (copy_from_user(buf, user_buf, buf_size))
2425 return -EFAULT;
2426 if (sscanf(buf, "%d", &csr) != 1)
2427 return -EFAULT;
2428
990aa6d7 2429 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2430
2431 return count;
2432}
2433
16db88ba 2434static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2435 char __user *user_buf,
2436 size_t count, loff_t *ppos)
16db88ba
EG		 2437{
2438 struct iwl_trans *trans = file->private_data;
94543a8d 2439 char *buf = NULL;
56c2477f 2440 ssize_t ret;
16db88ba 2441
56c2477f
JB		 2442 ret = iwl_dump_fh(trans, &buf);
2443 if (ret < 0)
2444 return ret;
2445 if (!buf)
2446 return -EINVAL;
2447 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2448 kfree(buf);
16db88ba
EG		 2449 return ret;
2450}
2451
1f7b6172 2452DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2453DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2454DEBUGFS_READ_FILE_OPS(rx_queue);
2455DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2456DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c 2457
f8a1edb7
JB		 2458/* Create the debugfs files and directories */
2459int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2460{
f8a1edb7
JB		 2461 struct dentry *dir = trans->dbgfs_dir;
2462
87e5666c
EG		 2463 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2464 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2465 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2466 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2467 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2468 return 0;
9da987ac
MV		 2469
2470err:
2471 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2472 return -ENOMEM;
87e5666c 2473}
aadede6e 2474#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2475
6983ba69 2476static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2477{
3cd1980b 2478 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2479 u32 cmdlen = 0;
2480 int i;
2481
3cd1980b 2482 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2483 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2484
2485 return cmdlen;
2486}
2487
bd7fc617
EG		 2488static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2489 struct iwl_fw_error_dump_data **data,
2490 int allocated_rb_nums)
2491{
2492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2493 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2494 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2495 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2496 u32 i, r, j, rb_len = 0;
2497
2498 spin_lock(&rxq->lock);
2499
2500 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2501
2502 for (i = rxq->read, j = 0;
2503 i != r && j < allocated_rb_nums;
2504 i = (i + 1) & RX_QUEUE_MASK, j++) {
2505 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2506 struct iwl_fw_error_dump_rb *rb;
2507
2508 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2509 DMA_FROM_DEVICE);
2510
2511 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2512
2513 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2514 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2515 rb = (void *)(*data)->data;
2516 rb->index = cpu_to_le32(i);
2517 memcpy(rb->data, page_address(rxb->page), max_len);
2518 /* remap the page for the free benefit */
2519 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2520 max_len,
2521 DMA_FROM_DEVICE);
2522
2523 *data = iwl_fw_error_next_data(*data);
2524 }
2525
2526 spin_unlock(&rxq->lock);
2527
2528 return rb_len;
2529}
473ad712
EG		 2530#define IWL_CSR_TO_DUMP (0x250)
2531
2532static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2533 struct iwl_fw_error_dump_data **data)
2534{
2535 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2536 __le32 *val;
2537 int i;
2538
2539 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2540 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2541 val = (void *)(*data)->data;
2542
2543 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2544 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2545
2546 *data = iwl_fw_error_next_data(*data);
2547
2548 return csr_len;
2549}
2550
06d51e0d
LK		 2551static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2552 struct iwl_fw_error_dump_data **data)
2553{
2554 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2555 unsigned long flags;
2556 __le32 *val;
2557 int i;
2558
23ba9340 2559 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2560 return 0;
2561
2562 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2563 (*data)->len = cpu_to_le32(fh_regs_len);
2564 val = (void *)(*data)->data;
2565
2566 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2567 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2568
2569 iwl_trans_release_nic_access(trans, &flags);
2570
2571 *data = iwl_fw_error_next_data(*data);
2572
2573 return sizeof(**data) + fh_regs_len;
2574}
2575
cc79ef66
LK		 2576static u32
2577iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2578 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2579 u32 monitor_len)
2580{
2581 u32 buf_size_in_dwords = (monitor_len >> 2);
2582 u32 *buffer = (u32 *)fw_mon_data->data;
2583 unsigned long flags;
2584 u32 i;
2585
23ba9340 2586 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2587 return 0;
2588
14ef1b43 2589 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2590 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2591 buffer[i] = iwl_read_prph_no_grab(trans,
2592 MON_DMARB_RD_DATA_ADDR);
2593 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2594
2595 iwl_trans_release_nic_access(trans, &flags);
2596
2597 return monitor_len;
2598}
2599
36fb9017
OG		 2600static u32
2601iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2602 struct iwl_fw_error_dump_data **data,
2603 u32 monitor_len)
2604{
2605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2606 u32 len = 0;
2607
2608 if ((trans_pcie->fw_mon_page &&
2609 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2610 trans->dbg_dest_tlv) {
2611 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2612 u32 base, write_ptr, wrap_cnt;
2613
2614 /* If there was a dest TLV - use the values from there */
2615 if (trans->dbg_dest_tlv) {
2616 write_ptr =
2617 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2618 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2619 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2620 } else {
2621 base = MON_BUFF_BASE_ADDR;
2622 write_ptr = MON_BUFF_WRPTR;
2623 wrap_cnt = MON_BUFF_CYCLE_CNT;
2624 }
2625
2626 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2627 fw_mon_data = (void *)(*data)->data;
2628 fw_mon_data->fw_mon_wr_ptr =
2629 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2630 fw_mon_data->fw_mon_cycle_cnt =
2631 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2632 fw_mon_data->fw_mon_base_ptr =
2633 cpu_to_le32(iwl_read_prph(trans, base));
2634
2635 len += sizeof(**data) + sizeof(*fw_mon_data);
2636 if (trans_pcie->fw_mon_page) {
2637 /*
2638 * The firmware is now asserted, it won't write anything
2639 * to the buffer. CPU can take ownership to fetch the
2640 * data. The buffer will be handed back to the device
2641 * before the firmware will be restarted.
2642 */
2643 dma_sync_single_for_cpu(trans->dev,
2644 trans_pcie->fw_mon_phys,
2645 trans_pcie->fw_mon_size,
2646 DMA_FROM_DEVICE);
2647 memcpy(fw_mon_data->data,
2648 page_address(trans_pcie->fw_mon_page),
2649 trans_pcie->fw_mon_size);
2650
2651 monitor_len = trans_pcie->fw_mon_size;
2652 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2653 /*
2654 * Update pointers to reflect actual values after
2655 * shifting
2656 */
2657 base = iwl_read_prph(trans, base) <<
2658 trans->dbg_dest_tlv->base_shift;
2659 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2660 monitor_len / sizeof(u32));
2661 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2662 monitor_len =
2663 iwl_trans_pci_dump_marbh_monitor(trans,
2664 fw_mon_data,
2665 monitor_len);
2666 } else {
2667 /* Didn't match anything - output no monitor data */
2668 monitor_len = 0;
2669 }
2670
2671 len += monitor_len;
2672 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2673 }
2674
2675 return len;
2676}
2677
2678static struct iwl_trans_dump_data
2679*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2680 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2681{
2682 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2683 struct iwl_fw_error_dump_data *data;
b2a3b1c1 2684 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
4d075007 2685 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2686 struct iwl_trans_dump_data *dump_data;
bd7fc617 2687 u32 len, num_rbs;
99684ae3 2688 u32 monitor_len;
4d075007 2689 int i, ptr;
96a6497b
SS		 2690 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2691 !trans->cfg->mq_rx_supported;
4d075007 2692
473ad712
EG		 2693 /* transport dump header */
2694 len = sizeof(*dump_data);
2695
2696 /* host commands */
2697 len += sizeof(*data) +
bb98ecd4 2698 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
c2d20201 2699
473ad712 2700 /* FW monitor */
99684ae3 2701 if (trans_pcie->fw_mon_page) {
c544e9c4 2702 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2703 trans_pcie->fw_mon_size;
2704 monitor_len = trans_pcie->fw_mon_size;
2705 } else if (trans->dbg_dest_tlv) {
2706 u32 base, end;
2707
2708 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2709 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2710
2711 base = iwl_read_prph(trans, base) <<
2712 trans->dbg_dest_tlv->base_shift;
2713 end = iwl_read_prph(trans, end) <<
2714 trans->dbg_dest_tlv->end_shift;
2715
2716 /* Make "end" point to the actual end */
cc79ef66
LK		 2717 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2718 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2719 end += (1 << trans->dbg_dest_tlv->end_shift);
2720 monitor_len = end - base;
2721 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2722 monitor_len;
2723 } else {
2724 monitor_len = 0;
2725 }
c2d20201 2726
36fb9017
OG		 2727 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2728 dump_data = vzalloc(len);
2729 if (!dump_data)
2730 return NULL;
2731
2732 data = (void *)dump_data->data;
2733 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2734 dump_data->len = len;
2735
2736 return dump_data;
2737 }
2738
2739 /* CSR registers */
2740 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2741
36fb9017
OG		 2742 /* FH registers */
2743 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2744
2745 if (dump_rbs) {
78485054
SS		 2746 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2747 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2748 /* RBs */
78485054 2749 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2750 & 0x0FFF;
78485054 2751 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2752 len += num_rbs * (sizeof(*data) +
2753 sizeof(struct iwl_fw_error_dump_rb) +
2754 (PAGE_SIZE << trans_pcie->rx_page_order));
2755 }
2756
48eb7b34
EG		 2757 dump_data = vzalloc(len);
2758 if (!dump_data)
2759 return NULL;
4d075007
JB		 2760
2761 len = 0;
48eb7b34 2762 data = (void *)dump_data->data;
4d075007
JB		 2763 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2764 txcmd = (void *)data->data;
2765 spin_lock_bh(&cmdq->lock);
bb98ecd4
SS		 2766 ptr = cmdq->write_ptr;
2767 for (i = 0; i < cmdq->n_window; i++) {
2768 u8 idx = get_cmd_index(cmdq, ptr);
4d075007
JB		 2769 u32 caplen, cmdlen;
2770
6983ba69
SS		 2771 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2772 trans_pcie->tfd_size * ptr);
4d075007
JB		 2773 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2774
2775 if (cmdlen) {
2776 len += sizeof(*txcmd) + caplen;
2777 txcmd->cmdlen = cpu_to_le32(cmdlen);
2778 txcmd->caplen = cpu_to_le32(caplen);
2779 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2780 txcmd = (void *)((u8 *)txcmd->data + caplen);
2781 }
2782
2783 ptr = iwl_queue_dec_wrap(ptr);
2784 }
2785 spin_unlock_bh(&cmdq->lock);
2786
2787 data->len = cpu_to_le32(len);
c2d20201 2788 len += sizeof(*data);
67c65f2c
EG		 2789 data = iwl_fw_error_next_data(data);
2790
473ad712 2791 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2792 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2793 if (dump_rbs)
2794 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2795
36fb9017 2796 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2797
48eb7b34
EG		 2798 dump_data->len = len;
2799
2800 return dump_data;
4d075007 2801}
87e5666c 2802
4cbb8e50
LC		 2803#ifdef CONFIG_PM_SLEEP
2804static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2805{
e4c49c49
LC		 2806 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2807 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 2808 return iwl_pci_fw_enter_d0i3(trans);
2809
2810 return 0;
2811}
2812
2813static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2814{
e4c49c49
LC		 2815 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2816 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
4cbb8e50
LC		 2817 iwl_pci_fw_exit_d0i3(trans);
2818}
2819#endif /* CONFIG_PM_SLEEP */
2820
623e7766
SS		 2821#define IWL_TRANS_COMMON_OPS \
2822 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
2823 .write8 = iwl_trans_pcie_write8, \
2824 .write32 = iwl_trans_pcie_write32, \
2825 .read32 = iwl_trans_pcie_read32, \
2826 .read_prph = iwl_trans_pcie_read_prph, \
2827 .write_prph = iwl_trans_pcie_write_prph, \
2828 .read_mem = iwl_trans_pcie_read_mem, \
2829 .write_mem = iwl_trans_pcie_write_mem, \
2830 .configure = iwl_trans_pcie_configure, \
2831 .set_pmi = iwl_trans_pcie_set_pmi, \
2832 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
2833 .release_nic_access = iwl_trans_pcie_release_nic_access, \
2834 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
2835 .ref = iwl_trans_pcie_ref, \
2836 .unref = iwl_trans_pcie_unref, \
2837 .dump_data = iwl_trans_pcie_dump_data, \
a1a57877 2838 .wait_tx_queues_empty = iwl_trans_pcie_wait_txq_empty, \
623e7766
SS		 2839 .d3_suspend = iwl_trans_pcie_d3_suspend, \
2840 .d3_resume = iwl_trans_pcie_d3_resume
2841
2842#ifdef CONFIG_PM_SLEEP
2843#define IWL_TRANS_PM_OPS \
2844 .suspend = iwl_trans_pcie_suspend, \
2845 .resume = iwl_trans_pcie_resume,
2846#else
2847#define IWL_TRANS_PM_OPS
2848#endif /* CONFIG_PM_SLEEP */
2849
d1ff5253 2850static const struct iwl_trans_ops trans_ops_pcie = {
623e7766
SS		 2851 IWL_TRANS_COMMON_OPS,
2852 IWL_TRANS_PM_OPS
57a1dc89 2853 .start_hw = iwl_trans_pcie_start_hw,
ed6a3803 2854 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2855 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2856 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2857
623e7766 2858 .send_cmd = iwl_trans_pcie_send_hcmd,
2dd4f9f7 2859
623e7766
SS		 2860 .tx = iwl_trans_pcie_tx,
2861 .reclaim = iwl_trans_pcie_reclaim,
2862
2863 .txq_disable = iwl_trans_pcie_txq_disable,
2864 .txq_enable = iwl_trans_pcie_txq_enable,
2865
2866 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2867
2868 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2869 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2870};
2871
2872static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
2873 IWL_TRANS_COMMON_OPS,
2874 IWL_TRANS_PM_OPS
2875 .start_hw = iwl_trans_pcie_start_hw,
eda50cde
SS		 2876 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
2877 .start_fw = iwl_trans_pcie_gen2_start_fw,
77c09bc8 2878 .stop_device = iwl_trans_pcie_gen2_stop_device,
4cbb8e50 2879
ca60da2e 2880 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
c85eb619 2881
ab6c6445 2882 .tx = iwl_trans_pcie_gen2_tx,
a0eaad71 2883 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2884
6b35ff91
SS		 2885 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
2886 .txq_free = iwl_trans_pcie_dyn_txq_free,
e6bb4c9c 2887};
a42a1844 2888
87ce05a2 2889struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2890 const struct pci_device_id *ent,
2891 const struct iwl_cfg *cfg)
a42a1844 2892{
a42a1844
EG		 2893 struct iwl_trans_pcie *trans_pcie;
2894 struct iwl_trans *trans;
96a6497b 2895 int ret, addr_size;
a42a1844 2896
5a41a86c
SD		 2897 ret = pcim_enable_device(pdev);
2898 if (ret)
2899 return ERR_PTR(ret);
2900
623e7766
SS		 2901 if (cfg->gen2)
2902 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2903 &pdev->dev, cfg, &trans_ops_pcie_gen2);
2904 else
2905 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2906 &pdev->dev, cfg, &trans_ops_pcie);
7b501d10
JB		 2907 if (!trans)
2908 return ERR_PTR(-ENOMEM);
a42a1844
EG		 2909
2910 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2911
a42a1844 2912 trans_pcie->trans = trans;
7b11488f 2913 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2914 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 2915 mutex_init(&trans_pcie->mutex);
13df1aab 2916 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 2917 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2918 if (!trans_pcie->tso_hdr_page) {
2919 ret = -ENOMEM;
2920 goto out_no_pci;
2921 }
a42a1844 2922
d819c6cf 2923
f2532b04
EG		 2924 if (!cfg->base_params->pcie_l1_allowed) {
2925 /*
2926 * W/A - seems to solve weird behavior. We need to remove this
2927 * if we don't want to stay in L1 all the time. This wastes a
2928 * lot of power.
2929 */
2930 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2931 PCIE_LINK_STATE_L1 |
2932 PCIE_LINK_STATE_CLKPM);
2933 }
a42a1844 2934
6983ba69 2935 if (cfg->use_tfh) {
2c6262b7 2936 addr_size = 64;
3cd1980b 2937 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 2938 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 2939 } else {
2c6262b7 2940 addr_size = 36;
3cd1980b 2941 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 2942 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
2943 }
3cd1980b
SS		 2944 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
2945
a42a1844
EG		 2946 pci_set_master(pdev);
2947
96a6497b 2948 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 2949 if (!ret)
96a6497b
SS		 2950 ret = pci_set_consistent_dma_mask(pdev,
2951 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 2952 if (ret) {
2953 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2954 if (!ret)
2955 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2956 DMA_BIT_MASK(32));
a42a1844 2957 /* both attempts failed: */
af3f2f74 2958 if (ret) {
6a4b09f8 2959 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 2960 goto out_no_pci;
a42a1844
EG		 2961 }
2962 }
2963
5a41a86c 2964 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 2965 if (ret) {
5a41a86c
SD		 2966 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
2967 goto out_no_pci;
a42a1844
EG		 2968 }
2969
5a41a86c 2970 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 2971 if (!trans_pcie->hw_base) {
5a41a86c 2972 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 2973 ret = -ENODEV;
5a41a86c 2974 goto out_no_pci;
a42a1844
EG		 2975 }
2976
a42a1844
EG		 2977 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2978 * PCI Tx retries from interfering with C3 CPU state */
2979 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2980
83f7a85f
EG		 2981 trans_pcie->pci_dev = pdev;
2982 iwl_disable_interrupts(trans);
2983
08079a49 2984 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2985 /*
2986 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2987 * changed, and now the revision step also includes bit 0-1 (no more
2988 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2989 * in the old format.
2990 */
7a42baa6
EH		 2991 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2992 unsigned long flags;
7a42baa6 2993
b513ee7f 2994 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2995 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2996
f9e5554c
EG		 2997 ret = iwl_pcie_prepare_card_hw(trans);
2998 if (ret) {
2999 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3000 goto out_no_pci;
f9e5554c
EG		 3001 }
3002
7a42baa6
EH		 3003 /*
3004 * in-order to recognize C step driver should read chip version
3005 * id located at the AUX bus MISC address space.
3006 */
3007 iwl_set_bit(trans, CSR_GP_CNTRL,
3008 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3009 udelay(2);
3010
3011 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3012 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3013 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3014 25000);
3015 if (ret < 0) {
3016 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
5a41a86c 3017 goto out_no_pci;
7a42baa6
EH		 3018 }
3019
23ba9340 3020 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3021 u32 hw_step;
3022
14ef1b43 3023 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 3024 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 3025 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3026 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3027 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3028 if (hw_step == 0x3)
3029 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3030 (SILICON_C_STEP << 2);
3031 iwl_trans_release_nic_access(trans, &flags);
3032 }
3033 }
3034
1afb0ae4
HD		 3035 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3036
2e5d4a8f 3037 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3038 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3039 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3040 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3041
69a10b29 3042 /* Initialize the wait queue for commands */
f946b529 3043 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3044
4cbb8e50
LC		 3045 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3046
2e5d4a8f
HD		 3047 if (trans_pcie->msix_enabled) {
3048 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
5a41a86c 3049 goto out_no_pci;
2e5d4a8f
HD		 3050 } else {
3051 ret = iwl_pcie_alloc_ict(trans);
3052 if (ret)
5a41a86c 3053 goto out_no_pci;
a8b691e6 3054
5a41a86c
SD		 3055 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3056 iwl_pcie_isr,
3057 iwl_pcie_irq_handler,
3058 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3059 if (ret) {
3060 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3061 goto out_free_ict;
3062 }
3063 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3064 }
83f7a85f 3065
b3ff1270
LC		 3066#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3067 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3068#else
3069 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3070#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3071
a42a1844
EG		 3072 return trans;
3073
a8b691e6
JB		 3074out_free_ict:
3075 iwl_pcie_free_ict(trans);
a42a1844 3076out_no_pci:
6eb5e529 3077 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3078 iwl_trans_free(trans);
af3f2f74 3079 return ERR_PTR(ret);
a42a1844 3080}
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