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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
51368bf7 | 3 | * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. |
4cbb8e50 | 4 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
eda50cde | 5 | * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
1053d35f RR |
6 | * |
7 | * Portions of this file are derived from the ipw3945 project, as well | |
8 | * as portions of the ieee80211 subsystem header files. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program; if not, write to the Free Software Foundation, Inc., | |
21 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
22 | * | |
23 | * The full GNU General Public License is included in this distribution in the | |
24 | * file called LICENSE. | |
25 | * | |
26 | * Contact Information: | |
cb2f8277 | 27 | * Intel Linux Wireless <linuxwifi@intel.com> |
1053d35f RR |
28 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
29 | * | |
30 | *****************************************************************************/ | |
fd4abac5 | 31 | #include <linux/etherdevice.h> |
6eb5e529 | 32 | #include <linux/ieee80211.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
253a634c | 34 | #include <linux/sched.h> |
71b1230c | 35 | #include <linux/pm_runtime.h> |
6eb5e529 EG |
36 | #include <net/ip6_checksum.h> |
37 | #include <net/tso.h> | |
253a634c | 38 | |
522376d2 EG |
39 | #include "iwl-debug.h" |
40 | #include "iwl-csr.h" | |
41 | #include "iwl-prph.h" | |
1053d35f | 42 | #include "iwl-io.h" |
680073b7 | 43 | #include "iwl-scd.h" |
ed277c93 | 44 | #include "iwl-op-mode.h" |
6468a01a | 45 | #include "internal.h" |
6238b008 | 46 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 47 | #include "dvm/commands.h" |
1053d35f | 48 | |
522376d2 EG |
49 | #define IWL_TX_CRC_SIZE 4 |
50 | #define IWL_TX_DELIMITER_SIZE 4 | |
51 | ||
f02831be EG |
52 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
53 | * DMA services | |
54 | * | |
55 | * Theory of operation | |
56 | * | |
57 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
58 | * of buffer descriptors, each of which points to one or more data buffers for | |
59 | * the device to read from or fill. Driver and device exchange status of each | |
60 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
61 | * entries in each circular buffer, to protect against confusing empty and full | |
62 | * queue states. | |
63 | * | |
64 | * The device reads or writes the data in the queues via the device's several | |
65 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
66 | * | |
67 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
68 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
69 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
70 | * Tx queue resumed. | |
71 | * | |
72 | ***************************************************/ | |
e22744af | 73 | |
ab6c6445 | 74 | int iwl_queue_space(const struct iwl_txq *q) |
f02831be | 75 | { |
a9b29246 IY |
76 | unsigned int max; |
77 | unsigned int used; | |
f02831be | 78 | |
a9b29246 IY |
79 | /* |
80 | * To avoid ambiguity between empty and completely full queues, there | |
83f32a4b JB |
81 | * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. |
82 | * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need | |
83 | * to reserve any queue entries for this purpose. | |
a9b29246 | 84 | */ |
83f32a4b | 85 | if (q->n_window < TFD_QUEUE_SIZE_MAX) |
a9b29246 IY |
86 | max = q->n_window; |
87 | else | |
83f32a4b | 88 | max = TFD_QUEUE_SIZE_MAX - 1; |
f02831be | 89 | |
a9b29246 | 90 | /* |
83f32a4b JB |
91 | * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to |
92 | * modulo by TFD_QUEUE_SIZE_MAX and is well defined. | |
a9b29246 | 93 | */ |
83f32a4b | 94 | used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); |
a9b29246 IY |
95 | |
96 | if (WARN_ON(used > max)) | |
97 | return 0; | |
98 | ||
99 | return max - used; | |
f02831be EG |
100 | } |
101 | ||
102 | /* | |
103 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
104 | */ | |
b8e8d7ce | 105 | static int iwl_queue_init(struct iwl_txq *q, int slots_num) |
f02831be | 106 | { |
f02831be | 107 | q->n_window = slots_num; |
f02831be | 108 | |
f02831be EG |
109 | /* slots_num must be power-of-two size, otherwise |
110 | * get_cmd_index is broken. */ | |
111 | if (WARN_ON(!is_power_of_2(slots_num))) | |
112 | return -EINVAL; | |
113 | ||
114 | q->low_mark = q->n_window / 4; | |
115 | if (q->low_mark < 4) | |
116 | q->low_mark = 4; | |
117 | ||
118 | q->high_mark = q->n_window / 8; | |
119 | if (q->high_mark < 2) | |
120 | q->high_mark = 2; | |
121 | ||
122 | q->write_ptr = 0; | |
123 | q->read_ptr = 0; | |
124 | ||
125 | return 0; | |
126 | } | |
127 | ||
13a3a390 SS |
128 | int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
129 | struct iwl_dma_ptr *ptr, size_t size) | |
f02831be EG |
130 | { |
131 | if (WARN_ON(ptr->addr)) | |
132 | return -EINVAL; | |
133 | ||
134 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
135 | &ptr->dma, GFP_KERNEL); | |
136 | if (!ptr->addr) | |
137 | return -ENOMEM; | |
138 | ptr->size = size; | |
139 | return 0; | |
140 | } | |
141 | ||
13a3a390 | 142 | void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) |
f02831be EG |
143 | { |
144 | if (unlikely(!ptr->addr)) | |
145 | return; | |
146 | ||
147 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
148 | memset(ptr, 0, sizeof(*ptr)); | |
149 | } | |
150 | ||
151 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
152 | { | |
153 | struct iwl_txq *txq = (void *)data; | |
f02831be EG |
154 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; |
155 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
f02831be EG |
156 | |
157 | spin_lock(&txq->lock); | |
158 | /* check if triggered erroneously */ | |
bb98ecd4 | 159 | if (txq->read_ptr == txq->write_ptr) { |
f02831be EG |
160 | spin_unlock(&txq->lock); |
161 | return; | |
162 | } | |
163 | spin_unlock(&txq->lock); | |
164 | ||
38398efb | 165 | iwl_trans_pcie_log_scd_error(trans, txq); |
f02831be | 166 | |
4c9706dc | 167 | iwl_force_nmi(trans); |
f02831be EG |
168 | } |
169 | ||
990aa6d7 EG |
170 | /* |
171 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 172 | */ |
f02831be | 173 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
4fe10bc6 SS |
174 | struct iwl_txq *txq, u16 byte_cnt, |
175 | int num_tbs) | |
48d42c42 | 176 | { |
105183b1 | 177 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 178 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
bb98ecd4 SS |
179 | int write_ptr = txq->write_ptr; |
180 | int txq_id = txq->id; | |
48d42c42 | 181 | u8 sec_ctl = 0; |
48d42c42 EG |
182 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; |
183 | __le16 bc_ent; | |
132f98c2 | 184 | struct iwl_tx_cmd *tx_cmd = |
bb98ecd4 | 185 | (void *)txq->entries[txq->write_ptr].cmd->payload; |
ab6c6445 | 186 | u8 sta_id = tx_cmd->sta_id; |
48d42c42 | 187 | |
105183b1 EG |
188 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
189 | ||
132f98c2 | 190 | sec_ctl = tx_cmd->sec_ctl; |
48d42c42 EG |
191 | |
192 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
193 | case TX_CMD_SEC_CCM: | |
4325f6ca | 194 | len += IEEE80211_CCMP_MIC_LEN; |
48d42c42 EG |
195 | break; |
196 | case TX_CMD_SEC_TKIP: | |
4325f6ca | 197 | len += IEEE80211_TKIP_ICV_LEN; |
48d42c42 EG |
198 | break; |
199 | case TX_CMD_SEC_WEP: | |
4325f6ca | 200 | len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; |
48d42c42 EG |
201 | break; |
202 | } | |
046db346 EG |
203 | if (trans_pcie->bc_table_dword) |
204 | len = DIV_ROUND_UP(len, 4); | |
205 | ||
31f920b6 EG |
206 | if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) |
207 | return; | |
208 | ||
ab6c6445 | 209 | bc_ent = cpu_to_le16(len | (sta_id << 12)); |
48d42c42 EG |
210 | |
211 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
212 | ||
213 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
214 | scd_bc_tbl[txq_id]. | |
215 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
216 | } | |
217 | ||
f02831be EG |
218 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
219 | struct iwl_txq *txq) | |
220 | { | |
221 | struct iwl_trans_pcie *trans_pcie = | |
222 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
223 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
bb98ecd4 SS |
224 | int txq_id = txq->id; |
225 | int read_ptr = txq->read_ptr; | |
f02831be EG |
226 | u8 sta_id = 0; |
227 | __le16 bc_ent; | |
228 | struct iwl_tx_cmd *tx_cmd = | |
bb98ecd4 | 229 | (void *)txq->entries[read_ptr].cmd->payload; |
f02831be EG |
230 | |
231 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
232 | ||
233 | if (txq_id != trans_pcie->cmd_queue) | |
234 | sta_id = tx_cmd->sta_id; | |
235 | ||
236 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
4fe10bc6 | 237 | |
f02831be EG |
238 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; |
239 | ||
240 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
241 | scd_bc_tbl[txq_id]. | |
242 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
243 | } | |
244 | ||
990aa6d7 EG |
245 | /* |
246 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 247 | */ |
ea68f460 JB |
248 | static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, |
249 | struct iwl_txq *txq) | |
fd4abac5 | 250 | { |
23e76d1a | 251 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
fd4abac5 | 252 | u32 reg = 0; |
bb98ecd4 | 253 | int txq_id = txq->id; |
fd4abac5 | 254 | |
ea68f460 | 255 | lockdep_assert_held(&txq->lock); |
fd4abac5 | 256 | |
5045388c EP |
257 | /* |
258 | * explicitly wake up the NIC if: | |
259 | * 1. shadow registers aren't enabled | |
260 | * 2. NIC is woken up for CMD regardless of shadow outside this function | |
261 | * 3. there is a chance that the NIC is asleep | |
262 | */ | |
263 | if (!trans->cfg->base_params->shadow_reg_enable && | |
264 | txq_id != trans_pcie->cmd_queue && | |
265 | test_bit(STATUS_TPOWER_PMI, &trans->status)) { | |
f81c1f48 | 266 | /* |
5045388c EP |
267 | * wake up nic if it's powered down ... |
268 | * uCode will wake up, and interrupt us again, so next | |
269 | * time we'll skip this part. | |
f81c1f48 | 270 | */ |
5045388c EP |
271 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
272 | ||
273 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
274 | IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", | |
275 | txq_id, reg); | |
276 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
277 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ea68f460 | 278 | txq->need_update = true; |
5045388c EP |
279 | return; |
280 | } | |
f81c1f48 | 281 | } |
5045388c EP |
282 | |
283 | /* | |
284 | * if not in power-save mode, uCode will never sleep when we're | |
285 | * trying to tx (during RFKILL, we're not trying to tx). | |
286 | */ | |
bb98ecd4 | 287 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); |
0cd58eaa EG |
288 | if (!txq->block) |
289 | iwl_write32(trans, HBUS_TARG_WRPTR, | |
bb98ecd4 | 290 | txq->write_ptr | (txq_id << 8)); |
ea68f460 | 291 | } |
5045388c | 292 | |
ea68f460 JB |
293 | void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) |
294 | { | |
295 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
296 | int i; | |
297 | ||
298 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
b2a3b1c1 | 299 | struct iwl_txq *txq = trans_pcie->txq[i]; |
ea68f460 | 300 | |
f6eac740 MG |
301 | if (!test_bit(i, trans_pcie->queue_used)) |
302 | continue; | |
303 | ||
d090f878 | 304 | spin_lock_bh(&txq->lock); |
b2a3b1c1 | 305 | if (txq->need_update) { |
ea68f460 | 306 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
b2a3b1c1 | 307 | txq->need_update = false; |
ea68f460 | 308 | } |
d090f878 | 309 | spin_unlock_bh(&txq->lock); |
ea68f460 | 310 | } |
fd4abac5 | 311 | } |
fd4abac5 | 312 | |
6983ba69 | 313 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, |
cc2f41f8 | 314 | void *_tfd, u8 idx) |
6983ba69 | 315 | { |
6983ba69 SS |
316 | |
317 | if (trans->cfg->use_tfh) { | |
cc2f41f8 JB |
318 | struct iwl_tfh_tfd *tfd = _tfd; |
319 | struct iwl_tfh_tb *tb = &tfd->tbs[idx]; | |
6983ba69 SS |
320 | |
321 | return (dma_addr_t)(le64_to_cpu(tb->addr)); | |
cc2f41f8 JB |
322 | } else { |
323 | struct iwl_tfd *tfd = _tfd; | |
324 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
325 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
326 | dma_addr_t hi_len; | |
6983ba69 | 327 | |
cc2f41f8 JB |
328 | if (sizeof(dma_addr_t) <= sizeof(u32)) |
329 | return addr; | |
214d14d4 | 330 | |
cc2f41f8 | 331 | hi_len = le16_to_cpu(tb->hi_n_len) & 0xF; |
214d14d4 | 332 | |
cc2f41f8 JB |
333 | /* |
334 | * shift by 16 twice to avoid warnings on 32-bit | |
335 | * (where this code never runs anyway due to the | |
336 | * if statement above) | |
337 | */ | |
338 | return addr | ((hi_len << 16) << 16); | |
339 | } | |
214d14d4 JB |
340 | } |
341 | ||
6983ba69 SS |
342 | static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, |
343 | u8 idx, dma_addr_t addr, u16 len) | |
214d14d4 | 344 | { |
ca60da2e SS |
345 | struct iwl_tfd *tfd_fh = (void *)tfd; |
346 | struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; | |
6983ba69 | 347 | |
ca60da2e | 348 | u16 hi_n_len = len << 4; |
214d14d4 | 349 | |
ca60da2e SS |
350 | put_unaligned_le32(addr, &tb->lo); |
351 | hi_n_len |= iwl_get_dma_hi_addr(addr); | |
214d14d4 | 352 | |
ca60da2e | 353 | tb->hi_n_len = cpu_to_le16(hi_n_len); |
6983ba69 | 354 | |
ca60da2e | 355 | tfd_fh->num_tbs = idx + 1; |
214d14d4 JB |
356 | } |
357 | ||
cc2f41f8 | 358 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd) |
214d14d4 | 359 | { |
6983ba69 | 360 | if (trans->cfg->use_tfh) { |
cc2f41f8 | 361 | struct iwl_tfh_tfd *tfd = _tfd; |
6983ba69 | 362 | |
cc2f41f8 JB |
363 | return le16_to_cpu(tfd->num_tbs) & 0x1f; |
364 | } else { | |
365 | struct iwl_tfd *tfd = _tfd; | |
6983ba69 | 366 | |
cc2f41f8 JB |
367 | return tfd->num_tbs & 0x1f; |
368 | } | |
214d14d4 JB |
369 | } |
370 | ||
f02831be | 371 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
98891754 | 372 | struct iwl_cmd_meta *meta, |
6983ba69 | 373 | struct iwl_txq *txq, int index) |
214d14d4 | 374 | { |
3cd1980b SS |
375 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
376 | int i, num_tbs; | |
6983ba69 | 377 | void *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index); |
214d14d4 | 378 | |
214d14d4 | 379 | /* Sanity check on number of chunks */ |
6983ba69 | 380 | num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); |
214d14d4 | 381 | |
3cd1980b | 382 | if (num_tbs >= trans_pcie->max_tbs) { |
6d8f6eeb | 383 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
384 | /* @todo issue fatal error, it is quite serious situation */ |
385 | return; | |
386 | } | |
387 | ||
8de437c7 | 388 | /* first TB is never freed - it's the bidirectional DMA data */ |
214d14d4 | 389 | |
206eea78 | 390 | for (i = 1; i < num_tbs; i++) { |
3cd1980b | 391 | if (meta->tbs & BIT(i)) |
206eea78 | 392 | dma_unmap_page(trans->dev, |
6983ba69 SS |
393 | iwl_pcie_tfd_tb_get_addr(trans, tfd, i), |
394 | iwl_pcie_tfd_tb_get_len(trans, tfd, i), | |
206eea78 JB |
395 | DMA_TO_DEVICE); |
396 | else | |
397 | dma_unmap_single(trans->dev, | |
6983ba69 SS |
398 | iwl_pcie_tfd_tb_get_addr(trans, tfd, |
399 | i), | |
400 | iwl_pcie_tfd_tb_get_len(trans, tfd, | |
401 | i), | |
206eea78 JB |
402 | DMA_TO_DEVICE); |
403 | } | |
6983ba69 SS |
404 | |
405 | if (trans->cfg->use_tfh) { | |
406 | struct iwl_tfh_tfd *tfd_fh = (void *)tfd; | |
407 | ||
408 | tfd_fh->num_tbs = 0; | |
409 | } else { | |
410 | struct iwl_tfd *tfd_fh = (void *)tfd; | |
411 | ||
412 | tfd_fh->num_tbs = 0; | |
413 | } | |
414 | ||
4ce7cc2b JB |
415 | } |
416 | ||
990aa6d7 EG |
417 | /* |
418 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 419 | * @trans - transport private data |
4ce7cc2b | 420 | * @txq - tx queue |
ebed633c | 421 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
422 | * |
423 | * Does NOT advance any TFD circular buffer read/write indexes | |
424 | * Does NOT free the TFD itself (which is within circular buffer) | |
425 | */ | |
6b35ff91 | 426 | void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
4ce7cc2b | 427 | { |
83f32a4b JB |
428 | /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and |
429 | * idx is bounded by n_window | |
430 | */ | |
bb98ecd4 SS |
431 | int rd_ptr = txq->read_ptr; |
432 | int idx = get_cmd_index(txq, rd_ptr); | |
ebed633c | 433 | |
015c15e1 JB |
434 | lockdep_assert_held(&txq->lock); |
435 | ||
83f32a4b JB |
436 | /* We have only q->n_window txq->entries, but we use |
437 | * TFD_QUEUE_SIZE_MAX tfds | |
438 | */ | |
6983ba69 | 439 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); |
214d14d4 JB |
440 | |
441 | /* free SKB */ | |
bf8440e6 | 442 | if (txq->entries) { |
214d14d4 JB |
443 | struct sk_buff *skb; |
444 | ||
ebed633c | 445 | skb = txq->entries[idx].skb; |
214d14d4 | 446 | |
909e9b23 EG |
447 | /* Can be called from irqs-disabled context |
448 | * If skb is not NULL, it means that the whole queue is being | |
449 | * freed and that the queue is not empty - free the skb | |
450 | */ | |
214d14d4 | 451 | if (skb) { |
ed277c93 | 452 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 453 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
454 | } |
455 | } | |
456 | } | |
457 | ||
f02831be | 458 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
6d6e68f8 | 459 | dma_addr_t addr, u16 len, bool reset) |
214d14d4 | 460 | { |
3cd1980b | 461 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
6983ba69 | 462 | void *tfd; |
214d14d4 JB |
463 | u32 num_tbs; |
464 | ||
bb98ecd4 | 465 | tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr; |
214d14d4 | 466 | |
f02831be | 467 | if (reset) |
6983ba69 | 468 | memset(tfd, 0, trans_pcie->tfd_size); |
f02831be | 469 | |
6983ba69 | 470 | num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); |
f02831be | 471 | |
6983ba69 | 472 | /* Each TFD can point to a maximum max_tbs Tx buffers */ |
3cd1980b | 473 | if (num_tbs >= trans_pcie->max_tbs) { |
f02831be | 474 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
3cd1980b | 475 | trans_pcie->max_tbs); |
f02831be EG |
476 | return -EINVAL; |
477 | } | |
478 | ||
1092b9bc EP |
479 | if (WARN(addr & ~IWL_TX_DMA_MASK, |
480 | "Unaligned address = %llx\n", (unsigned long long)addr)) | |
f02831be EG |
481 | return -EINVAL; |
482 | ||
6983ba69 | 483 | iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); |
f02831be | 484 | |
206eea78 | 485 | return num_tbs; |
f02831be EG |
486 | } |
487 | ||
13a3a390 | 488 | int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, |
b8e8d7ce | 489 | int slots_num, bool cmd_queue) |
f02831be EG |
490 | { |
491 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
6983ba69 | 492 | size_t tfd_sz = trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX; |
8de437c7 | 493 | size_t tb0_buf_sz; |
f02831be EG |
494 | int i; |
495 | ||
496 | if (WARN_ON(txq->entries || txq->tfds)) | |
497 | return -EINVAL; | |
498 | ||
499 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
500 | (unsigned long)txq); | |
501 | txq->trans_pcie = trans_pcie; | |
502 | ||
bb98ecd4 | 503 | txq->n_window = slots_num; |
f02831be EG |
504 | |
505 | txq->entries = kcalloc(slots_num, | |
506 | sizeof(struct iwl_pcie_txq_entry), | |
507 | GFP_KERNEL); | |
508 | ||
509 | if (!txq->entries) | |
510 | goto error; | |
511 | ||
b8e8d7ce | 512 | if (cmd_queue) |
f02831be EG |
513 | for (i = 0; i < slots_num; i++) { |
514 | txq->entries[i].cmd = | |
515 | kmalloc(sizeof(struct iwl_device_cmd), | |
516 | GFP_KERNEL); | |
517 | if (!txq->entries[i].cmd) | |
518 | goto error; | |
519 | } | |
520 | ||
521 | /* Circular buffer of transmit frame descriptors (TFDs), | |
522 | * shared with device */ | |
523 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
bb98ecd4 | 524 | &txq->dma_addr, GFP_KERNEL); |
d0320f75 | 525 | if (!txq->tfds) |
f02831be | 526 | goto error; |
38c0f334 | 527 | |
8de437c7 | 528 | BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); |
38c0f334 | 529 | |
8de437c7 | 530 | tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; |
38c0f334 | 531 | |
8de437c7 SS |
532 | txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, |
533 | &txq->first_tb_dma, | |
38c0f334 | 534 | GFP_KERNEL); |
8de437c7 | 535 | if (!txq->first_tb_bufs) |
38c0f334 JB |
536 | goto err_free_tfds; |
537 | ||
f02831be | 538 | return 0; |
38c0f334 | 539 | err_free_tfds: |
bb98ecd4 | 540 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); |
f02831be | 541 | error: |
b8e8d7ce | 542 | if (txq->entries && cmd_queue) |
f02831be EG |
543 | for (i = 0; i < slots_num; i++) |
544 | kfree(txq->entries[i].cmd); | |
545 | kfree(txq->entries); | |
546 | txq->entries = NULL; | |
547 | ||
548 | return -ENOMEM; | |
549 | ||
550 | } | |
551 | ||
13a3a390 | 552 | int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, |
b8e8d7ce | 553 | int slots_num, bool cmd_queue) |
f02831be EG |
554 | { |
555 | int ret; | |
556 | ||
43aa616f | 557 | txq->need_update = false; |
f02831be EG |
558 | |
559 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
560 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
561 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
562 | ||
563 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
b8e8d7ce | 564 | ret = iwl_queue_init(txq, slots_num); |
f02831be EG |
565 | if (ret) |
566 | return ret; | |
567 | ||
568 | spin_lock_init(&txq->lock); | |
faead41c | 569 | |
b8e8d7ce | 570 | if (cmd_queue) { |
faead41c JB |
571 | static struct lock_class_key iwl_pcie_cmd_queue_lock_class; |
572 | ||
573 | lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); | |
574 | } | |
575 | ||
3955525d | 576 | __skb_queue_head_init(&txq->overflow_q); |
f02831be | 577 | |
f02831be EG |
578 | return 0; |
579 | } | |
580 | ||
21cb3222 JB |
581 | static void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, |
582 | struct sk_buff *skb) | |
6eb5e529 | 583 | { |
21cb3222 | 584 | struct page **page_ptr; |
6eb5e529 | 585 | |
21cb3222 | 586 | page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); |
6eb5e529 | 587 | |
21cb3222 JB |
588 | if (*page_ptr) { |
589 | __free_page(*page_ptr); | |
590 | *page_ptr = NULL; | |
6eb5e529 EG |
591 | } |
592 | } | |
593 | ||
01d11cd1 SS |
594 | static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) |
595 | { | |
596 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
597 | ||
598 | lockdep_assert_held(&trans_pcie->reg_lock); | |
599 | ||
600 | if (trans_pcie->ref_cmd_in_flight) { | |
601 | trans_pcie->ref_cmd_in_flight = false; | |
602 | IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); | |
c24c7f58 | 603 | iwl_trans_unref(trans); |
01d11cd1 SS |
604 | } |
605 | ||
606 | if (!trans->cfg->base_params->apmg_wake_up_wa) | |
607 | return; | |
608 | if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) | |
609 | return; | |
610 | ||
611 | trans_pcie->cmd_hold_nic_awake = false; | |
612 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
613 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
614 | } | |
615 | ||
f02831be EG |
616 | /* |
617 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
618 | */ | |
619 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
620 | { | |
621 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
b2a3b1c1 | 622 | struct iwl_txq *txq = trans_pcie->txq[txq_id]; |
f02831be | 623 | |
f02831be | 624 | spin_lock_bh(&txq->lock); |
bb98ecd4 | 625 | while (txq->write_ptr != txq->read_ptr) { |
b967613d | 626 | IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", |
bb98ecd4 | 627 | txq_id, txq->read_ptr); |
6eb5e529 EG |
628 | |
629 | if (txq_id != trans_pcie->cmd_queue) { | |
bb98ecd4 | 630 | struct sk_buff *skb = txq->entries[txq->read_ptr].skb; |
6eb5e529 EG |
631 | |
632 | if (WARN_ON_ONCE(!skb)) | |
633 | continue; | |
634 | ||
21cb3222 | 635 | iwl_pcie_free_tso_page(trans_pcie, skb); |
6eb5e529 | 636 | } |
98891754 | 637 | iwl_pcie_txq_free_tfd(trans, txq); |
bb98ecd4 | 638 | txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr); |
01d11cd1 | 639 | |
bb98ecd4 | 640 | if (txq->read_ptr == txq->write_ptr) { |
01d11cd1 SS |
641 | unsigned long flags; |
642 | ||
643 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); | |
644 | if (txq_id != trans_pcie->cmd_queue) { | |
645 | IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", | |
bb98ecd4 | 646 | txq->id); |
c24c7f58 | 647 | iwl_trans_unref(trans); |
01d11cd1 SS |
648 | } else { |
649 | iwl_pcie_clear_cmd_in_flight(trans); | |
650 | } | |
651 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
652 | } | |
f02831be | 653 | } |
3955525d EG |
654 | |
655 | while (!skb_queue_empty(&txq->overflow_q)) { | |
656 | struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); | |
657 | ||
658 | iwl_op_mode_free_skb(trans->op_mode, skb); | |
659 | } | |
660 | ||
f02831be | 661 | spin_unlock_bh(&txq->lock); |
8a487b1a EG |
662 | |
663 | /* just in case - this queue may have been stopped */ | |
664 | iwl_wake_queue(trans, txq); | |
f02831be EG |
665 | } |
666 | ||
667 | /* | |
668 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
669 | * @txq: Transmit queue to deallocate. | |
670 | * | |
671 | * Empty queue by removing and destroying all BD's. | |
672 | * Free all buffers. | |
673 | * 0-fill, but do not free "txq" descriptor structure. | |
674 | */ | |
675 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
676 | { | |
677 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
b2a3b1c1 | 678 | struct iwl_txq *txq = trans_pcie->txq[txq_id]; |
f02831be EG |
679 | struct device *dev = trans->dev; |
680 | int i; | |
681 | ||
682 | if (WARN_ON(!txq)) | |
683 | return; | |
684 | ||
685 | iwl_pcie_txq_unmap(trans, txq_id); | |
686 | ||
687 | /* De-alloc array of command/tx buffers */ | |
688 | if (txq_id == trans_pcie->cmd_queue) | |
bb98ecd4 | 689 | for (i = 0; i < txq->n_window; i++) { |
5d4185ae JB |
690 | kzfree(txq->entries[i].cmd); |
691 | kzfree(txq->entries[i].free_buf); | |
f02831be EG |
692 | } |
693 | ||
694 | /* De-alloc circular buffer of TFDs */ | |
83f32a4b JB |
695 | if (txq->tfds) { |
696 | dma_free_coherent(dev, | |
6983ba69 | 697 | trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX, |
bb98ecd4 SS |
698 | txq->tfds, txq->dma_addr); |
699 | txq->dma_addr = 0; | |
83f32a4b | 700 | txq->tfds = NULL; |
38c0f334 JB |
701 | |
702 | dma_free_coherent(dev, | |
bb98ecd4 | 703 | sizeof(*txq->first_tb_bufs) * txq->n_window, |
8de437c7 | 704 | txq->first_tb_bufs, txq->first_tb_dma); |
f02831be EG |
705 | } |
706 | ||
707 | kfree(txq->entries); | |
708 | txq->entries = NULL; | |
709 | ||
710 | del_timer_sync(&txq->stuck_timer); | |
711 | ||
712 | /* 0-fill queue descriptor structure */ | |
713 | memset(txq, 0, sizeof(*txq)); | |
714 | } | |
715 | ||
f02831be EG |
716 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) |
717 | { | |
718 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 719 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
720 | int chan; |
721 | u32 reg_val; | |
22dc3c95 JB |
722 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
723 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
724 | |
725 | /* make sure all queue are not stopped/used */ | |
726 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
727 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
728 | ||
729 | trans_pcie->scd_base_addr = | |
730 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
731 | ||
732 | WARN_ON(scd_base_addr != 0 && | |
733 | scd_base_addr != trans_pcie->scd_base_addr); | |
734 | ||
22dc3c95 JB |
735 | /* reset context data, TX status and translation data */ |
736 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
737 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
738 | NULL, clear_dwords); | |
f02831be EG |
739 | |
740 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
741 | trans_pcie->scd_bc_tbls.dma >> 10); | |
742 | ||
743 | /* The chain extension of the SCD doesn't work well. This feature is | |
744 | * enabled by default by the HW, so we need to disable it manually. | |
745 | */ | |
e03bbb62 EG |
746 | if (trans->cfg->base_params->scd_chain_ext_wa) |
747 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
f02831be EG |
748 | |
749 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
4cf677fd EG |
750 | trans_pcie->cmd_fifo, |
751 | trans_pcie->cmd_q_wdg_timeout); | |
f02831be EG |
752 | |
753 | /* Activate all Tx DMA/FIFO channels */ | |
680073b7 | 754 | iwl_scd_activate_fifos(trans); |
f02831be EG |
755 | |
756 | /* Enable DMA channel */ | |
757 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
758 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
759 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
760 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
761 | ||
762 | /* Update FH chicken bits */ | |
763 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
764 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
765 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
766 | ||
767 | /* Enable L1-Active */ | |
6e584873 | 768 | if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) |
3073d8c0 EH |
769 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, |
770 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
f02831be EG |
771 | } |
772 | ||
ddaf5a5b JB |
773 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
774 | { | |
775 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
776 | int txq_id; | |
777 | ||
13a3a390 SS |
778 | /* |
779 | * we should never get here in gen2 trans mode return early to avoid | |
780 | * having invalid accesses | |
781 | */ | |
782 | if (WARN_ON_ONCE(trans->cfg->gen2)) | |
783 | return; | |
784 | ||
ddaf5a5b JB |
785 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; |
786 | txq_id++) { | |
b2a3b1c1 | 787 | struct iwl_txq *txq = trans_pcie->txq[txq_id]; |
e22744af SS |
788 | if (trans->cfg->use_tfh) |
789 | iwl_write_direct64(trans, | |
790 | FH_MEM_CBBC_QUEUE(trans, txq_id), | |
bb98ecd4 | 791 | txq->dma_addr); |
e22744af SS |
792 | else |
793 | iwl_write_direct32(trans, | |
794 | FH_MEM_CBBC_QUEUE(trans, txq_id), | |
bb98ecd4 | 795 | txq->dma_addr >> 8); |
ddaf5a5b | 796 | iwl_pcie_txq_unmap(trans, txq_id); |
bb98ecd4 SS |
797 | txq->read_ptr = 0; |
798 | txq->write_ptr = 0; | |
ddaf5a5b JB |
799 | } |
800 | ||
801 | /* Tell NIC where to find the "keep warm" buffer */ | |
802 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
803 | trans_pcie->kw.dma >> 4); | |
804 | ||
cd8f4384 EG |
805 | /* |
806 | * Send 0 as the scd_base_addr since the device may have be reset | |
807 | * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will | |
808 | * contain garbage. | |
809 | */ | |
810 | iwl_pcie_tx_start(trans, 0); | |
ddaf5a5b JB |
811 | } |
812 | ||
36277234 EG |
813 | static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) |
814 | { | |
815 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
816 | unsigned long flags; | |
817 | int ch, ret; | |
818 | u32 mask = 0; | |
819 | ||
820 | spin_lock(&trans_pcie->irq_lock); | |
821 | ||
23ba9340 | 822 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
36277234 EG |
823 | goto out; |
824 | ||
825 | /* Stop each Tx DMA channel */ | |
826 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
827 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
828 | mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); | |
829 | } | |
830 | ||
831 | /* Wait for DMA channels to be idle */ | |
832 | ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); | |
833 | if (ret < 0) | |
834 | IWL_ERR(trans, | |
835 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
836 | ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); | |
837 | ||
838 | iwl_trans_release_nic_access(trans, &flags); | |
839 | ||
840 | out: | |
841 | spin_unlock(&trans_pcie->irq_lock); | |
842 | } | |
843 | ||
f02831be EG |
844 | /* |
845 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
846 | */ | |
847 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
848 | { | |
849 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
36277234 | 850 | int txq_id; |
f02831be EG |
851 | |
852 | /* Turn off all Tx DMA fifos */ | |
680073b7 | 853 | iwl_scd_deactivate_fifos(trans); |
f02831be | 854 | |
36277234 EG |
855 | /* Turn off all Tx DMA channels */ |
856 | iwl_pcie_tx_stop_fh(trans); | |
f02831be | 857 | |
fba1c627 EG |
858 | /* |
859 | * This function can be called before the op_mode disabled the | |
860 | * queues. This happens when we have an rfkill interrupt. | |
861 | * Since we stop Tx altogether - mark the queues as stopped. | |
862 | */ | |
863 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
864 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
865 | ||
866 | /* This can happen: start_hw, stop_device */ | |
b2a3b1c1 | 867 | if (!trans_pcie->txq_memory) |
f02831be | 868 | return 0; |
f02831be EG |
869 | |
870 | /* Unmap DMA from host system and free skb's */ | |
871 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
872 | txq_id++) | |
873 | iwl_pcie_txq_unmap(trans, txq_id); | |
874 | ||
875 | return 0; | |
876 | } | |
877 | ||
878 | /* | |
879 | * iwl_trans_tx_free - Free TXQ Context | |
880 | * | |
881 | * Destroy all TX DMA queues and structures | |
882 | */ | |
883 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
884 | { | |
885 | int txq_id; | |
886 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
887 | ||
de74c455 SS |
888 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); |
889 | ||
f02831be | 890 | /* Tx queues */ |
b2a3b1c1 | 891 | if (trans_pcie->txq_memory) { |
f02831be | 892 | for (txq_id = 0; |
b2a3b1c1 SS |
893 | txq_id < trans->cfg->base_params->num_of_queues; |
894 | txq_id++) { | |
f02831be | 895 | iwl_pcie_txq_free(trans, txq_id); |
b2a3b1c1 SS |
896 | trans_pcie->txq[txq_id] = NULL; |
897 | } | |
f02831be EG |
898 | } |
899 | ||
b2a3b1c1 SS |
900 | kfree(trans_pcie->txq_memory); |
901 | trans_pcie->txq_memory = NULL; | |
f02831be EG |
902 | |
903 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
904 | ||
905 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
906 | } | |
907 | ||
908 | /* | |
909 | * iwl_pcie_tx_alloc - allocate TX context | |
910 | * Allocate all Tx DMA structures and initialize them | |
911 | */ | |
912 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
913 | { | |
914 | int ret; | |
915 | int txq_id, slots_num; | |
916 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
917 | ||
918 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
919 | sizeof(struct iwlagn_scd_bc_tbl); | |
920 | ||
921 | /*It is not allowed to alloc twice, so warn when this happens. | |
922 | * We cannot rely on the previous allocation, so free and fail */ | |
b2a3b1c1 | 923 | if (WARN_ON(trans_pcie->txq_memory)) { |
f02831be EG |
924 | ret = -EINVAL; |
925 | goto error; | |
926 | } | |
927 | ||
928 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
929 | scd_bc_tbls_size); | |
930 | if (ret) { | |
931 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
932 | goto error; | |
933 | } | |
934 | ||
935 | /* Alloc keep-warm buffer */ | |
936 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
937 | if (ret) { | |
938 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
939 | goto error; | |
940 | } | |
941 | ||
b2a3b1c1 SS |
942 | trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues, |
943 | sizeof(struct iwl_txq), GFP_KERNEL); | |
944 | if (!trans_pcie->txq_memory) { | |
f02831be | 945 | IWL_ERR(trans, "Not enough memory for txq\n"); |
2ab9ba0f | 946 | ret = -ENOMEM; |
f02831be EG |
947 | goto error; |
948 | } | |
949 | ||
950 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
951 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
952 | txq_id++) { | |
b8e8d7ce SS |
953 | bool cmd_queue = (txq_id == trans_pcie->cmd_queue); |
954 | ||
955 | slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
b2a3b1c1 SS |
956 | trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id]; |
957 | ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id], | |
b8e8d7ce | 958 | slots_num, cmd_queue); |
f02831be EG |
959 | if (ret) { |
960 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
961 | goto error; | |
962 | } | |
b8e8d7ce | 963 | trans_pcie->txq[txq_id]->id = txq_id; |
f02831be EG |
964 | } |
965 | ||
966 | return 0; | |
967 | ||
968 | error: | |
969 | iwl_pcie_tx_free(trans); | |
970 | ||
971 | return ret; | |
972 | } | |
eda50cde | 973 | |
f02831be EG |
974 | int iwl_pcie_tx_init(struct iwl_trans *trans) |
975 | { | |
976 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
977 | int ret; | |
978 | int txq_id, slots_num; | |
f02831be EG |
979 | bool alloc = false; |
980 | ||
b2a3b1c1 | 981 | if (!trans_pcie->txq_memory) { |
f02831be EG |
982 | ret = iwl_pcie_tx_alloc(trans); |
983 | if (ret) | |
984 | goto error; | |
985 | alloc = true; | |
986 | } | |
987 | ||
7b70bd63 | 988 | spin_lock(&trans_pcie->irq_lock); |
f02831be EG |
989 | |
990 | /* Turn off all Tx DMA fifos */ | |
680073b7 | 991 | iwl_scd_deactivate_fifos(trans); |
f02831be EG |
992 | |
993 | /* Tell NIC where to find the "keep warm" buffer */ | |
994 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
995 | trans_pcie->kw.dma >> 4); | |
996 | ||
7b70bd63 | 997 | spin_unlock(&trans_pcie->irq_lock); |
f02831be EG |
998 | |
999 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
1000 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
1001 | txq_id++) { | |
b8e8d7ce SS |
1002 | bool cmd_queue = (txq_id == trans_pcie->cmd_queue); |
1003 | ||
1004 | slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
b2a3b1c1 | 1005 | ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id], |
b8e8d7ce | 1006 | slots_num, cmd_queue); |
f02831be EG |
1007 | if (ret) { |
1008 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
1009 | goto error; | |
1010 | } | |
f02831be | 1011 | |
eda50cde SS |
1012 | /* |
1013 | * Tell nic where to find circular buffer of TFDs for a | |
1014 | * given Tx queue, and enable the DMA channel used for that | |
1015 | * queue. | |
1016 | * Circular buffer (TFD queue in DRAM) physical base address | |
1017 | */ | |
1018 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), | |
b2a3b1c1 | 1019 | trans_pcie->txq[txq_id]->dma_addr >> 8); |
ae79785f | 1020 | } |
e22744af | 1021 | |
94ce9e5e | 1022 | iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); |
cb6bb128 EG |
1023 | if (trans->cfg->base_params->num_of_queues > 20) |
1024 | iwl_set_bits_prph(trans, SCD_GP_CTRL, | |
1025 | SCD_GP_CTRL_ENABLE_31_QUEUES); | |
1026 | ||
f02831be EG |
1027 | return 0; |
1028 | error: | |
1029 | /*Upon error, free only if we allocated something */ | |
1030 | if (alloc) | |
1031 | iwl_pcie_tx_free(trans); | |
1032 | return ret; | |
1033 | } | |
1034 | ||
4cf677fd | 1035 | static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) |
f02831be | 1036 | { |
e0b8d405 EG |
1037 | lockdep_assert_held(&txq->lock); |
1038 | ||
4cf677fd | 1039 | if (!txq->wd_timeout) |
f02831be EG |
1040 | return; |
1041 | ||
e0b8d405 EG |
1042 | /* |
1043 | * station is asleep and we send data - that must | |
1044 | * be uAPSD or PS-Poll. Don't rearm the timer. | |
1045 | */ | |
1046 | if (txq->frozen) | |
1047 | return; | |
1048 | ||
f02831be EG |
1049 | /* |
1050 | * if empty delete timer, otherwise move timer forward | |
1051 | * since we're making progress on this queue | |
1052 | */ | |
bb98ecd4 | 1053 | if (txq->read_ptr == txq->write_ptr) |
f02831be EG |
1054 | del_timer(&txq->stuck_timer); |
1055 | else | |
4cf677fd | 1056 | mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); |
f02831be EG |
1057 | } |
1058 | ||
1059 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
1060 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
1061 | struct sk_buff_head *skbs) | |
f02831be EG |
1062 | { |
1063 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
b2a3b1c1 | 1064 | struct iwl_txq *txq = trans_pcie->txq[txq_id]; |
83f32a4b | 1065 | int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); |
f02831be | 1066 | int last_to_free; |
f02831be EG |
1067 | |
1068 | /* This function is not meant to release cmd queue*/ | |
1069 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 1070 | return; |
214d14d4 | 1071 | |
2bfb5092 | 1072 | spin_lock_bh(&txq->lock); |
f6d497cd | 1073 | |
de74c455 | 1074 | if (!test_bit(txq_id, trans_pcie->queue_used)) { |
b967613d EG |
1075 | IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", |
1076 | txq_id, ssn); | |
1077 | goto out; | |
1078 | } | |
1079 | ||
bb98ecd4 | 1080 | if (txq->read_ptr == tfd_num) |
f6d497cd EG |
1081 | goto out; |
1082 | ||
1083 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
bb98ecd4 | 1084 | txq_id, txq->read_ptr, tfd_num, ssn); |
214d14d4 | 1085 | |
f02831be EG |
1086 | /*Since we free until index _not_ inclusive, the one before index is |
1087 | * the last we will free. This one must be used */ | |
83f32a4b | 1088 | last_to_free = iwl_queue_dec_wrap(tfd_num); |
f02831be | 1089 | |
bb98ecd4 | 1090 | if (!iwl_queue_used(txq, last_to_free)) { |
f02831be EG |
1091 | IWL_ERR(trans, |
1092 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
83f32a4b | 1093 | __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, |
bb98ecd4 | 1094 | txq->write_ptr, txq->read_ptr); |
f6d497cd | 1095 | goto out; |
214d14d4 JB |
1096 | } |
1097 | ||
f02831be | 1098 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 1099 | goto out; |
214d14d4 | 1100 | |
f02831be | 1101 | for (; |
bb98ecd4 SS |
1102 | txq->read_ptr != tfd_num; |
1103 | txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) { | |
1104 | struct sk_buff *skb = txq->entries[txq->read_ptr].skb; | |
214d14d4 | 1105 | |
6eb5e529 | 1106 | if (WARN_ON_ONCE(!skb)) |
f02831be | 1107 | continue; |
214d14d4 | 1108 | |
21cb3222 | 1109 | iwl_pcie_free_tso_page(trans_pcie, skb); |
6eb5e529 EG |
1110 | |
1111 | __skb_queue_tail(skbs, skb); | |
214d14d4 | 1112 | |
bb98ecd4 | 1113 | txq->entries[txq->read_ptr].skb = NULL; |
fd4abac5 | 1114 | |
4fe10bc6 SS |
1115 | if (!trans->cfg->use_tfh) |
1116 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); | |
fd4abac5 | 1117 | |
98891754 | 1118 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be | 1119 | } |
fd4abac5 | 1120 | |
4cf677fd | 1121 | iwl_pcie_txq_progress(txq); |
f02831be | 1122 | |
bb98ecd4 | 1123 | if (iwl_queue_space(txq) > txq->low_mark && |
3955525d | 1124 | test_bit(txq_id, trans_pcie->queue_stopped)) { |
685b346c | 1125 | struct sk_buff_head overflow_skbs; |
3955525d | 1126 | |
685b346c EG |
1127 | __skb_queue_head_init(&overflow_skbs); |
1128 | skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); | |
3955525d EG |
1129 | |
1130 | /* | |
1131 | * This is tricky: we are in reclaim path which is non | |
1132 | * re-entrant, so noone will try to take the access the | |
1133 | * txq data from that path. We stopped tx, so we can't | |
1134 | * have tx as well. Bottom line, we can unlock and re-lock | |
1135 | * later. | |
1136 | */ | |
1137 | spin_unlock_bh(&txq->lock); | |
1138 | ||
685b346c EG |
1139 | while (!skb_queue_empty(&overflow_skbs)) { |
1140 | struct sk_buff *skb = __skb_dequeue(&overflow_skbs); | |
21cb3222 JB |
1141 | struct iwl_device_cmd *dev_cmd_ptr; |
1142 | ||
1143 | dev_cmd_ptr = *(void **)((u8 *)skb->cb + | |
1144 | trans_pcie->dev_cmd_offs); | |
3955525d EG |
1145 | |
1146 | /* | |
1147 | * Note that we can very well be overflowing again. | |
1148 | * In that case, iwl_queue_space will be small again | |
1149 | * and we won't wake mac80211's queue. | |
1150 | */ | |
21cb3222 | 1151 | iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id); |
3955525d EG |
1152 | } |
1153 | spin_lock_bh(&txq->lock); | |
1154 | ||
bb98ecd4 | 1155 | if (iwl_queue_space(txq) > txq->low_mark) |
3955525d EG |
1156 | iwl_wake_queue(trans, txq); |
1157 | } | |
7616f334 | 1158 | |
bb98ecd4 SS |
1159 | if (txq->read_ptr == txq->write_ptr) { |
1160 | IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id); | |
c24c7f58 | 1161 | iwl_trans_unref(trans); |
7616f334 EP |
1162 | } |
1163 | ||
f6d497cd | 1164 | out: |
2bfb5092 | 1165 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
1166 | } |
1167 | ||
7616f334 EP |
1168 | static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, |
1169 | const struct iwl_host_cmd *cmd) | |
804d4c5a EP |
1170 | { |
1171 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1172 | int ret; | |
1173 | ||
1174 | lockdep_assert_held(&trans_pcie->reg_lock); | |
1175 | ||
7616f334 EP |
1176 | if (!(cmd->flags & CMD_SEND_IN_IDLE) && |
1177 | !trans_pcie->ref_cmd_in_flight) { | |
1178 | trans_pcie->ref_cmd_in_flight = true; | |
1179 | IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); | |
c24c7f58 | 1180 | iwl_trans_ref(trans); |
7616f334 EP |
1181 | } |
1182 | ||
804d4c5a EP |
1183 | /* |
1184 | * wake up the NIC to make sure that the firmware will see the host | |
1185 | * command - we will let the NIC sleep once all the host commands | |
1186 | * returned. This needs to be done only on NICs that have | |
1187 | * apmg_wake_up_wa set. | |
1188 | */ | |
fc8a350d IP |
1189 | if (trans->cfg->base_params->apmg_wake_up_wa && |
1190 | !trans_pcie->cmd_hold_nic_awake) { | |
804d4c5a EP |
1191 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
1192 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
804d4c5a EP |
1193 | |
1194 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1195 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1196 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1197 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), | |
1198 | 15000); | |
1199 | if (ret < 0) { | |
1200 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
1201 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
804d4c5a EP |
1202 | IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); |
1203 | return -EIO; | |
1204 | } | |
fc8a350d | 1205 | trans_pcie->cmd_hold_nic_awake = true; |
804d4c5a EP |
1206 | } |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
f02831be EG |
1211 | /* |
1212 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
1213 | * | |
1214 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1215 | * need to be reclaimed. As result, some free space forms. If there is | |
1216 | * enough free space (> low mark), wake the stack that feeds us. | |
1217 | */ | |
1218 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 1219 | { |
f02831be | 1220 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
b2a3b1c1 | 1221 | struct iwl_txq *txq = trans_pcie->txq[txq_id]; |
b9439491 | 1222 | unsigned long flags; |
f02831be | 1223 | int nfreed = 0; |
48d42c42 | 1224 | |
f02831be | 1225 | lockdep_assert_held(&txq->lock); |
48d42c42 | 1226 | |
bb98ecd4 | 1227 | if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(txq, idx))) { |
f02831be EG |
1228 | IWL_ERR(trans, |
1229 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
83f32a4b | 1230 | __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, |
bb98ecd4 | 1231 | txq->write_ptr, txq->read_ptr); |
f02831be EG |
1232 | return; |
1233 | } | |
48d42c42 | 1234 | |
bb98ecd4 SS |
1235 | for (idx = iwl_queue_inc_wrap(idx); txq->read_ptr != idx; |
1236 | txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) { | |
48d42c42 | 1237 | |
f02831be EG |
1238 | if (nfreed++ > 0) { |
1239 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
bb98ecd4 | 1240 | idx, txq->write_ptr, txq->read_ptr); |
4c9706dc | 1241 | iwl_force_nmi(trans); |
f02831be EG |
1242 | } |
1243 | } | |
1244 | ||
bb98ecd4 | 1245 | if (txq->read_ptr == txq->write_ptr) { |
b9439491 | 1246 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
804d4c5a | 1247 | iwl_pcie_clear_cmd_in_flight(trans); |
b9439491 EG |
1248 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1249 | } | |
1250 | ||
4cf677fd | 1251 | iwl_pcie_txq_progress(txq); |
48d42c42 EG |
1252 | } |
1253 | ||
f02831be | 1254 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1255 | u16 txq_id) |
48d42c42 | 1256 | { |
20d3b647 | 1257 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1258 | u32 tbl_dw_addr; |
1259 | u32 tbl_dw; | |
1260 | u16 scd_q2ratid; | |
1261 | ||
1262 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1263 | ||
105183b1 | 1264 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1265 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1266 | ||
4fd442db | 1267 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1268 | |
1269 | if (txq_id & 0x1) | |
1270 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1271 | else | |
1272 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1273 | ||
4fd442db | 1274 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1275 | |
1276 | return 0; | |
1277 | } | |
1278 | ||
bd5f6a34 EG |
1279 | /* Receiver address (actually, Rx station's index into station table), |
1280 | * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ | |
1281 | #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) | |
1282 | ||
dcfbd67b | 1283 | bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, |
4cf677fd EG |
1284 | const struct iwl_trans_txq_scd_cfg *cfg, |
1285 | unsigned int wdg_timeout) | |
48d42c42 | 1286 | { |
9eae88fa | 1287 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
b2a3b1c1 | 1288 | struct iwl_txq *txq = trans_pcie->txq[txq_id]; |
d4578ea8 | 1289 | int fifo = -1; |
dcfbd67b | 1290 | bool scd_bug = false; |
4beaf6c2 | 1291 | |
9eae88fa JB |
1292 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1293 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1294 | |
4cf677fd EG |
1295 | txq->wd_timeout = msecs_to_jiffies(wdg_timeout); |
1296 | ||
d4578ea8 JB |
1297 | if (cfg) { |
1298 | fifo = cfg->fifo; | |
48d42c42 | 1299 | |
002a9e26 | 1300 | /* Disable the scheduler prior configuring the cmd queue */ |
3a736bcb EG |
1301 | if (txq_id == trans_pcie->cmd_queue && |
1302 | trans_pcie->scd_set_active) | |
002a9e26 AA |
1303 | iwl_scd_enable_set_active(trans, 0); |
1304 | ||
d4578ea8 JB |
1305 | /* Stop this Tx queue before configuring it */ |
1306 | iwl_scd_txq_set_inactive(trans, txq_id); | |
4beaf6c2 | 1307 | |
d4578ea8 JB |
1308 | /* Set this queue as a chain-building queue unless it is CMD */ |
1309 | if (txq_id != trans_pcie->cmd_queue) | |
1310 | iwl_scd_txq_set_chain(trans, txq_id); | |
48d42c42 | 1311 | |
64ba8930 | 1312 | if (cfg->aggregate) { |
d4578ea8 | 1313 | u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); |
48d42c42 | 1314 | |
d4578ea8 JB |
1315 | /* Map receiver-address / traffic-ID to this queue */ |
1316 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); | |
f4772520 | 1317 | |
d4578ea8 JB |
1318 | /* enable aggregations for the queue */ |
1319 | iwl_scd_txq_enable_agg(trans, txq_id); | |
4cf677fd | 1320 | txq->ampdu = true; |
d4578ea8 JB |
1321 | } else { |
1322 | /* | |
1323 | * disable aggregations for the queue, this will also | |
1324 | * make the ra_tid mapping configuration irrelevant | |
1325 | * since it is now a non-AGG queue. | |
1326 | */ | |
1327 | iwl_scd_txq_disable_agg(trans, txq_id); | |
1328 | ||
bb98ecd4 | 1329 | ssn = txq->read_ptr; |
d4578ea8 | 1330 | } |
dcfbd67b EG |
1331 | } else { |
1332 | /* | |
1333 | * If we need to move the SCD write pointer by steps of | |
1334 | * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let | |
1335 | * the op_mode know by returning true later. | |
1336 | * Do this only in case cfg is NULL since this trick can | |
1337 | * be done only if we have DQA enabled which is true for mvm | |
1338 | * only. And mvm never sets a cfg pointer. | |
1339 | * This is really ugly, but this is the easiest way out for | |
1340 | * this sad hardware issue. | |
1341 | * This bug has been fixed on devices 9000 and up. | |
1342 | */ | |
1343 | scd_bug = !trans->cfg->mq_rx_supported && | |
1344 | !((ssn - txq->write_ptr) & 0x3f) && | |
1345 | (ssn != txq->write_ptr); | |
1346 | if (scd_bug) | |
1347 | ssn++; | |
4beaf6c2 | 1348 | } |
48d42c42 EG |
1349 | |
1350 | /* Place first TFD at index corresponding to start sequence number. | |
1351 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
bb98ecd4 SS |
1352 | txq->read_ptr = (ssn & 0xff); |
1353 | txq->write_ptr = (ssn & 0xff); | |
0294d9ee EG |
1354 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
1355 | (ssn & 0xff) | (txq_id << 8)); | |
1ce8658c | 1356 | |
d4578ea8 JB |
1357 | if (cfg) { |
1358 | u8 frame_limit = cfg->frame_limit; | |
48d42c42 | 1359 | |
d4578ea8 JB |
1360 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); |
1361 | ||
1362 | /* Set up Tx window size and frame limit for this queue */ | |
1363 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + | |
1364 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); | |
1365 | iwl_trans_write_mem32(trans, | |
1366 | trans_pcie->scd_base_addr + | |
9eae88fa | 1367 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
f3779f47 JB |
1368 | SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | |
1369 | SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); | |
d4578ea8 JB |
1370 | |
1371 | /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ | |
1372 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), | |
1373 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1374 | (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1375 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1376 | SCD_QUEUE_STTS_REG_MSK); | |
002a9e26 AA |
1377 | |
1378 | /* enable the scheduler for this queue (only) */ | |
3a736bcb EG |
1379 | if (txq_id == trans_pcie->cmd_queue && |
1380 | trans_pcie->scd_set_active) | |
002a9e26 | 1381 | iwl_scd_enable_set_active(trans, BIT(txq_id)); |
0294d9ee EG |
1382 | |
1383 | IWL_DEBUG_TX_QUEUES(trans, | |
1384 | "Activate queue %d on FIFO %d WrPtr: %d\n", | |
1385 | txq_id, fifo, ssn & 0xff); | |
1386 | } else { | |
1387 | IWL_DEBUG_TX_QUEUES(trans, | |
1388 | "Activate queue %d WrPtr: %d\n", | |
1389 | txq_id, ssn & 0xff); | |
d4578ea8 | 1390 | } |
dcfbd67b EG |
1391 | |
1392 | return scd_bug; | |
4beaf6c2 EG |
1393 | } |
1394 | ||
42db09c1 LK |
1395 | void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, |
1396 | bool shared_mode) | |
1397 | { | |
1398 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
b2a3b1c1 | 1399 | struct iwl_txq *txq = trans_pcie->txq[txq_id]; |
42db09c1 LK |
1400 | |
1401 | txq->ampdu = !shared_mode; | |
1402 | } | |
1403 | ||
d4578ea8 JB |
1404 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, |
1405 | bool configure_scd) | |
288712a6 | 1406 | { |
8ad71bef | 1407 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1408 | u32 stts_addr = trans_pcie->scd_base_addr + |
1409 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1410 | static const u32 zero_val[4] = {}; | |
288712a6 | 1411 | |
b2a3b1c1 SS |
1412 | trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0; |
1413 | trans_pcie->txq[txq_id]->frozen = false; | |
e0b8d405 | 1414 | |
fba1c627 EG |
1415 | /* |
1416 | * Upon HW Rfkill - we stop the device, and then stop the queues | |
1417 | * in the op_mode. Just for the sake of the simplicity of the op_mode, | |
1418 | * allow the op_mode to call txq_disable after it already called | |
1419 | * stop_device. | |
1420 | */ | |
9eae88fa | 1421 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
fba1c627 EG |
1422 | WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), |
1423 | "queue %d not used", txq_id); | |
9eae88fa | 1424 | return; |
48d42c42 EG |
1425 | } |
1426 | ||
d4578ea8 JB |
1427 | if (configure_scd) { |
1428 | iwl_scd_txq_set_inactive(trans, txq_id); | |
ac928f8d | 1429 | |
d4578ea8 JB |
1430 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1431 | ARRAY_SIZE(zero_val)); | |
1432 | } | |
986ea6c9 | 1433 | |
990aa6d7 | 1434 | iwl_pcie_txq_unmap(trans, txq_id); |
b2a3b1c1 | 1435 | trans_pcie->txq[txq_id]->ampdu = false; |
6c3fd3f0 | 1436 | |
1ce8658c | 1437 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1438 | } |
1439 | ||
fd4abac5 TW |
1440 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1441 | ||
990aa6d7 | 1442 | /* |
f02831be | 1443 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 | 1444 | * @priv: device private data point |
e89044d7 | 1445 | * @cmd: a pointer to the ucode command structure |
fd4abac5 | 1446 | * |
e89044d7 EP |
1447 | * The function returns < 0 values to indicate the operation |
1448 | * failed. On success, it returns the index (>= 0) of command in the | |
fd4abac5 TW |
1449 | * command queue. |
1450 | */ | |
f02831be EG |
1451 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1452 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1453 | { |
8ad71bef | 1454 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
b2a3b1c1 | 1455 | struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; |
c2acea8e JB |
1456 | struct iwl_device_cmd *out_cmd; |
1457 | struct iwl_cmd_meta *out_meta; | |
b9439491 | 1458 | unsigned long flags; |
f4feb8ac | 1459 | void *dup_buf = NULL; |
fd4abac5 | 1460 | dma_addr_t phys_addr; |
f4feb8ac | 1461 | int idx; |
8de437c7 | 1462 | u16 copy_size, cmd_size, tb0_size; |
4ce7cc2b | 1463 | bool had_nocopy = false; |
ab02165c | 1464 | u8 group_id = iwl_cmd_groupid(cmd->id); |
b9439491 | 1465 | int i, ret; |
96791422 | 1466 | u32 cmd_pos; |
1afbfb60 JB |
1467 | const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; |
1468 | u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; | |
fd4abac5 | 1469 | |
5b88792c | 1470 | if (WARN(!trans->wide_cmd_header && |
88742c9e | 1471 | group_id > IWL_ALWAYS_LONG_GROUP, |
ab02165c AE |
1472 | "unsupported wide command %#x\n", cmd->id)) |
1473 | return -EINVAL; | |
1474 | ||
1475 | if (group_id != 0) { | |
1476 | copy_size = sizeof(struct iwl_cmd_header_wide); | |
1477 | cmd_size = sizeof(struct iwl_cmd_header_wide); | |
1478 | } else { | |
1479 | copy_size = sizeof(struct iwl_cmd_header); | |
1480 | cmd_size = sizeof(struct iwl_cmd_header); | |
1481 | } | |
4ce7cc2b JB |
1482 | |
1483 | /* need one for the header if the first is NOCOPY */ | |
1afbfb60 | 1484 | BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); |
4ce7cc2b | 1485 | |
1afbfb60 | 1486 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1487 | cmddata[i] = cmd->data[i]; |
1488 | cmdlen[i] = cmd->len[i]; | |
1489 | ||
4ce7cc2b JB |
1490 | if (!cmd->len[i]) |
1491 | continue; | |
8a964f44 | 1492 | |
8de437c7 SS |
1493 | /* need at least IWL_FIRST_TB_SIZE copied */ |
1494 | if (copy_size < IWL_FIRST_TB_SIZE) { | |
1495 | int copy = IWL_FIRST_TB_SIZE - copy_size; | |
8a964f44 JB |
1496 | |
1497 | if (copy > cmdlen[i]) | |
1498 | copy = cmdlen[i]; | |
1499 | cmdlen[i] -= copy; | |
1500 | cmddata[i] += copy; | |
1501 | copy_size += copy; | |
1502 | } | |
1503 | ||
4ce7cc2b JB |
1504 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1505 | had_nocopy = true; | |
f4feb8ac JB |
1506 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1507 | idx = -EINVAL; | |
1508 | goto free_dup_buf; | |
1509 | } | |
1510 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1511 | /* | |
1512 | * This is also a chunk that isn't copied | |
1513 | * to the static buffer so set had_nocopy. | |
1514 | */ | |
1515 | had_nocopy = true; | |
1516 | ||
1517 | /* only allowed once */ | |
1518 | if (WARN_ON(dup_buf)) { | |
1519 | idx = -EINVAL; | |
1520 | goto free_dup_buf; | |
1521 | } | |
1522 | ||
8a964f44 | 1523 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1524 | GFP_ATOMIC); |
1525 | if (!dup_buf) | |
1526 | return -ENOMEM; | |
4ce7cc2b JB |
1527 | } else { |
1528 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1529 | if (WARN_ON(had_nocopy)) { |
1530 | idx = -EINVAL; | |
1531 | goto free_dup_buf; | |
1532 | } | |
8a964f44 | 1533 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1534 | } |
1535 | cmd_size += cmd->len[i]; | |
1536 | } | |
fd4abac5 | 1537 | |
3e41ace5 JB |
1538 | /* |
1539 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1540 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1541 | * allocated into separate TFDs, then we will need to | |
1542 | * increase the size of the buffers. | |
3e41ace5 | 1543 | */ |
2a79e45e JB |
1544 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1545 | "Command %s (%#x) is too large (%d bytes)\n", | |
39bdb17e SD |
1546 | iwl_get_cmd_string(trans, cmd->id), |
1547 | cmd->id, copy_size)) { | |
f4feb8ac JB |
1548 | idx = -EINVAL; |
1549 | goto free_dup_buf; | |
1550 | } | |
fd4abac5 | 1551 | |
015c15e1 | 1552 | spin_lock_bh(&txq->lock); |
3598e177 | 1553 | |
bb98ecd4 | 1554 | if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1555 | spin_unlock_bh(&txq->lock); |
3598e177 | 1556 | |
6d8f6eeb | 1557 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1558 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1559 | idx = -ENOSPC; |
1560 | goto free_dup_buf; | |
fd4abac5 TW |
1561 | } |
1562 | ||
bb98ecd4 | 1563 | idx = get_cmd_index(txq, txq->write_ptr); |
bf8440e6 JB |
1564 | out_cmd = txq->entries[idx].cmd; |
1565 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1566 | |
8ce73f3a | 1567 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1568 | if (cmd->flags & CMD_WANT_SKB) |
1569 | out_meta->source = cmd; | |
fd4abac5 | 1570 | |
4ce7cc2b | 1571 | /* set up the header */ |
ab02165c AE |
1572 | if (group_id != 0) { |
1573 | out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); | |
1574 | out_cmd->hdr_wide.group_id = group_id; | |
1575 | out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); | |
1576 | out_cmd->hdr_wide.length = | |
1577 | cpu_to_le16(cmd_size - | |
1578 | sizeof(struct iwl_cmd_header_wide)); | |
1579 | out_cmd->hdr_wide.reserved = 0; | |
1580 | out_cmd->hdr_wide.sequence = | |
1581 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | | |
bb98ecd4 | 1582 | INDEX_TO_SEQ(txq->write_ptr)); |
ab02165c AE |
1583 | |
1584 | cmd_pos = sizeof(struct iwl_cmd_header_wide); | |
1585 | copy_size = sizeof(struct iwl_cmd_header_wide); | |
1586 | } else { | |
1587 | out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); | |
1588 | out_cmd->hdr.sequence = | |
1589 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | | |
bb98ecd4 | 1590 | INDEX_TO_SEQ(txq->write_ptr)); |
ab02165c AE |
1591 | out_cmd->hdr.group_id = 0; |
1592 | ||
1593 | cmd_pos = sizeof(struct iwl_cmd_header); | |
1594 | copy_size = sizeof(struct iwl_cmd_header); | |
1595 | } | |
4ce7cc2b JB |
1596 | |
1597 | /* and copy the data that needs to be copied */ | |
1afbfb60 | 1598 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
4d075007 | 1599 | int copy; |
8a964f44 | 1600 | |
cc904c71 | 1601 | if (!cmd->len[i]) |
4ce7cc2b | 1602 | continue; |
8a964f44 | 1603 | |
8a964f44 JB |
1604 | /* copy everything if not nocopy/dup */ |
1605 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
4d075007 | 1606 | IWL_HCMD_DFL_DUP))) { |
8a964f44 JB |
1607 | copy = cmd->len[i]; |
1608 | ||
8a964f44 JB |
1609 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); |
1610 | cmd_pos += copy; | |
1611 | copy_size += copy; | |
4d075007 JB |
1612 | continue; |
1613 | } | |
1614 | ||
1615 | /* | |
8de437c7 SS |
1616 | * Otherwise we need at least IWL_FIRST_TB_SIZE copied |
1617 | * in total (for bi-directional DMA), but copy up to what | |
4d075007 JB |
1618 | * we can fit into the payload for debug dump purposes. |
1619 | */ | |
1620 | copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); | |
1621 | ||
1622 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1623 | cmd_pos += copy; | |
1624 | ||
1625 | /* However, treat copy_size the proper way, we need it below */ | |
8de437c7 SS |
1626 | if (copy_size < IWL_FIRST_TB_SIZE) { |
1627 | copy = IWL_FIRST_TB_SIZE - copy_size; | |
4d075007 JB |
1628 | |
1629 | if (copy > cmd->len[i]) | |
1630 | copy = cmd->len[i]; | |
1631 | copy_size += copy; | |
8a964f44 | 1632 | } |
96791422 EG |
1633 | } |
1634 | ||
d9fb6465 | 1635 | IWL_DEBUG_HC(trans, |
ab02165c | 1636 | "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
39bdb17e | 1637 | iwl_get_cmd_string(trans, cmd->id), |
ab02165c AE |
1638 | group_id, out_cmd->hdr.cmd, |
1639 | le16_to_cpu(out_cmd->hdr.sequence), | |
bb98ecd4 | 1640 | cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); |
4ce7cc2b | 1641 | |
8de437c7 SS |
1642 | /* start the TFD with the minimum copy bytes */ |
1643 | tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); | |
1644 | memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); | |
38c0f334 | 1645 | iwl_pcie_txq_build_tfd(trans, txq, |
8de437c7 SS |
1646 | iwl_pcie_get_first_tb_dma(txq, idx), |
1647 | tb0_size, true); | |
38c0f334 JB |
1648 | |
1649 | /* map first command fragment, if any remains */ | |
8de437c7 | 1650 | if (copy_size > tb0_size) { |
38c0f334 | 1651 | phys_addr = dma_map_single(trans->dev, |
8de437c7 SS |
1652 | ((u8 *)&out_cmd->hdr) + tb0_size, |
1653 | copy_size - tb0_size, | |
38c0f334 JB |
1654 | DMA_TO_DEVICE); |
1655 | if (dma_mapping_error(trans->dev, phys_addr)) { | |
bb98ecd4 SS |
1656 | iwl_pcie_tfd_unmap(trans, out_meta, txq, |
1657 | txq->write_ptr); | |
38c0f334 JB |
1658 | idx = -ENOMEM; |
1659 | goto out; | |
1660 | } | |
8a964f44 | 1661 | |
38c0f334 | 1662 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, |
8de437c7 | 1663 | copy_size - tb0_size, false); |
2c46f72e JB |
1664 | } |
1665 | ||
8a964f44 | 1666 | /* map the remaining (adjusted) nocopy/dup fragments */ |
1afbfb60 | 1667 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 | 1668 | const void *data = cmddata[i]; |
f4feb8ac | 1669 | |
8a964f44 | 1670 | if (!cmdlen[i]) |
4ce7cc2b | 1671 | continue; |
f4feb8ac JB |
1672 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1673 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1674 | continue; |
f4feb8ac JB |
1675 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1676 | data = dup_buf; | |
1677 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
98891754 | 1678 | cmdlen[i], DMA_TO_DEVICE); |
1042db2a | 1679 | if (dma_mapping_error(trans->dev, phys_addr)) { |
bb98ecd4 SS |
1680 | iwl_pcie_tfd_unmap(trans, out_meta, txq, |
1681 | txq->write_ptr); | |
4ce7cc2b JB |
1682 | idx = -ENOMEM; |
1683 | goto out; | |
1684 | } | |
1685 | ||
6d6e68f8 | 1686 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); |
4ce7cc2b | 1687 | } |
df833b1d | 1688 | |
3cd1980b | 1689 | BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); |
afaf6b57 | 1690 | out_meta->flags = cmd->flags; |
f4feb8ac | 1691 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
5d4185ae | 1692 | kzfree(txq->entries[idx].free_buf); |
f4feb8ac | 1693 | txq->entries[idx].free_buf = dup_buf; |
2c46f72e | 1694 | |
ab02165c | 1695 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); |
df833b1d | 1696 | |
7c5ba4a8 | 1697 | /* start timer if queue currently empty */ |
bb98ecd4 | 1698 | if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) |
4cf677fd | 1699 | mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); |
7c5ba4a8 | 1700 | |
b9439491 | 1701 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
7616f334 | 1702 | ret = iwl_pcie_set_cmd_in_flight(trans, cmd); |
804d4c5a EP |
1703 | if (ret < 0) { |
1704 | idx = ret; | |
1705 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1706 | goto out; | |
b9439491 EG |
1707 | } |
1708 | ||
fd4abac5 | 1709 | /* Increment and update queue's write index */ |
bb98ecd4 | 1710 | txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr); |
990aa6d7 | 1711 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1712 | |
b9439491 EG |
1713 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1714 | ||
2c46f72e | 1715 | out: |
015c15e1 | 1716 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1717 | free_dup_buf: |
1718 | if (idx < 0) | |
1719 | kfree(dup_buf); | |
7bfedc59 | 1720 | return idx; |
fd4abac5 TW |
1721 | } |
1722 | ||
990aa6d7 EG |
1723 | /* |
1724 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1725 | * @rxb: Rx buffer to reclaim |
17b88929 | 1726 | */ |
990aa6d7 | 1727 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
f7e6469f | 1728 | struct iwl_rx_cmd_buffer *rxb) |
17b88929 | 1729 | { |
2f301227 | 1730 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 | 1731 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
d490e097 | 1732 | u8 group_id; |
39bdb17e | 1733 | u32 cmd_id; |
17b88929 TW |
1734 | int txq_id = SEQ_TO_QUEUE(sequence); |
1735 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1736 | int cmd_index; |
c2acea8e JB |
1737 | struct iwl_device_cmd *cmd; |
1738 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1739 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
b2a3b1c1 | 1740 | struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1741 | |
1742 | /* If a Tx command is being handled and it isn't in the actual | |
1743 | * command queue then there a command routing bug has been introduced | |
1744 | * in the queue management code. */ | |
c6f600fc | 1745 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1746 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
b2a3b1c1 SS |
1747 | txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr, |
1748 | txq->write_ptr)) { | |
3e10caeb | 1749 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1750 | return; |
01ef9323 | 1751 | } |
17b88929 | 1752 | |
2bfb5092 | 1753 | spin_lock_bh(&txq->lock); |
015c15e1 | 1754 | |
bb98ecd4 | 1755 | cmd_index = get_cmd_index(txq, index); |
bf8440e6 JB |
1756 | cmd = txq->entries[cmd_index].cmd; |
1757 | meta = &txq->entries[cmd_index].meta; | |
d490e097 | 1758 | group_id = cmd->hdr.group_id; |
39bdb17e | 1759 | cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); |
17b88929 | 1760 | |
6983ba69 | 1761 | iwl_pcie_tfd_unmap(trans, meta, txq, index); |
c33de625 | 1762 | |
17b88929 | 1763 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1764 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1765 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1766 | |
65b94a4a JB |
1767 | meta->source->resp_pkt = pkt; |
1768 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1769 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1770 | } |
2624e96c | 1771 | |
dcbb4746 EG |
1772 | if (meta->flags & CMD_WANT_ASYNC_CALLBACK) |
1773 | iwl_op_mode_async_cb(trans->op_mode, cmd); | |
1774 | ||
f02831be | 1775 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1776 | |
c2acea8e | 1777 | if (!(meta->flags & CMD_ASYNC)) { |
eb7ff77e | 1778 | if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { |
05c89b91 WYG |
1779 | IWL_WARN(trans, |
1780 | "HCMD_ACTIVE already clear for command %s\n", | |
39bdb17e | 1781 | iwl_get_cmd_string(trans, cmd_id)); |
05c89b91 | 1782 | } |
eb7ff77e | 1783 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6d8f6eeb | 1784 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
39bdb17e | 1785 | iwl_get_cmd_string(trans, cmd_id)); |
f946b529 | 1786 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1787 | } |
3598e177 | 1788 | |
4cbb8e50 LC |
1789 | if (meta->flags & CMD_MAKE_TRANS_IDLE) { |
1790 | IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", | |
1791 | iwl_get_cmd_string(trans, cmd->hdr.cmd)); | |
1792 | set_bit(STATUS_TRANS_IDLE, &trans->status); | |
1793 | wake_up(&trans_pcie->d0i3_waitq); | |
1794 | } | |
1795 | ||
1796 | if (meta->flags & CMD_WAKE_UP_TRANS) { | |
1797 | IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", | |
1798 | iwl_get_cmd_string(trans, cmd->hdr.cmd)); | |
1799 | clear_bit(STATUS_TRANS_IDLE, &trans->status); | |
1800 | wake_up(&trans_pcie->d0i3_waitq); | |
1801 | } | |
1802 | ||
dd487449 | 1803 | meta->flags = 0; |
3598e177 | 1804 | |
2bfb5092 | 1805 | spin_unlock_bh(&txq->lock); |
17b88929 | 1806 | } |
253a634c | 1807 | |
9439eac7 | 1808 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
253a634c | 1809 | |
f02831be EG |
1810 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1811 | struct iwl_host_cmd *cmd) | |
253a634c EG |
1812 | { |
1813 | int ret; | |
1814 | ||
1815 | /* An asynchronous command can not expect an SKB to be set. */ | |
1816 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1817 | return -EINVAL; | |
1818 | ||
f02831be | 1819 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1820 | if (ret < 0) { |
721c32f7 | 1821 | IWL_ERR(trans, |
b36b110c | 1822 | "Error sending %s: enqueue_hcmd failed: %d\n", |
39bdb17e | 1823 | iwl_get_cmd_string(trans, cmd->id), ret); |
253a634c EG |
1824 | return ret; |
1825 | } | |
1826 | return 0; | |
1827 | } | |
1828 | ||
f02831be EG |
1829 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1830 | struct iwl_host_cmd *cmd) | |
253a634c | 1831 | { |
8ad71bef | 1832 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
b2a3b1c1 | 1833 | struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; |
253a634c EG |
1834 | int cmd_idx; |
1835 | int ret; | |
1836 | ||
6d8f6eeb | 1837 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
39bdb17e | 1838 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c | 1839 | |
eb7ff77e AN |
1840 | if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, |
1841 | &trans->status), | |
bcbb8c9c | 1842 | "Command %s: a command is already active!\n", |
39bdb17e | 1843 | iwl_get_cmd_string(trans, cmd->id))) |
2cc39c94 | 1844 | return -EIO; |
2cc39c94 | 1845 | |
6d8f6eeb | 1846 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
39bdb17e | 1847 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c | 1848 | |
71b1230c LC |
1849 | if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { |
1850 | ret = wait_event_timeout(trans_pcie->d0i3_waitq, | |
1851 | pm_runtime_active(&trans_pcie->pci_dev->dev), | |
1852 | msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); | |
1853 | if (!ret) { | |
1854 | IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); | |
1855 | return -ETIMEDOUT; | |
1856 | } | |
1857 | } | |
1858 | ||
f02831be | 1859 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1860 | if (cmd_idx < 0) { |
1861 | ret = cmd_idx; | |
eb7ff77e | 1862 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
721c32f7 | 1863 | IWL_ERR(trans, |
b36b110c | 1864 | "Error sending %s: enqueue_hcmd failed: %d\n", |
39bdb17e | 1865 | iwl_get_cmd_string(trans, cmd->id), ret); |
253a634c EG |
1866 | return ret; |
1867 | } | |
1868 | ||
b9439491 EG |
1869 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
1870 | !test_bit(STATUS_SYNC_HCMD_ACTIVE, | |
1871 | &trans->status), | |
1872 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1873 | if (!ret) { |
6dde8c48 | 1874 | IWL_ERR(trans, "Error sending %s: time out after %dms.\n", |
39bdb17e | 1875 | iwl_get_cmd_string(trans, cmd->id), |
6dde8c48 | 1876 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
253a634c | 1877 | |
6dde8c48 | 1878 | IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", |
bb98ecd4 | 1879 | txq->read_ptr, txq->write_ptr); |
d10630af | 1880 | |
eb7ff77e | 1881 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6dde8c48 | 1882 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
39bdb17e | 1883 | iwl_get_cmd_string(trans, cmd->id)); |
6dde8c48 | 1884 | ret = -ETIMEDOUT; |
42550a53 | 1885 | |
4c9706dc | 1886 | iwl_force_nmi(trans); |
2a988e98 | 1887 | iwl_trans_fw_error(trans); |
42550a53 | 1888 | |
6dde8c48 | 1889 | goto cancel; |
253a634c EG |
1890 | } |
1891 | ||
eb7ff77e | 1892 | if (test_bit(STATUS_FW_ERROR, &trans->status)) { |
d18aa87f | 1893 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", |
39bdb17e | 1894 | iwl_get_cmd_string(trans, cmd->id)); |
b656fa33 | 1895 | dump_stack(); |
d18aa87f JB |
1896 | ret = -EIO; |
1897 | goto cancel; | |
1898 | } | |
1899 | ||
1094fa26 | 1900 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
326477e4 | 1901 | test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { |
f946b529 EG |
1902 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); |
1903 | ret = -ERFKILL; | |
1904 | goto cancel; | |
1905 | } | |
1906 | ||
65b94a4a | 1907 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1908 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
39bdb17e | 1909 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c EG |
1910 | ret = -EIO; |
1911 | goto cancel; | |
1912 | } | |
1913 | ||
1914 | return 0; | |
1915 | ||
1916 | cancel: | |
1917 | if (cmd->flags & CMD_WANT_SKB) { | |
1918 | /* | |
1919 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1920 | * TX cmd queue. Otherwise in case the cmd comes | |
1921 | * in later, it will possibly set an invalid | |
1922 | * address (cmd->meta.source). | |
1923 | */ | |
b2a3b1c1 | 1924 | txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; |
253a634c | 1925 | } |
9cac4943 | 1926 | |
65b94a4a JB |
1927 | if (cmd->resp_pkt) { |
1928 | iwl_free_resp(cmd); | |
1929 | cmd->resp_pkt = NULL; | |
253a634c EG |
1930 | } |
1931 | ||
1932 | return ret; | |
1933 | } | |
1934 | ||
f02831be | 1935 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1936 | { |
4f59334b | 1937 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
326477e4 | 1938 | test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { |
754d7d9e EG |
1939 | IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", |
1940 | cmd->id); | |
f946b529 | 1941 | return -ERFKILL; |
754d7d9e | 1942 | } |
f946b529 | 1943 | |
253a634c | 1944 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1945 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1946 | |
f946b529 | 1947 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1948 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1949 | } |
1950 | ||
3a0b2a42 EG |
1951 | static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, |
1952 | struct iwl_txq *txq, u8 hdr_len, | |
1953 | struct iwl_cmd_meta *out_meta, | |
1954 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
1955 | { | |
6983ba69 | 1956 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
3a0b2a42 EG |
1957 | u16 tb2_len; |
1958 | int i; | |
1959 | ||
1960 | /* | |
1961 | * Set up TFD's third entry to point directly to remainder | |
1962 | * of skb's head, if any | |
1963 | */ | |
1964 | tb2_len = skb_headlen(skb) - hdr_len; | |
1965 | ||
1966 | if (tb2_len > 0) { | |
1967 | dma_addr_t tb2_phys = dma_map_single(trans->dev, | |
1968 | skb->data + hdr_len, | |
1969 | tb2_len, DMA_TO_DEVICE); | |
1970 | if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { | |
bb98ecd4 SS |
1971 | iwl_pcie_tfd_unmap(trans, out_meta, txq, |
1972 | txq->write_ptr); | |
3a0b2a42 EG |
1973 | return -EINVAL; |
1974 | } | |
1975 | iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); | |
1976 | } | |
1977 | ||
1978 | /* set up the remaining entries to point to the data */ | |
1979 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1980 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1981 | dma_addr_t tb_phys; | |
1982 | int tb_idx; | |
1983 | ||
1984 | if (!skb_frag_size(frag)) | |
1985 | continue; | |
1986 | ||
1987 | tb_phys = skb_frag_dma_map(trans->dev, frag, 0, | |
1988 | skb_frag_size(frag), DMA_TO_DEVICE); | |
1989 | ||
1990 | if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { | |
bb98ecd4 SS |
1991 | iwl_pcie_tfd_unmap(trans, out_meta, txq, |
1992 | txq->write_ptr); | |
3a0b2a42 EG |
1993 | return -EINVAL; |
1994 | } | |
1995 | tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, | |
1996 | skb_frag_size(frag), false); | |
1997 | ||
3cd1980b | 1998 | out_meta->tbs |= BIT(tb_idx); |
3a0b2a42 EG |
1999 | } |
2000 | ||
2001 | trace_iwlwifi_dev_tx(trans->dev, skb, | |
bb98ecd4 | 2002 | iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr), |
6983ba69 | 2003 | trans_pcie->tfd_size, |
8de437c7 | 2004 | &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, |
8790fce4 | 2005 | hdr_len); |
78c1acf3 | 2006 | trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len); |
3a0b2a42 EG |
2007 | return 0; |
2008 | } | |
2009 | ||
6eb5e529 | 2010 | #ifdef CONFIG_INET |
6ffe5de3 | 2011 | struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len) |
6eb5e529 EG |
2012 | { |
2013 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2014 | struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); | |
2015 | ||
2016 | if (!p->page) | |
2017 | goto alloc; | |
2018 | ||
2019 | /* enough room on this page */ | |
2020 | if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) | |
2021 | return p; | |
2022 | ||
2023 | /* We don't have enough room on this page, get a new one. */ | |
2024 | __free_page(p->page); | |
2025 | ||
2026 | alloc: | |
2027 | p->page = alloc_page(GFP_ATOMIC); | |
2028 | if (!p->page) | |
2029 | return NULL; | |
2030 | p->pos = page_address(p->page); | |
2031 | return p; | |
2032 | } | |
2033 | ||
2034 | static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, | |
2035 | bool ipv6, unsigned int len) | |
2036 | { | |
2037 | if (ipv6) { | |
2038 | struct ipv6hdr *iphv6 = iph; | |
2039 | ||
2040 | tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, | |
2041 | len + tcph->doff * 4, | |
2042 | IPPROTO_TCP, 0); | |
2043 | } else { | |
2044 | struct iphdr *iphv4 = iph; | |
2045 | ||
2046 | ip_send_check(iphv4); | |
2047 | tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, | |
2048 | len + tcph->doff * 4, | |
2049 | IPPROTO_TCP, 0); | |
2050 | } | |
2051 | } | |
2052 | ||
066fd29a SS |
2053 | static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, |
2054 | struct iwl_txq *txq, u8 hdr_len, | |
2055 | struct iwl_cmd_meta *out_meta, | |
2056 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
6eb5e529 | 2057 | { |
05e5a7e5 | 2058 | struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; |
6eb5e529 EG |
2059 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; |
2060 | struct ieee80211_hdr *hdr = (void *)skb->data; | |
2061 | unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; | |
2062 | unsigned int mss = skb_shinfo(skb)->gso_size; | |
6eb5e529 EG |
2063 | u16 length, iv_len, amsdu_pad; |
2064 | u8 *start_hdr; | |
2065 | struct iwl_tso_hdr_page *hdr_page; | |
21cb3222 | 2066 | struct page **page_ptr; |
6eb5e529 EG |
2067 | int ret; |
2068 | struct tso_t tso; | |
2069 | ||
2070 | /* if the packet is protected, then it must be CCMP or GCMP */ | |
2071 | BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); | |
2072 | iv_len = ieee80211_has_protected(hdr->frame_control) ? | |
2073 | IEEE80211_CCMP_HDR_LEN : 0; | |
2074 | ||
2075 | trace_iwlwifi_dev_tx(trans->dev, skb, | |
bb98ecd4 | 2076 | iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr), |
6983ba69 | 2077 | trans_pcie->tfd_size, |
8790fce4 | 2078 | &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); |
6eb5e529 EG |
2079 | |
2080 | ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); | |
2081 | snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); | |
2082 | total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; | |
2083 | amsdu_pad = 0; | |
2084 | ||
2085 | /* total amount of header we may need for this A-MSDU */ | |
2086 | hdr_room = DIV_ROUND_UP(total_len, mss) * | |
2087 | (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; | |
2088 | ||
2089 | /* Our device supports 9 segments at most, it will fit in 1 page */ | |
2090 | hdr_page = get_page_hdr(trans, hdr_room); | |
2091 | if (!hdr_page) | |
2092 | return -ENOMEM; | |
2093 | ||
2094 | get_page(hdr_page->page); | |
2095 | start_hdr = hdr_page->pos; | |
21cb3222 JB |
2096 | page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); |
2097 | *page_ptr = hdr_page->page; | |
6eb5e529 EG |
2098 | memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); |
2099 | hdr_page->pos += iv_len; | |
2100 | ||
2101 | /* | |
2102 | * Pull the ieee80211 header + IV to be able to use TSO core, | |
2103 | * we will restore it for the tx_status flow. | |
2104 | */ | |
2105 | skb_pull(skb, hdr_len + iv_len); | |
2106 | ||
05e5a7e5 JB |
2107 | /* |
2108 | * Remove the length of all the headers that we don't actually | |
2109 | * have in the MPDU by themselves, but that we duplicate into | |
2110 | * all the different MSDUs inside the A-MSDU. | |
2111 | */ | |
2112 | le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); | |
2113 | ||
6eb5e529 EG |
2114 | tso_start(skb, &tso); |
2115 | ||
2116 | while (total_len) { | |
2117 | /* this is the data left for this subframe */ | |
2118 | unsigned int data_left = | |
2119 | min_t(unsigned int, mss, total_len); | |
2120 | struct sk_buff *csum_skb = NULL; | |
2121 | unsigned int hdr_tb_len; | |
2122 | dma_addr_t hdr_tb_phys; | |
2123 | struct tcphdr *tcph; | |
05e5a7e5 | 2124 | u8 *iph, *subf_hdrs_start = hdr_page->pos; |
6eb5e529 EG |
2125 | |
2126 | total_len -= data_left; | |
2127 | ||
2128 | memset(hdr_page->pos, 0, amsdu_pad); | |
2129 | hdr_page->pos += amsdu_pad; | |
2130 | amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + | |
2131 | data_left)) & 0x3; | |
2132 | ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); | |
2133 | hdr_page->pos += ETH_ALEN; | |
2134 | ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); | |
2135 | hdr_page->pos += ETH_ALEN; | |
2136 | ||
2137 | length = snap_ip_tcp_hdrlen + data_left; | |
2138 | *((__be16 *)hdr_page->pos) = cpu_to_be16(length); | |
2139 | hdr_page->pos += sizeof(length); | |
2140 | ||
2141 | /* | |
2142 | * This will copy the SNAP as well which will be considered | |
2143 | * as MAC header. | |
2144 | */ | |
2145 | tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); | |
2146 | iph = hdr_page->pos + 8; | |
2147 | tcph = (void *)(iph + ip_hdrlen); | |
2148 | ||
2149 | /* For testing on current hardware only */ | |
2150 | if (trans_pcie->sw_csum_tx) { | |
2151 | csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), | |
2152 | GFP_ATOMIC); | |
2153 | if (!csum_skb) { | |
2154 | ret = -ENOMEM; | |
2155 | goto out_unmap; | |
2156 | } | |
2157 | ||
2158 | iwl_compute_pseudo_hdr_csum(iph, tcph, | |
2159 | skb->protocol == | |
2160 | htons(ETH_P_IPV6), | |
2161 | data_left); | |
2162 | ||
59ae1d12 | 2163 | skb_put_data(csum_skb, tcph, tcp_hdrlen(skb)); |
a52a8a4d | 2164 | skb_reset_transport_header(csum_skb); |
6eb5e529 EG |
2165 | csum_skb->csum_start = |
2166 | (unsigned char *)tcp_hdr(csum_skb) - | |
2167 | csum_skb->head; | |
2168 | } | |
2169 | ||
2170 | hdr_page->pos += snap_ip_tcp_hdrlen; | |
2171 | ||
2172 | hdr_tb_len = hdr_page->pos - start_hdr; | |
2173 | hdr_tb_phys = dma_map_single(trans->dev, start_hdr, | |
2174 | hdr_tb_len, DMA_TO_DEVICE); | |
2175 | if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { | |
2176 | dev_kfree_skb(csum_skb); | |
2177 | ret = -EINVAL; | |
2178 | goto out_unmap; | |
2179 | } | |
2180 | iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, | |
2181 | hdr_tb_len, false); | |
2182 | trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, | |
2183 | hdr_tb_len); | |
05e5a7e5 JB |
2184 | /* add this subframe's headers' length to the tx_cmd */ |
2185 | le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); | |
6eb5e529 EG |
2186 | |
2187 | /* prepare the start_hdr for the next subframe */ | |
2188 | start_hdr = hdr_page->pos; | |
2189 | ||
2190 | /* put the payload */ | |
2191 | while (data_left) { | |
2192 | unsigned int size = min_t(unsigned int, tso.size, | |
2193 | data_left); | |
2194 | dma_addr_t tb_phys; | |
2195 | ||
2196 | if (trans_pcie->sw_csum_tx) | |
59ae1d12 | 2197 | skb_put_data(csum_skb, tso.data, size); |
6eb5e529 EG |
2198 | |
2199 | tb_phys = dma_map_single(trans->dev, tso.data, | |
2200 | size, DMA_TO_DEVICE); | |
2201 | if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { | |
2202 | dev_kfree_skb(csum_skb); | |
2203 | ret = -EINVAL; | |
2204 | goto out_unmap; | |
2205 | } | |
2206 | ||
2207 | iwl_pcie_txq_build_tfd(trans, txq, tb_phys, | |
2208 | size, false); | |
2209 | trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, | |
2210 | size); | |
2211 | ||
2212 | data_left -= size; | |
2213 | tso_build_data(skb, &tso, size); | |
2214 | } | |
2215 | ||
2216 | /* For testing on early hardware only */ | |
2217 | if (trans_pcie->sw_csum_tx) { | |
2218 | __wsum csum; | |
2219 | ||
2220 | csum = skb_checksum(csum_skb, | |
2221 | skb_checksum_start_offset(csum_skb), | |
2222 | csum_skb->len - | |
2223 | skb_checksum_start_offset(csum_skb), | |
2224 | 0); | |
2225 | dev_kfree_skb(csum_skb); | |
2226 | dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, | |
2227 | hdr_tb_len, DMA_TO_DEVICE); | |
2228 | tcph->check = csum_fold(csum); | |
2229 | dma_sync_single_for_device(trans->dev, hdr_tb_phys, | |
2230 | hdr_tb_len, DMA_TO_DEVICE); | |
2231 | } | |
2232 | } | |
2233 | ||
2234 | /* re -add the WiFi header and IV */ | |
2235 | skb_push(skb, hdr_len + iv_len); | |
2236 | ||
2237 | return 0; | |
2238 | ||
2239 | out_unmap: | |
bb98ecd4 | 2240 | iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr); |
6eb5e529 EG |
2241 | return ret; |
2242 | } | |
2243 | #else /* CONFIG_INET */ | |
2244 | static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, | |
2245 | struct iwl_txq *txq, u8 hdr_len, | |
2246 | struct iwl_cmd_meta *out_meta, | |
2247 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
2248 | { | |
2249 | /* No A-MSDU without CONFIG_INET */ | |
2250 | WARN_ON(1); | |
2251 | ||
2252 | return -1; | |
2253 | } | |
2254 | #endif /* CONFIG_INET */ | |
2255 | ||
f02831be EG |
2256 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
2257 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 2258 | { |
8ad71bef | 2259 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
206eea78 | 2260 | struct ieee80211_hdr *hdr; |
f02831be EG |
2261 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; |
2262 | struct iwl_cmd_meta *out_meta; | |
2263 | struct iwl_txq *txq; | |
38c0f334 JB |
2264 | dma_addr_t tb0_phys, tb1_phys, scratch_phys; |
2265 | void *tb1_addr; | |
4fe10bc6 | 2266 | void *tfd; |
3a0b2a42 | 2267 | u16 len, tb1_len; |
ea68f460 | 2268 | bool wait_write_ptr; |
206eea78 JB |
2269 | __le16 fc; |
2270 | u8 hdr_len; | |
68972c46 | 2271 | u16 wifi_seq; |
c772a3d3 | 2272 | bool amsdu; |
f02831be | 2273 | |
b2a3b1c1 | 2274 | txq = trans_pcie->txq[txq_id]; |
a0eaad71 | 2275 | |
961de6a5 JB |
2276 | if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), |
2277 | "TX on unused queue %d\n", txq_id)) | |
f02831be | 2278 | return -EINVAL; |
39644e9a | 2279 | |
41837ca9 EG |
2280 | if (unlikely(trans_pcie->sw_csum_tx && |
2281 | skb->ip_summed == CHECKSUM_PARTIAL)) { | |
2282 | int offs = skb_checksum_start_offset(skb); | |
2283 | int csum_offs = offs + skb->csum_offset; | |
2284 | __wsum csum; | |
2285 | ||
2286 | if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) | |
2287 | return -1; | |
2288 | ||
2289 | csum = skb_checksum(skb, offs, skb->len - offs, 0); | |
2290 | *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); | |
3955525d EG |
2291 | |
2292 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
41837ca9 EG |
2293 | } |
2294 | ||
206eea78 | 2295 | if (skb_is_nonlinear(skb) && |
3cd1980b | 2296 | skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && |
206eea78 JB |
2297 | __skb_linearize(skb)) |
2298 | return -ENOMEM; | |
2299 | ||
2300 | /* mac80211 always puts the full header into the SKB's head, | |
2301 | * so there's no need to check if it's readable there | |
2302 | */ | |
2303 | hdr = (struct ieee80211_hdr *)skb->data; | |
2304 | fc = hdr->frame_control; | |
2305 | hdr_len = ieee80211_hdrlen(fc); | |
2306 | ||
f02831be | 2307 | spin_lock(&txq->lock); |
015c15e1 | 2308 | |
bb98ecd4 | 2309 | if (iwl_queue_space(txq) < txq->high_mark) { |
3955525d EG |
2310 | iwl_stop_queue(trans, txq); |
2311 | ||
2312 | /* don't put the packet on the ring, if there is no room */ | |
bb98ecd4 | 2313 | if (unlikely(iwl_queue_space(txq) < 3)) { |
21cb3222 JB |
2314 | struct iwl_device_cmd **dev_cmd_ptr; |
2315 | ||
2316 | dev_cmd_ptr = (void *)((u8 *)skb->cb + | |
2317 | trans_pcie->dev_cmd_offs); | |
3955525d | 2318 | |
21cb3222 | 2319 | *dev_cmd_ptr = dev_cmd; |
3955525d EG |
2320 | __skb_queue_tail(&txq->overflow_q, skb); |
2321 | ||
2322 | spin_unlock(&txq->lock); | |
2323 | return 0; | |
2324 | } | |
2325 | } | |
2326 | ||
f02831be EG |
2327 | /* In AGG mode, the index in the ring must correspond to the WiFi |
2328 | * sequence number. This is a HW requirements to help the SCD to parse | |
2329 | * the BA. | |
2330 | * Check here that the packets are in the right place on the ring. | |
2331 | */ | |
9a886586 | 2332 | wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
1092b9bc | 2333 | WARN_ONCE(txq->ampdu && |
bb98ecd4 | 2334 | (wifi_seq & 0xff) != txq->write_ptr, |
f02831be | 2335 | "Q: %d WiFi Seq %d tfdNum %d", |
bb98ecd4 | 2336 | txq_id, wifi_seq, txq->write_ptr); |
f02831be EG |
2337 | |
2338 | /* Set up driver data for this TFD */ | |
bb98ecd4 SS |
2339 | txq->entries[txq->write_ptr].skb = skb; |
2340 | txq->entries[txq->write_ptr].cmd = dev_cmd; | |
f02831be | 2341 | |
f02831be EG |
2342 | dev_cmd->hdr.sequence = |
2343 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
bb98ecd4 | 2344 | INDEX_TO_SEQ(txq->write_ptr))); |
f02831be | 2345 | |
bb98ecd4 | 2346 | tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); |
38c0f334 JB |
2347 | scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + |
2348 | offsetof(struct iwl_tx_cmd, scratch); | |
2349 | ||
2350 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
2351 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
2352 | ||
f02831be | 2353 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
bb98ecd4 | 2354 | out_meta = &txq->entries[txq->write_ptr].meta; |
206eea78 | 2355 | out_meta->flags = 0; |
a0eaad71 | 2356 | |
f02831be | 2357 | /* |
38c0f334 JB |
2358 | * The second TB (tb1) points to the remainder of the TX command |
2359 | * and the 802.11 header - dword aligned size | |
2360 | * (This calculation modifies the TX command, so do it before the | |
2361 | * setup of the first TB) | |
f02831be | 2362 | */ |
38c0f334 | 2363 | len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + |
8de437c7 | 2364 | hdr_len - IWL_FIRST_TB_SIZE; |
c772a3d3 SS |
2365 | /* do not align A-MSDU to dword as the subframe header aligns it */ |
2366 | amsdu = ieee80211_is_data_qos(fc) && | |
2367 | (*ieee80211_get_qos_ctl(hdr) & | |
2368 | IEEE80211_QOS_CTL_A_MSDU_PRESENT); | |
2369 | if (trans_pcie->sw_csum_tx || !amsdu) { | |
2370 | tb1_len = ALIGN(len, 4); | |
2371 | /* Tell NIC about any 2-byte padding after MAC header */ | |
2372 | if (tb1_len != len) | |
2373 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
2374 | } else { | |
2375 | tb1_len = len; | |
2376 | } | |
f02831be | 2377 | |
05e5a7e5 JB |
2378 | /* |
2379 | * The first TB points to bi-directional DMA data, we'll | |
2380 | * memcpy the data into it later. | |
2381 | */ | |
38c0f334 | 2382 | iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, |
8de437c7 | 2383 | IWL_FIRST_TB_SIZE, true); |
f02831be | 2384 | |
38c0f334 | 2385 | /* there must be data left over for TB1 or this code must be changed */ |
8de437c7 | 2386 | BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); |
38c0f334 JB |
2387 | |
2388 | /* map the data for TB1 */ | |
8de437c7 | 2389 | tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; |
38c0f334 JB |
2390 | tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); |
2391 | if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) | |
2392 | goto out_err; | |
6d6e68f8 | 2393 | iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); |
a0eaad71 | 2394 | |
c772a3d3 | 2395 | if (amsdu) { |
6eb5e529 EG |
2396 | if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, |
2397 | out_meta, dev_cmd, | |
2398 | tb1_len))) | |
2399 | goto out_err; | |
2400 | } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, | |
2401 | out_meta, dev_cmd, tb1_len))) { | |
3a0b2a42 | 2402 | goto out_err; |
6eb5e529 | 2403 | } |
206eea78 | 2404 | |
05e5a7e5 JB |
2405 | /* building the A-MSDU might have changed this data, so memcpy it now */ |
2406 | memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr, | |
2407 | IWL_FIRST_TB_SIZE); | |
2408 | ||
bb98ecd4 | 2409 | tfd = iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr); |
f02831be | 2410 | /* Set up entry for this TFD in Tx byte-count array */ |
4fe10bc6 SS |
2411 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), |
2412 | iwl_pcie_tfd_get_num_tbs(trans, tfd)); | |
a0eaad71 | 2413 | |
ea68f460 | 2414 | wait_write_ptr = ieee80211_has_morefrags(fc); |
7c5ba4a8 | 2415 | |
f02831be | 2416 | /* start timer if queue currently empty */ |
bb98ecd4 | 2417 | if (txq->read_ptr == txq->write_ptr) { |
aecdc63d EG |
2418 | if (txq->wd_timeout) { |
2419 | /* | |
2420 | * If the TXQ is active, then set the timer, if not, | |
2421 | * set the timer in remainder so that the timer will | |
2422 | * be armed with the right value when the station will | |
2423 | * wake up. | |
2424 | */ | |
2425 | if (!txq->frozen) | |
2426 | mod_timer(&txq->stuck_timer, | |
2427 | jiffies + txq->wd_timeout); | |
2428 | else | |
2429 | txq->frozen_expiry_remainder = txq->wd_timeout; | |
2430 | } | |
bb98ecd4 | 2431 | IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id); |
c24c7f58 | 2432 | iwl_trans_ref(trans); |
7616f334 | 2433 | } |
f02831be EG |
2434 | |
2435 | /* Tell device the write index *just past* this latest filled TFD */ | |
bb98ecd4 | 2436 | txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr); |
ea68f460 JB |
2437 | if (!wait_write_ptr) |
2438 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
f02831be EG |
2439 | |
2440 | /* | |
2441 | * At this point the frame is "transmitted" successfully | |
43aa616f | 2442 | * and we will get a TX status notification eventually. |
f02831be | 2443 | */ |
f02831be EG |
2444 | spin_unlock(&txq->lock); |
2445 | return 0; | |
2446 | out_err: | |
2447 | spin_unlock(&txq->lock); | |
2448 | return -1; | |
a0eaad71 | 2449 | } |