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43f66a6c | 1 | /****************************************************************************** |
bf79451e | 2 | |
a0e04ab3 | 3 | Copyright(c) 2003 - 2005 Intel Corporation. All rights reserved. |
bf79451e JG |
4 | |
5 | This program is free software; you can redistribute it and/or modify it | |
6 | under the terms of version 2 of the GNU General Public License as | |
43f66a6c | 7 | published by the Free Software Foundation. |
bf79451e JG |
8 | |
9 | This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
43f66a6c | 12 | more details. |
bf79451e | 13 | |
43f66a6c | 14 | You should have received a copy of the GNU General Public License along with |
bf79451e | 15 | this program; if not, write to the Free Software Foundation, Inc., 59 |
43f66a6c | 16 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
bf79451e | 17 | |
43f66a6c JK |
18 | The full GNU General Public License is included in this distribution in the |
19 | file called LICENSE. | |
bf79451e | 20 | |
43f66a6c JK |
21 | Contact Information: |
22 | James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
23 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | ||
25 | ******************************************************************************/ | |
26 | ||
27 | #ifndef __ipw2200_h__ | |
28 | #define __ipw2200_h__ | |
29 | ||
30 | #define WEXT_USECHANNELS 1 | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/config.h> | |
35 | #include <linux/init.h> | |
36 | ||
43f66a6c JK |
37 | #include <linux/pci.h> |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/skbuff.h> | |
41 | #include <linux/etherdevice.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/random.h> | |
843684a2 | 44 | #include <linux/dma-mapping.h> |
43f66a6c JK |
45 | |
46 | #include <linux/firmware.h> | |
47 | #include <linux/wireless.h> | |
3da54c5b | 48 | #include <linux/dma-mapping.h> |
43f66a6c JK |
49 | #include <asm/io.h> |
50 | ||
51 | #include <net/ieee80211.h> | |
24a47dbd | 52 | #include <net/ieee80211_radiotap.h> |
43f66a6c JK |
53 | |
54 | #define DRV_NAME "ipw2200" | |
55 | ||
56 | #include <linux/workqueue.h> | |
57 | ||
43f66a6c | 58 | /* Authentication and Association States */ |
0edd5b44 | 59 | enum connection_manager_assoc_states { |
43f66a6c JK |
60 | CMAS_INIT = 0, |
61 | CMAS_TX_AUTH_SEQ_1, | |
62 | CMAS_RX_AUTH_SEQ_2, | |
63 | CMAS_AUTH_SEQ_1_PASS, | |
64 | CMAS_AUTH_SEQ_1_FAIL, | |
65 | CMAS_TX_AUTH_SEQ_3, | |
66 | CMAS_RX_AUTH_SEQ_4, | |
67 | CMAS_AUTH_SEQ_2_PASS, | |
68 | CMAS_AUTH_SEQ_2_FAIL, | |
69 | CMAS_AUTHENTICATED, | |
70 | CMAS_TX_ASSOC, | |
71 | CMAS_RX_ASSOC_RESP, | |
72 | CMAS_ASSOCIATED, | |
73 | CMAS_LAST | |
74 | }; | |
75 | ||
43f66a6c JK |
76 | #define IPW_WAIT (1<<0) |
77 | #define IPW_QUIET (1<<1) | |
78 | #define IPW_ROAMING (1<<2) | |
79 | ||
80 | #define IPW_POWER_MODE_CAM 0x00 //(always on) | |
81 | #define IPW_POWER_INDEX_1 0x01 | |
82 | #define IPW_POWER_INDEX_2 0x02 | |
83 | #define IPW_POWER_INDEX_3 0x03 | |
84 | #define IPW_POWER_INDEX_4 0x04 | |
85 | #define IPW_POWER_INDEX_5 0x05 | |
86 | #define IPW_POWER_AC 0x06 | |
87 | #define IPW_POWER_BATTERY 0x07 | |
88 | #define IPW_POWER_LIMIT 0x07 | |
89 | #define IPW_POWER_MASK 0x0F | |
90 | #define IPW_POWER_ENABLED 0x10 | |
91 | #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK) | |
92 | ||
93 | #define IPW_CMD_HOST_COMPLETE 2 | |
94 | #define IPW_CMD_POWER_DOWN 4 | |
95 | #define IPW_CMD_SYSTEM_CONFIG 6 | |
96 | #define IPW_CMD_MULTICAST_ADDRESS 7 | |
97 | #define IPW_CMD_SSID 8 | |
98 | #define IPW_CMD_ADAPTER_ADDRESS 11 | |
99 | #define IPW_CMD_PORT_TYPE 12 | |
100 | #define IPW_CMD_RTS_THRESHOLD 15 | |
101 | #define IPW_CMD_FRAG_THRESHOLD 16 | |
102 | #define IPW_CMD_POWER_MODE 17 | |
103 | #define IPW_CMD_WEP_KEY 18 | |
104 | #define IPW_CMD_TGI_TX_KEY 19 | |
105 | #define IPW_CMD_SCAN_REQUEST 20 | |
106 | #define IPW_CMD_ASSOCIATE 21 | |
107 | #define IPW_CMD_SUPPORTED_RATES 22 | |
108 | #define IPW_CMD_SCAN_ABORT 23 | |
109 | #define IPW_CMD_TX_FLUSH 24 | |
110 | #define IPW_CMD_QOS_PARAMETERS 25 | |
111 | #define IPW_CMD_SCAN_REQUEST_EXT 26 | |
112 | #define IPW_CMD_DINO_CONFIG 30 | |
113 | #define IPW_CMD_RSN_CAPABILITIES 31 | |
114 | #define IPW_CMD_RX_KEY 32 | |
115 | #define IPW_CMD_CARD_DISABLE 33 | |
116 | #define IPW_CMD_SEED_NUMBER 34 | |
117 | #define IPW_CMD_TX_POWER 35 | |
118 | #define IPW_CMD_COUNTRY_INFO 36 | |
119 | #define IPW_CMD_AIRONET_INFO 37 | |
120 | #define IPW_CMD_AP_TX_POWER 38 | |
121 | #define IPW_CMD_CCKM_INFO 39 | |
122 | #define IPW_CMD_CCX_VER_INFO 40 | |
123 | #define IPW_CMD_SET_CALIBRATION 41 | |
124 | #define IPW_CMD_SENSITIVITY_CALIB 42 | |
125 | #define IPW_CMD_RETRY_LIMIT 51 | |
126 | #define IPW_CMD_IPW_PRE_POWER_DOWN 58 | |
127 | #define IPW_CMD_VAP_BEACON_TEMPLATE 60 | |
128 | #define IPW_CMD_VAP_DTIM_PERIOD 61 | |
129 | #define IPW_CMD_EXT_SUPPORTED_RATES 62 | |
130 | #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63 | |
131 | #define IPW_CMD_VAP_QUIET_INTERVALS 64 | |
132 | #define IPW_CMD_VAP_CHANNEL_SWITCH 65 | |
133 | #define IPW_CMD_VAP_MANDATORY_CHANNELS 66 | |
134 | #define IPW_CMD_VAP_CELL_PWR_LIMIT 67 | |
135 | #define IPW_CMD_VAP_CF_PARAM_SET 68 | |
136 | #define IPW_CMD_VAP_SET_BEACONING_STATE 69 | |
137 | #define IPW_CMD_MEASUREMENT 80 | |
138 | #define IPW_CMD_POWER_CAPABILITY 81 | |
139 | #define IPW_CMD_SUPPORTED_CHANNELS 82 | |
140 | #define IPW_CMD_TPC_REPORT 83 | |
141 | #define IPW_CMD_WME_INFO 84 | |
142 | #define IPW_CMD_PRODUCTION_COMMAND 85 | |
143 | #define IPW_CMD_LINKSYS_EOU_INFO 90 | |
144 | ||
145 | #define RFD_SIZE 4 | |
146 | #define NUM_TFD_CHUNKS 6 | |
147 | ||
148 | #define TX_QUEUE_SIZE 32 | |
149 | #define RX_QUEUE_SIZE 32 | |
150 | ||
151 | #define DINO_CMD_WEP_KEY 0x08 | |
152 | #define DINO_CMD_TX 0x0B | |
153 | #define DCT_ANTENNA_A 0x01 | |
154 | #define DCT_ANTENNA_B 0x02 | |
155 | ||
156 | #define IPW_A_MODE 0 | |
157 | #define IPW_B_MODE 1 | |
158 | #define IPW_G_MODE 2 | |
159 | ||
bf79451e JG |
160 | /* |
161 | * TX Queue Flag Definitions | |
43f66a6c JK |
162 | */ |
163 | ||
b095c381 JK |
164 | /* tx wep key definition */ |
165 | #define DCT_WEP_KEY_NOT_IMMIDIATE 0x00 | |
166 | #define DCT_WEP_KEY_64Bit 0x40 | |
167 | #define DCT_WEP_KEY_128Bit 0x80 | |
168 | #define DCT_WEP_KEY_128bitIV 0xC0 | |
169 | #define DCT_WEP_KEY_SIZE_MASK 0xC0 | |
170 | ||
171 | #define DCT_WEP_KEY_INDEX_MASK 0x0F | |
172 | #define DCT_WEP_INDEX_USE_IMMEDIATE 0x20 | |
173 | ||
43f66a6c | 174 | /* abort attempt if mgmt frame is rx'd */ |
bf79451e JG |
175 | #define DCT_FLAG_ABORT_MGMT 0x01 |
176 | ||
43f66a6c JK |
177 | /* require CTS */ |
178 | #define DCT_FLAG_CTS_REQUIRED 0x02 | |
179 | ||
180 | /* use short preamble */ | |
ea2b26e0 JK |
181 | #define DCT_FLAG_LONG_PREAMBLE 0x00 |
182 | #define DCT_FLAG_SHORT_PREAMBLE 0x04 | |
43f66a6c JK |
183 | |
184 | /* RTS/CTS first */ | |
185 | #define DCT_FLAG_RTS_REQD 0x08 | |
186 | ||
187 | /* dont calculate duration field */ | |
188 | #define DCT_FLAG_DUR_SET 0x10 | |
189 | ||
190 | /* even if MAC WEP set (allows pre-encrypt) */ | |
191 | #define DCT_FLAG_NO_WEP 0x20 | |
8d45ff7d | 192 | |
43f66a6c JK |
193 | /* overwrite TSF field */ |
194 | #define DCT_FLAG_TSF_REQD 0x40 | |
195 | ||
196 | /* ACK rx is expected to follow */ | |
bf79451e | 197 | #define DCT_FLAG_ACK_REQD 0x80 |
43f66a6c | 198 | |
b095c381 | 199 | /* TX flags extension */ |
43f66a6c JK |
200 | #define DCT_FLAG_EXT_MODE_CCK 0x01 |
201 | #define DCT_FLAG_EXT_MODE_OFDM 0x00 | |
202 | ||
b095c381 JK |
203 | #define DCT_FLAG_EXT_SECURITY_WEP 0x00 |
204 | #define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP | |
205 | #define DCT_FLAG_EXT_SECURITY_CKIP 0x04 | |
206 | #define DCT_FLAG_EXT_SECURITY_CCM 0x08 | |
207 | #define DCT_FLAG_EXT_SECURITY_TKIP 0x0C | |
208 | #define DCT_FLAG_EXT_SECURITY_MASK 0x0C | |
209 | ||
210 | #define DCT_FLAG_EXT_QOS_ENABLED 0x10 | |
211 | ||
212 | #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00 | |
213 | #define DCT_FLAG_EXT_HC_SIFS 0x20 | |
214 | #define DCT_FLAG_EXT_HC_PIFS 0x40 | |
215 | ||
43f66a6c JK |
216 | #define TX_RX_TYPE_MASK 0xFF |
217 | #define TX_FRAME_TYPE 0x00 | |
218 | #define TX_HOST_COMMAND_TYPE 0x01 | |
219 | #define RX_FRAME_TYPE 0x09 | |
220 | #define RX_HOST_NOTIFICATION_TYPE 0x03 | |
221 | #define RX_HOST_CMD_RESPONSE_TYPE 0x04 | |
222 | #define RX_TX_FRAME_RESPONSE_TYPE 0x05 | |
223 | #define TFD_NEED_IRQ_MASK 0x04 | |
224 | ||
225 | #define HOST_CMD_DINO_CONFIG 30 | |
226 | ||
227 | #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10 | |
228 | #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11 | |
229 | #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12 | |
230 | #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13 | |
231 | #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14 | |
232 | #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15 | |
233 | #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16 | |
234 | #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17 | |
235 | #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18 | |
236 | #define HOST_NOTIFICATION_TX_STATUS 19 | |
237 | #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20 | |
238 | #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21 | |
239 | #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22 | |
240 | #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23 | |
241 | #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24 | |
242 | #define HOST_NOTIFICATION_NOISE_STATS 25 | |
bf79451e | 243 | #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30 |
43f66a6c JK |
244 | #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31 |
245 | ||
246 | #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1 | |
247 | #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24 | |
248 | #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8 | |
bf79451e | 249 | #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300 |
43f66a6c JK |
250 | |
251 | #define MACADRR_BYTE_LEN 6 | |
252 | ||
253 | #define DCR_TYPE_AP 0x01 | |
254 | #define DCR_TYPE_WLAP 0x02 | |
255 | #define DCR_TYPE_MU_ESS 0x03 | |
256 | #define DCR_TYPE_MU_IBSS 0x04 | |
257 | #define DCR_TYPE_MU_PIBSS 0x05 | |
258 | #define DCR_TYPE_SNIFFER 0x06 | |
259 | #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS | |
260 | ||
b095c381 JK |
261 | /* QoS definitions */ |
262 | ||
263 | #define CW_MIN_OFDM 15 | |
264 | #define CW_MAX_OFDM 1023 | |
265 | #define CW_MIN_CCK 31 | |
266 | #define CW_MAX_CCK 1023 | |
267 | ||
268 | #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM | |
269 | #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM | |
270 | #define QOS_TX2_CW_MIN_OFDM ( (CW_MIN_OFDM + 1) / 2 - 1 ) | |
271 | #define QOS_TX3_CW_MIN_OFDM ( (CW_MIN_OFDM + 1) / 4 - 1 ) | |
272 | ||
273 | #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK | |
274 | #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK | |
275 | #define QOS_TX2_CW_MIN_CCK ( (CW_MIN_CCK + 1) / 2 - 1 ) | |
276 | #define QOS_TX3_CW_MIN_CCK ( (CW_MIN_CCK + 1) / 4 - 1 ) | |
277 | ||
278 | #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM | |
279 | #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM | |
280 | #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM | |
281 | #define QOS_TX3_CW_MAX_OFDM ( (CW_MIN_OFDM + 1) / 2 - 1 ) | |
282 | ||
283 | #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK | |
284 | #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK | |
285 | #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK | |
286 | #define QOS_TX3_CW_MAX_CCK ( (CW_MIN_CCK + 1) / 2 - 1 ) | |
287 | ||
288 | #define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE) | |
289 | #define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE) | |
290 | #define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE) | |
291 | #define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE) | |
292 | ||
293 | #define QOS_TX0_ACM 0 | |
294 | #define QOS_TX1_ACM 0 | |
295 | #define QOS_TX2_ACM 0 | |
296 | #define QOS_TX3_ACM 0 | |
297 | ||
298 | #define QOS_TX0_TXOP_LIMIT_CCK 0 | |
299 | #define QOS_TX1_TXOP_LIMIT_CCK 0 | |
300 | #define QOS_TX2_TXOP_LIMIT_CCK 6016 | |
301 | #define QOS_TX3_TXOP_LIMIT_CCK 3264 | |
302 | ||
303 | #define QOS_TX0_TXOP_LIMIT_OFDM 0 | |
304 | #define QOS_TX1_TXOP_LIMIT_OFDM 0 | |
305 | #define QOS_TX2_TXOP_LIMIT_OFDM 3008 | |
306 | #define QOS_TX3_TXOP_LIMIT_OFDM 1504 | |
307 | ||
308 | #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM | |
309 | #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM | |
310 | #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM | |
311 | #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM | |
312 | ||
313 | #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK | |
314 | #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK | |
315 | #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK | |
316 | #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK | |
317 | ||
318 | #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM | |
319 | #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM | |
320 | #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM | |
321 | #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM | |
322 | ||
323 | #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK | |
324 | #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK | |
325 | #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK | |
326 | #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK | |
327 | ||
328 | #define DEF_TX0_AIFS 0 | |
329 | #define DEF_TX1_AIFS 0 | |
330 | #define DEF_TX2_AIFS 0 | |
331 | #define DEF_TX3_AIFS 0 | |
332 | ||
333 | #define DEF_TX0_ACM 0 | |
334 | #define DEF_TX1_ACM 0 | |
335 | #define DEF_TX2_ACM 0 | |
336 | #define DEF_TX3_ACM 0 | |
337 | ||
338 | #define DEF_TX0_TXOP_LIMIT_CCK 0 | |
339 | #define DEF_TX1_TXOP_LIMIT_CCK 0 | |
340 | #define DEF_TX2_TXOP_LIMIT_CCK 0 | |
341 | #define DEF_TX3_TXOP_LIMIT_CCK 0 | |
342 | ||
343 | #define DEF_TX0_TXOP_LIMIT_OFDM 0 | |
344 | #define DEF_TX1_TXOP_LIMIT_OFDM 0 | |
345 | #define DEF_TX2_TXOP_LIMIT_OFDM 0 | |
346 | #define DEF_TX3_TXOP_LIMIT_OFDM 0 | |
347 | ||
348 | #define QOS_QOS_SETS 3 | |
349 | #define QOS_PARAM_SET_ACTIVE 0 | |
350 | #define QOS_PARAM_SET_DEF_CCK 1 | |
351 | #define QOS_PARAM_SET_DEF_OFDM 2 | |
352 | ||
353 | #define CTRL_QOS_NO_ACK (0x0020) | |
354 | ||
355 | #define IPW_TX_QUEUE_1 1 | |
356 | #define IPW_TX_QUEUE_2 2 | |
357 | #define IPW_TX_QUEUE_3 3 | |
358 | #define IPW_TX_QUEUE_4 4 | |
359 | ||
360 | /* QoS sturctures */ | |
361 | struct ipw_qos_info { | |
362 | int qos_enable; | |
363 | struct ieee80211_qos_parameters *def_qos_parm_OFDM; | |
364 | struct ieee80211_qos_parameters *def_qos_parm_CCK; | |
365 | u32 burst_duration_CCK; | |
366 | u32 burst_duration_OFDM; | |
367 | u16 qos_no_ack_mask; | |
368 | int burst_enable; | |
369 | }; | |
370 | ||
371 | /**************************************************************/ | |
43f66a6c JK |
372 | /** |
373 | * Generic queue structure | |
bf79451e | 374 | * |
43f66a6c JK |
375 | * Contains common data for Rx and Tx queues |
376 | */ | |
377 | struct clx2_queue { | |
0edd5b44 JG |
378 | int n_bd; /**< number of BDs in this queue */ |
379 | int first_empty; /**< 1-st empty entry (index) */ | |
380 | int last_used; /**< last used entry (index) */ | |
381 | u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */ | |
382 | u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */ | |
383 | dma_addr_t dma_addr; /**< physical addr for BD's */ | |
384 | int low_mark; /**< low watermark, resume queue if free space more than this */ | |
385 | int high_mark; /**< high watermark, stop queue if free space less than this */ | |
43f66a6c JK |
386 | } __attribute__ ((packed)); |
387 | ||
0edd5b44 | 388 | struct machdr32 { |
43f66a6c | 389 | u16 frame_ctl; |
0edd5b44 JG |
390 | u16 duration; // watch out for endians! |
391 | u8 addr1[MACADRR_BYTE_LEN]; | |
392 | u8 addr2[MACADRR_BYTE_LEN]; | |
393 | u8 addr3[MACADRR_BYTE_LEN]; | |
394 | u16 seq_ctrl; // more endians! | |
395 | u8 addr4[MACADRR_BYTE_LEN]; | |
43f66a6c | 396 | u16 qos_ctrl; |
0edd5b44 | 397 | } __attribute__ ((packed)); |
43f66a6c | 398 | |
0edd5b44 | 399 | struct machdr30 { |
43f66a6c | 400 | u16 frame_ctl; |
0edd5b44 JG |
401 | u16 duration; // watch out for endians! |
402 | u8 addr1[MACADRR_BYTE_LEN]; | |
403 | u8 addr2[MACADRR_BYTE_LEN]; | |
404 | u8 addr3[MACADRR_BYTE_LEN]; | |
405 | u16 seq_ctrl; // more endians! | |
406 | u8 addr4[MACADRR_BYTE_LEN]; | |
407 | } __attribute__ ((packed)); | |
408 | ||
409 | struct machdr26 { | |
43f66a6c | 410 | u16 frame_ctl; |
0edd5b44 JG |
411 | u16 duration; // watch out for endians! |
412 | u8 addr1[MACADRR_BYTE_LEN]; | |
413 | u8 addr2[MACADRR_BYTE_LEN]; | |
414 | u8 addr3[MACADRR_BYTE_LEN]; | |
415 | u16 seq_ctrl; // more endians! | |
43f66a6c | 416 | u16 qos_ctrl; |
0edd5b44 | 417 | } __attribute__ ((packed)); |
43f66a6c | 418 | |
0edd5b44 | 419 | struct machdr24 { |
43f66a6c | 420 | u16 frame_ctl; |
0edd5b44 JG |
421 | u16 duration; // watch out for endians! |
422 | u8 addr1[MACADRR_BYTE_LEN]; | |
423 | u8 addr2[MACADRR_BYTE_LEN]; | |
424 | u8 addr3[MACADRR_BYTE_LEN]; | |
425 | u16 seq_ctrl; // more endians! | |
426 | } __attribute__ ((packed)); | |
43f66a6c JK |
427 | |
428 | // TX TFD with 32 byte MAC Header | |
0edd5b44 JG |
429 | struct tx_tfd_32 { |
430 | struct machdr32 mchdr; // 32 | |
431 | u32 uivplaceholder[2]; // 8 | |
432 | } __attribute__ ((packed)); | |
43f66a6c JK |
433 | |
434 | // TX TFD with 30 byte MAC Header | |
0edd5b44 JG |
435 | struct tx_tfd_30 { |
436 | struct machdr30 mchdr; // 30 | |
437 | u8 reserved[2]; // 2 | |
438 | u32 uivplaceholder[2]; // 8 | |
439 | } __attribute__ ((packed)); | |
43f66a6c JK |
440 | |
441 | // tx tfd with 26 byte mac header | |
0edd5b44 JG |
442 | struct tx_tfd_26 { |
443 | struct machdr26 mchdr; // 26 | |
444 | u8 reserved1[2]; // 2 | |
445 | u32 uivplaceholder[2]; // 8 | |
446 | u8 reserved2[4]; // 4 | |
447 | } __attribute__ ((packed)); | |
43f66a6c JK |
448 | |
449 | // tx tfd with 24 byte mac header | |
0edd5b44 JG |
450 | struct tx_tfd_24 { |
451 | struct machdr24 mchdr; // 24 | |
452 | u32 uivplaceholder[2]; // 8 | |
453 | u8 reserved[8]; // 8 | |
454 | } __attribute__ ((packed)); | |
43f66a6c JK |
455 | |
456 | #define DCT_WEP_KEY_FIELD_LENGTH 16 | |
457 | ||
0edd5b44 | 458 | struct tfd_command { |
43f66a6c JK |
459 | u8 index; |
460 | u8 length; | |
461 | u16 reserved; | |
462 | u8 payload[0]; | |
0edd5b44 | 463 | } __attribute__ ((packed)); |
43f66a6c JK |
464 | |
465 | struct tfd_data { | |
466 | /* Header */ | |
467 | u32 work_area_ptr; | |
0edd5b44 | 468 | u8 station_number; /* 0 for BSS */ |
43f66a6c JK |
469 | u8 reserved1; |
470 | u16 reserved2; | |
471 | ||
472 | /* Tx Parameters */ | |
473 | u8 cmd_id; | |
bf79451e JG |
474 | u8 seq_num; |
475 | u16 len; | |
43f66a6c JK |
476 | u8 priority; |
477 | u8 tx_flags; | |
478 | u8 tx_flags_ext; | |
479 | u8 key_index; | |
480 | u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH]; | |
481 | u8 rate; | |
482 | u8 antenna; | |
483 | u16 next_packet_duration; | |
bf79451e | 484 | u16 next_frag_len; |
0edd5b44 | 485 | u16 back_off_counter; //////txop; |
43f66a6c | 486 | u8 retrylimit; |
bf79451e | 487 | u16 cwcurrent; |
43f66a6c JK |
488 | u8 reserved3; |
489 | ||
490 | /* 802.11 MAC Header */ | |
0edd5b44 | 491 | union { |
43f66a6c JK |
492 | struct tx_tfd_24 tfd_24; |
493 | struct tx_tfd_26 tfd_26; | |
494 | struct tx_tfd_30 tfd_30; | |
495 | struct tx_tfd_32 tfd_32; | |
496 | } tfd; | |
497 | ||
498 | /* Payload DMA info */ | |
499 | u32 num_chunks; | |
500 | u32 chunk_ptr[NUM_TFD_CHUNKS]; | |
501 | u16 chunk_len[NUM_TFD_CHUNKS]; | |
502 | } __attribute__ ((packed)); | |
503 | ||
0edd5b44 | 504 | struct txrx_control_flags { |
43f66a6c JK |
505 | u8 message_type; |
506 | u8 rx_seq_num; | |
507 | u8 control_bits; | |
508 | u8 reserved; | |
509 | } __attribute__ ((packed)); | |
510 | ||
511 | #define TFD_SIZE 128 | |
512 | #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags)) | |
513 | ||
0edd5b44 | 514 | struct tfd_frame { |
43f66a6c JK |
515 | struct txrx_control_flags control_flags; |
516 | union { | |
517 | struct tfd_data data; | |
518 | struct tfd_command cmd; | |
519 | u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH]; | |
520 | } u; | |
0edd5b44 | 521 | } __attribute__ ((packed)); |
43f66a6c | 522 | |
0edd5b44 | 523 | typedef void destructor_func(const void *); |
43f66a6c JK |
524 | |
525 | /** | |
526 | * Tx Queue for DMA. Queue consists of circular buffer of | |
527 | * BD's and required locking structures. | |
528 | */ | |
529 | struct clx2_tx_queue { | |
530 | struct clx2_queue q; | |
0edd5b44 | 531 | struct tfd_frame *bd; |
43f66a6c JK |
532 | struct ieee80211_txb **txb; |
533 | }; | |
534 | ||
535 | /* | |
536 | * RX related structures and functions | |
537 | */ | |
538 | #define RX_FREE_BUFFERS 32 | |
539 | #define RX_LOW_WATERMARK 8 | |
540 | ||
a613bffd JK |
541 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 |
542 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
543 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
43f66a6c JK |
544 | |
545 | // Used for passing to driver number of successes and failures per rate | |
0edd5b44 | 546 | struct rate_histogram { |
43f66a6c JK |
547 | union { |
548 | u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS]; | |
549 | u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS]; | |
550 | u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS]; | |
551 | } success; | |
552 | union { | |
553 | u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS]; | |
554 | u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS]; | |
555 | u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS]; | |
556 | } failed; | |
557 | } __attribute__ ((packed)); | |
558 | ||
bf79451e | 559 | /* statistics command response */ |
43f66a6c JK |
560 | struct ipw_cmd_stats { |
561 | u8 cmd_id; | |
562 | u8 seq_num; | |
bf79451e JG |
563 | u16 good_sfd; |
564 | u16 bad_plcp; | |
565 | u16 wrong_bssid; | |
566 | u16 valid_mpdu; | |
567 | u16 bad_mac_header; | |
568 | u16 reserved_frame_types; | |
569 | u16 rx_ina; | |
570 | u16 bad_crc32; | |
571 | u16 invalid_cts; | |
572 | u16 invalid_acks; | |
573 | u16 long_distance_ina_fina; | |
43f66a6c | 574 | u16 dsp_silence_unreachable; |
bf79451e JG |
575 | u16 accumulated_rssi; |
576 | u16 rx_ovfl_frame_tossed; | |
43f66a6c JK |
577 | u16 rssi_silence_threshold; |
578 | u16 rx_ovfl_frame_supplied; | |
bf79451e JG |
579 | u16 last_rx_frame_signal; |
580 | u16 last_rx_frame_noise; | |
581 | u16 rx_autodetec_no_ofdm; | |
43f66a6c JK |
582 | u16 rx_autodetec_no_barker; |
583 | u16 reserved; | |
584 | } __attribute__ ((packed)); | |
585 | ||
586 | struct notif_channel_result { | |
587 | u8 channel_num; | |
588 | struct ipw_cmd_stats stats; | |
589 | u8 uReserved; | |
590 | } __attribute__ ((packed)); | |
591 | ||
e7582561 BC |
592 | #define SCAN_COMPLETED_STATUS_COMPLETE 1 |
593 | #define SCAN_COMPLETED_STATUS_ABORTED 2 | |
594 | ||
43f66a6c JK |
595 | struct notif_scan_complete { |
596 | u8 scan_type; | |
597 | u8 num_channels; | |
598 | u8 status; | |
599 | u8 reserved; | |
0edd5b44 | 600 | } __attribute__ ((packed)); |
43f66a6c JK |
601 | |
602 | struct notif_frag_length { | |
603 | u16 frag_length; | |
604 | u16 reserved; | |
0edd5b44 | 605 | } __attribute__ ((packed)); |
43f66a6c JK |
606 | |
607 | struct notif_beacon_state { | |
608 | u32 state; | |
609 | u32 number; | |
610 | } __attribute__ ((packed)); | |
611 | ||
612 | struct notif_tgi_tx_key { | |
613 | u8 key_state; | |
614 | u8 security_type; | |
615 | u8 station_index; | |
616 | u8 reserved; | |
617 | } __attribute__ ((packed)); | |
618 | ||
619 | struct notif_link_deterioration { | |
620 | struct ipw_cmd_stats stats; | |
621 | u8 rate; | |
622 | u8 modulation; | |
623 | struct rate_histogram histogram; | |
624 | u8 reserved1; | |
625 | u16 reserved2; | |
626 | } __attribute__ ((packed)); | |
627 | ||
628 | struct notif_association { | |
629 | u8 state; | |
630 | } __attribute__ ((packed)); | |
631 | ||
632 | struct notif_authenticate { | |
633 | u8 state; | |
634 | struct machdr24 addr; | |
635 | u16 status; | |
636 | } __attribute__ ((packed)); | |
637 | ||
43f66a6c JK |
638 | struct notif_calibration { |
639 | u8 data[104]; | |
640 | } __attribute__ ((packed)); | |
641 | ||
642 | struct notif_noise { | |
643 | u32 value; | |
644 | } __attribute__ ((packed)); | |
645 | ||
646 | struct ipw_rx_notification { | |
647 | u8 reserved[8]; | |
648 | u8 subtype; | |
649 | u8 flags; | |
650 | u16 size; | |
651 | union { | |
652 | struct notif_association assoc; | |
653 | struct notif_authenticate auth; | |
654 | struct notif_channel_result channel_result; | |
655 | struct notif_scan_complete scan_complete; | |
656 | struct notif_frag_length frag_len; | |
657 | struct notif_beacon_state beacon_state; | |
658 | struct notif_tgi_tx_key tgi_tx_key; | |
659 | struct notif_link_deterioration link_deterioration; | |
660 | struct notif_calibration calibration; | |
661 | struct notif_noise noise; | |
662 | u8 raw[0]; | |
663 | } u; | |
664 | } __attribute__ ((packed)); | |
665 | ||
666 | struct ipw_rx_frame { | |
bf79451e | 667 | u32 reserved1; |
0edd5b44 JG |
668 | u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER |
669 | u8 received_channel; // The channel that this frame was received on. | |
670 | // Note that for .11b this does not have to be | |
671 | // the same as the channel that it was sent. | |
672 | // Filled by LMAC | |
43f66a6c JK |
673 | u8 frameStatus; |
674 | u8 rate; | |
675 | u8 rssi; | |
676 | u8 agc; | |
677 | u8 rssi_dbm; | |
678 | u16 signal; | |
679 | u16 noise; | |
680 | u8 antennaAndPhy; | |
0edd5b44 JG |
681 | u8 control; // control bit should be on in bg |
682 | u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate | |
683 | // is identical) | |
684 | u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen | |
43f66a6c JK |
685 | u16 length; |
686 | u8 data[0]; | |
687 | } __attribute__ ((packed)); | |
bf79451e | 688 | |
43f66a6c JK |
689 | struct ipw_rx_header { |
690 | u8 message_type; | |
691 | u8 rx_seq_num; | |
692 | u8 control_bits; | |
693 | u8 reserved; | |
694 | } __attribute__ ((packed)); | |
695 | ||
0edd5b44 | 696 | struct ipw_rx_packet { |
43f66a6c JK |
697 | struct ipw_rx_header header; |
698 | union { | |
699 | struct ipw_rx_frame frame; | |
700 | struct ipw_rx_notification notification; | |
701 | } u; | |
702 | } __attribute__ ((packed)); | |
703 | ||
704 | #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12 | |
afbf30a2 JK |
705 | #define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \ |
706 | sizeof(struct ipw_rx_frame)) | |
43f66a6c JK |
707 | |
708 | struct ipw_rx_mem_buffer { | |
709 | dma_addr_t dma_addr; | |
710 | struct ipw_rx_buffer *rxb; | |
711 | struct sk_buff *skb; | |
712 | struct list_head list; | |
0edd5b44 | 713 | }; /* Not transferred over network, so not __attribute__ ((packed)) */ |
43f66a6c JK |
714 | |
715 | struct ipw_rx_queue { | |
716 | struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; | |
717 | struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
0edd5b44 JG |
718 | u32 processed; /* Internal index to last handled Rx packet */ |
719 | u32 read; /* Shared index to newest available Rx buffer */ | |
720 | u32 write; /* Shared index to oldest written Rx packet */ | |
721 | u32 free_count; /* Number of pre-allocated buffers in rx_free */ | |
43f66a6c | 722 | /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */ |
0edd5b44 JG |
723 | struct list_head rx_free; /* Own an SKBs */ |
724 | struct list_head rx_used; /* No SKB allocated */ | |
43f66a6c | 725 | spinlock_t lock; |
0edd5b44 | 726 | }; /* Not transferred over network, so not __attribute__ ((packed)) */ |
43f66a6c JK |
727 | |
728 | struct alive_command_responce { | |
729 | u8 alive_command; | |
730 | u8 sequence_number; | |
731 | u16 software_revision; | |
732 | u8 device_identifier; | |
733 | u8 reserved1[5]; | |
734 | u16 reserved2; | |
735 | u16 reserved3; | |
736 | u16 clock_settle_time; | |
737 | u16 powerup_settle_time; | |
738 | u16 reserved4; | |
739 | u8 time_stamp[5]; /* month, day, year, hours, minutes */ | |
740 | u8 ucode_valid; | |
741 | } __attribute__ ((packed)); | |
742 | ||
743 | #define IPW_MAX_RATES 12 | |
744 | ||
745 | struct ipw_rates { | |
746 | u8 num_rates; | |
747 | u8 rates[IPW_MAX_RATES]; | |
748 | } __attribute__ ((packed)); | |
749 | ||
0edd5b44 | 750 | struct command_block { |
43f66a6c JK |
751 | unsigned int control; |
752 | u32 source_addr; | |
753 | u32 dest_addr; | |
754 | unsigned int status; | |
755 | } __attribute__ ((packed)); | |
756 | ||
757 | #define CB_NUMBER_OF_ELEMENTS_SMALL 64 | |
0edd5b44 | 758 | struct fw_image_desc { |
43f66a6c JK |
759 | unsigned long last_cb_index; |
760 | unsigned long current_cb_index; | |
761 | struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL]; | |
0edd5b44 | 762 | void *v_addr; |
43f66a6c JK |
763 | unsigned long p_addr; |
764 | unsigned long len; | |
765 | }; | |
766 | ||
0edd5b44 | 767 | struct ipw_sys_config { |
43f66a6c JK |
768 | u8 bt_coexistence; |
769 | u8 reserved1; | |
770 | u8 answer_broadcast_ssid_probe; | |
771 | u8 accept_all_data_frames; | |
772 | u8 accept_non_directed_frames; | |
773 | u8 exclude_unicast_unencrypted; | |
774 | u8 disable_unicast_decryption; | |
775 | u8 exclude_multicast_unencrypted; | |
776 | u8 disable_multicast_decryption; | |
777 | u8 antenna_diversity; | |
778 | u8 pass_crc_to_host; | |
779 | u8 dot11g_auto_detection; | |
780 | u8 enable_cts_to_self; | |
781 | u8 enable_multicast_filtering; | |
782 | u8 bt_coexist_collision_thr; | |
783 | u8 reserved2; | |
784 | u8 accept_all_mgmt_bcpr; | |
785 | u8 accept_all_mgtm_frames; | |
786 | u8 pass_noise_stats_to_host; | |
787 | u8 reserved3; | |
788 | } __attribute__ ((packed)); | |
789 | ||
0edd5b44 | 790 | struct ipw_multicast_addr { |
43f66a6c JK |
791 | u8 num_of_multicast_addresses; |
792 | u8 reserved[3]; | |
793 | u8 mac1[6]; | |
794 | u8 mac2[6]; | |
795 | u8 mac3[6]; | |
796 | u8 mac4[6]; | |
797 | } __attribute__ ((packed)); | |
798 | ||
b095c381 JK |
799 | #define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */ |
800 | #define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */ | |
801 | ||
802 | #define DCW_WEP_KEY_SEC_TYPE_WEP 0x00 | |
803 | #define DCW_WEP_KEY_SEC_TYPE_CCM 0x20 | |
804 | #define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30 | |
805 | ||
806 | #define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */ | |
807 | #define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */ | |
808 | #define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */ | |
809 | #define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */ | |
810 | //#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */ | |
811 | ||
0edd5b44 | 812 | struct ipw_wep_key { |
43f66a6c JK |
813 | u8 cmd_id; |
814 | u8 seq_num; | |
815 | u8 key_index; | |
816 | u8 key_size; | |
817 | u8 key[16]; | |
818 | } __attribute__ ((packed)); | |
819 | ||
0edd5b44 | 820 | struct ipw_tgi_tx_key { |
bf79451e | 821 | u8 key_id; |
43f66a6c JK |
822 | u8 security_type; |
823 | u8 station_index; | |
824 | u8 flags; | |
825 | u8 key[16]; | |
826 | u32 tx_counter[2]; | |
827 | } __attribute__ ((packed)); | |
828 | ||
829 | #define IPW_SCAN_CHANNELS 54 | |
830 | ||
0edd5b44 | 831 | struct ipw_scan_request { |
43f66a6c JK |
832 | u8 scan_type; |
833 | u16 dwell_time; | |
834 | u8 channels_list[IPW_SCAN_CHANNELS]; | |
835 | u8 channels_reserved[3]; | |
836 | } __attribute__ ((packed)); | |
837 | ||
838 | enum { | |
839 | IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0, | |
840 | IPW_SCAN_PASSIVE_FULL_DWELL_SCAN, | |
841 | IPW_SCAN_ACTIVE_DIRECT_SCAN, | |
842 | IPW_SCAN_ACTIVE_BROADCAST_SCAN, | |
843 | IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN, | |
844 | IPW_SCAN_TYPES | |
845 | }; | |
846 | ||
0edd5b44 | 847 | struct ipw_scan_request_ext { |
43f66a6c JK |
848 | u32 full_scan_index; |
849 | u8 channels_list[IPW_SCAN_CHANNELS]; | |
850 | u8 scan_type[IPW_SCAN_CHANNELS / 2]; | |
851 | u8 reserved; | |
852 | u16 dwell_time[IPW_SCAN_TYPES]; | |
853 | } __attribute__ ((packed)); | |
854 | ||
bf79451e | 855 | extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index) |
43f66a6c JK |
856 | { |
857 | if (index % 2) | |
858 | return scan->scan_type[index / 2] & 0x0F; | |
859 | else | |
860 | return (scan->scan_type[index / 2] & 0xF0) >> 4; | |
861 | } | |
862 | ||
bf79451e | 863 | extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan, |
43f66a6c JK |
864 | u8 index, u8 scan_type) |
865 | { | |
bf79451e JG |
866 | if (index % 2) |
867 | scan->scan_type[index / 2] = | |
0edd5b44 | 868 | (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F); |
43f66a6c | 869 | else |
bf79451e | 870 | scan->scan_type[index / 2] = |
0edd5b44 JG |
871 | (scan->scan_type[index / 2] & 0x0F) | |
872 | ((scan_type & 0x0F) << 4); | |
43f66a6c JK |
873 | } |
874 | ||
0edd5b44 | 875 | struct ipw_associate { |
43f66a6c | 876 | u8 channel; |
0edd5b44 | 877 | u8 auth_type:4, auth_key:4; |
43f66a6c JK |
878 | u8 assoc_type; |
879 | u8 reserved; | |
880 | u16 policy_support; | |
881 | u8 preamble_length; | |
882 | u8 ieee_mode; | |
883 | u8 bssid[ETH_ALEN]; | |
884 | u32 assoc_tsf_msw; | |
885 | u32 assoc_tsf_lsw; | |
886 | u16 capability; | |
887 | u16 listen_interval; | |
888 | u16 beacon_interval; | |
889 | u8 dest[ETH_ALEN]; | |
890 | u16 atim_window; | |
891 | u8 smr; | |
892 | u8 reserved1; | |
893 | u16 reserved2; | |
894 | } __attribute__ ((packed)); | |
895 | ||
0edd5b44 | 896 | struct ipw_supported_rates { |
43f66a6c JK |
897 | u8 ieee_mode; |
898 | u8 num_rates; | |
899 | u8 purpose; | |
900 | u8 reserved; | |
901 | u8 supported_rates[IPW_MAX_RATES]; | |
902 | } __attribute__ ((packed)); | |
903 | ||
0edd5b44 | 904 | struct ipw_rts_threshold { |
43f66a6c JK |
905 | u16 rts_threshold; |
906 | u16 reserved; | |
907 | } __attribute__ ((packed)); | |
908 | ||
0edd5b44 | 909 | struct ipw_frag_threshold { |
43f66a6c JK |
910 | u16 frag_threshold; |
911 | u16 reserved; | |
912 | } __attribute__ ((packed)); | |
913 | ||
0edd5b44 | 914 | struct ipw_retry_limit { |
43f66a6c JK |
915 | u8 short_retry_limit; |
916 | u8 long_retry_limit; | |
917 | u16 reserved; | |
918 | } __attribute__ ((packed)); | |
919 | ||
0edd5b44 | 920 | struct ipw_dino_config { |
43f66a6c JK |
921 | u32 dino_config_addr; |
922 | u16 dino_config_size; | |
923 | u8 dino_response; | |
924 | u8 reserved; | |
925 | } __attribute__ ((packed)); | |
926 | ||
0edd5b44 | 927 | struct ipw_aironet_info { |
43f66a6c JK |
928 | u8 id; |
929 | u8 length; | |
930 | u16 reserved; | |
931 | } __attribute__ ((packed)); | |
932 | ||
0edd5b44 | 933 | struct ipw_rx_key { |
43f66a6c JK |
934 | u8 station_index; |
935 | u8 key_type; | |
936 | u8 key_id; | |
937 | u8 key_flag; | |
938 | u8 key[16]; | |
939 | u8 station_address[6]; | |
940 | u8 key_index; | |
941 | u8 reserved; | |
942 | } __attribute__ ((packed)); | |
943 | ||
0edd5b44 | 944 | struct ipw_country_channel_info { |
43f66a6c JK |
945 | u8 first_channel; |
946 | u8 no_channels; | |
947 | s8 max_tx_power; | |
948 | } __attribute__ ((packed)); | |
949 | ||
0edd5b44 | 950 | struct ipw_country_info { |
43f66a6c JK |
951 | u8 id; |
952 | u8 length; | |
953 | u8 country_str[3]; | |
954 | struct ipw_country_channel_info groups[7]; | |
955 | } __attribute__ ((packed)); | |
956 | ||
0edd5b44 | 957 | struct ipw_channel_tx_power { |
43f66a6c JK |
958 | u8 channel_number; |
959 | s8 tx_power; | |
960 | } __attribute__ ((packed)); | |
961 | ||
962 | #define SCAN_ASSOCIATED_INTERVAL (HZ) | |
963 | #define SCAN_INTERVAL (HZ / 10) | |
964 | #define MAX_A_CHANNELS 37 | |
965 | #define MAX_B_CHANNELS 14 | |
966 | ||
0edd5b44 | 967 | struct ipw_tx_power { |
43f66a6c JK |
968 | u8 num_channels; |
969 | u8 ieee_mode; | |
970 | struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS]; | |
971 | } __attribute__ ((packed)); | |
972 | ||
0edd5b44 | 973 | struct ipw_rsn_capabilities { |
43f66a6c JK |
974 | u8 id; |
975 | u8 length; | |
976 | u16 version; | |
977 | } __attribute__ ((packed)); | |
978 | ||
0edd5b44 | 979 | struct ipw_sensitivity_calib { |
43f66a6c JK |
980 | u16 beacon_rssi_raw; |
981 | u16 reserved; | |
982 | } __attribute__ ((packed)); | |
983 | ||
984 | /** | |
985 | * Host command structure. | |
bf79451e | 986 | * |
43f66a6c JK |
987 | * On input, the following fields should be filled: |
988 | * - cmd | |
989 | * - len | |
990 | * - status_len | |
991 | * - param (if needed) | |
bf79451e JG |
992 | * |
993 | * On output, | |
43f66a6c JK |
994 | * - \a status contains status; |
995 | * - \a param filled with status parameters. | |
996 | */ | |
997 | struct ipw_cmd { | |
0edd5b44 JG |
998 | u32 cmd; /**< Host command */ |
999 | u32 status;/**< Status */ | |
1000 | u32 status_len; | |
1001 | /**< How many 32 bit parameters in the status */ | |
1002 | u32 len; /**< incoming parameters length, bytes */ | |
43f66a6c | 1003 | /** |
bf79451e JG |
1004 | * command parameters. |
1005 | * There should be enough space for incoming and | |
43f66a6c JK |
1006 | * outcoming parameters. |
1007 | * Incoming parameters listed 1-st, followed by outcoming params. | |
1008 | * nParams=(len+3)/4+status_len | |
1009 | */ | |
0edd5b44 | 1010 | u32 param[0]; |
43f66a6c JK |
1011 | } __attribute__ ((packed)); |
1012 | ||
0edd5b44 | 1013 | #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */ |
43f66a6c JK |
1014 | |
1015 | #define STATUS_INT_ENABLED (1<<1) | |
1016 | #define STATUS_RF_KILL_HW (1<<2) | |
1017 | #define STATUS_RF_KILL_SW (1<<3) | |
1018 | #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW) | |
1019 | ||
1020 | #define STATUS_INIT (1<<5) | |
1021 | #define STATUS_AUTH (1<<6) | |
1022 | #define STATUS_ASSOCIATED (1<<7) | |
1023 | #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED) | |
1024 | ||
1025 | #define STATUS_ASSOCIATING (1<<8) | |
1026 | #define STATUS_DISASSOCIATING (1<<9) | |
1027 | #define STATUS_ROAMING (1<<10) | |
1028 | #define STATUS_EXIT_PENDING (1<<11) | |
1029 | #define STATUS_DISASSOC_PENDING (1<<12) | |
1030 | #define STATUS_STATE_PENDING (1<<13) | |
1031 | ||
1032 | #define STATUS_SCAN_PENDING (1<<20) | |
bf79451e JG |
1033 | #define STATUS_SCANNING (1<<21) |
1034 | #define STATUS_SCAN_ABORTING (1<<22) | |
afbf30a2 | 1035 | #define STATUS_SCAN_FORCED (1<<23) |
43f66a6c | 1036 | |
a613bffd JK |
1037 | #define STATUS_LED_LINK_ON (1<<24) |
1038 | #define STATUS_LED_ACT_ON (1<<25) | |
43f66a6c | 1039 | |
0edd5b44 JG |
1040 | #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */ |
1041 | #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */ | |
1042 | #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */ | |
43f66a6c | 1043 | |
0edd5b44 | 1044 | #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */ |
43f66a6c | 1045 | |
0edd5b44 JG |
1046 | #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */ |
1047 | #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */ | |
1048 | #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */ | |
43f66a6c | 1049 | #define CFG_CUSTOM_MAC (1<<3) |
ea2b26e0 | 1050 | #define CFG_PREAMBLE_LONG (1<<4) |
43f66a6c JK |
1051 | #define CFG_ADHOC_PERSIST (1<<5) |
1052 | #define CFG_ASSOCIATE (1<<6) | |
1053 | #define CFG_FIXED_RATE (1<<7) | |
1054 | #define CFG_ADHOC_CREATE (1<<8) | |
a613bffd JK |
1055 | #define CFG_NO_LED (1<<9) |
1056 | #define CFG_BACKGROUND_SCAN (1<<10) | |
b095c381 JK |
1057 | #define CFG_SPEED_SCAN (1<<11) |
1058 | #define CFG_NET_STATS (1<<12) | |
43f66a6c | 1059 | |
0edd5b44 JG |
1060 | #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */ |
1061 | #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */ | |
43f66a6c JK |
1062 | |
1063 | #define MAX_STATIONS 32 | |
1064 | #define IPW_INVALID_STATION (0xff) | |
1065 | ||
1066 | struct ipw_station_entry { | |
1067 | u8 mac_addr[ETH_ALEN]; | |
1068 | u8 reserved; | |
1069 | u8 support_mode; | |
1070 | }; | |
1071 | ||
1072 | #define AVG_ENTRIES 8 | |
1073 | struct average { | |
1074 | s16 entries[AVG_ENTRIES]; | |
1075 | u8 pos; | |
1076 | u8 init; | |
1077 | s32 sum; | |
1078 | }; | |
1079 | ||
b095c381 | 1080 | #define MAX_SPEED_SCAN 100 |
afbf30a2 JK |
1081 | #define IPW_IBSS_MAC_HASH_SIZE 31 |
1082 | ||
1083 | struct ipw_ibss_seq { | |
1084 | u8 mac[ETH_ALEN]; | |
1085 | u16 seq_num; | |
1086 | u16 frag_num; | |
1087 | unsigned long packet_time; | |
1088 | struct list_head list; | |
1089 | }; | |
b095c381 | 1090 | |
b39860c6 JK |
1091 | struct ipw_error_elem { |
1092 | u32 desc; | |
1093 | u32 time; | |
1094 | u32 blink1; | |
1095 | u32 blink2; | |
1096 | u32 link1; | |
1097 | u32 link2; | |
1098 | u32 data; | |
1099 | }; | |
1100 | ||
1101 | struct ipw_event { | |
1102 | u32 event; | |
1103 | u32 time; | |
1104 | u32 data; | |
1105 | } __attribute__ ((packed)); | |
1106 | ||
1107 | struct ipw_fw_error { | |
f6c5cb7c | 1108 | unsigned long jiffies; |
b39860c6 JK |
1109 | u32 status; |
1110 | u32 config; | |
1111 | u32 elem_len; | |
1112 | u32 log_len; | |
1113 | struct ipw_error_elem *elem; | |
1114 | struct ipw_event *log; | |
1115 | u8 payload[0]; | |
1116 | } __attribute__ ((packed)); | |
1117 | ||
43f66a6c JK |
1118 | struct ipw_priv { |
1119 | /* ieee device used by generic ieee processing code */ | |
1120 | struct ieee80211_device *ieee; | |
43f66a6c | 1121 | |
43f66a6c | 1122 | spinlock_t lock; |
c848d0af | 1123 | struct semaphore sem; |
43f66a6c JK |
1124 | |
1125 | /* basic pci-network driver stuff */ | |
1126 | struct pci_dev *pci_dev; | |
1127 | struct net_device *net_dev; | |
1128 | ||
1129 | /* pci hardware address support */ | |
1130 | void __iomem *hw_base; | |
1131 | unsigned long hw_len; | |
bf79451e | 1132 | |
43f66a6c JK |
1133 | struct fw_image_desc sram_desc; |
1134 | ||
1135 | /* result of ucode download */ | |
1136 | struct alive_command_responce dino_alive; | |
1137 | ||
0edd5b44 JG |
1138 | wait_queue_head_t wait_command_queue; |
1139 | wait_queue_head_t wait_state; | |
43f66a6c JK |
1140 | |
1141 | /* Rx and Tx DMA processing queues */ | |
1142 | struct ipw_rx_queue *rxq; | |
1143 | struct clx2_tx_queue txq_cmd; | |
1144 | struct clx2_tx_queue txq[4]; | |
1145 | u32 status; | |
1146 | u32 config; | |
1147 | u32 capability; | |
1148 | ||
1149 | u8 last_rx_rssi; | |
1150 | u8 last_noise; | |
1151 | struct average average_missed_beacons; | |
1152 | struct average average_rssi; | |
1153 | struct average average_noise; | |
1154 | u32 port_type; | |
0edd5b44 JG |
1155 | int rx_bufs_min; /**< minimum number of bufs in Rx queue */ |
1156 | int rx_pend_max; /**< maximum pending buffers for one IRQ */ | |
1157 | u32 hcmd_seq; /**< sequence number for hcmd */ | |
afbf30a2 | 1158 | u32 disassociate_threshold; |
bf79451e | 1159 | u32 roaming_threshold; |
43f66a6c JK |
1160 | |
1161 | struct ipw_associate assoc_request; | |
1162 | struct ieee80211_network *assoc_network; | |
1163 | ||
1164 | unsigned long ts_scan_abort; | |
1165 | struct ipw_supported_rates rates; | |
0edd5b44 JG |
1166 | struct ipw_rates phy[3]; /**< PHY restrictions, per band */ |
1167 | struct ipw_rates supp; /**< software defined */ | |
1168 | struct ipw_rates extended; /**< use for corresp. IE, AP only */ | |
43f66a6c JK |
1169 | |
1170 | struct notif_link_deterioration last_link_deterioration; /** for statistics */ | |
0edd5b44 | 1171 | struct ipw_cmd *hcmd; /**< host command currently executed */ |
43f66a6c JK |
1172 | |
1173 | wait_queue_head_t hcmd_wq; /**< host command waits for execution */ | |
0edd5b44 | 1174 | u32 tsf_bcn[2]; /**< TSF from latest beacon */ |
43f66a6c | 1175 | |
0edd5b44 | 1176 | struct notif_calibration calib; /**< last calibration */ |
43f66a6c JK |
1177 | |
1178 | /* ordinal interface with firmware */ | |
1179 | u32 table0_addr; | |
1180 | u32 table0_len; | |
1181 | u32 table1_addr; | |
1182 | u32 table1_len; | |
1183 | u32 table2_addr; | |
1184 | u32 table2_len; | |
1185 | ||
1186 | /* context information */ | |
1187 | u8 essid[IW_ESSID_MAX_SIZE]; | |
1188 | u8 essid_len; | |
1189 | u8 nick[IW_ESSID_MAX_SIZE]; | |
1190 | u16 rates_mask; | |
1191 | u8 channel; | |
1192 | struct ipw_sys_config sys_config; | |
1193 | u32 power_mode; | |
bf79451e | 1194 | u8 bssid[ETH_ALEN]; |
43f66a6c JK |
1195 | u16 rts_threshold; |
1196 | u8 mac_addr[ETH_ALEN]; | |
1197 | u8 num_stations; | |
bf79451e | 1198 | u8 stations[MAX_STATIONS][ETH_ALEN]; |
afbf30a2 JK |
1199 | u8 short_retry_limit; |
1200 | u8 long_retry_limit; | |
43f66a6c JK |
1201 | |
1202 | u32 notif_missed_beacons; | |
1203 | ||
1204 | /* Statistics and counters normalized with each association */ | |
1205 | u32 last_missed_beacons; | |
1206 | u32 last_tx_packets; | |
1207 | u32 last_rx_packets; | |
1208 | u32 last_tx_failures; | |
1209 | u32 last_rx_err; | |
1210 | u32 last_rate; | |
1211 | ||
1212 | u32 missed_adhoc_beacons; | |
1213 | u32 missed_beacons; | |
1214 | u32 rx_packets; | |
1215 | u32 tx_packets; | |
1216 | u32 quality; | |
1217 | ||
b095c381 JK |
1218 | u8 speed_scan[MAX_SPEED_SCAN]; |
1219 | u8 speed_scan_pos; | |
1220 | ||
afbf30a2 JK |
1221 | u16 last_seq_num; |
1222 | u16 last_frag_num; | |
1223 | unsigned long last_packet_time; | |
1224 | struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE]; | |
1225 | ||
0edd5b44 JG |
1226 | /* eeprom */ |
1227 | u8 eeprom[0x100]; /* 256 bytes of eeprom */ | |
afbf30a2 | 1228 | u8 country[4]; |
43f66a6c JK |
1229 | int eeprom_delay; |
1230 | ||
bf79451e | 1231 | struct iw_statistics wstats; |
43f66a6c | 1232 | |
97a78ca9 BB |
1233 | struct iw_public_data wireless_data; |
1234 | ||
43f66a6c | 1235 | struct workqueue_struct *workqueue; |
bf79451e | 1236 | |
43f66a6c JK |
1237 | struct work_struct adhoc_check; |
1238 | struct work_struct associate; | |
1239 | struct work_struct disassociate; | |
d8bad6df | 1240 | struct work_struct system_config; |
43f66a6c JK |
1241 | struct work_struct rx_replenish; |
1242 | struct work_struct request_scan; | |
1243 | struct work_struct adapter_restart; | |
1244 | struct work_struct rf_kill; | |
1245 | struct work_struct up; | |
1246 | struct work_struct down; | |
1247 | struct work_struct gather_stats; | |
1248 | struct work_struct abort_scan; | |
1249 | struct work_struct roam; | |
1250 | struct work_struct scan_check; | |
a613bffd JK |
1251 | struct work_struct link_up; |
1252 | struct work_struct link_down; | |
43f66a6c JK |
1253 | |
1254 | struct tasklet_struct irq_tasklet; | |
1255 | ||
a613bffd JK |
1256 | /* LED related variables and work_struct */ |
1257 | u8 nic_type; | |
1258 | u32 led_activity_on; | |
1259 | u32 led_activity_off; | |
1260 | u32 led_association_on; | |
1261 | u32 led_association_off; | |
1262 | u32 led_ofdm_on; | |
1263 | u32 led_ofdm_off; | |
1264 | ||
1265 | struct work_struct led_link_on; | |
1266 | struct work_struct led_link_off; | |
1267 | struct work_struct led_act_off; | |
c848d0af | 1268 | struct work_struct merge_networks; |
a613bffd | 1269 | |
f6c5cb7c JK |
1270 | struct ipw_cmd_log *cmdlog; |
1271 | int cmdlog_len; | |
1272 | int cmdlog_pos; | |
1273 | ||
43f66a6c JK |
1274 | #define IPW_2200BG 1 |
1275 | #define IPW_2915ABG 2 | |
1276 | u8 adapter; | |
1277 | ||
b095c381 | 1278 | s8 tx_power; |
43f66a6c | 1279 | |
bf79451e | 1280 | #ifdef CONFIG_PM |
43f66a6c JK |
1281 | u32 pm_state[16]; |
1282 | #endif | |
1283 | ||
b39860c6 JK |
1284 | struct ipw_fw_error *error; |
1285 | ||
43f66a6c JK |
1286 | /* network state */ |
1287 | ||
1288 | /* Used to pass the current INTA value from ISR to Tasklet */ | |
1289 | u32 isr_inta; | |
1290 | ||
b095c381 JK |
1291 | /* QoS */ |
1292 | struct ipw_qos_info qos_data; | |
1293 | struct work_struct qos_activate; | |
1294 | /*********************************/ | |
1295 | ||
43f66a6c JK |
1296 | /* debugging info */ |
1297 | u32 indirect_dword; | |
1298 | u32 direct_dword; | |
1299 | u32 indirect_byte; | |
1300 | }; /*ipw_priv */ | |
1301 | ||
43f66a6c JK |
1302 | /* debug macros */ |
1303 | ||
0f52bf90 | 1304 | #ifdef CONFIG_IPW2200_DEBUG |
43f66a6c JK |
1305 | #define IPW_DEBUG(level, fmt, args...) \ |
1306 | do { if (ipw_debug_level & (level)) \ | |
1307 | printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \ | |
1308 | in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0) | |
1309 | #else | |
1310 | #define IPW_DEBUG(level, fmt, args...) do {} while (0) | |
0f52bf90 | 1311 | #endif /* CONFIG_IPW2200_DEBUG */ |
43f66a6c JK |
1312 | |
1313 | /* | |
1314 | * To use the debug system; | |
1315 | * | |
1316 | * If you are defining a new debug classification, simply add it to the #define | |
1317 | * list here in the form of: | |
1318 | * | |
1319 | * #define IPW_DL_xxxx VALUE | |
bf79451e | 1320 | * |
43f66a6c JK |
1321 | * shifting value to the left one bit from the previous entry. xxxx should be |
1322 | * the name of the classification (for example, WEP) | |
1323 | * | |
1324 | * You then need to either add a IPW_xxxx_DEBUG() macro definition for your | |
1325 | * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want | |
1326 | * to send output to that classification. | |
1327 | * | |
1328 | * To add your debug level to the list of levels seen when you perform | |
1329 | * | |
1330 | * % cat /proc/net/ipw/debug_level | |
1331 | * | |
1332 | * you simply need to add your entry to the ipw_debug_levels array. | |
1333 | * | |
bf79451e | 1334 | * If you do not see debug_level in /proc/net/ipw then you do not have |
0f52bf90 | 1335 | * CONFIG_IPW2200_DEBUG defined in your kernel configuration |
43f66a6c JK |
1336 | * |
1337 | */ | |
1338 | ||
1339 | #define IPW_DL_ERROR (1<<0) | |
1340 | #define IPW_DL_WARNING (1<<1) | |
1341 | #define IPW_DL_INFO (1<<2) | |
1342 | #define IPW_DL_WX (1<<3) | |
1343 | #define IPW_DL_HOST_COMMAND (1<<5) | |
1344 | #define IPW_DL_STATE (1<<6) | |
1345 | ||
1346 | #define IPW_DL_NOTIF (1<<10) | |
1347 | #define IPW_DL_SCAN (1<<11) | |
1348 | #define IPW_DL_ASSOC (1<<12) | |
1349 | #define IPW_DL_DROP (1<<13) | |
1350 | #define IPW_DL_IOCTL (1<<14) | |
1351 | ||
1352 | #define IPW_DL_MANAGE (1<<15) | |
1353 | #define IPW_DL_FW (1<<16) | |
1354 | #define IPW_DL_RF_KILL (1<<17) | |
1355 | #define IPW_DL_FW_ERRORS (1<<18) | |
1356 | ||
a613bffd JK |
1357 | #define IPW_DL_LED (1<<19) |
1358 | ||
43f66a6c JK |
1359 | #define IPW_DL_ORD (1<<20) |
1360 | ||
1361 | #define IPW_DL_FRAG (1<<21) | |
1362 | #define IPW_DL_WEP (1<<22) | |
1363 | #define IPW_DL_TX (1<<23) | |
1364 | #define IPW_DL_RX (1<<24) | |
1365 | #define IPW_DL_ISR (1<<25) | |
1366 | #define IPW_DL_FW_INFO (1<<26) | |
1367 | #define IPW_DL_IO (1<<27) | |
1368 | #define IPW_DL_TRACE (1<<28) | |
1369 | ||
1370 | #define IPW_DL_STATS (1<<29) | |
c848d0af | 1371 | #define IPW_DL_MERGE (1<<30) |
b095c381 | 1372 | #define IPW_DL_QOS (1<<31) |
43f66a6c | 1373 | |
43f66a6c JK |
1374 | #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a) |
1375 | #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a) | |
1376 | #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a) | |
1377 | ||
1378 | #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a) | |
1379 | #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a) | |
1380 | #define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a) | |
1381 | #define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a) | |
1382 | #define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a) | |
1383 | #define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a) | |
1384 | #define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a) | |
1385 | #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a) | |
a613bffd | 1386 | #define IPW_DEBUG_LED(f, a...) IPW_DEBUG(IPW_DL_LED, f, ## a) |
43f66a6c JK |
1387 | #define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a) |
1388 | #define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a) | |
1389 | #define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a) | |
1390 | #define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a) | |
1391 | #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a) | |
1392 | #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a) | |
1393 | #define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a) | |
1394 | #define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a) | |
1395 | #define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a) | |
1396 | #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a) | |
1397 | #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a) | |
1398 | #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a) | |
1399 | #define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a) | |
c848d0af | 1400 | #define IPW_DEBUG_MERGE(f, a...) IPW_DEBUG(IPW_DL_MERGE, f, ## a) |
b095c381 | 1401 | #define IPW_DEBUG_QOS(f, a...) IPW_DEBUG(IPW_DL_QOS, f, ## a) |
43f66a6c JK |
1402 | |
1403 | #include <linux/ctype.h> | |
1404 | ||
1405 | /* | |
1406 | * Register bit definitions | |
1407 | */ | |
1408 | ||
1409 | /* Dino control registers bits */ | |
1410 | ||
1411 | #define DINO_ENABLE_SYSTEM 0x80 | |
1412 | #define DINO_ENABLE_CS 0x40 | |
bf79451e | 1413 | #define DINO_RXFIFO_DATA 0x01 |
43f66a6c JK |
1414 | #define DINO_CONTROL_REG 0x00200000 |
1415 | ||
b095c381 JK |
1416 | #define IPW_INTA_RW 0x00000008 |
1417 | #define IPW_INTA_MASK_R 0x0000000C | |
1418 | #define IPW_INDIRECT_ADDR 0x00000010 | |
1419 | #define IPW_INDIRECT_DATA 0x00000014 | |
1420 | #define IPW_AUTOINC_ADDR 0x00000018 | |
1421 | #define IPW_AUTOINC_DATA 0x0000001C | |
1422 | #define IPW_RESET_REG 0x00000020 | |
1423 | #define IPW_GP_CNTRL_RW 0x00000024 | |
43f66a6c | 1424 | |
b095c381 | 1425 | #define IPW_READ_INT_REGISTER 0xFF4 |
43f66a6c | 1426 | |
b095c381 | 1427 | #define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004 |
43f66a6c | 1428 | |
b095c381 JK |
1429 | #define IPW_REGISTER_DOMAIN1_END 0x00001000 |
1430 | #define IPW_SRAM_READ_INT_REGISTER 0x00000ff4 | |
43f66a6c | 1431 | |
b095c381 JK |
1432 | #define IPW_SHARED_LOWER_BOUND 0x00000200 |
1433 | #define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80 | |
43f66a6c | 1434 | |
b095c381 JK |
1435 | #define IPW_NIC_SRAM_LOWER_BOUND 0x00000000 |
1436 | #define IPW_NIC_SRAM_UPPER_BOUND 0x00030000 | |
43f66a6c | 1437 | |
b095c381 JK |
1438 | #define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29) |
1439 | #define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001 | |
1440 | #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002 | |
43f66a6c JK |
1441 | |
1442 | /* | |
1443 | * RESET Register Bit Indexes | |
1444 | */ | |
ea2b26e0 | 1445 | #define CBD_RESET_REG_PRINCETON_RESET (1<<0) |
b095c381 JK |
1446 | #define IPW_START_STANDBY (1<<2) |
1447 | #define IPW_ACTIVITY_LED (1<<4) | |
1448 | #define IPW_ASSOCIATED_LED (1<<5) | |
1449 | #define IPW_OFDM_LED (1<<6) | |
1450 | #define IPW_RESET_REG_SW_RESET (1<<7) | |
1451 | #define IPW_RESET_REG_MASTER_DISABLED (1<<8) | |
1452 | #define IPW_RESET_REG_STOP_MASTER (1<<9) | |
1453 | #define IPW_GATE_ODMA (1<<25) | |
1454 | #define IPW_GATE_IDMA (1<<26) | |
1455 | #define IPW_ARC_KESHET_CONFIG (1<<27) | |
1456 | #define IPW_GATE_ADMA (1<<29) | |
1457 | ||
1458 | #define IPW_CSR_CIS_UPPER_BOUND 0x00000200 | |
1459 | #define IPW_DOMAIN_0_END 0x1000 | |
43f66a6c JK |
1460 | #define CLX_MEM_BAR_SIZE 0x1000 |
1461 | ||
b095c381 JK |
1462 | #define IPW_BASEBAND_CONTROL_STATUS 0X00200000 |
1463 | #define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004 | |
1464 | #define IPW_BASEBAND_RX_FIFO_READ 0X00200004 | |
1465 | #define IPW_BASEBAND_CONTROL_STORE 0X00200010 | |
43f66a6c | 1466 | |
b095c381 JK |
1467 | #define IPW_INTERNAL_CMD_EVENT 0X00300004 |
1468 | #define IPW_BASEBAND_POWER_DOWN 0x00000001 | |
43f66a6c | 1469 | |
b095c381 | 1470 | #define IPW_MEM_HALT_AND_RESET 0x003000e0 |
43f66a6c JK |
1471 | |
1472 | /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */ | |
b095c381 JK |
1473 | #define IPW_BIT_HALT_RESET_ON 0x80000000 |
1474 | #define IPW_BIT_HALT_RESET_OFF 0x00000000 | |
43f66a6c JK |
1475 | |
1476 | #define CB_LAST_VALID 0x20000000 | |
1477 | #define CB_INT_ENABLED 0x40000000 | |
1478 | #define CB_VALID 0x80000000 | |
1479 | #define CB_SRC_LE 0x08000000 | |
1480 | #define CB_DEST_LE 0x04000000 | |
1481 | #define CB_SRC_AUTOINC 0x00800000 | |
1482 | #define CB_SRC_IO_GATED 0x00400000 | |
1483 | #define CB_DEST_AUTOINC 0x00080000 | |
1484 | #define CB_SRC_SIZE_LONG 0x00200000 | |
1485 | #define CB_DEST_SIZE_LONG 0x00020000 | |
1486 | ||
43f66a6c JK |
1487 | /* DMA DEFINES */ |
1488 | ||
1489 | #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000 | |
1490 | #define DMA_CB_STOP_AND_ABORT 0x00000C00 | |
bf79451e | 1491 | #define DMA_CB_START 0x00000100 |
43f66a6c | 1492 | |
b095c381 JK |
1493 | #define IPW_SHARED_SRAM_SIZE 0x00030000 |
1494 | #define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000 | |
43f66a6c JK |
1495 | #define CB_MAX_LENGTH 0x1FFF |
1496 | ||
b095c381 JK |
1497 | #define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18 |
1498 | #define IPW_EEPROM_IMAGE_SIZE 0x100 | |
43f66a6c | 1499 | |
43f66a6c | 1500 | /* DMA defs */ |
b095c381 JK |
1501 | #define IPW_DMA_I_CURRENT_CB 0x003000D0 |
1502 | #define IPW_DMA_O_CURRENT_CB 0x003000D4 | |
1503 | #define IPW_DMA_I_DMA_CONTROL 0x003000A4 | |
1504 | #define IPW_DMA_I_CB_BASE 0x003000A0 | |
1505 | ||
1506 | #define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200 | |
1507 | #define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204 | |
1508 | #define IPW_TX_QUEUE_0_BD_BASE 0x00000208 | |
1509 | #define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C) | |
1510 | #define IPW_TX_QUEUE_1_BD_BASE 0x00000210 | |
1511 | #define IPW_TX_QUEUE_1_BD_SIZE 0x00000214 | |
1512 | #define IPW_TX_QUEUE_2_BD_BASE 0x00000218 | |
1513 | #define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C) | |
1514 | #define IPW_TX_QUEUE_3_BD_BASE 0x00000220 | |
1515 | #define IPW_TX_QUEUE_3_BD_SIZE 0x00000224 | |
1516 | #define IPW_RX_BD_BASE 0x00000240 | |
1517 | #define IPW_RX_BD_SIZE 0x00000244 | |
1518 | #define IPW_RFDS_TABLE_LOWER 0x00000500 | |
1519 | ||
1520 | #define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280 | |
1521 | #define IPW_TX_QUEUE_0_READ_INDEX 0x00000284 | |
1522 | #define IPW_TX_QUEUE_1_READ_INDEX 0x00000288 | |
1523 | #define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C) | |
1524 | #define IPW_TX_QUEUE_3_READ_INDEX 0x00000290 | |
1525 | #define IPW_RX_READ_INDEX (0x000002A0) | |
1526 | ||
1527 | #define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80) | |
1528 | #define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84) | |
1529 | #define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88) | |
1530 | #define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C) | |
1531 | #define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90) | |
1532 | #define IPW_RX_WRITE_INDEX (0x00000FA0) | |
43f66a6c JK |
1533 | |
1534 | /* | |
1535 | * EEPROM Related Definitions | |
1536 | */ | |
1537 | ||
b095c381 JK |
1538 | #define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814) |
1539 | #define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818) | |
1540 | #define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C) | |
1541 | #define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820) | |
1542 | #define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0) | |
43f66a6c | 1543 | |
b095c381 JK |
1544 | #define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C) |
1545 | #define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C) | |
1546 | #define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C) | |
1547 | #define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10) | |
1548 | #define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14) | |
1549 | #define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18) | |
43f66a6c | 1550 | |
43f66a6c JK |
1551 | #define MSB 1 |
1552 | #define LSB 0 | |
1553 | #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16)) | |
1554 | ||
1555 | #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \ | |
1556 | ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) ) | |
1557 | ||
1558 | /* EEPROM access by BYTE */ | |
0edd5b44 JG |
1559 | #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */ |
1560 | #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */ | |
1561 | #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */ | |
1562 | #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */ | |
1563 | #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */ | |
1564 | #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */ | |
1565 | #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */ | |
1566 | #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */ | |
1567 | #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */ | |
1568 | #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */ | |
43f66a6c JK |
1569 | |
1570 | /* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/ | |
a613bffd JK |
1571 | #define EEPROM_NIC_TYPE_0 0 |
1572 | #define EEPROM_NIC_TYPE_1 1 | |
1573 | #define EEPROM_NIC_TYPE_2 2 | |
1574 | #define EEPROM_NIC_TYPE_3 3 | |
1575 | #define EEPROM_NIC_TYPE_4 4 | |
43f66a6c JK |
1576 | |
1577 | #define FW_MEM_REG_LOWER_BOUND 0x00300000 | |
bf79451e | 1578 | #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40) |
b095c381 | 1579 | #define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04) |
43f66a6c JK |
1580 | #define EEPROM_BIT_SK (1<<0) |
1581 | #define EEPROM_BIT_CS (1<<1) | |
1582 | #define EEPROM_BIT_DI (1<<2) | |
1583 | #define EEPROM_BIT_DO (1<<4) | |
1584 | ||
1585 | #define EEPROM_CMD_READ 0x2 | |
1586 | ||
1587 | /* Interrupts masks */ | |
b095c381 | 1588 | #define IPW_INTA_NONE 0x00000000 |
43f66a6c | 1589 | |
b095c381 JK |
1590 | #define IPW_INTA_BIT_RX_TRANSFER 0x00000002 |
1591 | #define IPW_INTA_BIT_STATUS_CHANGE 0x00000010 | |
1592 | #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020 | |
43f66a6c JK |
1593 | |
1594 | //Inta Bits for CF | |
b095c381 JK |
1595 | #define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800 |
1596 | #define IPW_INTA_BIT_TX_QUEUE_1 0x00001000 | |
1597 | #define IPW_INTA_BIT_TX_QUEUE_2 0x00002000 | |
1598 | #define IPW_INTA_BIT_TX_QUEUE_3 0x00004000 | |
1599 | #define IPW_INTA_BIT_TX_QUEUE_4 0x00008000 | |
43f66a6c | 1600 | |
b095c381 | 1601 | #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000 |
43f66a6c | 1602 | |
b095c381 JK |
1603 | #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000 |
1604 | #define IPW_INTA_BIT_POWER_DOWN 0x00200000 | |
43f66a6c | 1605 | |
b095c381 JK |
1606 | #define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000 |
1607 | #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000 | |
1608 | #define IPW_INTA_BIT_RF_KILL_DONE 0x04000000 | |
1609 | #define IPW_INTA_BIT_FATAL_ERROR 0x40000000 | |
1610 | #define IPW_INTA_BIT_PARITY_ERROR 0x80000000 | |
43f66a6c JK |
1611 | |
1612 | /* Interrupts enabled at init time. */ | |
b095c381 JK |
1613 | #define IPW_INTA_MASK_ALL \ |
1614 | (IPW_INTA_BIT_TX_QUEUE_1 | \ | |
1615 | IPW_INTA_BIT_TX_QUEUE_2 | \ | |
1616 | IPW_INTA_BIT_TX_QUEUE_3 | \ | |
1617 | IPW_INTA_BIT_TX_QUEUE_4 | \ | |
1618 | IPW_INTA_BIT_TX_CMD_QUEUE | \ | |
1619 | IPW_INTA_BIT_RX_TRANSFER | \ | |
1620 | IPW_INTA_BIT_FATAL_ERROR | \ | |
1621 | IPW_INTA_BIT_PARITY_ERROR | \ | |
1622 | IPW_INTA_BIT_STATUS_CHANGE | \ | |
1623 | IPW_INTA_BIT_FW_INITIALIZATION_DONE | \ | |
1624 | IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \ | |
1625 | IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \ | |
1626 | IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \ | |
1627 | IPW_INTA_BIT_POWER_DOWN | \ | |
1628 | IPW_INTA_BIT_RF_KILL_DONE ) | |
43f66a6c JK |
1629 | |
1630 | /* FW event log definitions */ | |
1631 | #define EVENT_ELEM_SIZE (3 * sizeof(u32)) | |
1632 | #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16)) | |
1633 | ||
1634 | /* FW error log definitions */ | |
1635 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1636 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1637 | ||
b095c381 JK |
1638 | /* TX power level (dbm) */ |
1639 | #define IPW_TX_POWER_MIN -12 | |
1640 | #define IPW_TX_POWER_MAX 20 | |
1641 | #define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX | |
1642 | ||
43f66a6c JK |
1643 | enum { |
1644 | IPW_FW_ERROR_OK = 0, | |
1645 | IPW_FW_ERROR_FAIL, | |
1646 | IPW_FW_ERROR_MEMORY_UNDERFLOW, | |
1647 | IPW_FW_ERROR_MEMORY_OVERFLOW, | |
1648 | IPW_FW_ERROR_BAD_PARAM, | |
1649 | IPW_FW_ERROR_BAD_CHECKSUM, | |
1650 | IPW_FW_ERROR_NMI_INTERRUPT, | |
1651 | IPW_FW_ERROR_BAD_DATABASE, | |
1652 | IPW_FW_ERROR_ALLOC_FAIL, | |
1653 | IPW_FW_ERROR_DMA_UNDERRUN, | |
1654 | IPW_FW_ERROR_DMA_STATUS, | |
b095c381 JK |
1655 | IPW_FW_ERROR_DINO_ERROR, |
1656 | IPW_FW_ERROR_EEPROM_ERROR, | |
43f66a6c JK |
1657 | IPW_FW_ERROR_SYSASSERT, |
1658 | IPW_FW_ERROR_FATAL_ERROR | |
1659 | }; | |
1660 | ||
1661 | #define AUTH_OPEN 0 | |
1662 | #define AUTH_SHARED_KEY 1 | |
1663 | #define AUTH_IGNORE 3 | |
1664 | ||
1665 | #define HC_ASSOCIATE 0 | |
1666 | #define HC_REASSOCIATE 1 | |
1667 | #define HC_DISASSOCIATE 2 | |
1668 | #define HC_IBSS_START 3 | |
1669 | #define HC_IBSS_RECONF 4 | |
1670 | #define HC_DISASSOC_QUIET 5 | |
1671 | ||
b095c381 JK |
1672 | #define HC_QOS_SUPPORT_ASSOC 0x01 |
1673 | ||
43f66a6c JK |
1674 | #define IPW_RATE_CAPABILITIES 1 |
1675 | #define IPW_RATE_CONNECT 0 | |
1676 | ||
bf79451e JG |
1677 | /* |
1678 | * Rate values and masks | |
43f66a6c JK |
1679 | */ |
1680 | #define IPW_TX_RATE_1MB 0x0A | |
1681 | #define IPW_TX_RATE_2MB 0x14 | |
1682 | #define IPW_TX_RATE_5MB 0x37 | |
1683 | #define IPW_TX_RATE_6MB 0x0D | |
1684 | #define IPW_TX_RATE_9MB 0x0F | |
bf79451e | 1685 | #define IPW_TX_RATE_11MB 0x6E |
43f66a6c JK |
1686 | #define IPW_TX_RATE_12MB 0x05 |
1687 | #define IPW_TX_RATE_18MB 0x07 | |
1688 | #define IPW_TX_RATE_24MB 0x09 | |
1689 | #define IPW_TX_RATE_36MB 0x0B | |
1690 | #define IPW_TX_RATE_48MB 0x01 | |
1691 | #define IPW_TX_RATE_54MB 0x03 | |
1692 | ||
1693 | #define IPW_ORD_TABLE_ID_MASK 0x0000FF00 | |
1694 | #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF | |
1695 | ||
bf79451e JG |
1696 | #define IPW_ORD_TABLE_0_MASK 0x0000F000 |
1697 | #define IPW_ORD_TABLE_1_MASK 0x0000F100 | |
1698 | #define IPW_ORD_TABLE_2_MASK 0x0000F200 | |
1699 | #define IPW_ORD_TABLE_3_MASK 0x0000F300 | |
1700 | #define IPW_ORD_TABLE_4_MASK 0x0000F400 | |
1701 | #define IPW_ORD_TABLE_5_MASK 0x0000F500 | |
1702 | #define IPW_ORD_TABLE_6_MASK 0x0000F600 | |
1703 | #define IPW_ORD_TABLE_7_MASK 0x0000F700 | |
43f66a6c JK |
1704 | |
1705 | /* | |
1706 | * Table 0 Entries (all entries are 32 bits) | |
1707 | */ | |
bf79451e | 1708 | enum { |
43f66a6c JK |
1709 | IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1, |
1710 | IPW_ORD_STAT_FRAG_TRESHOLD, | |
1711 | IPW_ORD_STAT_RTS_THRESHOLD, | |
bf79451e JG |
1712 | IPW_ORD_STAT_TX_HOST_REQUESTS, |
1713 | IPW_ORD_STAT_TX_HOST_COMPLETE, | |
1714 | IPW_ORD_STAT_TX_DIR_DATA, | |
43f66a6c JK |
1715 | IPW_ORD_STAT_TX_DIR_DATA_B_1, |
1716 | IPW_ORD_STAT_TX_DIR_DATA_B_2, | |
1717 | IPW_ORD_STAT_TX_DIR_DATA_B_5_5, | |
1718 | IPW_ORD_STAT_TX_DIR_DATA_B_11, | |
1719 | /* Hole */ | |
1720 | ||
43f66a6c JK |
1721 | IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19, |
1722 | IPW_ORD_STAT_TX_DIR_DATA_G_2, | |
1723 | IPW_ORD_STAT_TX_DIR_DATA_G_5_5, | |
1724 | IPW_ORD_STAT_TX_DIR_DATA_G_6, | |
1725 | IPW_ORD_STAT_TX_DIR_DATA_G_9, | |
bf79451e | 1726 | IPW_ORD_STAT_TX_DIR_DATA_G_11, |
43f66a6c JK |
1727 | IPW_ORD_STAT_TX_DIR_DATA_G_12, |
1728 | IPW_ORD_STAT_TX_DIR_DATA_G_18, | |
1729 | IPW_ORD_STAT_TX_DIR_DATA_G_24, | |
1730 | IPW_ORD_STAT_TX_DIR_DATA_G_36, | |
1731 | IPW_ORD_STAT_TX_DIR_DATA_G_48, | |
1732 | IPW_ORD_STAT_TX_DIR_DATA_G_54, | |
bf79451e | 1733 | IPW_ORD_STAT_TX_NON_DIR_DATA, |
43f66a6c JK |
1734 | IPW_ORD_STAT_TX_NON_DIR_DATA_B_1, |
1735 | IPW_ORD_STAT_TX_NON_DIR_DATA_B_2, | |
1736 | IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5, | |
bf79451e | 1737 | IPW_ORD_STAT_TX_NON_DIR_DATA_B_11, |
43f66a6c JK |
1738 | /* Hole */ |
1739 | ||
43f66a6c JK |
1740 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44, |
1741 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_2, | |
1742 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5, | |
1743 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_6, | |
1744 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_9, | |
bf79451e | 1745 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_11, |
43f66a6c JK |
1746 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_12, |
1747 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_18, | |
1748 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_24, | |
1749 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_36, | |
1750 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_48, | |
1751 | IPW_ORD_STAT_TX_NON_DIR_DATA_G_54, | |
1752 | IPW_ORD_STAT_TX_RETRY, | |
1753 | IPW_ORD_STAT_TX_FAILURE, | |
1754 | IPW_ORD_STAT_RX_ERR_CRC, | |
1755 | IPW_ORD_STAT_RX_ERR_ICV, | |
1756 | IPW_ORD_STAT_RX_NO_BUFFER, | |
1757 | IPW_ORD_STAT_FULL_SCANS, | |
1758 | IPW_ORD_STAT_PARTIAL_SCANS, | |
1759 | IPW_ORD_STAT_TGH_ABORTED_SCANS, | |
bf79451e | 1760 | IPW_ORD_STAT_TX_TOTAL_BYTES, |
43f66a6c JK |
1761 | IPW_ORD_STAT_CURR_RSSI_RAW, |
1762 | IPW_ORD_STAT_RX_BEACON, | |
1763 | IPW_ORD_STAT_MISSED_BEACONS, | |
bf79451e JG |
1764 | IPW_ORD_TABLE_0_LAST |
1765 | }; | |
43f66a6c JK |
1766 | |
1767 | #define IPW_RSSI_TO_DBM 112 | |
1768 | ||
1769 | /* Table 1 Entries | |
1770 | */ | |
1771 | enum { | |
1772 | IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1, | |
1773 | }; | |
1774 | ||
1775 | /* | |
1776 | * Table 2 Entries | |
1777 | * | |
1778 | * FW_VERSION: 16 byte string | |
1779 | * FW_DATE: 16 byte string (only 14 bytes used) | |
1780 | * UCODE_VERSION: 4 byte version code | |
1781 | * UCODE_DATE: 5 bytes code code | |
1782 | * ADDAPTER_MAC: 6 byte MAC address | |
1783 | * RTC: 4 byte clock | |
1784 | */ | |
bf79451e | 1785 | enum { |
43f66a6c | 1786 | IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1, |
bf79451e | 1787 | IPW_ORD_STAT_FW_DATE, |
43f66a6c | 1788 | IPW_ORD_STAT_UCODE_VERSION, |
bf79451e JG |
1789 | IPW_ORD_STAT_UCODE_DATE, |
1790 | IPW_ORD_STAT_ADAPTER_MAC, | |
1791 | IPW_ORD_STAT_RTC, | |
1792 | IPW_ORD_TABLE_2_LAST | |
1793 | }; | |
43f66a6c JK |
1794 | |
1795 | /* Table 3 */ | |
1796 | enum { | |
1797 | IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0, | |
1798 | IPW_ORD_STAT_TX_PACKET_FAILURE, | |
1799 | IPW_ORD_STAT_TX_PACKET_SUCCESS, | |
1800 | IPW_ORD_STAT_TX_PACKET_ABORTED, | |
1801 | IPW_ORD_TABLE_3_LAST | |
1802 | }; | |
1803 | ||
1804 | /* Table 4 */ | |
1805 | enum { | |
1806 | IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK | |
1807 | }; | |
1808 | ||
1809 | /* Table 5 */ | |
1810 | enum { | |
1811 | IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK, | |
1812 | IPW_ORD_STAT_AP_ASSNS, | |
1813 | IPW_ORD_STAT_ROAM, | |
1814 | IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS, | |
1815 | IPW_ORD_STAT_ROAM_CAUSE_UNASSOC, | |
1816 | IPW_ORD_STAT_ROAM_CAUSE_RSSI, | |
1817 | IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY, | |
1818 | IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE, | |
1819 | IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX, | |
1820 | IPW_ORD_STAT_LINK_UP, | |
1821 | IPW_ORD_STAT_LINK_DOWN, | |
1822 | IPW_ORD_ANTENNA_DIVERSITY, | |
1823 | IPW_ORD_CURR_FREQ, | |
1824 | IPW_ORD_TABLE_5_LAST | |
1825 | }; | |
1826 | ||
1827 | /* Table 6 */ | |
1828 | enum { | |
1829 | IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK, | |
1830 | IPW_ORD_CURR_BSSID, | |
1831 | IPW_ORD_CURR_SSID, | |
1832 | IPW_ORD_TABLE_6_LAST | |
1833 | }; | |
1834 | ||
1835 | /* Table 7 */ | |
1836 | enum { | |
1837 | IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK, | |
1838 | IPW_ORD_STAT_PERCENT_TX_RETRIES, | |
1839 | IPW_ORD_STAT_PERCENT_LINK_QUALITY, | |
1840 | IPW_ORD_STAT_CURR_RSSI_DBM, | |
1841 | IPW_ORD_TABLE_7_LAST | |
1842 | }; | |
1843 | ||
b39860c6 | 1844 | #define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410) |
b095c381 JK |
1845 | #define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414) |
1846 | #define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500) | |
1847 | #define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180) | |
1848 | #define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184) | |
1849 | #define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188) | |
1850 | #define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C) | |
43f66a6c JK |
1851 | |
1852 | struct ipw_fixed_rate { | |
1853 | u16 tx_rates; | |
1854 | u16 reserved; | |
1855 | } __attribute__ ((packed)); | |
1856 | ||
b095c381 | 1857 | #define IPW_INDIRECT_ADDR_MASK (~0x3ul) |
43f66a6c JK |
1858 | |
1859 | struct host_cmd { | |
1860 | u8 cmd; | |
1861 | u8 len; | |
1862 | u16 reserved; | |
1863 | u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH]; | |
1864 | } __attribute__ ((packed)); | |
1865 | ||
f6c5cb7c JK |
1866 | struct ipw_cmd_log { |
1867 | unsigned long jiffies; | |
1868 | int retcode; | |
1869 | struct host_cmd cmd; | |
1870 | }; | |
1871 | ||
43f66a6c JK |
1872 | #define CFG_BT_COEXISTENCE_MIN 0x00 |
1873 | #define CFG_BT_COEXISTENCE_DEFER 0x02 | |
1874 | #define CFG_BT_COEXISTENCE_KILL 0x04 | |
1875 | #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 | |
1876 | #define CFG_BT_COEXISTENCE_OOB 0x10 | |
1877 | #define CFG_BT_COEXISTENCE_MAX 0xFF | |
0edd5b44 | 1878 | #define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM */ |
43f66a6c JK |
1879 | |
1880 | #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0 | |
1881 | #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1 | |
1882 | #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN | |
1883 | ||
1884 | #define CFG_SYS_ANTENNA_BOTH 0x000 | |
1885 | #define CFG_SYS_ANTENNA_A 0x001 | |
1886 | #define CFG_SYS_ANTENNA_B 0x003 | |
1887 | ||
1888 | /* | |
bf79451e | 1889 | * The definitions below were lifted off the ipw2100 driver, which only |
43f66a6c | 1890 | * supports 'b' mode, so I'm sure these are not exactly correct. |
bf79451e | 1891 | * |
43f66a6c JK |
1892 | * Somebody fix these!! |
1893 | */ | |
1894 | #define REG_MIN_CHANNEL 0 | |
1895 | #define REG_MAX_CHANNEL 14 | |
1896 | ||
1897 | #define REG_CHANNEL_MASK 0x00003FFF | |
1898 | #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff | |
1899 | ||
43f66a6c JK |
1900 | #define IPW_MAX_CONFIG_RETRIES 10 |
1901 | ||
0dacca1f | 1902 | static inline u32 frame_hdr_len(struct ieee80211_hdr_4addr *hdr) |
43f66a6c JK |
1903 | { |
1904 | u32 retval; | |
1905 | u16 fc; | |
1906 | ||
0dacca1f | 1907 | retval = sizeof(struct ieee80211_hdr_3addr); |
43f66a6c JK |
1908 | fc = le16_to_cpu(hdr->frame_ctl); |
1909 | ||
1910 | /* | |
0edd5b44 JG |
1911 | * Function ToDS FromDS |
1912 | * IBSS 0 0 | |
1913 | * To AP 1 0 | |
1914 | * From AP 0 1 | |
1915 | * WDS (bridge) 1 1 | |
43f66a6c JK |
1916 | * |
1917 | * Only WDS frames use Address4 among them. --YZ | |
1918 | */ | |
1919 | if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS)) | |
1920 | retval -= ETH_ALEN; | |
1921 | ||
1922 | return retval; | |
1923 | } | |
1924 | ||
0edd5b44 | 1925 | #endif /* __ipw2200_h__ */ |