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Merge linux-2.6 into linux-acpi-2.6 test
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ipw2200.h
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43f66a6c 1/******************************************************************************
bf79451e 2
43f66a6c 3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
bf79451e
JG		 4
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
43f66a6c 7 published by the Free Software Foundation.
bf79451e
JG		 8
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
43f66a6c 12 more details.
bf79451e 13
43f66a6c 14 You should have received a copy of the GNU General Public License along with
bf79451e 15 this program; if not, write to the Free Software Foundation, Inc., 59
43f66a6c 16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
bf79451e 17
43f66a6c
JK		 18 The full GNU General Public License is included in this distribution in the
19 file called LICENSE.
bf79451e 20
43f66a6c
JK		 21 Contact Information:
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25******************************************************************************/
26
27#ifndef __ipw2200_h__
28#define __ipw2200_h__
29
30#define WEXT_USECHANNELS 1
31
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/config.h>
35#include <linux/init.h>
36
37#include <linux/version.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/ethtool.h>
41#include <linux/skbuff.h>
42#include <linux/etherdevice.h>
43#include <linux/delay.h>
44#include <linux/random.h>
45
46#include <linux/firmware.h>
47#include <linux/wireless.h>
48#include <asm/io.h>
49
50#include <net/ieee80211.h>
51
52#define DRV_NAME "ipw2200"
53
54#include <linux/workqueue.h>
55
43f66a6c
JK		 56/* Authentication and Association States */
57enum connection_manager_assoc_states
58{
59 CMAS_INIT = 0,
60 CMAS_TX_AUTH_SEQ_1,
61 CMAS_RX_AUTH_SEQ_2,
62 CMAS_AUTH_SEQ_1_PASS,
63 CMAS_AUTH_SEQ_1_FAIL,
64 CMAS_TX_AUTH_SEQ_3,
65 CMAS_RX_AUTH_SEQ_4,
66 CMAS_AUTH_SEQ_2_PASS,
67 CMAS_AUTH_SEQ_2_FAIL,
68 CMAS_AUTHENTICATED,
69 CMAS_TX_ASSOC,
70 CMAS_RX_ASSOC_RESP,
71 CMAS_ASSOCIATED,
72 CMAS_LAST
73};
74
75
43f66a6c
JK		 76#define IPW_WAIT (1<<0)
77#define IPW_QUIET (1<<1)
78#define IPW_ROAMING (1<<2)
79
80#define IPW_POWER_MODE_CAM 0x00 //(always on)
81#define IPW_POWER_INDEX_1 0x01
82#define IPW_POWER_INDEX_2 0x02
83#define IPW_POWER_INDEX_3 0x03
84#define IPW_POWER_INDEX_4 0x04
85#define IPW_POWER_INDEX_5 0x05
86#define IPW_POWER_AC 0x06
87#define IPW_POWER_BATTERY 0x07
88#define IPW_POWER_LIMIT 0x07
89#define IPW_POWER_MASK 0x0F
90#define IPW_POWER_ENABLED 0x10
91#define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
92
93#define IPW_CMD_HOST_COMPLETE 2
94#define IPW_CMD_POWER_DOWN 4
95#define IPW_CMD_SYSTEM_CONFIG 6
96#define IPW_CMD_MULTICAST_ADDRESS 7
97#define IPW_CMD_SSID 8
98#define IPW_CMD_ADAPTER_ADDRESS 11
99#define IPW_CMD_PORT_TYPE 12
100#define IPW_CMD_RTS_THRESHOLD 15
101#define IPW_CMD_FRAG_THRESHOLD 16
102#define IPW_CMD_POWER_MODE 17
103#define IPW_CMD_WEP_KEY 18
104#define IPW_CMD_TGI_TX_KEY 19
105#define IPW_CMD_SCAN_REQUEST 20
106#define IPW_CMD_ASSOCIATE 21
107#define IPW_CMD_SUPPORTED_RATES 22
108#define IPW_CMD_SCAN_ABORT 23
109#define IPW_CMD_TX_FLUSH 24
110#define IPW_CMD_QOS_PARAMETERS 25
111#define IPW_CMD_SCAN_REQUEST_EXT 26
112#define IPW_CMD_DINO_CONFIG 30
113#define IPW_CMD_RSN_CAPABILITIES 31
114#define IPW_CMD_RX_KEY 32
115#define IPW_CMD_CARD_DISABLE 33
116#define IPW_CMD_SEED_NUMBER 34
117#define IPW_CMD_TX_POWER 35
118#define IPW_CMD_COUNTRY_INFO 36
119#define IPW_CMD_AIRONET_INFO 37
120#define IPW_CMD_AP_TX_POWER 38
121#define IPW_CMD_CCKM_INFO 39
122#define IPW_CMD_CCX_VER_INFO 40
123#define IPW_CMD_SET_CALIBRATION 41
124#define IPW_CMD_SENSITIVITY_CALIB 42
125#define IPW_CMD_RETRY_LIMIT 51
126#define IPW_CMD_IPW_PRE_POWER_DOWN 58
127#define IPW_CMD_VAP_BEACON_TEMPLATE 60
128#define IPW_CMD_VAP_DTIM_PERIOD 61
129#define IPW_CMD_EXT_SUPPORTED_RATES 62
130#define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
131#define IPW_CMD_VAP_QUIET_INTERVALS 64
132#define IPW_CMD_VAP_CHANNEL_SWITCH 65
133#define IPW_CMD_VAP_MANDATORY_CHANNELS 66
134#define IPW_CMD_VAP_CELL_PWR_LIMIT 67
135#define IPW_CMD_VAP_CF_PARAM_SET 68
136#define IPW_CMD_VAP_SET_BEACONING_STATE 69
137#define IPW_CMD_MEASUREMENT 80
138#define IPW_CMD_POWER_CAPABILITY 81
139#define IPW_CMD_SUPPORTED_CHANNELS 82
140#define IPW_CMD_TPC_REPORT 83
141#define IPW_CMD_WME_INFO 84
142#define IPW_CMD_PRODUCTION_COMMAND 85
143#define IPW_CMD_LINKSYS_EOU_INFO 90
144
145#define RFD_SIZE 4
146#define NUM_TFD_CHUNKS 6
147
148#define TX_QUEUE_SIZE 32
149#define RX_QUEUE_SIZE 32
150
151#define DINO_CMD_WEP_KEY 0x08
152#define DINO_CMD_TX 0x0B
153#define DCT_ANTENNA_A 0x01
154#define DCT_ANTENNA_B 0x02
155
156#define IPW_A_MODE 0
157#define IPW_B_MODE 1
158#define IPW_G_MODE 2
159
bf79451e
JG		 160/*
161 * TX Queue Flag Definitions
43f66a6c
JK		 162 */
163
164/* abort attempt if mgmt frame is rx'd */
bf79451e
JG		 165#define DCT_FLAG_ABORT_MGMT 0x01
166
43f66a6c
JK		 167/* require CTS */
168#define DCT_FLAG_CTS_REQUIRED 0x02
169
170/* use short preamble */
bf79451e 171#define DCT_FLAG_SHORT_PREMBL 0x04
43f66a6c
JK		 172
173/* RTS/CTS first */
174#define DCT_FLAG_RTS_REQD 0x08
175
176/* dont calculate duration field */
177#define DCT_FLAG_DUR_SET 0x10
178
179/* even if MAC WEP set (allows pre-encrypt) */
180#define DCT_FLAG_NO_WEP 0x20
8d45ff7d 181
43f66a6c
JK		 182/* overwrite TSF field */
183#define DCT_FLAG_TSF_REQD 0x40
184
185/* ACK rx is expected to follow */
bf79451e 186#define DCT_FLAG_ACK_REQD 0x80
43f66a6c
JK		 187
188#define DCT_FLAG_EXT_MODE_CCK 0x01
189#define DCT_FLAG_EXT_MODE_OFDM 0x00
190
191
192#define TX_RX_TYPE_MASK 0xFF
193#define TX_FRAME_TYPE 0x00
194#define TX_HOST_COMMAND_TYPE 0x01
195#define RX_FRAME_TYPE 0x09
196#define RX_HOST_NOTIFICATION_TYPE 0x03
197#define RX_HOST_CMD_RESPONSE_TYPE 0x04
198#define RX_TX_FRAME_RESPONSE_TYPE 0x05
199#define TFD_NEED_IRQ_MASK 0x04
200
201#define HOST_CMD_DINO_CONFIG 30
202
203#define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
204#define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
205#define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
206#define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
207#define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
208#define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
209#define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
210#define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
211#define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
212#define HOST_NOTIFICATION_TX_STATUS 19
213#define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
214#define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
215#define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
216#define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
217#define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
218#define HOST_NOTIFICATION_NOISE_STATS 25
bf79451e 219#define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
43f66a6c
JK		 220#define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
221
222#define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
223#define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24
224#define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
bf79451e 225#define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
43f66a6c
JK		 226
227#define MACADRR_BYTE_LEN 6
228
229#define DCR_TYPE_AP 0x01
230#define DCR_TYPE_WLAP 0x02
231#define DCR_TYPE_MU_ESS 0x03
232#define DCR_TYPE_MU_IBSS 0x04
233#define DCR_TYPE_MU_PIBSS 0x05
234#define DCR_TYPE_SNIFFER 0x06
235#define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
236
237/**
238 * Generic queue structure
bf79451e 239 *
43f66a6c
JK		 240 * Contains common data for Rx and Tx queues
241 */
242struct clx2_queue {
243 int n_bd; /**< number of BDs in this queue */
244 int first_empty; /**< 1-st empty entry (index) */
245 int last_used; /**< last used entry (index) */
246 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
247 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
248 dma_addr_t dma_addr; /**< physical addr for BD's */
249 int low_mark; /**< low watermark, resume queue if free space more than this */
250 int high_mark; /**< high watermark, stop queue if free space less than this */
251} __attribute__ ((packed));
252
253struct machdr32
254{
255 u16 frame_ctl;
256 u16 duration; // watch out for endians!
257 u8 addr1[ MACADRR_BYTE_LEN ];
258 u8 addr2[ MACADRR_BYTE_LEN ];
259 u8 addr3[ MACADRR_BYTE_LEN ];
260 u16 seq_ctrl; // more endians!
261 u8 addr4[ MACADRR_BYTE_LEN ];
262 u16 qos_ctrl;
263} __attribute__ ((packed)) ;
264
265struct machdr30
266{
267 u16 frame_ctl;
268 u16 duration; // watch out for endians!
269 u8 addr1[ MACADRR_BYTE_LEN ];
270 u8 addr2[ MACADRR_BYTE_LEN ];
271 u8 addr3[ MACADRR_BYTE_LEN ];
272 u16 seq_ctrl; // more endians!
273 u8 addr4[ MACADRR_BYTE_LEN ];
274} __attribute__ ((packed)) ;
275
276struct machdr26
277{
278 u16 frame_ctl;
279 u16 duration; // watch out for endians!
280 u8 addr1[ MACADRR_BYTE_LEN ];
281 u8 addr2[ MACADRR_BYTE_LEN ];
282 u8 addr3[ MACADRR_BYTE_LEN ];
283 u16 seq_ctrl; // more endians!
284 u16 qos_ctrl;
285} __attribute__ ((packed)) ;
286
287struct machdr24
288{
289 u16 frame_ctl;
290 u16 duration; // watch out for endians!
291 u8 addr1[ MACADRR_BYTE_LEN ];
292 u8 addr2[ MACADRR_BYTE_LEN ];
293 u8 addr3[ MACADRR_BYTE_LEN ];
294 u16 seq_ctrl; // more endians!
295} __attribute__ ((packed)) ;
296
297// TX TFD with 32 byte MAC Header
298struct tx_tfd_32
bf79451e 299{
43f66a6c
JK		 300 struct machdr32 mchdr; // 32
301 u32 uivplaceholder[2]; // 8
302} __attribute__ ((packed)) ;
303
304// TX TFD with 30 byte MAC Header
305struct tx_tfd_30
306{
307 struct machdr30 mchdr; // 30
308 u8 reserved[2]; // 2
309 u32 uivplaceholder[2]; // 8
310} __attribute__ ((packed)) ;
311
312// tx tfd with 26 byte mac header
313struct tx_tfd_26
314{
315 struct machdr26 mchdr; // 26
316 u8 reserved1[2]; // 2
317 u32 uivplaceholder[2]; // 8
318 u8 reserved2[4]; // 4
319} __attribute__ ((packed)) ;
320
321// tx tfd with 24 byte mac header
322struct tx_tfd_24
323{
324 struct machdr24 mchdr; // 24
325 u32 uivplaceholder[2]; // 8
326 u8 reserved[8]; // 8
327} __attribute__ ((packed)) ;
328
329
330#define DCT_WEP_KEY_FIELD_LENGTH 16
331
332struct tfd_command
333{
334 u8 index;
335 u8 length;
336 u16 reserved;
337 u8 payload[0];
338} __attribute__ ((packed)) ;
339
340struct tfd_data {
341 /* Header */
342 u32 work_area_ptr;
343 u8 station_number; /* 0 for BSS */
344 u8 reserved1;
345 u16 reserved2;
346
347 /* Tx Parameters */
348 u8 cmd_id;
bf79451e
JG		 349 u8 seq_num;
350 u16 len;
43f66a6c
JK		 351 u8 priority;
352 u8 tx_flags;
353 u8 tx_flags_ext;
354 u8 key_index;
355 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
356 u8 rate;
357 u8 antenna;
358 u16 next_packet_duration;
bf79451e 359 u16 next_frag_len;
43f66a6c
JK		 360 u16 back_off_counter; //////txop;
361 u8 retrylimit;
bf79451e 362 u16 cwcurrent;
43f66a6c
JK		 363 u8 reserved3;
364
365 /* 802.11 MAC Header */
366 union
367 {
368 struct tx_tfd_24 tfd_24;
369 struct tx_tfd_26 tfd_26;
370 struct tx_tfd_30 tfd_30;
371 struct tx_tfd_32 tfd_32;
372 } tfd;
373
374 /* Payload DMA info */
375 u32 num_chunks;
376 u32 chunk_ptr[NUM_TFD_CHUNKS];
377 u16 chunk_len[NUM_TFD_CHUNKS];
378} __attribute__ ((packed));
379
380struct txrx_control_flags
381{
382 u8 message_type;
383 u8 rx_seq_num;
384 u8 control_bits;
385 u8 reserved;
386} __attribute__ ((packed));
387
388#define TFD_SIZE 128
389#define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
390
391struct tfd_frame
392{
393 struct txrx_control_flags control_flags;
394 union {
395 struct tfd_data data;
396 struct tfd_command cmd;
397 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
398 } u;
399} __attribute__ ((packed)) ;
400
401typedef void destructor_func(const void*);
402
403/**
404 * Tx Queue for DMA. Queue consists of circular buffer of
405 * BD's and required locking structures.
406 */
407struct clx2_tx_queue {
408 struct clx2_queue q;
409 struct tfd_frame* bd;
410 struct ieee80211_txb **txb;
411};
412
413/*
414 * RX related structures and functions
415 */
416#define RX_FREE_BUFFERS 32
417#define RX_LOW_WATERMARK 8
418
419#define SUP_RATE_11A_MAX_NUM_CHANNELS (8)
420#define SUP_RATE_11B_MAX_NUM_CHANNELS (4)
421#define SUP_RATE_11G_MAX_NUM_CHANNELS (12)
422
423// Used for passing to driver number of successes and failures per rate
424struct rate_histogram
425{
426 union {
427 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
428 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
429 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
430 } success;
431 union {
432 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
433 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
434 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
435 } failed;
436} __attribute__ ((packed));
437
bf79451e 438/* statistics command response */
43f66a6c
JK		 439struct ipw_cmd_stats {
440 u8 cmd_id;
441 u8 seq_num;
bf79451e
JG		 442 u16 good_sfd;
443 u16 bad_plcp;
444 u16 wrong_bssid;
445 u16 valid_mpdu;
446 u16 bad_mac_header;
447 u16 reserved_frame_types;
448 u16 rx_ina;
449 u16 bad_crc32;
450 u16 invalid_cts;
451 u16 invalid_acks;
452 u16 long_distance_ina_fina;
43f66a6c 453 u16 dsp_silence_unreachable;
bf79451e
JG		 454 u16 accumulated_rssi;
455 u16 rx_ovfl_frame_tossed;
43f66a6c
JK		 456 u16 rssi_silence_threshold;
457 u16 rx_ovfl_frame_supplied;
bf79451e
JG		 458 u16 last_rx_frame_signal;
459 u16 last_rx_frame_noise;
460 u16 rx_autodetec_no_ofdm;
43f66a6c
JK		 461 u16 rx_autodetec_no_barker;
462 u16 reserved;
463} __attribute__ ((packed));
464
465struct notif_channel_result {
466 u8 channel_num;
467 struct ipw_cmd_stats stats;
468 u8 uReserved;
469} __attribute__ ((packed));
470
471struct notif_scan_complete {
472 u8 scan_type;
473 u8 num_channels;
474 u8 status;
475 u8 reserved;
476} __attribute__ ((packed));
477
478struct notif_frag_length {
479 u16 frag_length;
480 u16 reserved;
481} __attribute__ ((packed));
482
483struct notif_beacon_state {
484 u32 state;
485 u32 number;
486} __attribute__ ((packed));
487
488struct notif_tgi_tx_key {
489 u8 key_state;
490 u8 security_type;
491 u8 station_index;
492 u8 reserved;
493} __attribute__ ((packed));
494
495struct notif_link_deterioration {
496 struct ipw_cmd_stats stats;
497 u8 rate;
498 u8 modulation;
499 struct rate_histogram histogram;
500 u8 reserved1;
501 u16 reserved2;
502} __attribute__ ((packed));
503
504struct notif_association {
505 u8 state;
506} __attribute__ ((packed));
507
508struct notif_authenticate {
509 u8 state;
510 struct machdr24 addr;
511 u16 status;
512} __attribute__ ((packed));
513
43f66a6c
JK		 514struct notif_calibration {
515 u8 data[104];
516} __attribute__ ((packed));
517
518struct notif_noise {
519 u32 value;
520} __attribute__ ((packed));
521
522struct ipw_rx_notification {
523 u8 reserved[8];
524 u8 subtype;
525 u8 flags;
526 u16 size;
527 union {
528 struct notif_association assoc;
529 struct notif_authenticate auth;
530 struct notif_channel_result channel_result;
531 struct notif_scan_complete scan_complete;
532 struct notif_frag_length frag_len;
533 struct notif_beacon_state beacon_state;
534 struct notif_tgi_tx_key tgi_tx_key;
535 struct notif_link_deterioration link_deterioration;
536 struct notif_calibration calibration;
537 struct notif_noise noise;
538 u8 raw[0];
539 } u;
540} __attribute__ ((packed));
541
542struct ipw_rx_frame {
bf79451e 543 u32 reserved1;
43f66a6c
JK		 544 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
545 u8 received_channel; // The channel that this frame was received on.
bf79451e
JG		 546 // Note that for .11b this does not have to be
547 // the same as the channel that it was sent.
43f66a6c
JK		 548 // Filled by LMAC
549 u8 frameStatus;
550 u8 rate;
551 u8 rssi;
552 u8 agc;
553 u8 rssi_dbm;
554 u16 signal;
555 u16 noise;
556 u8 antennaAndPhy;
557 u8 control; // control bit should be on in bg
bf79451e 558 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
43f66a6c
JK		 559 // is identical)
560 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
561 u16 length;
562 u8 data[0];
563} __attribute__ ((packed));
bf79451e 564
43f66a6c
JK		 565struct ipw_rx_header {
566 u8 message_type;
567 u8 rx_seq_num;
568 u8 control_bits;
569 u8 reserved;
570} __attribute__ ((packed));
571
572struct ipw_rx_packet
573{
574 struct ipw_rx_header header;
575 union {
576 struct ipw_rx_frame frame;
577 struct ipw_rx_notification notification;
578 } u;
579} __attribute__ ((packed));
580
581#define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
582#define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \
583 sizeof(struct ipw_rx_frame)
584
585struct ipw_rx_mem_buffer {
586 dma_addr_t dma_addr;
587 struct ipw_rx_buffer *rxb;
588 struct sk_buff *skb;
589 struct list_head list;
590}; /* Not transferred over network, so not __attribute__ ((packed)) */
591
592struct ipw_rx_queue {
593 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
594 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
595 u32 processed; /* Internal index to last handled Rx packet */
596 u32 read; /* Shared index to newest available Rx buffer */
597 u32 write; /* Shared index to oldest written Rx packet */
598 u32 free_count;/* Number of pre-allocated buffers in rx_free */
599 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
600 struct list_head rx_free; /* Own an SKBs */
601 struct list_head rx_used; /* No SKB allocated */
602 spinlock_t lock;
603}; /* Not transferred over network, so not __attribute__ ((packed)) */
604
605
606struct alive_command_responce {
607 u8 alive_command;
608 u8 sequence_number;
609 u16 software_revision;
610 u8 device_identifier;
611 u8 reserved1[5];
612 u16 reserved2;
613 u16 reserved3;
614 u16 clock_settle_time;
615 u16 powerup_settle_time;
616 u16 reserved4;
617 u8 time_stamp[5]; /* month, day, year, hours, minutes */
618 u8 ucode_valid;
619} __attribute__ ((packed));
620
621#define IPW_MAX_RATES 12
622
623struct ipw_rates {
624 u8 num_rates;
625 u8 rates[IPW_MAX_RATES];
626} __attribute__ ((packed));
627
628struct command_block
629{
630 unsigned int control;
631 u32 source_addr;
632 u32 dest_addr;
633 unsigned int status;
634} __attribute__ ((packed));
635
636#define CB_NUMBER_OF_ELEMENTS_SMALL 64
637struct fw_image_desc
638{
639 unsigned long last_cb_index;
640 unsigned long current_cb_index;
641 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
642 void * v_addr;
643 unsigned long p_addr;
644 unsigned long len;
645};
646
647struct ipw_sys_config
648{
649 u8 bt_coexistence;
650 u8 reserved1;
651 u8 answer_broadcast_ssid_probe;
652 u8 accept_all_data_frames;
653 u8 accept_non_directed_frames;
654 u8 exclude_unicast_unencrypted;
655 u8 disable_unicast_decryption;
656 u8 exclude_multicast_unencrypted;
657 u8 disable_multicast_decryption;
658 u8 antenna_diversity;
659 u8 pass_crc_to_host;
660 u8 dot11g_auto_detection;
661 u8 enable_cts_to_self;
662 u8 enable_multicast_filtering;
663 u8 bt_coexist_collision_thr;
664 u8 reserved2;
665 u8 accept_all_mgmt_bcpr;
666 u8 accept_all_mgtm_frames;
667 u8 pass_noise_stats_to_host;
668 u8 reserved3;
669} __attribute__ ((packed));
670
671struct ipw_multicast_addr
672{
673 u8 num_of_multicast_addresses;
674 u8 reserved[3];
675 u8 mac1[6];
676 u8 mac2[6];
677 u8 mac3[6];
678 u8 mac4[6];
679} __attribute__ ((packed));
680
681struct ipw_wep_key
682{
683 u8 cmd_id;
684 u8 seq_num;
685 u8 key_index;
686 u8 key_size;
687 u8 key[16];
688} __attribute__ ((packed));
689
690struct ipw_tgi_tx_key
bf79451e
JG		 691{
692 u8 key_id;
43f66a6c
JK		 693 u8 security_type;
694 u8 station_index;
695 u8 flags;
696 u8 key[16];
697 u32 tx_counter[2];
698} __attribute__ ((packed));
699
700#define IPW_SCAN_CHANNELS 54
701
bf79451e 702struct ipw_scan_request
43f66a6c
JK		 703{
704 u8 scan_type;
705 u16 dwell_time;
706 u8 channels_list[IPW_SCAN_CHANNELS];
707 u8 channels_reserved[3];
708} __attribute__ ((packed));
709
710enum {
711 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
712 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
713 IPW_SCAN_ACTIVE_DIRECT_SCAN,
714 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
715 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
716 IPW_SCAN_TYPES
717};
718
719struct ipw_scan_request_ext
720{
721 u32 full_scan_index;
722 u8 channels_list[IPW_SCAN_CHANNELS];
723 u8 scan_type[IPW_SCAN_CHANNELS / 2];
724 u8 reserved;
725 u16 dwell_time[IPW_SCAN_TYPES];
726} __attribute__ ((packed));
727
bf79451e 728extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
43f66a6c
JK		 729{
730 if (index % 2)
731 return scan->scan_type[index / 2] & 0x0F;
732 else
733 return (scan->scan_type[index / 2] & 0xF0) >> 4;
734}
735
bf79451e 736extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
43f66a6c
JK		 737 u8 index, u8 scan_type)
738{
bf79451e
JG		 739 if (index % 2)
740 scan->scan_type[index / 2] =
741 (scan->scan_type[index / 2] & 0xF0) |
43f66a6c
JK		 742 (scan_type & 0x0F);
743 else
bf79451e
JG		 744 scan->scan_type[index / 2] =
745 (scan->scan_type[index / 2] & 0x0F) |
43f66a6c
JK		 746 ((scan_type & 0x0F) << 4);
747}
748
749struct ipw_associate
750{
751 u8 channel;
752 u8 auth_type:4,
753 auth_key:4;
754 u8 assoc_type;
755 u8 reserved;
756 u16 policy_support;
757 u8 preamble_length;
758 u8 ieee_mode;
759 u8 bssid[ETH_ALEN];
760 u32 assoc_tsf_msw;
761 u32 assoc_tsf_lsw;
762 u16 capability;
763 u16 listen_interval;
764 u16 beacon_interval;
765 u8 dest[ETH_ALEN];
766 u16 atim_window;
767 u8 smr;
768 u8 reserved1;
769 u16 reserved2;
770} __attribute__ ((packed));
771
772struct ipw_supported_rates
773{
774 u8 ieee_mode;
775 u8 num_rates;
776 u8 purpose;
777 u8 reserved;
778 u8 supported_rates[IPW_MAX_RATES];
779} __attribute__ ((packed));
780
781struct ipw_rts_threshold
782{
783 u16 rts_threshold;
784 u16 reserved;
785} __attribute__ ((packed));
786
787struct ipw_frag_threshold
788{
789 u16 frag_threshold;
790 u16 reserved;
791} __attribute__ ((packed));
792
793struct ipw_retry_limit
794{
795 u8 short_retry_limit;
796 u8 long_retry_limit;
797 u16 reserved;
798} __attribute__ ((packed));
799
800struct ipw_dino_config
801{
802 u32 dino_config_addr;
803 u16 dino_config_size;
804 u8 dino_response;
805 u8 reserved;
806} __attribute__ ((packed));
807
808struct ipw_aironet_info
809{
810 u8 id;
811 u8 length;
812 u16 reserved;
813} __attribute__ ((packed));
814
815struct ipw_rx_key
816{
817 u8 station_index;
818 u8 key_type;
819 u8 key_id;
820 u8 key_flag;
821 u8 key[16];
822 u8 station_address[6];
823 u8 key_index;
824 u8 reserved;
825} __attribute__ ((packed));
826
827struct ipw_country_channel_info
828{
829 u8 first_channel;
830 u8 no_channels;
831 s8 max_tx_power;
832} __attribute__ ((packed));
833
834struct ipw_country_info
835{
836 u8 id;
837 u8 length;
838 u8 country_str[3];
839 struct ipw_country_channel_info groups[7];
840} __attribute__ ((packed));
841
842struct ipw_channel_tx_power
843{
844 u8 channel_number;
845 s8 tx_power;
846} __attribute__ ((packed));
847
848#define SCAN_ASSOCIATED_INTERVAL (HZ)
849#define SCAN_INTERVAL (HZ / 10)
850#define MAX_A_CHANNELS 37
851#define MAX_B_CHANNELS 14
852
853struct ipw_tx_power
854{
855 u8 num_channels;
856 u8 ieee_mode;
857 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
858} __attribute__ ((packed));
859
860struct ipw_qos_parameters
861{
862 u16 cw_min[4];
863 u16 cw_max[4];
864 u8 aifs[4];
865 u8 flag[4];
866 u16 tx_op_limit[4];
867} __attribute__ ((packed));
868
869struct ipw_rsn_capabilities
870{
871 u8 id;
872 u8 length;
873 u16 version;
874} __attribute__ ((packed));
875
876struct ipw_sensitivity_calib
877{
878 u16 beacon_rssi_raw;
879 u16 reserved;
880} __attribute__ ((packed));
881
882/**
883 * Host command structure.
bf79451e 884 *
43f66a6c
JK		 885 * On input, the following fields should be filled:
886 * - cmd
887 * - len
888 * - status_len
889 * - param (if needed)
bf79451e
JG		 890 *
891 * On output,
43f66a6c
JK		 892 * - \a status contains status;
893 * - \a param filled with status parameters.
894 */
895struct ipw_cmd {
896 u32 cmd; /**< Host command */
897 u32 status; /**< Status */
898 u32 status_len; /**< How many 32 bit parameters in the status */
899 u32 len; /**< incoming parameters length, bytes */
900 /**
bf79451e
JG		 901 * command parameters.
902 * There should be enough space for incoming and
43f66a6c
JK		 903 * outcoming parameters.
904 * Incoming parameters listed 1-st, followed by outcoming params.
905 * nParams=(len+3)/4+status_len
906 */
907 u32 param[0];
908} __attribute__ ((packed));
909
910#define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
911
912#define STATUS_INT_ENABLED (1<<1)
913#define STATUS_RF_KILL_HW (1<<2)
914#define STATUS_RF_KILL_SW (1<<3)
915#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
916
917#define STATUS_INIT (1<<5)
918#define STATUS_AUTH (1<<6)
919#define STATUS_ASSOCIATED (1<<7)
920#define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
921
922#define STATUS_ASSOCIATING (1<<8)
923#define STATUS_DISASSOCIATING (1<<9)
924#define STATUS_ROAMING (1<<10)
925#define STATUS_EXIT_PENDING (1<<11)
926#define STATUS_DISASSOC_PENDING (1<<12)
927#define STATUS_STATE_PENDING (1<<13)
928
929#define STATUS_SCAN_PENDING (1<<20)
bf79451e
JG		 930#define STATUS_SCANNING (1<<21)
931#define STATUS_SCAN_ABORTING (1<<22)
43f66a6c
JK		 932
933#define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
934#define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
935#define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
936
937#define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
938
939#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
940#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
941#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
942#define CFG_CUSTOM_MAC (1<<3)
943#define CFG_PREAMBLE (1<<4)
944#define CFG_ADHOC_PERSIST (1<<5)
945#define CFG_ASSOCIATE (1<<6)
946#define CFG_FIXED_RATE (1<<7)
947#define CFG_ADHOC_CREATE (1<<8)
948
949#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
950#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
951
952#define MAX_STATIONS 32
953#define IPW_INVALID_STATION (0xff)
954
955struct ipw_station_entry {
956 u8 mac_addr[ETH_ALEN];
957 u8 reserved;
958 u8 support_mode;
959};
960
961#define AVG_ENTRIES 8
962struct average {
963 s16 entries[AVG_ENTRIES];
964 u8 pos;
965 u8 init;
966 s32 sum;
967};
968
969struct ipw_priv {
970 /* ieee device used by generic ieee processing code */
971 struct ieee80211_device *ieee;
972 struct ieee80211_security sec;
973
974 /* spinlock */
975 spinlock_t lock;
976
977 /* basic pci-network driver stuff */
978 struct pci_dev *pci_dev;
979 struct net_device *net_dev;
980
981 /* pci hardware address support */
982 void __iomem *hw_base;
983 unsigned long hw_len;
bf79451e 984
43f66a6c
JK		 985 struct fw_image_desc sram_desc;
986
987 /* result of ucode download */
988 struct alive_command_responce dino_alive;
989
990 wait_queue_head_t wait_command_queue;
991 wait_queue_head_t wait_state;
992
993 /* Rx and Tx DMA processing queues */
994 struct ipw_rx_queue *rxq;
995 struct clx2_tx_queue txq_cmd;
996 struct clx2_tx_queue txq[4];
997 u32 status;
998 u32 config;
999 u32 capability;
1000
1001 u8 last_rx_rssi;
1002 u8 last_noise;
1003 struct average average_missed_beacons;
1004 struct average average_rssi;
1005 struct average average_noise;
1006 u32 port_type;
1007 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
1008 int rx_pend_max; /**< maximum pending buffers for one IRQ */
1009 u32 hcmd_seq; /**< sequence number for hcmd */
1010 u32 missed_beacon_threshold;
bf79451e 1011 u32 roaming_threshold;
43f66a6c
JK		 1012
1013 struct ipw_associate assoc_request;
1014 struct ieee80211_network *assoc_network;
1015
1016 unsigned long ts_scan_abort;
1017 struct ipw_supported_rates rates;
1018 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
1019 struct ipw_rates supp; /**< software defined */
1020 struct ipw_rates extended; /**< use for corresp. IE, AP only */
1021
1022 struct notif_link_deterioration last_link_deterioration; /** for statistics */
1023 struct ipw_cmd* hcmd; /**< host command currently executed */
1024
1025 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
1026 u32 tsf_bcn[2]; /**< TSF from latest beacon */
1027
1028 struct notif_calibration calib; /**< last calibration */
1029
1030 /* ordinal interface with firmware */
1031 u32 table0_addr;
1032 u32 table0_len;
1033 u32 table1_addr;
1034 u32 table1_len;
1035 u32 table2_addr;
1036 u32 table2_len;
1037
1038 /* context information */
1039 u8 essid[IW_ESSID_MAX_SIZE];
1040 u8 essid_len;
1041 u8 nick[IW_ESSID_MAX_SIZE];
1042 u16 rates_mask;
1043 u8 channel;
1044 struct ipw_sys_config sys_config;
1045 u32 power_mode;
bf79451e 1046 u8 bssid[ETH_ALEN];
43f66a6c
JK		 1047 u16 rts_threshold;
1048 u8 mac_addr[ETH_ALEN];
1049 u8 num_stations;
bf79451e 1050 u8 stations[MAX_STATIONS][ETH_ALEN];
43f66a6c
JK		 1051
1052 u32 notif_missed_beacons;
1053
1054 /* Statistics and counters normalized with each association */
1055 u32 last_missed_beacons;
1056 u32 last_tx_packets;
1057 u32 last_rx_packets;
1058 u32 last_tx_failures;
1059 u32 last_rx_err;
1060 u32 last_rate;
1061
1062 u32 missed_adhoc_beacons;
1063 u32 missed_beacons;
1064 u32 rx_packets;
1065 u32 tx_packets;
1066 u32 quality;
1067
1068 /* eeprom */
bf79451e 1069 u8 eeprom[0x100]; /* 256 bytes of eeprom */
43f66a6c
JK		 1070 int eeprom_delay;
1071
bf79451e 1072 struct iw_statistics wstats;
43f66a6c
JK		 1073
1074 struct workqueue_struct *workqueue;
bf79451e 1075
43f66a6c
JK		 1076 struct work_struct adhoc_check;
1077 struct work_struct associate;
1078 struct work_struct disassociate;
1079 struct work_struct rx_replenish;
1080 struct work_struct request_scan;
1081 struct work_struct adapter_restart;
1082 struct work_struct rf_kill;
1083 struct work_struct up;
1084 struct work_struct down;
1085 struct work_struct gather_stats;
1086 struct work_struct abort_scan;
1087 struct work_struct roam;
1088 struct work_struct scan_check;
1089
1090 struct tasklet_struct irq_tasklet;
1091
1092
1093#define IPW_2200BG 1
1094#define IPW_2915ABG 2
1095 u8 adapter;
1096
1097#define IPW_DEFAULT_TX_POWER 0x14
1098 u8 tx_power;
1099
bf79451e 1100#ifdef CONFIG_PM
43f66a6c
JK		 1101 u32 pm_state[16];
1102#endif
1103
1104 /* network state */
1105
1106 /* Used to pass the current INTA value from ISR to Tasklet */
1107 u32 isr_inta;
1108
1109 /* debugging info */
1110 u32 indirect_dword;
1111 u32 direct_dword;
1112 u32 indirect_byte;
1113}; /*ipw_priv */
1114
1115
1116/* debug macros */
1117
1118#ifdef CONFIG_IPW_DEBUG
1119#define IPW_DEBUG(level, fmt, args...) \
1120do { if (ipw_debug_level & (level)) \
1121 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1122 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1123#else
1124#define IPW_DEBUG(level, fmt, args...) do {} while (0)
1125#endif /* CONFIG_IPW_DEBUG */
1126
1127/*
1128 * To use the debug system;
1129 *
1130 * If you are defining a new debug classification, simply add it to the #define
1131 * list here in the form of:
1132 *
1133 * #define IPW_DL_xxxx VALUE
bf79451e 1134 *
43f66a6c
JK		 1135 * shifting value to the left one bit from the previous entry. xxxx should be
1136 * the name of the classification (for example, WEP)
1137 *
1138 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1139 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1140 * to send output to that classification.
1141 *
1142 * To add your debug level to the list of levels seen when you perform
1143 *
1144 * % cat /proc/net/ipw/debug_level
1145 *
1146 * you simply need to add your entry to the ipw_debug_levels array.
1147 *
bf79451e 1148 * If you do not see debug_level in /proc/net/ipw then you do not have
43f66a6c
JK		 1149 * CONFIG_IPW_DEBUG defined in your kernel configuration
1150 *
1151 */
1152
1153#define IPW_DL_ERROR (1<<0)
1154#define IPW_DL_WARNING (1<<1)
1155#define IPW_DL_INFO (1<<2)
1156#define IPW_DL_WX (1<<3)
1157#define IPW_DL_HOST_COMMAND (1<<5)
1158#define IPW_DL_STATE (1<<6)
1159
1160#define IPW_DL_NOTIF (1<<10)
1161#define IPW_DL_SCAN (1<<11)
1162#define IPW_DL_ASSOC (1<<12)
1163#define IPW_DL_DROP (1<<13)
1164#define IPW_DL_IOCTL (1<<14)
1165
1166#define IPW_DL_MANAGE (1<<15)
1167#define IPW_DL_FW (1<<16)
1168#define IPW_DL_RF_KILL (1<<17)
1169#define IPW_DL_FW_ERRORS (1<<18)
1170
1171
1172#define IPW_DL_ORD (1<<20)
1173
1174#define IPW_DL_FRAG (1<<21)
1175#define IPW_DL_WEP (1<<22)
1176#define IPW_DL_TX (1<<23)
1177#define IPW_DL_RX (1<<24)
1178#define IPW_DL_ISR (1<<25)
1179#define IPW_DL_FW_INFO (1<<26)
1180#define IPW_DL_IO (1<<27)
1181#define IPW_DL_TRACE (1<<28)
1182
1183#define IPW_DL_STATS (1<<29)
1184
1185
1186#define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1187#define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1188#define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1189
1190#define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1191#define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1192#define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a)
1193#define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a)
1194#define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a)
1195#define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
1196#define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
1197#define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1198#define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
1199#define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1200#define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
1201#define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a)
1202#define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1203#define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1204#define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a)
1205#define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a)
1206#define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a)
1207#define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1208#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1209#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1210#define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
1211
1212#include <linux/ctype.h>
1213
1214/*
1215* Register bit definitions
1216*/
1217
1218/* Dino control registers bits */
1219
1220#define DINO_ENABLE_SYSTEM 0x80
1221#define DINO_ENABLE_CS 0x40
bf79451e 1222#define DINO_RXFIFO_DATA 0x01
43f66a6c
JK		 1223#define DINO_CONTROL_REG 0x00200000
1224
1225#define CX2_INTA_RW 0x00000008
1226#define CX2_INTA_MASK_R 0x0000000C
1227#define CX2_INDIRECT_ADDR 0x00000010
1228#define CX2_INDIRECT_DATA 0x00000014
1229#define CX2_AUTOINC_ADDR 0x00000018
1230#define CX2_AUTOINC_DATA 0x0000001C
1231#define CX2_RESET_REG 0x00000020
1232#define CX2_GP_CNTRL_RW 0x00000024
1233
1234#define CX2_READ_INT_REGISTER 0xFF4
1235
1236#define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004
1237
1238#define CX2_REGISTER_DOMAIN1_END 0x00001000
1239#define CX2_SRAM_READ_INT_REGISTER 0x00000ff4
1240
1241#define CX2_SHARED_LOWER_BOUND 0x00000200
1242#define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1243
1244#define CX2_NIC_SRAM_LOWER_BOUND 0x00000000
1245#define CX2_NIC_SRAM_UPPER_BOUND 0x00030000
1246
1247#define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1248#define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1249#define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1250
1251/*
1252 * RESET Register Bit Indexes
1253 */
1254#define CBD_RESET_REG_PRINCETON_RESET 0x00000001 /* Bit 0 (LSB) */
1255#define CX2_RESET_REG_SW_RESET 0x00000080 /* Bit 7 */
1256#define CX2_RESET_REG_MASTER_DISABLED 0x00000100 /* Bit 8 */
1257#define CX2_RESET_REG_STOP_MASTER 0x00000200 /* Bit 9 */
1258#define CX2_ARC_KESHET_CONFIG 0x08000000 /* Bit 27 */
1259#define CX2_START_STANDBY 0x00000004 /* Bit 2 */
1260
1261#define CX2_CSR_CIS_UPPER_BOUND 0x00000200
1262#define CX2_DOMAIN_0_END 0x1000
1263#define CLX_MEM_BAR_SIZE 0x1000
1264
1265#define CX2_BASEBAND_CONTROL_STATUS 0X00200000
1266#define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004
1267#define CX2_BASEBAND_RX_FIFO_READ 0X00200004
1268#define CX2_BASEBAND_CONTROL_STORE 0X00200010
1269
1270#define CX2_INTERNAL_CMD_EVENT 0X00300004
1271#define CX2_BASEBAND_POWER_DOWN 0x00000001
1272
1273#define CX2_MEM_HALT_AND_RESET 0x003000e0
1274
1275/* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1276#define CX2_BIT_HALT_RESET_ON 0x80000000
1277#define CX2_BIT_HALT_RESET_OFF 0x00000000
1278
1279#define CB_LAST_VALID 0x20000000
1280#define CB_INT_ENABLED 0x40000000
1281#define CB_VALID 0x80000000
1282#define CB_SRC_LE 0x08000000
1283#define CB_DEST_LE 0x04000000
1284#define CB_SRC_AUTOINC 0x00800000
1285#define CB_SRC_IO_GATED 0x00400000
1286#define CB_DEST_AUTOINC 0x00080000
1287#define CB_SRC_SIZE_LONG 0x00200000
1288#define CB_DEST_SIZE_LONG 0x00020000
1289
1290
1291/* DMA DEFINES */
1292
1293#define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1294#define DMA_CB_STOP_AND_ABORT 0x00000C00
bf79451e 1295#define DMA_CB_START 0x00000100
43f66a6c
JK		 1296
1297
1298#define CX2_SHARED_SRAM_SIZE 0x00030000
1299#define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000
1300#define CB_MAX_LENGTH 0x1FFF
1301
1302#define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1303#define CX2_EEPROM_IMAGE_SIZE 0x100
1304
1305
1306/* DMA defs */
1307#define CX2_DMA_I_CURRENT_CB 0x003000D0
1308#define CX2_DMA_O_CURRENT_CB 0x003000D4
1309#define CX2_DMA_I_DMA_CONTROL 0x003000A4
1310#define CX2_DMA_I_CB_BASE 0x003000A0
1311
1312#define CX2_TX_CMD_QUEUE_BD_BASE (0x00000200)
1313#define CX2_TX_CMD_QUEUE_BD_SIZE (0x00000204)
1314#define CX2_TX_QUEUE_0_BD_BASE (0x00000208)
1315#define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C)
1316#define CX2_TX_QUEUE_1_BD_BASE (0x00000210)
1317#define CX2_TX_QUEUE_1_BD_SIZE (0x00000214)
1318#define CX2_TX_QUEUE_2_BD_BASE (0x00000218)
1319#define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C)
1320#define CX2_TX_QUEUE_3_BD_BASE (0x00000220)
1321#define CX2_TX_QUEUE_3_BD_SIZE (0x00000224)
1322#define CX2_RX_BD_BASE (0x00000240)
1323#define CX2_RX_BD_SIZE (0x00000244)
1324#define CX2_RFDS_TABLE_LOWER (0x00000500)
1325
1326#define CX2_TX_CMD_QUEUE_READ_INDEX (0x00000280)
1327#define CX2_TX_QUEUE_0_READ_INDEX (0x00000284)
1328#define CX2_TX_QUEUE_1_READ_INDEX (0x00000288)
1329#define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C)
1330#define CX2_TX_QUEUE_3_READ_INDEX (0x00000290)
1331#define CX2_RX_READ_INDEX (0x000002A0)
1332
1333#define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1334#define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1335#define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1336#define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1337#define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1338#define CX2_RX_WRITE_INDEX (0x00000FA0)
1339
1340/*
1341 * EEPROM Related Definitions
1342 */
1343
1344#define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814)
1345#define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818)
1346#define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C)
1347#define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820)
1348#define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0)
1349
1350#define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C)
1351#define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C)
1352#define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C)
1353#define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10)
1354#define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14)
1355#define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18)
1356
1357
1358#define MSB 1
1359#define LSB 0
1360#define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1361
1362#define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1363 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1364
1365/* EEPROM access by BYTE */
1366#define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1367#define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1368#define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1369#define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1370#define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1371#define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1372#define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1373#define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1374#define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1375#define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1376
1377/* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
1378#define EEPROM_NIC_TYPE_STANDARD 0
1379#define EEPROM_NIC_TYPE_DELL 1
1380#define EEPROM_NIC_TYPE_FUJITSU 2
1381#define EEPROM_NIC_TYPE_IBM 3
1382#define EEPROM_NIC_TYPE_HP 4
1383
1384#define FW_MEM_REG_LOWER_BOUND 0x00300000
bf79451e 1385#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
43f66a6c
JK		 1386
1387#define EEPROM_BIT_SK (1<<0)
1388#define EEPROM_BIT_CS (1<<1)
1389#define EEPROM_BIT_DI (1<<2)
1390#define EEPROM_BIT_DO (1<<4)
1391
1392#define EEPROM_CMD_READ 0x2
1393
1394/* Interrupts masks */
1395#define CX2_INTA_NONE 0x00000000
1396
1397#define CX2_INTA_BIT_RX_TRANSFER 0x00000002
1398#define CX2_INTA_BIT_STATUS_CHANGE 0x00000010
1399#define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1400
1401//Inta Bits for CF
1402#define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800
1403#define CX2_INTA_BIT_TX_QUEUE_1 0x00001000
1404#define CX2_INTA_BIT_TX_QUEUE_2 0x00002000
1405#define CX2_INTA_BIT_TX_QUEUE_3 0x00004000
1406#define CX2_INTA_BIT_TX_QUEUE_4 0x00008000
1407
1408#define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1409
1410#define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1411#define CX2_INTA_BIT_POWER_DOWN 0x00200000
1412
1413#define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1414#define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1415#define CX2_INTA_BIT_RF_KILL_DONE 0x04000000
1416#define CX2_INTA_BIT_FATAL_ERROR 0x40000000
1417#define CX2_INTA_BIT_PARITY_ERROR 0x80000000
1418
1419/* Interrupts enabled at init time. */
1420#define CX2_INTA_MASK_ALL \
1421 (CX2_INTA_BIT_TX_QUEUE_1 | \
1422 CX2_INTA_BIT_TX_QUEUE_2 | \
1423 CX2_INTA_BIT_TX_QUEUE_3 | \
1424 CX2_INTA_BIT_TX_QUEUE_4 | \
1425 CX2_INTA_BIT_TX_CMD_QUEUE | \
1426 CX2_INTA_BIT_RX_TRANSFER | \
1427 CX2_INTA_BIT_FATAL_ERROR | \
1428 CX2_INTA_BIT_PARITY_ERROR | \
1429 CX2_INTA_BIT_STATUS_CHANGE | \
1430 CX2_INTA_BIT_FW_INITIALIZATION_DONE | \
1431 CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1432 CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1433 CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1434 CX2_INTA_BIT_POWER_DOWN | \
1435 CX2_INTA_BIT_RF_KILL_DONE )
1436
1437#define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410)
1438#define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414)
1439
1440/* FW event log definitions */
1441#define EVENT_ELEM_SIZE (3 * sizeof(u32))
1442#define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1443
1444/* FW error log definitions */
1445#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1446#define ERROR_START_OFFSET (1 * sizeof(u32))
1447
1448enum {
1449 IPW_FW_ERROR_OK = 0,
1450 IPW_FW_ERROR_FAIL,
1451 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1452 IPW_FW_ERROR_MEMORY_OVERFLOW,
1453 IPW_FW_ERROR_BAD_PARAM,
1454 IPW_FW_ERROR_BAD_CHECKSUM,
1455 IPW_FW_ERROR_NMI_INTERRUPT,
1456 IPW_FW_ERROR_BAD_DATABASE,
1457 IPW_FW_ERROR_ALLOC_FAIL,
1458 IPW_FW_ERROR_DMA_UNDERRUN,
1459 IPW_FW_ERROR_DMA_STATUS,
1460 IPW_FW_ERROR_DINOSTATUS_ERROR,
1461 IPW_FW_ERROR_EEPROMSTATUS_ERROR,
1462 IPW_FW_ERROR_SYSASSERT,
1463 IPW_FW_ERROR_FATAL_ERROR
1464};
1465
1466#define AUTH_OPEN 0
1467#define AUTH_SHARED_KEY 1
1468#define AUTH_IGNORE 3
1469
1470#define HC_ASSOCIATE 0
1471#define HC_REASSOCIATE 1
1472#define HC_DISASSOCIATE 2
1473#define HC_IBSS_START 3
1474#define HC_IBSS_RECONF 4
1475#define HC_DISASSOC_QUIET 5
1476
1477#define IPW_RATE_CAPABILITIES 1
1478#define IPW_RATE_CONNECT 0
1479
1480
bf79451e
JG		 1481/*
1482 * Rate values and masks
43f66a6c
JK		 1483 */
1484#define IPW_TX_RATE_1MB 0x0A
1485#define IPW_TX_RATE_2MB 0x14
1486#define IPW_TX_RATE_5MB 0x37
1487#define IPW_TX_RATE_6MB 0x0D
1488#define IPW_TX_RATE_9MB 0x0F
bf79451e 1489#define IPW_TX_RATE_11MB 0x6E
43f66a6c
JK		 1490#define IPW_TX_RATE_12MB 0x05
1491#define IPW_TX_RATE_18MB 0x07
1492#define IPW_TX_RATE_24MB 0x09
1493#define IPW_TX_RATE_36MB 0x0B
1494#define IPW_TX_RATE_48MB 0x01
1495#define IPW_TX_RATE_54MB 0x03
1496
1497#define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1498#define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1499
bf79451e
JG		 1500#define IPW_ORD_TABLE_0_MASK 0x0000F000
1501#define IPW_ORD_TABLE_1_MASK 0x0000F100
1502#define IPW_ORD_TABLE_2_MASK 0x0000F200
1503#define IPW_ORD_TABLE_3_MASK 0x0000F300
1504#define IPW_ORD_TABLE_4_MASK 0x0000F400
1505#define IPW_ORD_TABLE_5_MASK 0x0000F500
1506#define IPW_ORD_TABLE_6_MASK 0x0000F600
1507#define IPW_ORD_TABLE_7_MASK 0x0000F700
43f66a6c
JK		 1508
1509/*
1510 * Table 0 Entries (all entries are 32 bits)
1511 */
bf79451e 1512enum {
43f66a6c
JK		 1513 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1514 IPW_ORD_STAT_FRAG_TRESHOLD,
1515 IPW_ORD_STAT_RTS_THRESHOLD,
bf79451e
JG		 1516 IPW_ORD_STAT_TX_HOST_REQUESTS,
1517 IPW_ORD_STAT_TX_HOST_COMPLETE,
1518 IPW_ORD_STAT_TX_DIR_DATA,
43f66a6c
JK		 1519 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1520 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1521 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1522 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1523 /* Hole */
1524
1525
1526
1527
1528
1529
1530
1531 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1532 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1533 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1534 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1535 IPW_ORD_STAT_TX_DIR_DATA_G_9,
bf79451e 1536 IPW_ORD_STAT_TX_DIR_DATA_G_11,
43f66a6c
JK		 1537 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1538 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1539 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1540 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1541 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1542 IPW_ORD_STAT_TX_DIR_DATA_G_54,
bf79451e 1543 IPW_ORD_STAT_TX_NON_DIR_DATA,
43f66a6c
JK		 1544 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1545 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1546 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
bf79451e 1547 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
43f66a6c
JK		 1548 /* Hole */
1549
1550
1551
1552
1553
1554
1555
1556 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1557 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1558 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1559 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1560 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
bf79451e 1561 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
43f66a6c
JK		 1562 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1563 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1564 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1565 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1566 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1567 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1568 IPW_ORD_STAT_TX_RETRY,
1569 IPW_ORD_STAT_TX_FAILURE,
1570 IPW_ORD_STAT_RX_ERR_CRC,
1571 IPW_ORD_STAT_RX_ERR_ICV,
1572 IPW_ORD_STAT_RX_NO_BUFFER,
1573 IPW_ORD_STAT_FULL_SCANS,
1574 IPW_ORD_STAT_PARTIAL_SCANS,
1575 IPW_ORD_STAT_TGH_ABORTED_SCANS,
bf79451e 1576 IPW_ORD_STAT_TX_TOTAL_BYTES,
43f66a6c
JK		 1577 IPW_ORD_STAT_CURR_RSSI_RAW,
1578 IPW_ORD_STAT_RX_BEACON,
1579 IPW_ORD_STAT_MISSED_BEACONS,
bf79451e
JG		 1580 IPW_ORD_TABLE_0_LAST
1581};
43f66a6c
JK		 1582
1583#define IPW_RSSI_TO_DBM 112
1584
1585/* Table 1 Entries
1586 */
1587enum {
1588 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1589};
1590
1591/*
1592 * Table 2 Entries
1593 *
1594 * FW_VERSION: 16 byte string
1595 * FW_DATE: 16 byte string (only 14 bytes used)
1596 * UCODE_VERSION: 4 byte version code
1597 * UCODE_DATE: 5 bytes code code
1598 * ADDAPTER_MAC: 6 byte MAC address
1599 * RTC: 4 byte clock
1600 */
bf79451e 1601enum {
43f66a6c 1602 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
bf79451e 1603 IPW_ORD_STAT_FW_DATE,
43f66a6c 1604 IPW_ORD_STAT_UCODE_VERSION,
bf79451e
JG		 1605 IPW_ORD_STAT_UCODE_DATE,
1606 IPW_ORD_STAT_ADAPTER_MAC,
1607 IPW_ORD_STAT_RTC,
1608 IPW_ORD_TABLE_2_LAST
1609};
43f66a6c
JK		 1610
1611/* Table 3 */
1612enum {
1613 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1614 IPW_ORD_STAT_TX_PACKET_FAILURE,
1615 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1616 IPW_ORD_STAT_TX_PACKET_ABORTED,
1617 IPW_ORD_TABLE_3_LAST
1618};
1619
1620/* Table 4 */
1621enum {
1622 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1623};
1624
1625/* Table 5 */
1626enum {
1627 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1628 IPW_ORD_STAT_AP_ASSNS,
1629 IPW_ORD_STAT_ROAM,
1630 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1631 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1632 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1633 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1634 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1635 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1636 IPW_ORD_STAT_LINK_UP,
1637 IPW_ORD_STAT_LINK_DOWN,
1638 IPW_ORD_ANTENNA_DIVERSITY,
1639 IPW_ORD_CURR_FREQ,
1640 IPW_ORD_TABLE_5_LAST
1641};
1642
1643/* Table 6 */
1644enum {
1645 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1646 IPW_ORD_CURR_BSSID,
1647 IPW_ORD_CURR_SSID,
1648 IPW_ORD_TABLE_6_LAST
1649};
1650
1651/* Table 7 */
1652enum {
1653 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1654 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1655 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1656 IPW_ORD_STAT_CURR_RSSI_DBM,
1657 IPW_ORD_TABLE_7_LAST
1658};
1659
1660#define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500)
1661#define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180)
1662#define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184)
1663#define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188)
1664#define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C)
1665
1666struct ipw_fixed_rate {
1667 u16 tx_rates;
1668 u16 reserved;
1669} __attribute__ ((packed));
1670
1671#define CX2_INDIRECT_ADDR_MASK (~0x3ul)
1672
1673struct host_cmd {
1674 u8 cmd;
1675 u8 len;
1676 u16 reserved;
1677 u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
1678} __attribute__ ((packed));
1679
1680#define CFG_BT_COEXISTENCE_MIN 0x00
1681#define CFG_BT_COEXISTENCE_DEFER 0x02
1682#define CFG_BT_COEXISTENCE_KILL 0x04
1683#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08
1684#define CFG_BT_COEXISTENCE_OOB 0x10
1685#define CFG_BT_COEXISTENCE_MAX 0xFF
bf79451e 1686#define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM*/
43f66a6c
JK		 1687
1688#define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0
1689#define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1
1690#define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1691
1692#define CFG_SYS_ANTENNA_BOTH 0x000
1693#define CFG_SYS_ANTENNA_A 0x001
1694#define CFG_SYS_ANTENNA_B 0x003
1695
1696/*
bf79451e 1697 * The definitions below were lifted off the ipw2100 driver, which only
43f66a6c 1698 * supports 'b' mode, so I'm sure these are not exactly correct.
bf79451e 1699 *
43f66a6c
JK		 1700 * Somebody fix these!!
1701 */
1702#define REG_MIN_CHANNEL 0
1703#define REG_MAX_CHANNEL 14
1704
1705#define REG_CHANNEL_MASK 0x00003FFF
1706#define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
1707
bf79451e
JG		 1708static const long ipw_frequencies[] = {
1709 2412, 2417, 2422, 2427,
1710 2432, 2437, 2442, 2447,
1711 2452, 2457, 2462, 2467,
1712 2472, 2484
43f66a6c
JK		 1713};
1714
1715#define FREQ_COUNT ARRAY_SIZE(ipw_frequencies)
1716
1717#define IPW_MAX_CONFIG_RETRIES 10
1718
1719static inline u32 frame_hdr_len(struct ieee80211_hdr *hdr)
1720{
1721 u32 retval;
1722 u16 fc;
1723
1724 retval = sizeof(struct ieee80211_hdr);
1725 fc = le16_to_cpu(hdr->frame_ctl);
1726
1727 /*
1728 * Function ToDS FromDS
1729 * IBSS 0 0
1730 * To AP 1 0
1731 * From AP 0 1
1732 * WDS (bridge) 1 1
1733 *
1734 * Only WDS frames use Address4 among them. --YZ
1735 */
1736 if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS))
1737 retval -= ETH_ALEN;
1738
1739 return retval;
1740}
1741
1742#endif /* __ipw2200_h__ */
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