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1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
33 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. | |
34 | * All rights reserved. | |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
63 | #ifndef __iwl_legacy_fh_h__ | |
64 | #define __iwl_legacy_fh_h__ | |
65 | ||
66 | /****************************/ | |
67 | /* Flow Handler Definitions */ | |
68 | /****************************/ | |
69 | ||
70 | /** | |
71 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) | |
72 | * Addresses are offsets from device's PCI hardware base address. | |
73 | */ | |
74 | #define FH_MEM_LOWER_BOUND (0x1000) | |
75 | #define FH_MEM_UPPER_BOUND (0x2000) | |
76 | ||
77 | /** | |
78 | * Keep-Warm (KW) buffer base address. | |
79 | * | |
80 | * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the | |
81 | * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency | |
82 | * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host | |
83 | * from going into a power-savings mode that would cause higher DRAM latency, | |
84 | * and possible data over/under-runs, before all Tx/Rx is complete. | |
85 | * | |
86 | * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) | |
87 | * of the buffer, which must be 4K aligned. Once this is set up, the 4965 | |
88 | * automatically invokes keep-warm accesses when normal accesses might not | |
89 | * be sufficient to maintain fast DRAM response. | |
90 | * | |
91 | * Bit fields: | |
92 | * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned | |
93 | */ | |
94 | #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) | |
95 | ||
96 | ||
97 | /** | |
98 | * TFD Circular Buffers Base (CBBC) addresses | |
99 | * | |
100 | * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident | |
101 | * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) | |
102 | * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 | |
103 | * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte | |
104 | * aligned (address bits 0-7 must be 0). | |
105 | * | |
106 | * Bit fields in each pointer register: | |
107 | * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned | |
108 | */ | |
109 | #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) | |
110 | #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) | |
111 | ||
112 | /* Find TFD CB base pointer for given queue (range 0-15). */ | |
113 | #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) | |
114 | ||
115 | ||
116 | /** | |
117 | * Rx SRAM Control and Status Registers (RSCSR) | |
118 | * | |
119 | * These registers provide handshake between driver and 4965 for the Rx queue | |
120 | * (this queue handles *all* command responses, notifications, Rx data, etc. | |
121 | * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx | |
122 | * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can | |
123 | * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer | |
124 | * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 | |
125 | * mapping between RBDs and RBs. | |
126 | * | |
127 | * Driver must allocate host DRAM memory for the following, and set the | |
128 | * physical address of each into 4965 registers: | |
129 | * | |
130 | * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 | |
131 | * entries (although any power of 2, up to 4096, is selectable by driver). | |
132 | * Each entry (1 dword) points to a receive buffer (RB) of consistent size | |
133 | * (typically 4K, although 8K or 16K are also selectable by driver). | |
134 | * Driver sets up RB size and number of RBDs in the CB via Rx config | |
135 | * register FH_MEM_RCSR_CHNL0_CONFIG_REG. | |
136 | * | |
137 | * Bit fields within one RBD: | |
138 | * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned | |
139 | * | |
140 | * Driver sets physical address [35:8] of base of RBD circular buffer | |
141 | * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. | |
142 | * | |
143 | * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers | |
144 | * (RBs) have been filled, via a "write pointer", actually the index of | |
145 | * the RB's corresponding RBD within the circular buffer. Driver sets | |
146 | * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. | |
147 | * | |
148 | * Bit fields in lower dword of Rx status buffer (upper dword not used | |
149 | * by driver; see struct iwl4965_shared, val0): | |
150 | * 31-12: Not used by driver | |
151 | * 11- 0: Index of last filled Rx buffer descriptor | |
152 | * (4965 writes, driver reads this value) | |
153 | * | |
154 | * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must | |
155 | * enter pointers to these RBs into contiguous RBD circular buffer entries, | |
156 | * and update the 4965's "write" index register, | |
157 | * FH_RSCSR_CHNL0_RBDCB_WPTR_REG. | |
158 | * | |
159 | * This "write" index corresponds to the *next* RBD that the driver will make | |
160 | * available, i.e. one RBD past the tail of the ready-to-fill RBDs within | |
161 | * the circular buffer. This value should initially be 0 (before preparing any | |
162 | * RBs), should be 8 after preparing the first 8 RBs (for example), and must | |
163 | * wrap back to 0 at the end of the circular buffer (but don't wrap before | |
164 | * "read" index has advanced past 1! See below). | |
165 | * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. | |
166 | * | |
167 | * As the 4965 fills RBs (referenced from contiguous RBDs within the circular | |
168 | * buffer), it updates the Rx status buffer in host DRAM, 2) described above, | |
169 | * to tell the driver the index of the latest filled RBD. The driver must | |
170 | * read this "read" index from DRAM after receiving an Rx interrupt from 4965. | |
171 | * | |
172 | * The driver must also internally keep track of a third index, which is the | |
173 | * next RBD to process. When receiving an Rx interrupt, driver should process | |
174 | * all filled but unprocessed RBs up to, but not including, the RB | |
175 | * corresponding to the "read" index. For example, if "read" index becomes "1", | |
176 | * driver may process the RB pointed to by RBD 0. Depending on volume of | |
177 | * traffic, there may be many RBs to process. | |
178 | * | |
179 | * If read index == write index, 4965 thinks there is no room to put new data. | |
180 | * Due to this, the maximum number of filled RBs is 255, instead of 256. To | |
181 | * be safe, make sure that there is a gap of at least 2 RBDs between "write" | |
182 | * and "read" indexes; that is, make sure that there are no more than 254 | |
183 | * buffers waiting to be filled. | |
184 | */ | |
185 | #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) | |
186 | #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
187 | #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) | |
188 | ||
189 | /** | |
190 | * Physical base address of 8-byte Rx Status buffer. | |
191 | * Bit fields: | |
192 | * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. | |
193 | */ | |
194 | #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) | |
195 | ||
196 | /** | |
197 | * Physical base address of Rx Buffer Descriptor Circular Buffer. | |
198 | * Bit fields: | |
199 | * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. | |
200 | */ | |
201 | #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) | |
202 | ||
203 | /** | |
204 | * Rx write pointer (index, really!). | |
205 | * Bit fields: | |
206 | * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. | |
207 | * NOTE: For 256-entry circular buffer, use only bits [7:0]. | |
208 | */ | |
209 | #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) | |
210 | #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) | |
211 | ||
212 | ||
213 | /** | |
214 | * Rx Config/Status Registers (RCSR) | |
215 | * Rx Config Reg for channel 0 (only channel used) | |
216 | * | |
217 | * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for | |
218 | * normal operation (see bit fields). | |
219 | * | |
220 | * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. | |
221 | * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for | |
222 | * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. | |
223 | * | |
224 | * Bit fields: | |
225 | * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
226 | * '10' operate normally | |
227 | * 29-24: reserved | |
228 | * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), | |
229 | * min "5" for 32 RBDs, max "12" for 4096 RBDs. | |
230 | * 19-18: reserved | |
231 | * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, | |
232 | * '10' 12K, '11' 16K. | |
233 | * 15-14: reserved | |
234 | * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) | |
235 | * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) | |
236 | * typical value 0x10 (about 1/2 msec) | |
237 | * 3- 0: reserved | |
238 | */ | |
239 | #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
240 | #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) | |
241 | #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) | |
242 | ||
243 | #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) | |
244 | ||
245 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ | |
246 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ | |
247 | #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ | |
248 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ | |
249 | #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ | |
250 | #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ | |
251 | ||
252 | #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) | |
253 | #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) | |
254 | #define RX_RB_TIMEOUT (0x10) | |
255 | ||
256 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) | |
257 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) | |
258 | #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) | |
259 | ||
260 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) | |
261 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) | |
262 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) | |
263 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) | |
264 | ||
265 | #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) | |
266 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) | |
267 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) | |
268 | ||
269 | #define FH_RSCSR_FRAME_SIZE_MSK (0x00003FFF) /* bits 0-13 */ | |
270 | ||
271 | /** | |
272 | * Rx Shared Status Registers (RSSR) | |
273 | * | |
274 | * After stopping Rx DMA channel (writing 0 to | |
275 | * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll | |
276 | * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. | |
277 | * | |
278 | * Bit fields: | |
279 | * 24: 1 = Channel 0 is idle | |
280 | * | |
281 | * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV | |
282 | * contain default values that should not be altered by the driver. | |
283 | */ | |
284 | #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) | |
285 | #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) | |
286 | ||
287 | #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) | |
288 | #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) | |
289 | #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ | |
290 | (FH_MEM_RSSR_LOWER_BOUND + 0x008) | |
291 | ||
292 | #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) | |
293 | ||
294 | #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 | |
295 | ||
296 | /* TFDB Area - TFDs buffer table */ | |
297 | #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) | |
298 | #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) | |
299 | #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) | |
300 | #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) | |
301 | #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) | |
302 | ||
303 | /** | |
304 | * Transmit DMA Channel Control/Status Registers (TCSR) | |
305 | * | |
306 | * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels | |
307 | * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, | |
308 | * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. | |
309 | * | |
310 | * To use a Tx DMA channel, driver must initialize its | |
311 | * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: | |
312 | * | |
313 | * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
314 | * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | |
315 | * | |
316 | * All other bits should be 0. | |
317 | * | |
318 | * Bit fields: | |
319 | * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
320 | * '10' operate normally | |
321 | * 29- 4: Reserved, set to "0" | |
322 | * 3: Enable internal DMA requests (1, normal operation), disable (0) | |
323 | * 2- 0: Reserved, set to "0" | |
324 | */ | |
325 | #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) | |
326 | #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) | |
327 | ||
328 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ | |
329 | #define FH49_TCSR_CHNL_NUM (7) | |
330 | #define FH50_TCSR_CHNL_NUM (8) | |
331 | ||
332 | /* TCSR: tx_config register values */ | |
333 | #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ | |
334 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) | |
335 | #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ | |
336 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) | |
337 | #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ | |
338 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) | |
339 | ||
340 | #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) | |
341 | #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) | |
342 | ||
343 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) | |
344 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) | |
345 | ||
346 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) | |
347 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) | |
348 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) | |
349 | ||
350 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) | |
351 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) | |
352 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) | |
353 | ||
354 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) | |
355 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) | |
356 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
357 | ||
358 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) | |
359 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) | |
360 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) | |
361 | ||
362 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) | |
363 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) | |
364 | ||
365 | /** | |
366 | * Tx Shared Status Registers (TSSR) | |
367 | * | |
368 | * After stopping Tx DMA channel (writing 0 to | |
369 | * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll | |
370 | * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle | |
371 | * (channel's buffers empty | no pending requests). | |
372 | * | |
373 | * Bit fields: | |
374 | * 31-24: 1 = Channel buffers empty (channel 7:0) | |
375 | * 23-16: 1 = No pending requests (channel 7:0) | |
376 | */ | |
377 | #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) | |
378 | #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) | |
379 | ||
380 | #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) | |
381 | ||
382 | /** | |
383 | * Bit fields for TSSR(Tx Shared Status & Control) error status register: | |
384 | * 31: Indicates an address error when accessed to internal memory | |
385 | * uCode/driver must write "1" in order to clear this flag | |
386 | * 30: Indicates that Host did not send the expected number of dwords to FH | |
387 | * uCode/driver must write "1" in order to clear this flag | |
388 | * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA | |
389 | * command was received from the scheduler while the TRB was already full | |
390 | * with previous command | |
391 | * uCode/driver must write "1" in order to clear this flag | |
392 | * 7-0: Each status bit indicates a channel's TxCredit error. When an error | |
393 | * bit is set, it indicates that the FH has received a full indication | |
394 | * from the RTC TxFIFO and the current value of the TxCredit counter was | |
395 | * not equal to zero. This mean that the credit mechanism was not | |
396 | * synchronized to the TxFIFO status | |
397 | * uCode/driver must write "1" in order to clear this flag | |
398 | */ | |
399 | #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) | |
400 | ||
401 | #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) | |
402 | ||
403 | /* Tx service channels */ | |
404 | #define FH_SRVC_CHNL (9) | |
405 | #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) | |
406 | #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) | |
407 | #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ | |
408 | (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) | |
409 | ||
410 | #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) | |
411 | /* Instruct FH to increment the retry count of a packet when | |
412 | * it is brought from the memory to TX-FIFO | |
413 | */ | |
414 | #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) | |
415 | ||
416 | #define RX_QUEUE_SIZE 256 | |
417 | #define RX_QUEUE_MASK 255 | |
418 | #define RX_QUEUE_SIZE_LOG 8 | |
419 | ||
420 | /* | |
421 | * RX related structures and functions | |
422 | */ | |
423 | #define RX_FREE_BUFFERS 64 | |
424 | #define RX_LOW_WATERMARK 8 | |
425 | ||
426 | /* Size of one Rx buffer in host DRAM */ | |
427 | #define IWL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */ | |
428 | #define IWL_RX_BUF_SIZE_4K (4 * 1024) | |
429 | #define IWL_RX_BUF_SIZE_8K (8 * 1024) | |
430 | ||
431 | /** | |
432 | * struct iwl_rb_status - reseve buffer status | |
433 | * host memory mapped FH registers | |
434 | * @closed_rb_num [0:11] - Indicates the index of the RB which was closed | |
435 | * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed | |
436 | * @finished_rb_num [0:11] - Indicates the index of the current RB | |
437 | * in which the last frame was written to | |
438 | * @finished_fr_num [0:11] - Indicates the index of the RX Frame | |
25985edc | 439 | * which was transferred |
be663ab6 WYG |
440 | */ |
441 | struct iwl_rb_status { | |
442 | __le16 closed_rb_num; | |
443 | __le16 closed_fr_num; | |
444 | __le16 finished_rb_num; | |
445 | __le16 finished_fr_nam; | |
446 | __le32 __unused; /* 3945 only */ | |
447 | } __packed; | |
448 | ||
449 | ||
450 | #define TFD_QUEUE_SIZE_MAX (256) | |
451 | #define TFD_QUEUE_SIZE_BC_DUP (64) | |
452 | #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) | |
453 | #define IWL_TX_DMA_MASK DMA_BIT_MASK(36) | |
454 | #define IWL_NUM_OF_TBS 20 | |
455 | ||
456 | static inline u8 iwl_legacy_get_dma_hi_addr(dma_addr_t addr) | |
457 | { | |
458 | return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; | |
459 | } | |
460 | /** | |
461 | * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor | |
462 | * | |
463 | * This structure contains dma address and length of transmission address | |
464 | * | |
465 | * @lo: low [31:0] portion of the dma address of TX buffer | |
466 | * every even is unaligned on 16 bit boundary | |
467 | * @hi_n_len 0-3 [35:32] portion of dma | |
468 | * 4-15 length of the tx buffer | |
469 | */ | |
470 | struct iwl_tfd_tb { | |
471 | __le32 lo; | |
472 | __le16 hi_n_len; | |
473 | } __packed; | |
474 | ||
475 | /** | |
476 | * struct iwl_tfd | |
477 | * | |
478 | * Transmit Frame Descriptor (TFD) | |
479 | * | |
480 | * @ __reserved1[3] reserved | |
481 | * @ num_tbs 0-4 number of active tbs | |
482 | * 5 reserved | |
483 | * 6-7 padding (not used) | |
484 | * @ tbs[20] transmit frame buffer descriptors | |
485 | * @ __pad padding | |
486 | * | |
487 | * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. | |
488 | * Both driver and device share these circular buffers, each of which must be | |
489 | * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes | |
490 | * | |
491 | * Driver must indicate the physical address of the base of each | |
492 | * circular buffer via the FH_MEM_CBBC_QUEUE registers. | |
493 | * | |
494 | * Each TFD contains pointer/size information for up to 20 data buffers | |
495 | * in host DRAM. These buffers collectively contain the (one) frame described | |
496 | * by the TFD. Each buffer must be a single contiguous block of memory within | |
497 | * itself, but buffers may be scattered in host DRAM. Each buffer has max size | |
498 | * of (4K - 4). The concatenates all of a TFD's buffers into a single | |
499 | * Tx frame, up to 8 KBytes in size. | |
500 | * | |
501 | * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. | |
502 | */ | |
503 | struct iwl_tfd { | |
504 | u8 __reserved1[3]; | |
505 | u8 num_tbs; | |
506 | struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; | |
507 | __le32 __pad; | |
508 | } __packed; | |
509 | ||
510 | /* Keep Warm Size */ | |
511 | #define IWL_KW_SIZE 0x1000 /* 4k */ | |
512 | ||
513 | #endif /* !__iwl_legacy_fh_h__ */ |