]>
Commit | Line | Data |
---|---|---|
be663ab6 WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/slab.h> | |
ee40fa06 | 33 | #include <linux/export.h> |
be663ab6 WYG |
34 | #include <net/mac80211.h> |
35 | #include "iwl-eeprom.h" | |
36 | #include "iwl-dev.h" | |
37 | #include "iwl-core.h" | |
38 | #include "iwl-sta.h" | |
39 | #include "iwl-io.h" | |
40 | #include "iwl-helpers.h" | |
41 | ||
42 | /** | |
43 | * iwl_legacy_txq_update_write_ptr - Send new write index to hardware | |
44 | */ | |
45 | void | |
46 | iwl_legacy_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
47 | { | |
48 | u32 reg = 0; | |
49 | int txq_id = txq->q.id; | |
50 | ||
51 | if (txq->need_update == 0) | |
52 | return; | |
53 | ||
54 | /* if we're trying to save power */ | |
55 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
56 | /* wake up nic if it's powered down ... | |
57 | * uCode will wake up, and interrupt us again, so next | |
58 | * time we'll skip this part. */ | |
59 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
60 | ||
61 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
62 | IWL_DEBUG_INFO(priv, | |
63 | "Tx queue %d requesting wakeup," | |
64 | " GP1 = 0x%x\n", txq_id, reg); | |
65 | iwl_legacy_set_bit(priv, CSR_GP_CNTRL, | |
66 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
67 | return; | |
68 | } | |
69 | ||
70 | iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR, | |
71 | txq->q.write_ptr | (txq_id << 8)); | |
72 | ||
73 | /* | |
74 | * else not in power-save mode, | |
75 | * uCode will never sleep when we're | |
76 | * trying to tx (during RFKILL, we're not trying to tx). | |
77 | */ | |
78 | } else | |
79 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
80 | txq->q.write_ptr | (txq_id << 8)); | |
81 | txq->need_update = 0; | |
82 | } | |
83 | EXPORT_SYMBOL(iwl_legacy_txq_update_write_ptr); | |
84 | ||
8a032c13 SG |
85 | /** |
86 | * iwl_legacy_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
87 | */ | |
88 | void iwl_legacy_tx_queue_unmap(struct iwl_priv *priv, int txq_id) | |
89 | { | |
90 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
91 | struct iwl_queue *q = &txq->q; | |
92 | ||
93 | if (q->n_bd == 0) | |
94 | return; | |
95 | ||
96 | while (q->write_ptr != q->read_ptr) { | |
97 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); | |
98 | q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd); | |
99 | } | |
100 | } | |
101 | EXPORT_SYMBOL(iwl_legacy_tx_queue_unmap); | |
102 | ||
be663ab6 WYG |
103 | /** |
104 | * iwl_legacy_tx_queue_free - Deallocate DMA queue. | |
105 | * @txq: Transmit queue to deallocate. | |
106 | * | |
107 | * Empty queue by removing and destroying all BD's. | |
108 | * Free all buffers. | |
109 | * 0-fill, but do not free "txq" descriptor structure. | |
110 | */ | |
111 | void iwl_legacy_tx_queue_free(struct iwl_priv *priv, int txq_id) | |
112 | { | |
113 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
be663ab6 WYG |
114 | struct device *dev = &priv->pci_dev->dev; |
115 | int i; | |
116 | ||
8a032c13 | 117 | iwl_legacy_tx_queue_unmap(priv, txq_id); |
be663ab6 WYG |
118 | |
119 | /* De-alloc array of command/tx buffers */ | |
120 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) | |
121 | kfree(txq->cmd[i]); | |
122 | ||
123 | /* De-alloc circular buffer of TFDs */ | |
124 | if (txq->q.n_bd) | |
125 | dma_free_coherent(dev, priv->hw_params.tfd_size * | |
126 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
127 | ||
128 | /* De-alloc array of per-TFD driver data */ | |
129 | kfree(txq->txb); | |
130 | txq->txb = NULL; | |
131 | ||
132 | /* deallocate arrays */ | |
133 | kfree(txq->cmd); | |
134 | kfree(txq->meta); | |
135 | txq->cmd = NULL; | |
136 | txq->meta = NULL; | |
137 | ||
138 | /* 0-fill queue descriptor structure */ | |
139 | memset(txq, 0, sizeof(*txq)); | |
140 | } | |
141 | EXPORT_SYMBOL(iwl_legacy_tx_queue_free); | |
142 | ||
143 | /** | |
8a032c13 | 144 | * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue |
be663ab6 | 145 | */ |
8a032c13 | 146 | void iwl_legacy_cmd_queue_unmap(struct iwl_priv *priv) |
be663ab6 WYG |
147 | { |
148 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; | |
149 | struct iwl_queue *q = &txq->q; | |
8a032c13 | 150 | int i; |
be663ab6 WYG |
151 | |
152 | if (q->n_bd == 0) | |
153 | return; | |
154 | ||
8a032c13 | 155 | while (q->read_ptr != q->write_ptr) { |
be663ab6 WYG |
156 | i = iwl_legacy_get_cmd_index(q, q->read_ptr, 0); |
157 | ||
81e63263 | 158 | if (txq->meta[i].flags & CMD_MAPPED) { |
8a032c13 SG |
159 | pci_unmap_single(priv->pci_dev, |
160 | dma_unmap_addr(&txq->meta[i], mapping), | |
161 | dma_unmap_len(&txq->meta[i], len), | |
162 | PCI_DMA_BIDIRECTIONAL); | |
81e63263 SG |
163 | txq->meta[i].flags = 0; |
164 | } | |
be663ab6 | 165 | |
8a032c13 | 166 | q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd); |
be663ab6 | 167 | } |
8a032c13 | 168 | |
81e63263 SG |
169 | i = q->n_window; |
170 | if (txq->meta[i].flags & CMD_MAPPED) { | |
be663ab6 WYG |
171 | pci_unmap_single(priv->pci_dev, |
172 | dma_unmap_addr(&txq->meta[i], mapping), | |
173 | dma_unmap_len(&txq->meta[i], len), | |
174 | PCI_DMA_BIDIRECTIONAL); | |
81e63263 | 175 | txq->meta[i].flags = 0; |
be663ab6 | 176 | } |
8a032c13 SG |
177 | } |
178 | EXPORT_SYMBOL(iwl_legacy_cmd_queue_unmap); | |
179 | ||
180 | /** | |
181 | * iwl_legacy_cmd_queue_free - Deallocate DMA queue. | |
182 | * @txq: Transmit queue to deallocate. | |
183 | * | |
184 | * Empty queue by removing and destroying all BD's. | |
185 | * Free all buffers. | |
186 | * 0-fill, but do not free "txq" descriptor structure. | |
187 | */ | |
188 | void iwl_legacy_cmd_queue_free(struct iwl_priv *priv) | |
189 | { | |
190 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; | |
191 | struct device *dev = &priv->pci_dev->dev; | |
192 | int i; | |
193 | ||
194 | iwl_legacy_cmd_queue_unmap(priv); | |
be663ab6 WYG |
195 | |
196 | /* De-alloc array of command/tx buffers */ | |
197 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
198 | kfree(txq->cmd[i]); | |
199 | ||
200 | /* De-alloc circular buffer of TFDs */ | |
201 | if (txq->q.n_bd) | |
202 | dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd, | |
203 | txq->tfds, txq->q.dma_addr); | |
204 | ||
205 | /* deallocate arrays */ | |
206 | kfree(txq->cmd); | |
207 | kfree(txq->meta); | |
208 | txq->cmd = NULL; | |
209 | txq->meta = NULL; | |
210 | ||
211 | /* 0-fill queue descriptor structure */ | |
212 | memset(txq, 0, sizeof(*txq)); | |
213 | } | |
214 | EXPORT_SYMBOL(iwl_legacy_cmd_queue_free); | |
215 | ||
216 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** | |
217 | * DMA services | |
218 | * | |
219 | * Theory of operation | |
220 | * | |
221 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
222 | * of buffer descriptors, each of which points to one or more data buffers for | |
223 | * the device to read from or fill. Driver and device exchange status of each | |
224 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
225 | * entries in each circular buffer, to protect against confusing empty and full | |
226 | * queue states. | |
227 | * | |
228 | * The device reads or writes the data in the queues via the device's several | |
229 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
230 | * | |
231 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
232 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
233 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
234 | * Tx queue resumed. | |
235 | * | |
236 | * See more detailed info in iwl-4965-hw.h. | |
237 | ***************************************************/ | |
238 | ||
239 | int iwl_legacy_queue_space(const struct iwl_queue *q) | |
240 | { | |
241 | int s = q->read_ptr - q->write_ptr; | |
242 | ||
243 | if (q->read_ptr > q->write_ptr) | |
244 | s -= q->n_bd; | |
245 | ||
246 | if (s <= 0) | |
247 | s += q->n_window; | |
248 | /* keep some reserve to not confuse empty and full situations */ | |
249 | s -= 2; | |
250 | if (s < 0) | |
251 | s = 0; | |
252 | return s; | |
253 | } | |
254 | EXPORT_SYMBOL(iwl_legacy_queue_space); | |
255 | ||
256 | ||
257 | /** | |
258 | * iwl_legacy_queue_init - Initialize queue's high/low-water and read/write indexes | |
259 | */ | |
260 | static int iwl_legacy_queue_init(struct iwl_priv *priv, struct iwl_queue *q, | |
261 | int count, int slots_num, u32 id) | |
262 | { | |
263 | q->n_bd = count; | |
264 | q->n_window = slots_num; | |
265 | q->id = id; | |
266 | ||
267 | /* count must be power-of-two size, otherwise iwl_legacy_queue_inc_wrap | |
268 | * and iwl_legacy_queue_dec_wrap are broken. */ | |
269 | BUG_ON(!is_power_of_2(count)); | |
270 | ||
271 | /* slots_num must be power-of-two size, otherwise | |
272 | * iwl_legacy_get_cmd_index is broken. */ | |
273 | BUG_ON(!is_power_of_2(slots_num)); | |
274 | ||
275 | q->low_mark = q->n_window / 4; | |
276 | if (q->low_mark < 4) | |
277 | q->low_mark = 4; | |
278 | ||
279 | q->high_mark = q->n_window / 8; | |
280 | if (q->high_mark < 2) | |
281 | q->high_mark = 2; | |
282 | ||
283 | q->write_ptr = q->read_ptr = 0; | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | /** | |
289 | * iwl_legacy_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
290 | */ | |
291 | static int iwl_legacy_tx_queue_alloc(struct iwl_priv *priv, | |
292 | struct iwl_tx_queue *txq, u32 id) | |
293 | { | |
294 | struct device *dev = &priv->pci_dev->dev; | |
295 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; | |
296 | ||
297 | /* Driver private data, only for Tx (not command) queues, | |
298 | * not shared with device. */ | |
299 | if (id != priv->cmd_queue) { | |
300 | txq->txb = kzalloc(sizeof(txq->txb[0]) * | |
301 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
302 | if (!txq->txb) { | |
303 | IWL_ERR(priv, "kmalloc for auxiliary BD " | |
304 | "structures failed\n"); | |
305 | goto error; | |
306 | } | |
307 | } else { | |
308 | txq->txb = NULL; | |
309 | } | |
310 | ||
311 | /* Circular buffer of transmit frame descriptors (TFDs), | |
312 | * shared with device */ | |
313 | txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, | |
314 | GFP_KERNEL); | |
315 | if (!txq->tfds) { | |
316 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); | |
317 | goto error; | |
318 | } | |
319 | txq->q.id = id; | |
320 | ||
321 | return 0; | |
322 | ||
323 | error: | |
324 | kfree(txq->txb); | |
325 | txq->txb = NULL; | |
326 | ||
327 | return -ENOMEM; | |
328 | } | |
329 | ||
330 | /** | |
331 | * iwl_legacy_tx_queue_init - Allocate and initialize one tx/cmd queue | |
332 | */ | |
333 | int iwl_legacy_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, | |
334 | int slots_num, u32 txq_id) | |
335 | { | |
336 | int i, len; | |
337 | int ret; | |
338 | int actual_slots = slots_num; | |
339 | ||
340 | /* | |
341 | * Alloc buffer array for commands (Tx or other types of commands). | |
342 | * For the command queue (#4/#9), allocate command space + one big | |
343 | * command for scan, since scan command is very huge; the system will | |
344 | * not have two scans at the same time, so only one is needed. | |
345 | * For normal Tx queues (all other queues), no super-size command | |
346 | * space is needed. | |
347 | */ | |
348 | if (txq_id == priv->cmd_queue) | |
349 | actual_slots++; | |
350 | ||
351 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, | |
352 | GFP_KERNEL); | |
353 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, | |
354 | GFP_KERNEL); | |
355 | ||
356 | if (!txq->meta || !txq->cmd) | |
357 | goto out_free_arrays; | |
358 | ||
359 | len = sizeof(struct iwl_device_cmd); | |
360 | for (i = 0; i < actual_slots; i++) { | |
361 | /* only happens for cmd queue */ | |
362 | if (i == slots_num) | |
363 | len = IWL_MAX_CMD_SIZE; | |
364 | ||
365 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); | |
366 | if (!txq->cmd[i]) | |
367 | goto err; | |
368 | } | |
369 | ||
370 | /* Alloc driver data array and TFD circular buffer */ | |
371 | ret = iwl_legacy_tx_queue_alloc(priv, txq, txq_id); | |
372 | if (ret) | |
373 | goto err; | |
374 | ||
375 | txq->need_update = 0; | |
376 | ||
377 | /* | |
378 | * For the default queues 0-3, set up the swq_id | |
379 | * already -- all others need to get one later | |
380 | * (if they need one at all). | |
381 | */ | |
382 | if (txq_id < 4) | |
383 | iwl_legacy_set_swq_id(txq, txq_id, txq_id); | |
384 | ||
385 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
386 | * iwl_legacy_queue_inc_wrap and iwl_legacy_queue_dec_wrap are broken. */ | |
387 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
388 | ||
389 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
390 | iwl_legacy_queue_init(priv, &txq->q, | |
391 | TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
392 | ||
393 | /* Tell device where to find queue */ | |
394 | priv->cfg->ops->lib->txq_init(priv, txq); | |
395 | ||
396 | return 0; | |
397 | err: | |
398 | for (i = 0; i < actual_slots; i++) | |
399 | kfree(txq->cmd[i]); | |
400 | out_free_arrays: | |
401 | kfree(txq->meta); | |
402 | kfree(txq->cmd); | |
403 | ||
404 | return -ENOMEM; | |
405 | } | |
406 | EXPORT_SYMBOL(iwl_legacy_tx_queue_init); | |
407 | ||
408 | void iwl_legacy_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq, | |
409 | int slots_num, u32 txq_id) | |
410 | { | |
411 | int actual_slots = slots_num; | |
412 | ||
413 | if (txq_id == priv->cmd_queue) | |
414 | actual_slots++; | |
415 | ||
416 | memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots); | |
417 | ||
418 | txq->need_update = 0; | |
419 | ||
420 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
421 | iwl_legacy_queue_init(priv, &txq->q, | |
422 | TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
423 | ||
424 | /* Tell device where to find queue */ | |
425 | priv->cfg->ops->lib->txq_init(priv, txq); | |
426 | } | |
427 | EXPORT_SYMBOL(iwl_legacy_tx_queue_reset); | |
428 | ||
429 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
430 | ||
431 | /** | |
432 | * iwl_legacy_enqueue_hcmd - enqueue a uCode command | |
433 | * @priv: device private data point | |
434 | * @cmd: a point to the ucode command structure | |
435 | * | |
436 | * The function returns < 0 values to indicate the operation is | |
437 | * failed. On success, it turns the index (> 0) of command in the | |
438 | * command queue. | |
439 | */ | |
440 | int iwl_legacy_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
441 | { | |
442 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; | |
443 | struct iwl_queue *q = &txq->q; | |
444 | struct iwl_device_cmd *out_cmd; | |
445 | struct iwl_cmd_meta *out_meta; | |
446 | dma_addr_t phys_addr; | |
447 | unsigned long flags; | |
448 | int len; | |
449 | u32 idx; | |
450 | u16 fix_size; | |
451 | ||
452 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
453 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
454 | ||
455 | /* If any of the command structures end up being larger than | |
456 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
457 | * we will need to increase the size of the TFD entries | |
458 | * Also, check to see if command buffer should not exceed the size | |
459 | * of device_cmd and max_cmd_size. */ | |
460 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
461 | !(cmd->flags & CMD_SIZE_HUGE)); | |
462 | BUG_ON(fix_size > IWL_MAX_CMD_SIZE); | |
463 | ||
464 | if (iwl_legacy_is_rfkill(priv) || iwl_legacy_is_ctkill(priv)) { | |
465 | IWL_WARN(priv, "Not sending command - %s KILL\n", | |
466 | iwl_legacy_is_rfkill(priv) ? "RF" : "CT"); | |
467 | return -EIO; | |
468 | } | |
469 | ||
81e63263 SG |
470 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
471 | ||
be663ab6 | 472 | if (iwl_legacy_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
81e63263 SG |
473 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
474 | ||
475 | IWL_ERR(priv, "Restarting adapter due to command queue full\n"); | |
be663ab6 WYG |
476 | queue_work(priv->workqueue, &priv->restart); |
477 | return -ENOSPC; | |
478 | } | |
479 | ||
be663ab6 WYG |
480 | idx = iwl_legacy_get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); |
481 | out_cmd = txq->cmd[idx]; | |
482 | out_meta = &txq->meta[idx]; | |
483 | ||
81e63263 SG |
484 | if (WARN_ON(out_meta->flags & CMD_MAPPED)) { |
485 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
486 | return -ENOSPC; | |
487 | } | |
488 | ||
be663ab6 | 489 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
81e63263 | 490 | out_meta->flags = cmd->flags | CMD_MAPPED; |
be663ab6 WYG |
491 | if (cmd->flags & CMD_WANT_SKB) |
492 | out_meta->source = cmd; | |
493 | if (cmd->flags & CMD_ASYNC) | |
494 | out_meta->callback = cmd->callback; | |
495 | ||
496 | out_cmd->hdr.cmd = cmd->id; | |
497 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
498 | ||
499 | /* At this point, the out_cmd now has all of the incoming cmd | |
500 | * information */ | |
501 | ||
502 | out_cmd->hdr.flags = 0; | |
503 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) | | |
504 | INDEX_TO_SEQ(q->write_ptr)); | |
505 | if (cmd->flags & CMD_SIZE_HUGE) | |
506 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; | |
507 | len = sizeof(struct iwl_device_cmd); | |
508 | if (idx == TFD_CMD_SLOTS) | |
509 | len = IWL_MAX_CMD_SIZE; | |
510 | ||
511 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG | |
512 | switch (out_cmd->hdr.cmd) { | |
513 | case REPLY_TX_LINK_QUALITY_CMD: | |
514 | case SENSITIVITY_CMD: | |
515 | IWL_DEBUG_HC_DUMP(priv, | |
516 | "Sending command %s (#%x), seq: 0x%04X, " | |
517 | "%d bytes at %d[%d]:%d\n", | |
518 | iwl_legacy_get_cmd_string(out_cmd->hdr.cmd), | |
519 | out_cmd->hdr.cmd, | |
520 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
521 | q->write_ptr, idx, priv->cmd_queue); | |
522 | break; | |
523 | default: | |
524 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " | |
525 | "%d bytes at %d[%d]:%d\n", | |
526 | iwl_legacy_get_cmd_string(out_cmd->hdr.cmd), | |
527 | out_cmd->hdr.cmd, | |
528 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
529 | q->write_ptr, idx, priv->cmd_queue); | |
530 | } | |
531 | #endif | |
532 | txq->need_update = 1; | |
533 | ||
534 | if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl) | |
535 | /* Set up entry in queue's byte count circular buffer */ | |
536 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
537 | ||
538 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, | |
539 | fix_size, PCI_DMA_BIDIRECTIONAL); | |
540 | dma_unmap_addr_set(out_meta, mapping, phys_addr); | |
541 | dma_unmap_len_set(out_meta, len, fix_size); | |
542 | ||
543 | trace_iwlwifi_legacy_dev_hcmd(priv, &out_cmd->hdr, | |
544 | fix_size, cmd->flags); | |
545 | ||
546 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, | |
547 | phys_addr, fix_size, 1, | |
548 | U32_PAD(cmd->len)); | |
549 | ||
550 | /* Increment and update queue's write index */ | |
551 | q->write_ptr = iwl_legacy_queue_inc_wrap(q->write_ptr, q->n_bd); | |
552 | iwl_legacy_txq_update_write_ptr(priv, txq); | |
553 | ||
554 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
555 | return idx; | |
556 | } | |
557 | ||
558 | /** | |
559 | * iwl_legacy_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
560 | * | |
561 | * When FW advances 'R' index, all entries between old and new 'R' index | |
562 | * need to be reclaimed. As result, some free space forms. If there is | |
563 | * enough free space (> low mark), wake the stack that feeds us. | |
564 | */ | |
565 | static void iwl_legacy_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, | |
566 | int idx, int cmd_idx) | |
567 | { | |
568 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
569 | struct iwl_queue *q = &txq->q; | |
570 | int nfreed = 0; | |
571 | ||
572 | if ((idx >= q->n_bd) || (iwl_legacy_queue_used(q, idx) == 0)) { | |
573 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " | |
574 | "is out of range [0-%d] %d %d.\n", txq_id, | |
575 | idx, q->n_bd, q->write_ptr, q->read_ptr); | |
576 | return; | |
577 | } | |
578 | ||
579 | for (idx = iwl_legacy_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; | |
580 | q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
581 | ||
582 | if (nfreed++ > 0) { | |
583 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, | |
584 | q->write_ptr, q->read_ptr); | |
585 | queue_work(priv->workqueue, &priv->restart); | |
586 | } | |
587 | ||
588 | } | |
589 | } | |
590 | ||
591 | /** | |
592 | * iwl_legacy_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
593 | * @rxb: Rx buffer to reclaim | |
594 | * | |
595 | * If an Rx buffer has an async callback associated with it the callback | |
596 | * will be executed. The attached skb (if present) will only be freed | |
597 | * if the callback returns 1 | |
598 | */ | |
599 | void | |
600 | iwl_legacy_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
601 | { | |
602 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
603 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
604 | int txq_id = SEQ_TO_QUEUE(sequence); | |
605 | int index = SEQ_TO_INDEX(sequence); | |
606 | int cmd_index; | |
607 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); | |
608 | struct iwl_device_cmd *cmd; | |
609 | struct iwl_cmd_meta *meta; | |
610 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; | |
81e63263 | 611 | unsigned long flags; |
be663ab6 WYG |
612 | |
613 | /* If a Tx command is being handled and it isn't in the actual | |
614 | * command queue then there a command routing bug has been introduced | |
615 | * in the queue management code. */ | |
616 | if (WARN(txq_id != priv->cmd_queue, | |
617 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", | |
618 | txq_id, priv->cmd_queue, sequence, | |
619 | priv->txq[priv->cmd_queue].q.read_ptr, | |
620 | priv->txq[priv->cmd_queue].q.write_ptr)) { | |
621 | iwl_print_hex_error(priv, pkt, 32); | |
622 | return; | |
623 | } | |
624 | ||
be663ab6 WYG |
625 | cmd_index = iwl_legacy_get_cmd_index(&txq->q, index, huge); |
626 | cmd = txq->cmd[cmd_index]; | |
627 | meta = &txq->meta[cmd_index]; | |
628 | ||
2e2a41d6 SG |
629 | txq->time_stamp = jiffies; |
630 | ||
be663ab6 WYG |
631 | pci_unmap_single(priv->pci_dev, |
632 | dma_unmap_addr(meta, mapping), | |
633 | dma_unmap_len(meta, len), | |
634 | PCI_DMA_BIDIRECTIONAL); | |
635 | ||
636 | /* Input error checking is done when commands are added to queue. */ | |
637 | if (meta->flags & CMD_WANT_SKB) { | |
638 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); | |
639 | rxb->page = NULL; | |
640 | } else if (meta->callback) | |
641 | meta->callback(priv, cmd, pkt); | |
642 | ||
81e63263 SG |
643 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
644 | ||
be663ab6 WYG |
645 | iwl_legacy_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
646 | ||
647 | if (!(meta->flags & CMD_ASYNC)) { | |
648 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
649 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", | |
650 | iwl_legacy_get_cmd_string(cmd->hdr.cmd)); | |
65d0f19e | 651 | wake_up(&priv->wait_command_queue); |
be663ab6 | 652 | } |
81e63263 SG |
653 | |
654 | /* Mark as unmapped */ | |
be663ab6 | 655 | meta->flags = 0; |
81e63263 SG |
656 | |
657 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
be663ab6 WYG |
658 | } |
659 | EXPORT_SYMBOL(iwl_legacy_tx_cmd_complete); |