projects / mirror_ubuntu-zesty-kernel.git / blame
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| b481de9c ZY |
1 | /****************************************************************************** |
| 2 | * | |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
| 4 | * redistributing this file, you may do so under either license. | |
| 5 | * | |
| 6 | * GPL LICENSE SUMMARY | |
| 7 | * | |
| 8 | * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 01ebd063 | 11 | * it under the terms of version 2 of the GNU General Public License as |
| b481de9c ZY |
12 | * published by the Free Software Foundation. |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, but | |
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 17 | * General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
| 22 | * USA | |
| 23 | * | |
| 24 | * The full GNU General Public License is included in this distribution | |
| 25 | * in the file called LICENSE.GPL. | |
| 26 | * | |
| 27 | * Contact Information: | |
| 28 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
| 29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 30 | * | |
| 31 | * BSD LICENSE | |
| 32 | * | |
| 33 | * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. | |
| 34 | * All rights reserved. | |
| 35 | * | |
| 36 | * Redistribution and use in source and binary forms, with or without | |
| 37 | * modification, are permitted provided that the following conditions | |
| 38 | * are met: | |
| 39 | * | |
| 40 | * * Redistributions of source code must retain the above copyright | |
| 41 | * notice, this list of conditions and the following disclaimer. | |
| 42 | * * Redistributions in binary form must reproduce the above copyright | |
| 43 | * notice, this list of conditions and the following disclaimer in | |
| 44 | * the documentation and/or other materials provided with the | |
| 45 | * distribution. | |
| 46 | * * Neither the name Intel Corporation nor the names of its | |
| 47 | * contributors may be used to endorse or promote products derived | |
| 48 | * from this software without specific prior written permission. | |
| 49 | * | |
| 50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 61 | * | |
| 62 | *****************************************************************************/ | |
| 63 | ||
| 64 | #ifndef __iwl_3945_hw__ | |
| 65 | #define __iwl_3945_hw__ | |
| 66 | ||
| 5d08cd1d CH |
67 | /* uCode queue management definitions */ |
| 68 | #define IWL_CMD_QUEUE_NUM 4 | |
| 69 | #define IWL_CMD_FIFO_NUM 4 | |
| 70 | #define IWL_BACK_QUEUE_FIRST_ID 7 | |
| 71 | ||
| 72 | /* Tx rates */ | |
| 73 | #define IWL_CCK_RATES 4 | |
| 74 | #define IWL_OFDM_RATES 8 | |
| 75 | ||
| 76 | #define IWL_HT_RATES 0 | |
| 77 | ||
| 78 | #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES) | |
| 79 | ||
| 80 | /* Time constants */ | |
| 81 | #define SHORT_SLOT_TIME 9 | |
| 82 | #define LONG_SLOT_TIME 20 | |
| 83 | ||
| 84 | /* RSSI to dBm */ | |
| 85 | #define IWL_RSSI_OFFSET 95 | |
| 86 | ||
| 87 | /* | |
| 796083cb | 88 | * EEPROM related constants, enums, and structures. |
| 5d08cd1d CH |
89 | */ |
| 90 | ||
| 796083cb BC |
91 | /* |
| 92 | * EEPROM access time values: | |
| 93 | * | |
| 94 | * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG, | |
| 95 | * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit | |
| 96 | * CSR_EEPROM_REG_BIT_CMD (0x2). | |
| 97 | * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). | |
| 98 | * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. | |
| 99 | * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. | |
| 100 | */ | |
| 5d08cd1d CH |
101 | #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ |
| 102 | #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */ | |
| 796083cb | 103 | |
| 5d08cd1d CH |
104 | /* EEPROM field values */ |
| 105 | #define ANTENNA_SWITCH_NORMAL 0 | |
| 106 | #define ANTENNA_SWITCH_INVERSE 1 | |
| 107 | ||
| 796083cb BC |
108 | /* |
| 109 | * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags. | |
| 110 | * | |
| 111 | * IBSS and/or AP operation is allowed *only* on those channels with | |
| 112 | * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because | |
| 113 | * RADAR detection is not supported by the 3945 driver, but is a | |
| 114 | * requirement for establishing a new network for legal operation on channels | |
| 115 | * requiring RADAR detection or restricting ACTIVE scanning. | |
| 116 | * | |
| 117 | * NOTE: "WIDE" flag indicates that 20 MHz channel is supported; | |
| 118 | * 3945 does not support FAT 40 MHz-wide channels. | |
| 119 | * | |
| 120 | * NOTE: Using a channel inappropriately will result in a uCode error! | |
| 121 | */ | |
| 5d08cd1d CH |
122 | enum { |
| 123 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ | |
| 796083cb | 124 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ |
| 5d08cd1d CH |
125 | /* Bit 2 Reserved */ |
| 126 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ | |
| 127 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ | |
| 796083cb BC |
128 | EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ |
| 129 | EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel, not used */ | |
| 5d08cd1d CH |
130 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ |
| 131 | }; | |
| 132 | ||
| 133 | /* EEPROM field lengths */ | |
| 134 | #define EEPROM_BOARD_PBA_NUMBER_LENGTH 11 | |
| 135 | ||
| 136 | /* EEPROM field lengths */ | |
| 137 | #define EEPROM_BOARD_PBA_NUMBER_LENGTH 11 | |
| 138 | #define EEPROM_REGULATORY_SKU_ID_LENGTH 4 | |
| 139 | #define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14 | |
| 140 | #define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13 | |
| 141 | #define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12 | |
| 142 | #define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11 | |
| 143 | #define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6 | |
| 144 | ||
| 145 | #define EEPROM_REGULATORY_CHANNELS_LENGTH ( \ | |
| 146 | EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \ | |
| 147 | EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \ | |
| 148 | EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \ | |
| 149 | EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \ | |
| 150 | EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH) | |
| 151 | ||
| 152 | #define EEPROM_REGULATORY_NUMBER_OF_BANDS 5 | |
| 153 | ||
| 154 | /* SKU Capabilities */ | |
| 155 | #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) | |
| 156 | #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) | |
| 157 | #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) | |
| 158 | ||
| 159 | /* *regulatory* channel data from eeprom, one for each channel */ | |
| bb8c093b | 160 | struct iwl3945_eeprom_channel { |
| 5d08cd1d CH |
161 | u8 flags; /* flags copied from EEPROM */ |
| 162 | s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ | |
| 163 | } __attribute__ ((packed)); | |
| 164 | ||
| 165 | /* | |
| 166 | * Mapping of a Tx power level, at factory calibration temperature, | |
| 167 | * to a radio/DSP gain table index. | |
| 168 | * One for each of 5 "sample" power levels in each band. | |
| 169 | * v_det is measured at the factory, using the 3945's built-in power amplifier | |
| 170 | * (PA) output voltage detector. This same detector is used during Tx of | |
| 171 | * long packets in normal operation to provide feedback as to proper output | |
| 172 | * level. | |
| 173 | * Data copied from EEPROM. | |
| 796083cb | 174 | * DO NOT ALTER THIS STRUCTURE!!! |
| 5d08cd1d | 175 | */ |
| bb8c093b | 176 | struct iwl3945_eeprom_txpower_sample { |
| 5d08cd1d CH |
177 | u8 gain_index; /* index into power (gain) setup table ... */ |
| 178 | s8 power; /* ... for this pwr level for this chnl group */ | |
| 179 | u16 v_det; /* PA output voltage */ | |
| 180 | } __attribute__ ((packed)); | |
| 181 | ||
| 182 | /* | |
| 183 | * Mappings of Tx power levels -> nominal radio/DSP gain table indexes. | |
| 184 | * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). | |
| 185 | * Tx power setup code interpolates between the 5 "sample" power levels | |
| 186 | * to determine the nominal setup for a requested power level. | |
| 187 | * Data copied from EEPROM. | |
| 188 | * DO NOT ALTER THIS STRUCTURE!!! | |
| 189 | */ | |
| bb8c093b | 190 | struct iwl3945_eeprom_txpower_group { |
| 796083cb | 191 | struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ |
| 5d08cd1d CH |
192 | s32 a, b, c, d, e; /* coefficients for voltage->power |
| 193 | * formula (signed) */ | |
| 194 | s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on | |
| 796083cb | 195 | * frequency (signed) */ |
| 5d08cd1d CH |
196 | s8 saturation_power; /* highest power possible by h/w in this |
| 197 | * band */ | |
| 198 | u8 group_channel; /* "representative" channel # in this band */ | |
| 199 | s16 temperature; /* h/w temperature at factory calib this band | |
| 200 | * (signed) */ | |
| 201 | } __attribute__ ((packed)); | |
| 202 | ||
| 203 | /* | |
| 204 | * Temperature-based Tx-power compensation data, not band-specific. | |
| 205 | * These coefficients are use to modify a/b/c/d/e coeffs based on | |
| 206 | * difference between current temperature and factory calib temperature. | |
| 207 | * Data copied from EEPROM. | |
| 208 | */ | |
| bb8c093b | 209 | struct iwl3945_eeprom_temperature_corr { |
| 5d08cd1d CH |
210 | u32 Ta; |
| 211 | u32 Tb; | |
| 212 | u32 Tc; | |
| 213 | u32 Td; | |
| 214 | u32 Te; | |
| 215 | } __attribute__ ((packed)); | |
| 216 | ||
| 796083cb BC |
217 | /* |
| 218 | * EEPROM map | |
| 219 | */ | |
| bb8c093b | 220 | struct iwl3945_eeprom { |
| 5d08cd1d CH |
221 | u8 reserved0[16]; |
| 222 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ | |
| 223 | u16 device_id; /* abs.ofs: 16 */ | |
| 224 | u8 reserved1[2]; | |
| 225 | #define EEPROM_PMC (2*0x0A) /* 2 bytes */ | |
| 226 | u16 pmc; /* abs.ofs: 20 */ | |
| 227 | u8 reserved2[20]; | |
| 228 | #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ | |
| 229 | u8 mac_address[6]; /* abs.ofs: 42 */ | |
| 230 | u8 reserved3[58]; | |
| 231 | #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ | |
| 232 | u16 board_revision; /* abs.ofs: 106 */ | |
| 233 | u8 reserved4[11]; | |
| 234 | #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ | |
| 235 | u8 board_pba_number[9]; /* abs.ofs: 119 */ | |
| 236 | u8 reserved5[8]; | |
| 237 | #define EEPROM_VERSION (2*0x44) /* 2 bytes */ | |
| 238 | u16 version; /* abs.ofs: 136 */ | |
| 239 | #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */ | |
| 240 | u8 sku_cap; /* abs.ofs: 138 */ | |
| 241 | #define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */ | |
| 242 | u8 leds_mode; /* abs.ofs: 139 */ | |
| 243 | #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ | |
| 244 | u16 oem_mode; | |
| 245 | #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */ | |
| 246 | u16 wowlan_mode; /* abs.ofs: 142 */ | |
| 247 | #define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */ | |
| 248 | u16 leds_time_interval; /* abs.ofs: 144 */ | |
| 249 | #define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */ | |
| 250 | u8 leds_off_time; /* abs.ofs: 146 */ | |
| 251 | #define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */ | |
| 252 | u8 leds_on_time; /* abs.ofs: 147 */ | |
| 253 | #define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */ | |
| 254 | u8 almgor_m_version; /* abs.ofs: 148 */ | |
| 255 | #define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */ | |
| 256 | u8 antenna_switch_type; /* abs.ofs: 149 */ | |
| 257 | u8 reserved6[42]; | |
| 258 | #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ | |
| 259 | u8 sku_id[4]; /* abs.ofs: 192 */ | |
| 796083cb BC |
260 | |
| 261 | /* | |
| 262 | * Per-channel regulatory data. | |
| 263 | * | |
| 264 | * Each channel that *might* be supported by 3945 or 4965 has a fixed location | |
| 265 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory | |
| 266 | * txpower (MSB). | |
| 267 | * | |
| 268 | * Entries immediately below are for 20 MHz channel width. FAT (40 MHz) | |
| 269 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. | |
| 270 | * | |
| 271 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
| 272 | */ | |
| 5d08cd1d CH |
273 | #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ |
| 274 | u16 band_1_count; /* abs.ofs: 196 */ | |
| 275 | #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ | |
| 796083cb BC |
276 | struct iwl3945_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */ |
| 277 | ||
| 278 | /* | |
| 279 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, | |
| 280 | * 5.0 GHz channels 7, 8, 11, 12, 16 | |
| 281 | * (4915-5080MHz) (none of these is ever supported) | |
| 282 | */ | |
| 5d08cd1d CH |
283 | #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ |
| 284 | u16 band_2_count; /* abs.ofs: 226 */ | |
| 285 | #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ | |
| 796083cb BC |
286 | struct iwl3945_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ |
| 287 | ||
| 288 | /* | |
| 289 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
| 290 | * (5170-5320MHz) | |
| 291 | */ | |
| 5d08cd1d CH |
292 | #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ |
| 293 | u16 band_3_count; /* abs.ofs: 254 */ | |
| 294 | #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ | |
| 796083cb BC |
295 | struct iwl3945_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ |
| 296 | ||
| 297 | /* | |
| 298 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
| 299 | * (5500-5700MHz) | |
| 300 | */ | |
| 5d08cd1d CH |
301 | #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ |
| 302 | u16 band_4_count; /* abs.ofs: 280 */ | |
| 303 | #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ | |
| 796083cb BC |
304 | struct iwl3945_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ |
| 305 | ||
| 306 | /* | |
| 307 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 | |
| 308 | * (5725-5825MHz) | |
| 309 | */ | |
| 5d08cd1d CH |
310 | #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ |
| 311 | u16 band_5_count; /* abs.ofs: 304 */ | |
| 312 | #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ | |
| 796083cb | 313 | struct iwl3945_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ |
| 5d08cd1d CH |
314 | |
| 315 | u8 reserved9[194]; | |
| 316 | ||
| 796083cb BC |
317 | |
| 318 | /* | |
| 319 | * 3945 Txpower calibration data. | |
| 320 | */ | |
| 5d08cd1d CH |
321 | #define EEPROM_TXPOWER_CALIB_GROUP0 0x200 |
| 322 | #define EEPROM_TXPOWER_CALIB_GROUP1 0x240 | |
| 323 | #define EEPROM_TXPOWER_CALIB_GROUP2 0x280 | |
| 324 | #define EEPROM_TXPOWER_CALIB_GROUP3 0x2c0 | |
| 325 | #define EEPROM_TXPOWER_CALIB_GROUP4 0x300 | |
| 326 | #define IWL_NUM_TX_CALIB_GROUPS 5 | |
| bb8c093b | 327 | struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS]; |
| 5d08cd1d CH |
328 | /* abs.ofs: 512 */ |
| 329 | #define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340 | |
| 796083cb | 330 | struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ |
| 5d08cd1d CH |
331 | u8 reserved16[172]; /* fill out to full 1024 byte block */ |
| 332 | } __attribute__ ((packed)); | |
| 333 | ||
| 334 | #define IWL_EEPROM_IMAGE_SIZE 1024 | |
| 335 | ||
| 796083cb BC |
336 | /* End of EEPROM */ |
| 337 | ||
| 5d08cd1d CH |
338 | |
| 339 | #include "iwl-3945-commands.h" | |
| 340 | ||
| 341 | #define PCI_LINK_CTRL 0x0F0 | |
| 342 | #define PCI_POWER_SOURCE 0x0C8 | |
| 343 | #define PCI_REG_WUM8 0x0E8 | |
| 344 | #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) | |
| 345 | ||
| 346 | /*=== CSR (control and status registers) ===*/ | |
| 347 | #define CSR_BASE (0x000) | |
| 348 | ||
| 349 | #define CSR_SW_VER (CSR_BASE+0x000) | |
| 350 | #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ | |
| 351 | #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ | |
| 352 | #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ | |
| 353 | #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ | |
| 354 | #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ | |
| 355 | #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ | |
| 356 | #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ | |
| 357 | #define CSR_GP_CNTRL (CSR_BASE+0x024) | |
| 358 | #define CSR_HW_REV (CSR_BASE+0x028) | |
| 359 | #define CSR_EEPROM_REG (CSR_BASE+0x02c) | |
| 360 | #define CSR_EEPROM_GP (CSR_BASE+0x030) | |
| 361 | #define CSR_GP_UCODE (CSR_BASE+0x044) | |
| 362 | #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) | |
| 363 | #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) | |
| 364 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) | |
| 365 | #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) | |
| 366 | #define CSR_LED_REG (CSR_BASE+0x094) | |
| 367 | #define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0) | |
| 368 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) | |
| 369 | #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) | |
| 370 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) | |
| 371 | ||
| 372 | /* HW I/F configuration */ | |
| 373 | #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100) | |
| 374 | #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200) | |
| 375 | #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) | |
| 376 | #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) | |
| 377 | #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) | |
| 378 | #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) | |
| 379 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | |
| 380 | ||
| 381 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), | |
| 382 | * acknowledged (reset) by host writing "1" to flagged bits. */ | |
| 383 | #define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */ | |
| 384 | #define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */ | |
| 385 | #define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */ | |
| 386 | #define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ | |
| 387 | #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ | |
| 388 | #define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */ | |
| 389 | #define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ | |
| 390 | #define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ | |
| 391 | #define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */ | |
| 392 | #define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ | |
| 393 | #define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */ | |
| 394 | ||
| 395 | #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ | |
| 396 | CSR_INT_BIT_HW_ERR | \ | |
| 397 | CSR_INT_BIT_FH_TX | \ | |
| 398 | CSR_INT_BIT_SW_ERR | \ | |
| 399 | CSR_INT_BIT_RF_KILL | \ | |
| 400 | CSR_INT_BIT_SW_RX | \ | |
| 401 | CSR_INT_BIT_WAKEUP | \ | |
| 402 | CSR_INT_BIT_ALIVE) | |
| 403 | ||
| 404 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ | |
| 405 | #define CSR_FH_INT_BIT_ERR (1<<31) /* Error */ | |
| 406 | #define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */ | |
| 407 | #define CSR_FH_INT_BIT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */ | |
| 408 | #define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */ | |
| 409 | #define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */ | |
| 410 | #define CSR_FH_INT_BIT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */ | |
| 411 | #define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */ | |
| 412 | #define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */ | |
| 413 | ||
| 414 | #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ | |
| 415 | CSR_FH_INT_BIT_RX_CHNL2 | \ | |
| 416 | CSR_FH_INT_BIT_RX_CHNL1 | \ | |
| 417 | CSR_FH_INT_BIT_RX_CHNL0) | |
| 418 | ||
| 419 | #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \ | |
| 420 | CSR_FH_INT_BIT_TX_CHNL1 | \ | |
| 93a3b607 | 421 | CSR_FH_INT_BIT_TX_CHNL0) |
| 5d08cd1d CH |
422 | |
| 423 | ||
| 424 | /* RESET */ | |
| 425 | #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) | |
| 426 | #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) | |
| 427 | #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) | |
| 428 | #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) | |
| 429 | #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) | |
| 430 | ||
| 431 | /* GP (general purpose) CONTROL */ | |
| 432 | #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) | |
| 433 | #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) | |
| 434 | #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) | |
| 435 | #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) | |
| 436 | ||
| 437 | #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) | |
| 438 | ||
| 439 | #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) | |
| 440 | #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) | |
| 441 | #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) | |
| 442 | ||
| 443 | ||
| 444 | /* EEPROM REG */ | |
| 445 | #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) | |
| 446 | #define CSR_EEPROM_REG_BIT_CMD (0x00000002) | |
| 447 | ||
| 448 | /* EEPROM GP */ | |
| 449 | #define CSR_EEPROM_GP_VALID_MSK (0x00000006) | |
| 450 | #define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000) | |
| 451 | #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) | |
| 452 | ||
| 453 | /* UCODE DRV GP */ | |
| 454 | #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) | |
| 455 | #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) | |
| 456 | #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) | |
| 457 | #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) | |
| 458 | ||
| 459 | /* GPIO */ | |
| 460 | #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) | |
| 461 | #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) | |
| 462 | #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER | |
| 463 | ||
| 464 | /* GI Chicken Bits */ | |
| 465 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) | |
| 466 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) | |
| 467 | ||
| 468 | /* CSR_ANA_PLL_CFG */ | |
| 469 | #define CSR_ANA_PLL_CFG_SH (0x00880300) | |
| 470 | ||
| 471 | #define CSR_LED_REG_TRUN_ON (0x00000078) | |
| 472 | #define CSR_LED_REG_TRUN_OFF (0x00000038) | |
| 473 | #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) | |
| 474 | ||
| 475 | /* DRAM_INT_TBL_CTRL */ | |
| 476 | #define CSR_DRAM_INT_TBL_CTRL_EN (1<<31) | |
| 477 | #define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27) | |
| 478 | ||
| 479 | /*=== HBUS (Host-side Bus) ===*/ | |
| 480 | #define HBUS_BASE (0x400) | |
| 481 | ||
| 482 | #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) | |
| 483 | #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) | |
| 484 | #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) | |
| 485 | #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) | |
| 486 | #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) | |
| 487 | #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) | |
| 488 | #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) | |
| 489 | #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) | |
| 490 | #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) | |
| 491 | ||
| 492 | #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) | |
| 493 | ||
| 494 | ||
| 495 | /* SCD (Scheduler) */ | |
| 496 | #define SCD_BASE (CSR_BASE + 0x2E00) | |
| 497 | ||
| 498 | #define SCD_MODE_REG (SCD_BASE + 0x000) | |
| 499 | #define SCD_ARASTAT_REG (SCD_BASE + 0x004) | |
| 500 | #define SCD_TXFACT_REG (SCD_BASE + 0x010) | |
| 501 | #define SCD_TXF4MF_REG (SCD_BASE + 0x014) | |
| 502 | #define SCD_TXF5MF_REG (SCD_BASE + 0x020) | |
| 503 | #define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C) | |
| 504 | #define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030) | |
| 505 | ||
| 506 | /*=== FH (data Flow Handler) ===*/ | |
| 507 | #define FH_BASE (0x800) | |
| 508 | ||
| 509 | #define FH_CBCC_TABLE (FH_BASE+0x140) | |
| 510 | #define FH_TFDB_TABLE (FH_BASE+0x180) | |
| 511 | #define FH_RCSR_TABLE (FH_BASE+0x400) | |
| 512 | #define FH_RSSR_TABLE (FH_BASE+0x4c0) | |
| 513 | #define FH_TCSR_TABLE (FH_BASE+0x500) | |
| 514 | #define FH_TSSR_TABLE (FH_BASE+0x680) | |
| 515 | ||
| 516 | /* TFDB (Transmit Frame Buffer Descriptor) */ | |
| 517 | #define FH_TFDB(_channel, buf) \ | |
| 518 | (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28) | |
| 519 | #define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \ | |
| 520 | (FH_TFDB_TABLE + 0x50 * _channel) | |
| 521 | /* CBCC _channel is [0,2] */ | |
| 522 | #define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8) | |
| 523 | #define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00) | |
| 524 | #define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04) | |
| 525 | ||
| 526 | /* RCSR _channel is [0,2] */ | |
| 527 | #define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40) | |
| 528 | #define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00) | |
| 529 | #define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04) | |
| 530 | #define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20) | |
| 531 | #define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24) | |
| 532 | ||
| 533 | #define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0)) | |
| 534 | ||
| 535 | /* RSSR */ | |
| 536 | #define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000) | |
| 537 | #define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004) | |
| 538 | /* TCSR */ | |
| 539 | #define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20) | |
| 540 | #define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00) | |
| 541 | #define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04) | |
| 542 | #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08) | |
| 543 | /* TSSR */ | |
| 544 | #define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000) | |
| 545 | #define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008) | |
| 546 | #define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010) | |
| 547 | /* 18 - reserved */ | |
| 548 | ||
| 549 | /* card static random access memory (SRAM) for processor data and instructs */ | |
| 550 | #define RTC_INST_LOWER_BOUND (0x000000) | |
| 551 | #define RTC_DATA_LOWER_BOUND (0x800000) | |
| 552 | ||
| 553 | ||
| 554 | /* DBM */ | |
| 555 | ||
| 556 | #define ALM_FH_SRVC_CHNL (6) | |
| 557 | ||
| 558 | #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) | |
| 559 | #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) | |
| 560 | ||
| 561 | #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) | |
| 562 | ||
| 563 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) | |
| 564 | ||
| 565 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) | |
| 566 | ||
| 567 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) | |
| 568 | ||
| 569 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) | |
| 570 | ||
| 571 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) | |
| 572 | ||
| 573 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) | |
| 574 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) | |
| 575 | ||
| 576 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) | |
| 577 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) | |
| 578 | ||
| 579 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) | |
| 580 | ||
| 581 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) | |
| 582 | ||
| 583 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) | |
| 584 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
| 585 | ||
| 586 | #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) | |
| 587 | ||
| 588 | #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) | |
| 589 | ||
| 590 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) | |
| 591 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) | |
| 592 | ||
| 593 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) | |
| 594 | ||
| 595 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) | |
| 596 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) | |
| 597 | ||
| 598 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) | |
| 599 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) | |
| 600 | ||
| 601 | #define ALM_TB_MAX_BYTES_COUNT (0xFFF0) | |
| 602 | ||
| 603 | #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \ | |
| 604 | ((1LU << _channel) << 24) | |
| 605 | #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \ | |
| 606 | ((1LU << _channel) << 16) | |
| 607 | ||
| 608 | #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \ | |
| 609 | (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \ | |
| 610 | ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel)) | |
| 611 | #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ | |
| 612 | #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ | |
| 613 | ||
| 614 | #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) | |
| 615 | ||
| 616 | #define TFD_QUEUE_MIN 0 | |
| 617 | #define TFD_QUEUE_MAX 6 | |
| 618 | #define TFD_QUEUE_SIZE_MAX (256) | |
| 619 | ||
| 620 | /* spectrum and channel data structures */ | |
| 621 | #define IWL_NUM_SCAN_RATES (2) | |
| 622 | ||
| 623 | #define IWL_SCAN_FLAG_24GHZ (1<<0) | |
| 624 | #define IWL_SCAN_FLAG_52GHZ (1<<1) | |
| 625 | #define IWL_SCAN_FLAG_ACTIVE (1<<2) | |
| 626 | #define IWL_SCAN_FLAG_DIRECT (1<<3) | |
| 627 | ||
| 628 | #define IWL_MAX_CMD_SIZE 1024 | |
| 629 | ||
| 630 | #define IWL_DEFAULT_TX_RETRY 15 | |
| 631 | #define IWL_MAX_TX_RETRY 16 | |
| 632 | ||
| 633 | /*********************************************/ | |
| 634 | ||
| 635 | #define RFD_SIZE 4 | |
| 636 | #define NUM_TFD_CHUNKS 4 | |
| 637 | ||
| 638 | #define RX_QUEUE_SIZE 256 | |
| 639 | #define RX_QUEUE_MASK 255 | |
| 640 | #define RX_QUEUE_SIZE_LOG 8 | |
| 641 | ||
| 642 | /* QoS definitions */ | |
| 643 | ||
| 644 | #define CW_MIN_OFDM 15 | |
| 645 | #define CW_MAX_OFDM 1023 | |
| 646 | #define CW_MIN_CCK 31 | |
| 647 | #define CW_MAX_CCK 1023 | |
| 648 | ||
| 649 | #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM | |
| 650 | #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM | |
| 651 | #define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1) | |
| 652 | #define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1) | |
| 653 | ||
| 654 | #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK | |
| 655 | #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK | |
| 656 | #define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1) | |
| 657 | #define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1) | |
| 658 | ||
| 659 | #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM | |
| 660 | #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM | |
| 661 | #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM | |
| 662 | #define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1) | |
| 663 | ||
| 664 | #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK | |
| 665 | #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK | |
| 666 | #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK | |
| 667 | #define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1) | |
| 668 | ||
| 669 | #define QOS_TX0_AIFS 3 | |
| 670 | #define QOS_TX1_AIFS 7 | |
| 671 | #define QOS_TX2_AIFS 2 | |
| 672 | #define QOS_TX3_AIFS 2 | |
| 673 | ||
| 674 | #define QOS_TX0_ACM 0 | |
| 675 | #define QOS_TX1_ACM 0 | |
| 676 | #define QOS_TX2_ACM 0 | |
| 677 | #define QOS_TX3_ACM 0 | |
| 678 | ||
| 679 | #define QOS_TX0_TXOP_LIMIT_CCK 0 | |
| 680 | #define QOS_TX1_TXOP_LIMIT_CCK 0 | |
| 681 | #define QOS_TX2_TXOP_LIMIT_CCK 6016 | |
| 682 | #define QOS_TX3_TXOP_LIMIT_CCK 3264 | |
| 683 | ||
| 684 | #define QOS_TX0_TXOP_LIMIT_OFDM 0 | |
| 685 | #define QOS_TX1_TXOP_LIMIT_OFDM 0 | |
| 686 | #define QOS_TX2_TXOP_LIMIT_OFDM 3008 | |
| 687 | #define QOS_TX3_TXOP_LIMIT_OFDM 1504 | |
| 688 | ||
| 689 | #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM | |
| 690 | #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM | |
| 691 | #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM | |
| 692 | #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM | |
| 693 | ||
| 694 | #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK | |
| 695 | #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK | |
| 696 | #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK | |
| 697 | #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK | |
| 698 | ||
| 699 | #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM | |
| 700 | #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM | |
| 701 | #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM | |
| 702 | #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM | |
| 703 | ||
| 704 | #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK | |
| 705 | #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK | |
| 706 | #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK | |
| 707 | #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK | |
| 708 | ||
| 709 | #define DEF_TX0_AIFS (2) | |
| 710 | #define DEF_TX1_AIFS (2) | |
| 711 | #define DEF_TX2_AIFS (2) | |
| 712 | #define DEF_TX3_AIFS (2) | |
| 713 | ||
| 714 | #define DEF_TX0_ACM 0 | |
| 715 | #define DEF_TX1_ACM 0 | |
| 716 | #define DEF_TX2_ACM 0 | |
| 717 | #define DEF_TX3_ACM 0 | |
| 718 | ||
| 719 | #define DEF_TX0_TXOP_LIMIT_CCK 0 | |
| 720 | #define DEF_TX1_TXOP_LIMIT_CCK 0 | |
| 721 | #define DEF_TX2_TXOP_LIMIT_CCK 0 | |
| 722 | #define DEF_TX3_TXOP_LIMIT_CCK 0 | |
| 723 | ||
| 724 | #define DEF_TX0_TXOP_LIMIT_OFDM 0 | |
| 725 | #define DEF_TX1_TXOP_LIMIT_OFDM 0 | |
| 726 | #define DEF_TX2_TXOP_LIMIT_OFDM 0 | |
| 727 | #define DEF_TX3_TXOP_LIMIT_OFDM 0 | |
| 728 | ||
| 729 | #define QOS_QOS_SETS 3 | |
| 730 | #define QOS_PARAM_SET_ACTIVE 0 | |
| 731 | #define QOS_PARAM_SET_DEF_CCK 1 | |
| 732 | #define QOS_PARAM_SET_DEF_OFDM 2 | |
| 733 | ||
| 734 | #define CTRL_QOS_NO_ACK (0x0020) | |
| 735 | #define DCT_FLAG_EXT_QOS_ENABLED (0x10) | |
| 736 | ||
| 737 | #define U32_PAD(n) ((4-(n))&0x3) | |
| 738 | ||
| 739 | /* | |
| 740 | * Generic queue structure | |
| 741 | * | |
| 742 | * Contains common data for Rx and Tx queues | |
| 743 | */ | |
| 744 | #define TFD_CTL_COUNT_SET(n) (n<<24) | |
| 745 | #define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7) | |
| 746 | #define TFD_CTL_PAD_SET(n) (n<<28) | |
| 747 | #define TFD_CTL_PAD_GET(ctl) (ctl>>28) | |
| 748 | ||
| 749 | #define TFD_TX_CMD_SLOTS 256 | |
| 750 | #define TFD_CMD_SLOTS 32 | |
| 751 | ||
| bb8c093b CH |
752 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl3945_cmd) - \ |
| 753 | sizeof(struct iwl3945_cmd_meta)) | |
| 5d08cd1d CH |
754 | |
| 755 | /* | |
| 756 | * RX related structures and functions | |
| 757 | */ | |
| 758 | #define RX_FREE_BUFFERS 64 | |
| 759 | #define RX_LOW_WATERMARK 8 | |
| 760 | ||
| 761 | ||
| b481de9c ZY |
762 | #define IWL_RX_BUF_SIZE 3000 |
| 763 | /* card static random access memory (SRAM) for processor data and instructs */ | |
| 764 | #define ALM_RTC_INST_UPPER_BOUND (0x014000) | |
| 765 | #define ALM_RTC_DATA_UPPER_BOUND (0x808000) | |
| 766 | ||
| 767 | #define ALM_RTC_INST_SIZE (ALM_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND) | |
| 768 | #define ALM_RTC_DATA_SIZE (ALM_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND) | |
| 769 | ||
| 770 | #define IWL_MAX_BSM_SIZE ALM_RTC_INST_SIZE | |
| 771 | #define IWL_MAX_INST_SIZE ALM_RTC_INST_SIZE | |
| 772 | #define IWL_MAX_DATA_SIZE ALM_RTC_DATA_SIZE | |
| 773 | #define IWL_MAX_NUM_QUEUES 8 | |
| 774 | ||
| bb8c093b | 775 | static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr) |
| b481de9c ZY |
776 | { |
| 777 | return (addr >= RTC_DATA_LOWER_BOUND) && | |
| 778 | (addr < ALM_RTC_DATA_UPPER_BOUND); | |
| 779 | } | |
| 780 | ||
| bb8c093b CH |
781 | /* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE |
| 782 | * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */ | |
| 783 | struct iwl3945_shared { | |
| b481de9c ZY |
784 | __le32 tx_base_ptr[8]; |
| 785 | __le32 rx_read_ptr[3]; | |
| 786 | } __attribute__ ((packed)); | |
| 787 | ||
| bb8c093b | 788 | struct iwl3945_tfd_frame_data { |
| b481de9c ZY |
789 | __le32 addr; |
| 790 | __le32 len; | |
| 791 | } __attribute__ ((packed)); | |
| 792 | ||
| bb8c093b | 793 | struct iwl3945_tfd_frame { |
| b481de9c | 794 | __le32 control_flags; |
| bb8c093b | 795 | struct iwl3945_tfd_frame_data pa[4]; |
| b481de9c ZY |
796 | u8 reserved[28]; |
| 797 | } __attribute__ ((packed)); | |
| 798 | ||
| bb8c093b | 799 | static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags) |
| b481de9c ZY |
800 | { |
| 801 | return le16_to_cpu(rate_n_flags) & 0xFF; | |
| 802 | } | |
| 803 | ||
| bb8c093b | 804 | static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags) |
| b481de9c ZY |
805 | { |
| 806 | return le16_to_cpu(rate_n_flags); | |
| 807 | } | |
| 808 | ||
| bb8c093b | 809 | static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags) |
| b481de9c ZY |
810 | { |
| 811 | return cpu_to_le16((u16)rate|flags); | |
| 812 | } | |
| 813 | #endif |