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a1175124 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
901069c7 | 5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
a1175124 JB |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/sched.h> | |
617f3d0d | 33 | #include <linux/gfp.h> |
a1175124 JB |
34 | #include <net/mac80211.h> |
35 | ||
36 | #include "iwl-dev.h" | |
37 | #include "iwl-core.h" | |
38 | #include "iwl-agn.h" | |
39 | #include "iwl-helpers.h" | |
40 | ||
41 | #define ICT_COUNT (PAGE_SIZE/sizeof(u32)) | |
42 | ||
43 | /* Free dram table */ | |
44 | void iwl_free_isr_ict(struct iwl_priv *priv) | |
45 | { | |
a4c8b2a6 | 46 | if (priv->_agn.ict_tbl_vir) { |
3599d39a | 47 | dma_free_coherent(priv->bus.dev, |
a1175124 | 48 | (sizeof(u32) * ICT_COUNT) + PAGE_SIZE, |
a4c8b2a6 JB |
49 | priv->_agn.ict_tbl_vir, |
50 | priv->_agn.ict_tbl_dma); | |
51 | priv->_agn.ict_tbl_vir = NULL; | |
34c1b7ba EG |
52 | memset(&priv->_agn.ict_tbl_dma, 0, |
53 | sizeof(priv->_agn.ict_tbl_dma)); | |
54 | memset(&priv->_agn.aligned_ict_tbl_dma, 0, | |
55 | sizeof(priv->_agn.aligned_ict_tbl_dma)); | |
a1175124 JB |
56 | } |
57 | } | |
58 | ||
59 | ||
60 | /* allocate dram shared table it is a PAGE_SIZE aligned | |
61 | * also reset all data related to ICT table interrupt. | |
62 | */ | |
63 | int iwl_alloc_isr_ict(struct iwl_priv *priv) | |
64 | { | |
65 | ||
a1175124 | 66 | /* allocate shrared data table */ |
a4c8b2a6 | 67 | priv->_agn.ict_tbl_vir = |
3599d39a | 68 | dma_alloc_coherent(priv->bus.dev, |
a4c8b2a6 JB |
69 | (sizeof(u32) * ICT_COUNT) + PAGE_SIZE, |
70 | &priv->_agn.ict_tbl_dma, GFP_KERNEL); | |
71 | if (!priv->_agn.ict_tbl_vir) | |
a1175124 JB |
72 | return -ENOMEM; |
73 | ||
25985edc | 74 | /* align table to PAGE_SIZE boundary */ |
a4c8b2a6 | 75 | priv->_agn.aligned_ict_tbl_dma = ALIGN(priv->_agn.ict_tbl_dma, PAGE_SIZE); |
a1175124 JB |
76 | |
77 | IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n", | |
a4c8b2a6 JB |
78 | (unsigned long long)priv->_agn.ict_tbl_dma, |
79 | (unsigned long long)priv->_agn.aligned_ict_tbl_dma, | |
80 | (int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma)); | |
a1175124 | 81 | |
a4c8b2a6 JB |
82 | priv->_agn.ict_tbl = priv->_agn.ict_tbl_vir + |
83 | (priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma); | |
a1175124 JB |
84 | |
85 | IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n", | |
a4c8b2a6 JB |
86 | priv->_agn.ict_tbl, priv->_agn.ict_tbl_vir, |
87 | (int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma)); | |
a1175124 JB |
88 | |
89 | /* reset table and index to all 0 */ | |
a4c8b2a6 JB |
90 | memset(priv->_agn.ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE); |
91 | priv->_agn.ict_index = 0; | |
a1175124 JB |
92 | |
93 | /* add periodic RX interrupt */ | |
94 | priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC; | |
95 | return 0; | |
96 | } | |
97 | ||
98 | /* Device is going up inform it about using ICT interrupt table, | |
99 | * also we need to tell the driver to start using ICT interrupt. | |
100 | */ | |
101 | int iwl_reset_ict(struct iwl_priv *priv) | |
102 | { | |
103 | u32 val; | |
104 | unsigned long flags; | |
105 | ||
a4c8b2a6 | 106 | if (!priv->_agn.ict_tbl_vir) |
a1175124 JB |
107 | return 0; |
108 | ||
109 | spin_lock_irqsave(&priv->lock, flags); | |
110 | iwl_disable_interrupts(priv); | |
111 | ||
a4c8b2a6 | 112 | memset(&priv->_agn.ict_tbl[0], 0, sizeof(u32) * ICT_COUNT); |
a1175124 | 113 | |
a4c8b2a6 | 114 | val = priv->_agn.aligned_ict_tbl_dma >> PAGE_SHIFT; |
a1175124 JB |
115 | |
116 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
117 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
118 | ||
119 | IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X " | |
120 | "aligned dma address %Lx\n", | |
a4c8b2a6 | 121 | val, (unsigned long long)priv->_agn.aligned_ict_tbl_dma); |
a1175124 JB |
122 | |
123 | iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val); | |
a4c8b2a6 JB |
124 | priv->_agn.use_ict = true; |
125 | priv->_agn.ict_index = 0; | |
a1175124 JB |
126 | iwl_write32(priv, CSR_INT, priv->inta_mask); |
127 | iwl_enable_interrupts(priv); | |
128 | spin_unlock_irqrestore(&priv->lock, flags); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | /* Device is going down disable ict interrupt usage */ | |
134 | void iwl_disable_ict(struct iwl_priv *priv) | |
135 | { | |
136 | unsigned long flags; | |
137 | ||
138 | spin_lock_irqsave(&priv->lock, flags); | |
a4c8b2a6 | 139 | priv->_agn.use_ict = false; |
a1175124 JB |
140 | spin_unlock_irqrestore(&priv->lock, flags); |
141 | } | |
142 | ||
143 | static irqreturn_t iwl_isr(int irq, void *data) | |
144 | { | |
145 | struct iwl_priv *priv = data; | |
146 | u32 inta, inta_mask; | |
6e8cc38d | 147 | unsigned long flags; |
a1175124 JB |
148 | #ifdef CONFIG_IWLWIFI_DEBUG |
149 | u32 inta_fh; | |
150 | #endif | |
151 | if (!priv) | |
152 | return IRQ_NONE; | |
153 | ||
6e8cc38d | 154 | spin_lock_irqsave(&priv->lock, flags); |
a1175124 JB |
155 | |
156 | /* Disable (but don't clear!) interrupts here to avoid | |
157 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
158 | * If we have something to service, the tasklet will re-enable ints. | |
159 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
160 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
161 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
162 | ||
163 | /* Discover which interrupts are active/pending */ | |
164 | inta = iwl_read32(priv, CSR_INT); | |
165 | ||
166 | /* Ignore interrupt if there's nothing in NIC to service. | |
167 | * This may be due to IRQ shared with another device, | |
168 | * or due to sporadic interrupts thrown from our NIC. */ | |
169 | if (!inta) { | |
170 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); | |
171 | goto none; | |
172 | } | |
173 | ||
174 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
175 | /* Hardware disappeared. It might have already raised | |
176 | * an interrupt */ | |
177 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); | |
178 | goto unplugged; | |
179 | } | |
180 | ||
181 | #ifdef CONFIG_IWLWIFI_DEBUG | |
182 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { | |
183 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
184 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, " | |
185 | "fh 0x%08x\n", inta, inta_mask, inta_fh); | |
186 | } | |
187 | #endif | |
188 | ||
a4c8b2a6 | 189 | priv->_agn.inta |= inta; |
a1175124 JB |
190 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
191 | if (likely(inta)) | |
192 | tasklet_schedule(&priv->irq_tasklet); | |
a4c8b2a6 | 193 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) |
a1175124 JB |
194 | iwl_enable_interrupts(priv); |
195 | ||
196 | unplugged: | |
6e8cc38d | 197 | spin_unlock_irqrestore(&priv->lock, flags); |
a1175124 JB |
198 | return IRQ_HANDLED; |
199 | ||
200 | none: | |
201 | /* re-enable interrupts here since we don't have anything to service. */ | |
62e45c14 | 202 | /* only Re-enable if disabled by irq and no schedules tasklet. */ |
a4c8b2a6 | 203 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) |
a1175124 JB |
204 | iwl_enable_interrupts(priv); |
205 | ||
6e8cc38d | 206 | spin_unlock_irqrestore(&priv->lock, flags); |
a1175124 JB |
207 | return IRQ_NONE; |
208 | } | |
209 | ||
210 | /* interrupt handler using ict table, with this interrupt driver will | |
211 | * stop using INTA register to get device's interrupt, reading this register | |
212 | * is expensive, device will write interrupts in ICT dram table, increment | |
213 | * index then will fire interrupt to driver, driver will OR all ICT table | |
214 | * entries from current index up to table entry with 0 value. the result is | |
215 | * the interrupt we need to service, driver will set the entries back to 0 and | |
216 | * set index. | |
217 | */ | |
218 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
219 | { | |
220 | struct iwl_priv *priv = data; | |
221 | u32 inta, inta_mask; | |
222 | u32 val = 0; | |
6e8cc38d | 223 | unsigned long flags; |
a1175124 JB |
224 | |
225 | if (!priv) | |
226 | return IRQ_NONE; | |
227 | ||
228 | /* dram interrupt table not set yet, | |
229 | * use legacy interrupt. | |
230 | */ | |
a4c8b2a6 | 231 | if (!priv->_agn.use_ict) |
a1175124 JB |
232 | return iwl_isr(irq, data); |
233 | ||
6e8cc38d | 234 | spin_lock_irqsave(&priv->lock, flags); |
a1175124 JB |
235 | |
236 | /* Disable (but don't clear!) interrupts here to avoid | |
237 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
238 | * If we have something to service, the tasklet will re-enable ints. | |
239 | * If we *don't* have something, we'll re-enable before leaving here. | |
240 | */ | |
241 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
242 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
243 | ||
244 | ||
245 | /* Ignore interrupt if there's nothing in NIC to service. | |
246 | * This may be due to IRQ shared with another device, | |
247 | * or due to sporadic interrupts thrown from our NIC. */ | |
a4c8b2a6 | 248 | if (!priv->_agn.ict_tbl[priv->_agn.ict_index]) { |
a1175124 JB |
249 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); |
250 | goto none; | |
251 | } | |
252 | ||
253 | /* read all entries that not 0 start with ict_index */ | |
a4c8b2a6 | 254 | while (priv->_agn.ict_tbl[priv->_agn.ict_index]) { |
a1175124 | 255 | |
a4c8b2a6 | 256 | val |= le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]); |
a1175124 | 257 | IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n", |
a4c8b2a6 JB |
258 | priv->_agn.ict_index, |
259 | le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index])); | |
260 | priv->_agn.ict_tbl[priv->_agn.ict_index] = 0; | |
261 | priv->_agn.ict_index = iwl_queue_inc_wrap(priv->_agn.ict_index, | |
a1175124 JB |
262 | ICT_COUNT); |
263 | ||
264 | } | |
265 | ||
266 | /* We should not get this value, just ignore it. */ | |
267 | if (val == 0xffffffff) | |
268 | val = 0; | |
269 | ||
270 | /* | |
271 | * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit | |
272 | * (bit 15 before shifting it to 31) to clear when using interrupt | |
273 | * coalescing. fortunately, bits 18 and 19 stay set when this happens | |
274 | * so we use them to decide on the real state of the Rx bit. | |
275 | * In order words, bit 15 is set if bit 18 or bit 19 are set. | |
276 | */ | |
277 | if (val & 0xC0000) | |
278 | val |= 0x8000; | |
279 | ||
280 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
281 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", | |
282 | inta, inta_mask, val); | |
283 | ||
284 | inta &= priv->inta_mask; | |
a4c8b2a6 | 285 | priv->_agn.inta |= inta; |
a1175124 JB |
286 | |
287 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
288 | if (likely(inta)) | |
289 | tasklet_schedule(&priv->irq_tasklet); | |
a4c8b2a6 | 290 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) { |
a1175124 JB |
291 | /* Allow interrupt if was disabled by this handler and |
292 | * no tasklet was schedules, We should not enable interrupt, | |
293 | * tasklet will enable it. | |
294 | */ | |
295 | iwl_enable_interrupts(priv); | |
296 | } | |
297 | ||
6e8cc38d | 298 | spin_unlock_irqrestore(&priv->lock, flags); |
a1175124 JB |
299 | return IRQ_HANDLED; |
300 | ||
301 | none: | |
302 | /* re-enable interrupts here since we don't have anything to service. | |
303 | * only Re-enable if disabled by irq. | |
304 | */ | |
a4c8b2a6 | 305 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) |
a1175124 JB |
306 | iwl_enable_interrupts(priv); |
307 | ||
6e8cc38d | 308 | spin_unlock_irqrestore(&priv->lock, flags); |
a1175124 JB |
309 | return IRQ_NONE; |
310 | } |