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iwlagn: set dynamic aggregation threshold for BT
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
CommitLineData
e04ed0a5
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
8d801080 29#include <linux/etherdevice.h>
e04ed0a5
WYG		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/sched.h>
34
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-io.h"
38#include "iwl-helpers.h"
39#include "iwl-agn-hw.h"
40#include "iwl-agn.h"
1fa61b2e 41#include "iwl-sta.h"
e04ed0a5 42
898dade1 43static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
e04ed0a5
WYG		 44{
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47}
48
91835ba4
WYG		 49static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50{
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
1d270075 114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
91835ba4
WYG		 115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
1d270075 117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
91835ba4
WYG		 118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124}
125
814665fe
WYG		 126static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127{
128 status &= AGG_TX_STATUS_MSK;
129
130 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
133 break;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
136 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
139 break;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
142 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
154 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157 break;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
160 break;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
163 break;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
166 break;
167 default:
168 priv->_agn.reply_agg_tx_stats.unknown++;
169 break;
170 }
171}
172
743e015d
WYG		 173static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
898dade1 175 struct iwlagn_tx_resp *tx_resp,
743e015d
WYG		 176 int txq_id, bool is_agg)
177{
178 u16 status = le16_to_cpu(tx_resp->status.status);
179
180 info->status.rates[0].count = tx_resp->failure_frame + 1;
181 if (is_agg)
182 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
183 info->flags |= iwl_tx_status_to_mac80211(status);
184 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
185 info);
91835ba4
WYG		 186 if (!iwl_is_tx_success(status))
187 iwlagn_count_tx_err_status(priv, status);
743e015d
WYG		 188
189 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
190 "0x%x retries %d\n",
191 txq_id,
192 iwl_get_tx_fail_reason(status), status,
193 le32_to_cpu(tx_resp->rate_n_flags),
194 tx_resp->failure_frame);
195}
196
e1b3fa0c
WYG		 197#ifdef CONFIG_IWLWIFI_DEBUG
198#define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
199
200const char *iwl_get_agg_tx_fail_reason(u16 status)
201{
202 status &= AGG_TX_STATUS_MSK;
203 switch (status) {
204 case AGG_TX_STATE_TRANSMITTED:
205 return "SUCCESS";
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
209 AGG_TX_STATE_FAIL(ABORT_MSK);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
218 }
219
220 return "UNKNOWN";
221}
222#endif /* CONFIG_IWLWIFI_DEBUG */
223
e04ed0a5
WYG		 224static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
225 struct iwl_ht_agg *agg,
898dade1 226 struct iwlagn_tx_resp *tx_resp,
e04ed0a5
WYG		 227 int txq_id, u16 start_idx)
228{
229 u16 status;
230 struct agg_tx_status *frame_status = &tx_resp->status;
e04ed0a5 231 struct ieee80211_hdr *hdr = NULL;
e04ed0a5
WYG		 232 int i, sh, idx;
233 u16 seq;
234
235 if (agg->wait_for_ba)
236 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
237
238 agg->frame_count = tx_resp->frame_count;
239 agg->start_idx = start_idx;
743e015d 240 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
e04ed0a5
WYG		 241 agg->bitmap = 0;
242
243 /* # frames attempted by Tx command */
244 if (agg->frame_count == 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
e04ed0a5
WYG		 246 idx = start_idx;
247
e04ed0a5
WYG		 248 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg->frame_count, agg->start_idx, idx);
743e015d
WYG		 250 iwlagn_set_tx_status(priv,
251 IEEE80211_SKB_CB(
252 priv->txq[txq_id].txb[idx].skb),
253 tx_resp, txq_id, true);
e04ed0a5
WYG		 254 agg->wait_for_ba = 0;
255 } else {
256 /* Two or more frames were attempted; expect block-ack */
257 u64 bitmap = 0;
f668da2f
DH		 258
259 /*
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
263 */
e04ed0a5
WYG		 264 int start = agg->start_idx;
265
266 /* Construct bit-map of pending frames within Tx window */
267 for (i = 0; i < agg->frame_count; i++) {
268 u16 sc;
269 status = le16_to_cpu(frame_status[i].status);
270 seq = le16_to_cpu(frame_status[i].sequence);
271 idx = SEQ_TO_INDEX(seq);
272 txq_id = SEQ_TO_QUEUE(seq);
273
814665fe
WYG		 274 if (status & AGG_TX_STATUS_MSK)
275 iwlagn_count_agg_tx_err_status(priv, status);
276
e04ed0a5
WYG		 277 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
278 AGG_TX_STATE_ABORT_MSK))
279 continue;
280
281 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg->frame_count, txq_id, idx);
e1b3fa0c
WYG		 283 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status),
286 status & AGG_TX_STATUS_MSK,
287 status & AGG_TX_TRY_MSK);
e04ed0a5
WYG		 288
289 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
290 if (!hdr) {
291 IWL_ERR(priv,
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx, txq_id);
294 return -1;
295 }
296
297 sc = le16_to_cpu(hdr->seq_ctrl);
298 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
299 IWL_ERR(priv,
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
302 idx, SEQ_TO_SN(sc),
303 hdr->seq_ctrl);
304 return -1;
305 }
306
307 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
308 i, idx, SEQ_TO_SN(sc));
309
f668da2f
DH		 310 /*
311 * sh -> how many frames ahead of the starting frame is
312 * the current one?
313 *
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
318 */
e04ed0a5 319 sh = idx - start;
f668da2f
DH		 320
321 /*
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
326 */
327 if (sh >= 64) {
328 /* Shift bitmap by start - idx, wrapped */
329 sh = 0x100 - idx + start;
e04ed0a5 330 bitmap = bitmap << sh;
f668da2f 331 /* Now idx is the new start so sh = 0 */
e04ed0a5
WYG		 332 sh = 0;
333 start = idx;
f668da2f
DH		 334 /*
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
337 */
338 } else if (sh <= -64) {
339 sh = 0x100 - start + idx;
340 /*
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
343 */
344 } else if (sh < 0) {
345 /* Shift by how far start is ahead of idx */
e04ed0a5 346 sh = start - idx;
e04ed0a5 347 bitmap = bitmap << sh;
f668da2f
DH		 348 /* Now idx is the new start so sh = 0 */
349 start = idx;
e04ed0a5
WYG		 350 sh = 0;
351 }
f668da2f 352 /* Sequence number start + sh was sent in this batch */
e04ed0a5
WYG		 353 bitmap |= 1ULL << sh;
354 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
355 start, (unsigned long long)bitmap);
356 }
357
f668da2f
DH		 358 /*
359 * Store the bitmap and possibly the new start, if we wrapped
360 * the buffer above
361 */
e04ed0a5
WYG		 362 agg->bitmap = bitmap;
363 agg->start_idx = start;
364 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg->frame_count, agg->start_idx,
366 (unsigned long long)agg->bitmap);
367
368 if (bitmap)
369 agg->wait_for_ba = 1;
370 }
371 return 0;
372}
373
04569cbe
WYG		 374void iwl_check_abort_status(struct iwl_priv *priv,
375 u8 frame_count, u32 status)
376{
377 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
65550636
WYG		 378 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
380 queue_work(priv->workqueue, &priv->tx_flush);
04569cbe
WYG		 381 }
382}
383
e04ed0a5
WYG		 384static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
385 struct iwl_rx_mem_buffer *rxb)
386{
387 struct iwl_rx_packet *pkt = rxb_addr(rxb);
388 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
389 int txq_id = SEQ_TO_QUEUE(sequence);
390 int index = SEQ_TO_INDEX(sequence);
391 struct iwl_tx_queue *txq = &priv->txq[txq_id];
392 struct ieee80211_tx_info *info;
898dade1 393 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
e04ed0a5
WYG		 394 u32 status = le16_to_cpu(tx_resp->status.status);
395 int tid;
396 int sta_id;
397 int freed;
9c5ac091 398 unsigned long flags;
e04ed0a5
WYG		 399
400 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
401 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id,
403 index, txq->q.n_bd, txq->q.write_ptr,
404 txq->q.read_ptr);
405 return;
406 }
407
ff0d91c3 408 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
e04ed0a5
WYG		 409 memset(&info->status, 0, sizeof(info->status));
410
898dade1
WYG		 411 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
412 IWLAGN_TX_RES_TID_POS;
413 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
414 IWLAGN_TX_RES_RA_POS;
e04ed0a5 415
9c5ac091 416 spin_lock_irqsave(&priv->sta_lock, flags);
e04ed0a5
WYG		 417 if (txq->sched_retry) {
418 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
9c5ac091 419 struct iwl_ht_agg *agg;
e04ed0a5
WYG		 420
421 agg = &priv->stations[sta_id].tid[tid].agg;
c6c996b5
WYG		 422 /*
423 * If the BT kill count is non-zero, we'll get this
424 * notification again.
425 */
426 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
7cb1b088
WYG		 427 priv->cfg->bt_params &&
428 priv->cfg->bt_params->advanced_bt_coexist) {
c6c996b5
WYG		 429 IWL_WARN(priv, "receive reply tx with bt_kill\n");
430 }
e04ed0a5
WYG		 431 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
432
433 /* check if BAR is needed */
434 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
435 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
436
437 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
438 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
439 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
440 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
441 scd_ssn , index, txq_id, txq->swq_id);
442
74bcdb33 443 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
e04ed0a5
WYG		 444 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
445
446 if (priv->mac80211_registered &&
447 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
448 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
449 if (agg->state == IWL_AGG_OFF)
450 iwl_wake_queue(priv, txq_id);
451 else
452 iwl_wake_queue(priv, txq->swq_id);
453 }
454 }
455 } else {
456 BUG_ON(txq_id != txq->swq_id);
743e015d 457 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
74bcdb33 458 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
e04ed0a5
WYG		 459 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
460
461 if (priv->mac80211_registered &&
462 (iwl_queue_space(&txq->q) > txq->q.low_mark))
463 iwl_wake_queue(priv, txq_id);
464 }
465
74bcdb33 466 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
e04ed0a5 467
04569cbe 468 iwl_check_abort_status(priv, tx_resp->frame_count, status);
9c5ac091 469 spin_unlock_irqrestore(&priv->sta_lock, flags);
e04ed0a5
WYG		 470}
471
472void iwlagn_rx_handler_setup(struct iwl_priv *priv)
473{
474 /* init calibration handlers */
475 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
476 iwlagn_rx_calib_result;
477 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
478 iwlagn_rx_calib_complete;
479 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
480}
481
482void iwlagn_setup_deferred_work(struct iwl_priv *priv)
483{
484 /* in agn, the tx power calibration is done in uCode */
485 priv->disable_tx_power_cal = 1;
486}
487
488int iwlagn_hw_valid_rtc_data_addr(u32 addr)
489{
490 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
491 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
492}
493
494int iwlagn_send_tx_power(struct iwl_priv *priv)
495{
ab63c68a 496 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
e04ed0a5
WYG		 497 u8 tx_ant_cfg_cmd;
498
4beeba7d
SG		 499 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
500 "TX Power requested while scanning!\n"))
501 return -EAGAIN;
502
e04ed0a5
WYG		 503 /* half dBm need to multiply */
504 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
505
506 if (priv->tx_power_lmt_in_half_dbm &&
507 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
508 /*
509 * For the newer devices which using enhanced/extend tx power
510 * table in EEPROM, the format is in half dBm. driver need to
511 * convert to dBm format before report to mac80211.
512 * By doing so, there is a possibility of 1/2 dBm resolution
513 * lost. driver will perform "round-up" operation before
514 * reporting, but it will cause 1/2 dBm tx power over the
515 * regulatory limit. Perform the checking here, if the
516 * "tx_power_user_lmt" is higher than EEPROM value (in
517 * half-dBm format), lower the tx power based on EEPROM
518 */
519 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
520 }
ab63c68a
WYG		 521 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
522 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
e04ed0a5
WYG		 523
524 if (IWL_UCODE_API(priv->ucode_ver) == 1)
525 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
526 else
527 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
528
4cbf1b12
SG		 529 return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
530 &tx_power_cmd);
e04ed0a5
WYG		 531}
532
533void iwlagn_temperature(struct iwl_priv *priv)
534{
535 /* store temperature from statistics (in Celsius) */
f3aebeee 536 priv->temperature =
325322ee 537 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
e04ed0a5
WYG		 538 iwl_tt_handler(priv);
539}
540
541u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
542{
543 struct iwl_eeprom_calib_hdr {
544 u8 version;
545 u8 pa_type;
546 u16 voltage;
547 } *hdr;
548
549 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
7944f8e4 550 EEPROM_CALIB_ALL);
e04ed0a5
WYG		 551 return hdr->version;
552
553}
554
555/*
556 * EEPROM
557 */
558static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
559{
560 u16 offset = 0;
561
562 if ((address & INDIRECT_ADDRESS) == 0)
563 return address;
564
565 switch (address & INDIRECT_TYPE_MSK) {
566 case INDIRECT_HOST:
7944f8e4 567 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
e04ed0a5
WYG		 568 break;
569 case INDIRECT_GENERAL:
7944f8e4 570 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
e04ed0a5
WYG		 571 break;
572 case INDIRECT_REGULATORY:
7944f8e4 573 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
e04ed0a5
WYG		 574 break;
575 case INDIRECT_CALIBRATION:
7944f8e4 576 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
e04ed0a5
WYG		 577 break;
578 case INDIRECT_PROCESS_ADJST:
7944f8e4 579 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
e04ed0a5
WYG		 580 break;
581 case INDIRECT_OTHERS:
7944f8e4 582 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
e04ed0a5
WYG		 583 break;
584 default:
585 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
586 address & INDIRECT_TYPE_MSK);
587 break;
588 }
589
590 /* translate the offset from words to byte */
591 return (address & ADDRESS_MSK) + (offset << 1);
592}
593
594const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
595 size_t offset)
596{
597 u32 address = eeprom_indirect_address(priv, offset);
7cb1b088 598 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
e04ed0a5
WYG		 599 return &priv->eeprom[address];
600}
348ee7cd
WYG		 601
602struct iwl_mod_params iwlagn_mod_params = {
603 .amsdu_size_8K = 1,
604 .restart_fw = 1,
605 /* the rest are 0 by default */
606};
74bcdb33
WYG		 607
608void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
609{
610 unsigned long flags;
611 int i;
612 spin_lock_irqsave(&rxq->lock, flags);
613 INIT_LIST_HEAD(&rxq->rx_free);
614 INIT_LIST_HEAD(&rxq->rx_used);
615 /* Fill the rx_used queue with _all_ of the Rx buffers */
616 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
617 /* In the reset function, these buffers may have been allocated
618 * to an SKB, so we need to unmap and free potential storage */
619 if (rxq->pool[i].page != NULL) {
620 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
621 PAGE_SIZE << priv->hw_params.rx_page_order,
622 PCI_DMA_FROMDEVICE);
623 __iwl_free_pages(priv, rxq->pool[i].page);
624 rxq->pool[i].page = NULL;
625 }
626 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
627 }
628
6aac74b4
ZY		 629 for (i = 0; i < RX_QUEUE_SIZE; i++)
630 rxq->queue[i] = NULL;
631
74bcdb33
WYG		 632 /* Set us so that we have processed and used all buffers, but have
633 * not restocked the Rx queue with fresh buffers */
634 rxq->read = rxq->write = 0;
635 rxq->write_actual = 0;
636 rxq->free_count = 0;
637 spin_unlock_irqrestore(&rxq->lock, flags);
638}
639
640int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
641{
642 u32 rb_size;
643 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
644 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
645
7cb1b088 646 if (!priv->cfg->base_params->use_isr_legacy)
74bcdb33
WYG		 647 rb_timeout = RX_RB_TIMEOUT;
648
649 if (priv->cfg->mod_params->amsdu_size_8K)
650 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
651 else
652 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
653
654 /* Stop Rx DMA */
655 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
656
657 /* Reset driver's Rx queue write index */
658 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
659
660 /* Tell device where to find RBD circular buffer in DRAM */
661 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
d5b25c90 662 (u32)(rxq->bd_dma >> 8));
74bcdb33
WYG		 663
664 /* Tell device where in DRAM to update its Rx status */
665 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
666 rxq->rb_stts_dma >> 4);
667
668 /* Enable Rx DMA
669 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
670 * the credit mechanism in 5000 HW RX FIFO
671 * Direct rx interrupts to hosts
672 * Rx buffer size 4 or 8k
673 * RB timeout 0x10
674 * 256 RBDs
675 */
676 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
677 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
678 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
679 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
680 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
681 rb_size|
682 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
683 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
684
685 /* Set interrupt coalescing timer to default (2048 usecs) */
686 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
687
688 return 0;
689}
690
9597ebac
JB		 691static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
692{
693/*
694 * (for documentation purposes)
695 * to set power to V_AUX, do:
696
697 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
698 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
699 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
700 ~APMG_PS_CTRL_MSK_PWR_SRC);
701 */
702
703 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
704 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
705 ~APMG_PS_CTRL_MSK_PWR_SRC);
706}
707
74bcdb33
WYG		 708int iwlagn_hw_nic_init(struct iwl_priv *priv)
709{
710 unsigned long flags;
711 struct iwl_rx_queue *rxq = &priv->rxq;
712 int ret;
713
714 /* nic_init */
715 spin_lock_irqsave(&priv->lock, flags);
716 priv->cfg->ops->lib->apm_ops.init(priv);
717
718 /* Set interrupt coalescing calibration timer to default (512 usecs) */
719 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
720
721 spin_unlock_irqrestore(&priv->lock, flags);
722
9597ebac 723 iwlagn_set_pwr_vmain(priv);
74bcdb33
WYG		 724
725 priv->cfg->ops->lib->apm_ops.config(priv);
726
727 /* Allocate the RX queue, or reset if it is already allocated */
728 if (!rxq->bd) {
729 ret = iwl_rx_queue_alloc(priv);
730 if (ret) {
731 IWL_ERR(priv, "Unable to initialize Rx queue\n");
732 return -ENOMEM;
733 }
734 } else
735 iwlagn_rx_queue_reset(priv, rxq);
736
54b81550 737 iwlagn_rx_replenish(priv);
74bcdb33
WYG		 738
739 iwlagn_rx_init(priv, rxq);
740
741 spin_lock_irqsave(&priv->lock, flags);
742
743 rxq->need_update = 1;
744 iwl_rx_queue_update_write_ptr(priv, rxq);
745
746 spin_unlock_irqrestore(&priv->lock, flags);
747
470058e0
ZY		 748 /* Allocate or reset and init all Tx and Command queues */
749 if (!priv->txq) {
750 ret = iwlagn_txq_ctx_alloc(priv);
751 if (ret)
752 return ret;
753 } else
754 iwlagn_txq_ctx_reset(priv);
74bcdb33 755
f81c1f48
WYG		 756 if (priv->cfg->base_params->shadow_reg_enable) {
757 /* enable shadow regs in HW */
758 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
759 0x800FFFFF);
760 }
761
74bcdb33
WYG		 762 set_bit(STATUS_INIT, &priv->status);
763
764 return 0;
765}
54b81550
WYG		 766
767/**
768 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
769 */
770static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
771 dma_addr_t dma_addr)
772{
773 return cpu_to_le32((u32)(dma_addr >> 8));
774}
775
776/**
777 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
778 *
779 * If there are slots in the RX queue that need to be restocked,
780 * and we have free pre-allocated buffers, fill the ranks as much
781 * as we can, pulling from rx_free.
782 *
783 * This moves the 'write' index forward to catch up with 'processed', and
784 * also updates the memory address in the firmware to reference the new
785 * target buffer.
786 */
787void iwlagn_rx_queue_restock(struct iwl_priv *priv)
788{
789 struct iwl_rx_queue *rxq = &priv->rxq;
790 struct list_head *element;
791 struct iwl_rx_mem_buffer *rxb;
792 unsigned long flags;
54b81550
WYG		 793
794 spin_lock_irqsave(&rxq->lock, flags);
54b81550 795 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6aac74b4
ZY		 796 /* The overwritten rxb must be a used one */
797 rxb = rxq->queue[rxq->write];
798 BUG_ON(rxb && rxb->page);
799
54b81550
WYG		 800 /* Get next free Rx buffer, remove from free list */
801 element = rxq->rx_free.next;
802 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
803 list_del(element);
804
805 /* Point to Rx buffer via next RBD in circular buffer */
806 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
807 rxb->page_dma);
808 rxq->queue[rxq->write] = rxb;
809 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
810 rxq->free_count--;
811 }
812 spin_unlock_irqrestore(&rxq->lock, flags);
813 /* If the pre-allocated buffer pool is dropping low, schedule to
814 * refill it */
815 if (rxq->free_count <= RX_LOW_WATERMARK)
816 queue_work(priv->workqueue, &priv->rx_replenish);
817
818
819 /* If we've added more space for the firmware to place data, tell it.
820 * Increment device's write pointer in multiples of 8. */
821 if (rxq->write_actual != (rxq->write & ~0x7)) {
822 spin_lock_irqsave(&rxq->lock, flags);
823 rxq->need_update = 1;
824 spin_unlock_irqrestore(&rxq->lock, flags);
825 iwl_rx_queue_update_write_ptr(priv, rxq);
826 }
827}
828
829/**
830 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
831 *
832 * When moving to rx_free an SKB is allocated for the slot.
833 *
834 * Also restock the Rx queue via iwl_rx_queue_restock.
835 * This is called as a scheduled work item (except for during initialization)
836 */
837void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
838{
839 struct iwl_rx_queue *rxq = &priv->rxq;
840 struct list_head *element;
841 struct iwl_rx_mem_buffer *rxb;
842 struct page *page;
843 unsigned long flags;
844 gfp_t gfp_mask = priority;
845
846 while (1) {
847 spin_lock_irqsave(&rxq->lock, flags);
848 if (list_empty(&rxq->rx_used)) {
849 spin_unlock_irqrestore(&rxq->lock, flags);
850 return;
851 }
852 spin_unlock_irqrestore(&rxq->lock, flags);
853
854 if (rxq->free_count > RX_LOW_WATERMARK)
855 gfp_mask |= __GFP_NOWARN;
856
857 if (priv->hw_params.rx_page_order > 0)
858 gfp_mask |= __GFP_COMP;
859
860 /* Alloc a new receive buffer */
861 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
862 if (!page) {
863 if (net_ratelimit())
864 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
865 "order: %d\n",
866 priv->hw_params.rx_page_order);
867
868 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
869 net_ratelimit())
870 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
871 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
872 rxq->free_count);
873 /* We don't reschedule replenish work here -- we will
874 * call the restock method and if it still needs
875 * more buffers it will schedule replenish */
876 return;
877 }
878
879 spin_lock_irqsave(&rxq->lock, flags);
880
881 if (list_empty(&rxq->rx_used)) {
882 spin_unlock_irqrestore(&rxq->lock, flags);
883 __free_pages(page, priv->hw_params.rx_page_order);
884 return;
885 }
886 element = rxq->rx_used.next;
887 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
888 list_del(element);
889
890 spin_unlock_irqrestore(&rxq->lock, flags);
891
6aac74b4 892 BUG_ON(rxb->page);
54b81550
WYG		 893 rxb->page = page;
894 /* Get physical address of the RB */
895 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
896 PAGE_SIZE << priv->hw_params.rx_page_order,
897 PCI_DMA_FROMDEVICE);
898 /* dma address must be no more than 36 bits */
899 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
900 /* and also 256 byte aligned! */
901 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
902
903 spin_lock_irqsave(&rxq->lock, flags);
904
905 list_add_tail(&rxb->list, &rxq->rx_free);
906 rxq->free_count++;
907 priv->alloc_rxb_page++;
908
909 spin_unlock_irqrestore(&rxq->lock, flags);
910 }
911}
912
913void iwlagn_rx_replenish(struct iwl_priv *priv)
914{
915 unsigned long flags;
916
917 iwlagn_rx_allocate(priv, GFP_KERNEL);
918
919 spin_lock_irqsave(&priv->lock, flags);
920 iwlagn_rx_queue_restock(priv);
921 spin_unlock_irqrestore(&priv->lock, flags);
922}
923
924void iwlagn_rx_replenish_now(struct iwl_priv *priv)
925{
926 iwlagn_rx_allocate(priv, GFP_ATOMIC);
927
928 iwlagn_rx_queue_restock(priv);
929}
930
931/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
932 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
933 * This free routine walks the list of POOL entries and if SKB is set to
934 * non NULL it is unmapped and freed
935 */
936void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
937{
938 int i;
939 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
940 if (rxq->pool[i].page != NULL) {
941 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
942 PAGE_SIZE << priv->hw_params.rx_page_order,
943 PCI_DMA_FROMDEVICE);
944 __iwl_free_pages(priv, rxq->pool[i].page);
945 rxq->pool[i].page = NULL;
946 }
947 }
948
949 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
d5b25c90 950 rxq->bd_dma);
54b81550
WYG		 951 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
952 rxq->rb_stts, rxq->rb_stts_dma);
953 rxq->bd = NULL;
954 rxq->rb_stts = NULL;
955}
956
957int iwlagn_rxq_stop(struct iwl_priv *priv)
958{
959
960 /* stop Rx DMA */
961 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
962 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
963 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
964
965 return 0;
966}
8d801080
WYG		 967
968int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
969{
970 int idx = 0;
971 int band_offset = 0;
972
973 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
974 if (rate_n_flags & RATE_MCS_HT_MSK) {
975 idx = (rate_n_flags & 0xff);
976 return idx;
977 /* Legacy rate format, search for match in table */
978 } else {
979 if (band == IEEE80211_BAND_5GHZ)
980 band_offset = IWL_FIRST_OFDM_RATE;
981 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
982 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
983 return idx - band_offset;
984 }
985
986 return -1;
987}
988
989/* Calc max signal level (dBm) among 3 possible receivers */
990static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
991 struct iwl_rx_phy_res *rx_resp)
992{
993 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
994}
995
8d801080
WYG		 996static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
997{
998 u32 decrypt_out = 0;
999
1000 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
1001 RX_RES_STATUS_STATION_FOUND)
1002 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
1003 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
1004
1005 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
1006
1007 /* packet was not encrypted */
1008 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1009 RX_RES_STATUS_SEC_TYPE_NONE)
1010 return decrypt_out;
1011
1012 /* packet was encrypted with unknown alg */
1013 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1014 RX_RES_STATUS_SEC_TYPE_ERR)
1015 return decrypt_out;
1016
1017 /* decryption was not done in HW */
1018 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
1019 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
1020 return decrypt_out;
1021
1022 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
1023
1024 case RX_RES_STATUS_SEC_TYPE_CCMP:
1025 /* alg is CCM: check MIC only */
1026 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
1027 /* Bad MIC */
1028 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1029 else
1030 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1031
1032 break;
1033
1034 case RX_RES_STATUS_SEC_TYPE_TKIP:
1035 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1036 /* Bad TTAK */
1037 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1038 break;
1039 }
1040 /* fall through if TTAK OK */
1041 default:
1042 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1043 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1044 else
1045 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1046 break;
ee289b64 1047 }
8d801080
WYG		 1048
1049 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
1050 decrypt_in, decrypt_out);
1051
1052 return decrypt_out;
1053}
1054
1055static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1056 struct ieee80211_hdr *hdr,
1057 u16 len,
1058 u32 ampdu_status,
1059 struct iwl_rx_mem_buffer *rxb,
1060 struct ieee80211_rx_status *stats)
1061{
1062 struct sk_buff *skb;
8d801080
WYG		 1063 __le16 fc = hdr->frame_control;
1064
1065 /* We only process data packets if the interface is open */
1066 if (unlikely(!priv->is_open)) {
1067 IWL_DEBUG_DROP_LIMIT(priv,
1068 "Dropping packet while interface is not open.\n");
1069 return;
1070 }
1071
1072 /* In case of HW accelerated crypto and bad decryption, drop */
1073 if (!priv->cfg->mod_params->sw_crypto &&
1074 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1075 return;
1076
ecdf94b8 1077 skb = dev_alloc_skb(128);
8d801080 1078 if (!skb) {
ecdf94b8 1079 IWL_ERR(priv, "dev_alloc_skb failed\n");
8d801080
WYG		 1080 return;
1081 }
1082
8d801080
WYG		 1083 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1084
8d801080
WYG		 1085 iwl_update_stats(priv, false, fc, len);
1086 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1087
1088 ieee80211_rx(priv->hw, skb);
8d801080
WYG		 1089 priv->alloc_rxb_page--;
1090 rxb->page = NULL;
1091}
1092
1093/* Called for REPLY_RX (legacy ABG frames), or
1094 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1095void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1096 struct iwl_rx_mem_buffer *rxb)
1097{
1098 struct ieee80211_hdr *header;
1099 struct ieee80211_rx_status rx_status;
1100 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1101 struct iwl_rx_phy_res *phy_res;
1102 __le32 rx_pkt_status;
2fb291ee 1103 struct iwl_rx_mpdu_res_start *amsdu;
8d801080
WYG		 1104 u32 len;
1105 u32 ampdu_status;
1106 u32 rate_n_flags;
1107
1108 /**
1109 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1110 * REPLY_RX: physical layer info is in this buffer
1111 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1112 * command and cached in priv->last_phy_res
1113 *
1114 * Here we set up local variables depending on which command is
1115 * received.
1116 */
1117 if (pkt->hdr.cmd == REPLY_RX) {
1118 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1119 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1120 + phy_res->cfg_phy_cnt);
1121
1122 len = le16_to_cpu(phy_res->byte_count);
1123 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1124 phy_res->cfg_phy_cnt + len);
1125 ampdu_status = le32_to_cpu(rx_pkt_status);
1126 } else {
05d57520 1127 if (!priv->_agn.last_phy_res_valid) {
8d801080
WYG		 1128 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1129 return;
1130 }
05d57520 1131 phy_res = &priv->_agn.last_phy_res;
2fb291ee 1132 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
8d801080
WYG		 1133 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1134 len = le16_to_cpu(amsdu->byte_count);
1135 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1136 ampdu_status = iwlagn_translate_rx_status(priv,
1137 le32_to_cpu(rx_pkt_status));
1138 }
1139
1140 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1141 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1142 phy_res->cfg_phy_cnt);
1143 return;
1144 }
1145
1146 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1147 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1148 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1149 le32_to_cpu(rx_pkt_status));
1150 return;
1151 }
1152
1153 /* This will be used in several places later */
1154 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1155
1156 /* rx_status carries information about the packet to mac80211 */
1157 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1158 rx_status.freq =
1159 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1160 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1161 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1162 rx_status.rate_idx =
1163 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1164 rx_status.flag = 0;
1165
1166 /* TSF isn't reliable. In order to allow smooth user experience,
1167 * this W/A doesn't propagate it to the mac80211 */
1168 /*rx_status.flag |= RX_FLAG_TSFT;*/
1169
1170 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1171
1172 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1173 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1174
8d801080 1175 iwl_dbg_log_rx_data_frame(priv, len, header);
ed1b6e99
JB		 1176 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1177 rx_status.signal, (unsigned long long)rx_status.mactime);
8d801080
WYG		 1178
1179 /*
1180 * "antenna number"
1181 *
1182 * It seems that the antenna field in the phy flags value
1183 * is actually a bit field. This is undefined by radiotap,
1184 * it wants an actual antenna number but I always get "7"
1185 * for most legacy frames I receive indicating that the
1186 * same frame was received on all three RX chains.
1187 *
1188 * I think this field should be removed in favor of a
1189 * new 802.11n radiotap field "RX chains" that is defined
1190 * as a bitmask.
1191 */
1192 rx_status.antenna =
1193 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1194 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1195
1196 /* set the preamble flag if appropriate */
1197 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1198 rx_status.flag |= RX_FLAG_SHORTPRE;
1199
1200 /* Set up the HT phy flags */
1201 if (rate_n_flags & RATE_MCS_HT_MSK)
1202 rx_status.flag |= RX_FLAG_HT;
1203 if (rate_n_flags & RATE_MCS_HT40_MSK)
1204 rx_status.flag |= RX_FLAG_40MHZ;
1205 if (rate_n_flags & RATE_MCS_SGI_MSK)
1206 rx_status.flag |= RX_FLAG_SHORT_GI;
1207
1208 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1209 rxb, &rx_status);
1210}
1211
1212/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1213 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1214void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
05d57520 1215 struct iwl_rx_mem_buffer *rxb)
8d801080
WYG		 1216{
1217 struct iwl_rx_packet *pkt = rxb_addr(rxb);
05d57520
JB		 1218 priv->_agn.last_phy_res_valid = true;
1219 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
8d801080
WYG		 1220 sizeof(struct iwl_rx_phy_res));
1221}
b6e4c55a
JB		 1222
1223static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1dda6d28
JB		 1224 struct ieee80211_vif *vif,
1225 enum ieee80211_band band,
1226 struct iwl_scan_channel *scan_ch)
b6e4c55a
JB		 1227{
1228 const struct ieee80211_supported_band *sband;
b6e4c55a
JB		 1229 u16 passive_dwell = 0;
1230 u16 active_dwell = 0;
14023641 1231 int added = 0;
b6e4c55a
JB		 1232 u16 channel = 0;
1233
1234 sband = iwl_get_hw_mode(priv, band);
1235 if (!sband) {
1236 IWL_ERR(priv, "invalid band\n");
1237 return added;
1238 }
1239
1240 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1dda6d28 1241 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
b6e4c55a
JB		 1242
1243 if (passive_dwell <= active_dwell)
1244 passive_dwell = active_dwell + 1;
1245
14023641 1246 channel = iwl_get_single_channel_number(priv, band);
b6e4c55a
JB		 1247 if (channel) {
1248 scan_ch->channel = cpu_to_le16(channel);
1249 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1250 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1251 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1252 /* Set txpower levels to defaults */
1253 scan_ch->dsp_atten = 110;
1254 if (band == IEEE80211_BAND_5GHZ)
1255 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1256 else
1257 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1258 added++;
1259 } else
1260 IWL_ERR(priv, "no valid channel found\n");
1261 return added;
1262}
1263
1264static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1dda6d28 1265 struct ieee80211_vif *vif,
b6e4c55a
JB		 1266 enum ieee80211_band band,
1267 u8 is_active, u8 n_probes,
1268 struct iwl_scan_channel *scan_ch)
1269{
1270 struct ieee80211_channel *chan;
1271 const struct ieee80211_supported_band *sband;
1272 const struct iwl_channel_info *ch_info;
1273 u16 passive_dwell = 0;
1274 u16 active_dwell = 0;
1275 int added, i;
1276 u16 channel;
1277
1278 sband = iwl_get_hw_mode(priv, band);
1279 if (!sband)
1280 return 0;
1281
1282 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1dda6d28 1283 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
b6e4c55a
JB		 1284
1285 if (passive_dwell <= active_dwell)
1286 passive_dwell = active_dwell + 1;
1287
1288 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1289 chan = priv->scan_request->channels[i];
1290
1291 if (chan->band != band)
1292 continue;
1293
81e95430 1294 channel = chan->hw_value;
b6e4c55a
JB		 1295 scan_ch->channel = cpu_to_le16(channel);
1296
1297 ch_info = iwl_get_channel_info(priv, band, channel);
1298 if (!is_channel_valid(ch_info)) {
1299 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1300 channel);
1301 continue;
1302 }
1303
1304 if (!is_active || is_channel_passive(ch_info) ||
1305 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1306 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1307 else
1308 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1309
1310 if (n_probes)
1311 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1312
1313 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1314 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1315
1316 /* Set txpower levels to defaults */
1317 scan_ch->dsp_atten = 110;
1318
1319 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1320 * power level:
1321 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1322 */
1323 if (band == IEEE80211_BAND_5GHZ)
1324 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1325 else
1326 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1327
1328 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1329 channel, le32_to_cpu(scan_ch->type),
1330 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1331 "ACTIVE" : "PASSIVE",
1332 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1333 active_dwell : passive_dwell);
1334
1335 scan_ch++;
1336 added++;
1337 }
1338
1339 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1340 return added;
1341}
1342
3eecce52 1343int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
b6e4c55a
JB		 1344{
1345 struct iwl_host_cmd cmd = {
1346 .id = REPLY_SCAN_CMD,
1347 .len = sizeof(struct iwl_scan_cmd),
1348 .flags = CMD_SIZE_HUGE,
1349 };
1350 struct iwl_scan_cmd *scan;
a194e324 1351 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b6e4c55a
JB		 1352 u32 rate_flags = 0;
1353 u16 cmd_len;
1354 u16 rx_chain = 0;
1355 enum ieee80211_band band;
1356 u8 n_probes = 0;
1357 u8 rx_ant = priv->hw_params.valid_rx_ant;
1358 u8 rate;
1359 bool is_active = false;
1360 int chan_mod;
1361 u8 active_chains;
0e1654fa 1362 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
3eecce52
JB		 1363 int ret;
1364
1365 lockdep_assert_held(&priv->mutex);
b6e4c55a 1366
a194e324
JB		 1367 if (vif)
1368 ctx = iwl_rxon_ctx_from_vif(vif);
1369
b6e4c55a
JB		 1370 if (!priv->scan_cmd) {
1371 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1372 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1373 if (!priv->scan_cmd) {
1374 IWL_DEBUG_SCAN(priv,
1375 "fail to allocate memory for scan\n");
3eecce52 1376 return -ENOMEM;
b6e4c55a
JB		 1377 }
1378 }
1379 scan = priv->scan_cmd;
1380 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1381
1382 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1383 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1384
246ed355 1385 if (iwl_is_any_associated(priv)) {
b6e4c55a
JB		 1386 u16 interval = 0;
1387 u32 extra;
1388 u32 suspend_time = 100;
1389 u32 scan_suspend_time = 100;
1390 unsigned long flags;
1391
1392 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1393 spin_lock_irqsave(&priv->lock, flags);
a6e492b9
JL		 1394 if (priv->is_internal_short_scan)
1395 interval = 0;
1396 else
1397 interval = vif->bss_conf.beacon_int;
b6e4c55a
JB		 1398 spin_unlock_irqrestore(&priv->lock, flags);
1399
1400 scan->suspend_time = 0;
1401 scan->max_out_time = cpu_to_le32(200 * 1024);
1402 if (!interval)
1403 interval = suspend_time;
1404
1405 extra = (suspend_time / interval) << 22;
1406 scan_suspend_time = (extra |
1407 ((suspend_time % interval) * 1024));
1408 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1409 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1410 scan_suspend_time, interval);
1411 }
1412
1413 if (priv->is_internal_short_scan) {
1414 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1415 } else if (priv->scan_request->n_ssids) {
1416 int i, p = 0;
1417 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1418 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1419 /* always does wildcard anyway */
1420 if (!priv->scan_request->ssids[i].ssid_len)
1421 continue;
1422 scan->direct_scan[p].id = WLAN_EID_SSID;
1423 scan->direct_scan[p].len =
1424 priv->scan_request->ssids[i].ssid_len;
1425 memcpy(scan->direct_scan[p].ssid,
1426 priv->scan_request->ssids[i].ssid,
1427 priv->scan_request->ssids[i].ssid_len);
1428 n_probes++;
1429 p++;
1430 }
1431 is_active = true;
1432 } else
1433 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1434
1435 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
a194e324 1436 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
b6e4c55a
JB		 1437 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1438
1439 switch (priv->scan_band) {
1440 case IEEE80211_BAND_2GHZ:
1441 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
246ed355
JB		 1442 chan_mod = le32_to_cpu(
1443 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1444 RXON_FLG_CHANNEL_MODE_MSK)
b6e4c55a
JB		 1445 >> RXON_FLG_CHANNEL_MODE_POS;
1446 if (chan_mod == CHANNEL_MODE_PURE_40) {
1447 rate = IWL_RATE_6M_PLCP;
1448 } else {
1449 rate = IWL_RATE_1M_PLCP;
1450 rate_flags = RATE_MCS_CCK_MSK;
1451 }
d44ae69e
JB		 1452 /*
1453 * Internal scans are passive, so we can indiscriminately set
1454 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1455 */
7cb1b088
WYG		 1456 if (priv->cfg->bt_params &&
1457 priv->cfg->bt_params->advanced_bt_coexist)
d44ae69e 1458 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
b6e4c55a
JB		 1459 break;
1460 case IEEE80211_BAND_5GHZ:
1461 rate = IWL_RATE_6M_PLCP;
b6e4c55a
JB		 1462 break;
1463 default:
3eecce52
JB		 1464 IWL_WARN(priv, "Invalid scan band\n");
1465 return -EIO;
b6e4c55a
JB		 1466 }
1467
085fbca2
JB		 1468 /*
1469 * If active scanning is requested but a certain channel is
1470 * marked passive, we can do active scanning if we detect
1471 * transmissions.
1472 *
1473 * There is an issue with some firmware versions that triggers
1474 * a sysassert on a "good CRC threshold" of zero (== disabled),
1475 * on a radar channel even though this means that we should NOT
1476 * send probes.
1477 *
1478 * The "good CRC threshold" is the number of frames that we
1479 * need to receive during our dwell time on a channel before
1480 * sending out probes -- setting this to a huge value will
1481 * mean we never reach it, but at the same time work around
1482 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1483 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1484 */
1485 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1486 IWL_GOOD_CRC_TH_NEVER;
1487
b6e4c55a
JB		 1488 band = priv->scan_band;
1489
0e1654fa
JB		 1490 if (priv->cfg->scan_rx_antennas[band])
1491 rx_ant = priv->cfg->scan_rx_antennas[band];
e7cb4955 1492
0e1654fa
JB		 1493 if (priv->cfg->scan_tx_antennas[band])
1494 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1495
7cb1b088
WYG		 1496 if (priv->cfg->bt_params &&
1497 priv->cfg->bt_params->advanced_bt_coexist &&
1498 priv->bt_full_concurrent) {
bee008b7 1499 /* operated as 1x1 in full concurrency mode */
7cb1b088
WYG		 1500 scan_tx_antennas = first_antenna(
1501 priv->cfg->scan_tx_antennas[band]);
bee008b7
WYG		 1502 }
1503
0e1654fa
JB		 1504 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1505 scan_tx_antennas);
b6e4c55a
JB		 1506 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1507 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1508
1509 /* In power save mode use one chain, otherwise use all chains */
1510 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1511 /* rx_ant has been set to all valid chains previously */
1512 active_chains = rx_ant &
1513 ((u8)(priv->chain_noise_data.active_chains));
1514 if (!active_chains)
1515 active_chains = rx_ant;
1516
1517 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1518 priv->chain_noise_data.active_chains);
1519
1520 rx_ant = first_antenna(active_chains);
1521 }
7cb1b088
WYG		 1522 if (priv->cfg->bt_params &&
1523 priv->cfg->bt_params->advanced_bt_coexist &&
1524 priv->bt_full_concurrent) {
bee008b7
WYG		 1525 /* operated as 1x1 in full concurrency mode */
1526 rx_ant = first_antenna(rx_ant);
1527 }
1528
b6e4c55a
JB		 1529 /* MIMO is not used here, but value is required */
1530 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1531 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1532 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1533 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1534 scan->rx_chain = cpu_to_le16(rx_chain);
1535 if (!priv->is_internal_short_scan) {
1536 cmd_len = iwl_fill_probe_req(priv,
1537 (struct ieee80211_mgmt *)scan->data,
3a0b9aad 1538 vif->addr,
b6e4c55a
JB		 1539 priv->scan_request->ie,
1540 priv->scan_request->ie_len,
1541 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1542 } else {
3a0b9aad 1543 /* use bcast addr, will not be transmitted but must be valid */
b6e4c55a
JB		 1544 cmd_len = iwl_fill_probe_req(priv,
1545 (struct ieee80211_mgmt *)scan->data,
3a0b9aad 1546 iwl_bcast_addr, NULL, 0,
b6e4c55a
JB		 1547 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1548
1549 }
1550 scan->tx_cmd.len = cpu_to_le16(cmd_len);
b6e4c55a
JB		 1551
1552 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1553 RXON_FILTER_BCON_AWARE_MSK);
1554
1555 if (priv->is_internal_short_scan) {
1556 scan->channel_count =
1dda6d28 1557 iwl_get_single_channel_for_scan(priv, vif, band,
b6e4c55a
JB		 1558 (void *)&scan->data[le16_to_cpu(
1559 scan->tx_cmd.len)]);
1560 } else {
1561 scan->channel_count =
1dda6d28 1562 iwl_get_channels_for_scan(priv, vif, band,
b6e4c55a
JB		 1563 is_active, n_probes,
1564 (void *)&scan->data[le16_to_cpu(
1565 scan->tx_cmd.len)]);
1566 }
1567 if (scan->channel_count == 0) {
1568 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
3eecce52 1569 return -EIO;
b6e4c55a
JB		 1570 }
1571
1572 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1573 scan->channel_count * sizeof(struct iwl_scan_channel);
1574 cmd.data = scan;
1575 scan->len = cpu_to_le16(cmd.len);
1576
1cf26373
JB		 1577 /* set scan bit here for PAN params */
1578 set_bit(STATUS_SCAN_HW, &priv->status);
1579
3eecce52
JB		 1580 if (priv->cfg->ops->hcmd->set_pan_params) {
1581 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1582 if (ret)
1583 return ret;
1584 }
b6e4c55a 1585
3eecce52
JB		 1586 ret = iwl_send_cmd_sync(priv, &cmd);
1587 if (ret) {
1588 clear_bit(STATUS_SCAN_HW, &priv->status);
1589 if (priv->cfg->ops->hcmd->set_pan_params)
1590 priv->cfg->ops->hcmd->set_pan_params(priv);
1591 }
b6e4c55a 1592
3eecce52 1593 return ret;
b6e4c55a 1594}
1fa61b2e
JB		 1595
1596int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1597 struct ieee80211_vif *vif, bool add)
1598{
fd1af15d
JB		 1599 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1600
1fa61b2e 1601 if (add)
a30e3112
JB		 1602 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1603 vif->bss_conf.bssid,
1604 &vif_priv->ibss_bssid_sta_id);
fd1af15d
JB		 1605 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1606 vif->bss_conf.bssid);
1fa61b2e 1607}
1ff504e0
JB		 1608
1609void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1610 int sta_id, int tid, int freed)
1611{
a24d52f3 1612 lockdep_assert_held(&priv->sta_lock);
9c5ac091 1613
1ff504e0
JB		 1614 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1615 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1616 else {
1617 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1618 priv->stations[sta_id].tid[tid].tfds_in_queue,
1619 freed);
1620 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1621 }
1622}
716c74b0
WYG		 1623
1624#define IWL_FLUSH_WAIT_MS 2000
1625
1626int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1627{
1628 struct iwl_tx_queue *txq;
1629 struct iwl_queue *q;
1630 int cnt;
1631 unsigned long now = jiffies;
1632 int ret = 0;
1633
1634 /* waiting for all the tx frames complete might take a while */
1635 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
13bb9483 1636 if (cnt == priv->cmd_queue)
716c74b0
WYG		 1637 continue;
1638 txq = &priv->txq[cnt];
1639 q = &txq->q;
1640 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1641 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1642 msleep(1);
1643
1644 if (q->read_ptr != q->write_ptr) {
1645 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1646 ret = -ETIMEDOUT;
1647 break;
1648 }
1649 }
1650 return ret;
1651}
1652
1653#define IWL_TX_QUEUE_MSK 0xfffff
1654
1655/**
1656 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1657 *
1658 * pre-requirements:
1659 * 1. acquire mutex before calling
1660 * 2. make sure rf is on and not in exit state
1661 */
1662int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1663{
1664 struct iwl_txfifo_flush_cmd flush_cmd;
1665 struct iwl_host_cmd cmd = {
1666 .id = REPLY_TXFIFO_FLUSH,
1667 .len = sizeof(struct iwl_txfifo_flush_cmd),
1668 .flags = CMD_SYNC,
1669 .data = &flush_cmd,
1670 };
1671
1672 might_sleep();
1673
1674 memset(&flush_cmd, 0, sizeof(flush_cmd));
1675 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1676 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1677 if (priv->cfg->sku & IWL_SKU_N)
1678 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1679
1680 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1681 flush_cmd.fifo_control);
1682 flush_cmd.flush_control = cpu_to_le16(flush_control);
1683
1684 return iwl_send_cmd(priv, &cmd);
1685}
65550636
WYG		 1686
1687void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1688{
1689 mutex_lock(&priv->mutex);
1690 ieee80211_stop_queues(priv->hw);
1691 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1692 IWL_ERR(priv, "flush request fail\n");
1693 goto done;
1694 }
1695 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1696 iwlagn_wait_tx_queue_empty(priv);
1697done:
1698 ieee80211_wake_queues(priv->hw);
1699 mutex_unlock(&priv->mutex);
1700}
b6e116e8
WYG		 1701
1702/*
1703 * BT coex
1704 */
1705/*
1706 * Macros to access the lookup table.
1707 *
1708 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1709* wifi_prio, wifi_txrx and wifi_sh_ant_req.
1710 *
1711 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1712 *
1713 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1714 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1715 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1716 *
1717 * These macros encode that format.
1718 */
1719#define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1720 wifi_txrx, wifi_sh_ant_req) \
1721 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1722 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1723
1724#define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1725 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1726#define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1727 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1728 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1729 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1730 wifi_sh_ant_req))))
1731#define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1732 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1733 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1734 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1735 wifi_sh_ant_req))
1736#define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1737 wifi_req, wifi_prio, wifi_txrx, \
1738 wifi_sh_ant_req) \
1739 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1740 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1741 wifi_sh_ant_req))
1742
1743#define LUT_WLAN_KILL_OP(lut, op, val) \
1744 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1745#define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1746 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1747 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1748 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1749#define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1750 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1751 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1752 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1753#define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1754 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1755 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1756 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1757
1758#define LUT_ANT_SWITCH_OP(lut, op, val) \
1759 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1760#define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1761 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1762 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1763 wifi_req, wifi_prio, wifi_txrx, \
1764 wifi_sh_ant_req))))
1765#define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1766 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1767 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1768 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1769#define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1770 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1771 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1772 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1773
1774static const __le32 iwlagn_def_3w_lookup[12] = {
1775 cpu_to_le32(0xaaaaaaaa),
1776 cpu_to_le32(0xaaaaaaaa),
1777 cpu_to_le32(0xaeaaaaaa),
1778 cpu_to_le32(0xaaaaaaaa),
1779 cpu_to_le32(0xcc00ff28),
1780 cpu_to_le32(0x0000aaaa),
1781 cpu_to_le32(0xcc00aaaa),
1782 cpu_to_le32(0x0000aaaa),
1783 cpu_to_le32(0xc0004000),
1784 cpu_to_le32(0x00004000),
1785 cpu_to_le32(0xf0005000),
1786 cpu_to_le32(0xf0004000),
1787};
1788
1789static const __le32 iwlagn_concurrent_lookup[12] = {
1790 cpu_to_le32(0xaaaaaaaa),
1791 cpu_to_le32(0xaaaaaaaa),
1792 cpu_to_le32(0xaaaaaaaa),
1793 cpu_to_le32(0xaaaaaaaa),
1794 cpu_to_le32(0xaaaaaaaa),
1795 cpu_to_le32(0xaaaaaaaa),
1796 cpu_to_le32(0xaaaaaaaa),
1797 cpu_to_le32(0xaaaaaaaa),
1798 cpu_to_le32(0x00000000),
1799 cpu_to_le32(0x00000000),
1800 cpu_to_le32(0x00000000),
1801 cpu_to_le32(0x00000000),
1802};
1803
1804void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1805{
1806 struct iwlagn_bt_cmd bt_cmd = {
1807 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1808 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1809 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1810 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1811 };
1812
1813 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1814 sizeof(bt_cmd.bt3_lookup_table));
1815
7cb1b088
WYG		 1816 if (priv->cfg->bt_params)
1817 bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
1818 else
1819 bt_cmd.prio_boost = 0;
b6e116e8
WYG		 1820 bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1821 bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1822 bt_cmd.valid = priv->bt_valid;
09f250ac
WYG		 1823 bt_cmd.tx_prio_boost = 0;
1824 bt_cmd.rx_prio_boost = 0;
b6e116e8
WYG		 1825
1826 /*
1827 * Configure BT coex mode to "no coexistence" when the
1828 * user disabled BT coexistence, we have no interface
1829 * (might be in monitor mode), or the interface is in
1830 * IBSS mode (no proper uCode support for coex then).
1831 */
1832 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1833 bt_cmd.flags = 0;
1834 } else {
1835 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1836 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1837 if (priv->bt_ch_announce)
1838 bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1839 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1840 }
1841 if (priv->bt_full_concurrent)
1842 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1843 sizeof(iwlagn_concurrent_lookup));
1844 else
1845 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1846 sizeof(iwlagn_def_3w_lookup));
1847
1848 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1849 bt_cmd.flags ? "active" : "disabled",
1850 priv->bt_full_concurrent ?
1851 "full concurrency" : "3-wire");
1852
1853 if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1854 IWL_ERR(priv, "failed to send BT Coex Config\n");
1855
1856 /*
1857 * When we are doing a restart, need to also reconfigure BT
1858 * SCO to the device. If not doing a restart, bt_sco_active
1859 * will always be false, so there's no need to have an extra
1860 * variable to check for it.
1861 */
1862 if (priv->bt_sco_active) {
1863 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1864
1865 if (priv->bt_sco_active)
1866 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1867 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1868 sizeof(sco_cmd), &sco_cmd))
1869 IWL_ERR(priv, "failed to send BT SCO command\n");
1870 }
1871}
1872
1873static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1874{
1875 struct iwl_priv *priv =
1876 container_of(work, struct iwl_priv, bt_traffic_change_work);
8bd413e6 1877 struct iwl_rxon_context *ctx;
b6e116e8
WYG		 1878 int smps_request = -1;
1879
5eda74a4
SG		 1880 /*
1881 * Note: bt_traffic_load can be overridden by scan complete and
1882 * coex profile notifications. Ignore that since only bad consequence
1883 * can be not matching debug print with actual state.
1884 */
b6e116e8
WYG		 1885 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1886 priv->bt_traffic_load);
1887
1888 switch (priv->bt_traffic_load) {
1889 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
f5682c01
WYG		 1890 if (priv->bt_status)
1891 smps_request = IEEE80211_SMPS_DYNAMIC;
1892 else
1893 smps_request = IEEE80211_SMPS_AUTOMATIC;
b6e116e8
WYG		 1894 break;
1895 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1896 smps_request = IEEE80211_SMPS_DYNAMIC;
1897 break;
1898 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1899 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1900 smps_request = IEEE80211_SMPS_STATIC;
1901 break;
1902 default:
1903 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1904 priv->bt_traffic_load);
1905 break;
1906 }
1907
1908 mutex_lock(&priv->mutex);
1909
5eda74a4
SG		 1910 /*
1911 * We can not send command to firmware while scanning. When the scan
1912 * complete we will schedule this work again. We do check with mutex
1913 * locked to prevent new scan request to arrive. We do not check
1914 * STATUS_SCANNING to avoid race when queue_work two times from
1915 * different notifications, but quit and not perform any work at all.
1916 */
1917 if (test_bit(STATUS_SCAN_HW, &priv->status))
1918 goto out;
1919
b6e116e8
WYG		 1920 if (priv->cfg->ops->lib->update_chain_flags)
1921 priv->cfg->ops->lib->update_chain_flags(priv);
1922
8bd413e6
JB		 1923 if (smps_request != -1) {
1924 for_each_context(priv, ctx) {
1925 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1926 ieee80211_request_smps(ctx->vif, smps_request);
1927 }
1928 }
5eda74a4 1929out:
b6e116e8
WYG		 1930 mutex_unlock(&priv->mutex);
1931}
1932
1933static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1934 struct iwl_bt_uart_msg *uart_msg)
1935{
1936 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1937 "Update Req = 0x%X",
1938 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1939 BT_UART_MSG_FRAME1MSGTYPE_POS,
1940 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1941 BT_UART_MSG_FRAME1SSN_POS,
1942 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1943 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1944
1945 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1946 "Chl_SeqN = 0x%X, In band = 0x%X",
1947 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1948 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1949 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1950 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1951 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1952 BT_UART_MSG_FRAME2CHLSEQN_POS,
1953 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1954 BT_UART_MSG_FRAME2INBAND_POS);
1955
1956 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1957 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1958 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1959 BT_UART_MSG_FRAME3SCOESCO_POS,
1960 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1961 BT_UART_MSG_FRAME3SNIFF_POS,
1962 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1963 BT_UART_MSG_FRAME3A2DP_POS,
1964 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1965 BT_UART_MSG_FRAME3ACL_POS,
1966 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1967 BT_UART_MSG_FRAME3MASTER_POS,
1968 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1969 BT_UART_MSG_FRAME3OBEX_POS);
1970
1971 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1972 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1973 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1974
1975 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1976 "eSCO Retransmissions = 0x%X",
1977 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1978 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1979 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1980 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1981 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1982 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1983
1984 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1985 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1986 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1987 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1988 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1989
1990 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1991 "0x%X, Connectable = 0x%X",
1992 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1993 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1994 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1995 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1996 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1997 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1998}
1999
2000static void iwlagn_set_kill_ack_msk(struct iwl_priv *priv,
2001 struct iwl_bt_uart_msg *uart_msg)
2002{
2003 u8 kill_ack_msk;
2004 __le32 bt_kill_ack_msg[2] = {
2005 cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
2006
2007 kill_ack_msk = (((BT_UART_MSG_FRAME3A2DP_MSK |
2008 BT_UART_MSG_FRAME3SNIFF_MSK |
2009 BT_UART_MSG_FRAME3SCOESCO_MSK) &
2010 uart_msg->frame3) == 0) ? 1 : 0;
2011 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_ack_msk]) {
2012 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
2013 priv->kill_ack_mask = bt_kill_ack_msg[kill_ack_msk];
2014 /* schedule to send runtime bt_config */
2015 queue_work(priv->workqueue, &priv->bt_runtime_config);
2016 }
2017
2018}
2019
2020void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
2021 struct iwl_rx_mem_buffer *rxb)
2022{
2023 unsigned long flags;
2024 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2025 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
2026 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
2027 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
2028 u8 last_traffic_load;
2029
2030 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
2031 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
2032 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
2033 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
2034 coex->bt_ci_compliance);
2035 iwlagn_print_uartmsg(priv, uart_msg);
2036
2037 last_traffic_load = priv->notif_bt_traffic_load;
2038 priv->notif_bt_traffic_load = coex->bt_traffic_load;
2039 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2040 if (priv->bt_status != coex->bt_status ||
2041 last_traffic_load != coex->bt_traffic_load) {
2042 if (coex->bt_status) {
2043 /* BT on */
2044 if (!priv->bt_ch_announce)
2045 priv->bt_traffic_load =
2046 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
2047 else
2048 priv->bt_traffic_load =
2049 coex->bt_traffic_load;
2050 } else {
2051 /* BT off */
2052 priv->bt_traffic_load =
2053 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2054 }
2055 priv->bt_status = coex->bt_status;
2056 queue_work(priv->workqueue,
2057 &priv->bt_traffic_change_work);
2058 }
2059 if (priv->bt_sco_active !=
2060 (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
2061 priv->bt_sco_active = uart_msg->frame3 &
2062 BT_UART_MSG_FRAME3SCOESCO_MSK;
2063 if (priv->bt_sco_active)
2064 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
2065 iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
2066 sizeof(sco_cmd), &sco_cmd, NULL);
2067 }
2068 }
2069
2070 iwlagn_set_kill_ack_msk(priv, uart_msg);
2071
2072 /* FIXME: based on notification, adjust the prio_boost */
2073
2074 spin_lock_irqsave(&priv->lock, flags);
2075 priv->bt_ci_compliance = coex->bt_ci_compliance;
2076 spin_unlock_irqrestore(&priv->lock, flags);
2077}
2078
2079void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2080{
2081 iwlagn_rx_handler_setup(priv);
2082 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2083 iwlagn_bt_coex_profile_notif;
2084}
2085
2086void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2087{
2088 iwlagn_setup_deferred_work(priv);
2089
2090 INIT_WORK(&priv->bt_traffic_change_work,
2091 iwlagn_bt_traffic_change_work);
2092}
2093
2094void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2095{
2096 cancel_work_sync(&priv->bt_traffic_change_work);
2097}
5de33068
JB		 2098
2099static bool is_single_rx_stream(struct iwl_priv *priv)
2100{
2101 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
2102 priv->current_ht_config.single_chain_sufficient;
2103}
2104
2105#define IWL_NUM_RX_CHAINS_MULTIPLE 3
2106#define IWL_NUM_RX_CHAINS_SINGLE 2
2107#define IWL_NUM_IDLE_CHAINS_DUAL 2
2108#define IWL_NUM_IDLE_CHAINS_SINGLE 1
2109
2110/*
2111 * Determine how many receiver/antenna chains to use.
2112 *
2113 * More provides better reception via diversity. Fewer saves power
2114 * at the expense of throughput, but only when not in powersave to
2115 * start with.
2116 *
2117 * MIMO (dual stream) requires at least 2, but works better with 3.
2118 * This does not determine *which* chains to use, just how many.
2119 */
2120static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2121{
2122 if (priv->cfg->bt_params &&
2123 priv->cfg->bt_params->advanced_bt_coexist &&
2124 (priv->bt_full_concurrent ||
2125 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2126 /*
2127 * only use chain 'A' in bt high traffic load or
2128 * full concurrency mode
2129 */
2130 return IWL_NUM_RX_CHAINS_SINGLE;
2131 }
2132 /* # of Rx chains to use when expecting MIMO. */
2133 if (is_single_rx_stream(priv))
2134 return IWL_NUM_RX_CHAINS_SINGLE;
2135 else
2136 return IWL_NUM_RX_CHAINS_MULTIPLE;
2137}
2138
2139/*
2140 * When we are in power saving mode, unless device support spatial
2141 * multiplexing power save, use the active count for rx chain count.
2142 */
2143static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2144{
2145 /* # Rx chains when idling, depending on SMPS mode */
2146 switch (priv->current_ht_config.smps) {
2147 case IEEE80211_SMPS_STATIC:
2148 case IEEE80211_SMPS_DYNAMIC:
2149 return IWL_NUM_IDLE_CHAINS_SINGLE;
2150 case IEEE80211_SMPS_OFF:
2151 return active_cnt;
2152 default:
2153 WARN(1, "invalid SMPS mode %d",
2154 priv->current_ht_config.smps);
2155 return active_cnt;
2156 }
2157}
2158
2159/* up to 4 chains */
2160static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2161{
2162 u8 res;
2163 res = (chain_bitmap & BIT(0)) >> 0;
2164 res += (chain_bitmap & BIT(1)) >> 1;
2165 res += (chain_bitmap & BIT(2)) >> 2;
2166 res += (chain_bitmap & BIT(3)) >> 3;
2167 return res;
2168}
2169
2170/**
2171 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2172 *
2173 * Selects how many and which Rx receivers/antennas/chains to use.
2174 * This should not be used for scan command ... it puts data in wrong place.
2175 */
2176void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2177{
2178 bool is_single = is_single_rx_stream(priv);
2179 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2180 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2181 u32 active_chains;
2182 u16 rx_chain;
2183
2184 /* Tell uCode which antennas are actually connected.
2185 * Before first association, we assume all antennas are connected.
2186 * Just after first association, iwl_chain_noise_calibration()
2187 * checks which antennas actually *are* connected. */
2188 if (priv->chain_noise_data.active_chains)
2189 active_chains = priv->chain_noise_data.active_chains;
2190 else
2191 active_chains = priv->hw_params.valid_rx_ant;
2192
2193 if (priv->cfg->bt_params &&
2194 priv->cfg->bt_params->advanced_bt_coexist &&
2195 (priv->bt_full_concurrent ||
2196 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2197 /*
2198 * only use chain 'A' in bt high traffic load or
2199 * full concurrency mode
2200 */
2201 active_chains = first_antenna(active_chains);
2202 }
2203
2204 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2205
2206 /* How many receivers should we use? */
2207 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2208 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2209
2210
2211 /* correct rx chain count according hw settings
2212 * and chain noise calibration
2213 */
2214 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2215 if (valid_rx_cnt < active_rx_cnt)
2216 active_rx_cnt = valid_rx_cnt;
2217
2218 if (valid_rx_cnt < idle_rx_cnt)
2219 idle_rx_cnt = valid_rx_cnt;
2220
2221 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2222 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2223
2224 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2225
2226 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2227 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2228 else
2229 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2230
2231 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2232 ctx->staging.rx_chain,
2233 active_rx_cnt, idle_rx_cnt);
2234
2235 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2236 active_rx_cnt < idle_rx_cnt);
2237}
facd982e
JB		 2238
2239u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2240{
2241 int i;
2242 u8 ind = ant;
2243
2244 if (priv->band == IEEE80211_BAND_2GHZ &&
2245 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2246 return 0;
2247
2248 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2249 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2250 if (valid & BIT(ind))
2251 return ind;
2252 }
2253 return ant;
2254}
fed73292
JB		 2255
2256static const char *get_csr_string(int cmd)
2257{
2258 switch (cmd) {
2259 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2260 IWL_CMD(CSR_INT_COALESCING);
2261 IWL_CMD(CSR_INT);
2262 IWL_CMD(CSR_INT_MASK);
2263 IWL_CMD(CSR_FH_INT_STATUS);
2264 IWL_CMD(CSR_GPIO_IN);
2265 IWL_CMD(CSR_RESET);
2266 IWL_CMD(CSR_GP_CNTRL);
2267 IWL_CMD(CSR_HW_REV);
2268 IWL_CMD(CSR_EEPROM_REG);
2269 IWL_CMD(CSR_EEPROM_GP);
2270 IWL_CMD(CSR_OTP_GP_REG);
2271 IWL_CMD(CSR_GIO_REG);
2272 IWL_CMD(CSR_GP_UCODE_REG);
2273 IWL_CMD(CSR_GP_DRIVER_REG);
2274 IWL_CMD(CSR_UCODE_DRV_GP1);
2275 IWL_CMD(CSR_UCODE_DRV_GP2);
2276 IWL_CMD(CSR_LED_REG);
2277 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2278 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2279 IWL_CMD(CSR_ANA_PLL_CFG);
2280 IWL_CMD(CSR_HW_REV_WA_REG);
2281 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2282 default:
2283 return "UNKNOWN";
2284 }
2285}
2286
2287void iwl_dump_csr(struct iwl_priv *priv)
2288{
2289 int i;
2290 u32 csr_tbl[] = {
2291 CSR_HW_IF_CONFIG_REG,
2292 CSR_INT_COALESCING,
2293 CSR_INT,
2294 CSR_INT_MASK,
2295 CSR_FH_INT_STATUS,
2296 CSR_GPIO_IN,
2297 CSR_RESET,
2298 CSR_GP_CNTRL,
2299 CSR_HW_REV,
2300 CSR_EEPROM_REG,
2301 CSR_EEPROM_GP,
2302 CSR_OTP_GP_REG,
2303 CSR_GIO_REG,
2304 CSR_GP_UCODE_REG,
2305 CSR_GP_DRIVER_REG,
2306 CSR_UCODE_DRV_GP1,
2307 CSR_UCODE_DRV_GP2,
2308 CSR_LED_REG,
2309 CSR_DRAM_INT_TBL_REG,
2310 CSR_GIO_CHICKEN_BITS,
2311 CSR_ANA_PLL_CFG,
2312 CSR_HW_REV_WA_REG,
2313 CSR_DBG_HPET_MEM_REG
2314 };
2315 IWL_ERR(priv, "CSR values:\n");
2316 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2317 "CSR_INT_PERIODIC_REG)\n");
2318 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2319 IWL_ERR(priv, " %25s: 0X%08x\n",
2320 get_csr_string(csr_tbl[i]),
2321 iwl_read32(priv, csr_tbl[i]));
2322 }
2323}
84fac3d9
JB		 2324
2325static const char *get_fh_string(int cmd)
2326{
2327 switch (cmd) {
2328 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2329 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2330 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2331 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2332 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2333 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2334 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2335 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2336 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2337 default:
2338 return "UNKNOWN";
2339 }
2340}
2341
2342int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2343{
2344 int i;
2345#ifdef CONFIG_IWLWIFI_DEBUG
2346 int pos = 0;
2347 size_t bufsz = 0;
2348#endif
2349 u32 fh_tbl[] = {
2350 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2351 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2352 FH_RSCSR_CHNL0_WPTR,
2353 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2354 FH_MEM_RSSR_SHARED_CTRL_REG,
2355 FH_MEM_RSSR_RX_STATUS_REG,
2356 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2357 FH_TSSR_TX_STATUS_REG,
2358 FH_TSSR_TX_ERROR_REG
2359 };
2360#ifdef CONFIG_IWLWIFI_DEBUG
2361 if (display) {
2362 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2363 *buf = kmalloc(bufsz, GFP_KERNEL);
2364 if (!*buf)
2365 return -ENOMEM;
2366 pos += scnprintf(*buf + pos, bufsz - pos,
2367 "FH register values:\n");
2368 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2369 pos += scnprintf(*buf + pos, bufsz - pos,
2370 " %34s: 0X%08x\n",
2371 get_fh_string(fh_tbl[i]),
2372 iwl_read_direct32(priv, fh_tbl[i]));
2373 }
2374 return pos;
2375 }
2376#endif
2377 IWL_ERR(priv, "FH register values:\n");
2378 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2379 IWL_ERR(priv, " %34s: 0X%08x\n",
2380 get_fh_string(fh_tbl[i]),
2381 iwl_read_direct32(priv, fh_tbl[i]));
2382 }
2383 return 0;
2384}
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