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stmmac: update the driver's module version
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CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
b481de9c
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37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
b481de9c
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44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
a3139c59
SO
48#define DRV_NAME "iwlagn"
49
6bc913bd 50#include "iwl-eeprom.h"
3e0d4cb1 51#include "iwl-dev.h"
fee1247a 52#include "iwl-core.h"
3395f6e9 53#include "iwl-io.h"
b481de9c 54#include "iwl-helpers.h"
6974e363 55#include "iwl-sta.h"
f0832f13 56#include "iwl-calib.h"
b481de9c 57
416e1438 58
b481de9c
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59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
b481de9c
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65/*
66 * module name, copyright, version, etc.
b481de9c 67 */
d783b061 68#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 69
0a6857e7 70#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
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71#define VD "d"
72#else
73#define VD
74#endif
75
80bc5393 76#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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77#define VS "s"
78#else
79#define VS
80#endif
81
df48c323 82#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 83
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84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
a7b75207 87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 88MODULE_LICENSE("GPL");
4fc22b21 89MODULE_ALIAS("iwl4965");
b481de9c 90
b481de9c 91/*************** STATION TABLE MANAGEMENT ****
9fbab516 92 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
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93 * the functionality provided here
94 */
95
96/**************************************************************/
97
b481de9c 98/**
5b9f8cd3 99 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 100 *
01ebd063 101 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
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102 * the active_rxon structure is updated with the new data. This
103 * function correctly transitions out of the RXON_ASSOC_MSK state if
104 * a HW tune is required based on the RXON structure changes.
105 */
e0158e61 106int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
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107{
108 /* cast away the const for active_rxon in this function */
c1adf9fb 109 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
110 int ret;
111 bool new_assoc =
112 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 113
fee1247a 114 if (!iwl_is_alive(priv))
43d59b32 115 return -EBUSY;
b481de9c
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116
117 /* always get timestamp with Rx frame */
118 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
119
8ccde88a 120 ret = iwl_check_rxon_cmd(priv);
43d59b32 121 if (ret) {
15b1687c 122 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
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123 return -EINVAL;
124 }
125
0924e519
WYG
126 /*
127 * receive commit_rxon request
128 * abort any previous channel switch if still in process
129 */
130 if (priv->switch_rxon.switch_in_progress &&
131 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
132 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
133 le16_to_cpu(priv->switch_rxon.channel));
134 priv->switch_rxon.switch_in_progress = false;
135 }
136
b481de9c 137 /* If we don't need to send a full RXON, we can use
5b9f8cd3 138 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 139 * and other flags for the current radio configuration. */
54559703 140 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
141 ret = iwl_send_rxon_assoc(priv);
142 if (ret) {
15b1687c 143 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 144 return ret;
b481de9c
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145 }
146
147 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 148 iwl_print_rx_config_cmd(priv);
b481de9c
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149 return 0;
150 }
151
152 /* station table will be cleared */
153 priv->assoc_station_added = 0;
154
b481de9c
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155 /* If we are currently associated and the new config requires
156 * an RXON_ASSOC and the new config wants the associated mask enabled,
157 * we must clear the associated from the active configuration
158 * before we apply the new config */
43d59b32 159 if (iwl_is_associated(priv) && new_assoc) {
e1623446 160 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
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161 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
162
43d59b32 163 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 164 sizeof(struct iwl_rxon_cmd),
b481de9c
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165 &priv->active_rxon);
166
167 /* If the mask clearing failed then we set
168 * active_rxon back to what it was previously */
43d59b32 169 if (ret) {
b481de9c 170 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 171 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 172 return ret;
b481de9c 173 }
b481de9c
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174 }
175
e1623446 176 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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177 "* with%s RXON_FILTER_ASSOC_MSK\n"
178 "* channel = %d\n"
e174961c 179 "* bssid = %pM\n",
43d59b32 180 (new_assoc ? "" : "out"),
b481de9c 181 le16_to_cpu(priv->staging_rxon.channel),
e174961c 182 priv->staging_rxon.bssid_addr);
b481de9c 183
90e8e424 184 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
185
186 /* Apply the new configuration
187 * RXON unassoc clears the station table in uCode, send it before
188 * we add the bcast station. If assoc bit is set, we will send RXON
189 * after having added the bcast and bssid station.
190 */
191 if (!new_assoc) {
192 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 193 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 194 if (ret) {
15b1687c 195 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
196 return ret;
197 }
198 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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199 }
200
c587de0b 201 iwl_clear_stations_table(priv);
556f8db7 202
19cc1087 203 priv->start_calib = 0;
b481de9c 204
b481de9c 205 /* Add the broadcast address so we can send broadcast frames */
9a9ca65f 206 iwl_add_bcast_station(priv);
b481de9c
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207
208 /* If we have set the ASSOC_MSK and we are in BSS mode then
209 * add the IWL_AP_ID to the station rate table */
9185159d 210 if (new_assoc) {
05c914fe 211 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
212 ret = iwl_rxon_add_station(priv,
213 priv->active_rxon.bssid_addr, 1);
214 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
215 IWL_ERR(priv,
216 "Error adding AP address for TX.\n");
9185159d
TW
217 return -EIO;
218 }
219 priv->assoc_station_added = 1;
220 if (priv->default_wep_key &&
221 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
222 IWL_ERR(priv,
223 "Could not send WEP static key.\n");
b481de9c 224 }
43d59b32 225
47eef9bd
WYG
226 /*
227 * allow CTS-to-self if possible for new association.
228 * this is relevant only for 5000 series and up,
229 * but will not damage 4965
230 */
231 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
232
43d59b32
EG
233 /* Apply the new configuration
234 * RXON assoc doesn't clear the station table in uCode,
235 */
236 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
237 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
238 if (ret) {
15b1687c 239 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
240 return ret;
241 }
242 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 243 }
a643565e 244 iwl_print_rx_config_cmd(priv);
b481de9c 245
36da7d70
ZY
246 iwl_init_sensitivity(priv);
247
248 /* If we issue a new RXON command which required a tune then we must
249 * send a new TXPOWER command or we won't be able to Tx any frames */
250 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
251 if (ret) {
15b1687c 252 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
253 return ret;
254 }
255
b481de9c
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256 return 0;
257}
258
5b9f8cd3 259void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
260{
261
45823531
AK
262 if (priv->cfg->ops->hcmd->set_rxon_chain)
263 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 264 iwlcore_commit_rxon(priv);
5da4b55f
MA
265}
266
fcab423d 267static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
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268{
269 struct list_head *element;
270
e1623446 271 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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272 priv->frames_count);
273
274 while (!list_empty(&priv->free_frames)) {
275 element = priv->free_frames.next;
276 list_del(element);
fcab423d 277 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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278 priv->frames_count--;
279 }
280
281 if (priv->frames_count) {
39aadf8c 282 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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283 priv->frames_count);
284 priv->frames_count = 0;
285 }
286}
287
fcab423d 288static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 289{
fcab423d 290 struct iwl_frame *frame;
b481de9c
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291 struct list_head *element;
292 if (list_empty(&priv->free_frames)) {
293 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
294 if (!frame) {
15b1687c 295 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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296 return NULL;
297 }
298
299 priv->frames_count++;
300 return frame;
301 }
302
303 element = priv->free_frames.next;
304 list_del(element);
fcab423d 305 return list_entry(element, struct iwl_frame, list);
b481de9c
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306}
307
fcab423d 308static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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309{
310 memset(frame, 0, sizeof(*frame));
311 list_add(&frame->list, &priv->free_frames);
312}
313
47ff65c4 314static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 315 struct ieee80211_hdr *hdr,
73ec1cc2 316 int left)
b481de9c 317{
3109ece1 318 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
319 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
320 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
321 return 0;
322
323 if (priv->ibss_beacon->len > left)
324 return 0;
325
326 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
327
328 return priv->ibss_beacon->len;
329}
330
47ff65c4
DH
331/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
332static void iwl_set_beacon_tim(struct iwl_priv *priv,
333 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
334 u8 *beacon, u32 frame_size)
335{
336 u16 tim_idx;
337 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
338
339 /*
340 * The index is relative to frame start but we start looking at the
341 * variable-length part of the beacon.
342 */
343 tim_idx = mgmt->u.beacon.variable - beacon;
344
345 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
346 while ((tim_idx < (frame_size - 2)) &&
347 (beacon[tim_idx] != WLAN_EID_TIM))
348 tim_idx += beacon[tim_idx+1] + 2;
349
350 /* If TIM field was found, set variables */
351 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
352 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
353 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
354 } else
355 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
356}
357
5b9f8cd3 358static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 359 struct iwl_frame *frame)
4bf64efd
TW
360{
361 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH
362 u32 frame_size;
363 u32 rate_flags;
364 u32 rate;
365 /*
366 * We have to set up the TX command, the TX Beacon command, and the
367 * beacon contents.
368 */
4bf64efd 369
47ff65c4 370 /* Initialize memory */
4bf64efd
TW
371 tx_beacon_cmd = &frame->u.beacon;
372 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
373
47ff65c4 374 /* Set up TX beacon contents */
4bf64efd 375 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 376 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH
377 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
378 return 0;
4bf64efd 379
47ff65c4 380 /* Set up TX command fields */
4bf64efd 381 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH
382 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
383 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
384 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
385 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 386
47ff65c4
DH
387 /* Set up TX beacon command fields */
388 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
389 frame_size);
4bf64efd 390
47ff65c4
DH
391 /* Set up packet rate and flags */
392 rate = iwl_rate_get_lowest_plcp(priv);
393 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
394 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
395 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
396 rate_flags |= RATE_MCS_CCK_MSK;
397 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
398 rate_flags);
4bf64efd
TW
399
400 return sizeof(*tx_beacon_cmd) + frame_size;
401}
5b9f8cd3 402static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 403{
fcab423d 404 struct iwl_frame *frame;
b481de9c
ZY
405 unsigned int frame_size;
406 int rc;
b481de9c 407
fcab423d 408 frame = iwl_get_free_frame(priv);
b481de9c 409 if (!frame) {
15b1687c 410 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
411 "command.\n");
412 return -ENOMEM;
413 }
414
47ff65c4
DH
415 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
416 if (!frame_size) {
417 IWL_ERR(priv, "Error configuring the beacon command\n");
418 iwl_free_frame(priv, frame);
419 return -EINVAL;
420 }
b481de9c 421
857485c0 422 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
423 &frame->u.cmd[0]);
424
fcab423d 425 iwl_free_frame(priv, frame);
b481de9c
ZY
426
427 return rc;
428}
429
7aaa1d79
SO
430static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
431{
432 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
433
434 dma_addr_t addr = get_unaligned_le32(&tb->lo);
435 if (sizeof(dma_addr_t) > sizeof(u32))
436 addr |=
437 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
438
439 return addr;
440}
441
442static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
443{
444 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
445
446 return le16_to_cpu(tb->hi_n_len) >> 4;
447}
448
449static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
450 dma_addr_t addr, u16 len)
451{
452 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
453 u16 hi_n_len = len << 4;
454
455 put_unaligned_le32(addr, &tb->lo);
456 if (sizeof(dma_addr_t) > sizeof(u32))
457 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
458
459 tb->hi_n_len = cpu_to_le16(hi_n_len);
460
461 tfd->num_tbs = idx + 1;
462}
463
464static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
465{
466 return tfd->num_tbs & 0x1f;
467}
468
469/**
470 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
471 * @priv - driver private data
472 * @txq - tx queue
473 *
474 * Does NOT advance any TFD circular buffer read/write indexes
475 * Does NOT free the TFD itself (which is within circular buffer)
476 */
477void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
478{
59606ffa 479 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
480 struct iwl_tfd *tfd;
481 struct pci_dev *dev = priv->pci_dev;
482 int index = txq->q.read_ptr;
483 int i;
484 int num_tbs;
485
486 tfd = &tfd_tmp[index];
487
488 /* Sanity check on number of chunks */
489 num_tbs = iwl_tfd_get_num_tbs(tfd);
490
491 if (num_tbs >= IWL_NUM_OF_TBS) {
492 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
493 /* @todo issue fatal error, it is quite serious situation */
494 return;
495 }
496
497 /* Unmap tx_cmd */
498 if (num_tbs)
499 pci_unmap_single(dev,
c2acea8e
JB
500 pci_unmap_addr(&txq->meta[index], mapping),
501 pci_unmap_len(&txq->meta[index], len),
96891cee 502 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
503
504 /* Unmap chunks, if any. */
505 for (i = 1; i < num_tbs; i++) {
506 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
507 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
508
509 if (txq->txb) {
510 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
511 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
512 }
513 }
514}
515
516int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
517 struct iwl_tx_queue *txq,
518 dma_addr_t addr, u16 len,
519 u8 reset, u8 pad)
520{
521 struct iwl_queue *q;
59606ffa 522 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
523 u32 num_tbs;
524
525 q = &txq->q;
59606ffa
SO
526 tfd_tmp = (struct iwl_tfd *)txq->tfds;
527 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
528
529 if (reset)
530 memset(tfd, 0, sizeof(*tfd));
531
532 num_tbs = iwl_tfd_get_num_tbs(tfd);
533
534 /* Each TFD can point to a maximum 20 Tx buffers */
535 if (num_tbs >= IWL_NUM_OF_TBS) {
536 IWL_ERR(priv, "Error can not send more than %d chunks\n",
537 IWL_NUM_OF_TBS);
538 return -EINVAL;
539 }
540
541 BUG_ON(addr & ~DMA_BIT_MASK(36));
542 if (unlikely(addr & ~IWL_TX_DMA_MASK))
543 IWL_ERR(priv, "Unaligned address = %llx\n",
544 (unsigned long long)addr);
545
546 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
547
548 return 0;
549}
550
a8e74e27
SO
551/*
552 * Tell nic where to find circular buffer of Tx Frame Descriptors for
553 * given Tx queue, and enable the DMA channel used for that queue.
554 *
555 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
556 * channels supported in hardware.
557 */
558int iwl_hw_tx_queue_init(struct iwl_priv *priv,
559 struct iwl_tx_queue *txq)
560{
a8e74e27
SO
561 int txq_id = txq->q.id;
562
a8e74e27
SO
563 /* Circular buffer (TFD queue in DRAM) physical base address */
564 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
565 txq->q.dma_addr >> 8);
566
a8e74e27
SO
567 return 0;
568}
569
b481de9c
ZY
570/******************************************************************************
571 *
572 * Generic RX handler implementations
573 *
574 ******************************************************************************/
885ba202
TW
575static void iwl_rx_reply_alive(struct iwl_priv *priv,
576 struct iwl_rx_mem_buffer *rxb)
b481de9c 577{
2f301227 578 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 579 struct iwl_alive_resp *palive;
b481de9c
ZY
580 struct delayed_work *pwork;
581
582 palive = &pkt->u.alive_frame;
583
e1623446 584 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
585 "0x%01X 0x%01X\n",
586 palive->is_valid, palive->ver_type,
587 palive->ver_subtype);
588
589 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 590 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
591 memcpy(&priv->card_alive_init,
592 &pkt->u.alive_frame,
885ba202 593 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
594 pwork = &priv->init_alive_start;
595 } else {
e1623446 596 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 597 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 598 sizeof(struct iwl_alive_resp));
b481de9c
ZY
599 pwork = &priv->alive_start;
600 }
601
602 /* We delay the ALIVE response by 5ms to
603 * give the HW RF Kill time to activate... */
604 if (palive->is_valid == UCODE_VALID_OK)
605 queue_delayed_work(priv->workqueue, pwork,
606 msecs_to_jiffies(5));
607 else
39aadf8c 608 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
609}
610
5b9f8cd3 611static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 612{
c79dd5b5
TW
613 struct iwl_priv *priv =
614 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
615 struct sk_buff *beacon;
616
617 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 618 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
619
620 if (!beacon) {
15b1687c 621 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
622 return;
623 }
624
625 mutex_lock(&priv->mutex);
626 /* new beacon skb is allocated every time; dispose previous.*/
627 if (priv->ibss_beacon)
628 dev_kfree_skb(priv->ibss_beacon);
629
630 priv->ibss_beacon = beacon;
631 mutex_unlock(&priv->mutex);
632
5b9f8cd3 633 iwl_send_beacon_cmd(priv);
b481de9c
ZY
634}
635
4e39317d 636/**
5b9f8cd3 637 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
638 *
639 * This callback is provided in order to send a statistics request.
640 *
641 * This timer function is continually reset to execute within
642 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
643 * was received. We need to ensure we receive the statistics in order
644 * to update the temperature used for calibrating the TXPOWER.
645 */
5b9f8cd3 646static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
647{
648 struct iwl_priv *priv = (struct iwl_priv *)data;
649
650 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
651 return;
652
61780ee3
MA
653 /* dont send host command if rf-kill is on */
654 if (!iwl_is_ready_rf(priv))
655 return;
656
ef8d5529 657 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
658}
659
a9e1cb6a
WYG
660
661static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
662 u32 start_idx, u32 num_events,
663 u32 mode)
664{
665 u32 i;
666 u32 ptr; /* SRAM byte address of log data */
667 u32 ev, time, data; /* event log data */
668 unsigned long reg_flags;
669
670 if (mode == 0)
671 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
672 else
673 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
674
675 /* Make sure device is powered up for SRAM reads */
676 spin_lock_irqsave(&priv->reg_lock, reg_flags);
677 if (iwl_grab_nic_access(priv)) {
678 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
679 return;
680 }
681
682 /* Set starting address; reads will auto-increment */
683 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
684 rmb();
685
686 /*
687 * "time" is actually "data" for mode 0 (no timestamp).
688 * place event id # at far right for easier visual parsing.
689 */
690 for (i = 0; i < num_events; i++) {
691 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
692 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
693 if (mode == 0) {
694 trace_iwlwifi_dev_ucode_cont_event(priv,
695 0, time, ev);
696 } else {
697 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
698 trace_iwlwifi_dev_ucode_cont_event(priv,
699 time, data, ev);
700 }
701 }
702 /* Allow device to power down */
703 iwl_release_nic_access(priv);
704 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
705}
706
707void iwl_continuous_event_trace(struct iwl_priv *priv)
708{
709 u32 capacity; /* event log capacity in # entries */
710 u32 base; /* SRAM byte address of event log header */
711 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
712 u32 num_wraps; /* # times uCode wrapped to top of log */
713 u32 next_entry; /* index of next entry to be written by uCode */
714
715 if (priv->ucode_type == UCODE_INIT)
716 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
717 else
718 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
719 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
720 capacity = iwl_read_targ_mem(priv, base);
721 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
722 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
723 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
724 } else
725 return;
726
727 if (num_wraps == priv->event_log.num_wraps) {
728 iwl_print_cont_event_trace(priv,
729 base, priv->event_log.next_entry,
730 next_entry - priv->event_log.next_entry,
731 mode);
732 priv->event_log.non_wraps_count++;
733 } else {
734 if ((num_wraps - priv->event_log.num_wraps) > 1)
735 priv->event_log.wraps_more_count++;
736 else
737 priv->event_log.wraps_once_count++;
738 trace_iwlwifi_dev_ucode_wrap_event(priv,
739 num_wraps - priv->event_log.num_wraps,
740 next_entry, priv->event_log.next_entry);
741 if (next_entry < priv->event_log.next_entry) {
742 iwl_print_cont_event_trace(priv, base,
743 priv->event_log.next_entry,
744 capacity - priv->event_log.next_entry,
745 mode);
746
747 iwl_print_cont_event_trace(priv, base, 0,
748 next_entry, mode);
749 } else {
750 iwl_print_cont_event_trace(priv, base,
751 next_entry, capacity - next_entry,
752 mode);
753
754 iwl_print_cont_event_trace(priv, base, 0,
755 next_entry, mode);
756 }
757 }
758 priv->event_log.num_wraps = num_wraps;
759 priv->event_log.next_entry = next_entry;
760}
761
762/**
763 * iwl_bg_ucode_trace - Timer callback to log ucode event
764 *
765 * The timer is continually set to execute every
766 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
767 * this function is to perform continuous uCode event logging operation
768 * if enabled
769 */
770static void iwl_bg_ucode_trace(unsigned long data)
771{
772 struct iwl_priv *priv = (struct iwl_priv *)data;
773
774 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
775 return;
776
777 if (priv->event_log.ucode_trace) {
778 iwl_continuous_event_trace(priv);
779 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
780 mod_timer(&priv->ucode_trace,
781 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
782 }
783}
784
5b9f8cd3 785static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 786 struct iwl_rx_mem_buffer *rxb)
b481de9c 787{
0a6857e7 788#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 789 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
790 struct iwl4965_beacon_notif *beacon =
791 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 792 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 793
e1623446 794 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 795 "tsf %d %d rate %d\n",
25a6572c 796 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
797 beacon->beacon_notify_hdr.failure_frame,
798 le32_to_cpu(beacon->ibss_mgr_status),
799 le32_to_cpu(beacon->high_tsf),
800 le32_to_cpu(beacon->low_tsf), rate);
801#endif
802
05c914fe 803 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
804 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
805 queue_work(priv->workqueue, &priv->beacon_update);
806}
807
b481de9c
ZY
808/* Handle notification from uCode that card's power state is changing
809 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 810static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 811 struct iwl_rx_mem_buffer *rxb)
b481de9c 812{
2f301227 813 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
814 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
815 unsigned long status = priv->status;
816
3a41bbd5 817 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 818 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG
819 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
820 (flags & CT_CARD_DISABLED) ?
821 "Reached" : "Not reached");
b481de9c
ZY
822
823 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 824 CT_CARD_DISABLED)) {
b481de9c 825
3395f6e9 826 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
827 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
828
a8b50a0a
MA
829 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
830 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
831
832 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 833 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 834 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 835 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 836 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 837 }
3a41bbd5 838 if (flags & CT_CARD_DISABLED)
39b73fb1 839 iwl_tt_enter_ct_kill(priv);
b481de9c 840 }
3a41bbd5 841 if (!(flags & CT_CARD_DISABLED))
39b73fb1 842 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
843
844 if (flags & HW_CARD_DISABLED)
845 set_bit(STATUS_RF_KILL_HW, &priv->status);
846 else
847 clear_bit(STATUS_RF_KILL_HW, &priv->status);
848
849
b481de9c 850 if (!(flags & RXON_CARD_DISABLED))
2a421b91 851 iwl_scan_cancel(priv);
b481de9c
ZY
852
853 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
854 test_bit(STATUS_RF_KILL_HW, &priv->status)))
855 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
856 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
857 else
858 wake_up_interruptible(&priv->wait_command_queue);
859}
860
5b9f8cd3 861int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 862{
e2e3c57b 863 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 864 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
865 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
866 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
867 ~APMG_PS_CTRL_MSK_PWR_SRC);
868 } else {
869 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
870 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
871 ~APMG_PS_CTRL_MSK_PWR_SRC);
872 }
873
a8b50a0a 874 return 0;
e2e3c57b
TW
875}
876
b481de9c 877/**
5b9f8cd3 878 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
879 *
880 * Setup the RX handlers for each of the reply types sent from the uCode
881 * to the host.
882 *
883 * This function chains into the hardware specific files for them to setup
884 * any hardware specific handlers as well.
885 */
653fa4a0 886static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 887{
885ba202 888 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
889 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
890 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 891 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 892 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
893 iwl_rx_pm_debug_statistics_notif;
894 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 895
9fbab516
BC
896 /*
897 * The same handler is used for both the REPLY to a discrete
898 * statistics request from the host as well as for the periodic
899 * statistics notifications (after received beacons) from the uCode.
b481de9c 900 */
ef8d5529 901 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 902 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 903
21c339bf 904 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
905 iwl_setup_rx_scan_handlers(priv);
906
37a44211 907 /* status change handler */
5b9f8cd3 908 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 909
c1354754
TW
910 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
911 iwl_rx_missed_beacon_notif;
37a44211 912 /* Rx handlers */
1781a07f
EG
913 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
914 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
915 /* block ack */
916 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 917 /* Set up hardware specific Rx handlers */
d4789efe 918 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
919}
920
b481de9c 921/**
a55360e4 922 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
923 *
924 * Uses the priv->rx_handlers callback function array to invoke
925 * the appropriate handlers, including command responses,
926 * frame-received notifications, and other notifications.
927 */
a55360e4 928void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 929{
a55360e4 930 struct iwl_rx_mem_buffer *rxb;
db11d634 931 struct iwl_rx_packet *pkt;
a55360e4 932 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
933 u32 r, i;
934 int reclaim;
935 unsigned long flags;
5c0eef96 936 u8 fill_rx = 0;
d68ab680 937 u32 count = 8;
4752c93c 938 int total_empty;
b481de9c 939
6440adb5
BC
940 /* uCode's read index (stored in shared DRAM) indicates the last Rx
941 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 942 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
943 i = rxq->read;
944
945 /* Rx interrupt, but nothing sent from uCode */
946 if (i == r)
e1623446 947 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 948
4752c93c 949 /* calculate total frames need to be restock after handling RX */
7300515d 950 total_empty = r - rxq->write_actual;
4752c93c
MA
951 if (total_empty < 0)
952 total_empty += RX_QUEUE_SIZE;
953
954 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
955 fill_rx = 1;
956
b481de9c
ZY
957 while (i != r) {
958 rxb = rxq->queue[i];
959
9fbab516 960 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
961 * then a bug has been introduced in the queue refilling
962 * routines -- catch it here */
963 BUG_ON(rxb == NULL);
964
965 rxq->queue[i] = NULL;
966
2f301227
ZY
967 pci_unmap_page(priv->pci_dev, rxb->page_dma,
968 PAGE_SIZE << priv->hw_params.rx_page_order,
969 PCI_DMA_FROMDEVICE);
970 pkt = rxb_addr(rxb);
b481de9c 971
be1a71a1
JB
972 trace_iwlwifi_dev_rx(priv, pkt,
973 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
974
b481de9c
ZY
975 /* Reclaim a command buffer only if this packet is a response
976 * to a (driver-originated) command.
977 * If the packet (e.g. Rx frame) originated from uCode,
978 * there is no command buffer to reclaim.
979 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
980 * but apparently a few don't get set; catch them here. */
981 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
982 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 983 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 984 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 985 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
986 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
987 (pkt->hdr.cmd != REPLY_TX);
988
989 /* Based on type of command response or notification,
990 * handle those that need handling via function in
5b9f8cd3 991 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 992 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 993 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 994 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 995 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 996 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
997 } else {
998 /* No handling needed */
e1623446 999 IWL_DEBUG_RX(priv,
b481de9c
ZY
1000 "r %d i %d No handler needed for %s, 0x%02x\n",
1001 r, i, get_cmd_string(pkt->hdr.cmd),
1002 pkt->hdr.cmd);
1003 }
1004
29b1b268
ZY
1005 /*
1006 * XXX: After here, we should always check rxb->page
1007 * against NULL before touching it or its virtual
1008 * memory (pkt). Because some rx_handler might have
1009 * already taken or freed the pages.
1010 */
1011
b481de9c 1012 if (reclaim) {
2f301227
ZY
1013 /* Invoke any callbacks, transfer the buffer to caller,
1014 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1015 * as we reclaim the driver command queue */
29b1b268 1016 if (rxb->page)
17b88929 1017 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1018 else
39aadf8c 1019 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1020 }
1021
7300515d
ZY
1022 /* Reuse the page if possible. For notification packets and
1023 * SKBs that fail to Rx correctly, add them back into the
1024 * rx_free list for reuse later. */
1025 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1026 if (rxb->page != NULL) {
7300515d
ZY
1027 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1028 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1029 PCI_DMA_FROMDEVICE);
1030 list_add_tail(&rxb->list, &rxq->rx_free);
1031 rxq->free_count++;
1032 } else
1033 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1034
b481de9c 1035 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1036
b481de9c 1037 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1038 /* If there are a lot of unused frames,
1039 * restock the Rx queue so ucode wont assert. */
1040 if (fill_rx) {
1041 count++;
1042 if (count >= 8) {
7300515d 1043 rxq->read = i;
4752c93c 1044 iwl_rx_replenish_now(priv);
5c0eef96
MA
1045 count = 0;
1046 }
1047 }
b481de9c
ZY
1048 }
1049
1050 /* Backtrack one entry */
7300515d 1051 rxq->read = i;
4752c93c
MA
1052 if (fill_rx)
1053 iwl_rx_replenish_now(priv);
1054 else
1055 iwl_rx_queue_restock(priv);
a55360e4 1056}
a55360e4 1057
0359facc
MA
1058/* call this function to flush any scheduled tasklet */
1059static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1060{
a96a27f9 1061 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1062 synchronize_irq(priv->pci_dev->irq);
1063 tasklet_kill(&priv->irq_tasklet);
1064}
1065
ef850d7c 1066static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
1067{
1068 u32 inta, handled = 0;
1069 u32 inta_fh;
1070 unsigned long flags;
c2e61da2 1071 u32 i;
0a6857e7 1072#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1073 u32 inta_mask;
1074#endif
1075
1076 spin_lock_irqsave(&priv->lock, flags);
1077
1078 /* Ack/clear/reset pending uCode interrupts.
1079 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1080 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
1081 inta = iwl_read32(priv, CSR_INT);
1082 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1083
1084 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1085 * Any new interrupts that happen after this, either while we're
1086 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
1087 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1088 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1089
0a6857e7 1090#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1091 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1092 /* just for debug */
3395f6e9 1093 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1094 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1095 inta, inta_mask, inta_fh);
1096 }
1097#endif
1098
2f301227
ZY
1099 spin_unlock_irqrestore(&priv->lock, flags);
1100
b481de9c
ZY
1101 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1102 * atomic, make sure that inta covers all the interrupts that
1103 * we've discovered, even if FH interrupt came in just after
1104 * reading CSR_INT. */
6f83eaa1 1105 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1106 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1107 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
1108 inta |= CSR_INT_BIT_FH_TX;
1109
1110 /* Now service all interrupt bits discovered above. */
1111 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1112 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1113
1114 /* Tell the device to stop sending interrupts */
5b9f8cd3 1115 iwl_disable_interrupts(priv);
b481de9c 1116
a83b9141 1117 priv->isr_stats.hw++;
5b9f8cd3 1118 iwl_irq_handle_error(priv);
b481de9c
ZY
1119
1120 handled |= CSR_INT_BIT_HW_ERR;
1121
b481de9c
ZY
1122 return;
1123 }
1124
0a6857e7 1125#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1126 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1127 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1128 if (inta & CSR_INT_BIT_SCD) {
e1623446 1129 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1130 "the frame/frames.\n");
a83b9141
WYG
1131 priv->isr_stats.sch++;
1132 }
b481de9c
ZY
1133
1134 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1135 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1136 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1137 priv->isr_stats.alive++;
1138 }
b481de9c
ZY
1139 }
1140#endif
1141 /* Safely ignore these bits for debug checks below */
25c03d8e 1142 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1143
9fbab516 1144 /* HW RF KILL switch toggled */
b481de9c
ZY
1145 if (inta & CSR_INT_BIT_RF_KILL) {
1146 int hw_rf_kill = 0;
3395f6e9 1147 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1148 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1149 hw_rf_kill = 1;
1150
4c423a2b 1151 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1152 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1153
a83b9141
WYG
1154 priv->isr_stats.rfkill++;
1155
a9efa652 1156 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1157 * the driver allows loading the ucode even if the radio
1158 * is killed. Hence update the killswitch state here. The
1159 * rfkill handler will care about restarting if needed.
a9efa652 1160 */
6cd0b1cb
HS
1161 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1162 if (hw_rf_kill)
1163 set_bit(STATUS_RF_KILL_HW, &priv->status);
1164 else
1165 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1166 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1167 }
b481de9c
ZY
1168
1169 handled |= CSR_INT_BIT_RF_KILL;
1170 }
1171
9fbab516 1172 /* Chip got too hot and stopped itself */
b481de9c 1173 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1174 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1175 priv->isr_stats.ctkill++;
b481de9c
ZY
1176 handled |= CSR_INT_BIT_CT_KILL;
1177 }
1178
1179 /* Error detected by uCode */
1180 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1181 IWL_ERR(priv, "Microcode SW error detected. "
1182 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1183 priv->isr_stats.sw++;
1184 priv->isr_stats.sw_err = inta;
5b9f8cd3 1185 iwl_irq_handle_error(priv);
b481de9c
ZY
1186 handled |= CSR_INT_BIT_SW_ERR;
1187 }
1188
c2e61da2
BC
1189 /*
1190 * uCode wakes up after power-down sleep.
1191 * Tell device about any new tx or host commands enqueued,
1192 * and about any Rx buffers made available while asleep.
1193 */
b481de9c 1194 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1195 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1196 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1197 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1198 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1199 priv->isr_stats.wakeup++;
b481de9c
ZY
1200 handled |= CSR_INT_BIT_WAKEUP;
1201 }
1202
1203 /* All uCode command responses, including Tx command responses,
1204 * Rx "responses" (frame-received notification), and other
1205 * notifications from uCode come through here*/
1206 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1207 iwl_rx_handle(priv);
a83b9141 1208 priv->isr_stats.rx++;
b481de9c
ZY
1209 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1210 }
1211
c72cd19f 1212 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1213 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1214 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1215 priv->isr_stats.tx++;
b481de9c 1216 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1217 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1218 priv->ucode_write_complete = 1;
1219 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1220 }
1221
a83b9141 1222 if (inta & ~handled) {
15b1687c 1223 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1224 priv->isr_stats.unhandled++;
1225 }
b481de9c 1226
40cefda9 1227 if (inta & ~(priv->inta_mask)) {
39aadf8c 1228 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1229 inta & ~priv->inta_mask);
39aadf8c 1230 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1231 }
1232
1233 /* Re-enable all interrupts */
0359facc
MA
1234 /* only Re-enable if diabled by irq */
1235 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1236 iwl_enable_interrupts(priv);
b481de9c 1237
0a6857e7 1238#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1239 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1240 inta = iwl_read32(priv, CSR_INT);
1241 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1242 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1243 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1244 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1245 }
1246#endif
b481de9c
ZY
1247}
1248
ef850d7c
MA
1249/* tasklet for iwlagn interrupt */
1250static void iwl_irq_tasklet(struct iwl_priv *priv)
1251{
1252 u32 inta = 0;
1253 u32 handled = 0;
1254 unsigned long flags;
8756990f 1255 u32 i;
ef850d7c
MA
1256#ifdef CONFIG_IWLWIFI_DEBUG
1257 u32 inta_mask;
1258#endif
1259
1260 spin_lock_irqsave(&priv->lock, flags);
1261
1262 /* Ack/clear/reset pending uCode interrupts.
1263 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1264 */
1265 iwl_write32(priv, CSR_INT, priv->inta);
1266
1267 inta = priv->inta;
1268
1269#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1270 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1271 /* just for debug */
1272 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1273 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1274 inta, inta_mask);
1275 }
1276#endif
2f301227
ZY
1277
1278 spin_unlock_irqrestore(&priv->lock, flags);
1279
ef850d7c
MA
1280 /* saved interrupt in inta variable now we can reset priv->inta */
1281 priv->inta = 0;
1282
1283 /* Now service all interrupt bits discovered above. */
1284 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1285 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1286
1287 /* Tell the device to stop sending interrupts */
1288 iwl_disable_interrupts(priv);
1289
1290 priv->isr_stats.hw++;
1291 iwl_irq_handle_error(priv);
1292
1293 handled |= CSR_INT_BIT_HW_ERR;
1294
ef850d7c
MA
1295 return;
1296 }
1297
1298#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1299 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1300 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1301 if (inta & CSR_INT_BIT_SCD) {
1302 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1303 "the frame/frames.\n");
1304 priv->isr_stats.sch++;
1305 }
1306
1307 /* Alive notification via Rx interrupt will do the real work */
1308 if (inta & CSR_INT_BIT_ALIVE) {
1309 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1310 priv->isr_stats.alive++;
1311 }
1312 }
1313#endif
1314 /* Safely ignore these bits for debug checks below */
1315 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1316
1317 /* HW RF KILL switch toggled */
1318 if (inta & CSR_INT_BIT_RF_KILL) {
1319 int hw_rf_kill = 0;
1320 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1321 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1322 hw_rf_kill = 1;
1323
4c423a2b 1324 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1325 hw_rf_kill ? "disable radio" : "enable radio");
1326
1327 priv->isr_stats.rfkill++;
1328
1329 /* driver only loads ucode once setting the interface up.
1330 * the driver allows loading the ucode even if the radio
1331 * is killed. Hence update the killswitch state here. The
1332 * rfkill handler will care about restarting if needed.
1333 */
1334 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1335 if (hw_rf_kill)
1336 set_bit(STATUS_RF_KILL_HW, &priv->status);
1337 else
1338 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1339 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1340 }
1341
1342 handled |= CSR_INT_BIT_RF_KILL;
1343 }
1344
1345 /* Chip got too hot and stopped itself */
1346 if (inta & CSR_INT_BIT_CT_KILL) {
1347 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1348 priv->isr_stats.ctkill++;
1349 handled |= CSR_INT_BIT_CT_KILL;
1350 }
1351
1352 /* Error detected by uCode */
1353 if (inta & CSR_INT_BIT_SW_ERR) {
1354 IWL_ERR(priv, "Microcode SW error detected. "
1355 " Restarting 0x%X.\n", inta);
1356 priv->isr_stats.sw++;
1357 priv->isr_stats.sw_err = inta;
1358 iwl_irq_handle_error(priv);
1359 handled |= CSR_INT_BIT_SW_ERR;
1360 }
1361
1362 /* uCode wakes up after power-down sleep */
1363 if (inta & CSR_INT_BIT_WAKEUP) {
1364 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1365 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1366 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1367 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1368
1369 priv->isr_stats.wakeup++;
1370
1371 handled |= CSR_INT_BIT_WAKEUP;
1372 }
1373
1374 /* All uCode command responses, including Tx command responses,
1375 * Rx "responses" (frame-received notification), and other
1376 * notifications from uCode come through here*/
40cefda9
MA
1377 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1378 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1379 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1380 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1381 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1382 iwl_write32(priv, CSR_FH_INT_STATUS,
1383 CSR49_FH_INT_RX_MASK);
1384 }
1385 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1386 handled |= CSR_INT_BIT_RX_PERIODIC;
1387 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1388 }
1389 /* Sending RX interrupt require many steps to be done in the
1390 * the device:
1391 * 1- write interrupt to current index in ICT table.
1392 * 2- dma RX frame.
1393 * 3- update RX shared data to indicate last write index.
1394 * 4- send interrupt.
1395 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC
1396 * but the shared data changes does not reflect this;
1397 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1398 */
74ba67ed
BC
1399
1400 /* Disable periodic interrupt; we use it as just a one-shot. */
1401 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1402 CSR_INT_PERIODIC_DIS);
ef850d7c 1403 iwl_rx_handle(priv);
74ba67ed
BC
1404
1405 /*
1406 * Enable periodic interrupt in 8 msec only if we received
1407 * real RX interrupt (instead of just periodic int), to catch
1408 * any dangling Rx interrupt. If it was just the periodic
1409 * interrupt, there was no dangling Rx activity, and no need
1410 * to extend the periodic interrupt; one-shot is enough.
1411 */
40cefda9 1412 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1413 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA
1414 CSR_INT_PERIODIC_ENA);
1415
ef850d7c 1416 priv->isr_stats.rx++;
ef850d7c
MA
1417 }
1418
c72cd19f 1419 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1420 if (inta & CSR_INT_BIT_FH_TX) {
1421 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1422 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1423 priv->isr_stats.tx++;
1424 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1425 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1426 priv->ucode_write_complete = 1;
1427 wake_up_interruptible(&priv->wait_command_queue);
1428 }
1429
1430 if (inta & ~handled) {
1431 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1432 priv->isr_stats.unhandled++;
1433 }
1434
40cefda9 1435 if (inta & ~(priv->inta_mask)) {
ef850d7c 1436 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1437 inta & ~priv->inta_mask);
ef850d7c
MA
1438 }
1439
ef850d7c
MA
1440 /* Re-enable all interrupts */
1441 /* only Re-enable if diabled by irq */
1442 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1443 iwl_enable_interrupts(priv);
ef850d7c
MA
1444}
1445
a83b9141 1446
b481de9c
ZY
1447/******************************************************************************
1448 *
1449 * uCode download functions
1450 *
1451 ******************************************************************************/
1452
5b9f8cd3 1453static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1454{
98c92211
TW
1455 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1456 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1457 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1458 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1459 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1460 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1461}
1462
5b9f8cd3 1463static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1464{
1465 /* Remove all resets to allow NIC to operate */
1466 iwl_write32(priv, CSR_RESET, 0);
1467}
1468
1469
b481de9c 1470/**
5b9f8cd3 1471 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1472 *
1473 * Copy into buffers for card to fetch via bus-mastering
1474 */
5b9f8cd3 1475static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1476{
cc0f555d 1477 struct iwl_ucode_header *ucode;
a0987a8d 1478 int ret = -EINVAL, index;
b481de9c 1479 const struct firmware *ucode_raw;
a0987a8d
RC
1480 const char *name_pre = priv->cfg->fw_name_pre;
1481 const unsigned int api_max = priv->cfg->ucode_api_max;
1482 const unsigned int api_min = priv->cfg->ucode_api_min;
1483 char buf[25];
b481de9c
ZY
1484 u8 *src;
1485 size_t len;
cc0f555d
JS
1486 u32 api_ver, build;
1487 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1488 u16 eeprom_ver;
b481de9c
ZY
1489
1490 /* Ask kernel firmware_class module to get the boot firmware off disk.
1491 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1492 for (index = api_max; index >= api_min; index--) {
1493 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1494 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1495 if (ret < 0) {
15b1687c 1496 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1497 buf, ret);
1498 if (ret == -ENOENT)
1499 continue;
1500 else
1501 goto error;
1502 } else {
1503 if (index < api_max)
15b1687c
WT
1504 IWL_ERR(priv, "Loaded firmware %s, "
1505 "which is deprecated. "
1506 "Please use API v%u instead.\n",
a0987a8d 1507 buf, api_max);
15b1687c 1508
e1623446 1509 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1510 buf, ucode_raw->size);
1511 break;
1512 }
b481de9c
ZY
1513 }
1514
a0987a8d
RC
1515 if (ret < 0)
1516 goto error;
b481de9c 1517
cc0f555d
JS
1518 /* Make sure that we got at least the v1 header! */
1519 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1520 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1521 ret = -EINVAL;
b481de9c
ZY
1522 goto err_release;
1523 }
1524
1525 /* Data from ucode file: header followed by uCode images */
cc0f555d 1526 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1527
c02b3acd 1528 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1529 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1530 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1531 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1532 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1533 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1534 init_data_size =
1535 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1536 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1537 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1538
a0987a8d
RC
1539 /* api_ver should match the api version forming part of the
1540 * firmware filename ... but we don't check for that and only rely
877d0310 1541 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1542
1543 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1544 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1545 "Driver supports v%u, firmware is v%u.\n",
1546 api_max, api_ver);
1547 priv->ucode_ver = 0;
1548 ret = -EINVAL;
1549 goto err_release;
1550 }
1551 if (api_ver != api_max)
978785a3 1552 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1553 "got v%u. New firmware can be obtained "
1554 "from http://www.intellinuxwireless.org.\n",
1555 api_max, api_ver);
1556
978785a3
TW
1557 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1558 IWL_UCODE_MAJOR(priv->ucode_ver),
1559 IWL_UCODE_MINOR(priv->ucode_ver),
1560 IWL_UCODE_API(priv->ucode_ver),
1561 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1562
5ebeb5a6
RC
1563 snprintf(priv->hw->wiphy->fw_version,
1564 sizeof(priv->hw->wiphy->fw_version),
1565 "%u.%u.%u.%u",
1566 IWL_UCODE_MAJOR(priv->ucode_ver),
1567 IWL_UCODE_MINOR(priv->ucode_ver),
1568 IWL_UCODE_API(priv->ucode_ver),
1569 IWL_UCODE_SERIAL(priv->ucode_ver));
1570
cc0f555d
JS
1571 if (build)
1572 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1573
abdc2d62
JS
1574 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1575 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1576 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1577 ? "OTP" : "EEPROM", eeprom_ver);
1578
e1623446 1579 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1580 priv->ucode_ver);
e1623446 1581 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1582 inst_size);
e1623446 1583 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1584 data_size);
e1623446 1585 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1586 init_size);
e1623446 1587 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1588 init_data_size);
e1623446 1589 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1590 boot_size);
1591
1592 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1593 if (ucode_raw->size !=
1594 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1595 inst_size + data_size + init_size +
1596 init_data_size + boot_size) {
1597
cc0f555d
JS
1598 IWL_DEBUG_INFO(priv,
1599 "uCode file size %d does not match expected size\n",
1600 (int)ucode_raw->size);
90e759d1 1601 ret = -EINVAL;
b481de9c
ZY
1602 goto err_release;
1603 }
1604
1605 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1606 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1607 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1608 inst_size);
1609 ret = -EINVAL;
b481de9c
ZY
1610 goto err_release;
1611 }
1612
099b40b7 1613 if (data_size > priv->hw_params.max_data_size) {
e1623446 1614 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1615 data_size);
1616 ret = -EINVAL;
b481de9c
ZY
1617 goto err_release;
1618 }
099b40b7 1619 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1620 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1621 init_size);
90e759d1 1622 ret = -EINVAL;
b481de9c
ZY
1623 goto err_release;
1624 }
099b40b7 1625 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1626 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1627 init_data_size);
1628 ret = -EINVAL;
b481de9c
ZY
1629 goto err_release;
1630 }
099b40b7 1631 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1632 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1633 boot_size);
90e759d1 1634 ret = -EINVAL;
b481de9c
ZY
1635 goto err_release;
1636 }
1637
1638 /* Allocate ucode buffers for card's bus-master loading ... */
1639
1640 /* Runtime instructions and 2 copies of data:
1641 * 1) unmodified from disk
1642 * 2) backup cache for save/restore during power-downs */
1643 priv->ucode_code.len = inst_size;
98c92211 1644 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1645
1646 priv->ucode_data.len = data_size;
98c92211 1647 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1648
1649 priv->ucode_data_backup.len = data_size;
98c92211 1650 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1651
1f304e4e
ZY
1652 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1653 !priv->ucode_data_backup.v_addr)
1654 goto err_pci_alloc;
1655
b481de9c 1656 /* Initialization instructions and data */
90e759d1
TW
1657 if (init_size && init_data_size) {
1658 priv->ucode_init.len = init_size;
98c92211 1659 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1660
1661 priv->ucode_init_data.len = init_data_size;
98c92211 1662 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1663
1664 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1665 goto err_pci_alloc;
1666 }
b481de9c
ZY
1667
1668 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1669 if (boot_size) {
1670 priv->ucode_boot.len = boot_size;
98c92211 1671 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1672
90e759d1
TW
1673 if (!priv->ucode_boot.v_addr)
1674 goto err_pci_alloc;
1675 }
b481de9c
ZY
1676
1677 /* Copy images into buffers for card's bus-master reads ... */
1678
1679 /* Runtime instructions (first block of data in file) */
cc0f555d 1680 len = inst_size;
e1623446 1681 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1682 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1683 src += len;
1684
e1623446 1685 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1686 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1687
1688 /* Runtime data (2nd block)
5b9f8cd3 1689 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1690 len = data_size;
e1623446 1691 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1692 memcpy(priv->ucode_data.v_addr, src, len);
1693 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1694 src += len;
b481de9c
ZY
1695
1696 /* Initialization instructions (3rd block) */
1697 if (init_size) {
cc0f555d 1698 len = init_size;
e1623446 1699 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1700 len);
b481de9c 1701 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1702 src += len;
b481de9c
ZY
1703 }
1704
1705 /* Initialization data (4th block) */
1706 if (init_data_size) {
cc0f555d 1707 len = init_data_size;
e1623446 1708 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1709 len);
b481de9c 1710 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1711 src += len;
b481de9c
ZY
1712 }
1713
1714 /* Bootstrap instructions (5th block) */
cc0f555d 1715 len = boot_size;
e1623446 1716 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1717 memcpy(priv->ucode_boot.v_addr, src, len);
1718
1719 /* We have our copies now, allow OS release its copies */
1720 release_firmware(ucode_raw);
1721 return 0;
1722
1723 err_pci_alloc:
15b1687c 1724 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1725 ret = -ENOMEM;
5b9f8cd3 1726 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1727
1728 err_release:
1729 release_firmware(ucode_raw);
1730
1731 error:
90e759d1 1732 return ret;
b481de9c
ZY
1733}
1734
b7a79404
RC
1735static const char *desc_lookup_text[] = {
1736 "OK",
1737 "FAIL",
1738 "BAD_PARAM",
1739 "BAD_CHECKSUM",
1740 "NMI_INTERRUPT_WDG",
1741 "SYSASSERT",
1742 "FATAL_ERROR",
1743 "BAD_COMMAND",
1744 "HW_ERROR_TUNE_LOCK",
1745 "HW_ERROR_TEMPERATURE",
1746 "ILLEGAL_CHAN_FREQ",
1747 "VCC_NOT_STABLE",
1748 "FH_ERROR",
1749 "NMI_INTERRUPT_HOST",
1750 "NMI_INTERRUPT_ACTION_PT",
1751 "NMI_INTERRUPT_UNKNOWN",
1752 "UCODE_VERSION_MISMATCH",
1753 "HW_ERROR_ABS_LOCK",
1754 "HW_ERROR_CAL_LOCK_FAIL",
1755 "NMI_INTERRUPT_INST_ACTION_PT",
1756 "NMI_INTERRUPT_DATA_ACTION_PT",
1757 "NMI_TRM_HW_ER",
1758 "NMI_INTERRUPT_TRM",
1759 "NMI_INTERRUPT_BREAK_POINT"
1760 "DEBUG_0",
1761 "DEBUG_1",
1762 "DEBUG_2",
1763 "DEBUG_3",
1764 "UNKNOWN"
1765};
1766
1767static const char *desc_lookup(int i)
1768{
1769 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1770
1771 if (i < 0 || i > max)
1772 i = max;
1773
1774 return desc_lookup_text[i];
1775}
1776
1777#define ERROR_START_OFFSET (1 * sizeof(u32))
1778#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1779
1780void iwl_dump_nic_error_log(struct iwl_priv *priv)
1781{
1782 u32 data2, line;
1783 u32 desc, time, count, base, data1;
1784 u32 blink1, blink2, ilink1, ilink2;
1785
1786 if (priv->ucode_type == UCODE_INIT)
1787 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1788 else
1789 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1790
1791 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1792 IWL_ERR(priv,
1793 "Not valid error log pointer 0x%08X for %s uCode\n",
1794 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC
1795 return;
1796 }
1797
1798 count = iwl_read_targ_mem(priv, base);
1799
1800 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1801 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1802 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1803 priv->status, count);
1804 }
1805
1806 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1807 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1808 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1809 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1810 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1811 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1812 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1813 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1814 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1815
be1a71a1
JB
1816 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1817 blink1, blink2, ilink1, ilink2);
1818
b7a79404
RC
1819 IWL_ERR(priv, "Desc Time "
1820 "data1 data2 line\n");
1821 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1822 desc_lookup(desc), desc, time, data1, data2, line);
1823 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1824 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1825 ilink1, ilink2);
1826
1827}
1828
1829#define EVENT_START_OFFSET (4 * sizeof(u32))
1830
1831/**
1832 * iwl_print_event_log - Dump error event log to syslog
1833 *
1834 */
b03d7d0f
WYG
1835static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1836 u32 num_events, u32 mode,
1837 int pos, char **buf, size_t bufsz)
b7a79404
RC
1838{
1839 u32 i;
1840 u32 base; /* SRAM byte address of event log header */
1841 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1842 u32 ptr; /* SRAM byte address of log data */
1843 u32 ev, time, data; /* event log data */
e5854471 1844 unsigned long reg_flags;
b7a79404
RC
1845
1846 if (num_events == 0)
b03d7d0f 1847 return pos;
b7a79404
RC
1848 if (priv->ucode_type == UCODE_INIT)
1849 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1850 else
1851 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1852
1853 if (mode == 0)
1854 event_size = 2 * sizeof(u32);
1855 else
1856 event_size = 3 * sizeof(u32);
1857
1858 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1859
e5854471
BC
1860 /* Make sure device is powered up for SRAM reads */
1861 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1862 iwl_grab_nic_access(priv);
1863
1864 /* Set starting address; reads will auto-increment */
1865 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1866 rmb();
1867
b7a79404
RC
1868 /* "time" is actually "data" for mode 0 (no timestamp).
1869 * place event id # at far right for easier visual parsing. */
1870 for (i = 0; i < num_events; i++) {
e5854471
BC
1871 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1872 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1873 if (mode == 0) {
1874 /* data, ev */
b03d7d0f
WYG
1875 if (bufsz) {
1876 pos += scnprintf(*buf + pos, bufsz - pos,
1877 "EVT_LOG:0x%08x:%04u\n",
1878 time, ev);
1879 } else {
1880 trace_iwlwifi_dev_ucode_event(priv, 0,
1881 time, ev);
1882 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1883 time, ev);
1884 }
b7a79404 1885 } else {
e5854471 1886 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1887 if (bufsz) {
1888 pos += scnprintf(*buf + pos, bufsz - pos,
1889 "EVT_LOGT:%010u:0x%08x:%04u\n",
1890 time, data, ev);
1891 } else {
1892 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 1893 time, data, ev);
b03d7d0f
WYG
1894 trace_iwlwifi_dev_ucode_event(priv, time,
1895 data, ev);
1896 }
b7a79404
RC
1897 }
1898 }
e5854471
BC
1899
1900 /* Allow device to power down */
1901 iwl_release_nic_access(priv);
1902 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1903 return pos;
b7a79404
RC
1904}
1905
c341ddb2
WYG
1906/**
1907 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1908 */
b03d7d0f
WYG
1909static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1910 u32 num_wraps, u32 next_entry,
1911 u32 size, u32 mode,
1912 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1913{
1914 /*
1915 * display the newest DEFAULT_LOG_ENTRIES entries
1916 * i.e the entries just before the next ont that uCode would fill.
1917 */
1918 if (num_wraps) {
1919 if (next_entry < size) {
b03d7d0f
WYG
1920 pos = iwl_print_event_log(priv,
1921 capacity - (size - next_entry),
1922 size - next_entry, mode,
1923 pos, buf, bufsz);
1924 pos = iwl_print_event_log(priv, 0,
1925 next_entry, mode,
1926 pos, buf, bufsz);
c341ddb2 1927 } else
b03d7d0f
WYG
1928 pos = iwl_print_event_log(priv, next_entry - size,
1929 size, mode, pos, buf, bufsz);
c341ddb2 1930 } else {
b03d7d0f
WYG
1931 if (next_entry < size) {
1932 pos = iwl_print_event_log(priv, 0, next_entry,
1933 mode, pos, buf, bufsz);
1934 } else {
1935 pos = iwl_print_event_log(priv, next_entry - size,
1936 size, mode, pos, buf, bufsz);
1937 }
c341ddb2 1938 }
b03d7d0f 1939 return pos;
c341ddb2
WYG
1940}
1941
84c40692
BC
1942/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1943#define MAX_EVENT_LOG_SIZE (512)
1944
c341ddb2
WYG
1945#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
1946
b03d7d0f
WYG
1947int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1948 char **buf, bool display)
b7a79404
RC
1949{
1950 u32 base; /* SRAM byte address of event log header */
1951 u32 capacity; /* event log capacity in # entries */
1952 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1953 u32 num_wraps; /* # times uCode wrapped to top of log */
1954 u32 next_entry; /* index of next entry to be written by uCode */
1955 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
1956 int pos = 0;
1957 size_t bufsz = 0;
b7a79404
RC
1958
1959 if (priv->ucode_type == UCODE_INIT)
1960 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1961 else
1962 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1963
1964 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1965 IWL_ERR(priv,
1966 "Invalid event log pointer 0x%08X for %s uCode\n",
1967 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b03d7d0f 1968 return pos;
b7a79404
RC
1969 }
1970
1971 /* event log header */
1972 capacity = iwl_read_targ_mem(priv, base);
1973 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1974 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1975 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1976
84c40692
BC
1977 if (capacity > MAX_EVENT_LOG_SIZE) {
1978 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1979 capacity, MAX_EVENT_LOG_SIZE);
1980 capacity = MAX_EVENT_LOG_SIZE;
1981 }
1982
1983 if (next_entry > MAX_EVENT_LOG_SIZE) {
1984 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1985 next_entry, MAX_EVENT_LOG_SIZE);
1986 next_entry = MAX_EVENT_LOG_SIZE;
1987 }
1988
b7a79404
RC
1989 size = num_wraps ? capacity : next_entry;
1990
1991 /* bail out if nothing in log */
1992 if (size == 0) {
1993 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1994 return pos;
b7a79404
RC
1995 }
1996
c341ddb2 1997#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1998 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
1999 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2000 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2001#else
2002 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2003 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2004#endif
2005 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2006 size);
b7a79404 2007
c341ddb2 2008#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
2009 if (display) {
2010 if (full_log)
2011 bufsz = capacity * 48;
2012 else
2013 bufsz = size * 48;
2014 *buf = kmalloc(bufsz, GFP_KERNEL);
2015 if (!*buf)
2016 return pos;
2017 }
c341ddb2
WYG
2018 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2019 /*
2020 * if uCode has wrapped back to top of log,
2021 * start at the oldest entry,
2022 * i.e the next one that uCode would fill.
2023 */
2024 if (num_wraps)
b03d7d0f
WYG
2025 pos = iwl_print_event_log(priv, next_entry,
2026 capacity - next_entry, mode,
2027 pos, buf, bufsz);
c341ddb2 2028 /* (then/else) start at top of log */
b03d7d0f
WYG
2029 pos = iwl_print_event_log(priv, 0,
2030 next_entry, mode, pos, buf, bufsz);
c341ddb2 2031 } else
b03d7d0f
WYG
2032 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2033 next_entry, size, mode,
2034 pos, buf, bufsz);
c341ddb2 2035#else
b03d7d0f
WYG
2036 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2037 next_entry, size, mode,
2038 pos, buf, bufsz);
b7a79404 2039#endif
b03d7d0f 2040 return pos;
c341ddb2 2041}
b7a79404 2042
b481de9c 2043/**
4a4a9e81 2044 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2045 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2046 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2047 */
4a4a9e81 2048static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2049{
57aab75a 2050 int ret = 0;
b481de9c 2051
e1623446 2052 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2053
2054 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2055 /* We had an error bringing up the hardware, so take it
2056 * all the way back down so we can try again */
e1623446 2057 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2058 goto restart;
2059 }
2060
2061 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2062 * This is a paranoid check, because we would not have gotten the
2063 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2064 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
2065 /* Runtime instruction load was bad;
2066 * take it all the way back down so we can try again */
e1623446 2067 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2068 goto restart;
2069 }
2070
c587de0b 2071 iwl_clear_stations_table(priv);
57aab75a
TW
2072 ret = priv->cfg->ops->lib->alive_notify(priv);
2073 if (ret) {
39aadf8c
WT
2074 IWL_WARN(priv,
2075 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
2076 goto restart;
2077 }
2078
5b9f8cd3 2079 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
2080 set_bit(STATUS_ALIVE, &priv->status);
2081
fee1247a 2082 if (iwl_is_rfkill(priv))
b481de9c
ZY
2083 return;
2084
36d6825b 2085 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2086
2087 priv->active_rate = priv->rates_mask;
2088 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2089
2f748dec
WYG
2090 /* Configure Tx antenna selection based on H/W config */
2091 if (priv->cfg->ops->hcmd->set_tx_ant)
2092 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2093
3109ece1 2094 if (iwl_is_associated(priv)) {
c1adf9fb
GG
2095 struct iwl_rxon_cmd *active_rxon =
2096 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
2097 /* apply any changes in staging */
2098 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2099 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2100 } else {
2101 /* Initialize our rx_config data */
5b9f8cd3 2102 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
2103
2104 if (priv->cfg->ops->hcmd->set_rxon_chain)
2105 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2106
b481de9c
ZY
2107 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2108 }
2109
9fbab516 2110 /* Configure Bluetooth device coexistence support */
5b9f8cd3 2111 iwl_send_bt_config(priv);
b481de9c 2112
4a4a9e81
TW
2113 iwl_reset_run_time_calib(priv);
2114
b481de9c 2115 /* Configure the adapter for unassociated operation */
e0158e61 2116 iwlcore_commit_rxon(priv);
b481de9c
ZY
2117
2118 /* At this point, the NIC is initialized and operational */
47f4a587 2119 iwl_rf_kill_ct_config(priv);
5a66926a 2120
e932a609 2121 iwl_leds_init(priv);
fe00b5a5 2122
e1623446 2123 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2124 set_bit(STATUS_READY, &priv->status);
5a66926a 2125 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2126
e312c24c 2127 iwl_power_update_mode(priv, true);
c46fbefa 2128
ada17513
MA
2129 /* reassociate for ADHOC mode */
2130 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2131 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2132 priv->vif);
2133 if (beacon)
2134 iwl_mac_beacon_update(priv->hw, beacon);
2135 }
2136
2137
c46fbefa 2138 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 2139 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 2140
b481de9c
ZY
2141 return;
2142
2143 restart:
2144 queue_work(priv->workqueue, &priv->restart);
2145}
2146
4e39317d 2147static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2148
5b9f8cd3 2149static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2150{
2151 unsigned long flags;
2152 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2153
e1623446 2154 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2155
b481de9c
ZY
2156 if (!exit_pending)
2157 set_bit(STATUS_EXIT_PENDING, &priv->status);
2158
c587de0b 2159 iwl_clear_stations_table(priv);
b481de9c
ZY
2160
2161 /* Unblock any waiting calls */
2162 wake_up_interruptible_all(&priv->wait_command_queue);
2163
b481de9c
ZY
2164 /* Wipe out the EXIT_PENDING status bit if we are not actually
2165 * exiting the module */
2166 if (!exit_pending)
2167 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2168
2169 /* stop and reset the on-board processor */
3395f6e9 2170 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2171
2172 /* tell the device to stop sending interrupts */
0359facc 2173 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2174 iwl_disable_interrupts(priv);
0359facc
MA
2175 spin_unlock_irqrestore(&priv->lock, flags);
2176 iwl_synchronize_irq(priv);
b481de9c
ZY
2177
2178 if (priv->mac80211_registered)
2179 ieee80211_stop_queues(priv->hw);
2180
5b9f8cd3 2181 /* If we have not previously called iwl_init() then
a60e77e5 2182 * clear all bits but the RF Kill bit and return */
fee1247a 2183 if (!iwl_is_init(priv)) {
b481de9c
ZY
2184 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2185 STATUS_RF_KILL_HW |
9788864e
RC
2186 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2187 STATUS_GEO_CONFIGURED |
052ec3f1
MA
2188 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2189 STATUS_EXIT_PENDING;
b481de9c
ZY
2190 goto exit;
2191 }
2192
6da3a13e 2193 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2194 * bit and continue taking the NIC down. */
b481de9c
ZY
2195 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2196 STATUS_RF_KILL_HW |
9788864e
RC
2197 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2198 STATUS_GEO_CONFIGURED |
b481de9c 2199 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
2200 STATUS_FW_ERROR |
2201 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2202 STATUS_EXIT_PENDING;
b481de9c 2203
ef850d7c
MA
2204 /* device going down, Stop using ICT table */
2205 iwl_disable_ict(priv);
b481de9c 2206
da1bc453 2207 iwl_txq_ctx_stop(priv);
b3bbacb7 2208 iwl_rxq_stop(priv);
b481de9c 2209
309e731a
BC
2210 /* Power-down device's busmaster DMA clocks */
2211 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2212 udelay(5);
2213
309e731a
BC
2214 /* Make sure (redundant) we've released our request to stay awake */
2215 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2216
4d2ccdb9
BC
2217 /* Stop the device, and put it in low power state */
2218 priv->cfg->ops->lib->apm_ops.stop(priv);
2219
b481de9c 2220 exit:
885ba202 2221 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2222
2223 if (priv->ibss_beacon)
2224 dev_kfree_skb(priv->ibss_beacon);
2225 priv->ibss_beacon = NULL;
2226
2227 /* clear out any free frames */
fcab423d 2228 iwl_clear_free_frames(priv);
b481de9c
ZY
2229}
2230
5b9f8cd3 2231static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2232{
2233 mutex_lock(&priv->mutex);
5b9f8cd3 2234 __iwl_down(priv);
b481de9c 2235 mutex_unlock(&priv->mutex);
b24d22b1 2236
4e39317d 2237 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2238}
2239
086ed117
MA
2240#define HW_READY_TIMEOUT (50)
2241
2242static int iwl_set_hw_ready(struct iwl_priv *priv)
2243{
2244 int ret = 0;
2245
2246 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2247 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2248
2249 /* See if we got it */
2250 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2251 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2252 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2253 HW_READY_TIMEOUT);
2254 if (ret != -ETIMEDOUT)
2255 priv->hw_ready = true;
2256 else
2257 priv->hw_ready = false;
2258
2259 IWL_DEBUG_INFO(priv, "hardware %s\n",
2260 (priv->hw_ready == 1) ? "ready" : "not ready");
2261 return ret;
2262}
2263
2264static int iwl_prepare_card_hw(struct iwl_priv *priv)
2265{
2266 int ret = 0;
2267
2268 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
2269
3354a0f6
MA
2270 ret = iwl_set_hw_ready(priv);
2271 if (priv->hw_ready)
2272 return ret;
2273
2274 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2275 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2276 CSR_HW_IF_CONFIG_REG_PREPARE);
2277
2278 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2279 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2280 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2281
3354a0f6 2282 /* HW should be ready by now, check again. */
086ed117
MA
2283 if (ret != -ETIMEDOUT)
2284 iwl_set_hw_ready(priv);
2285
2286 return ret;
2287}
2288
b481de9c
ZY
2289#define MAX_HW_RESTARTS 5
2290
5b9f8cd3 2291static int __iwl_up(struct iwl_priv *priv)
b481de9c 2292{
57aab75a
TW
2293 int i;
2294 int ret;
b481de9c
ZY
2295
2296 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2297 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2298 return -EIO;
2299 }
2300
e903fbd4 2301 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2302 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2303 return -EIO;
2304 }
2305
086ed117
MA
2306 iwl_prepare_card_hw(priv);
2307
2308 if (!priv->hw_ready) {
2309 IWL_WARN(priv, "Exit HW not ready\n");
2310 return -EIO;
2311 }
2312
e655b9f0 2313 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2314 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2315 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2316 else
e655b9f0 2317 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2318
c1842d61 2319 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2320 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2321
5b9f8cd3 2322 iwl_enable_interrupts(priv);
a60e77e5 2323 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2324 return 0;
b481de9c
ZY
2325 }
2326
3395f6e9 2327 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2328
1053d35f 2329 ret = iwl_hw_nic_init(priv);
57aab75a 2330 if (ret) {
15b1687c 2331 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2332 return ret;
b481de9c
ZY
2333 }
2334
2335 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2336 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2337 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2338 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2339
2340 /* clear (again), then enable host interrupts */
3395f6e9 2341 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2342 iwl_enable_interrupts(priv);
b481de9c
ZY
2343
2344 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2345 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2346 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2347
2348 /* Copy original ucode data image from disk into backup cache.
2349 * This will be used to initialize the on-board processor's
2350 * data SRAM for a clean start when the runtime program first loads. */
2351 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2352 priv->ucode_data.len);
b481de9c 2353
b481de9c
ZY
2354 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2355
c587de0b 2356 iwl_clear_stations_table(priv);
b481de9c
ZY
2357
2358 /* load bootstrap state machine,
2359 * load bootstrap program into processor's memory,
2360 * prepare to load the "initialize" uCode */
57aab75a 2361 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2362
57aab75a 2363 if (ret) {
15b1687c
WT
2364 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2365 ret);
b481de9c
ZY
2366 continue;
2367 }
2368
2369 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2370 iwl_nic_start(priv);
b481de9c 2371
e1623446 2372 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2373
2374 return 0;
2375 }
2376
2377 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2378 __iwl_down(priv);
64e72c3e 2379 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2380
2381 /* tried to restart and config the device for as long as our
2382 * patience could withstand */
15b1687c 2383 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2384 return -EIO;
2385}
2386
2387
2388/*****************************************************************************
2389 *
2390 * Workqueue callbacks
2391 *
2392 *****************************************************************************/
2393
4a4a9e81 2394static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2395{
c79dd5b5
TW
2396 struct iwl_priv *priv =
2397 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2398
2399 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2400 return;
2401
2402 mutex_lock(&priv->mutex);
f3ccc08c 2403 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2404 mutex_unlock(&priv->mutex);
2405}
2406
4a4a9e81 2407static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2408{
c79dd5b5
TW
2409 struct iwl_priv *priv =
2410 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2411
2412 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2413 return;
2414
258c44a0
MA
2415 /* enable dram interrupt */
2416 iwl_reset_ict(priv);
2417
b481de9c 2418 mutex_lock(&priv->mutex);
4a4a9e81 2419 iwl_alive_start(priv);
b481de9c
ZY
2420 mutex_unlock(&priv->mutex);
2421}
2422
16e727e8
EG
2423static void iwl_bg_run_time_calib_work(struct work_struct *work)
2424{
2425 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2426 run_time_calib_work);
2427
2428 mutex_lock(&priv->mutex);
2429
2430 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2431 test_bit(STATUS_SCANNING, &priv->status)) {
2432 mutex_unlock(&priv->mutex);
2433 return;
2434 }
2435
2436 if (priv->start_calib) {
2437 iwl_chain_noise_calibration(priv, &priv->statistics);
2438
2439 iwl_sensitivity_calibration(priv, &priv->statistics);
2440 }
2441
2442 mutex_unlock(&priv->mutex);
2443 return;
2444}
2445
5b9f8cd3 2446static void iwl_bg_up(struct work_struct *data)
b481de9c 2447{
c79dd5b5 2448 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2449
2450 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2451 return;
2452
2453 mutex_lock(&priv->mutex);
5b9f8cd3 2454 __iwl_up(priv);
b481de9c
ZY
2455 mutex_unlock(&priv->mutex);
2456}
2457
5b9f8cd3 2458static void iwl_bg_restart(struct work_struct *data)
b481de9c 2459{
c79dd5b5 2460 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2461
2462 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2463 return;
2464
19cc1087
JB
2465 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2466 mutex_lock(&priv->mutex);
2467 priv->vif = NULL;
2468 priv->is_open = 0;
2469 mutex_unlock(&priv->mutex);
2470 iwl_down(priv);
2471 ieee80211_restart_hw(priv->hw);
2472 } else {
2473 iwl_down(priv);
2474 queue_work(priv->workqueue, &priv->up);
2475 }
b481de9c
ZY
2476}
2477
5b9f8cd3 2478static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2479{
c79dd5b5
TW
2480 struct iwl_priv *priv =
2481 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2482
2483 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2484 return;
2485
2486 mutex_lock(&priv->mutex);
a55360e4 2487 iwl_rx_replenish(priv);
b481de9c
ZY
2488 mutex_unlock(&priv->mutex);
2489}
2490
7878a5a4
MA
2491#define IWL_DELAY_NEXT_SCAN (HZ*2)
2492
5bbe233b 2493void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2494{
b481de9c 2495 struct ieee80211_conf *conf = NULL;
857485c0 2496 int ret = 0;
1ff50bda 2497 unsigned long flags;
b481de9c 2498
05c914fe 2499 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2500 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2501 return;
2502 }
2503
e1623446 2504 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2505 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2506
2507
2508 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2509 return;
2510
b481de9c 2511
508e32e1 2512 if (!priv->vif || !priv->is_open)
948c171c 2513 return;
508e32e1 2514
2a421b91 2515 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2516
b481de9c
ZY
2517 conf = ieee80211_get_hw_conf(priv->hw);
2518
2519 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2520 iwlcore_commit_rxon(priv);
b481de9c 2521
3195c1f3 2522 iwl_setup_rxon_timing(priv);
857485c0 2523 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2524 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2525 if (ret)
39aadf8c 2526 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2527 "Attempting to continue.\n");
2528
2529 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2530
42eb7c64 2531 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2532
45823531
AK
2533 if (priv->cfg->ops->hcmd->set_rxon_chain)
2534 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2535
b481de9c
ZY
2536 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2537
e1623446 2538 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2539 priv->assoc_id, priv->beacon_int);
2540
2541 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2542 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2543 else
2544 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2545
2546 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2547 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2548 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2549 else
2550 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2551
05c914fe 2552 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2553 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2554
2555 }
2556
e0158e61 2557 iwlcore_commit_rxon(priv);
b481de9c
ZY
2558
2559 switch (priv->iw_mode) {
05c914fe 2560 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2561 break;
2562
05c914fe 2563 case NL80211_IFTYPE_ADHOC:
b481de9c 2564
c46fbefa
AK
2565 /* assume default assoc id */
2566 priv->assoc_id = 1;
b481de9c 2567
4f40e4d9 2568 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2569 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2570
2571 break;
2572
2573 default:
15b1687c 2574 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2575 __func__, priv->iw_mode);
b481de9c
ZY
2576 break;
2577 }
2578
05c914fe 2579 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2580 priv->assoc_station_added = 1;
2581
1ff50bda
EG
2582 spin_lock_irqsave(&priv->lock, flags);
2583 iwl_activate_qos(priv, 0);
2584 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2585
04816448
GE
2586 /* the chain noise calibration will enabled PM upon completion
2587 * If chain noise has already been run, then we need to enable
2588 * power management here */
2589 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2590 iwl_power_update_mode(priv, false);
c90a74ba
EG
2591
2592 /* Enable Rx differential gain and sensitivity calibrations */
2593 iwl_chain_noise_reset(priv);
2594 priv->start_calib = 1;
2595
508e32e1
RC
2596}
2597
b481de9c
ZY
2598/*****************************************************************************
2599 *
2600 * mac80211 entry point functions
2601 *
2602 *****************************************************************************/
2603
154b25ce 2604#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2605
f0b6e2e8
RC
2606/*
2607 * Not a mac80211 entry point function, but it fits in with all the
2608 * other mac80211 functions grouped here.
2609 */
2610static int iwl_setup_mac(struct iwl_priv *priv)
2611{
2612 int ret;
2613 struct ieee80211_hw *hw = priv->hw;
2614 hw->rate_control_algorithm = "iwl-agn-rs";
2615
2616 /* Tell mac80211 our characteristics */
2617 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2618 IEEE80211_HW_NOISE_DBM |
2619 IEEE80211_HW_AMPDU_AGGREGATION |
2620 IEEE80211_HW_SPECTRUM_MGMT;
2621
2622 if (!priv->cfg->broken_powersave)
2623 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2624 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2625
ba37a3d0
JB
2626 if (priv->cfg->sku & IWL_SKU_N)
2627 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2628 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2629
8d9698b3 2630 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2631 hw->wiphy->interface_modes =
2632 BIT(NL80211_IFTYPE_STATION) |
2633 BIT(NL80211_IFTYPE_ADHOC);
2634
5be83de5
JB
2635 hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
2636 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC
2637
2638 /*
2639 * For now, disable PS by default because it affects
2640 * RX performance significantly.
2641 */
5be83de5 2642 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8
RC
2643
2644 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2645 /* we create the 802.11 header and a zero-length SSID element */
2646 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2647
2648 /* Default value; 4 EDCA QOS priorities */
2649 hw->queues = 4;
2650
2651 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2652
2653 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2654 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2655 &priv->bands[IEEE80211_BAND_2GHZ];
2656 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2657 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2658 &priv->bands[IEEE80211_BAND_5GHZ];
2659
2660 ret = ieee80211_register_hw(priv->hw);
2661 if (ret) {
2662 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2663 return ret;
2664 }
2665 priv->mac80211_registered = 1;
2666
2667 return 0;
2668}
2669
2670
5b9f8cd3 2671static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2672{
c79dd5b5 2673 struct iwl_priv *priv = hw->priv;
5a66926a 2674 int ret;
b481de9c 2675
e1623446 2676 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2677
2678 /* we should be verifying the device is ready to be opened */
2679 mutex_lock(&priv->mutex);
2680
5a66926a
ZY
2681 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2682 * ucode filename and max sizes are card-specific. */
b481de9c 2683
5a66926a 2684 if (!priv->ucode_code.len) {
5b9f8cd3 2685 ret = iwl_read_ucode(priv);
5a66926a 2686 if (ret) {
15b1687c 2687 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2688 mutex_unlock(&priv->mutex);
6cd0b1cb 2689 return ret;
5a66926a
ZY
2690 }
2691 }
b481de9c 2692
5b9f8cd3 2693 ret = __iwl_up(priv);
5a66926a 2694
b481de9c 2695 mutex_unlock(&priv->mutex);
5a66926a 2696
e655b9f0 2697 if (ret)
6cd0b1cb 2698 return ret;
e655b9f0 2699
c1842d61
TW
2700 if (iwl_is_rfkill(priv))
2701 goto out;
2702
e1623446 2703 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2704
fe9b6b72 2705 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2706 * mac80211 will not be run successfully. */
154b25ce
EG
2707 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2708 test_bit(STATUS_READY, &priv->status),
2709 UCODE_READY_TIMEOUT);
2710 if (!ret) {
2711 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2712 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2713 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2714 return -ETIMEDOUT;
5a66926a 2715 }
fe9b6b72 2716 }
0a078ffa 2717
e932a609
JB
2718 iwl_led_start(priv);
2719
c1842d61 2720out:
0a078ffa 2721 priv->is_open = 1;
e1623446 2722 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2723 return 0;
2724}
2725
5b9f8cd3 2726static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2727{
c79dd5b5 2728 struct iwl_priv *priv = hw->priv;
b481de9c 2729
e1623446 2730 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2731
19cc1087 2732 if (!priv->is_open)
e655b9f0 2733 return;
e655b9f0 2734
b481de9c 2735 priv->is_open = 0;
5a66926a 2736
5bddf549 2737 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2738 /* stop mac, cancel any scan request and clear
2739 * RXON_FILTER_ASSOC_MSK BIT
2740 */
5a66926a 2741 mutex_lock(&priv->mutex);
2a421b91 2742 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2743 mutex_unlock(&priv->mutex);
fde3571f
MA
2744 }
2745
5b9f8cd3 2746 iwl_down(priv);
5a66926a
ZY
2747
2748 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2749
2750 /* enable interrupts again in order to receive rfkill changes */
2751 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2752 iwl_enable_interrupts(priv);
948c171c 2753
e1623446 2754 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2755}
2756
5b9f8cd3 2757static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2758{
c79dd5b5 2759 struct iwl_priv *priv = hw->priv;
b481de9c 2760
e1623446 2761 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2762
e1623446 2763 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2764 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2765
e039fa4a 2766 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2767 dev_kfree_skb_any(skb);
2768
e1623446 2769 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2770 return NETDEV_TX_OK;
b481de9c
ZY
2771}
2772
60690a6a 2773void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2774{
857485c0 2775 int ret = 0;
1ff50bda 2776 unsigned long flags;
b481de9c 2777
d986bcd1 2778 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2779 return;
2780
2781 /* The following should be done only at AP bring up */
3195c1f3 2782 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2783
2784 /* RXON - unassoc (to set timing command) */
2785 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2786 iwlcore_commit_rxon(priv);
b481de9c
ZY
2787
2788 /* RXON Timing */
3195c1f3 2789 iwl_setup_rxon_timing(priv);
857485c0 2790 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2791 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2792 if (ret)
39aadf8c 2793 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2794 "Attempting to continue.\n");
2795
f513dfff
DH
2796 /* AP has all antennas */
2797 priv->chain_noise_data.active_chains =
2798 priv->hw_params.valid_rx_ant;
2799 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK
2800 if (priv->cfg->ops->hcmd->set_rxon_chain)
2801 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2802
2803 /* FIXME: what should be the assoc_id for AP? */
2804 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2805 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2806 priv->staging_rxon.flags |=
2807 RXON_FLG_SHORT_PREAMBLE_MSK;
2808 else
2809 priv->staging_rxon.flags &=
2810 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2811
2812 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2813 if (priv->assoc_capability &
2814 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2815 priv->staging_rxon.flags |=
2816 RXON_FLG_SHORT_SLOT_MSK;
2817 else
2818 priv->staging_rxon.flags &=
2819 ~RXON_FLG_SHORT_SLOT_MSK;
2820
05c914fe 2821 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2822 priv->staging_rxon.flags &=
2823 ~RXON_FLG_SHORT_SLOT_MSK;
2824 }
2825 /* restore RXON assoc */
2826 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2827 iwlcore_commit_rxon(priv);
f513dfff 2828 iwl_reset_qos(priv);
1ff50bda
EG
2829 spin_lock_irqsave(&priv->lock, flags);
2830 iwl_activate_qos(priv, 1);
2831 spin_unlock_irqrestore(&priv->lock, flags);
9a9ca65f 2832 iwl_add_bcast_station(priv);
e1493deb 2833 }
5b9f8cd3 2834 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2835
2836 /* FIXME - we need to add code here to detect a totally new
2837 * configuration, reset the AP, unassoc, rxon timing, assoc,
2838 * clear sta table, add BCAST sta... */
2839}
2840
5b9f8cd3 2841static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2842 struct ieee80211_key_conf *keyconf, const u8 *addr,
2843 u32 iv32, u16 *phase1key)
2844{
ab885f8c 2845
9f58671e 2846 struct iwl_priv *priv = hw->priv;
e1623446 2847 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2848
9f58671e 2849 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2850
e1623446 2851 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2852}
2853
5b9f8cd3 2854static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2855 struct ieee80211_vif *vif,
2856 struct ieee80211_sta *sta,
b481de9c
ZY
2857 struct ieee80211_key_conf *key)
2858{
c79dd5b5 2859 struct iwl_priv *priv = hw->priv;
42986796
WT
2860 const u8 *addr;
2861 int ret;
2862 u8 sta_id;
2863 bool is_default_wep_key = false;
b481de9c 2864
e1623446 2865 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2866
90e8e424 2867 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2868 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2869 return -EOPNOTSUPP;
2870 }
42986796 2871 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2872 sta_id = iwl_find_station(priv, addr);
6974e363 2873 if (sta_id == IWL_INVALID_STATION) {
e1623446 2874 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2875 addr);
6974e363 2876 return -EINVAL;
b481de9c 2877
deb09c43 2878 }
b481de9c 2879
6974e363 2880 mutex_lock(&priv->mutex);
2a421b91 2881 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2882 mutex_unlock(&priv->mutex);
2883
2884 /* If we are getting WEP group key and we didn't receive any key mapping
2885 * so far, we are in legacy wep mode (group key only), otherwise we are
2886 * in 1X mode.
2887 * In legacy wep mode, we use another host command to the uCode */
5425e490 2888 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2889 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2890 if (cmd == SET_KEY)
2891 is_default_wep_key = !priv->key_mapping_key;
2892 else
ccc038ab
EG
2893 is_default_wep_key =
2894 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2895 }
052c4b9f 2896
b481de9c 2897 switch (cmd) {
deb09c43 2898 case SET_KEY:
6974e363
EG
2899 if (is_default_wep_key)
2900 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2901 else
7480513f 2902 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2903
e1623446 2904 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2905 break;
2906 case DISABLE_KEY:
6974e363
EG
2907 if (is_default_wep_key)
2908 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2909 else
3ec47732 2910 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2911
e1623446 2912 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2913 break;
2914 default:
deb09c43 2915 ret = -EINVAL;
b481de9c
ZY
2916 }
2917
e1623446 2918 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2919
deb09c43 2920 return ret;
b481de9c
ZY
2921}
2922
5b9f8cd3 2923static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2924 struct ieee80211_vif *vif,
d783b061 2925 enum ieee80211_ampdu_mlme_action action,
17741cdc 2926 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2927{
2928 struct iwl_priv *priv = hw->priv;
5c2207c6 2929 int ret;
d783b061 2930
e1623446 2931 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2932 sta->addr, tid);
d783b061
TW
2933
2934 if (!(priv->cfg->sku & IWL_SKU_N))
2935 return -EACCES;
2936
2937 switch (action) {
2938 case IEEE80211_AMPDU_RX_START:
e1623446 2939 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2940 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2941 case IEEE80211_AMPDU_RX_STOP:
e1623446 2942 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2943 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2944 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2945 return 0;
2946 else
2947 return ret;
d783b061 2948 case IEEE80211_AMPDU_TX_START:
e1623446 2949 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2950 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2951 case IEEE80211_AMPDU_TX_STOP:
e1623446 2952 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2953 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2954 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2955 return 0;
2956 else
2957 return ret;
d783b061 2958 default:
e1623446 2959 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2960 return -EINVAL;
2961 break;
2962 }
2963 return 0;
2964}
9f58671e 2965
5b9f8cd3 2966static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2967 struct ieee80211_low_level_stats *stats)
2968{
bf403db8
EK
2969 struct iwl_priv *priv = hw->priv;
2970
2971 priv = hw->priv;
e1623446
TW
2972 IWL_DEBUG_MAC80211(priv, "enter\n");
2973 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2974
2975 return 0;
2976}
2977
6ab10ff8
JB
2978static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
2979 struct ieee80211_vif *vif,
2980 enum sta_notify_cmd cmd,
2981 struct ieee80211_sta *sta)
2982{
2983 struct iwl_priv *priv = hw->priv;
2984 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2985 int sta_id;
2986
2987 /*
2988 * TODO: We really should use this callback to
2989 * actually maintain the station table in
2990 * the device.
2991 */
2992
2993 switch (cmd) {
2994 case STA_NOTIFY_ADD:
2995 atomic_set(&sta_priv->pending_frames, 0);
2996 if (vif->type == NL80211_IFTYPE_AP)
2997 sta_priv->client = true;
2998 break;
2999 case STA_NOTIFY_SLEEP:
3000 WARN_ON(!sta_priv->client);
3001 sta_priv->asleep = true;
3002 if (atomic_read(&sta_priv->pending_frames) > 0)
3003 ieee80211_sta_block_awake(hw, sta, true);
3004 break;
3005 case STA_NOTIFY_AWAKE:
3006 WARN_ON(!sta_priv->client);
3007 sta_priv->asleep = false;
3008 sta_id = iwl_find_station(priv, sta->addr);
3009 if (sta_id != IWL_INVALID_STATION)
3010 iwl_sta_modify_ps_wake(priv, sta_id);
3011 break;
3012 default:
3013 break;
3014 }
3015}
3016
b481de9c
ZY
3017/*****************************************************************************
3018 *
3019 * sysfs attributes
3020 *
3021 *****************************************************************************/
3022
0a6857e7 3023#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3024
3025/*
3026 * The following adds a new attribute to the sysfs representation
c3a739fa 3027 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
3028 * used for controlling the debug level.
3029 *
3030 * See the level definitions in iwl for details.
a562a9dd 3031 *
3d816c77
RC
3032 * The debug_level being managed using sysfs below is a per device debug
3033 * level that is used instead of the global debug level if it (the per
3034 * device debug level) is set.
b481de9c 3035 */
8cf769c6
EK
3036static ssize_t show_debug_level(struct device *d,
3037 struct device_attribute *attr, char *buf)
b481de9c 3038{
3d816c77
RC
3039 struct iwl_priv *priv = dev_get_drvdata(d);
3040 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3041}
8cf769c6
EK
3042static ssize_t store_debug_level(struct device *d,
3043 struct device_attribute *attr,
b481de9c
ZY
3044 const char *buf, size_t count)
3045{
928841b1 3046 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3047 unsigned long val;
3048 int ret;
b481de9c 3049
9257746f
TW
3050 ret = strict_strtoul(buf, 0, &val);
3051 if (ret)
978785a3 3052 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3053 else {
3d816c77 3054 priv->debug_level = val;
20594eb0
WYG
3055 if (iwl_alloc_traffic_mem(priv))
3056 IWL_ERR(priv,
3057 "Not enough memory to generate traffic log\n");
3058 }
b481de9c
ZY
3059 return strnlen(buf, count);
3060}
3061
8cf769c6
EK
3062static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3063 show_debug_level, store_debug_level);
3064
b481de9c 3065
0a6857e7 3066#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3067
b481de9c
ZY
3068
3069static ssize_t show_temperature(struct device *d,
3070 struct device_attribute *attr, char *buf)
3071{
928841b1 3072 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3073
fee1247a 3074 if (!iwl_is_alive(priv))
b481de9c
ZY
3075 return -EAGAIN;
3076
91dbc5bd 3077 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
3078}
3079
3080static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3081
b481de9c
ZY
3082static ssize_t show_tx_power(struct device *d,
3083 struct device_attribute *attr, char *buf)
3084{
928841b1 3085 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
3086
3087 if (!iwl_is_ready_rf(priv))
3088 return sprintf(buf, "off\n");
3089 else
3090 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3091}
3092
3093static ssize_t store_tx_power(struct device *d,
3094 struct device_attribute *attr,
3095 const char *buf, size_t count)
3096{
928841b1 3097 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3098 unsigned long val;
3099 int ret;
b481de9c 3100
9257746f
TW
3101 ret = strict_strtoul(buf, 10, &val);
3102 if (ret)
978785a3 3103 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
3104 else {
3105 ret = iwl_set_tx_power(priv, val, false);
3106 if (ret)
3107 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3108 ret);
3109 else
3110 ret = count;
3111 }
3112 return ret;
b481de9c
ZY
3113}
3114
3115static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3116
3117static ssize_t show_flags(struct device *d,
3118 struct device_attribute *attr, char *buf)
3119{
928841b1 3120 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3121
3122 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
3123}
3124
3125static ssize_t store_flags(struct device *d,
3126 struct device_attribute *attr,
3127 const char *buf, size_t count)
3128{
928841b1 3129 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3130 unsigned long val;
3131 u32 flags;
3132 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 3133 if (ret)
9257746f
TW
3134 return ret;
3135 flags = (u32)val;
b481de9c
ZY
3136
3137 mutex_lock(&priv->mutex);
3138 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
3139 /* Cancel any currently running scans... */
2a421b91 3140 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3141 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3142 else {
e1623446 3143 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 3144 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3145 iwlcore_commit_rxon(priv);
b481de9c
ZY
3146 }
3147 }
3148 mutex_unlock(&priv->mutex);
3149
3150 return count;
3151}
3152
3153static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3154
3155static ssize_t show_filter_flags(struct device *d,
3156 struct device_attribute *attr, char *buf)
3157{
928841b1 3158 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3159
3160 return sprintf(buf, "0x%04X\n",
3161 le32_to_cpu(priv->active_rxon.filter_flags));
3162}
3163
3164static ssize_t store_filter_flags(struct device *d,
3165 struct device_attribute *attr,
3166 const char *buf, size_t count)
3167{
928841b1 3168 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3169 unsigned long val;
3170 u32 filter_flags;
3171 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 3172 if (ret)
9257746f
TW
3173 return ret;
3174 filter_flags = (u32)val;
b481de9c
ZY
3175
3176 mutex_lock(&priv->mutex);
3177 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
3178 /* Cancel any currently running scans... */
2a421b91 3179 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3180 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3181 else {
e1623446 3182 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
3183 "0x%04X\n", filter_flags);
3184 priv->staging_rxon.filter_flags =
3185 cpu_to_le32(filter_flags);
e0158e61 3186 iwlcore_commit_rxon(priv);
b481de9c
ZY
3187 }
3188 }
3189 mutex_unlock(&priv->mutex);
3190
3191 return count;
3192}
3193
3194static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3195 store_filter_flags);
3196
b481de9c
ZY
3197
3198static ssize_t show_statistics(struct device *d,
3199 struct device_attribute *attr, char *buf)
3200{
c79dd5b5 3201 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 3202 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 3203 u32 len = 0, ofs = 0;
3ac7f146 3204 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
3205 int rc = 0;
3206
fee1247a 3207 if (!iwl_is_alive(priv))
b481de9c
ZY
3208 return -EAGAIN;
3209
3210 mutex_lock(&priv->mutex);
ef8d5529 3211 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
3212 mutex_unlock(&priv->mutex);
3213
3214 if (rc) {
3215 len = sprintf(buf,
3216 "Error sending statistics request: 0x%08X\n", rc);
3217 return len;
3218 }
3219
3220 while (size && (PAGE_SIZE - len)) {
3221 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3222 PAGE_SIZE - len, 1);
3223 len = strlen(buf);
3224 if (PAGE_SIZE - len)
3225 buf[len++] = '\n';
3226
3227 ofs += 16;
3228 size -= min(size, 16U);
3229 }
3230
3231 return len;
3232}
3233
3234static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3235
01abfbb2
WYG
3236static ssize_t show_rts_ht_protection(struct device *d,
3237 struct device_attribute *attr, char *buf)
3238{
3239 struct iwl_priv *priv = dev_get_drvdata(d);
3240
3241 return sprintf(buf, "%s\n",
3242 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3243}
3244
3245static ssize_t store_rts_ht_protection(struct device *d,
3246 struct device_attribute *attr,
3247 const char *buf, size_t count)
3248{
3249 struct iwl_priv *priv = dev_get_drvdata(d);
3250 unsigned long val;
3251 int ret;
3252
3253 ret = strict_strtoul(buf, 10, &val);
3254 if (ret)
3255 IWL_INFO(priv, "Input is not in decimal form.\n");
3256 else {
3257 if (!iwl_is_associated(priv))
3258 priv->cfg->use_rts_for_ht = val ? true : false;
3259 else
3260 IWL_ERR(priv, "Sta associated with AP - "
3261 "Change protection mechanism is not allowed\n");
3262 ret = count;
3263 }
3264 return ret;
3265}
3266
3267static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3268 show_rts_ht_protection, store_rts_ht_protection);
3269
b481de9c 3270
b481de9c
ZY
3271/*****************************************************************************
3272 *
3273 * driver setup and teardown
3274 *
3275 *****************************************************************************/
3276
4e39317d 3277static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3278{
d21050c7 3279 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3280
3281 init_waitqueue_head(&priv->wait_command_queue);
3282
5b9f8cd3
EG
3283 INIT_WORK(&priv->up, iwl_bg_up);
3284 INIT_WORK(&priv->restart, iwl_bg_restart);
3285 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3286 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3287 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
3288 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3289 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3290
2a421b91 3291 iwl_setup_scan_deferred_work(priv);
bb8c093b 3292
4e39317d
EG
3293 if (priv->cfg->ops->lib->setup_deferred_work)
3294 priv->cfg->ops->lib->setup_deferred_work(priv);
3295
3296 init_timer(&priv->statistics_periodic);
3297 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3298 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3299
a9e1cb6a
WYG
3300 init_timer(&priv->ucode_trace);
3301 priv->ucode_trace.data = (unsigned long)priv;
3302 priv->ucode_trace.function = iwl_bg_ucode_trace;
3303
ef850d7c
MA
3304 if (!priv->cfg->use_isr_legacy)
3305 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3306 iwl_irq_tasklet, (unsigned long)priv);
3307 else
3308 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3309 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
3310}
3311
4e39317d 3312static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3313{
4e39317d
EG
3314 if (priv->cfg->ops->lib->cancel_deferred_work)
3315 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3316
3ae6a054 3317 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3318 cancel_delayed_work(&priv->scan_check);
3319 cancel_delayed_work(&priv->alive_start);
b481de9c 3320 cancel_work_sync(&priv->beacon_update);
4e39317d 3321 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3322 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY
3323}
3324
89f186a8
RC
3325static void iwl_init_hw_rates(struct iwl_priv *priv,
3326 struct ieee80211_rate *rates)
3327{
3328 int i;
3329
3330 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3331 rates[i].bitrate = iwl_rates[i].ieee * 5;
3332 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3333 rates[i].hw_value_short = i;
3334 rates[i].flags = 0;
3335 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3336 /*
3337 * If CCK != 1M then set short preamble rate flag.
3338 */
3339 rates[i].flags |=
3340 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3341 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3342 }
3343 }
3344}
3345
3346static int iwl_init_drv(struct iwl_priv *priv)
3347{
3348 int ret;
3349
3350 priv->ibss_beacon = NULL;
3351
89f186a8
RC
3352 spin_lock_init(&priv->sta_lock);
3353 spin_lock_init(&priv->hcmd_lock);
3354
3355 INIT_LIST_HEAD(&priv->free_frames);
3356
3357 mutex_init(&priv->mutex);
3358
3359 /* Clear the driver's (not device's) station table */
3360 iwl_clear_stations_table(priv);
3361
3362 priv->ieee_channels = NULL;
3363 priv->ieee_rates = NULL;
3364 priv->band = IEEE80211_BAND_2GHZ;
3365
3366 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3367 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
89f186a8
RC
3368
3369 /* Choose which receivers/antennas to use */
3370 if (priv->cfg->ops->hcmd->set_rxon_chain)
3371 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3372
3373 iwl_init_scan_params(priv);
3374
3375 iwl_reset_qos(priv);
3376
3377 priv->qos_data.qos_active = 0;
3378 priv->qos_data.qos_cap.val = 0;
3379
3380 priv->rates_mask = IWL_RATES_MASK;
3381 /* Set the tx_power_user_lmt to the lowest power level
3382 * this value will get overwritten by channel max power avg
3383 * from eeprom */
3384 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3385
3386 ret = iwl_init_channel_map(priv);
3387 if (ret) {
3388 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3389 goto err;
3390 }
3391
3392 ret = iwlcore_init_geos(priv);
3393 if (ret) {
3394 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3395 goto err_free_channel_map;
3396 }
3397 iwl_init_hw_rates(priv, priv->ieee_rates);
3398
3399 return 0;
3400
3401err_free_channel_map:
3402 iwl_free_channel_map(priv);
3403err:
3404 return ret;
3405}
3406
3407static void iwl_uninit_drv(struct iwl_priv *priv)
3408{
3409 iwl_calib_free_results(priv);
3410 iwlcore_free_geos(priv);
3411 iwl_free_channel_map(priv);
3412 kfree(priv->scan);
3413}
3414
5b9f8cd3 3415static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
3416 &dev_attr_flags.attr,
3417 &dev_attr_filter_flags.attr,
b481de9c 3418 &dev_attr_statistics.attr,
b481de9c 3419 &dev_attr_temperature.attr,
b481de9c 3420 &dev_attr_tx_power.attr,
01abfbb2 3421 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3422#ifdef CONFIG_IWLWIFI_DEBUG
3423 &dev_attr_debug_level.attr,
3424#endif
b481de9c
ZY
3425 NULL
3426};
3427
5b9f8cd3 3428static struct attribute_group iwl_attribute_group = {
b481de9c 3429 .name = NULL, /* put in device directory */
5b9f8cd3 3430 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3431};
3432
5b9f8cd3
EG
3433static struct ieee80211_ops iwl_hw_ops = {
3434 .tx = iwl_mac_tx,
3435 .start = iwl_mac_start,
3436 .stop = iwl_mac_stop,
3437 .add_interface = iwl_mac_add_interface,
3438 .remove_interface = iwl_mac_remove_interface,
3439 .config = iwl_mac_config,
5b9f8cd3
EG
3440 .configure_filter = iwl_configure_filter,
3441 .set_key = iwl_mac_set_key,
3442 .update_tkip_key = iwl_mac_update_tkip_key,
3443 .get_stats = iwl_mac_get_stats,
3444 .get_tx_stats = iwl_mac_get_tx_stats,
3445 .conf_tx = iwl_mac_conf_tx,
3446 .reset_tsf = iwl_mac_reset_tsf,
3447 .bss_info_changed = iwl_bss_info_changed,
3448 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB
3449 .hw_scan = iwl_mac_hw_scan,
3450 .sta_notify = iwl_mac_sta_notify,
b481de9c
ZY
3451};
3452
5b9f8cd3 3453static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3454{
3455 int err = 0;
c79dd5b5 3456 struct iwl_priv *priv;
b481de9c 3457 struct ieee80211_hw *hw;
82b9a121 3458 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3459 unsigned long flags;
6cd0b1cb 3460 u16 pci_cmd;
b481de9c 3461
316c30d9
AK
3462 /************************
3463 * 1. Allocating HW data
3464 ************************/
3465
6440adb5
BC
3466 /* Disabling hardware scan means that mac80211 will perform scans
3467 * "the hard way", rather than using device's scan. */
1ea87396 3468 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3469 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3470 dev_printk(KERN_DEBUG, &(pdev->dev),
3471 "Disabling hw_scan\n");
5b9f8cd3 3472 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3473 }
3474
5b9f8cd3 3475 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3476 if (!hw) {
b481de9c
ZY
3477 err = -ENOMEM;
3478 goto out;
3479 }
1d0a082d
AK
3480 priv = hw->priv;
3481 /* At this point both hw and priv are allocated. */
3482
b481de9c
ZY
3483 SET_IEEE80211_DEV(hw, &pdev->dev);
3484
e1623446 3485 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3486 priv->cfg = cfg;
b481de9c 3487 priv->pci_dev = pdev;
40cefda9 3488 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3489
0a6857e7 3490#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3491 atomic_set(&priv->restrict_refcnt, 0);
3492#endif
20594eb0
WYG
3493 if (iwl_alloc_traffic_mem(priv))
3494 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3495
316c30d9
AK
3496 /**************************
3497 * 2. Initializing PCI bus
3498 **************************/
3499 if (pci_enable_device(pdev)) {
3500 err = -ENODEV;
3501 goto out_ieee80211_free_hw;
3502 }
3503
3504 pci_set_master(pdev);
3505
093d874c 3506 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3507 if (!err)
093d874c 3508 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3509 if (err) {
093d874c 3510 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3511 if (!err)
093d874c 3512 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3513 /* both attempts failed: */
316c30d9 3514 if (err) {
978785a3 3515 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3516 goto out_pci_disable_device;
cc2a8ea8 3517 }
316c30d9
AK
3518 }
3519
3520 err = pci_request_regions(pdev, DRV_NAME);
3521 if (err)
3522 goto out_pci_disable_device;
3523
3524 pci_set_drvdata(pdev, priv);
3525
316c30d9
AK
3526
3527 /***********************
3528 * 3. Read REV register
3529 ***********************/
3530 priv->hw_base = pci_iomap(pdev, 0, 0);
3531 if (!priv->hw_base) {
3532 err = -ENODEV;
3533 goto out_pci_release_regions;
3534 }
3535
e1623446 3536 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3537 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3538 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3539
731a29b7 3540 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
3541 * we should init now
3542 */
3543 spin_lock_init(&priv->reg_lock);
731a29b7 3544 spin_lock_init(&priv->lock);
b661c819 3545 iwl_hw_detect(priv);
978785a3 3546 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3547 priv->cfg->name, priv->hw_rev);
316c30d9 3548
e7b63581
TW
3549 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3550 * PCI Tx retries from interfering with C3 CPU state */
3551 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3552
086ed117
MA
3553 iwl_prepare_card_hw(priv);
3554 if (!priv->hw_ready) {
3555 IWL_WARN(priv, "Failed, HW not ready\n");
3556 goto out_iounmap;
3557 }
3558
91238714
TW
3559 /*****************
3560 * 4. Read EEPROM
3561 *****************/
316c30d9
AK
3562 /* Read the EEPROM */
3563 err = iwl_eeprom_init(priv);
3564 if (err) {
15b1687c 3565 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3566 goto out_iounmap;
3567 }
8614f360
TW
3568 err = iwl_eeprom_check_version(priv);
3569 if (err)
c8f16138 3570 goto out_free_eeprom;
8614f360 3571
02883017 3572 /* extract MAC Address */
316c30d9 3573 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3574 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3575 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3576
3577 /************************
3578 * 5. Setup HW constants
3579 ************************/
da154e30 3580 if (iwl_set_hw_params(priv)) {
15b1687c 3581 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3582 goto out_free_eeprom;
316c30d9
AK
3583 }
3584
3585 /*******************
6ba87956 3586 * 6. Setup priv
316c30d9 3587 *******************/
b481de9c 3588
6ba87956 3589 err = iwl_init_drv(priv);
bf85ea4f 3590 if (err)
399f4900 3591 goto out_free_eeprom;
bf85ea4f 3592 /* At this point both hw and priv are initialized. */
316c30d9 3593
316c30d9 3594 /********************
09f9bf79 3595 * 7. Setup services
316c30d9 3596 ********************/
0359facc 3597 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3598 iwl_disable_interrupts(priv);
0359facc 3599 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3600
6cd0b1cb
HS
3601 pci_enable_msi(priv->pci_dev);
3602
ef850d7c
MA
3603 iwl_alloc_isr_ict(priv);
3604 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3605 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3606 if (err) {
3607 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3608 goto out_disable_msi;
3609 }
5b9f8cd3 3610 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3611 if (err) {
15b1687c 3612 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3613 goto out_free_irq;
316c30d9
AK
3614 }
3615
4e39317d 3616 iwl_setup_deferred_work(priv);
653fa4a0 3617 iwl_setup_rx_handlers(priv);
316c30d9 3618
6ba87956 3619 /**********************************
09f9bf79 3620 * 8. Setup and register mac80211
6ba87956
TW
3621 **********************************/
3622
6cd0b1cb
HS
3623 /* enable interrupts if needed: hw bug w/a */
3624 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3625 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3626 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3627 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3628 }
3629
3630 iwl_enable_interrupts(priv);
3631
6ba87956
TW
3632 err = iwl_setup_mac(priv);
3633 if (err)
3634 goto out_remove_sysfs;
3635
3636 err = iwl_dbgfs_register(priv, DRV_NAME);
3637 if (err)
a75fbe8d 3638 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3639
6cd0b1cb
HS
3640 /* If platform's RF_KILL switch is NOT set to KILL */
3641 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3642 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3643 else
3644 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3645
a60e77e5
JB
3646 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3647 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3648
58d0f361 3649 iwl_power_initialize(priv);
39b73fb1 3650 iwl_tt_initialize(priv);
b481de9c
ZY
3651 return 0;
3652
316c30d9 3653 out_remove_sysfs:
c8f16138
RC
3654 destroy_workqueue(priv->workqueue);
3655 priv->workqueue = NULL;
5b9f8cd3 3656 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3657 out_free_irq:
3658 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3659 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3660 out_disable_msi:
3661 pci_disable_msi(priv->pci_dev);
6ba87956 3662 iwl_uninit_drv(priv);
073d3f5f
TW
3663 out_free_eeprom:
3664 iwl_eeprom_free(priv);
b481de9c
ZY
3665 out_iounmap:
3666 pci_iounmap(pdev, priv->hw_base);
3667 out_pci_release_regions:
316c30d9 3668 pci_set_drvdata(pdev, NULL);
623d563e 3669 pci_release_regions(pdev);
b481de9c
ZY
3670 out_pci_disable_device:
3671 pci_disable_device(pdev);
b481de9c 3672 out_ieee80211_free_hw:
20594eb0 3673 iwl_free_traffic_mem(priv);
d7c76f4c 3674 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3675 out:
3676 return err;
3677}
3678
5b9f8cd3 3679static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3680{
c79dd5b5 3681 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3682 unsigned long flags;
b481de9c
ZY
3683
3684 if (!priv)
3685 return;
3686
e1623446 3687 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3688
67249625 3689 iwl_dbgfs_unregister(priv);
5b9f8cd3 3690 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3691
5b9f8cd3
EG
3692 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3693 * to be called and iwl_down since we are removing the device
0b124c31
GG
3694 * we need to set STATUS_EXIT_PENDING bit.
3695 */
3696 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3697 if (priv->mac80211_registered) {
3698 ieee80211_unregister_hw(priv->hw);
3699 priv->mac80211_registered = 0;
0b124c31 3700 } else {
5b9f8cd3 3701 iwl_down(priv);
c4f55232
RR
3702 }
3703
c166b25a
BC
3704 /*
3705 * Make sure device is reset to low power before unloading driver.
3706 * This may be redundant with iwl_down(), but there are paths to
3707 * run iwl_down() without calling apm_ops.stop(), and there are
3708 * paths to avoid running iwl_down() at all before leaving driver.
3709 * This (inexpensive) call *makes sure* device is reset.
3710 */
3711 priv->cfg->ops->lib->apm_ops.stop(priv);
3712
39b73fb1
WYG
3713 iwl_tt_exit(priv);
3714
0359facc
MA
3715 /* make sure we flush any pending irq or
3716 * tasklet for the driver
3717 */
3718 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3719 iwl_disable_interrupts(priv);
0359facc
MA
3720 spin_unlock_irqrestore(&priv->lock, flags);
3721
3722 iwl_synchronize_irq(priv);
3723
5b9f8cd3 3724 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3725
3726 if (priv->rxq.bd)
a55360e4 3727 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3728 iwl_hw_txq_ctx_free(priv);
b481de9c 3729
c587de0b 3730 iwl_clear_stations_table(priv);
073d3f5f 3731 iwl_eeprom_free(priv);
b481de9c 3732
b481de9c 3733
948c171c
MA
3734 /*netif_stop_queue(dev); */
3735 flush_workqueue(priv->workqueue);
3736
5b9f8cd3 3737 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3738 * priv->workqueue... so we can't take down the workqueue
3739 * until now... */
3740 destroy_workqueue(priv->workqueue);
3741 priv->workqueue = NULL;
20594eb0 3742 iwl_free_traffic_mem(priv);
b481de9c 3743
6cd0b1cb
HS
3744 free_irq(priv->pci_dev->irq, priv);
3745 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3746 pci_iounmap(pdev, priv->hw_base);
3747 pci_release_regions(pdev);
3748 pci_disable_device(pdev);
3749 pci_set_drvdata(pdev, NULL);
3750
6ba87956 3751 iwl_uninit_drv(priv);
b481de9c 3752
ef850d7c
MA
3753 iwl_free_isr_ict(priv);
3754
b481de9c
ZY
3755 if (priv->ibss_beacon)
3756 dev_kfree_skb(priv->ibss_beacon);
3757
3758 ieee80211_free_hw(priv->hw);
3759}
3760
b481de9c
ZY
3761
3762/*****************************************************************************
3763 *
3764 * driver and module entry point
3765 *
3766 *****************************************************************************/
3767
fed9017e
RR
3768/* Hardware specific file defines the PCI IDs table for that hardware module */
3769static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3770#ifdef CONFIG_IWL4965
fed9017e
RR
3771 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3772 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3773#endif /* CONFIG_IWL4965 */
5a6a256e 3774#ifdef CONFIG_IWL5000
ac592574
WYG
3775/* 5100 Series WiFi */
3776 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3777 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3778 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3779 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3780 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3781 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3782 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3783 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3784 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3785 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3786 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3787 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3788 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3789 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3790 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3791 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3792 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3793 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3794 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3795 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3796 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3797 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3798 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3799 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3800
3801/* 5300 Series WiFi */
3802 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3803 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3804 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3805 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3806 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3807 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3808 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3809 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3810 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3811 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3812 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3813 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3814
3815/* 5350 Series WiFi/WiMax */
3816 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3817 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3818 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3819
3820/* 5150 Series Wifi/WiMax */
3821 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3822 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3823 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3824 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3825 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3826 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3827
3828 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3829 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3830 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3831 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG
3832
3833/* 6x00 Series */
5953a62e
WYG
3834 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3835 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3836 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3837 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3838 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3839 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3840 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3841 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3842 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3843 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3844
3845/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3846 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3847 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3848 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3849 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3850 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3851 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3852
77dcb6a9 3853/* 1000 Series WiFi */
4bd0914f
WYG
3854 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3855 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3856 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3857 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3858 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3859 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3860 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3861 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3862 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3863 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3864 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3865 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3866#endif /* CONFIG_IWL5000 */
7100e924 3867
fed9017e
RR
3868 {0}
3869};
3870MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3871
3872static struct pci_driver iwl_driver = {
b481de9c 3873 .name = DRV_NAME,
fed9017e 3874 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3875 .probe = iwl_pci_probe,
3876 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3877#ifdef CONFIG_PM
5b9f8cd3
EG
3878 .suspend = iwl_pci_suspend,
3879 .resume = iwl_pci_resume,
b481de9c
ZY
3880#endif
3881};
3882
5b9f8cd3 3883static int __init iwl_init(void)
b481de9c
ZY
3884{
3885
3886 int ret;
3887 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3888 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3889
e227ceac 3890 ret = iwlagn_rate_control_register();
897e1cf2 3891 if (ret) {
a3139c59
SO
3892 printk(KERN_ERR DRV_NAME
3893 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3894 return ret;
3895 }
3896
fed9017e 3897 ret = pci_register_driver(&iwl_driver);
b481de9c 3898 if (ret) {
a3139c59 3899 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3900 goto error_register;
b481de9c 3901 }
b481de9c
ZY
3902
3903 return ret;
897e1cf2 3904
897e1cf2 3905error_register:
e227ceac 3906 iwlagn_rate_control_unregister();
897e1cf2 3907 return ret;
b481de9c
ZY
3908}
3909
5b9f8cd3 3910static void __exit iwl_exit(void)
b481de9c 3911{
fed9017e 3912 pci_unregister_driver(&iwl_driver);
e227ceac 3913 iwlagn_rate_control_unregister();
b481de9c
ZY
3914}
3915
5b9f8cd3
EG
3916module_exit(iwl_exit);
3917module_init(iwl_init);
a562a9dd
RC
3918
3919#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3920module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3921MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3922module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3923MODULE_PARM_DESC(debug, "debug output mask");
3924#endif
3925