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iwlwifi: fix dual-mode scanning
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
0de76736 60#include "iwl-agn-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY		 64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY		 70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
bee008b7 90static int iwlagn_ant_coupling;
f37837c9 91static bool iwlagn_bt_ch_announce = 1;
bee008b7 92
b481de9c 93/**
7314c2b3 94 * iwlagn_commit_rxon - commit staging_rxon to hardware
b481de9c 95 *
01ebd063 96 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
100 */
7314c2b3 101int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
b481de9c
ZY		 102{
103 /* cast away the const for active_rxon in this function */
246ed355 104 struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
43d59b32
EG		 105 int ret;
106 bool new_assoc =
246ed355 107 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
b01efe43 108 bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 109
fee1247a 110 if (!iwl_is_alive(priv))
43d59b32 111 return -EBUSY;
b481de9c 112
763cc3bf
JB		 113 if (!ctx->is_active)
114 return 0;
115
b481de9c 116 /* always get timestamp with Rx frame */
246ed355 117 ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
b481de9c 118
246ed355 119 ret = iwl_check_rxon_cmd(priv, ctx);
43d59b32 120 if (ret) {
15b1687c 121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 122 return -EINVAL;
123 }
124
0924e519
WYG		 125 /*
126 * receive commit_rxon request
127 * abort any previous channel switch if still in process
128 */
129 if (priv->switch_rxon.switch_in_progress &&
246ed355 130 (priv->switch_rxon.channel != ctx->staging.channel)) {
0924e519
WYG		 131 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
132 le16_to_cpu(priv->switch_rxon.channel));
79d07325 133 iwl_chswitch_done(priv, false);
0924e519
WYG		 134 }
135
b481de9c 136 /* If we don't need to send a full RXON, we can use
5b9f8cd3 137 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 138 * and other flags for the current radio configuration. */
246ed355
JB		 139 if (!iwl_full_rxon_required(priv, ctx)) {
140 ret = iwl_send_rxon_assoc(priv, ctx);
43d59b32 141 if (ret) {
15b1687c 142 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 143 return ret;
b481de9c
ZY		 144 }
145
246ed355
JB		 146 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
147 iwl_print_rx_config_cmd(priv, ctx);
b481de9c
ZY		 148 return 0;
149 }
150
b481de9c
ZY		 151 /* If we are currently associated and the new config requires
152 * an RXON_ASSOC and the new config wants the associated mask enabled,
153 * we must clear the associated from the active configuration
154 * before we apply the new config */
246ed355 155 if (iwl_is_associated_ctx(ctx) && new_assoc) {
e1623446 156 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 157 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
158
8f2d3d2a 159 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355
JB		 160 sizeof(struct iwl_rxon_cmd),
161 active_rxon);
b481de9c
ZY		 162
163 /* If the mask clearing failed then we set
164 * active_rxon back to what it was previously */
43d59b32 165 if (ret) {
b481de9c 166 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 167 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 168 return ret;
b481de9c 169 }
dcef732c
JB		 170 iwl_clear_ucode_stations(priv, ctx);
171 iwl_restore_stations(priv, ctx);
c10afb6e 172 ret = iwl_restore_default_wep_keys(priv, ctx);
335348b1
JB		 173 if (ret) {
174 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
175 return ret;
176 }
b481de9c
ZY		 177 }
178
e1623446 179 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 180 "* with%s RXON_FILTER_ASSOC_MSK\n"
181 "* channel = %d\n"
e174961c 182 "* bssid = %pM\n",
43d59b32 183 (new_assoc ? "" : "out"),
246ed355
JB		 184 le16_to_cpu(ctx->staging.channel),
185 ctx->staging.bssid_addr);
b481de9c 186
246ed355 187 iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
43d59b32 188
b01efe43 189 if (!old_assoc) {
2491fa42
JB		 190 /*
191 * First of all, before setting associated, we need to
192 * send RXON timing so the device knows about the DTIM
193 * period and other timing values
194 */
47313e34 195 ret = iwl_send_rxon_timing(priv, ctx);
2491fa42
JB		 196 if (ret) {
197 IWL_ERR(priv, "Error setting RXON timing!\n");
198 return ret;
199 }
200 }
201
52a02d15
JB		 202 if (priv->cfg->ops->hcmd->set_pan_params) {
203 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
204 if (ret)
205 return ret;
206 }
207
43d59b32 208 /* Apply the new configuration
7e246191
RC		 209 * RXON unassoc clears the station table in uCode so restoration of
210 * stations is needed after it (the RXON command) completes
43d59b32
EG		 211 */
212 if (!new_assoc) {
8f2d3d2a 213 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 214 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 215 if (ret) {
15b1687c 216 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 217 return ret;
218 }
91dd6c27 219 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
246ed355 220 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
dcef732c
JB		 221 iwl_clear_ucode_stations(priv, ctx);
222 iwl_restore_stations(priv, ctx);
c10afb6e 223 ret = iwl_restore_default_wep_keys(priv, ctx);
335348b1
JB		 224 if (ret) {
225 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
226 return ret;
227 }
b481de9c 228 }
9185159d 229 if (new_assoc) {
8f1d9687 230 priv->start_calib = 0;
43d59b32
EG		 231 /* Apply the new configuration
232 * RXON assoc doesn't clear the station table in uCode,
233 */
8f2d3d2a 234 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 235 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 236 if (ret) {
15b1687c 237 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 238 return ret;
239 }
246ed355 240 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
b481de9c 241 }
246ed355 242 iwl_print_rx_config_cmd(priv, ctx);
b481de9c 243
36da7d70
ZY		 244 iwl_init_sensitivity(priv);
245
246 /* If we issue a new RXON command which required a tune then we must
247 * send a new TXPOWER command or we won't be able to Tx any frames */
248 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
249 if (ret) {
15b1687c 250 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 251 return ret;
252 }
253
b481de9c
ZY		 254 return 0;
255}
256
5b9f8cd3 257void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 258{
246ed355 259 struct iwl_rxon_context *ctx;
5da4b55f 260
246ed355
JB		 261 if (priv->cfg->ops->hcmd->set_rxon_chain) {
262 for_each_context(priv, ctx) {
263 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
264 iwlcore_commit_rxon(priv, ctx);
265 }
266 }
5da4b55f
MA		 267}
268
fcab423d 269static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 270{
271 struct list_head *element;
272
e1623446 273 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 274 priv->frames_count);
275
276 while (!list_empty(&priv->free_frames)) {
277 element = priv->free_frames.next;
278 list_del(element);
fcab423d 279 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 280 priv->frames_count--;
281 }
282
283 if (priv->frames_count) {
39aadf8c 284 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 285 priv->frames_count);
286 priv->frames_count = 0;
287 }
288}
289
fcab423d 290static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 291{
fcab423d 292 struct iwl_frame *frame;
b481de9c
ZY		 293 struct list_head *element;
294 if (list_empty(&priv->free_frames)) {
295 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
296 if (!frame) {
15b1687c 297 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 298 return NULL;
299 }
300
301 priv->frames_count++;
302 return frame;
303 }
304
305 element = priv->free_frames.next;
306 list_del(element);
fcab423d 307 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 308}
309
fcab423d 310static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 311{
312 memset(frame, 0, sizeof(*frame));
313 list_add(&frame->list, &priv->free_frames);
314}
315
47ff65c4 316static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 317 struct ieee80211_hdr *hdr,
73ec1cc2 318 int left)
b481de9c 319{
6abbe554 320 if (!priv->ibss_beacon)
b481de9c
ZY		 321 return 0;
322
323 if (priv->ibss_beacon->len > left)
324 return 0;
325
326 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
327
328 return priv->ibss_beacon->len;
329}
330
47ff65c4
DH		 331/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
332static void iwl_set_beacon_tim(struct iwl_priv *priv,
333 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
334 u8 *beacon, u32 frame_size)
335{
336 u16 tim_idx;
337 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
338
339 /*
340 * The index is relative to frame start but we start looking at the
341 * variable-length part of the beacon.
342 */
343 tim_idx = mgmt->u.beacon.variable - beacon;
344
345 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
346 while ((tim_idx < (frame_size - 2)) &&
347 (beacon[tim_idx] != WLAN_EID_TIM))
348 tim_idx += beacon[tim_idx+1] + 2;
349
350 /* If TIM field was found, set variables */
351 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
352 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
353 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
354 } else
355 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
356}
357
5b9f8cd3 358static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 359 struct iwl_frame *frame)
4bf64efd
TW		 360{
361 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 362 u32 frame_size;
363 u32 rate_flags;
364 u32 rate;
365 /*
366 * We have to set up the TX command, the TX Beacon command, and the
367 * beacon contents.
368 */
4bf64efd 369
76d04815
JB		 370 lockdep_assert_held(&priv->mutex);
371
372 if (!priv->beacon_ctx) {
373 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
950094cb 374 return 0;
76d04815
JB		 375 }
376
47ff65c4 377 /* Initialize memory */
4bf64efd
TW		 378 tx_beacon_cmd = &frame->u.beacon;
379 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
380
47ff65c4 381 /* Set up TX beacon contents */
4bf64efd 382 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 383 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 384 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
385 return 0;
4bf64efd 386
47ff65c4 387 /* Set up TX command fields */
4bf64efd 388 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
76d04815 389 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
47ff65c4
DH		 390 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
391 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
392 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 393
47ff65c4
DH		 394 /* Set up TX beacon command fields */
395 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
396 frame_size);
4bf64efd 397
47ff65c4 398 /* Set up packet rate and flags */
76d04815 399 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
0e1654fa
JB		 400 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
401 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 402 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
403 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
404 rate_flags |= RATE_MCS_CCK_MSK;
405 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
406 rate_flags);
4bf64efd
TW		 407
408 return sizeof(*tx_beacon_cmd) + frame_size;
409}
5b9f8cd3 410static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 411{
fcab423d 412 struct iwl_frame *frame;
b481de9c
ZY		 413 unsigned int frame_size;
414 int rc;
b481de9c 415
fcab423d 416 frame = iwl_get_free_frame(priv);
b481de9c 417 if (!frame) {
15b1687c 418 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 419 "command.\n");
420 return -ENOMEM;
421 }
422
47ff65c4
DH		 423 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
424 if (!frame_size) {
425 IWL_ERR(priv, "Error configuring the beacon command\n");
426 iwl_free_frame(priv, frame);
427 return -EINVAL;
428 }
b481de9c 429
857485c0 430 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 431 &frame->u.cmd[0]);
432
fcab423d 433 iwl_free_frame(priv, frame);
b481de9c
ZY		 434
435 return rc;
436}
437
7aaa1d79
SO		 438static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
439{
440 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
441
442 dma_addr_t addr = get_unaligned_le32(&tb->lo);
443 if (sizeof(dma_addr_t) > sizeof(u32))
444 addr |=
445 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
446
447 return addr;
448}
449
450static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
451{
452 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
453
454 return le16_to_cpu(tb->hi_n_len) >> 4;
455}
456
457static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
458 dma_addr_t addr, u16 len)
459{
460 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
461 u16 hi_n_len = len << 4;
462
463 put_unaligned_le32(addr, &tb->lo);
464 if (sizeof(dma_addr_t) > sizeof(u32))
465 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
466
467 tb->hi_n_len = cpu_to_le16(hi_n_len);
468
469 tfd->num_tbs = idx + 1;
470}
471
472static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
473{
474 return tfd->num_tbs & 0x1f;
475}
476
477/**
478 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
479 * @priv - driver private data
480 * @txq - tx queue
481 *
482 * Does NOT advance any TFD circular buffer read/write indexes
483 * Does NOT free the TFD itself (which is within circular buffer)
484 */
485void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
486{
59606ffa 487 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 488 struct iwl_tfd *tfd;
489 struct pci_dev *dev = priv->pci_dev;
490 int index = txq->q.read_ptr;
491 int i;
492 int num_tbs;
493
494 tfd = &tfd_tmp[index];
495
496 /* Sanity check on number of chunks */
497 num_tbs = iwl_tfd_get_num_tbs(tfd);
498
499 if (num_tbs >= IWL_NUM_OF_TBS) {
500 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
501 /* @todo issue fatal error, it is quite serious situation */
502 return;
503 }
504
505 /* Unmap tx_cmd */
506 if (num_tbs)
507 pci_unmap_single(dev,
2e724443
FT		 508 dma_unmap_addr(&txq->meta[index], mapping),
509 dma_unmap_len(&txq->meta[index], len),
96891cee 510 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 511
512 /* Unmap chunks, if any. */
ff0d91c3 513 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 514 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
515 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
516
ff0d91c3
JB		 517 /* free SKB */
518 if (txq->txb) {
519 struct sk_buff *skb;
6f80240e 520
ff0d91c3 521 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 522
ff0d91c3
JB		 523 /* can be called from irqs-disabled context */
524 if (skb) {
525 dev_kfree_skb_any(skb);
526 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 527 }
528 }
529}
530
531int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
532 struct iwl_tx_queue *txq,
533 dma_addr_t addr, u16 len,
534 u8 reset, u8 pad)
535{
536 struct iwl_queue *q;
59606ffa 537 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 538 u32 num_tbs;
539
540 q = &txq->q;
59606ffa
SO		 541 tfd_tmp = (struct iwl_tfd *)txq->tfds;
542 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 543
544 if (reset)
545 memset(tfd, 0, sizeof(*tfd));
546
547 num_tbs = iwl_tfd_get_num_tbs(tfd);
548
549 /* Each TFD can point to a maximum 20 Tx buffers */
550 if (num_tbs >= IWL_NUM_OF_TBS) {
551 IWL_ERR(priv, "Error can not send more than %d chunks\n",
552 IWL_NUM_OF_TBS);
553 return -EINVAL;
554 }
555
556 BUG_ON(addr & ~DMA_BIT_MASK(36));
557 if (unlikely(addr & ~IWL_TX_DMA_MASK))
558 IWL_ERR(priv, "Unaligned address = %llx\n",
559 (unsigned long long)addr);
560
561 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
562
563 return 0;
564}
565
a8e74e27
SO		 566/*
567 * Tell nic where to find circular buffer of Tx Frame Descriptors for
568 * given Tx queue, and enable the DMA channel used for that queue.
569 *
570 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
571 * channels supported in hardware.
572 */
573int iwl_hw_tx_queue_init(struct iwl_priv *priv,
574 struct iwl_tx_queue *txq)
575{
a8e74e27
SO		 576 int txq_id = txq->q.id;
577
a8e74e27
SO		 578 /* Circular buffer (TFD queue in DRAM) physical base address */
579 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
580 txq->q.dma_addr >> 8);
581
a8e74e27
SO		 582 return 0;
583}
584
b481de9c
ZY		 585/******************************************************************************
586 *
587 * Generic RX handler implementations
588 *
589 ******************************************************************************/
885ba202
TW		 590static void iwl_rx_reply_alive(struct iwl_priv *priv,
591 struct iwl_rx_mem_buffer *rxb)
b481de9c 592{
2f301227 593 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 594 struct iwl_alive_resp *palive;
b481de9c
ZY		 595 struct delayed_work *pwork;
596
597 palive = &pkt->u.alive_frame;
598
e1623446 599 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 600 "0x%01X 0x%01X\n",
601 palive->is_valid, palive->ver_type,
602 palive->ver_subtype);
603
604 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 605 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 606 memcpy(&priv->card_alive_init,
607 &pkt->u.alive_frame,
885ba202 608 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 609 pwork = &priv->init_alive_start;
610 } else {
e1623446 611 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 612 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 613 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 614 pwork = &priv->alive_start;
615 }
616
617 /* We delay the ALIVE response by 5ms to
618 * give the HW RF Kill time to activate... */
619 if (palive->is_valid == UCODE_VALID_OK)
620 queue_delayed_work(priv->workqueue, pwork,
621 msecs_to_jiffies(5));
622 else
39aadf8c 623 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 624}
625
5b9f8cd3 626static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 627{
c79dd5b5
TW		 628 struct iwl_priv *priv =
629 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 630 struct sk_buff *beacon;
631
76d04815
JB		 632 mutex_lock(&priv->mutex);
633 if (!priv->beacon_ctx) {
634 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
635 goto out;
636 }
b481de9c 637
60744f62
JB		 638 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
639 /*
640 * The ucode will send beacon notifications even in
641 * IBSS mode, but we don't want to process them. But
642 * we need to defer the type check to here due to
643 * requiring locking around the beacon_ctx access.
644 */
645 goto out;
646 }
647
76d04815
JB		 648 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
649 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
b481de9c 650 if (!beacon) {
15b1687c 651 IWL_ERR(priv, "update beacon failed\n");
76d04815 652 goto out;
b481de9c
ZY		 653 }
654
b481de9c
ZY		 655 /* new beacon skb is allocated every time; dispose previous.*/
656 if (priv->ibss_beacon)
657 dev_kfree_skb(priv->ibss_beacon);
658
659 priv->ibss_beacon = beacon;
b481de9c 660
5b9f8cd3 661 iwl_send_beacon_cmd(priv);
76d04815
JB		 662 out:
663 mutex_unlock(&priv->mutex);
b481de9c
ZY		 664}
665
fbba9410
WYG		 666static void iwl_bg_bt_runtime_config(struct work_struct *work)
667{
668 struct iwl_priv *priv =
669 container_of(work, struct iwl_priv, bt_runtime_config);
670
671 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
672 return;
673
674 /* dont send host command if rf-kill is on */
675 if (!iwl_is_ready_rf(priv))
676 return;
677 priv->cfg->ops->hcmd->send_bt_config(priv);
678}
679
bee008b7
WYG		 680static void iwl_bg_bt_full_concurrency(struct work_struct *work)
681{
682 struct iwl_priv *priv =
683 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 684 struct iwl_rxon_context *ctx;
bee008b7
WYG		 685
686 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
687 return;
688
689 /* dont send host command if rf-kill is on */
690 if (!iwl_is_ready_rf(priv))
691 return;
692
693 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
694 priv->bt_full_concurrent ?
695 "full concurrency" : "3-wire");
696
697 /*
698 * LQ & RXON updated cmds must be sent before BT Config cmd
699 * to avoid 3-wire collisions
700 */
246ed355
JB		 701 mutex_lock(&priv->mutex);
702 for_each_context(priv, ctx) {
703 if (priv->cfg->ops->hcmd->set_rxon_chain)
704 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
705 iwlcore_commit_rxon(priv, ctx);
706 }
707 mutex_unlock(&priv->mutex);
bee008b7
WYG		 708
709 priv->cfg->ops->hcmd->send_bt_config(priv);
710}
711
4e39317d 712/**
5b9f8cd3 713 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 714 *
715 * This callback is provided in order to send a statistics request.
716 *
717 * This timer function is continually reset to execute within
718 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
719 * was received. We need to ensure we receive the statistics in order
720 * to update the temperature used for calibrating the TXPOWER.
721 */
5b9f8cd3 722static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 723{
724 struct iwl_priv *priv = (struct iwl_priv *)data;
725
726 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
727 return;
728
61780ee3
MA		 729 /* dont send host command if rf-kill is on */
730 if (!iwl_is_ready_rf(priv))
731 return;
732
ef8d5529 733 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 734}
735
a9e1cb6a
WYG		 736
737static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
738 u32 start_idx, u32 num_events,
739 u32 mode)
740{
741 u32 i;
742 u32 ptr; /* SRAM byte address of log data */
743 u32 ev, time, data; /* event log data */
744 unsigned long reg_flags;
745
746 if (mode == 0)
747 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
748 else
749 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
750
751 /* Make sure device is powered up for SRAM reads */
752 spin_lock_irqsave(&priv->reg_lock, reg_flags);
753 if (iwl_grab_nic_access(priv)) {
754 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
755 return;
756 }
757
758 /* Set starting address; reads will auto-increment */
759 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
760 rmb();
761
762 /*
763 * "time" is actually "data" for mode 0 (no timestamp).
764 * place event id # at far right for easier visual parsing.
765 */
766 for (i = 0; i < num_events; i++) {
767 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
768 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
769 if (mode == 0) {
770 trace_iwlwifi_dev_ucode_cont_event(priv,
771 0, time, ev);
772 } else {
773 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
774 trace_iwlwifi_dev_ucode_cont_event(priv,
775 time, data, ev);
776 }
777 }
778 /* Allow device to power down */
779 iwl_release_nic_access(priv);
780 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
781}
782
875295f1 783static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 784{
785 u32 capacity; /* event log capacity in # entries */
786 u32 base; /* SRAM byte address of event log header */
787 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
788 u32 num_wraps; /* # times uCode wrapped to top of log */
789 u32 next_entry; /* index of next entry to be written by uCode */
790
791 if (priv->ucode_type == UCODE_INIT)
792 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
793 else
794 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
795 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
796 capacity = iwl_read_targ_mem(priv, base);
797 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
798 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
799 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
800 } else
801 return;
802
803 if (num_wraps == priv->event_log.num_wraps) {
804 iwl_print_cont_event_trace(priv,
805 base, priv->event_log.next_entry,
806 next_entry - priv->event_log.next_entry,
807 mode);
808 priv->event_log.non_wraps_count++;
809 } else {
810 if ((num_wraps - priv->event_log.num_wraps) > 1)
811 priv->event_log.wraps_more_count++;
812 else
813 priv->event_log.wraps_once_count++;
814 trace_iwlwifi_dev_ucode_wrap_event(priv,
815 num_wraps - priv->event_log.num_wraps,
816 next_entry, priv->event_log.next_entry);
817 if (next_entry < priv->event_log.next_entry) {
818 iwl_print_cont_event_trace(priv, base,
819 priv->event_log.next_entry,
820 capacity - priv->event_log.next_entry,
821 mode);
822
823 iwl_print_cont_event_trace(priv, base, 0,
824 next_entry, mode);
825 } else {
826 iwl_print_cont_event_trace(priv, base,
827 next_entry, capacity - next_entry,
828 mode);
829
830 iwl_print_cont_event_trace(priv, base, 0,
831 next_entry, mode);
832 }
833 }
834 priv->event_log.num_wraps = num_wraps;
835 priv->event_log.next_entry = next_entry;
836}
837
838/**
839 * iwl_bg_ucode_trace - Timer callback to log ucode event
840 *
841 * The timer is continually set to execute every
842 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
843 * this function is to perform continuous uCode event logging operation
844 * if enabled
845 */
846static void iwl_bg_ucode_trace(unsigned long data)
847{
848 struct iwl_priv *priv = (struct iwl_priv *)data;
849
850 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
851 return;
852
853 if (priv->event_log.ucode_trace) {
854 iwl_continuous_event_trace(priv);
855 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
856 mod_timer(&priv->ucode_trace,
857 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
858 }
859}
860
5b9f8cd3 861static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 862 struct iwl_rx_mem_buffer *rxb)
b481de9c 863{
2f301227 864 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 865 struct iwl4965_beacon_notif *beacon =
866 (struct iwl4965_beacon_notif *)pkt->u.raw;
a85d7cca 867#ifdef CONFIG_IWLWIFI_DEBUG
e7d326ac 868 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 869
e1623446 870 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 871 "tsf %d %d rate %d\n",
25a6572c 872 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 873 beacon->beacon_notify_hdr.failure_frame,
874 le32_to_cpu(beacon->ibss_mgr_status),
875 le32_to_cpu(beacon->high_tsf),
876 le32_to_cpu(beacon->low_tsf), rate);
877#endif
878
a85d7cca
JB		 879 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
880
60744f62 881 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 882 queue_work(priv->workqueue, &priv->beacon_update);
883}
884
b481de9c
ZY		 885/* Handle notification from uCode that card's power state is changing
886 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 887static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 888 struct iwl_rx_mem_buffer *rxb)
b481de9c 889{
2f301227 890 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 891 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
892 unsigned long status = priv->status;
893
3a41bbd5 894 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 895 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 896 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
897 (flags & CT_CARD_DISABLED) ?
898 "Reached" : "Not reached");
b481de9c
ZY		 899
900 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 901 CT_CARD_DISABLED)) {
b481de9c 902
3395f6e9 903 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 904 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
905
a8b50a0a
MA		 906 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
907 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 908
909 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 910 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 911 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 912 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 913 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 914 }
3a41bbd5 915 if (flags & CT_CARD_DISABLED)
39b73fb1 916 iwl_tt_enter_ct_kill(priv);
b481de9c 917 }
3a41bbd5 918 if (!(flags & CT_CARD_DISABLED))
39b73fb1 919 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 920
921 if (flags & HW_CARD_DISABLED)
922 set_bit(STATUS_RF_KILL_HW, &priv->status);
923 else
924 clear_bit(STATUS_RF_KILL_HW, &priv->status);
925
926
b481de9c 927 if (!(flags & RXON_CARD_DISABLED))
2a421b91 928 iwl_scan_cancel(priv);
b481de9c
ZY		 929
930 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 931 test_bit(STATUS_RF_KILL_HW, &priv->status)))
932 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
933 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 934 else
935 wake_up_interruptible(&priv->wait_command_queue);
936}
937
65550636
WYG		 938static void iwl_bg_tx_flush(struct work_struct *work)
939{
940 struct iwl_priv *priv =
941 container_of(work, struct iwl_priv, tx_flush);
942
943 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
944 return;
945
946 /* do nothing if rf-kill is on */
947 if (!iwl_is_ready_rf(priv))
948 return;
949
950 if (priv->cfg->ops->lib->txfifo_flush) {
951 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
952 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
953 }
954}
955
b481de9c 956/**
5b9f8cd3 957 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 958 *
959 * Setup the RX handlers for each of the reply types sent from the uCode
960 * to the host.
961 *
962 * This function chains into the hardware specific files for them to setup
963 * any hardware specific handlers as well.
964 */
653fa4a0 965static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 966{
885ba202 967 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 968 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
969 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 970 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
971 iwl_rx_spectrum_measure_notif;
5b9f8cd3 972 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 973 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 974 iwl_rx_pm_debug_statistics_notif;
975 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 976
9fbab516
BC		 977 /*
978 * The same handler is used for both the REPLY to a discrete
979 * statistics request from the host as well as for the periodic
980 * statistics notifications (after received beacons) from the uCode.
b481de9c 981 */
ef8d5529 982 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 983 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 984
985 iwl_setup_rx_scan_handlers(priv);
986
37a44211 987 /* status change handler */
5b9f8cd3 988 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 989
c1354754
TW		 990 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
991 iwl_rx_missed_beacon_notif;
37a44211 992 /* Rx handlers */
8d801080
WYG		 993 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
994 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 995 /* block ack */
74bcdb33 996 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 997 /* Set up hardware specific Rx handlers */
d4789efe 998 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 999}
1000
b481de9c 1001/**
a55360e4 1002 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 1003 *
1004 * Uses the priv->rx_handlers callback function array to invoke
1005 * the appropriate handlers, including command responses,
1006 * frame-received notifications, and other notifications.
1007 */
a55360e4 1008void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 1009{
a55360e4 1010 struct iwl_rx_mem_buffer *rxb;
db11d634 1011 struct iwl_rx_packet *pkt;
a55360e4 1012 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 1013 u32 r, i;
1014 int reclaim;
1015 unsigned long flags;
5c0eef96 1016 u8 fill_rx = 0;
d68ab680 1017 u32 count = 8;
4752c93c 1018 int total_empty;
b481de9c 1019
6440adb5
BC		 1020 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1021 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 1022 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 1023 i = rxq->read;
1024
1025 /* Rx interrupt, but nothing sent from uCode */
1026 if (i == r)
e1623446 1027 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 1028
4752c93c 1029 /* calculate total frames need to be restock after handling RX */
7300515d 1030 total_empty = r - rxq->write_actual;
4752c93c
MA		 1031 if (total_empty < 0)
1032 total_empty += RX_QUEUE_SIZE;
1033
1034 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 1035 fill_rx = 1;
1036
b481de9c 1037 while (i != r) {
f4989d9b
JB		 1038 int len;
1039
b481de9c
ZY		 1040 rxb = rxq->queue[i];
1041
9fbab516 1042 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 1043 * then a bug has been introduced in the queue refilling
1044 * routines -- catch it here */
1045 BUG_ON(rxb == NULL);
1046
1047 rxq->queue[i] = NULL;
1048
2f301227
ZY		 1049 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1050 PAGE_SIZE << priv->hw_params.rx_page_order,
1051 PCI_DMA_FROMDEVICE);
1052 pkt = rxb_addr(rxb);
b481de9c 1053
f4989d9b
JB		 1054 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1055 len += sizeof(u32); /* account for status word */
1056 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 1057
b481de9c
ZY		 1058 /* Reclaim a command buffer only if this packet is a response
1059 * to a (driver-originated) command.
1060 * If the packet (e.g. Rx frame) originated from uCode,
1061 * there is no command buffer to reclaim.
1062 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1063 * but apparently a few don't get set; catch them here. */
1064 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1065 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 1066 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 1067 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 1068 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 1069 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1070 (pkt->hdr.cmd != REPLY_TX);
1071
1072 /* Based on type of command response or notification,
1073 * handle those that need handling via function in
5b9f8cd3 1074 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 1075 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1076 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1077 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 1078 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1079 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 1080 } else {
1081 /* No handling needed */
e1623446 1082 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1083 "r %d i %d No handler needed for %s, 0x%02x\n",
1084 r, i, get_cmd_string(pkt->hdr.cmd),
1085 pkt->hdr.cmd);
1086 }
1087
29b1b268
ZY		 1088 /*
1089 * XXX: After here, we should always check rxb->page
1090 * against NULL before touching it or its virtual
1091 * memory (pkt). Because some rx_handler might have
1092 * already taken or freed the pages.
1093 */
1094
b481de9c 1095 if (reclaim) {
2f301227
ZY		 1096 /* Invoke any callbacks, transfer the buffer to caller,
1097 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1098 * as we reclaim the driver command queue */
29b1b268 1099 if (rxb->page)
17b88929 1100 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1101 else
39aadf8c 1102 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1103 }
1104
7300515d
ZY		 1105 /* Reuse the page if possible. For notification packets and
1106 * SKBs that fail to Rx correctly, add them back into the
1107 * rx_free list for reuse later. */
1108 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1109 if (rxb->page != NULL) {
7300515d
ZY		 1110 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1111 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1112 PCI_DMA_FROMDEVICE);
1113 list_add_tail(&rxb->list, &rxq->rx_free);
1114 rxq->free_count++;
1115 } else
1116 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1117
b481de9c 1118 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1119
b481de9c 1120 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1121 /* If there are a lot of unused frames,
1122 * restock the Rx queue so ucode wont assert. */
1123 if (fill_rx) {
1124 count++;
1125 if (count >= 8) {
7300515d 1126 rxq->read = i;
54b81550 1127 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1128 count = 0;
1129 }
1130 }
b481de9c
ZY		 1131 }
1132
1133 /* Backtrack one entry */
7300515d 1134 rxq->read = i;
4752c93c 1135 if (fill_rx)
54b81550 1136 iwlagn_rx_replenish_now(priv);
4752c93c 1137 else
54b81550 1138 iwlagn_rx_queue_restock(priv);
a55360e4 1139}
a55360e4 1140
0359facc
MA		 1141/* call this function to flush any scheduled tasklet */
1142static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1143{
a96a27f9 1144 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1145 synchronize_irq(priv->pci_dev->irq);
1146 tasklet_kill(&priv->irq_tasklet);
1147}
1148
ef850d7c 1149static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1150{
1151 u32 inta, handled = 0;
1152 u32 inta_fh;
1153 unsigned long flags;
c2e61da2 1154 u32 i;
0a6857e7 1155#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1156 u32 inta_mask;
1157#endif
1158
1159 spin_lock_irqsave(&priv->lock, flags);
1160
1161 /* Ack/clear/reset pending uCode interrupts.
1162 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1163 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1164 inta = iwl_read32(priv, CSR_INT);
1165 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1166
1167 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1168 * Any new interrupts that happen after this, either while we're
1169 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1170 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1171 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1172
0a6857e7 1173#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1174 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1175 /* just for debug */
3395f6e9 1176 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1177 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1178 inta, inta_mask, inta_fh);
1179 }
1180#endif
1181
2f301227
ZY		 1182 spin_unlock_irqrestore(&priv->lock, flags);
1183
b481de9c
ZY		 1184 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1185 * atomic, make sure that inta covers all the interrupts that
1186 * we've discovered, even if FH interrupt came in just after
1187 * reading CSR_INT. */
6f83eaa1 1188 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1189 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1190 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1191 inta |= CSR_INT_BIT_FH_TX;
1192
1193 /* Now service all interrupt bits discovered above. */
1194 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1195 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1196
1197 /* Tell the device to stop sending interrupts */
5b9f8cd3 1198 iwl_disable_interrupts(priv);
b481de9c 1199
a83b9141 1200 priv->isr_stats.hw++;
5b9f8cd3 1201 iwl_irq_handle_error(priv);
b481de9c
ZY		 1202
1203 handled |= CSR_INT_BIT_HW_ERR;
1204
b481de9c
ZY		 1205 return;
1206 }
1207
0a6857e7 1208#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1209 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1210 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1211 if (inta & CSR_INT_BIT_SCD) {
e1623446 1212 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1213 "the frame/frames.\n");
a83b9141
WYG		 1214 priv->isr_stats.sch++;
1215 }
b481de9c
ZY		 1216
1217 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1218 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1219 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1220 priv->isr_stats.alive++;
1221 }
b481de9c
ZY		 1222 }
1223#endif
1224 /* Safely ignore these bits for debug checks below */
25c03d8e 1225 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1226
9fbab516 1227 /* HW RF KILL switch toggled */
b481de9c
ZY		 1228 if (inta & CSR_INT_BIT_RF_KILL) {
1229 int hw_rf_kill = 0;
3395f6e9 1230 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1231 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1232 hw_rf_kill = 1;
1233
4c423a2b 1234 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1235 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1236
a83b9141
WYG		 1237 priv->isr_stats.rfkill++;
1238
a9efa652 1239 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1240 * the driver allows loading the ucode even if the radio
1241 * is killed. Hence update the killswitch state here. The
1242 * rfkill handler will care about restarting if needed.
a9efa652 1243 */
6cd0b1cb
HS		 1244 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1245 if (hw_rf_kill)
1246 set_bit(STATUS_RF_KILL_HW, &priv->status);
1247 else
1248 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1249 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1250 }
b481de9c
ZY		 1251
1252 handled |= CSR_INT_BIT_RF_KILL;
1253 }
1254
9fbab516 1255 /* Chip got too hot and stopped itself */
b481de9c 1256 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1257 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1258 priv->isr_stats.ctkill++;
b481de9c
ZY		 1259 handled |= CSR_INT_BIT_CT_KILL;
1260 }
1261
1262 /* Error detected by uCode */
1263 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1264 IWL_ERR(priv, "Microcode SW error detected. "
1265 " Restarting 0x%X.\n", inta);
a83b9141 1266 priv->isr_stats.sw++;
5b9f8cd3 1267 iwl_irq_handle_error(priv);
b481de9c
ZY		 1268 handled |= CSR_INT_BIT_SW_ERR;
1269 }
1270
c2e61da2
BC		 1271 /*
1272 * uCode wakes up after power-down sleep.
1273 * Tell device about any new tx or host commands enqueued,
1274 * and about any Rx buffers made available while asleep.
1275 */
b481de9c 1276 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1277 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1278 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1279 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1280 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1281 priv->isr_stats.wakeup++;
b481de9c
ZY		 1282 handled |= CSR_INT_BIT_WAKEUP;
1283 }
1284
1285 /* All uCode command responses, including Tx command responses,
1286 * Rx "responses" (frame-received notification), and other
1287 * notifications from uCode come through here*/
1288 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1289 iwl_rx_handle(priv);
a83b9141 1290 priv->isr_stats.rx++;
b481de9c
ZY		 1291 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1292 }
1293
c72cd19f 1294 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1295 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1296 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1297 priv->isr_stats.tx++;
b481de9c 1298 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1299 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1300 priv->ucode_write_complete = 1;
1301 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1302 }
1303
a83b9141 1304 if (inta & ~handled) {
15b1687c 1305 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1306 priv->isr_stats.unhandled++;
1307 }
b481de9c 1308
40cefda9 1309 if (inta & ~(priv->inta_mask)) {
39aadf8c 1310 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1311 inta & ~priv->inta_mask);
39aadf8c 1312 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1313 }
1314
1315 /* Re-enable all interrupts */
0359facc
MA		 1316 /* only Re-enable if diabled by irq */
1317 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1318 iwl_enable_interrupts(priv);
b481de9c 1319
0a6857e7 1320#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1321 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1322 inta = iwl_read32(priv, CSR_INT);
1323 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1324 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1325 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1326 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1327 }
1328#endif
b481de9c
ZY		 1329}
1330
ef850d7c
MA		 1331/* tasklet for iwlagn interrupt */
1332static void iwl_irq_tasklet(struct iwl_priv *priv)
1333{
1334 u32 inta = 0;
1335 u32 handled = 0;
1336 unsigned long flags;
8756990f 1337 u32 i;
ef850d7c
MA		 1338#ifdef CONFIG_IWLWIFI_DEBUG
1339 u32 inta_mask;
1340#endif
1341
1342 spin_lock_irqsave(&priv->lock, flags);
1343
1344 /* Ack/clear/reset pending uCode interrupts.
1345 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1346 */
48a6be6a
SZ		 1347 /* There is a hardware bug in the interrupt mask function that some
1348 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1349 * they are disabled in the CSR_INT_MASK register. Furthermore the
1350 * ICT interrupt handling mechanism has another bug that might cause
1351 * these unmasked interrupts fail to be detected. We workaround the
1352 * hardware bugs here by ACKing all the possible interrupts so that
1353 * interrupt coalescing can still be achieved.
1354 */
4a35ecf8 1355 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1356
a4c8b2a6 1357 inta = priv->_agn.inta;
ef850d7c
MA		 1358
1359#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1360 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1361 /* just for debug */
1362 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1363 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1364 inta, inta_mask);
1365 }
1366#endif
2f301227
ZY		 1367
1368 spin_unlock_irqrestore(&priv->lock, flags);
1369
a4c8b2a6
JB		 1370 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1371 priv->_agn.inta = 0;
ef850d7c
MA		 1372
1373 /* Now service all interrupt bits discovered above. */
1374 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1375 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1376
1377 /* Tell the device to stop sending interrupts */
1378 iwl_disable_interrupts(priv);
1379
1380 priv->isr_stats.hw++;
1381 iwl_irq_handle_error(priv);
1382
1383 handled |= CSR_INT_BIT_HW_ERR;
1384
ef850d7c
MA		 1385 return;
1386 }
1387
1388#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1389 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1390 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1391 if (inta & CSR_INT_BIT_SCD) {
1392 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1393 "the frame/frames.\n");
1394 priv->isr_stats.sch++;
1395 }
1396
1397 /* Alive notification via Rx interrupt will do the real work */
1398 if (inta & CSR_INT_BIT_ALIVE) {
1399 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1400 priv->isr_stats.alive++;
1401 }
1402 }
1403#endif
1404 /* Safely ignore these bits for debug checks below */
1405 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1406
1407 /* HW RF KILL switch toggled */
1408 if (inta & CSR_INT_BIT_RF_KILL) {
1409 int hw_rf_kill = 0;
1410 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1411 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1412 hw_rf_kill = 1;
1413
4c423a2b 1414 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1415 hw_rf_kill ? "disable radio" : "enable radio");
1416
1417 priv->isr_stats.rfkill++;
1418
1419 /* driver only loads ucode once setting the interface up.
1420 * the driver allows loading the ucode even if the radio
1421 * is killed. Hence update the killswitch state here. The
1422 * rfkill handler will care about restarting if needed.
1423 */
1424 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1425 if (hw_rf_kill)
1426 set_bit(STATUS_RF_KILL_HW, &priv->status);
1427 else
1428 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1429 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1430 }
1431
1432 handled |= CSR_INT_BIT_RF_KILL;
1433 }
1434
1435 /* Chip got too hot and stopped itself */
1436 if (inta & CSR_INT_BIT_CT_KILL) {
1437 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1438 priv->isr_stats.ctkill++;
1439 handled |= CSR_INT_BIT_CT_KILL;
1440 }
1441
1442 /* Error detected by uCode */
1443 if (inta & CSR_INT_BIT_SW_ERR) {
1444 IWL_ERR(priv, "Microcode SW error detected. "
1445 " Restarting 0x%X.\n", inta);
1446 priv->isr_stats.sw++;
ef850d7c
MA		 1447 iwl_irq_handle_error(priv);
1448 handled |= CSR_INT_BIT_SW_ERR;
1449 }
1450
1451 /* uCode wakes up after power-down sleep */
1452 if (inta & CSR_INT_BIT_WAKEUP) {
1453 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1454 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1455 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1456 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1457
1458 priv->isr_stats.wakeup++;
1459
1460 handled |= CSR_INT_BIT_WAKEUP;
1461 }
1462
1463 /* All uCode command responses, including Tx command responses,
1464 * Rx "responses" (frame-received notification), and other
1465 * notifications from uCode come through here*/
40cefda9
MA		 1466 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1467 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1468 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1469 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1470 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1471 iwl_write32(priv, CSR_FH_INT_STATUS,
1472 CSR49_FH_INT_RX_MASK);
1473 }
1474 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1475 handled |= CSR_INT_BIT_RX_PERIODIC;
1476 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1477 }
1478 /* Sending RX interrupt require many steps to be done in the
1479 * the device:
1480 * 1- write interrupt to current index in ICT table.
1481 * 2- dma RX frame.
1482 * 3- update RX shared data to indicate last write index.
1483 * 4- send interrupt.
1484 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1485 * but the shared data changes does not reflect this;
1486 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1487 */
74ba67ed
BC		 1488
1489 /* Disable periodic interrupt; we use it as just a one-shot. */
1490 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1491 CSR_INT_PERIODIC_DIS);
ef850d7c 1492 iwl_rx_handle(priv);
74ba67ed
BC		 1493
1494 /*
1495 * Enable periodic interrupt in 8 msec only if we received
1496 * real RX interrupt (instead of just periodic int), to catch
1497 * any dangling Rx interrupt. If it was just the periodic
1498 * interrupt, there was no dangling Rx activity, and no need
1499 * to extend the periodic interrupt; one-shot is enough.
1500 */
40cefda9 1501 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1502 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1503 CSR_INT_PERIODIC_ENA);
1504
ef850d7c 1505 priv->isr_stats.rx++;
ef850d7c
MA		 1506 }
1507
c72cd19f 1508 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1509 if (inta & CSR_INT_BIT_FH_TX) {
1510 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1511 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1512 priv->isr_stats.tx++;
1513 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1514 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1515 priv->ucode_write_complete = 1;
1516 wake_up_interruptible(&priv->wait_command_queue);
1517 }
1518
1519 if (inta & ~handled) {
1520 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1521 priv->isr_stats.unhandled++;
1522 }
1523
40cefda9 1524 if (inta & ~(priv->inta_mask)) {
ef850d7c 1525 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1526 inta & ~priv->inta_mask);
ef850d7c
MA		 1527 }
1528
ef850d7c
MA		 1529 /* Re-enable all interrupts */
1530 /* only Re-enable if diabled by irq */
1531 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1532 iwl_enable_interrupts(priv);
ef850d7c
MA		 1533}
1534
872c8ddc
WYG		 1535/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1536#define ACK_CNT_RATIO (50)
1537#define BA_TIMEOUT_CNT (5)
1538#define BA_TIMEOUT_MAX (16)
1539
1540/**
1541 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1542 *
1543 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1544 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1545 * operation state.
1546 */
1547bool iwl_good_ack_health(struct iwl_priv *priv,
1548 struct iwl_rx_packet *pkt)
1549{
1550 bool rc = true;
1551 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1552 int ba_timeout_delta;
1553
1554 actual_ack_cnt_delta =
1555 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1556 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1557 expected_ack_cnt_delta =
1558 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1559 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1560 ba_timeout_delta =
1561 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1562 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1563 if ((priv->_agn.agg_tids_count > 0) &&
1564 (expected_ack_cnt_delta > 0) &&
1565 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1566 < ACK_CNT_RATIO) &&
1567 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1568 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1569 " expected_ack_cnt = %d\n",
1570 actual_ack_cnt_delta, expected_ack_cnt_delta);
1571
d73e4923
JB		 1572#ifdef CONFIG_IWLWIFI_DEBUGFS
1573 /*
1574 * This is ifdef'ed on DEBUGFS because otherwise the
1575 * statistics aren't available. If DEBUGFS is set but
1576 * DEBUG is not, these will just compile out.
1577 */
872c8ddc 1578 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1579 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1580 IWL_DEBUG_RADIO(priv,
1581 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1582 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1583 ack_or_ba_timeout_collision);
1584#endif
1585 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1586 ba_timeout_delta);
1587 if (!actual_ack_cnt_delta &&
1588 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1589 rc = false;
1590 }
1591 return rc;
1592}
1593
a83b9141 1594
7d47618a
EG		 1595/*****************************************************************************
1596 *
1597 * sysfs attributes
1598 *
1599 *****************************************************************************/
1600
1601#ifdef CONFIG_IWLWIFI_DEBUG
1602
1603/*
1604 * The following adds a new attribute to the sysfs representation
1605 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1606 * used for controlling the debug level.
1607 *
1608 * See the level definitions in iwl for details.
1609 *
1610 * The debug_level being managed using sysfs below is a per device debug
1611 * level that is used instead of the global debug level if it (the per
1612 * device debug level) is set.
1613 */
1614static ssize_t show_debug_level(struct device *d,
1615 struct device_attribute *attr, char *buf)
1616{
1617 struct iwl_priv *priv = dev_get_drvdata(d);
1618 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1619}
1620static ssize_t store_debug_level(struct device *d,
1621 struct device_attribute *attr,
1622 const char *buf, size_t count)
1623{
1624 struct iwl_priv *priv = dev_get_drvdata(d);
1625 unsigned long val;
1626 int ret;
1627
1628 ret = strict_strtoul(buf, 0, &val);
1629 if (ret)
1630 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1631 else {
1632 priv->debug_level = val;
1633 if (iwl_alloc_traffic_mem(priv))
1634 IWL_ERR(priv,
1635 "Not enough memory to generate traffic log\n");
1636 }
1637 return strnlen(buf, count);
1638}
1639
1640static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1641 show_debug_level, store_debug_level);
1642
1643
1644#endif /* CONFIG_IWLWIFI_DEBUG */
1645
1646
1647static ssize_t show_temperature(struct device *d,
1648 struct device_attribute *attr, char *buf)
1649{
1650 struct iwl_priv *priv = dev_get_drvdata(d);
1651
1652 if (!iwl_is_alive(priv))
1653 return -EAGAIN;
1654
1655 return sprintf(buf, "%d\n", priv->temperature);
1656}
1657
1658static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1659
1660static ssize_t show_tx_power(struct device *d,
1661 struct device_attribute *attr, char *buf)
1662{
1663 struct iwl_priv *priv = dev_get_drvdata(d);
1664
1665 if (!iwl_is_ready_rf(priv))
1666 return sprintf(buf, "off\n");
1667 else
1668 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1669}
1670
1671static ssize_t store_tx_power(struct device *d,
1672 struct device_attribute *attr,
1673 const char *buf, size_t count)
1674{
1675 struct iwl_priv *priv = dev_get_drvdata(d);
1676 unsigned long val;
1677 int ret;
1678
1679 ret = strict_strtoul(buf, 10, &val);
1680 if (ret)
1681 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1682 else {
1683 ret = iwl_set_tx_power(priv, val, false);
1684 if (ret)
1685 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1686 ret);
1687 else
1688 ret = count;
1689 }
1690 return ret;
1691}
1692
1693static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1694
7d47618a
EG		 1695static struct attribute *iwl_sysfs_entries[] = {
1696 &dev_attr_temperature.attr,
1697 &dev_attr_tx_power.attr,
7d47618a
EG		 1698#ifdef CONFIG_IWLWIFI_DEBUG
1699 &dev_attr_debug_level.attr,
1700#endif
1701 NULL
1702};
1703
1704static struct attribute_group iwl_attribute_group = {
1705 .name = NULL, /* put in device directory */
1706 .attrs = iwl_sysfs_entries,
1707};
1708
b481de9c
ZY		 1709/******************************************************************************
1710 *
1711 * uCode download functions
1712 *
1713 ******************************************************************************/
1714
5b9f8cd3 1715static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1716{
98c92211
TW		 1717 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1718 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1719 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1720 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1721 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1722 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1723}
1724
5b9f8cd3 1725static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1726{
1727 /* Remove all resets to allow NIC to operate */
1728 iwl_write32(priv, CSR_RESET, 0);
1729}
1730
dd7a2509
JB		 1731struct iwlagn_ucode_capabilities {
1732 u32 max_probe_length;
6a822d06 1733 u32 standard_phy_calibration_size;
ece9c4ee 1734 bool pan;
dd7a2509 1735};
edcdf8b2 1736
b08dfd04 1737static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1738static int iwl_mac_setup_register(struct iwl_priv *priv,
1739 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1740
39396085
JS		 1741#define UCODE_EXPERIMENTAL_INDEX 100
1742#define UCODE_EXPERIMENTAL_TAG "exp"
1743
b08dfd04
JB		 1744static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1745{
1746 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1747 char tag[8];
b08dfd04 1748
39396085
JS		 1749 if (first) {
1750#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1751 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1752 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1753 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1754#endif
b08dfd04 1755 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1756 sprintf(tag, "%d", priv->fw_index);
1757 } else {
b08dfd04 1758 priv->fw_index--;
39396085
JS		 1759 sprintf(tag, "%d", priv->fw_index);
1760 }
b08dfd04
JB		 1761
1762 if (priv->fw_index < priv->cfg->ucode_api_min) {
1763 IWL_ERR(priv, "no suitable firmware found!\n");
1764 return -ENOENT;
1765 }
1766
39396085 1767 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1768
39396085
JS		 1769 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1770 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1771 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1772 priv->firmware_name);
1773
1774 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1775 &priv->pci_dev->dev, GFP_KERNEL, priv,
1776 iwl_ucode_callback);
1777}
1778
0e9a44dc
JB		 1779struct iwlagn_firmware_pieces {
1780 const void *inst, *data, *init, *init_data, *boot;
1781 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1782
1783 u32 build;
b2e640d4
JB		 1784
1785 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1786 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1787};
1788
1789static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1790 const struct firmware *ucode_raw,
1791 struct iwlagn_firmware_pieces *pieces)
1792{
1793 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1794 u32 api_ver, hdr_size;
1795 const u8 *src;
1796
1797 priv->ucode_ver = le32_to_cpu(ucode->ver);
1798 api_ver = IWL_UCODE_API(priv->ucode_ver);
1799
1800 switch (api_ver) {
1801 default:
1802 /*
1803 * 4965 doesn't revision the firmware file format
1804 * along with the API version, it always uses v1
1805 * file format.
1806 */
1807 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1808 CSR_HW_REV_TYPE_4965) {
1809 hdr_size = 28;
1810 if (ucode_raw->size < hdr_size) {
1811 IWL_ERR(priv, "File size too small!\n");
1812 return -EINVAL;
1813 }
1814 pieces->build = le32_to_cpu(ucode->u.v2.build);
1815 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1816 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1817 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1818 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1819 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1820 src = ucode->u.v2.data;
1821 break;
1822 }
1823 /* fall through for 4965 */
1824 case 0:
1825 case 1:
1826 case 2:
1827 hdr_size = 24;
1828 if (ucode_raw->size < hdr_size) {
1829 IWL_ERR(priv, "File size too small!\n");
1830 return -EINVAL;
1831 }
1832 pieces->build = 0;
1833 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1834 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1835 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1836 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1837 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1838 src = ucode->u.v1.data;
1839 break;
1840 }
1841
1842 /* Verify size of file vs. image size info in file's header */
1843 if (ucode_raw->size != hdr_size + pieces->inst_size +
1844 pieces->data_size + pieces->init_size +
1845 pieces->init_data_size + pieces->boot_size) {
1846
1847 IWL_ERR(priv,
1848 "uCode file size %d does not match expected size\n",
1849 (int)ucode_raw->size);
1850 return -EINVAL;
1851 }
1852
1853 pieces->inst = src;
1854 src += pieces->inst_size;
1855 pieces->data = src;
1856 src += pieces->data_size;
1857 pieces->init = src;
1858 src += pieces->init_size;
1859 pieces->init_data = src;
1860 src += pieces->init_data_size;
1861 pieces->boot = src;
1862 src += pieces->boot_size;
1863
1864 return 0;
1865}
1866
dd7a2509
JB		 1867static int iwlagn_wanted_ucode_alternative = 1;
1868
1869static int iwlagn_load_firmware(struct iwl_priv *priv,
1870 const struct firmware *ucode_raw,
1871 struct iwlagn_firmware_pieces *pieces,
1872 struct iwlagn_ucode_capabilities *capa)
1873{
1874 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1875 struct iwl_ucode_tlv *tlv;
1876 size_t len = ucode_raw->size;
1877 const u8 *data;
1878 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1879 u64 alternatives;
ad8d8333
WYG		 1880 u32 tlv_len;
1881 enum iwl_ucode_tlv_type tlv_type;
1882 const u8 *tlv_data;
dd7a2509 1883
ad8d8333
WYG		 1884 if (len < sizeof(*ucode)) {
1885 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1886 return -EINVAL;
ad8d8333 1887 }
dd7a2509 1888
ad8d8333
WYG		 1889 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1890 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1891 le32_to_cpu(ucode->magic));
dd7a2509 1892 return -EINVAL;
ad8d8333 1893 }
dd7a2509
JB		 1894
1895 /*
1896 * Check which alternatives are present, and "downgrade"
1897 * when the chosen alternative is not present, warning
1898 * the user when that happens. Some files may not have
1899 * any alternatives, so don't warn in that case.
1900 */
1901 alternatives = le64_to_cpu(ucode->alternatives);
1902 tmp = wanted_alternative;
1903 if (wanted_alternative > 63)
1904 wanted_alternative = 63;
1905 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1906 wanted_alternative--;
1907 if (wanted_alternative && wanted_alternative != tmp)
1908 IWL_WARN(priv,
1909 "uCode alternative %d not available, choosing %d\n",
1910 tmp, wanted_alternative);
1911
1912 priv->ucode_ver = le32_to_cpu(ucode->ver);
1913 pieces->build = le32_to_cpu(ucode->build);
1914 data = ucode->data;
1915
1916 len -= sizeof(*ucode);
1917
704da534 1918 while (len >= sizeof(*tlv)) {
dd7a2509 1919 u16 tlv_alt;
dd7a2509
JB		 1920
1921 len -= sizeof(*tlv);
1922 tlv = (void *)data;
1923
1924 tlv_len = le32_to_cpu(tlv->length);
1925 tlv_type = le16_to_cpu(tlv->type);
1926 tlv_alt = le16_to_cpu(tlv->alternative);
1927 tlv_data = tlv->data;
1928
ad8d8333
WYG		 1929 if (len < tlv_len) {
1930 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1931 len, tlv_len);
dd7a2509 1932 return -EINVAL;
ad8d8333 1933 }
dd7a2509
JB		 1934 len -= ALIGN(tlv_len, 4);
1935 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1936
1937 /*
1938 * Alternative 0 is always valid.
1939 *
1940 * Skip alternative TLVs that are not selected.
1941 */
1942 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1943 continue;
1944
1945 switch (tlv_type) {
1946 case IWL_UCODE_TLV_INST:
1947 pieces->inst = tlv_data;
1948 pieces->inst_size = tlv_len;
1949 break;
1950 case IWL_UCODE_TLV_DATA:
1951 pieces->data = tlv_data;
1952 pieces->data_size = tlv_len;
1953 break;
1954 case IWL_UCODE_TLV_INIT:
1955 pieces->init = tlv_data;
1956 pieces->init_size = tlv_len;
1957 break;
1958 case IWL_UCODE_TLV_INIT_DATA:
1959 pieces->init_data = tlv_data;
1960 pieces->init_data_size = tlv_len;
1961 break;
1962 case IWL_UCODE_TLV_BOOT:
1963 pieces->boot = tlv_data;
1964 pieces->boot_size = tlv_len;
1965 break;
1966 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1967 if (tlv_len != sizeof(u32))
1968 goto invalid_tlv_len;
1969 capa->max_probe_length =
ad8d8333 1970 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1971 break;
ece9c4ee
JB		 1972 case IWL_UCODE_TLV_PAN:
1973 if (tlv_len)
1974 goto invalid_tlv_len;
1975 capa->pan = true;
1976 break;
b2e640d4 1977 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1978 if (tlv_len != sizeof(u32))
1979 goto invalid_tlv_len;
1980 pieces->init_evtlog_ptr =
ad8d8333 1981 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1982 break;
1983 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1984 if (tlv_len != sizeof(u32))
1985 goto invalid_tlv_len;
1986 pieces->init_evtlog_size =
ad8d8333 1987 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1988 break;
1989 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 1990 if (tlv_len != sizeof(u32))
1991 goto invalid_tlv_len;
1992 pieces->init_errlog_ptr =
ad8d8333 1993 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1994 break;
1995 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 1996 if (tlv_len != sizeof(u32))
1997 goto invalid_tlv_len;
1998 pieces->inst_evtlog_ptr =
ad8d8333 1999 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2000 break;
2001 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 2002 if (tlv_len != sizeof(u32))
2003 goto invalid_tlv_len;
2004 pieces->inst_evtlog_size =
ad8d8333 2005 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2006 break;
2007 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 2008 if (tlv_len != sizeof(u32))
2009 goto invalid_tlv_len;
2010 pieces->inst_errlog_ptr =
ad8d8333 2011 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 2012 break;
c8312fac
WYG		 2013 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2014 if (tlv_len)
704da534
JB		 2015 goto invalid_tlv_len;
2016 priv->enhance_sensitivity_table = true;
c8312fac 2017 break;
6a822d06 2018 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 2019 if (tlv_len != sizeof(u32))
2020 goto invalid_tlv_len;
2021 capa->standard_phy_calibration_size =
6a822d06
WYG		 2022 le32_to_cpup((__le32 *)tlv_data);
2023 break;
dd7a2509 2024 default:
ad8d8333 2025 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 2026 break;
2027 }
2028 }
2029
ad8d8333
WYG		 2030 if (len) {
2031 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2032 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 2033 return -EINVAL;
ad8d8333 2034 }
dd7a2509 2035
704da534
JB		 2036 return 0;
2037
2038 invalid_tlv_len:
2039 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2040 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2041
2042 return -EINVAL;
dd7a2509
JB		 2043}
2044
b481de9c 2045/**
b08dfd04 2046 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 2047 *
b08dfd04
JB		 2048 * If loaded successfully, copies the firmware into buffers
2049 * for the card to fetch (via DMA).
b481de9c 2050 */
b08dfd04 2051static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 2052{
b08dfd04 2053 struct iwl_priv *priv = context;
cc0f555d 2054 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 2055 int err;
2056 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 2057 const unsigned int api_max = priv->cfg->ucode_api_max;
2058 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 2059 u32 api_ver;
3e4de761 2060 char buildstr[25];
0e9a44dc 2061 u32 build;
dd7a2509
JB		 2062 struct iwlagn_ucode_capabilities ucode_capa = {
2063 .max_probe_length = 200,
6a822d06
WYG		 2064 .standard_phy_calibration_size =
2065 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 2066 };
0e9a44dc
JB		 2067
2068 memset(&pieces, 0, sizeof(pieces));
b481de9c 2069
b08dfd04 2070 if (!ucode_raw) {
39396085
JS		 2071 if (priv->fw_index <= priv->cfg->ucode_api_max)
2072 IWL_ERR(priv,
2073 "request for firmware file '%s' failed.\n",
2074 priv->firmware_name);
b08dfd04 2075 goto try_again;
b481de9c
ZY		 2076 }
2077
b08dfd04
JB		 2078 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2079 priv->firmware_name, ucode_raw->size);
b481de9c 2080
22adba2a
JB		 2081 /* Make sure that we got at least the API version number */
2082 if (ucode_raw->size < 4) {
15b1687c 2083 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 2084 goto try_again;
b481de9c
ZY		 2085 }
2086
2087 /* Data from ucode file: header followed by uCode images */
cc0f555d 2088 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2089
0e9a44dc
JB		 2090 if (ucode->ver)
2091 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2092 else
dd7a2509
JB		 2093 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2094 &ucode_capa);
22adba2a 2095
0e9a44dc
JB		 2096 if (err)
2097 goto try_again;
b481de9c 2098
a0987a8d 2099 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 2100 build = pieces.build;
a0987a8d 2101
0e9a44dc
JB		 2102 /*
2103 * api_ver should match the api version forming part of the
2104 * firmware filename ... but we don't check for that and only rely
2105 * on the API version read from firmware header from here on forward
2106 */
a0987a8d 2107 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2108 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 2109 "Driver supports v%u, firmware is v%u.\n",
2110 api_max, api_ver);
b08dfd04 2111 goto try_again;
a0987a8d 2112 }
b08dfd04 2113
a0987a8d 2114 if (api_ver != api_max)
978785a3 2115 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 2116 "got v%u. New firmware can be obtained "
2117 "from http://www.intellinuxwireless.org.\n",
2118 api_max, api_ver);
2119
3e4de761 2120 if (build)
39396085
JS		 2121 sprintf(buildstr, " build %u%s", build,
2122 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2123 ? " (EXP)" : "");
3e4de761
JB		 2124 else
2125 buildstr[0] = '\0';
2126
2127 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2128 IWL_UCODE_MAJOR(priv->ucode_ver),
2129 IWL_UCODE_MINOR(priv->ucode_ver),
2130 IWL_UCODE_API(priv->ucode_ver),
2131 IWL_UCODE_SERIAL(priv->ucode_ver),
2132 buildstr);
a0987a8d 2133
5ebeb5a6
RC		 2134 snprintf(priv->hw->wiphy->fw_version,
2135 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2136 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2137 IWL_UCODE_MAJOR(priv->ucode_ver),
2138 IWL_UCODE_MINOR(priv->ucode_ver),
2139 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2140 IWL_UCODE_SERIAL(priv->ucode_ver),
2141 buildstr);
b481de9c 2142
b08dfd04
JB		 2143 /*
2144 * For any of the failures below (before allocating pci memory)
2145 * we will try to load a version with a smaller API -- maybe the
2146 * user just got a corrupted version of the latest API.
2147 */
2148
0e9a44dc
JB		 2149 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2150 priv->ucode_ver);
2151 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2152 pieces.inst_size);
2153 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2154 pieces.data_size);
2155 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2156 pieces.init_size);
2157 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2158 pieces.init_data_size);
2159 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2160 pieces.boot_size);
b481de9c
ZY		 2161
2162 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2163 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2164 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2165 pieces.inst_size);
b08dfd04 2166 goto try_again;
b481de9c
ZY		 2167 }
2168
0e9a44dc
JB		 2169 if (pieces.data_size > priv->hw_params.max_data_size) {
2170 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2171 pieces.data_size);
b08dfd04 2172 goto try_again;
b481de9c 2173 }
0e9a44dc
JB		 2174
2175 if (pieces.init_size > priv->hw_params.max_inst_size) {
2176 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2177 pieces.init_size);
b08dfd04 2178 goto try_again;
b481de9c 2179 }
0e9a44dc
JB		 2180
2181 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2182 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2183 pieces.init_data_size);
b08dfd04 2184 goto try_again;
b481de9c 2185 }
0e9a44dc
JB		 2186
2187 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2188 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2189 pieces.boot_size);
b08dfd04 2190 goto try_again;
b481de9c
ZY		 2191 }
2192
2193 /* Allocate ucode buffers for card's bus-master loading ... */
2194
2195 /* Runtime instructions and 2 copies of data:
2196 * 1) unmodified from disk
2197 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2198 priv->ucode_code.len = pieces.inst_size;
98c92211 2199 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2200
0e9a44dc 2201 priv->ucode_data.len = pieces.data_size;
98c92211 2202 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2203
0e9a44dc 2204 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2205 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2206
1f304e4e
ZY		 2207 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2208 !priv->ucode_data_backup.v_addr)
2209 goto err_pci_alloc;
2210
b481de9c 2211 /* Initialization instructions and data */
0e9a44dc
JB		 2212 if (pieces.init_size && pieces.init_data_size) {
2213 priv->ucode_init.len = pieces.init_size;
98c92211 2214 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2215
0e9a44dc 2216 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2217 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2218
2219 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2220 goto err_pci_alloc;
2221 }
b481de9c
ZY		 2222
2223 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2224 if (pieces.boot_size) {
2225 priv->ucode_boot.len = pieces.boot_size;
98c92211 2226 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2227
90e759d1
TW		 2228 if (!priv->ucode_boot.v_addr)
2229 goto err_pci_alloc;
2230 }
b481de9c 2231
b2e640d4
JB		 2232 /* Now that we can no longer fail, copy information */
2233
2234 /*
2235 * The (size - 16) / 12 formula is based on the information recorded
2236 * for each event, which is of mode 1 (including timestamp) for all
2237 * new microcodes that include this information.
2238 */
2239 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2240 if (pieces.init_evtlog_size)
2241 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2242 else
7cb1b088
WYG		 2243 priv->_agn.init_evtlog_size =
2244 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2245 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2246 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2247 if (pieces.inst_evtlog_size)
2248 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2249 else
7cb1b088
WYG		 2250 priv->_agn.inst_evtlog_size =
2251 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2252 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2253
ece9c4ee
JB		 2254 if (ucode_capa.pan) {
2255 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
c10afb6e 2256 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
ece9c4ee
JB		 2257 } else
2258 priv->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 2259
b481de9c
ZY		 2260 /* Copy images into buffers for card's bus-master reads ... */
2261
2262 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2263 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2264 pieces.inst_size);
2265 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2266
e1623446 2267 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2268 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2269
0e9a44dc
JB		 2270 /*
2271 * Runtime data
2272 * NOTE: Copy into backup buffer will be done in iwl_up()
2273 */
2274 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2275 pieces.data_size);
2276 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2277 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2278
2279 /* Initialization instructions */
2280 if (pieces.init_size) {
e1623446 2281 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2282 pieces.init_size);
2283 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2284 }
2285
0e9a44dc
JB		 2286 /* Initialization data */
2287 if (pieces.init_data_size) {
e1623446 2288 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2289 pieces.init_data_size);
2290 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2291 pieces.init_data_size);
b481de9c
ZY		 2292 }
2293
0e9a44dc
JB		 2294 /* Bootstrap instructions */
2295 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2296 pieces.boot_size);
2297 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2298
6a822d06
WYG		 2299 /*
2300 * figure out the offset of chain noise reset and gain commands
2301 * base on the size of standard phy calibration commands table size
2302 */
2303 if (ucode_capa.standard_phy_calibration_size >
2304 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2305 ucode_capa.standard_phy_calibration_size =
2306 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2307
2308 priv->_agn.phy_calib_chain_noise_reset_cmd =
2309 ucode_capa.standard_phy_calibration_size;
2310 priv->_agn.phy_calib_chain_noise_gain_cmd =
2311 ucode_capa.standard_phy_calibration_size + 1;
2312
b08dfd04
JB		 2313 /**************************************************
2314 * This is still part of probe() in a sense...
2315 *
2316 * 9. Setup and register with mac80211 and debugfs
2317 **************************************************/
dd7a2509 2318 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2319 if (err)
2320 goto out_unbind;
2321
2322 err = iwl_dbgfs_register(priv, DRV_NAME);
2323 if (err)
2324 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2325
7d47618a
EG		 2326 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2327 &iwl_attribute_group);
2328 if (err) {
2329 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2330 goto out_unbind;
2331 }
2332
b481de9c
ZY		 2333 /* We have our copies now, allow OS release its copies */
2334 release_firmware(ucode_raw);
a15707d8 2335 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2336 return;
2337
2338 try_again:
2339 /* try next, if any */
2340 if (iwl_request_firmware(priv, false))
2341 goto out_unbind;
2342 release_firmware(ucode_raw);
2343 return;
b481de9c
ZY		 2344
2345 err_pci_alloc:
15b1687c 2346 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2347 iwl_dealloc_ucode_pci(priv);
b08dfd04 2348 out_unbind:
a15707d8 2349 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2350 device_release_driver(&priv->pci_dev->dev);
b481de9c 2351 release_firmware(ucode_raw);
b481de9c
ZY		 2352}
2353
b7a79404
RC		 2354static const char *desc_lookup_text[] = {
2355 "OK",
2356 "FAIL",
2357 "BAD_PARAM",
2358 "BAD_CHECKSUM",
2359 "NMI_INTERRUPT_WDG",
2360 "SYSASSERT",
2361 "FATAL_ERROR",
2362 "BAD_COMMAND",
2363 "HW_ERROR_TUNE_LOCK",
2364 "HW_ERROR_TEMPERATURE",
2365 "ILLEGAL_CHAN_FREQ",
2366 "VCC_NOT_STABLE",
2367 "FH_ERROR",
2368 "NMI_INTERRUPT_HOST",
2369 "NMI_INTERRUPT_ACTION_PT",
2370 "NMI_INTERRUPT_UNKNOWN",
2371 "UCODE_VERSION_MISMATCH",
2372 "HW_ERROR_ABS_LOCK",
2373 "HW_ERROR_CAL_LOCK_FAIL",
2374 "NMI_INTERRUPT_INST_ACTION_PT",
2375 "NMI_INTERRUPT_DATA_ACTION_PT",
2376 "NMI_TRM_HW_ER",
2377 "NMI_INTERRUPT_TRM",
2378 "NMI_INTERRUPT_BREAK_POINT"
2379 "DEBUG_0",
2380 "DEBUG_1",
2381 "DEBUG_2",
2382 "DEBUG_3",
b7a79404
RC		 2383};
2384
4b58645c
JS		 2385static struct { char *name; u8 num; } advanced_lookup[] = {
2386 { "NMI_INTERRUPT_WDG", 0x34 },
2387 { "SYSASSERT", 0x35 },
2388 { "UCODE_VERSION_MISMATCH", 0x37 },
2389 { "BAD_COMMAND", 0x38 },
2390 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2391 { "FATAL_ERROR", 0x3D },
2392 { "NMI_TRM_HW_ERR", 0x46 },
2393 { "NMI_INTERRUPT_TRM", 0x4C },
2394 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2395 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2396 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2397 { "NMI_INTERRUPT_HOST", 0x66 },
2398 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2399 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2400 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2401 { "ADVANCED_SYSASSERT", 0 },
2402};
2403
2404static const char *desc_lookup(u32 num)
b7a79404 2405{
4b58645c
JS		 2406 int i;
2407 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2408
4b58645c
JS		 2409 if (num < max)
2410 return desc_lookup_text[num];
b7a79404 2411
4b58645c
JS		 2412 max = ARRAY_SIZE(advanced_lookup) - 1;
2413 for (i = 0; i < max; i++) {
2414 if (advanced_lookup[i].num == num)
2415 break;;
2416 }
2417 return advanced_lookup[i].name;
b7a79404
RC		 2418}
2419
2420#define ERROR_START_OFFSET (1 * sizeof(u32))
2421#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2422
2423void iwl_dump_nic_error_log(struct iwl_priv *priv)
2424{
2425 u32 data2, line;
2426 u32 desc, time, count, base, data1;
2427 u32 blink1, blink2, ilink1, ilink2;
461ef382 2428 u32 pc, hcmd;
b7a79404 2429
b2e640d4 2430 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2431 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2432 if (!base)
2433 base = priv->_agn.init_errlog_ptr;
2434 } else {
b7a79404 2435 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2436 if (!base)
2437 base = priv->_agn.inst_errlog_ptr;
2438 }
b7a79404
RC		 2439
2440 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2441 IWL_ERR(priv,
2442 "Not valid error log pointer 0x%08X for %s uCode\n",
2443 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2444 return;
2445 }
2446
2447 count = iwl_read_targ_mem(priv, base);
2448
2449 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2450 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2451 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2452 priv->status, count);
2453 }
2454
2455 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
6e6ebf4b 2456 priv->isr_stats.err_code = desc;
461ef382 2457 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2458 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2459 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2460 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2461 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2462 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2463 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2464 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2465 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2466 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2467
be1a71a1
JB		 2468 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2469 blink1, blink2, ilink1, ilink2);
2470
87563715 2471 IWL_ERR(priv, "Desc Time "
b7a79404 2472 "data1 data2 line\n");
87563715 2473 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2474 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2475 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2476 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2477 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2478}
2479
2480#define EVENT_START_OFFSET (4 * sizeof(u32))
2481
2482/**
2483 * iwl_print_event_log - Dump error event log to syslog
2484 *
2485 */
b03d7d0f
WYG		 2486static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2487 u32 num_events, u32 mode,
2488 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2489{
2490 u32 i;
2491 u32 base; /* SRAM byte address of event log header */
2492 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2493 u32 ptr; /* SRAM byte address of log data */
2494 u32 ev, time, data; /* event log data */
e5854471 2495 unsigned long reg_flags;
b7a79404
RC		 2496
2497 if (num_events == 0)
b03d7d0f 2498 return pos;
b2e640d4
JB		 2499
2500 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2501 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2502 if (!base)
2503 base = priv->_agn.init_evtlog_ptr;
2504 } else {
b7a79404 2505 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2506 if (!base)
2507 base = priv->_agn.inst_evtlog_ptr;
2508 }
b7a79404
RC		 2509
2510 if (mode == 0)
2511 event_size = 2 * sizeof(u32);
2512 else
2513 event_size = 3 * sizeof(u32);
2514
2515 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2516
e5854471
BC		 2517 /* Make sure device is powered up for SRAM reads */
2518 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2519 iwl_grab_nic_access(priv);
2520
2521 /* Set starting address; reads will auto-increment */
2522 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2523 rmb();
2524
b7a79404
RC		 2525 /* "time" is actually "data" for mode 0 (no timestamp).
2526 * place event id # at far right for easier visual parsing. */
2527 for (i = 0; i < num_events; i++) {
e5854471
BC		 2528 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2529 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2530 if (mode == 0) {
2531 /* data, ev */
b03d7d0f
WYG		 2532 if (bufsz) {
2533 pos += scnprintf(*buf + pos, bufsz - pos,
2534 "EVT_LOG:0x%08x:%04u\n",
2535 time, ev);
2536 } else {
2537 trace_iwlwifi_dev_ucode_event(priv, 0,
2538 time, ev);
2539 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2540 time, ev);
2541 }
b7a79404 2542 } else {
e5854471 2543 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2544 if (bufsz) {
2545 pos += scnprintf(*buf + pos, bufsz - pos,
2546 "EVT_LOGT:%010u:0x%08x:%04u\n",
2547 time, data, ev);
2548 } else {
2549 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2550 time, data, ev);
b03d7d0f
WYG		 2551 trace_iwlwifi_dev_ucode_event(priv, time,
2552 data, ev);
2553 }
b7a79404
RC		 2554 }
2555 }
e5854471
BC		 2556
2557 /* Allow device to power down */
2558 iwl_release_nic_access(priv);
2559 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2560 return pos;
b7a79404
RC		 2561}
2562
c341ddb2
WYG		 2563/**
2564 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2565 */
b03d7d0f
WYG		 2566static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2567 u32 num_wraps, u32 next_entry,
2568 u32 size, u32 mode,
2569 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2570{
2571 /*
2572 * display the newest DEFAULT_LOG_ENTRIES entries
2573 * i.e the entries just before the next ont that uCode would fill.
2574 */
2575 if (num_wraps) {
2576 if (next_entry < size) {
b03d7d0f
WYG		 2577 pos = iwl_print_event_log(priv,
2578 capacity - (size - next_entry),
2579 size - next_entry, mode,
2580 pos, buf, bufsz);
2581 pos = iwl_print_event_log(priv, 0,
2582 next_entry, mode,
2583 pos, buf, bufsz);
c341ddb2 2584 } else
b03d7d0f
WYG		 2585 pos = iwl_print_event_log(priv, next_entry - size,
2586 size, mode, pos, buf, bufsz);
c341ddb2 2587 } else {
b03d7d0f
WYG		 2588 if (next_entry < size) {
2589 pos = iwl_print_event_log(priv, 0, next_entry,
2590 mode, pos, buf, bufsz);
2591 } else {
2592 pos = iwl_print_event_log(priv, next_entry - size,
2593 size, mode, pos, buf, bufsz);
2594 }
c341ddb2 2595 }
b03d7d0f 2596 return pos;
c341ddb2
WYG		 2597}
2598
c341ddb2
WYG		 2599#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2600
b03d7d0f
WYG		 2601int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2602 char **buf, bool display)
b7a79404
RC		 2603{
2604 u32 base; /* SRAM byte address of event log header */
2605 u32 capacity; /* event log capacity in # entries */
2606 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2607 u32 num_wraps; /* # times uCode wrapped to top of log */
2608 u32 next_entry; /* index of next entry to be written by uCode */
2609 u32 size; /* # entries that we'll print */
b2e640d4 2610 u32 logsize;
b03d7d0f
WYG		 2611 int pos = 0;
2612 size_t bufsz = 0;
b7a79404 2613
b2e640d4 2614 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2615 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2616 logsize = priv->_agn.init_evtlog_size;
2617 if (!base)
2618 base = priv->_agn.init_evtlog_ptr;
2619 } else {
b7a79404 2620 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2621 logsize = priv->_agn.inst_evtlog_size;
2622 if (!base)
2623 base = priv->_agn.inst_evtlog_ptr;
2624 }
b7a79404
RC		 2625
2626 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2627 IWL_ERR(priv,
2628 "Invalid event log pointer 0x%08X for %s uCode\n",
2629 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2630 return -EINVAL;
b7a79404
RC		 2631 }
2632
2633 /* event log header */
2634 capacity = iwl_read_targ_mem(priv, base);
2635 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2636 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2637 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2638
b2e640d4 2639 if (capacity > logsize) {
84c40692 2640 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2641 capacity, logsize);
2642 capacity = logsize;
84c40692
BC		 2643 }
2644
b2e640d4 2645 if (next_entry > logsize) {
84c40692 2646 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2647 next_entry, logsize);
2648 next_entry = logsize;
84c40692
BC		 2649 }
2650
b7a79404
RC		 2651 size = num_wraps ? capacity : next_entry;
2652
2653 /* bail out if nothing in log */
2654 if (size == 0) {
2655 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2656 return pos;
b7a79404
RC		 2657 }
2658
f37837c9
WYG		 2659 /* enable/disable bt channel announcement */
2660 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2661
c341ddb2 2662#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2663 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2664 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2665 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2666#else
2667 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2668 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2669#endif
2670 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2671 size);
b7a79404 2672
c341ddb2 2673#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2674 if (display) {
2675 if (full_log)
2676 bufsz = capacity * 48;
2677 else
2678 bufsz = size * 48;
2679 *buf = kmalloc(bufsz, GFP_KERNEL);
2680 if (!*buf)
937c397e 2681 return -ENOMEM;
b03d7d0f 2682 }
c341ddb2
WYG		 2683 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2684 /*
2685 * if uCode has wrapped back to top of log,
2686 * start at the oldest entry,
2687 * i.e the next one that uCode would fill.
2688 */
2689 if (num_wraps)
b03d7d0f
WYG		 2690 pos = iwl_print_event_log(priv, next_entry,
2691 capacity - next_entry, mode,
2692 pos, buf, bufsz);
c341ddb2 2693 /* (then/else) start at top of log */
b03d7d0f
WYG		 2694 pos = iwl_print_event_log(priv, 0,
2695 next_entry, mode, pos, buf, bufsz);
c341ddb2 2696 } else
b03d7d0f
WYG		 2697 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2698 next_entry, size, mode,
2699 pos, buf, bufsz);
c341ddb2 2700#else
b03d7d0f
WYG		 2701 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2702 next_entry, size, mode,
2703 pos, buf, bufsz);
b7a79404 2704#endif
b03d7d0f 2705 return pos;
c341ddb2 2706}
b7a79404 2707
0975cc8f
WYG		 2708static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2709{
2710 struct iwl_ct_kill_config cmd;
2711 struct iwl_ct_kill_throttling_config adv_cmd;
2712 unsigned long flags;
2713 int ret = 0;
2714
2715 spin_lock_irqsave(&priv->lock, flags);
2716 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2717 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2718 spin_unlock_irqrestore(&priv->lock, flags);
2719 priv->thermal_throttle.ct_kill_toggle = false;
2720
7cb1b088 2721 if (priv->cfg->base_params->support_ct_kill_exit) {
0975cc8f
WYG		 2722 adv_cmd.critical_temperature_enter =
2723 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2724 adv_cmd.critical_temperature_exit =
2725 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2726
2727 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2728 sizeof(adv_cmd), &adv_cmd);
2729 if (ret)
2730 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2731 else
2732 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2733 "succeeded, "
2734 "critical temperature enter is %d,"
2735 "exit is %d\n",
2736 priv->hw_params.ct_kill_threshold,
2737 priv->hw_params.ct_kill_exit_threshold);
2738 } else {
2739 cmd.critical_temperature_R =
2740 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2741
2742 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2743 sizeof(cmd), &cmd);
2744 if (ret)
2745 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2746 else
2747 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2748 "succeeded, "
2749 "critical temperature is %d\n",
2750 priv->hw_params.ct_kill_threshold);
2751 }
2752}
2753
6d6a1afd
SZ		 2754static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2755{
2756 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2757 struct iwl_host_cmd cmd = {
2758 .id = CALIBRATION_CFG_CMD,
2759 .len = sizeof(struct iwl_calib_cfg_cmd),
2760 .data = &calib_cfg_cmd,
2761 };
2762
2763 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2764 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
7cb1b088 2765 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
6d6a1afd
SZ		 2766
2767 return iwl_send_cmd(priv, &cmd);
2768}
2769
2770
b481de9c 2771/**
4a4a9e81 2772 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2773 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2774 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2775 */
4a4a9e81 2776static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2777{
57aab75a 2778 int ret = 0;
246ed355 2779 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2780
e1623446 2781 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2782
2783 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2784 /* We had an error bringing up the hardware, so take it
2785 * all the way back down so we can try again */
e1623446 2786 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2787 goto restart;
2788 }
2789
2790 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2791 * This is a paranoid check, because we would not have gotten the
2792 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2793 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2794 /* Runtime instruction load was bad;
2795 * take it all the way back down so we can try again */
e1623446 2796 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2797 goto restart;
2798 }
2799
57aab75a
TW		 2800 ret = priv->cfg->ops->lib->alive_notify(priv);
2801 if (ret) {
39aadf8c
WT		 2802 IWL_WARN(priv,
2803 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2804 goto restart;
2805 }
2806
6d6a1afd
SZ		 2807 if (priv->hw_params.calib_rt_cfg)
2808 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2809
2810
5b9f8cd3 2811 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2812 set_bit(STATUS_ALIVE, &priv->status);
2813
b74e31a9
WYG		 2814 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2815 /* Enable timer to monitor the driver queues */
2816 mod_timer(&priv->monitor_recover,
2817 jiffies +
7cb1b088
WYG		 2818 msecs_to_jiffies(
2819 priv->cfg->base_params->monitor_recover_period));
b74e31a9
WYG		 2820 }
2821
fee1247a 2822 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2823 return;
2824
7cb1b088
WYG		 2825 if (priv->cfg->bt_params &&
2826 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f
WYG		 2827 /* Configure Bluetooth device coexistence support */
2828 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2829 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2830 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2831 priv->cfg->ops->hcmd->send_bt_config(priv);
2832 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2833 if (bt_coex_active && priv->iw_mode != NL80211_IFTYPE_ADHOC)
2834 iwlagn_send_prio_tbl(priv);
2835
2836 /* FIXME: w/a to force change uCode BT state machine */
2837 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2838 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2839 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2840 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2841 }
36d6825b 2842 ieee80211_wake_queues(priv->hw);
b481de9c 2843
470ab2dd 2844 priv->active_rate = IWL_RATES_MASK;
b481de9c 2845
2f748dec
WYG		 2846 /* Configure Tx antenna selection based on H/W config */
2847 if (priv->cfg->ops->hcmd->set_tx_ant)
2848 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2849
246ed355 2850 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2851 struct iwl_rxon_cmd *active_rxon =
246ed355 2852 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2853 /* apply any changes in staging */
246ed355 2854 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2855 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2856 } else {
d0fe478c 2857 struct iwl_rxon_context *tmp;
b481de9c 2858 /* Initialize our rx_config data */
d0fe478c
JB		 2859 for_each_context(priv, tmp)
2860 iwl_connection_init_rx_config(priv, tmp);
45823531
AK		 2861
2862 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 2863 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c
ZY		 2864 }
2865
7cb1b088
WYG		 2866 if (priv->cfg->bt_params &&
2867 !priv->cfg->bt_params->advanced_bt_coexist) {
aeb4a2ee
WYG		 2868 /* Configure Bluetooth device coexistence support */
2869 priv->cfg->ops->hcmd->send_bt_config(priv);
2870 }
b481de9c 2871
4a4a9e81
TW		 2872 iwl_reset_run_time_calib(priv);
2873
b481de9c 2874 /* Configure the adapter for unassociated operation */
246ed355 2875 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 2876
2877 /* At this point, the NIC is initialized and operational */
47f4a587 2878 iwl_rf_kill_ct_config(priv);
5a66926a 2879
e932a609 2880 iwl_leds_init(priv);
fe00b5a5 2881
e1623446 2882 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2883 set_bit(STATUS_READY, &priv->status);
5a66926a 2884 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2885
e312c24c 2886 iwl_power_update_mode(priv, true);
7e246191
RC		 2887 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2888
c46fbefa 2889
b481de9c
ZY		 2890 return;
2891
2892 restart:
2893 queue_work(priv->workqueue, &priv->restart);
2894}
2895
4e39317d 2896static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2897
5b9f8cd3 2898static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2899{
2900 unsigned long flags;
2901 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2902
e1623446 2903 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2904
d745d472
SG		 2905 iwl_scan_cancel_timeout(priv, 200);
2906
2907 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2908
b62177a0
SG		 2909 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2910 * to prevent rearm timer */
2911 if (priv->cfg->ops->lib->recover_from_tx_stall)
2912 del_timer_sync(&priv->monitor_recover);
2913
dcef732c 2914 iwl_clear_ucode_stations(priv, NULL);
a194e324 2915 iwl_dealloc_bcast_stations(priv);
db125c78 2916 iwl_clear_driver_stations(priv);
b481de9c 2917
a1174138 2918 /* reset BT coex data */
da5dbb97 2919 priv->bt_status = 0;
7cb1b088
WYG		 2920 if (priv->cfg->bt_params)
2921 priv->bt_traffic_load =
2922 priv->cfg->bt_params->bt_init_traffic_load;
2923 else
2924 priv->bt_traffic_load = 0;
a1174138 2925 priv->bt_sco_active = false;
bee008b7
WYG		 2926 priv->bt_full_concurrent = false;
2927 priv->bt_ci_compliance = 0;
a1174138 2928
b481de9c
ZY		 2929 /* Unblock any waiting calls */
2930 wake_up_interruptible_all(&priv->wait_command_queue);
2931
b481de9c
ZY		 2932 /* Wipe out the EXIT_PENDING status bit if we are not actually
2933 * exiting the module */
2934 if (!exit_pending)
2935 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2936
2937 /* stop and reset the on-board processor */
3395f6e9 2938 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2939
2940 /* tell the device to stop sending interrupts */
0359facc 2941 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2942 iwl_disable_interrupts(priv);
0359facc
MA		 2943 spin_unlock_irqrestore(&priv->lock, flags);
2944 iwl_synchronize_irq(priv);
b481de9c
ZY		 2945
2946 if (priv->mac80211_registered)
2947 ieee80211_stop_queues(priv->hw);
2948
5b9f8cd3 2949 /* If we have not previously called iwl_init() then
a60e77e5 2950 * clear all bits but the RF Kill bit and return */
fee1247a 2951 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2952 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2953 STATUS_RF_KILL_HW |
9788864e
RC		 2954 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2955 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2956 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2957 STATUS_EXIT_PENDING;
b481de9c
ZY		 2958 goto exit;
2959 }
2960
6da3a13e 2961 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2962 * bit and continue taking the NIC down. */
b481de9c
ZY		 2963 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2964 STATUS_RF_KILL_HW |
9788864e
RC		 2965 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2966 STATUS_GEO_CONFIGURED |
b481de9c 2967 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2968 STATUS_FW_ERROR |
2969 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2970 STATUS_EXIT_PENDING;
b481de9c 2971
ef850d7c
MA		 2972 /* device going down, Stop using ICT table */
2973 iwl_disable_ict(priv);
b481de9c 2974
74bcdb33 2975 iwlagn_txq_ctx_stop(priv);
54b81550 2976 iwlagn_rxq_stop(priv);
b481de9c 2977
309e731a
BC		 2978 /* Power-down device's busmaster DMA clocks */
2979 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2980 udelay(5);
2981
309e731a
BC		 2982 /* Make sure (redundant) we've released our request to stay awake */
2983 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2984
4d2ccdb9 2985 /* Stop the device, and put it in low power state */
14e8e4af 2986 iwl_apm_stop(priv);
4d2ccdb9 2987
b481de9c 2988 exit:
885ba202 2989 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2990
2991 if (priv->ibss_beacon)
2992 dev_kfree_skb(priv->ibss_beacon);
2993 priv->ibss_beacon = NULL;
2994
2995 /* clear out any free frames */
fcab423d 2996 iwl_clear_free_frames(priv);
b481de9c
ZY		 2997}
2998
5b9f8cd3 2999static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 3000{
3001 mutex_lock(&priv->mutex);
5b9f8cd3 3002 __iwl_down(priv);
b481de9c 3003 mutex_unlock(&priv->mutex);
b24d22b1 3004
4e39317d 3005 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 3006}
3007
086ed117
MA		 3008#define HW_READY_TIMEOUT (50)
3009
3010static int iwl_set_hw_ready(struct iwl_priv *priv)
3011{
3012 int ret = 0;
3013
3014 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3015 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
3016
3017 /* See if we got it */
3018 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3019 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3020 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3021 HW_READY_TIMEOUT);
3022 if (ret != -ETIMEDOUT)
3023 priv->hw_ready = true;
3024 else
3025 priv->hw_ready = false;
3026
3027 IWL_DEBUG_INFO(priv, "hardware %s\n",
3028 (priv->hw_ready == 1) ? "ready" : "not ready");
3029 return ret;
3030}
3031
3032static int iwl_prepare_card_hw(struct iwl_priv *priv)
3033{
3034 int ret = 0;
3035
91dd6c27 3036 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 3037
3354a0f6
MA		 3038 ret = iwl_set_hw_ready(priv);
3039 if (priv->hw_ready)
3040 return ret;
3041
3042 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 3043 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3044 CSR_HW_IF_CONFIG_REG_PREPARE);
3045
3046 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3047 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3048 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3049
3354a0f6 3050 /* HW should be ready by now, check again. */
086ed117
MA		 3051 if (ret != -ETIMEDOUT)
3052 iwl_set_hw_ready(priv);
3053
3054 return ret;
3055}
3056
b481de9c
ZY		 3057#define MAX_HW_RESTARTS 5
3058
5b9f8cd3 3059static int __iwl_up(struct iwl_priv *priv)
b481de9c 3060{
a194e324 3061 struct iwl_rxon_context *ctx;
57aab75a
TW		 3062 int i;
3063 int ret;
b481de9c
ZY		 3064
3065 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 3066 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 3067 return -EIO;
3068 }
3069
e903fbd4 3070 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 3071 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 3072 return -EIO;
3073 }
3074
a194e324 3075 for_each_context(priv, ctx) {
a30e3112 3076 ret = iwlagn_alloc_bcast_station(priv, ctx);
a194e324
JB		 3077 if (ret) {
3078 iwl_dealloc_bcast_stations(priv);
3079 return ret;
3080 }
3081 }
2c810ccd 3082
086ed117
MA		 3083 iwl_prepare_card_hw(priv);
3084
3085 if (!priv->hw_ready) {
3086 IWL_WARN(priv, "Exit HW not ready\n");
3087 return -EIO;
3088 }
3089
e655b9f0 3090 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 3091 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 3092 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3093 else
e655b9f0 3094 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3095
c1842d61 3096 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 3097 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3098
5b9f8cd3 3099 iwl_enable_interrupts(priv);
a60e77e5 3100 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 3101 return 0;
b481de9c
ZY		 3102 }
3103
3395f6e9 3104 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 3105
13bb9483 3106 /* must be initialised before iwl_hw_nic_init */
751ca305
JB		 3107 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3108 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3109 else
3110 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
13bb9483 3111
74bcdb33 3112 ret = iwlagn_hw_nic_init(priv);
57aab75a 3113 if (ret) {
15b1687c 3114 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 3115 return ret;
b481de9c
ZY		 3116 }
3117
3118 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3119 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3120 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 3121 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3122
3123 /* clear (again), then enable host interrupts */
3395f6e9 3124 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 3125 iwl_enable_interrupts(priv);
b481de9c
ZY		 3126
3127 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3128 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3129 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3130
3131 /* Copy original ucode data image from disk into backup cache.
3132 * This will be used to initialize the on-board processor's
3133 * data SRAM for a clean start when the runtime program first loads. */
3134 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 3135 priv->ucode_data.len);
b481de9c 3136
b481de9c
ZY		 3137 for (i = 0; i < MAX_HW_RESTARTS; i++) {
3138
b481de9c
ZY		 3139 /* load bootstrap state machine,
3140 * load bootstrap program into processor's memory,
3141 * prepare to load the "initialize" uCode */
57aab75a 3142 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 3143
57aab75a 3144 if (ret) {
15b1687c
WT		 3145 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3146 ret);
b481de9c
ZY		 3147 continue;
3148 }
3149
3150 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 3151 iwl_nic_start(priv);
b481de9c 3152
e1623446 3153 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 3154
3155 return 0;
3156 }
3157
3158 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 3159 __iwl_down(priv);
64e72c3e 3160 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 3161
3162 /* tried to restart and config the device for as long as our
3163 * patience could withstand */
15b1687c 3164 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 3165 return -EIO;
3166}
3167
3168
3169/*****************************************************************************
3170 *
3171 * Workqueue callbacks
3172 *
3173 *****************************************************************************/
3174
4a4a9e81 3175static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 3176{
c79dd5b5
TW		 3177 struct iwl_priv *priv =
3178 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 3179
3180 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3181 return;
3182
3183 mutex_lock(&priv->mutex);
f3ccc08c 3184 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 3185 mutex_unlock(&priv->mutex);
3186}
3187
4a4a9e81 3188static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 3189{
c79dd5b5
TW		 3190 struct iwl_priv *priv =
3191 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3192
3193 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3194 return;
3195
258c44a0
MA		 3196 /* enable dram interrupt */
3197 iwl_reset_ict(priv);
3198
b481de9c 3199 mutex_lock(&priv->mutex);
4a4a9e81 3200 iwl_alive_start(priv);
b481de9c
ZY		 3201 mutex_unlock(&priv->mutex);
3202}
3203
16e727e8
EG		 3204static void iwl_bg_run_time_calib_work(struct work_struct *work)
3205{
3206 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3207 run_time_calib_work);
3208
3209 mutex_lock(&priv->mutex);
3210
3211 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3212 test_bit(STATUS_SCANNING, &priv->status)) {
3213 mutex_unlock(&priv->mutex);
3214 return;
3215 }
3216
3217 if (priv->start_calib) {
7cb1b088
WYG		 3218 if (priv->cfg->bt_params &&
3219 priv->cfg->bt_params->bt_statistics) {
7980fba5
WYG		 3220 iwl_chain_noise_calibration(priv,
3221 (void *)&priv->_agn.statistics_bt);
3222 iwl_sensitivity_calibration(priv,
3223 (void *)&priv->_agn.statistics_bt);
3224 } else {
3225 iwl_chain_noise_calibration(priv,
3226 (void *)&priv->_agn.statistics);
3227 iwl_sensitivity_calibration(priv,
3228 (void *)&priv->_agn.statistics);
3229 }
16e727e8
EG		 3230 }
3231
3232 mutex_unlock(&priv->mutex);
16e727e8
EG		 3233}
3234
5b9f8cd3 3235static void iwl_bg_restart(struct work_struct *data)
b481de9c 3236{
c79dd5b5 3237 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3238
3239 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3240 return;
3241
19cc1087 3242 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
8bd413e6 3243 struct iwl_rxon_context *ctx;
bee008b7
WYG		 3244 bool bt_sco, bt_full_concurrent;
3245 u8 bt_ci_compliance;
511b082d 3246 u8 bt_load;
da5dbb97 3247 u8 bt_status;
511b082d 3248
19cc1087 3249 mutex_lock(&priv->mutex);
8bd413e6
JB		 3250 for_each_context(priv, ctx)
3251 ctx->vif = NULL;
19cc1087 3252 priv->is_open = 0;
511b082d
JB		 3253
3254 /*
3255 * __iwl_down() will clear the BT status variables,
3256 * which is correct, but when we restart we really
3257 * want to keep them so restore them afterwards.
3258 *
3259 * The restart process will later pick them up and
3260 * re-configure the hw when we reconfigure the BT
3261 * command.
3262 */
3263 bt_sco = priv->bt_sco_active;
bee008b7
WYG		 3264 bt_full_concurrent = priv->bt_full_concurrent;
3265 bt_ci_compliance = priv->bt_ci_compliance;
511b082d 3266 bt_load = priv->bt_traffic_load;
da5dbb97 3267 bt_status = priv->bt_status;
511b082d 3268
a1174138 3269 __iwl_down(priv);
511b082d
JB		 3270
3271 priv->bt_sco_active = bt_sco;
bee008b7
WYG		 3272 priv->bt_full_concurrent = bt_full_concurrent;
3273 priv->bt_ci_compliance = bt_ci_compliance;
511b082d 3274 priv->bt_traffic_load = bt_load;
da5dbb97 3275 priv->bt_status = bt_status;
511b082d 3276
19cc1087 3277 mutex_unlock(&priv->mutex);
a1174138 3278 iwl_cancel_deferred_work(priv);
19cc1087
JB		 3279 ieee80211_restart_hw(priv->hw);
3280 } else {
3281 iwl_down(priv);
80676518
JB		 3282
3283 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3284 return;
3285
3286 mutex_lock(&priv->mutex);
3287 __iwl_up(priv);
3288 mutex_unlock(&priv->mutex);
19cc1087 3289 }
b481de9c
ZY		 3290}
3291
5b9f8cd3 3292static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3293{
c79dd5b5
TW		 3294 struct iwl_priv *priv =
3295 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3296
3297 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3298 return;
3299
3300 mutex_lock(&priv->mutex);
54b81550 3301 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3302 mutex_unlock(&priv->mutex);
3303}
3304
7878a5a4
MA		 3305#define IWL_DELAY_NEXT_SCAN (HZ*2)
3306
1dda6d28 3307void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3308{
246ed355 3309 struct iwl_rxon_context *ctx;
b481de9c 3310 struct ieee80211_conf *conf = NULL;
857485c0 3311 int ret = 0;
b481de9c 3312
1dda6d28
JB		 3313 if (!vif || !priv->is_open)
3314 return;
3315
246ed355
JB		 3316 ctx = iwl_rxon_ctx_from_vif(vif);
3317
1dda6d28 3318 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3319 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 3320 return;
3321 }
3322
b481de9c
ZY		 3323 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3324 return;
3325
2a421b91 3326 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3327
b481de9c
ZY		 3328 conf = ieee80211_get_hw_conf(priv->hw);
3329
246ed355
JB		 3330 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3331 iwlcore_commit_rxon(priv, ctx);
b481de9c 3332
47313e34 3333 ret = iwl_send_rxon_timing(priv, ctx);
857485c0 3334 if (ret)
8f2d3d2a 3335 IWL_WARN(priv, "RXON timing - "
b481de9c
ZY		 3336 "Attempting to continue.\n");
3337
246ed355 3338 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3339
42eb7c64 3340 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3341
45823531 3342 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3343 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
45823531 3344
246ed355 3345 ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3346
e1623446 3347 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3348 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3349
c213d745 3350 if (vif->bss_conf.use_short_preamble)
246ed355 3351 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3352 else
246ed355 3353 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3354
246ed355 3355 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3356 if (vif->bss_conf.use_short_slot)
246ed355 3357 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3358 else
246ed355 3359 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3360 }
3361
246ed355 3362 iwlcore_commit_rxon(priv, ctx);
b481de9c 3363
fe6b23dd 3364 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
246ed355 3365 vif->bss_conf.aid, ctx->active.bssid_addr);
fe6b23dd 3366
1dda6d28 3367 switch (vif->type) {
05c914fe 3368 case NL80211_IFTYPE_STATION:
b481de9c 3369 break;
05c914fe 3370 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3371 iwl_send_beacon_cmd(priv);
b481de9c 3372 break;
b481de9c 3373 default:
15b1687c 3374 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3375 __func__, vif->type);
b481de9c
ZY		 3376 break;
3377 }
3378
04816448
GE		 3379 /* the chain noise calibration will enabled PM upon completion
3380 * If chain noise has already been run, then we need to enable
3381 * power management here */
3382 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3383 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3384
3385 /* Enable Rx differential gain and sensitivity calibrations */
3386 iwl_chain_noise_reset(priv);
3387 priv->start_calib = 1;
3388
508e32e1
RC		 3389}
3390
b481de9c
ZY		 3391/*****************************************************************************
3392 *
3393 * mac80211 entry point functions
3394 *
3395 *****************************************************************************/
3396
154b25ce 3397#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3398
f0b6e2e8
RC		 3399/*
3400 * Not a mac80211 entry point function, but it fits in with all the
3401 * other mac80211 functions grouped here.
3402 */
dd7a2509
JB		 3403static int iwl_mac_setup_register(struct iwl_priv *priv,
3404 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3405{
3406 int ret;
3407 struct ieee80211_hw *hw = priv->hw;
d0fe478c
JB		 3408 struct iwl_rxon_context *ctx;
3409
f0b6e2e8
RC		 3410 hw->rate_control_algorithm = "iwl-agn-rs";
3411
3412 /* Tell mac80211 our characteristics */
3413 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8 3414 IEEE80211_HW_AMPDU_AGGREGATION |
2491fa42 3415 IEEE80211_HW_NEED_DTIM_PERIOD |
f0b6e2e8
RC		 3416 IEEE80211_HW_SPECTRUM_MGMT;
3417
7cb1b088 3418 if (!priv->cfg->base_params->broken_powersave)
f0b6e2e8
RC		 3419 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3420 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3421
ba37a3d0
JB		 3422 if (priv->cfg->sku & IWL_SKU_N)
3423 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3424 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3425
8d9698b3 3426 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3427 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3428
d0fe478c
JB		 3429 for_each_context(priv, ctx) {
3430 hw->wiphy->interface_modes |= ctx->interface_modes;
3431 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3432 }
f0b6e2e8 3433
f6c8f152 3434 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3435 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3436
3437 /*
3438 * For now, disable PS by default because it affects
3439 * RX performance significantly.
3440 */
5be83de5 3441 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3442
1382c71c 3443 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3444 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3445 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3446
3447 /* Default value; 4 EDCA QOS priorities */
3448 hw->queues = 4;
3449
3450 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3451
3452 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3453 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3454 &priv->bands[IEEE80211_BAND_2GHZ];
3455 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3456 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3457 &priv->bands[IEEE80211_BAND_5GHZ];
3458
3459 ret = ieee80211_register_hw(priv->hw);
3460 if (ret) {
3461 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3462 return ret;
3463 }
3464 priv->mac80211_registered = 1;
3465
3466 return 0;
3467}
3468
3469
5b9f8cd3 3470static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3471{
c79dd5b5 3472 struct iwl_priv *priv = hw->priv;
5a66926a 3473 int ret;
b481de9c 3474
e1623446 3475 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3476
3477 /* we should be verifying the device is ready to be opened */
3478 mutex_lock(&priv->mutex);
5b9f8cd3 3479 ret = __iwl_up(priv);
b481de9c 3480 mutex_unlock(&priv->mutex);
5a66926a 3481
e655b9f0 3482 if (ret)
6cd0b1cb 3483 return ret;
e655b9f0 3484
c1842d61
TW		 3485 if (iwl_is_rfkill(priv))
3486 goto out;
3487
e1623446 3488 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3489
fe9b6b72 3490 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3491 * mac80211 will not be run successfully. */
154b25ce
EG		 3492 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3493 test_bit(STATUS_READY, &priv->status),
3494 UCODE_READY_TIMEOUT);
3495 if (!ret) {
3496 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3497 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3498 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3499 return -ETIMEDOUT;
5a66926a 3500 }
fe9b6b72 3501 }
0a078ffa 3502
e932a609
JB		 3503 iwl_led_start(priv);
3504
c1842d61 3505out:
0a078ffa 3506 priv->is_open = 1;
e1623446 3507 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3508 return 0;
3509}
3510
5b9f8cd3 3511static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3512{
c79dd5b5 3513 struct iwl_priv *priv = hw->priv;
b481de9c 3514
e1623446 3515 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3516
19cc1087 3517 if (!priv->is_open)
e655b9f0 3518 return;
e655b9f0 3519
b481de9c 3520 priv->is_open = 0;
5a66926a 3521
5b9f8cd3 3522 iwl_down(priv);
5a66926a
ZY		 3523
3524 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3525
3526 /* enable interrupts again in order to receive rfkill changes */
3527 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3528 iwl_enable_interrupts(priv);
948c171c 3529
e1623446 3530 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3531}
3532
5b9f8cd3 3533static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3534{
c79dd5b5 3535 struct iwl_priv *priv = hw->priv;
b481de9c 3536
e1623446 3537 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3538
e1623446 3539 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3540 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3541
74bcdb33 3542 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3543 dev_kfree_skb_any(skb);
3544
e1623446 3545 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3546 return NETDEV_TX_OK;
b481de9c
ZY		 3547}
3548
1dda6d28 3549void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3550{
246ed355 3551 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
857485c0 3552 int ret = 0;
b481de9c 3553
76d04815
JB		 3554 lockdep_assert_held(&priv->mutex);
3555
d986bcd1 3556 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3557 return;
3558
3559 /* The following should be done only at AP bring up */
246ed355 3560 if (!iwl_is_associated_ctx(ctx)) {
b481de9c
ZY		 3561
3562 /* RXON - unassoc (to set timing command) */
246ed355
JB		 3563 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3564 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 3565
3566 /* RXON Timing */
47313e34 3567 ret = iwl_send_rxon_timing(priv, ctx);
857485c0 3568 if (ret)
8f2d3d2a 3569 IWL_WARN(priv, "RXON timing failed - "
b481de9c
ZY		 3570 "Attempting to continue.\n");
3571
f513dfff
DH		 3572 /* AP has all antennas */
3573 priv->chain_noise_data.active_chains =
3574 priv->hw_params.valid_rx_ant;
3575 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531 3576 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3577 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c 3578
246ed355 3579 ctx->staging.assoc_id = 0;
1dda6d28 3580
c213d745 3581 if (vif->bss_conf.use_short_preamble)
246ed355 3582 ctx->staging.flags |=
b481de9c
ZY		 3583 RXON_FLG_SHORT_PREAMBLE_MSK;
3584 else
246ed355 3585 ctx->staging.flags &=
b481de9c
ZY		 3586 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3587
246ed355 3588 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3589 if (vif->bss_conf.use_short_slot)
246ed355 3590 ctx->staging.flags |=
b481de9c
ZY		 3591 RXON_FLG_SHORT_SLOT_MSK;
3592 else
246ed355 3593 ctx->staging.flags &=
b481de9c 3594 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3595 }
08abc53c
JB		 3596 /* need to send beacon cmd before committing assoc RXON! */
3597 iwl_send_beacon_cmd(priv);
b481de9c 3598 /* restore RXON assoc */
246ed355
JB		 3599 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3600 iwlcore_commit_rxon(priv, ctx);
e1493deb 3601 }
5b9f8cd3 3602 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3603
3604 /* FIXME - we need to add code here to detect a totally new
3605 * configuration, reset the AP, unassoc, rxon timing, assoc,
3606 * clear sta table, add BCAST sta... */
3607}
3608
5b9f8cd3 3609static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3610 struct ieee80211_vif *vif,
3611 struct ieee80211_key_conf *keyconf,
3612 struct ieee80211_sta *sta,
3613 u32 iv32, u16 *phase1key)
ab885f8c 3614{
ab885f8c 3615
9f58671e 3616 struct iwl_priv *priv = hw->priv;
a194e324
JB		 3617 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3618
e1623446 3619 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3620
a194e324 3621 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 3622 iv32, phase1key);
ab885f8c 3623
e1623446 3624 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3625}
3626
5b9f8cd3 3627static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3628 struct ieee80211_vif *vif,
3629 struct ieee80211_sta *sta,
b481de9c
ZY		 3630 struct ieee80211_key_conf *key)
3631{
c79dd5b5 3632 struct iwl_priv *priv = hw->priv;
a194e324 3633 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
c10afb6e 3634 struct iwl_rxon_context *ctx = vif_priv->ctx;
42986796
WT		 3635 int ret;
3636 u8 sta_id;
3637 bool is_default_wep_key = false;
b481de9c 3638
e1623446 3639 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3640
90e8e424 3641 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3642 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3643 return -EOPNOTSUPP;
3644 }
b481de9c 3645
a194e324 3646 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB		 3647 if (sta_id == IWL_INVALID_STATION)
3648 return -EINVAL;
b481de9c 3649
6974e363 3650 mutex_lock(&priv->mutex);
2a421b91 3651 iwl_scan_cancel_timeout(priv, 100);
6974e363 3652
a90178fa
JB		 3653 /*
3654 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3655 * so far, we are in legacy wep mode (group key only), otherwise we are
3656 * in 1X mode.
a90178fa
JB		 3657 * In legacy wep mode, we use another host command to the uCode.
3658 */
97359d12
JB		 3659 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3660 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 3661 !sta) {
6974e363 3662 if (cmd == SET_KEY)
c10afb6e 3663 is_default_wep_key = !ctx->key_mapping_keys;
6974e363 3664 else
ccc038ab
EG		 3665 is_default_wep_key =
3666 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3667 }
052c4b9f 3668
b481de9c 3669 switch (cmd) {
deb09c43 3670 case SET_KEY:
6974e363 3671 if (is_default_wep_key)
2995bafa 3672 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 3673 else
a194e324
JB		 3674 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3675 key, sta_id);
deb09c43 3676
e1623446 3677 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3678 break;
3679 case DISABLE_KEY:
6974e363 3680 if (is_default_wep_key)
c10afb6e 3681 ret = iwl_remove_default_wep_key(priv, ctx, key);
deb09c43 3682 else
c10afb6e 3683 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
deb09c43 3684
e1623446 3685 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3686 break;
3687 default:
deb09c43 3688 ret = -EINVAL;
b481de9c
ZY		 3689 }
3690
72e15d71 3691 mutex_unlock(&priv->mutex);
e1623446 3692 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3693
deb09c43 3694 return ret;
b481de9c
ZY		 3695}
3696
5b9f8cd3 3697static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3698 struct ieee80211_vif *vif,
832f47e3
JB		 3699 enum ieee80211_ampdu_mlme_action action,
3700 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3701{
3702 struct iwl_priv *priv = hw->priv;
4620fefa 3703 int ret = -EINVAL;
d783b061 3704
e1623446 3705 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3706 sta->addr, tid);
d783b061
TW		 3707
3708 if (!(priv->cfg->sku & IWL_SKU_N))
3709 return -EACCES;
3710
4620fefa
JB		 3711 mutex_lock(&priv->mutex);
3712
d783b061
TW		 3713 switch (action) {
3714 case IEEE80211_AMPDU_RX_START:
e1623446 3715 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3716 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3717 break;
d783b061 3718 case IEEE80211_AMPDU_RX_STOP:
e1623446 3719 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3720 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3721 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3722 ret = 0;
3723 break;
d783b061 3724 case IEEE80211_AMPDU_TX_START:
e1623446 3725 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3726 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3727 if (ret == 0) {
3728 priv->_agn.agg_tids_count++;
3729 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3730 priv->_agn.agg_tids_count);
3731 }
4620fefa 3732 break;
d783b061 3733 case IEEE80211_AMPDU_TX_STOP:
e1623446 3734 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3735 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3736 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3737 priv->_agn.agg_tids_count--;
3738 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3739 priv->_agn.agg_tids_count);
3740 }
5c2207c6 3741 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 3742 ret = 0;
7cb1b088
WYG		 3743 if (priv->cfg->ht_params &&
3744 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3745 struct iwl_station_priv *sta_priv =
3746 (void *) sta->drv_priv;
3747 /*
3748 * switch off RTS/CTS if it was previously enabled
3749 */
3750
3751 sta_priv->lq_sta.lq.general_params.flags &=
3752 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3753 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3754 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
94597ab2 3755 }
4620fefa 3756 break;
f0527971 3757 case IEEE80211_AMPDU_TX_OPERATIONAL:
7cb1b088
WYG		 3758 if (priv->cfg->ht_params &&
3759 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3760 struct iwl_station_priv *sta_priv =
3761 (void *) sta->drv_priv;
3762
cfecc6b4
WYG		 3763 /*
3764 * switch to RTS/CTS if it is the prefer protection
3765 * method for HT traffic
3766 */
94597ab2
JB		 3767
3768 sta_priv->lq_sta.lq.general_params.flags |=
3769 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3770 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3771 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
cfecc6b4
WYG		 3772 }
3773 ret = 0;
d783b061
TW		 3774 break;
3775 }
4620fefa
JB		 3776 mutex_unlock(&priv->mutex);
3777
3778 return ret;
d783b061 3779}
9f58671e 3780
6ab10ff8
JB		 3781static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3782 struct ieee80211_vif *vif,
3783 enum sta_notify_cmd cmd,
3784 struct ieee80211_sta *sta)
3785{
3786 struct iwl_priv *priv = hw->priv;
3787 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3788 int sta_id;
3789
6ab10ff8 3790 switch (cmd) {
6ab10ff8
JB		 3791 case STA_NOTIFY_SLEEP:
3792 WARN_ON(!sta_priv->client);
3793 sta_priv->asleep = true;
3794 if (atomic_read(&sta_priv->pending_frames) > 0)
3795 ieee80211_sta_block_awake(hw, sta, true);
3796 break;
3797 case STA_NOTIFY_AWAKE:
3798 WARN_ON(!sta_priv->client);
49dcc819
DH		 3799 if (!sta_priv->asleep)
3800 break;
6ab10ff8 3801 sta_priv->asleep = false;
2a87c26b 3802 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3803 if (sta_id != IWL_INVALID_STATION)
3804 iwl_sta_modify_ps_wake(priv, sta_id);
3805 break;
3806 default:
3807 break;
3808 }
3809}
3810
fe6b23dd
RC		 3811static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3812 struct ieee80211_vif *vif,
3813 struct ieee80211_sta *sta)
3814{
3815 struct iwl_priv *priv = hw->priv;
3816 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 3817 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 3818 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3819 int ret;
3820 u8 sta_id;
3821
3822 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3823 sta->addr);
da5ae1cf
RC		 3824 mutex_lock(&priv->mutex);
3825 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3826 sta->addr);
3827 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3828
3829 atomic_set(&sta_priv->pending_frames, 0);
3830 if (vif->type == NL80211_IFTYPE_AP)
3831 sta_priv->client = true;
3832
a194e324 3833 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
238d781d 3834 is_ap, sta, &sta_id);
fe6b23dd
RC		 3835 if (ret) {
3836 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3837 sta->addr, ret);
3838 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3839 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3840 return ret;
3841 }
3842
fd1af15d
JB		 3843 sta_priv->common.sta_id = sta_id;
3844
fe6b23dd 3845 /* Initialize rate scaling */
91dd6c27 3846 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3847 sta->addr);
3848 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3849 mutex_unlock(&priv->mutex);
fe6b23dd 3850
fd1af15d 3851 return 0;
fe6b23dd
RC		 3852}
3853
79d07325
WYG		 3854static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3855 struct ieee80211_channel_switch *ch_switch)
3856{
3857 struct iwl_priv *priv = hw->priv;
3858 const struct iwl_channel_info *ch_info;
3859 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 3860 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 3861 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB		 3862 /*
3863 * MULTI-FIXME
3864 * When we add support for multiple interfaces, we need to
3865 * revisit this. The channel switch command in the device
3866 * only affects the BSS context, but what does that really
3867 * mean? And what if we get a CSA on the second interface?
3868 * This needs a lot of work.
3869 */
3870 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325
WYG		 3871 u16 ch;
3872 unsigned long flags = 0;
3873
3874 IWL_DEBUG_MAC80211(priv, "enter\n");
3875
3876 if (iwl_is_rfkill(priv))
3877 goto out_exit;
3878
3879 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3880 test_bit(STATUS_SCANNING, &priv->status))
3881 goto out_exit;
3882
246ed355 3883 if (!iwl_is_associated_ctx(ctx))
79d07325
WYG		 3884 goto out_exit;
3885
3886 /* channel switch in progress */
3887 if (priv->switch_rxon.switch_in_progress == true)
3888 goto out_exit;
3889
3890 mutex_lock(&priv->mutex);
3891 if (priv->cfg->ops->lib->set_channel_switch) {
3892
aa2dc6b5 3893 ch = channel->hw_value;
246ed355 3894 if (le16_to_cpu(ctx->active.channel) != ch) {
79d07325 3895 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 3896 channel->band,
79d07325
WYG		 3897 ch);
3898 if (!is_channel_valid(ch_info)) {
3899 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3900 goto out;
3901 }
3902 spin_lock_irqsave(&priv->lock, flags);
3903
3904 priv->current_ht_config.smps = conf->smps_mode;
3905
3906 /* Configure HT40 channels */
7e6a5886
JB		 3907 ctx->ht.enabled = conf_is_ht(conf);
3908 if (ctx->ht.enabled) {
79d07325 3909 if (conf_is_ht40_minus(conf)) {
7e6a5886 3910 ctx->ht.extension_chan_offset =
79d07325 3911 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
7e6a5886 3912 ctx->ht.is_40mhz = true;
79d07325 3913 } else if (conf_is_ht40_plus(conf)) {
7e6a5886 3914 ctx->ht.extension_chan_offset =
79d07325 3915 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
7e6a5886 3916 ctx->ht.is_40mhz = true;
79d07325 3917 } else {
7e6a5886 3918 ctx->ht.extension_chan_offset =
79d07325 3919 IEEE80211_HT_PARAM_CHA_SEC_NONE;
7e6a5886 3920 ctx->ht.is_40mhz = false;
79d07325
WYG		 3921 }
3922 } else
7e6a5886 3923 ctx->ht.is_40mhz = false;
79d07325 3924
246ed355
JB		 3925 if ((le16_to_cpu(ctx->staging.channel) != ch))
3926 ctx->staging.flags = 0;
79d07325 3927
246ed355 3928 iwl_set_rxon_channel(priv, channel, ctx);
79d07325 3929 iwl_set_rxon_ht(priv, ht_conf);
246ed355 3930 iwl_set_flags_for_band(priv, ctx, channel->band,
8bd413e6 3931 ctx->vif);
79d07325
WYG		 3932 spin_unlock_irqrestore(&priv->lock, flags);
3933
3934 iwl_set_rate(priv);
3935 /*
3936 * at this point, staging_rxon has the
3937 * configuration for channel switch
3938 */
3939 if (priv->cfg->ops->lib->set_channel_switch(priv,
3940 ch_switch))
3941 priv->switch_rxon.switch_in_progress = false;
3942 }
3943 }
3944out:
3945 mutex_unlock(&priv->mutex);
3946out_exit:
3947 if (!priv->switch_rxon.switch_in_progress)
8bd413e6 3948 ieee80211_chswitch_done(ctx->vif, false);
79d07325
WYG		 3949 IWL_DEBUG_MAC80211(priv, "leave\n");
3950}
3951
8b8ab9d5
JB		 3952static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3953 unsigned int changed_flags,
3954 unsigned int *total_flags,
3955 u64 multicast)
3956{
3957 struct iwl_priv *priv = hw->priv;
3958 __le32 filter_or = 0, filter_nand = 0;
246ed355 3959 struct iwl_rxon_context *ctx;
8b8ab9d5
JB		 3960
3961#define CHK(test, flag) do { \
3962 if (*total_flags & (test)) \
3963 filter_or |= (flag); \
3964 else \
3965 filter_nand |= (flag); \
3966 } while (0)
3967
3968 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3969 changed_flags, *total_flags);
3970
3971 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3972 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3973 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3974
3975#undef CHK
3976
3977 mutex_lock(&priv->mutex);
3978
246ed355
JB		 3979 for_each_context(priv, ctx) {
3980 ctx->staging.filter_flags &= ~filter_nand;
3981 ctx->staging.filter_flags |= filter_or;
3982 iwlcore_commit_rxon(priv, ctx);
3983 }
8b8ab9d5
JB		 3984
3985 mutex_unlock(&priv->mutex);
3986
3987 /*
3988 * Receiving all multicast frames is always enabled by the
3989 * default flags setup in iwl_connection_init_rx_config()
3990 * since we currently do not support programming multicast
3991 * filters into the device.
3992 */
3993 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3994 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3995}
3996
716c74b0
WYG		 3997static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3998{
3999 struct iwl_priv *priv = hw->priv;
4000
4001 mutex_lock(&priv->mutex);
4002 IWL_DEBUG_MAC80211(priv, "enter\n");
4003
4004 /* do not support "flush" */
4005 if (!priv->cfg->ops->lib->txfifo_flush)
4006 goto done;
4007
4008 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4009 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
4010 goto done;
4011 }
4012 if (iwl_is_rfkill(priv)) {
4013 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
4014 goto done;
4015 }
4016
4017 /*
4018 * mac80211 will not push any more frames for transmit
4019 * until the flush is completed
4020 */
4021 if (drop) {
4022 IWL_DEBUG_MAC80211(priv, "send flush command\n");
4023 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
4024 IWL_ERR(priv, "flush request fail\n");
4025 goto done;
4026 }
4027 }
4028 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
4029 iwlagn_wait_tx_queue_empty(priv);
4030done:
4031 mutex_unlock(&priv->mutex);
4032 IWL_DEBUG_MAC80211(priv, "leave\n");
4033}
4034
b481de9c
ZY		 4035/*****************************************************************************
4036 *
4037 * driver setup and teardown
4038 *
4039 *****************************************************************************/
4040
4e39317d 4041static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 4042{
d21050c7 4043 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 4044
4045 init_waitqueue_head(&priv->wait_command_queue);
4046
5b9f8cd3
EG		 4047 INIT_WORK(&priv->restart, iwl_bg_restart);
4048 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 4049 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 4050 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 4051 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 4052 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 4053 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4a4a9e81
TW		 4054 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4055 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 4056
2a421b91 4057 iwl_setup_scan_deferred_work(priv);
bb8c093b 4058
4e39317d
EG		 4059 if (priv->cfg->ops->lib->setup_deferred_work)
4060 priv->cfg->ops->lib->setup_deferred_work(priv);
4061
4062 init_timer(&priv->statistics_periodic);
4063 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 4064 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 4065
a9e1cb6a
WYG		 4066 init_timer(&priv->ucode_trace);
4067 priv->ucode_trace.data = (unsigned long)priv;
4068 priv->ucode_trace.function = iwl_bg_ucode_trace;
4069
b74e31a9
WYG		 4070 if (priv->cfg->ops->lib->recover_from_tx_stall) {
4071 init_timer(&priv->monitor_recover);
4072 priv->monitor_recover.data = (unsigned long)priv;
4073 priv->monitor_recover.function =
4074 priv->cfg->ops->lib->recover_from_tx_stall;
4075 }
4076
7cb1b088 4077 if (!priv->cfg->base_params->use_isr_legacy)
ef850d7c
MA		 4078 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4079 iwl_irq_tasklet, (unsigned long)priv);
4080 else
4081 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4082 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 4083}
4084
4e39317d 4085static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 4086{
4e39317d
EG		 4087 if (priv->cfg->ops->lib->cancel_deferred_work)
4088 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 4089
3ae6a054 4090 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 4091 cancel_delayed_work(&priv->alive_start);
815e629b 4092 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 4093 cancel_work_sync(&priv->beacon_update);
e7e16b90
SG		 4094
4095 iwl_cancel_scan_deferred_work(priv);
4096
bee008b7 4097 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 4098 cancel_work_sync(&priv->bt_runtime_config);
e7e16b90 4099
4e39317d 4100 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 4101 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 4102}
4103
89f186a8
RC		 4104static void iwl_init_hw_rates(struct iwl_priv *priv,
4105 struct ieee80211_rate *rates)
4106{
4107 int i;
4108
4109 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4110 rates[i].bitrate = iwl_rates[i].ieee * 5;
4111 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4112 rates[i].hw_value_short = i;
4113 rates[i].flags = 0;
4114 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4115 /*
4116 * If CCK != 1M then set short preamble rate flag.
4117 */
4118 rates[i].flags |=
4119 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4120 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4121 }
4122 }
4123}
4124
4125static int iwl_init_drv(struct iwl_priv *priv)
4126{
4127 int ret;
4128
4129 priv->ibss_beacon = NULL;
4130
89f186a8
RC		 4131 spin_lock_init(&priv->sta_lock);
4132 spin_lock_init(&priv->hcmd_lock);
4133
4134 INIT_LIST_HEAD(&priv->free_frames);
4135
4136 mutex_init(&priv->mutex);
d2dfe6df 4137 mutex_init(&priv->sync_cmd_mutex);
89f186a8 4138
89f186a8
RC		 4139 priv->ieee_channels = NULL;
4140 priv->ieee_rates = NULL;
4141 priv->band = IEEE80211_BAND_2GHZ;
4142
4143 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 4144 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 4145 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 4146 priv->_agn.agg_tids_count = 0;
89f186a8 4147
8a472da4
WYG		 4148 /* initialize force reset */
4149 priv->force_reset[IWL_RF_RESET].reset_duration =
4150 IWL_DELAY_NEXT_FORCE_RF_RESET;
4151 priv->force_reset[IWL_FW_RESET].reset_duration =
4152 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 4153
4154 /* Choose which receivers/antennas to use */
4155 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355
JB		 4156 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4157 &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC		 4158
4159 iwl_init_scan_params(priv);
4160
22bf59a0 4161 /* init bt coex */
7cb1b088
WYG		 4162 if (priv->cfg->bt_params &&
4163 priv->cfg->bt_params->advanced_bt_coexist) {
b6e116e8
WYG		 4164 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4165 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4166 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 4167 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4168 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4169 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4170 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4171 }
4172
89f186a8
RC		 4173 /* Set the tx_power_user_lmt to the lowest power level
4174 * this value will get overwritten by channel max power avg
4175 * from eeprom */
b744cb79 4176 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 4177
4178 ret = iwl_init_channel_map(priv);
4179 if (ret) {
4180 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4181 goto err;
4182 }
4183
4184 ret = iwlcore_init_geos(priv);
4185 if (ret) {
4186 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4187 goto err_free_channel_map;
4188 }
4189 iwl_init_hw_rates(priv, priv->ieee_rates);
4190
4191 return 0;
4192
4193err_free_channel_map:
4194 iwl_free_channel_map(priv);
4195err:
4196 return ret;
4197}
4198
4199static void iwl_uninit_drv(struct iwl_priv *priv)
4200{
4201 iwl_calib_free_results(priv);
4202 iwlcore_free_geos(priv);
4203 iwl_free_channel_map(priv);
811ecc99 4204 kfree(priv->scan_cmd);
89f186a8
RC		 4205}
4206
5b9f8cd3
EG		 4207static struct ieee80211_ops iwl_hw_ops = {
4208 .tx = iwl_mac_tx,
4209 .start = iwl_mac_start,
4210 .stop = iwl_mac_stop,
4211 .add_interface = iwl_mac_add_interface,
4212 .remove_interface = iwl_mac_remove_interface,
4213 .config = iwl_mac_config,
8b8ab9d5 4214 .configure_filter = iwlagn_configure_filter,
5b9f8cd3
EG		 4215 .set_key = iwl_mac_set_key,
4216 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 4217 .conf_tx = iwl_mac_conf_tx,
4218 .reset_tsf = iwl_mac_reset_tsf,
4219 .bss_info_changed = iwl_bss_info_changed,
4220 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 4221 .hw_scan = iwl_mac_hw_scan,
4222 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 4223 .sta_add = iwlagn_mac_sta_add,
4224 .sta_remove = iwl_mac_sta_remove,
79d07325 4225 .channel_switch = iwl_mac_channel_switch,
716c74b0 4226 .flush = iwl_mac_flush,
a85d7cca 4227 .tx_last_beacon = iwl_mac_tx_last_beacon,
b481de9c
ZY		 4228};
4229
3867fe04
WYG		 4230static void iwl_hw_detect(struct iwl_priv *priv)
4231{
4232 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4233 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4234 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
49ded76b 4235 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3867fe04
WYG		 4236}
4237
07d4f1ad
WYG		 4238static int iwl_set_hw_params(struct iwl_priv *priv)
4239{
4240 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4241 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4242 if (priv->cfg->mod_params->amsdu_size_8K)
4243 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4244 else
4245 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4246
4247 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4248
4249 if (priv->cfg->mod_params->disable_11n)
4250 priv->cfg->sku &= ~IWL_SKU_N;
4251
4252 /* Device-specific setup */
4253 return priv->cfg->ops->lib->set_hw_params(priv);
4254}
4255
e72f368b
JB		 4256static const u8 iwlagn_bss_ac_to_fifo[] = {
4257 IWL_TX_FIFO_VO,
4258 IWL_TX_FIFO_VI,
4259 IWL_TX_FIFO_BE,
4260 IWL_TX_FIFO_BK,
4261};
4262
4263static const u8 iwlagn_bss_ac_to_queue[] = {
4264 0, 1, 2, 3,
4265};
4266
4267static const u8 iwlagn_pan_ac_to_fifo[] = {
4268 IWL_TX_FIFO_VO_IPAN,
4269 IWL_TX_FIFO_VI_IPAN,
4270 IWL_TX_FIFO_BE_IPAN,
4271 IWL_TX_FIFO_BK_IPAN,
4272};
4273
4274static const u8 iwlagn_pan_ac_to_queue[] = {
4275 7, 6, 5, 4,
4276};
4277
5b9f8cd3 4278static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 4279{
246ed355 4280 int err = 0, i;
c79dd5b5 4281 struct iwl_priv *priv;
b481de9c 4282 struct ieee80211_hw *hw;
82b9a121 4283 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 4284 unsigned long flags;
c6fa17ed 4285 u16 pci_cmd, num_mac;
b481de9c 4286
316c30d9
AK		 4287 /************************
4288 * 1. Allocating HW data
4289 ************************/
4290
6440adb5
BC		 4291 /* Disabling hardware scan means that mac80211 will perform scans
4292 * "the hard way", rather than using device's scan. */
1ea87396 4293 if (cfg->mod_params->disable_hw_scan) {
72645eff
WYG		 4294 dev_printk(KERN_DEBUG, &(pdev->dev),
4295 "sw scan support is deprecated\n");
5b9f8cd3 4296 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 4297 }
4298
5b9f8cd3 4299 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 4300 if (!hw) {
b481de9c
ZY		 4301 err = -ENOMEM;
4302 goto out;
4303 }
1d0a082d
AK		 4304 priv = hw->priv;
4305 /* At this point both hw and priv are allocated. */
4306
246ed355
JB		 4307 /*
4308 * The default context is always valid,
4309 * more may be discovered when firmware
4310 * is loaded.
4311 */
4312 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4313
4314 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4315 priv->contexts[i].ctxid = i;
4316
763cc3bf
JB		 4317 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4318 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
8f2d3d2a
JB		 4319 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4320 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4321 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 4322 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 4323 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 4324 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
e72f368b
JB		 4325 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4326 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
d0fe478c
JB		 4327 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4328 BIT(NL80211_IFTYPE_ADHOC);
4329 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4330 BIT(NL80211_IFTYPE_STATION);
4331 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4332 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4333 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
ece9c4ee
JB		 4334
4335 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4336 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4337 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4338 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4339 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4340 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4341 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4342 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
e72f368b
JB		 4343 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4344 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4345 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
d0fe478c
JB		 4346 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4347 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4348 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4349 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4350 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
ece9c4ee
JB		 4351
4352 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
8f2d3d2a 4353
b481de9c
ZY		 4354 SET_IEEE80211_DEV(hw, &pdev->dev);
4355
e1623446 4356 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 4357 priv->cfg = cfg;
b481de9c 4358 priv->pci_dev = pdev;
40cefda9 4359 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 4360
bee008b7
WYG		 4361 /* is antenna coupling more than 35dB ? */
4362 priv->bt_ant_couple_ok =
4363 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4364 true : false;
4365
f37837c9
WYG		 4366 /* enable/disable bt channel announcement */
4367 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4368
20594eb0
WYG		 4369 if (iwl_alloc_traffic_mem(priv))
4370 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4371
316c30d9
AK		 4372 /**************************
4373 * 2. Initializing PCI bus
4374 **************************/
1a7123cd
JL		 4375 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4376 PCIE_LINK_STATE_CLKPM);
4377
316c30d9
AK		 4378 if (pci_enable_device(pdev)) {
4379 err = -ENODEV;
4380 goto out_ieee80211_free_hw;
4381 }
4382
4383 pci_set_master(pdev);
4384
093d874c 4385 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 4386 if (!err)
093d874c 4387 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 4388 if (err) {
093d874c 4389 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4390 if (!err)
093d874c 4391 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4392 /* both attempts failed: */
316c30d9 4393 if (err) {
978785a3 4394 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 4395 goto out_pci_disable_device;
cc2a8ea8 4396 }
316c30d9
AK		 4397 }
4398
4399 err = pci_request_regions(pdev, DRV_NAME);
4400 if (err)
4401 goto out_pci_disable_device;
4402
4403 pci_set_drvdata(pdev, priv);
4404
316c30d9
AK		 4405
4406 /***********************
4407 * 3. Read REV register
4408 ***********************/
4409 priv->hw_base = pci_iomap(pdev, 0, 0);
4410 if (!priv->hw_base) {
4411 err = -ENODEV;
4412 goto out_pci_release_regions;
4413 }
4414
e1623446 4415 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4416 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4417 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4418
731a29b7 4419 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4420 * we should init now
4421 */
4422 spin_lock_init(&priv->reg_lock);
731a29b7 4423 spin_lock_init(&priv->lock);
4843b5a7
RC		 4424
4425 /*
4426 * stop and reset the on-board processor just in case it is in a
4427 * strange state ... like being left stranded by a primary kernel
4428 * and this is now the kdump kernel trying to start up
4429 */
4430 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4431
b661c819 4432 iwl_hw_detect(priv);
c11362c0 4433 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4434 priv->cfg->name, priv->hw_rev);
316c30d9 4435
e7b63581
TW		 4436 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4437 * PCI Tx retries from interfering with C3 CPU state */
4438 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4439
086ed117
MA		 4440 iwl_prepare_card_hw(priv);
4441 if (!priv->hw_ready) {
4442 IWL_WARN(priv, "Failed, HW not ready\n");
4443 goto out_iounmap;
4444 }
4445
91238714
TW		 4446 /*****************
4447 * 4. Read EEPROM
4448 *****************/
316c30d9
AK		 4449 /* Read the EEPROM */
4450 err = iwl_eeprom_init(priv);
4451 if (err) {
15b1687c 4452 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4453 goto out_iounmap;
4454 }
8614f360
TW		 4455 err = iwl_eeprom_check_version(priv);
4456 if (err)
c8f16138 4457 goto out_free_eeprom;
8614f360 4458
02883017 4459 /* extract MAC Address */
c6fa17ed
WYG		 4460 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4461 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4462 priv->hw->wiphy->addresses = priv->addresses;
4463 priv->hw->wiphy->n_addresses = 1;
4464 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4465 if (num_mac > 1) {
4466 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4467 ETH_ALEN);
4468 priv->addresses[1].addr[5]++;
4469 priv->hw->wiphy->n_addresses++;
4470 }
316c30d9
AK		 4471
4472 /************************
4473 * 5. Setup HW constants
4474 ************************/
da154e30 4475 if (iwl_set_hw_params(priv)) {
15b1687c 4476 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4477 goto out_free_eeprom;
316c30d9
AK		 4478 }
4479
4480 /*******************
6ba87956 4481 * 6. Setup priv
316c30d9 4482 *******************/
b481de9c 4483
6ba87956 4484 err = iwl_init_drv(priv);
bf85ea4f 4485 if (err)
399f4900 4486 goto out_free_eeprom;
bf85ea4f 4487 /* At this point both hw and priv are initialized. */
316c30d9 4488
316c30d9 4489 /********************
09f9bf79 4490 * 7. Setup services
316c30d9 4491 ********************/
0359facc 4492 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4493 iwl_disable_interrupts(priv);
0359facc 4494 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4495
6cd0b1cb
HS		 4496 pci_enable_msi(priv->pci_dev);
4497
ef850d7c
MA		 4498 iwl_alloc_isr_ict(priv);
4499 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4500 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4501 if (err) {
4502 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4503 goto out_disable_msi;
4504 }
316c30d9 4505
4e39317d 4506 iwl_setup_deferred_work(priv);
653fa4a0 4507 iwl_setup_rx_handlers(priv);
316c30d9 4508
158bea07
JB		 4509 /*********************************************
4510 * 8. Enable interrupts and read RFKILL state
4511 *********************************************/
6ba87956 4512
6cd0b1cb
HS		 4513 /* enable interrupts if needed: hw bug w/a */
4514 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4515 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4516 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4517 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4518 }
4519
4520 iwl_enable_interrupts(priv);
4521
6cd0b1cb
HS		 4522 /* If platform's RF_KILL switch is NOT set to KILL */
4523 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4524 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4525 else
4526 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4527
a60e77e5
JB		 4528 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4529 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4530
58d0f361 4531 iwl_power_initialize(priv);
39b73fb1 4532 iwl_tt_initialize(priv);
158bea07 4533
a15707d8 4534 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4535
b08dfd04 4536 err = iwl_request_firmware(priv, true);
158bea07 4537 if (err)
7d47618a 4538 goto out_destroy_workqueue;
158bea07 4539
b481de9c
ZY		 4540 return 0;
4541
7d47618a 4542 out_destroy_workqueue:
c8f16138
RC		 4543 destroy_workqueue(priv->workqueue);
4544 priv->workqueue = NULL;
795cc0ad 4545 free_irq(priv->pci_dev->irq, priv);
ef850d7c 4546 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 4547 out_disable_msi:
4548 pci_disable_msi(priv->pci_dev);
6ba87956 4549 iwl_uninit_drv(priv);
073d3f5f
TW		 4550 out_free_eeprom:
4551 iwl_eeprom_free(priv);
b481de9c
ZY		 4552 out_iounmap:
4553 pci_iounmap(pdev, priv->hw_base);
4554 out_pci_release_regions:
316c30d9 4555 pci_set_drvdata(pdev, NULL);
623d563e 4556 pci_release_regions(pdev);
b481de9c
ZY		 4557 out_pci_disable_device:
4558 pci_disable_device(pdev);
b481de9c 4559 out_ieee80211_free_hw:
20594eb0 4560 iwl_free_traffic_mem(priv);
d7c76f4c 4561 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4562 out:
4563 return err;
4564}
4565
5b9f8cd3 4566static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4567{
c79dd5b5 4568 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4569 unsigned long flags;
b481de9c
ZY		 4570
4571 if (!priv)
4572 return;
4573
a15707d8 4574 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4575
e1623446 4576 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4577
67249625 4578 iwl_dbgfs_unregister(priv);
5b9f8cd3 4579 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4580
5b9f8cd3
EG		 4581 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4582 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4583 * we need to set STATUS_EXIT_PENDING bit.
4584 */
4585 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4586 if (priv->mac80211_registered) {
4587 ieee80211_unregister_hw(priv->hw);
4588 priv->mac80211_registered = 0;
0b124c31 4589 } else {
5b9f8cd3 4590 iwl_down(priv);
c4f55232
RR		 4591 }
4592
c166b25a
BC		 4593 /*
4594 * Make sure device is reset to low power before unloading driver.
4595 * This may be redundant with iwl_down(), but there are paths to
4596 * run iwl_down() without calling apm_ops.stop(), and there are
4597 * paths to avoid running iwl_down() at all before leaving driver.
4598 * This (inexpensive) call *makes sure* device is reset.
4599 */
14e8e4af 4600 iwl_apm_stop(priv);
c166b25a 4601
39b73fb1
WYG		 4602 iwl_tt_exit(priv);
4603
0359facc
MA		 4604 /* make sure we flush any pending irq or
4605 * tasklet for the driver
4606 */
4607 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4608 iwl_disable_interrupts(priv);
0359facc
MA		 4609 spin_unlock_irqrestore(&priv->lock, flags);
4610
4611 iwl_synchronize_irq(priv);
4612
5b9f8cd3 4613 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4614
4615 if (priv->rxq.bd)
54b81550 4616 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4617 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4618
073d3f5f 4619 iwl_eeprom_free(priv);
b481de9c 4620
b481de9c 4621
948c171c
MA		 4622 /*netif_stop_queue(dev); */
4623 flush_workqueue(priv->workqueue);
4624
5b9f8cd3 4625 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4626 * priv->workqueue... so we can't take down the workqueue
4627 * until now... */
4628 destroy_workqueue(priv->workqueue);
4629 priv->workqueue = NULL;
20594eb0 4630 iwl_free_traffic_mem(priv);
b481de9c 4631
6cd0b1cb
HS		 4632 free_irq(priv->pci_dev->irq, priv);
4633 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4634 pci_iounmap(pdev, priv->hw_base);
4635 pci_release_regions(pdev);
4636 pci_disable_device(pdev);
4637 pci_set_drvdata(pdev, NULL);
4638
6ba87956 4639 iwl_uninit_drv(priv);
b481de9c 4640
ef850d7c
MA		 4641 iwl_free_isr_ict(priv);
4642
b481de9c
ZY		 4643 if (priv->ibss_beacon)
4644 dev_kfree_skb(priv->ibss_beacon);
4645
4646 ieee80211_free_hw(priv->hw);
4647}
4648
b481de9c
ZY		 4649
4650/*****************************************************************************
4651 *
4652 * driver and module entry point
4653 *
4654 *****************************************************************************/
4655
fed9017e 4656/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4657static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4658#ifdef CONFIG_IWL4965
fed9017e
RR		 4659 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4660 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4661#endif /* CONFIG_IWL4965 */
5a6a256e 4662#ifdef CONFIG_IWL5000
ac592574
WYG		 4663/* 5100 Series WiFi */
4664 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4665 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4666 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4667 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4668 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4669 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4670 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4671 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4672 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4673 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4674 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4675 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4676 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4677 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4678 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4679 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4680 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4681 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4682 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4683 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4684 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4685 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4686 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4687 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4688
4689/* 5300 Series WiFi */
4690 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4691 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4692 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4693 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4694 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4695 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4696 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4697 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4698 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4699 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4700 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4701 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4702
4703/* 5350 Series WiFi/WiMax */
4704 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4705 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4706 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4707
4708/* 5150 Series Wifi/WiMax */
4709 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4710 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4711 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4712 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4713 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4714 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4715
4716 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4717 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4718 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4719 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4720
4721/* 6x00 Series */
5953a62e
WYG		 4722 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4723 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4724 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4725 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4726 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4727 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4728 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4729 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4730 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4731 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4732
95b13014
SZ		 4733/* 6x00 Series Gen2a */
4734 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4735 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4736 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4737 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4738 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4739 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4740 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4741 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4742 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4743 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4744 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4745 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4746 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4747 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4748
4749/* 6x00 Series Gen2b */
4750 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4751 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4752 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4753 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4754 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4755 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4756 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4757 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4758 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4759 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4760 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4761 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4762 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4763 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4764 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4765 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4766 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4767 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4768 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4769 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4770 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4771 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4772 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4773 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4774 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4775 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4776 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4777 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4778
4779/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4780 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4781 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4782 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4783 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4784 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4785 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4786
03264339
SZ		 4787/* 6x50 WiFi/WiMax Series Gen2 */
4788 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4789 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4790 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4791 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4792 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4793 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4794
77dcb6a9 4795/* 1000 Series WiFi */
4bd0914f
WYG		 4796 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4797 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4798 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4799 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4800 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4801 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4802 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4803 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4804 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4805 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4806 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4807 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
1de19ecc 4808
58a39090 4809/* 100 Series WiFi */
1de19ecc
JS		 4810 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4811 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4812 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4813 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4814 {IWL_PCI_DEVICE(0x08AE, 0x1017, iwl100_bg_cfg)},
58a39090
WYG		 4815
4816/* 130 Series WiFi */
4817 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4818 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4819 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4820 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4821 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4822 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4823
5a6a256e 4824#endif /* CONFIG_IWL5000 */
7100e924 4825
fed9017e
RR		 4826 {0}
4827};
4828MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4829
4830static struct pci_driver iwl_driver = {
b481de9c 4831 .name = DRV_NAME,
fed9017e 4832 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4833 .probe = iwl_pci_probe,
4834 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4835#ifdef CONFIG_PM
5b9f8cd3
EG		 4836 .suspend = iwl_pci_suspend,
4837 .resume = iwl_pci_resume,
b481de9c
ZY		 4838#endif
4839};
4840
5b9f8cd3 4841static int __init iwl_init(void)
b481de9c
ZY		 4842{
4843
4844 int ret;
c96c31e4
JP		 4845 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4846 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4847
e227ceac 4848 ret = iwlagn_rate_control_register();
897e1cf2 4849 if (ret) {
c96c31e4 4850 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4851 return ret;
4852 }
4853
fed9017e 4854 ret = pci_register_driver(&iwl_driver);
b481de9c 4855 if (ret) {
c96c31e4 4856 pr_err("Unable to initialize PCI module\n");
897e1cf2 4857 goto error_register;
b481de9c 4858 }
b481de9c
ZY		 4859
4860 return ret;
897e1cf2 4861
897e1cf2 4862error_register:
e227ceac 4863 iwlagn_rate_control_unregister();
897e1cf2 4864 return ret;
b481de9c
ZY		 4865}
4866
5b9f8cd3 4867static void __exit iwl_exit(void)
b481de9c 4868{
fed9017e 4869 pci_unregister_driver(&iwl_driver);
e227ceac 4870 iwlagn_rate_control_unregister();
b481de9c
ZY		 4871}
4872
5b9f8cd3
EG		 4873module_exit(iwl_exit);
4874module_init(iwl_init);
a562a9dd
RC		 4875
4876#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4877module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4878MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4879module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4880MODULE_PARM_DESC(debug, "debug output mask");
4881#endif
4882
2b068618
WYG		 4883module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4884MODULE_PARM_DESC(swcrypto50,
4885 "using crypto in software (default 0 [hardware]) (deprecated)");
4886module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4887MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4888module_param_named(queues_num50,
4889 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4890MODULE_PARM_DESC(queues_num50,
4891 "number of hw queues in 50xx series (deprecated)");
4892module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4893MODULE_PARM_DESC(queues_num, "number of hw queues.");
4894module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4895MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4896module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4897MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4898module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4899 int, S_IRUGO);
4900MODULE_PARM_DESC(amsdu_size_8K50,
4901 "enable 8K amsdu size in 50XX series (deprecated)");
4902module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4903 int, S_IRUGO);
4904MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4905module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4906MODULE_PARM_DESC(fw_restart50,
4907 "restart firmware in case of error (deprecated)");
4908module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4909MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4910module_param_named(
4911 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
72645eff
WYG		 4912MODULE_PARM_DESC(disable_hw_scan,
4913 "disable hardware scanning (default 0) (deprecated)");
dd7a2509
JB		 4914
4915module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4916 S_IRUGO);
4917MODULE_PARM_DESC(ucode_alternative,
4918 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 4919
4920module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4921MODULE_PARM_DESC(antenna_coupling,
4922 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9
WYG		 4923
4924module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4925MODULE_PARM_DESC(bt_ch_announce,
4926 "Enable BT channel announcement mode (default: enable)");
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