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CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
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37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
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44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
a3139c59
SO
48#define DRV_NAME "iwlagn"
49
6bc913bd 50#include "iwl-eeprom.h"
3e0d4cb1 51#include "iwl-dev.h"
fee1247a 52#include "iwl-core.h"
3395f6e9 53#include "iwl-io.h"
b481de9c 54#include "iwl-helpers.h"
6974e363 55#include "iwl-sta.h"
f0832f13 56#include "iwl-calib.h"
b481de9c 57
416e1438 58
b481de9c
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59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
b481de9c
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65/*
66 * module name, copyright, version, etc.
b481de9c 67 */
d783b061 68#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 69
0a6857e7 70#ifdef CONFIG_IWLWIFI_DEBUG
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71#define VD "d"
72#else
73#define VD
74#endif
75
80bc5393 76#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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77#define VS "s"
78#else
79#define VS
80#endif
81
df48c323 82#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 83
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84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
a7b75207 87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 88MODULE_LICENSE("GPL");
4fc22b21 89MODULE_ALIAS("iwl4965");
b481de9c 90
b481de9c 91/*************** STATION TABLE MANAGEMENT ****
9fbab516 92 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
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93 * the functionality provided here
94 */
95
96/**************************************************************/
97
b481de9c 98/**
5b9f8cd3 99 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 100 *
01ebd063 101 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
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102 * the active_rxon structure is updated with the new data. This
103 * function correctly transitions out of the RXON_ASSOC_MSK state if
104 * a HW tune is required based on the RXON structure changes.
105 */
e0158e61 106int iwl_commit_rxon(struct iwl_priv *priv)
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107{
108 /* cast away the const for active_rxon in this function */
c1adf9fb 109 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
110 int ret;
111 bool new_assoc =
112 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 113
fee1247a 114 if (!iwl_is_alive(priv))
43d59b32 115 return -EBUSY;
b481de9c
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116
117 /* always get timestamp with Rx frame */
118 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
119
8ccde88a 120 ret = iwl_check_rxon_cmd(priv);
43d59b32 121 if (ret) {
15b1687c 122 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
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123 return -EINVAL;
124 }
125
0924e519
WYG
126 /*
127 * receive commit_rxon request
128 * abort any previous channel switch if still in process
129 */
130 if (priv->switch_rxon.switch_in_progress &&
131 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
132 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
133 le16_to_cpu(priv->switch_rxon.channel));
134 priv->switch_rxon.switch_in_progress = false;
135 }
136
b481de9c 137 /* If we don't need to send a full RXON, we can use
5b9f8cd3 138 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 139 * and other flags for the current radio configuration. */
54559703 140 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
141 ret = iwl_send_rxon_assoc(priv);
142 if (ret) {
15b1687c 143 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 144 return ret;
b481de9c
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145 }
146
147 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 148 iwl_print_rx_config_cmd(priv);
b481de9c
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149 return 0;
150 }
151
152 /* station table will be cleared */
153 priv->assoc_station_added = 0;
154
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155 /* If we are currently associated and the new config requires
156 * an RXON_ASSOC and the new config wants the associated mask enabled,
157 * we must clear the associated from the active configuration
158 * before we apply the new config */
43d59b32 159 if (iwl_is_associated(priv) && new_assoc) {
e1623446 160 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
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161 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
162
43d59b32 163 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 164 sizeof(struct iwl_rxon_cmd),
b481de9c
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165 &priv->active_rxon);
166
167 /* If the mask clearing failed then we set
168 * active_rxon back to what it was previously */
43d59b32 169 if (ret) {
b481de9c 170 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 171 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 172 return ret;
b481de9c 173 }
b481de9c
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174 }
175
e1623446 176 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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177 "* with%s RXON_FILTER_ASSOC_MSK\n"
178 "* channel = %d\n"
e174961c 179 "* bssid = %pM\n",
43d59b32 180 (new_assoc ? "" : "out"),
b481de9c 181 le16_to_cpu(priv->staging_rxon.channel),
e174961c 182 priv->staging_rxon.bssid_addr);
b481de9c 183
90e8e424 184 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
185
186 /* Apply the new configuration
187 * RXON unassoc clears the station table in uCode, send it before
188 * we add the bcast station. If assoc bit is set, we will send RXON
189 * after having added the bcast and bssid station.
190 */
191 if (!new_assoc) {
192 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 193 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 194 if (ret) {
15b1687c 195 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
196 return ret;
197 }
198 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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199 }
200
c587de0b 201 iwl_clear_stations_table(priv);
556f8db7 202
19cc1087 203 priv->start_calib = 0;
b481de9c 204
b481de9c 205 /* Add the broadcast address so we can send broadcast frames */
9a9ca65f 206 iwl_add_bcast_station(priv);
b481de9c
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207
208 /* If we have set the ASSOC_MSK and we are in BSS mode then
209 * add the IWL_AP_ID to the station rate table */
9185159d 210 if (new_assoc) {
05c914fe 211 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
212 ret = iwl_rxon_add_station(priv,
213 priv->active_rxon.bssid_addr, 1);
214 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
215 IWL_ERR(priv,
216 "Error adding AP address for TX.\n");
9185159d
TW
217 return -EIO;
218 }
219 priv->assoc_station_added = 1;
220 if (priv->default_wep_key &&
221 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
222 IWL_ERR(priv,
223 "Could not send WEP static key.\n");
b481de9c 224 }
43d59b32 225
47eef9bd
WYG
226 /*
227 * allow CTS-to-self if possible for new association.
228 * this is relevant only for 5000 series and up,
229 * but will not damage 4965
230 */
231 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
232
43d59b32
EG
233 /* Apply the new configuration
234 * RXON assoc doesn't clear the station table in uCode,
235 */
236 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
237 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
238 if (ret) {
15b1687c 239 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
240 return ret;
241 }
242 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 243 }
a643565e 244 iwl_print_rx_config_cmd(priv);
b481de9c 245
36da7d70
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246 iwl_init_sensitivity(priv);
247
248 /* If we issue a new RXON command which required a tune then we must
249 * send a new TXPOWER command or we won't be able to Tx any frames */
250 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
251 if (ret) {
15b1687c 252 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
253 return ret;
254 }
255
b481de9c
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256 return 0;
257}
258
5b9f8cd3 259void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
260{
261
45823531
AK
262 if (priv->cfg->ops->hcmd->set_rxon_chain)
263 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 264 iwlcore_commit_rxon(priv);
5da4b55f
MA
265}
266
fcab423d 267static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
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268{
269 struct list_head *element;
270
e1623446 271 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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272 priv->frames_count);
273
274 while (!list_empty(&priv->free_frames)) {
275 element = priv->free_frames.next;
276 list_del(element);
fcab423d 277 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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278 priv->frames_count--;
279 }
280
281 if (priv->frames_count) {
39aadf8c 282 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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283 priv->frames_count);
284 priv->frames_count = 0;
285 }
286}
287
fcab423d 288static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 289{
fcab423d 290 struct iwl_frame *frame;
b481de9c
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291 struct list_head *element;
292 if (list_empty(&priv->free_frames)) {
293 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
294 if (!frame) {
15b1687c 295 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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296 return NULL;
297 }
298
299 priv->frames_count++;
300 return frame;
301 }
302
303 element = priv->free_frames.next;
304 list_del(element);
fcab423d 305 return list_entry(element, struct iwl_frame, list);
b481de9c
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306}
307
fcab423d 308static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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309{
310 memset(frame, 0, sizeof(*frame));
311 list_add(&frame->list, &priv->free_frames);
312}
313
47ff65c4 314static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 315 struct ieee80211_hdr *hdr,
73ec1cc2 316 int left)
b481de9c 317{
3109ece1 318 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
319 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
320 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
321 return 0;
322
323 if (priv->ibss_beacon->len > left)
324 return 0;
325
326 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
327
328 return priv->ibss_beacon->len;
329}
330
47ff65c4
DH
331/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
332static void iwl_set_beacon_tim(struct iwl_priv *priv,
333 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
334 u8 *beacon, u32 frame_size)
335{
336 u16 tim_idx;
337 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
338
339 /*
340 * The index is relative to frame start but we start looking at the
341 * variable-length part of the beacon.
342 */
343 tim_idx = mgmt->u.beacon.variable - beacon;
344
345 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
346 while ((tim_idx < (frame_size - 2)) &&
347 (beacon[tim_idx] != WLAN_EID_TIM))
348 tim_idx += beacon[tim_idx+1] + 2;
349
350 /* If TIM field was found, set variables */
351 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
352 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
353 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
354 } else
355 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
356}
357
5b9f8cd3 358static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 359 struct iwl_frame *frame)
4bf64efd
TW
360{
361 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH
362 u32 frame_size;
363 u32 rate_flags;
364 u32 rate;
365 /*
366 * We have to set up the TX command, the TX Beacon command, and the
367 * beacon contents.
368 */
4bf64efd 369
47ff65c4 370 /* Initialize memory */
4bf64efd
TW
371 tx_beacon_cmd = &frame->u.beacon;
372 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
373
47ff65c4 374 /* Set up TX beacon contents */
4bf64efd 375 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 376 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH
377 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
378 return 0;
4bf64efd 379
47ff65c4 380 /* Set up TX command fields */
4bf64efd 381 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH
382 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
383 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
384 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
385 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 386
47ff65c4
DH
387 /* Set up TX beacon command fields */
388 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
389 frame_size);
4bf64efd 390
47ff65c4
DH
391 /* Set up packet rate and flags */
392 rate = iwl_rate_get_lowest_plcp(priv);
393 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
394 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
395 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
396 rate_flags |= RATE_MCS_CCK_MSK;
397 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
398 rate_flags);
4bf64efd
TW
399
400 return sizeof(*tx_beacon_cmd) + frame_size;
401}
5b9f8cd3 402static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 403{
fcab423d 404 struct iwl_frame *frame;
b481de9c
ZY
405 unsigned int frame_size;
406 int rc;
b481de9c 407
fcab423d 408 frame = iwl_get_free_frame(priv);
b481de9c 409 if (!frame) {
15b1687c 410 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
411 "command.\n");
412 return -ENOMEM;
413 }
414
47ff65c4
DH
415 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
416 if (!frame_size) {
417 IWL_ERR(priv, "Error configuring the beacon command\n");
418 iwl_free_frame(priv, frame);
419 return -EINVAL;
420 }
b481de9c 421
857485c0 422 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
423 &frame->u.cmd[0]);
424
fcab423d 425 iwl_free_frame(priv, frame);
b481de9c
ZY
426
427 return rc;
428}
429
7aaa1d79
SO
430static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
431{
432 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
433
434 dma_addr_t addr = get_unaligned_le32(&tb->lo);
435 if (sizeof(dma_addr_t) > sizeof(u32))
436 addr |=
437 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
438
439 return addr;
440}
441
442static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
443{
444 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
445
446 return le16_to_cpu(tb->hi_n_len) >> 4;
447}
448
449static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
450 dma_addr_t addr, u16 len)
451{
452 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
453 u16 hi_n_len = len << 4;
454
455 put_unaligned_le32(addr, &tb->lo);
456 if (sizeof(dma_addr_t) > sizeof(u32))
457 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
458
459 tb->hi_n_len = cpu_to_le16(hi_n_len);
460
461 tfd->num_tbs = idx + 1;
462}
463
464static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
465{
466 return tfd->num_tbs & 0x1f;
467}
468
469/**
470 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
471 * @priv - driver private data
472 * @txq - tx queue
473 *
474 * Does NOT advance any TFD circular buffer read/write indexes
475 * Does NOT free the TFD itself (which is within circular buffer)
476 */
477void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
478{
59606ffa 479 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
480 struct iwl_tfd *tfd;
481 struct pci_dev *dev = priv->pci_dev;
482 int index = txq->q.read_ptr;
483 int i;
484 int num_tbs;
485
486 tfd = &tfd_tmp[index];
487
488 /* Sanity check on number of chunks */
489 num_tbs = iwl_tfd_get_num_tbs(tfd);
490
491 if (num_tbs >= IWL_NUM_OF_TBS) {
492 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
493 /* @todo issue fatal error, it is quite serious situation */
494 return;
495 }
496
497 /* Unmap tx_cmd */
498 if (num_tbs)
499 pci_unmap_single(dev,
c2acea8e
JB
500 pci_unmap_addr(&txq->meta[index], mapping),
501 pci_unmap_len(&txq->meta[index], len),
96891cee 502 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
503
504 /* Unmap chunks, if any. */
505 for (i = 1; i < num_tbs; i++) {
506 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
507 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
508
509 if (txq->txb) {
510 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
511 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
512 }
513 }
514}
515
516int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
517 struct iwl_tx_queue *txq,
518 dma_addr_t addr, u16 len,
519 u8 reset, u8 pad)
520{
521 struct iwl_queue *q;
59606ffa 522 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
523 u32 num_tbs;
524
525 q = &txq->q;
59606ffa
SO
526 tfd_tmp = (struct iwl_tfd *)txq->tfds;
527 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
528
529 if (reset)
530 memset(tfd, 0, sizeof(*tfd));
531
532 num_tbs = iwl_tfd_get_num_tbs(tfd);
533
534 /* Each TFD can point to a maximum 20 Tx buffers */
535 if (num_tbs >= IWL_NUM_OF_TBS) {
536 IWL_ERR(priv, "Error can not send more than %d chunks\n",
537 IWL_NUM_OF_TBS);
538 return -EINVAL;
539 }
540
541 BUG_ON(addr & ~DMA_BIT_MASK(36));
542 if (unlikely(addr & ~IWL_TX_DMA_MASK))
543 IWL_ERR(priv, "Unaligned address = %llx\n",
544 (unsigned long long)addr);
545
546 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
547
548 return 0;
549}
550
a8e74e27
SO
551/*
552 * Tell nic where to find circular buffer of Tx Frame Descriptors for
553 * given Tx queue, and enable the DMA channel used for that queue.
554 *
555 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
556 * channels supported in hardware.
557 */
558int iwl_hw_tx_queue_init(struct iwl_priv *priv,
559 struct iwl_tx_queue *txq)
560{
a8e74e27
SO
561 int txq_id = txq->q.id;
562
a8e74e27
SO
563 /* Circular buffer (TFD queue in DRAM) physical base address */
564 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
565 txq->q.dma_addr >> 8);
566
a8e74e27
SO
567 return 0;
568}
569
b481de9c
ZY
570/******************************************************************************
571 *
572 * Generic RX handler implementations
573 *
574 ******************************************************************************/
885ba202
TW
575static void iwl_rx_reply_alive(struct iwl_priv *priv,
576 struct iwl_rx_mem_buffer *rxb)
b481de9c 577{
2f301227 578 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 579 struct iwl_alive_resp *palive;
b481de9c
ZY
580 struct delayed_work *pwork;
581
582 palive = &pkt->u.alive_frame;
583
e1623446 584 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
585 "0x%01X 0x%01X\n",
586 palive->is_valid, palive->ver_type,
587 palive->ver_subtype);
588
589 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 590 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
591 memcpy(&priv->card_alive_init,
592 &pkt->u.alive_frame,
885ba202 593 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
594 pwork = &priv->init_alive_start;
595 } else {
e1623446 596 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 597 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 598 sizeof(struct iwl_alive_resp));
b481de9c
ZY
599 pwork = &priv->alive_start;
600 }
601
602 /* We delay the ALIVE response by 5ms to
603 * give the HW RF Kill time to activate... */
604 if (palive->is_valid == UCODE_VALID_OK)
605 queue_delayed_work(priv->workqueue, pwork,
606 msecs_to_jiffies(5));
607 else
39aadf8c 608 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
609}
610
5b9f8cd3 611static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 612{
c79dd5b5
TW
613 struct iwl_priv *priv =
614 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
615 struct sk_buff *beacon;
616
617 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 618 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
619
620 if (!beacon) {
15b1687c 621 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
622 return;
623 }
624
625 mutex_lock(&priv->mutex);
626 /* new beacon skb is allocated every time; dispose previous.*/
627 if (priv->ibss_beacon)
628 dev_kfree_skb(priv->ibss_beacon);
629
630 priv->ibss_beacon = beacon;
631 mutex_unlock(&priv->mutex);
632
5b9f8cd3 633 iwl_send_beacon_cmd(priv);
b481de9c
ZY
634}
635
4e39317d 636/**
5b9f8cd3 637 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
638 *
639 * This callback is provided in order to send a statistics request.
640 *
641 * This timer function is continually reset to execute within
642 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
643 * was received. We need to ensure we receive the statistics in order
644 * to update the temperature used for calibrating the TXPOWER.
645 */
5b9f8cd3 646static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
647{
648 struct iwl_priv *priv = (struct iwl_priv *)data;
649
650 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
651 return;
652
61780ee3
MA
653 /* dont send host command if rf-kill is on */
654 if (!iwl_is_ready_rf(priv))
655 return;
656
ef8d5529 657 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
658}
659
5b9f8cd3 660static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 661 struct iwl_rx_mem_buffer *rxb)
b481de9c 662{
0a6857e7 663#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 664 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
665 struct iwl4965_beacon_notif *beacon =
666 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 667 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 668
e1623446 669 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 670 "tsf %d %d rate %d\n",
25a6572c 671 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
672 beacon->beacon_notify_hdr.failure_frame,
673 le32_to_cpu(beacon->ibss_mgr_status),
674 le32_to_cpu(beacon->high_tsf),
675 le32_to_cpu(beacon->low_tsf), rate);
676#endif
677
05c914fe 678 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
679 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
680 queue_work(priv->workqueue, &priv->beacon_update);
681}
682
b481de9c
ZY
683/* Handle notification from uCode that card's power state is changing
684 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 685static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 686 struct iwl_rx_mem_buffer *rxb)
b481de9c 687{
2f301227 688 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
689 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
690 unsigned long status = priv->status;
691
e1623446 692 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
693 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
694 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
695
696 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
697 RF_CARD_DISABLED)) {
698
3395f6e9 699 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
700 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
701
a8b50a0a
MA
702 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
703 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
704
705 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 706 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 707 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 708 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 709 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 710 }
39b73fb1
WYG
711 if (flags & RF_CARD_DISABLED)
712 iwl_tt_enter_ct_kill(priv);
b481de9c 713 }
39b73fb1
WYG
714 if (!(flags & RF_CARD_DISABLED))
715 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
716
717 if (flags & HW_CARD_DISABLED)
718 set_bit(STATUS_RF_KILL_HW, &priv->status);
719 else
720 clear_bit(STATUS_RF_KILL_HW, &priv->status);
721
722
b481de9c 723 if (!(flags & RXON_CARD_DISABLED))
2a421b91 724 iwl_scan_cancel(priv);
b481de9c
ZY
725
726 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
727 test_bit(STATUS_RF_KILL_HW, &priv->status)))
728 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
729 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
730 else
731 wake_up_interruptible(&priv->wait_command_queue);
732}
733
5b9f8cd3 734int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 735{
e2e3c57b 736 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 737 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
738 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
739 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
740 ~APMG_PS_CTRL_MSK_PWR_SRC);
741 } else {
742 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
743 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
744 ~APMG_PS_CTRL_MSK_PWR_SRC);
745 }
746
a8b50a0a 747 return 0;
e2e3c57b
TW
748}
749
b481de9c 750/**
5b9f8cd3 751 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
752 *
753 * Setup the RX handlers for each of the reply types sent from the uCode
754 * to the host.
755 *
756 * This function chains into the hardware specific files for them to setup
757 * any hardware specific handlers as well.
758 */
653fa4a0 759static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 760{
885ba202 761 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
762 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
763 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 764 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 765 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
766 iwl_rx_pm_debug_statistics_notif;
767 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 768
9fbab516
BC
769 /*
770 * The same handler is used for both the REPLY to a discrete
771 * statistics request from the host as well as for the periodic
772 * statistics notifications (after received beacons) from the uCode.
b481de9c 773 */
ef8d5529 774 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 775 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 776
21c339bf 777 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
778 iwl_setup_rx_scan_handlers(priv);
779
37a44211 780 /* status change handler */
5b9f8cd3 781 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 782
c1354754
TW
783 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
784 iwl_rx_missed_beacon_notif;
37a44211 785 /* Rx handlers */
1781a07f
EG
786 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
787 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
788 /* block ack */
789 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 790 /* Set up hardware specific Rx handlers */
d4789efe 791 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
792}
793
b481de9c 794/**
a55360e4 795 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
796 *
797 * Uses the priv->rx_handlers callback function array to invoke
798 * the appropriate handlers, including command responses,
799 * frame-received notifications, and other notifications.
800 */
a55360e4 801void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 802{
a55360e4 803 struct iwl_rx_mem_buffer *rxb;
db11d634 804 struct iwl_rx_packet *pkt;
a55360e4 805 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
806 u32 r, i;
807 int reclaim;
808 unsigned long flags;
5c0eef96 809 u8 fill_rx = 0;
d68ab680 810 u32 count = 8;
4752c93c 811 int total_empty;
b481de9c 812
6440adb5
BC
813 /* uCode's read index (stored in shared DRAM) indicates the last Rx
814 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 815 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
816 i = rxq->read;
817
818 /* Rx interrupt, but nothing sent from uCode */
819 if (i == r)
e1623446 820 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 821
4752c93c 822 /* calculate total frames need to be restock after handling RX */
7300515d 823 total_empty = r - rxq->write_actual;
4752c93c
MA
824 if (total_empty < 0)
825 total_empty += RX_QUEUE_SIZE;
826
827 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
828 fill_rx = 1;
829
b481de9c
ZY
830 while (i != r) {
831 rxb = rxq->queue[i];
832
9fbab516 833 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
834 * then a bug has been introduced in the queue refilling
835 * routines -- catch it here */
836 BUG_ON(rxb == NULL);
837
838 rxq->queue[i] = NULL;
839
2f301227
ZY
840 pci_unmap_page(priv->pci_dev, rxb->page_dma,
841 PAGE_SIZE << priv->hw_params.rx_page_order,
842 PCI_DMA_FROMDEVICE);
843 pkt = rxb_addr(rxb);
b481de9c 844
be1a71a1
JB
845 trace_iwlwifi_dev_rx(priv, pkt,
846 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
847
b481de9c
ZY
848 /* Reclaim a command buffer only if this packet is a response
849 * to a (driver-originated) command.
850 * If the packet (e.g. Rx frame) originated from uCode,
851 * there is no command buffer to reclaim.
852 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
853 * but apparently a few don't get set; catch them here. */
854 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
855 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 856 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 857 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 858 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
859 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
860 (pkt->hdr.cmd != REPLY_TX);
861
862 /* Based on type of command response or notification,
863 * handle those that need handling via function in
5b9f8cd3 864 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 865 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 866 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 867 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 868 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 869 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
870 } else {
871 /* No handling needed */
e1623446 872 IWL_DEBUG_RX(priv,
b481de9c
ZY
873 "r %d i %d No handler needed for %s, 0x%02x\n",
874 r, i, get_cmd_string(pkt->hdr.cmd),
875 pkt->hdr.cmd);
876 }
877
29b1b268
ZY
878 /*
879 * XXX: After here, we should always check rxb->page
880 * against NULL before touching it or its virtual
881 * memory (pkt). Because some rx_handler might have
882 * already taken or freed the pages.
883 */
884
b481de9c 885 if (reclaim) {
2f301227
ZY
886 /* Invoke any callbacks, transfer the buffer to caller,
887 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 888 * as we reclaim the driver command queue */
29b1b268 889 if (rxb->page)
17b88929 890 iwl_tx_cmd_complete(priv, rxb);
b481de9c 891 else
39aadf8c 892 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
893 }
894
7300515d
ZY
895 /* Reuse the page if possible. For notification packets and
896 * SKBs that fail to Rx correctly, add them back into the
897 * rx_free list for reuse later. */
898 spin_lock_irqsave(&rxq->lock, flags);
2f301227 899 if (rxb->page != NULL) {
7300515d
ZY
900 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
901 0, PAGE_SIZE << priv->hw_params.rx_page_order,
902 PCI_DMA_FROMDEVICE);
903 list_add_tail(&rxb->list, &rxq->rx_free);
904 rxq->free_count++;
905 } else
906 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 907
b481de9c 908 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 909
b481de9c 910 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
911 /* If there are a lot of unused frames,
912 * restock the Rx queue so ucode wont assert. */
913 if (fill_rx) {
914 count++;
915 if (count >= 8) {
7300515d 916 rxq->read = i;
4752c93c 917 iwl_rx_replenish_now(priv);
5c0eef96
MA
918 count = 0;
919 }
920 }
b481de9c
ZY
921 }
922
923 /* Backtrack one entry */
7300515d 924 rxq->read = i;
4752c93c
MA
925 if (fill_rx)
926 iwl_rx_replenish_now(priv);
927 else
928 iwl_rx_queue_restock(priv);
a55360e4 929}
a55360e4 930
0359facc
MA
931/* call this function to flush any scheduled tasklet */
932static inline void iwl_synchronize_irq(struct iwl_priv *priv)
933{
a96a27f9 934 /* wait to make sure we flush pending tasklet*/
0359facc
MA
935 synchronize_irq(priv->pci_dev->irq);
936 tasklet_kill(&priv->irq_tasklet);
937}
938
ef850d7c 939static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
940{
941 u32 inta, handled = 0;
942 u32 inta_fh;
943 unsigned long flags;
c2e61da2 944 u32 i;
0a6857e7 945#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
946 u32 inta_mask;
947#endif
948
949 spin_lock_irqsave(&priv->lock, flags);
950
951 /* Ack/clear/reset pending uCode interrupts.
952 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
953 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
954 inta = iwl_read32(priv, CSR_INT);
955 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
956
957 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
958 * Any new interrupts that happen after this, either while we're
959 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
960 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
961 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 962
0a6857e7 963#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 964 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 965 /* just for debug */
3395f6e9 966 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 967 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
968 inta, inta_mask, inta_fh);
969 }
970#endif
971
2f301227
ZY
972 spin_unlock_irqrestore(&priv->lock, flags);
973
b481de9c
ZY
974 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
975 * atomic, make sure that inta covers all the interrupts that
976 * we've discovered, even if FH interrupt came in just after
977 * reading CSR_INT. */
6f83eaa1 978 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 979 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 980 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
981 inta |= CSR_INT_BIT_FH_TX;
982
983 /* Now service all interrupt bits discovered above. */
984 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 985 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
986
987 /* Tell the device to stop sending interrupts */
5b9f8cd3 988 iwl_disable_interrupts(priv);
b481de9c 989
a83b9141 990 priv->isr_stats.hw++;
5b9f8cd3 991 iwl_irq_handle_error(priv);
b481de9c
ZY
992
993 handled |= CSR_INT_BIT_HW_ERR;
994
b481de9c
ZY
995 return;
996 }
997
0a6857e7 998#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 999 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1000 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1001 if (inta & CSR_INT_BIT_SCD) {
e1623446 1002 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1003 "the frame/frames.\n");
a83b9141
WYG
1004 priv->isr_stats.sch++;
1005 }
b481de9c
ZY
1006
1007 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1008 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1009 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1010 priv->isr_stats.alive++;
1011 }
b481de9c
ZY
1012 }
1013#endif
1014 /* Safely ignore these bits for debug checks below */
25c03d8e 1015 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1016
9fbab516 1017 /* HW RF KILL switch toggled */
b481de9c
ZY
1018 if (inta & CSR_INT_BIT_RF_KILL) {
1019 int hw_rf_kill = 0;
3395f6e9 1020 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1021 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1022 hw_rf_kill = 1;
1023
4c423a2b 1024 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1025 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1026
a83b9141
WYG
1027 priv->isr_stats.rfkill++;
1028
a9efa652 1029 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1030 * the driver allows loading the ucode even if the radio
1031 * is killed. Hence update the killswitch state here. The
1032 * rfkill handler will care about restarting if needed.
a9efa652 1033 */
6cd0b1cb
HS
1034 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1035 if (hw_rf_kill)
1036 set_bit(STATUS_RF_KILL_HW, &priv->status);
1037 else
1038 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1039 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1040 }
b481de9c
ZY
1041
1042 handled |= CSR_INT_BIT_RF_KILL;
1043 }
1044
9fbab516 1045 /* Chip got too hot and stopped itself */
b481de9c 1046 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1047 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1048 priv->isr_stats.ctkill++;
b481de9c
ZY
1049 handled |= CSR_INT_BIT_CT_KILL;
1050 }
1051
1052 /* Error detected by uCode */
1053 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1054 IWL_ERR(priv, "Microcode SW error detected. "
1055 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1056 priv->isr_stats.sw++;
1057 priv->isr_stats.sw_err = inta;
5b9f8cd3 1058 iwl_irq_handle_error(priv);
b481de9c
ZY
1059 handled |= CSR_INT_BIT_SW_ERR;
1060 }
1061
c2e61da2
BC
1062 /*
1063 * uCode wakes up after power-down sleep.
1064 * Tell device about any new tx or host commands enqueued,
1065 * and about any Rx buffers made available while asleep.
1066 */
b481de9c 1067 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1068 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1069 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1070 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1071 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1072 priv->isr_stats.wakeup++;
b481de9c
ZY
1073 handled |= CSR_INT_BIT_WAKEUP;
1074 }
1075
1076 /* All uCode command responses, including Tx command responses,
1077 * Rx "responses" (frame-received notification), and other
1078 * notifications from uCode come through here*/
1079 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1080 iwl_rx_handle(priv);
a83b9141 1081 priv->isr_stats.rx++;
b481de9c
ZY
1082 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1083 }
1084
c72cd19f 1085 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1086 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1087 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1088 priv->isr_stats.tx++;
b481de9c 1089 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1090 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1091 priv->ucode_write_complete = 1;
1092 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1093 }
1094
a83b9141 1095 if (inta & ~handled) {
15b1687c 1096 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1097 priv->isr_stats.unhandled++;
1098 }
b481de9c 1099
40cefda9 1100 if (inta & ~(priv->inta_mask)) {
39aadf8c 1101 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1102 inta & ~priv->inta_mask);
39aadf8c 1103 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1104 }
1105
1106 /* Re-enable all interrupts */
0359facc
MA
1107 /* only Re-enable if diabled by irq */
1108 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1109 iwl_enable_interrupts(priv);
b481de9c 1110
0a6857e7 1111#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1112 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1113 inta = iwl_read32(priv, CSR_INT);
1114 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1115 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1116 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1117 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1118 }
1119#endif
b481de9c
ZY
1120}
1121
ef850d7c
MA
1122/* tasklet for iwlagn interrupt */
1123static void iwl_irq_tasklet(struct iwl_priv *priv)
1124{
1125 u32 inta = 0;
1126 u32 handled = 0;
1127 unsigned long flags;
8756990f 1128 u32 i;
ef850d7c
MA
1129#ifdef CONFIG_IWLWIFI_DEBUG
1130 u32 inta_mask;
1131#endif
1132
1133 spin_lock_irqsave(&priv->lock, flags);
1134
1135 /* Ack/clear/reset pending uCode interrupts.
1136 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1137 */
1138 iwl_write32(priv, CSR_INT, priv->inta);
1139
1140 inta = priv->inta;
1141
1142#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1143 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1144 /* just for debug */
1145 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1146 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1147 inta, inta_mask);
1148 }
1149#endif
2f301227
ZY
1150
1151 spin_unlock_irqrestore(&priv->lock, flags);
1152
ef850d7c
MA
1153 /* saved interrupt in inta variable now we can reset priv->inta */
1154 priv->inta = 0;
1155
1156 /* Now service all interrupt bits discovered above. */
1157 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1158 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1159
1160 /* Tell the device to stop sending interrupts */
1161 iwl_disable_interrupts(priv);
1162
1163 priv->isr_stats.hw++;
1164 iwl_irq_handle_error(priv);
1165
1166 handled |= CSR_INT_BIT_HW_ERR;
1167
ef850d7c
MA
1168 return;
1169 }
1170
1171#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1172 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1173 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1174 if (inta & CSR_INT_BIT_SCD) {
1175 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1176 "the frame/frames.\n");
1177 priv->isr_stats.sch++;
1178 }
1179
1180 /* Alive notification via Rx interrupt will do the real work */
1181 if (inta & CSR_INT_BIT_ALIVE) {
1182 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1183 priv->isr_stats.alive++;
1184 }
1185 }
1186#endif
1187 /* Safely ignore these bits for debug checks below */
1188 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1189
1190 /* HW RF KILL switch toggled */
1191 if (inta & CSR_INT_BIT_RF_KILL) {
1192 int hw_rf_kill = 0;
1193 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1194 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1195 hw_rf_kill = 1;
1196
4c423a2b 1197 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1198 hw_rf_kill ? "disable radio" : "enable radio");
1199
1200 priv->isr_stats.rfkill++;
1201
1202 /* driver only loads ucode once setting the interface up.
1203 * the driver allows loading the ucode even if the radio
1204 * is killed. Hence update the killswitch state here. The
1205 * rfkill handler will care about restarting if needed.
1206 */
1207 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1208 if (hw_rf_kill)
1209 set_bit(STATUS_RF_KILL_HW, &priv->status);
1210 else
1211 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1212 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1213 }
1214
1215 handled |= CSR_INT_BIT_RF_KILL;
1216 }
1217
1218 /* Chip got too hot and stopped itself */
1219 if (inta & CSR_INT_BIT_CT_KILL) {
1220 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1221 priv->isr_stats.ctkill++;
1222 handled |= CSR_INT_BIT_CT_KILL;
1223 }
1224
1225 /* Error detected by uCode */
1226 if (inta & CSR_INT_BIT_SW_ERR) {
1227 IWL_ERR(priv, "Microcode SW error detected. "
1228 " Restarting 0x%X.\n", inta);
1229 priv->isr_stats.sw++;
1230 priv->isr_stats.sw_err = inta;
1231 iwl_irq_handle_error(priv);
1232 handled |= CSR_INT_BIT_SW_ERR;
1233 }
1234
1235 /* uCode wakes up after power-down sleep */
1236 if (inta & CSR_INT_BIT_WAKEUP) {
1237 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1238 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1239 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1240 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1241
1242 priv->isr_stats.wakeup++;
1243
1244 handled |= CSR_INT_BIT_WAKEUP;
1245 }
1246
1247 /* All uCode command responses, including Tx command responses,
1248 * Rx "responses" (frame-received notification), and other
1249 * notifications from uCode come through here*/
40cefda9
MA
1250 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1251 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1252 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1253 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1254 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1255 iwl_write32(priv, CSR_FH_INT_STATUS,
1256 CSR49_FH_INT_RX_MASK);
1257 }
1258 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1259 handled |= CSR_INT_BIT_RX_PERIODIC;
1260 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1261 }
1262 /* Sending RX interrupt require many steps to be done in the
1263 * the device:
1264 * 1- write interrupt to current index in ICT table.
1265 * 2- dma RX frame.
1266 * 3- update RX shared data to indicate last write index.
1267 * 4- send interrupt.
1268 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC
1269 * but the shared data changes does not reflect this;
1270 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1271 */
74ba67ed
BC
1272
1273 /* Disable periodic interrupt; we use it as just a one-shot. */
1274 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1275 CSR_INT_PERIODIC_DIS);
ef850d7c 1276 iwl_rx_handle(priv);
74ba67ed
BC
1277
1278 /*
1279 * Enable periodic interrupt in 8 msec only if we received
1280 * real RX interrupt (instead of just periodic int), to catch
1281 * any dangling Rx interrupt. If it was just the periodic
1282 * interrupt, there was no dangling Rx activity, and no need
1283 * to extend the periodic interrupt; one-shot is enough.
1284 */
40cefda9 1285 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1286 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA
1287 CSR_INT_PERIODIC_ENA);
1288
ef850d7c 1289 priv->isr_stats.rx++;
ef850d7c
MA
1290 }
1291
c72cd19f 1292 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1293 if (inta & CSR_INT_BIT_FH_TX) {
1294 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1295 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1296 priv->isr_stats.tx++;
1297 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1298 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1299 priv->ucode_write_complete = 1;
1300 wake_up_interruptible(&priv->wait_command_queue);
1301 }
1302
1303 if (inta & ~handled) {
1304 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1305 priv->isr_stats.unhandled++;
1306 }
1307
40cefda9 1308 if (inta & ~(priv->inta_mask)) {
ef850d7c 1309 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1310 inta & ~priv->inta_mask);
ef850d7c
MA
1311 }
1312
ef850d7c
MA
1313 /* Re-enable all interrupts */
1314 /* only Re-enable if diabled by irq */
1315 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1316 iwl_enable_interrupts(priv);
ef850d7c
MA
1317}
1318
a83b9141 1319
b481de9c
ZY
1320/******************************************************************************
1321 *
1322 * uCode download functions
1323 *
1324 ******************************************************************************/
1325
5b9f8cd3 1326static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1327{
98c92211
TW
1328 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1329 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1330 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1331 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1332 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1333 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1334}
1335
5b9f8cd3 1336static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1337{
1338 /* Remove all resets to allow NIC to operate */
1339 iwl_write32(priv, CSR_RESET, 0);
1340}
1341
1342
b481de9c 1343/**
5b9f8cd3 1344 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1345 *
1346 * Copy into buffers for card to fetch via bus-mastering
1347 */
5b9f8cd3 1348static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1349{
cc0f555d 1350 struct iwl_ucode_header *ucode;
a0987a8d 1351 int ret = -EINVAL, index;
b481de9c 1352 const struct firmware *ucode_raw;
a0987a8d
RC
1353 const char *name_pre = priv->cfg->fw_name_pre;
1354 const unsigned int api_max = priv->cfg->ucode_api_max;
1355 const unsigned int api_min = priv->cfg->ucode_api_min;
1356 char buf[25];
b481de9c
ZY
1357 u8 *src;
1358 size_t len;
cc0f555d
JS
1359 u32 api_ver, build;
1360 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1361 u16 eeprom_ver;
b481de9c
ZY
1362
1363 /* Ask kernel firmware_class module to get the boot firmware off disk.
1364 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1365 for (index = api_max; index >= api_min; index--) {
1366 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1367 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1368 if (ret < 0) {
15b1687c 1369 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1370 buf, ret);
1371 if (ret == -ENOENT)
1372 continue;
1373 else
1374 goto error;
1375 } else {
1376 if (index < api_max)
15b1687c
WT
1377 IWL_ERR(priv, "Loaded firmware %s, "
1378 "which is deprecated. "
1379 "Please use API v%u instead.\n",
a0987a8d 1380 buf, api_max);
15b1687c 1381
e1623446 1382 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1383 buf, ucode_raw->size);
1384 break;
1385 }
b481de9c
ZY
1386 }
1387
a0987a8d
RC
1388 if (ret < 0)
1389 goto error;
b481de9c 1390
cc0f555d
JS
1391 /* Make sure that we got at least the v1 header! */
1392 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1393 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1394 ret = -EINVAL;
b481de9c
ZY
1395 goto err_release;
1396 }
1397
1398 /* Data from ucode file: header followed by uCode images */
cc0f555d 1399 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1400
c02b3acd 1401 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1402 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1403 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1404 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1405 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1406 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1407 init_data_size =
1408 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1409 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1410 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1411
a0987a8d
RC
1412 /* api_ver should match the api version forming part of the
1413 * firmware filename ... but we don't check for that and only rely
877d0310 1414 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1415
1416 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1417 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1418 "Driver supports v%u, firmware is v%u.\n",
1419 api_max, api_ver);
1420 priv->ucode_ver = 0;
1421 ret = -EINVAL;
1422 goto err_release;
1423 }
1424 if (api_ver != api_max)
978785a3 1425 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1426 "got v%u. New firmware can be obtained "
1427 "from http://www.intellinuxwireless.org.\n",
1428 api_max, api_ver);
1429
978785a3
TW
1430 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1431 IWL_UCODE_MAJOR(priv->ucode_ver),
1432 IWL_UCODE_MINOR(priv->ucode_ver),
1433 IWL_UCODE_API(priv->ucode_ver),
1434 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1435
5ebeb5a6
RC
1436 snprintf(priv->hw->wiphy->fw_version,
1437 sizeof(priv->hw->wiphy->fw_version),
1438 "%u.%u.%u.%u",
1439 IWL_UCODE_MAJOR(priv->ucode_ver),
1440 IWL_UCODE_MINOR(priv->ucode_ver),
1441 IWL_UCODE_API(priv->ucode_ver),
1442 IWL_UCODE_SERIAL(priv->ucode_ver));
1443
cc0f555d
JS
1444 if (build)
1445 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1446
abdc2d62
JS
1447 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1448 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1449 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1450 ? "OTP" : "EEPROM", eeprom_ver);
1451
e1623446 1452 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1453 priv->ucode_ver);
e1623446 1454 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1455 inst_size);
e1623446 1456 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1457 data_size);
e1623446 1458 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1459 init_size);
e1623446 1460 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1461 init_data_size);
e1623446 1462 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1463 boot_size);
1464
1465 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1466 if (ucode_raw->size !=
1467 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1468 inst_size + data_size + init_size +
1469 init_data_size + boot_size) {
1470
cc0f555d
JS
1471 IWL_DEBUG_INFO(priv,
1472 "uCode file size %d does not match expected size\n",
1473 (int)ucode_raw->size);
90e759d1 1474 ret = -EINVAL;
b481de9c
ZY
1475 goto err_release;
1476 }
1477
1478 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1479 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1480 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1481 inst_size);
1482 ret = -EINVAL;
b481de9c
ZY
1483 goto err_release;
1484 }
1485
099b40b7 1486 if (data_size > priv->hw_params.max_data_size) {
e1623446 1487 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1488 data_size);
1489 ret = -EINVAL;
b481de9c
ZY
1490 goto err_release;
1491 }
099b40b7 1492 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1493 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1494 init_size);
90e759d1 1495 ret = -EINVAL;
b481de9c
ZY
1496 goto err_release;
1497 }
099b40b7 1498 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1499 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1500 init_data_size);
1501 ret = -EINVAL;
b481de9c
ZY
1502 goto err_release;
1503 }
099b40b7 1504 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1505 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1506 boot_size);
90e759d1 1507 ret = -EINVAL;
b481de9c
ZY
1508 goto err_release;
1509 }
1510
1511 /* Allocate ucode buffers for card's bus-master loading ... */
1512
1513 /* Runtime instructions and 2 copies of data:
1514 * 1) unmodified from disk
1515 * 2) backup cache for save/restore during power-downs */
1516 priv->ucode_code.len = inst_size;
98c92211 1517 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1518
1519 priv->ucode_data.len = data_size;
98c92211 1520 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1521
1522 priv->ucode_data_backup.len = data_size;
98c92211 1523 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1524
1f304e4e
ZY
1525 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1526 !priv->ucode_data_backup.v_addr)
1527 goto err_pci_alloc;
1528
b481de9c 1529 /* Initialization instructions and data */
90e759d1
TW
1530 if (init_size && init_data_size) {
1531 priv->ucode_init.len = init_size;
98c92211 1532 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1533
1534 priv->ucode_init_data.len = init_data_size;
98c92211 1535 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1536
1537 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1538 goto err_pci_alloc;
1539 }
b481de9c
ZY
1540
1541 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1542 if (boot_size) {
1543 priv->ucode_boot.len = boot_size;
98c92211 1544 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1545
90e759d1
TW
1546 if (!priv->ucode_boot.v_addr)
1547 goto err_pci_alloc;
1548 }
b481de9c
ZY
1549
1550 /* Copy images into buffers for card's bus-master reads ... */
1551
1552 /* Runtime instructions (first block of data in file) */
cc0f555d 1553 len = inst_size;
e1623446 1554 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1555 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1556 src += len;
1557
e1623446 1558 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1559 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1560
1561 /* Runtime data (2nd block)
5b9f8cd3 1562 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1563 len = data_size;
e1623446 1564 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1565 memcpy(priv->ucode_data.v_addr, src, len);
1566 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1567 src += len;
b481de9c
ZY
1568
1569 /* Initialization instructions (3rd block) */
1570 if (init_size) {
cc0f555d 1571 len = init_size;
e1623446 1572 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1573 len);
b481de9c 1574 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1575 src += len;
b481de9c
ZY
1576 }
1577
1578 /* Initialization data (4th block) */
1579 if (init_data_size) {
cc0f555d 1580 len = init_data_size;
e1623446 1581 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1582 len);
b481de9c 1583 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1584 src += len;
b481de9c
ZY
1585 }
1586
1587 /* Bootstrap instructions (5th block) */
cc0f555d 1588 len = boot_size;
e1623446 1589 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1590 memcpy(priv->ucode_boot.v_addr, src, len);
1591
1592 /* We have our copies now, allow OS release its copies */
1593 release_firmware(ucode_raw);
1594 return 0;
1595
1596 err_pci_alloc:
15b1687c 1597 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1598 ret = -ENOMEM;
5b9f8cd3 1599 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1600
1601 err_release:
1602 release_firmware(ucode_raw);
1603
1604 error:
90e759d1 1605 return ret;
b481de9c
ZY
1606}
1607
b7a79404
RC
1608static const char *desc_lookup_text[] = {
1609 "OK",
1610 "FAIL",
1611 "BAD_PARAM",
1612 "BAD_CHECKSUM",
1613 "NMI_INTERRUPT_WDG",
1614 "SYSASSERT",
1615 "FATAL_ERROR",
1616 "BAD_COMMAND",
1617 "HW_ERROR_TUNE_LOCK",
1618 "HW_ERROR_TEMPERATURE",
1619 "ILLEGAL_CHAN_FREQ",
1620 "VCC_NOT_STABLE",
1621 "FH_ERROR",
1622 "NMI_INTERRUPT_HOST",
1623 "NMI_INTERRUPT_ACTION_PT",
1624 "NMI_INTERRUPT_UNKNOWN",
1625 "UCODE_VERSION_MISMATCH",
1626 "HW_ERROR_ABS_LOCK",
1627 "HW_ERROR_CAL_LOCK_FAIL",
1628 "NMI_INTERRUPT_INST_ACTION_PT",
1629 "NMI_INTERRUPT_DATA_ACTION_PT",
1630 "NMI_TRM_HW_ER",
1631 "NMI_INTERRUPT_TRM",
1632 "NMI_INTERRUPT_BREAK_POINT"
1633 "DEBUG_0",
1634 "DEBUG_1",
1635 "DEBUG_2",
1636 "DEBUG_3",
1637 "UNKNOWN"
1638};
1639
1640static const char *desc_lookup(int i)
1641{
1642 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1643
1644 if (i < 0 || i > max)
1645 i = max;
1646
1647 return desc_lookup_text[i];
1648}
1649
1650#define ERROR_START_OFFSET (1 * sizeof(u32))
1651#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1652
1653void iwl_dump_nic_error_log(struct iwl_priv *priv)
1654{
1655 u32 data2, line;
1656 u32 desc, time, count, base, data1;
1657 u32 blink1, blink2, ilink1, ilink2;
1658
1659 if (priv->ucode_type == UCODE_INIT)
1660 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1661 else
1662 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1663
1664 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1665 IWL_ERR(priv,
1666 "Not valid error log pointer 0x%08X for %s uCode\n",
1667 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC
1668 return;
1669 }
1670
1671 count = iwl_read_targ_mem(priv, base);
1672
1673 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1674 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1675 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1676 priv->status, count);
1677 }
1678
1679 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1680 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1681 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1682 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1683 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1684 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1685 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1686 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1687 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1688
be1a71a1
JB
1689 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1690 blink1, blink2, ilink1, ilink2);
1691
b7a79404
RC
1692 IWL_ERR(priv, "Desc Time "
1693 "data1 data2 line\n");
1694 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1695 desc_lookup(desc), desc, time, data1, data2, line);
1696 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1697 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1698 ilink1, ilink2);
1699
1700}
1701
1702#define EVENT_START_OFFSET (4 * sizeof(u32))
1703
1704/**
1705 * iwl_print_event_log - Dump error event log to syslog
1706 *
1707 */
1708static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1709 u32 num_events, u32 mode)
1710{
1711 u32 i;
1712 u32 base; /* SRAM byte address of event log header */
1713 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1714 u32 ptr; /* SRAM byte address of log data */
1715 u32 ev, time, data; /* event log data */
e5854471 1716 unsigned long reg_flags;
b7a79404
RC
1717
1718 if (num_events == 0)
1719 return;
1720 if (priv->ucode_type == UCODE_INIT)
1721 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1722 else
1723 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1724
1725 if (mode == 0)
1726 event_size = 2 * sizeof(u32);
1727 else
1728 event_size = 3 * sizeof(u32);
1729
1730 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1731
e5854471
BC
1732 /* Make sure device is powered up for SRAM reads */
1733 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1734 iwl_grab_nic_access(priv);
1735
1736 /* Set starting address; reads will auto-increment */
1737 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1738 rmb();
1739
b7a79404
RC
1740 /* "time" is actually "data" for mode 0 (no timestamp).
1741 * place event id # at far right for easier visual parsing. */
1742 for (i = 0; i < num_events; i++) {
e5854471
BC
1743 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1744 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1745 if (mode == 0) {
1746 /* data, ev */
be1a71a1 1747 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
b7a79404
RC
1748 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1749 } else {
e5854471 1750 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1751 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1752 time, data, ev);
be1a71a1 1753 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
b7a79404
RC
1754 }
1755 }
e5854471
BC
1756
1757 /* Allow device to power down */
1758 iwl_release_nic_access(priv);
1759 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b7a79404
RC
1760}
1761
c341ddb2
WYG
1762/**
1763 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1764 */
1765static void iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1766 u32 num_wraps, u32 next_entry,
1767 u32 size, u32 mode)
1768{
1769 /*
1770 * display the newest DEFAULT_LOG_ENTRIES entries
1771 * i.e the entries just before the next ont that uCode would fill.
1772 */
1773 if (num_wraps) {
1774 if (next_entry < size) {
1775 iwl_print_event_log(priv,
1776 capacity - (size - next_entry),
1777 size - next_entry, mode);
1778 iwl_print_event_log(priv, 0,
1779 next_entry, mode);
1780 } else
1781 iwl_print_event_log(priv, next_entry - size,
1782 size, mode);
1783 } else {
1784 if (next_entry < size)
1785 iwl_print_event_log(priv, 0, next_entry, mode);
1786 else
1787 iwl_print_event_log(priv, next_entry - size,
1788 size, mode);
1789 }
1790}
1791
84c40692
BC
1792/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1793#define MAX_EVENT_LOG_SIZE (512)
1794
c341ddb2
WYG
1795#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
1796
1797void iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log)
b7a79404
RC
1798{
1799 u32 base; /* SRAM byte address of event log header */
1800 u32 capacity; /* event log capacity in # entries */
1801 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1802 u32 num_wraps; /* # times uCode wrapped to top of log */
1803 u32 next_entry; /* index of next entry to be written by uCode */
1804 u32 size; /* # entries that we'll print */
1805
1806 if (priv->ucode_type == UCODE_INIT)
1807 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1808 else
1809 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1810
1811 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1812 IWL_ERR(priv,
1813 "Invalid event log pointer 0x%08X for %s uCode\n",
1814 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC
1815 return;
1816 }
1817
1818 /* event log header */
1819 capacity = iwl_read_targ_mem(priv, base);
1820 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1821 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1822 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1823
84c40692
BC
1824 if (capacity > MAX_EVENT_LOG_SIZE) {
1825 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1826 capacity, MAX_EVENT_LOG_SIZE);
1827 capacity = MAX_EVENT_LOG_SIZE;
1828 }
1829
1830 if (next_entry > MAX_EVENT_LOG_SIZE) {
1831 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1832 next_entry, MAX_EVENT_LOG_SIZE);
1833 next_entry = MAX_EVENT_LOG_SIZE;
1834 }
1835
b7a79404
RC
1836 size = num_wraps ? capacity : next_entry;
1837
1838 /* bail out if nothing in log */
1839 if (size == 0) {
1840 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1841 return;
1842 }
1843
c341ddb2
WYG
1844#ifdef CONFIG_IWLWIFI_DEBUG
1845 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS))
1846 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1847 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1848#else
1849 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1850 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1851#endif
1852 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
1853 size);
b7a79404 1854
c341ddb2
WYG
1855#ifdef CONFIG_IWLWIFI_DEBUG
1856 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1857 /*
1858 * if uCode has wrapped back to top of log,
1859 * start at the oldest entry,
1860 * i.e the next one that uCode would fill.
1861 */
1862 if (num_wraps)
1863 iwl_print_event_log(priv, next_entry,
1864 capacity - next_entry, mode);
1865 /* (then/else) start at top of log */
1866 iwl_print_event_log(priv, 0, next_entry, mode);
1867 } else
1868 iwl_print_last_event_logs(priv, capacity, num_wraps,
1869 next_entry, size, mode);
1870#else
1871 iwl_print_last_event_logs(priv, capacity, num_wraps,
1872 next_entry, size, mode);
b7a79404 1873#endif
c341ddb2 1874}
b7a79404 1875
b481de9c 1876/**
4a4a9e81 1877 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1878 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1879 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1880 */
4a4a9e81 1881static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1882{
57aab75a 1883 int ret = 0;
b481de9c 1884
e1623446 1885 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1886
1887 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1888 /* We had an error bringing up the hardware, so take it
1889 * all the way back down so we can try again */
e1623446 1890 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1891 goto restart;
1892 }
1893
1894 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1895 * This is a paranoid check, because we would not have gotten the
1896 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1897 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1898 /* Runtime instruction load was bad;
1899 * take it all the way back down so we can try again */
e1623446 1900 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1901 goto restart;
1902 }
1903
c587de0b 1904 iwl_clear_stations_table(priv);
57aab75a
TW
1905 ret = priv->cfg->ops->lib->alive_notify(priv);
1906 if (ret) {
39aadf8c
WT
1907 IWL_WARN(priv,
1908 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1909 goto restart;
1910 }
1911
5b9f8cd3 1912 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1913 set_bit(STATUS_ALIVE, &priv->status);
1914
fee1247a 1915 if (iwl_is_rfkill(priv))
b481de9c
ZY
1916 return;
1917
36d6825b 1918 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1919
1920 priv->active_rate = priv->rates_mask;
1921 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1922
2f748dec
WYG
1923 /* Configure Tx antenna selection based on H/W config */
1924 if (priv->cfg->ops->hcmd->set_tx_ant)
1925 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
1926
3109ece1 1927 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1928 struct iwl_rxon_cmd *active_rxon =
1929 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1930 /* apply any changes in staging */
1931 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1932 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1933 } else {
1934 /* Initialize our rx_config data */
5b9f8cd3 1935 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1936
1937 if (priv->cfg->ops->hcmd->set_rxon_chain)
1938 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1939
b481de9c
ZY
1940 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1941 }
1942
9fbab516 1943 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1944 iwl_send_bt_config(priv);
b481de9c 1945
4a4a9e81
TW
1946 iwl_reset_run_time_calib(priv);
1947
b481de9c 1948 /* Configure the adapter for unassociated operation */
e0158e61 1949 iwlcore_commit_rxon(priv);
b481de9c
ZY
1950
1951 /* At this point, the NIC is initialized and operational */
47f4a587 1952 iwl_rf_kill_ct_config(priv);
5a66926a 1953
e932a609 1954 iwl_leds_init(priv);
fe00b5a5 1955
e1623446 1956 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1957 set_bit(STATUS_READY, &priv->status);
5a66926a 1958 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1959
e312c24c 1960 iwl_power_update_mode(priv, true);
c46fbefa 1961
ada17513
MA
1962 /* reassociate for ADHOC mode */
1963 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1964 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1965 priv->vif);
1966 if (beacon)
1967 iwl_mac_beacon_update(priv->hw, beacon);
1968 }
1969
1970
c46fbefa 1971 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1972 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1973
b481de9c
ZY
1974 return;
1975
1976 restart:
1977 queue_work(priv->workqueue, &priv->restart);
1978}
1979
4e39317d 1980static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1981
5b9f8cd3 1982static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1983{
1984 unsigned long flags;
1985 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1986
e1623446 1987 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1988
b481de9c
ZY
1989 if (!exit_pending)
1990 set_bit(STATUS_EXIT_PENDING, &priv->status);
1991
c587de0b 1992 iwl_clear_stations_table(priv);
b481de9c
ZY
1993
1994 /* Unblock any waiting calls */
1995 wake_up_interruptible_all(&priv->wait_command_queue);
1996
b481de9c
ZY
1997 /* Wipe out the EXIT_PENDING status bit if we are not actually
1998 * exiting the module */
1999 if (!exit_pending)
2000 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2001
2002 /* stop and reset the on-board processor */
3395f6e9 2003 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2004
2005 /* tell the device to stop sending interrupts */
0359facc 2006 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2007 iwl_disable_interrupts(priv);
0359facc
MA
2008 spin_unlock_irqrestore(&priv->lock, flags);
2009 iwl_synchronize_irq(priv);
b481de9c
ZY
2010
2011 if (priv->mac80211_registered)
2012 ieee80211_stop_queues(priv->hw);
2013
5b9f8cd3 2014 /* If we have not previously called iwl_init() then
a60e77e5 2015 * clear all bits but the RF Kill bit and return */
fee1247a 2016 if (!iwl_is_init(priv)) {
b481de9c
ZY
2017 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2018 STATUS_RF_KILL_HW |
9788864e
RC
2019 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2020 STATUS_GEO_CONFIGURED |
052ec3f1
MA
2021 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2022 STATUS_EXIT_PENDING;
b481de9c
ZY
2023 goto exit;
2024 }
2025
6da3a13e 2026 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2027 * bit and continue taking the NIC down. */
b481de9c
ZY
2028 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2029 STATUS_RF_KILL_HW |
9788864e
RC
2030 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2031 STATUS_GEO_CONFIGURED |
b481de9c 2032 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
2033 STATUS_FW_ERROR |
2034 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2035 STATUS_EXIT_PENDING;
b481de9c 2036
ef850d7c
MA
2037 /* device going down, Stop using ICT table */
2038 iwl_disable_ict(priv);
b481de9c 2039
da1bc453 2040 iwl_txq_ctx_stop(priv);
b3bbacb7 2041 iwl_rxq_stop(priv);
b481de9c 2042
309e731a
BC
2043 /* Power-down device's busmaster DMA clocks */
2044 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2045 udelay(5);
2046
309e731a
BC
2047 /* Make sure (redundant) we've released our request to stay awake */
2048 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2049
4d2ccdb9
BC
2050 /* Stop the device, and put it in low power state */
2051 priv->cfg->ops->lib->apm_ops.stop(priv);
2052
b481de9c 2053 exit:
885ba202 2054 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2055
2056 if (priv->ibss_beacon)
2057 dev_kfree_skb(priv->ibss_beacon);
2058 priv->ibss_beacon = NULL;
2059
2060 /* clear out any free frames */
fcab423d 2061 iwl_clear_free_frames(priv);
b481de9c
ZY
2062}
2063
5b9f8cd3 2064static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2065{
2066 mutex_lock(&priv->mutex);
5b9f8cd3 2067 __iwl_down(priv);
b481de9c 2068 mutex_unlock(&priv->mutex);
b24d22b1 2069
4e39317d 2070 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2071}
2072
086ed117
MA
2073#define HW_READY_TIMEOUT (50)
2074
2075static int iwl_set_hw_ready(struct iwl_priv *priv)
2076{
2077 int ret = 0;
2078
2079 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2080 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2081
2082 /* See if we got it */
2083 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2084 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2085 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2086 HW_READY_TIMEOUT);
2087 if (ret != -ETIMEDOUT)
2088 priv->hw_ready = true;
2089 else
2090 priv->hw_ready = false;
2091
2092 IWL_DEBUG_INFO(priv, "hardware %s\n",
2093 (priv->hw_ready == 1) ? "ready" : "not ready");
2094 return ret;
2095}
2096
2097static int iwl_prepare_card_hw(struct iwl_priv *priv)
2098{
2099 int ret = 0;
2100
2101 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
2102
3354a0f6
MA
2103 ret = iwl_set_hw_ready(priv);
2104 if (priv->hw_ready)
2105 return ret;
2106
2107 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2108 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2109 CSR_HW_IF_CONFIG_REG_PREPARE);
2110
2111 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2112 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2113 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2114
3354a0f6 2115 /* HW should be ready by now, check again. */
086ed117
MA
2116 if (ret != -ETIMEDOUT)
2117 iwl_set_hw_ready(priv);
2118
2119 return ret;
2120}
2121
b481de9c
ZY
2122#define MAX_HW_RESTARTS 5
2123
5b9f8cd3 2124static int __iwl_up(struct iwl_priv *priv)
b481de9c 2125{
57aab75a
TW
2126 int i;
2127 int ret;
b481de9c
ZY
2128
2129 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2130 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2131 return -EIO;
2132 }
2133
e903fbd4 2134 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2135 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2136 return -EIO;
2137 }
2138
086ed117
MA
2139 iwl_prepare_card_hw(priv);
2140
2141 if (!priv->hw_ready) {
2142 IWL_WARN(priv, "Exit HW not ready\n");
2143 return -EIO;
2144 }
2145
e655b9f0 2146 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2147 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2148 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2149 else
e655b9f0 2150 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2151
c1842d61 2152 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2153 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2154
5b9f8cd3 2155 iwl_enable_interrupts(priv);
a60e77e5 2156 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2157 return 0;
b481de9c
ZY
2158 }
2159
3395f6e9 2160 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2161
1053d35f 2162 ret = iwl_hw_nic_init(priv);
57aab75a 2163 if (ret) {
15b1687c 2164 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2165 return ret;
b481de9c
ZY
2166 }
2167
2168 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2169 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2170 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2171 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2172
2173 /* clear (again), then enable host interrupts */
3395f6e9 2174 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2175 iwl_enable_interrupts(priv);
b481de9c
ZY
2176
2177 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2178 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2179 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2180
2181 /* Copy original ucode data image from disk into backup cache.
2182 * This will be used to initialize the on-board processor's
2183 * data SRAM for a clean start when the runtime program first loads. */
2184 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2185 priv->ucode_data.len);
b481de9c 2186
b481de9c
ZY
2187 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2188
c587de0b 2189 iwl_clear_stations_table(priv);
b481de9c
ZY
2190
2191 /* load bootstrap state machine,
2192 * load bootstrap program into processor's memory,
2193 * prepare to load the "initialize" uCode */
57aab75a 2194 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2195
57aab75a 2196 if (ret) {
15b1687c
WT
2197 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2198 ret);
b481de9c
ZY
2199 continue;
2200 }
2201
2202 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2203 iwl_nic_start(priv);
b481de9c 2204
e1623446 2205 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2206
2207 return 0;
2208 }
2209
2210 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2211 __iwl_down(priv);
64e72c3e 2212 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2213
2214 /* tried to restart and config the device for as long as our
2215 * patience could withstand */
15b1687c 2216 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2217 return -EIO;
2218}
2219
2220
2221/*****************************************************************************
2222 *
2223 * Workqueue callbacks
2224 *
2225 *****************************************************************************/
2226
4a4a9e81 2227static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2228{
c79dd5b5
TW
2229 struct iwl_priv *priv =
2230 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2231
2232 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2233 return;
2234
2235 mutex_lock(&priv->mutex);
f3ccc08c 2236 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2237 mutex_unlock(&priv->mutex);
2238}
2239
4a4a9e81 2240static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2241{
c79dd5b5
TW
2242 struct iwl_priv *priv =
2243 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2244
2245 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2246 return;
2247
258c44a0
MA
2248 /* enable dram interrupt */
2249 iwl_reset_ict(priv);
2250
b481de9c 2251 mutex_lock(&priv->mutex);
4a4a9e81 2252 iwl_alive_start(priv);
b481de9c
ZY
2253 mutex_unlock(&priv->mutex);
2254}
2255
16e727e8
EG
2256static void iwl_bg_run_time_calib_work(struct work_struct *work)
2257{
2258 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2259 run_time_calib_work);
2260
2261 mutex_lock(&priv->mutex);
2262
2263 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2264 test_bit(STATUS_SCANNING, &priv->status)) {
2265 mutex_unlock(&priv->mutex);
2266 return;
2267 }
2268
2269 if (priv->start_calib) {
2270 iwl_chain_noise_calibration(priv, &priv->statistics);
2271
2272 iwl_sensitivity_calibration(priv, &priv->statistics);
2273 }
2274
2275 mutex_unlock(&priv->mutex);
2276 return;
2277}
2278
5b9f8cd3 2279static void iwl_bg_up(struct work_struct *data)
b481de9c 2280{
c79dd5b5 2281 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2282
2283 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2284 return;
2285
2286 mutex_lock(&priv->mutex);
5b9f8cd3 2287 __iwl_up(priv);
b481de9c
ZY
2288 mutex_unlock(&priv->mutex);
2289}
2290
5b9f8cd3 2291static void iwl_bg_restart(struct work_struct *data)
b481de9c 2292{
c79dd5b5 2293 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2294
2295 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2296 return;
2297
19cc1087
JB
2298 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2299 mutex_lock(&priv->mutex);
2300 priv->vif = NULL;
2301 priv->is_open = 0;
2302 mutex_unlock(&priv->mutex);
2303 iwl_down(priv);
2304 ieee80211_restart_hw(priv->hw);
2305 } else {
2306 iwl_down(priv);
2307 queue_work(priv->workqueue, &priv->up);
2308 }
b481de9c
ZY
2309}
2310
5b9f8cd3 2311static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2312{
c79dd5b5
TW
2313 struct iwl_priv *priv =
2314 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2315
2316 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2317 return;
2318
2319 mutex_lock(&priv->mutex);
a55360e4 2320 iwl_rx_replenish(priv);
b481de9c
ZY
2321 mutex_unlock(&priv->mutex);
2322}
2323
7878a5a4
MA
2324#define IWL_DELAY_NEXT_SCAN (HZ*2)
2325
5bbe233b 2326void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2327{
b481de9c 2328 struct ieee80211_conf *conf = NULL;
857485c0 2329 int ret = 0;
1ff50bda 2330 unsigned long flags;
b481de9c 2331
05c914fe 2332 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2333 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2334 return;
2335 }
2336
e1623446 2337 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2338 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2339
2340
2341 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2342 return;
2343
b481de9c 2344
508e32e1 2345 if (!priv->vif || !priv->is_open)
948c171c 2346 return;
508e32e1 2347
2a421b91 2348 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2349
b481de9c
ZY
2350 conf = ieee80211_get_hw_conf(priv->hw);
2351
2352 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2353 iwlcore_commit_rxon(priv);
b481de9c 2354
3195c1f3 2355 iwl_setup_rxon_timing(priv);
857485c0 2356 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2357 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2358 if (ret)
39aadf8c 2359 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2360 "Attempting to continue.\n");
2361
2362 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2363
42eb7c64 2364 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2365
45823531
AK
2366 if (priv->cfg->ops->hcmd->set_rxon_chain)
2367 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2368
b481de9c
ZY
2369 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2370
e1623446 2371 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2372 priv->assoc_id, priv->beacon_int);
2373
2374 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2375 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2376 else
2377 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2378
2379 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2380 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2381 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2382 else
2383 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2384
05c914fe 2385 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2386 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2387
2388 }
2389
e0158e61 2390 iwlcore_commit_rxon(priv);
b481de9c
ZY
2391
2392 switch (priv->iw_mode) {
05c914fe 2393 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2394 break;
2395
05c914fe 2396 case NL80211_IFTYPE_ADHOC:
b481de9c 2397
c46fbefa
AK
2398 /* assume default assoc id */
2399 priv->assoc_id = 1;
b481de9c 2400
4f40e4d9 2401 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2402 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2403
2404 break;
2405
2406 default:
15b1687c 2407 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2408 __func__, priv->iw_mode);
b481de9c
ZY
2409 break;
2410 }
2411
05c914fe 2412 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2413 priv->assoc_station_added = 1;
2414
1ff50bda
EG
2415 spin_lock_irqsave(&priv->lock, flags);
2416 iwl_activate_qos(priv, 0);
2417 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2418
04816448
GE
2419 /* the chain noise calibration will enabled PM upon completion
2420 * If chain noise has already been run, then we need to enable
2421 * power management here */
2422 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2423 iwl_power_update_mode(priv, false);
c90a74ba
EG
2424
2425 /* Enable Rx differential gain and sensitivity calibrations */
2426 iwl_chain_noise_reset(priv);
2427 priv->start_calib = 1;
2428
508e32e1
RC
2429}
2430
b481de9c
ZY
2431/*****************************************************************************
2432 *
2433 * mac80211 entry point functions
2434 *
2435 *****************************************************************************/
2436
154b25ce 2437#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2438
f0b6e2e8
RC
2439/*
2440 * Not a mac80211 entry point function, but it fits in with all the
2441 * other mac80211 functions grouped here.
2442 */
2443static int iwl_setup_mac(struct iwl_priv *priv)
2444{
2445 int ret;
2446 struct ieee80211_hw *hw = priv->hw;
2447 hw->rate_control_algorithm = "iwl-agn-rs";
2448
2449 /* Tell mac80211 our characteristics */
2450 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2451 IEEE80211_HW_NOISE_DBM |
2452 IEEE80211_HW_AMPDU_AGGREGATION |
2453 IEEE80211_HW_SPECTRUM_MGMT;
2454
2455 if (!priv->cfg->broken_powersave)
2456 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2457 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2458
8d9698b3 2459 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2460 hw->wiphy->interface_modes =
2461 BIT(NL80211_IFTYPE_STATION) |
2462 BIT(NL80211_IFTYPE_ADHOC);
2463
5be83de5
JB
2464 hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
2465 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC
2466
2467 /*
2468 * For now, disable PS by default because it affects
2469 * RX performance significantly.
2470 */
5be83de5 2471 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8
RC
2472
2473 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2474 /* we create the 802.11 header and a zero-length SSID element */
2475 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2476
2477 /* Default value; 4 EDCA QOS priorities */
2478 hw->queues = 4;
2479
2480 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2481
2482 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2483 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2484 &priv->bands[IEEE80211_BAND_2GHZ];
2485 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2486 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2487 &priv->bands[IEEE80211_BAND_5GHZ];
2488
2489 ret = ieee80211_register_hw(priv->hw);
2490 if (ret) {
2491 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2492 return ret;
2493 }
2494 priv->mac80211_registered = 1;
2495
2496 return 0;
2497}
2498
2499
5b9f8cd3 2500static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2501{
c79dd5b5 2502 struct iwl_priv *priv = hw->priv;
5a66926a 2503 int ret;
b481de9c 2504
e1623446 2505 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2506
2507 /* we should be verifying the device is ready to be opened */
2508 mutex_lock(&priv->mutex);
2509
5a66926a
ZY
2510 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2511 * ucode filename and max sizes are card-specific. */
b481de9c 2512
5a66926a 2513 if (!priv->ucode_code.len) {
5b9f8cd3 2514 ret = iwl_read_ucode(priv);
5a66926a 2515 if (ret) {
15b1687c 2516 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2517 mutex_unlock(&priv->mutex);
6cd0b1cb 2518 return ret;
5a66926a
ZY
2519 }
2520 }
b481de9c 2521
5b9f8cd3 2522 ret = __iwl_up(priv);
5a66926a 2523
b481de9c 2524 mutex_unlock(&priv->mutex);
5a66926a 2525
e655b9f0 2526 if (ret)
6cd0b1cb 2527 return ret;
e655b9f0 2528
c1842d61
TW
2529 if (iwl_is_rfkill(priv))
2530 goto out;
2531
e1623446 2532 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2533
fe9b6b72 2534 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2535 * mac80211 will not be run successfully. */
154b25ce
EG
2536 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2537 test_bit(STATUS_READY, &priv->status),
2538 UCODE_READY_TIMEOUT);
2539 if (!ret) {
2540 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2541 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2542 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2543 return -ETIMEDOUT;
5a66926a 2544 }
fe9b6b72 2545 }
0a078ffa 2546
e932a609
JB
2547 iwl_led_start(priv);
2548
c1842d61 2549out:
0a078ffa 2550 priv->is_open = 1;
e1623446 2551 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2552 return 0;
2553}
2554
5b9f8cd3 2555static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2556{
c79dd5b5 2557 struct iwl_priv *priv = hw->priv;
b481de9c 2558
e1623446 2559 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2560
19cc1087 2561 if (!priv->is_open)
e655b9f0 2562 return;
e655b9f0 2563
b481de9c 2564 priv->is_open = 0;
5a66926a 2565
5bddf549 2566 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2567 /* stop mac, cancel any scan request and clear
2568 * RXON_FILTER_ASSOC_MSK BIT
2569 */
5a66926a 2570 mutex_lock(&priv->mutex);
2a421b91 2571 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2572 mutex_unlock(&priv->mutex);
fde3571f
MA
2573 }
2574
5b9f8cd3 2575 iwl_down(priv);
5a66926a
ZY
2576
2577 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2578
2579 /* enable interrupts again in order to receive rfkill changes */
2580 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2581 iwl_enable_interrupts(priv);
948c171c 2582
e1623446 2583 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2584}
2585
5b9f8cd3 2586static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2587{
c79dd5b5 2588 struct iwl_priv *priv = hw->priv;
b481de9c 2589
e1623446 2590 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2591
e1623446 2592 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2593 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2594
e039fa4a 2595 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2596 dev_kfree_skb_any(skb);
2597
e1623446 2598 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2599 return NETDEV_TX_OK;
b481de9c
ZY
2600}
2601
60690a6a 2602void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2603{
857485c0 2604 int ret = 0;
1ff50bda 2605 unsigned long flags;
b481de9c 2606
d986bcd1 2607 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2608 return;
2609
2610 /* The following should be done only at AP bring up */
3195c1f3 2611 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2612
2613 /* RXON - unassoc (to set timing command) */
2614 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2615 iwlcore_commit_rxon(priv);
b481de9c
ZY
2616
2617 /* RXON Timing */
3195c1f3 2618 iwl_setup_rxon_timing(priv);
857485c0 2619 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2620 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2621 if (ret)
39aadf8c 2622 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2623 "Attempting to continue.\n");
2624
f513dfff
DH
2625 /* AP has all antennas */
2626 priv->chain_noise_data.active_chains =
2627 priv->hw_params.valid_rx_ant;
2628 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK
2629 if (priv->cfg->ops->hcmd->set_rxon_chain)
2630 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2631
2632 /* FIXME: what should be the assoc_id for AP? */
2633 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2634 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2635 priv->staging_rxon.flags |=
2636 RXON_FLG_SHORT_PREAMBLE_MSK;
2637 else
2638 priv->staging_rxon.flags &=
2639 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2640
2641 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2642 if (priv->assoc_capability &
2643 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2644 priv->staging_rxon.flags |=
2645 RXON_FLG_SHORT_SLOT_MSK;
2646 else
2647 priv->staging_rxon.flags &=
2648 ~RXON_FLG_SHORT_SLOT_MSK;
2649
05c914fe 2650 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2651 priv->staging_rxon.flags &=
2652 ~RXON_FLG_SHORT_SLOT_MSK;
2653 }
2654 /* restore RXON assoc */
2655 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2656 iwlcore_commit_rxon(priv);
f513dfff 2657 iwl_reset_qos(priv);
1ff50bda
EG
2658 spin_lock_irqsave(&priv->lock, flags);
2659 iwl_activate_qos(priv, 1);
2660 spin_unlock_irqrestore(&priv->lock, flags);
9a9ca65f 2661 iwl_add_bcast_station(priv);
e1493deb 2662 }
5b9f8cd3 2663 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2664
2665 /* FIXME - we need to add code here to detect a totally new
2666 * configuration, reset the AP, unassoc, rxon timing, assoc,
2667 * clear sta table, add BCAST sta... */
2668}
2669
5b9f8cd3 2670static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2671 struct ieee80211_key_conf *keyconf, const u8 *addr,
2672 u32 iv32, u16 *phase1key)
2673{
ab885f8c 2674
9f58671e 2675 struct iwl_priv *priv = hw->priv;
e1623446 2676 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2677
9f58671e 2678 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2679
e1623446 2680 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2681}
2682
5b9f8cd3 2683static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2684 struct ieee80211_vif *vif,
2685 struct ieee80211_sta *sta,
b481de9c
ZY
2686 struct ieee80211_key_conf *key)
2687{
c79dd5b5 2688 struct iwl_priv *priv = hw->priv;
42986796
WT
2689 const u8 *addr;
2690 int ret;
2691 u8 sta_id;
2692 bool is_default_wep_key = false;
b481de9c 2693
e1623446 2694 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2695
90e8e424 2696 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2697 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2698 return -EOPNOTSUPP;
2699 }
42986796 2700 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2701 sta_id = iwl_find_station(priv, addr);
6974e363 2702 if (sta_id == IWL_INVALID_STATION) {
e1623446 2703 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2704 addr);
6974e363 2705 return -EINVAL;
b481de9c 2706
deb09c43 2707 }
b481de9c 2708
6974e363 2709 mutex_lock(&priv->mutex);
2a421b91 2710 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2711 mutex_unlock(&priv->mutex);
2712
2713 /* If we are getting WEP group key and we didn't receive any key mapping
2714 * so far, we are in legacy wep mode (group key only), otherwise we are
2715 * in 1X mode.
2716 * In legacy wep mode, we use another host command to the uCode */
5425e490 2717 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2718 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2719 if (cmd == SET_KEY)
2720 is_default_wep_key = !priv->key_mapping_key;
2721 else
ccc038ab
EG
2722 is_default_wep_key =
2723 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2724 }
052c4b9f 2725
b481de9c 2726 switch (cmd) {
deb09c43 2727 case SET_KEY:
6974e363
EG
2728 if (is_default_wep_key)
2729 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2730 else
7480513f 2731 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2732
e1623446 2733 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2734 break;
2735 case DISABLE_KEY:
6974e363
EG
2736 if (is_default_wep_key)
2737 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2738 else
3ec47732 2739 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2740
e1623446 2741 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2742 break;
2743 default:
deb09c43 2744 ret = -EINVAL;
b481de9c
ZY
2745 }
2746
e1623446 2747 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2748
deb09c43 2749 return ret;
b481de9c
ZY
2750}
2751
5b9f8cd3 2752static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2753 struct ieee80211_vif *vif,
d783b061 2754 enum ieee80211_ampdu_mlme_action action,
17741cdc 2755 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2756{
2757 struct iwl_priv *priv = hw->priv;
5c2207c6 2758 int ret;
d783b061 2759
e1623446 2760 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2761 sta->addr, tid);
d783b061
TW
2762
2763 if (!(priv->cfg->sku & IWL_SKU_N))
2764 return -EACCES;
2765
2766 switch (action) {
2767 case IEEE80211_AMPDU_RX_START:
e1623446 2768 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2769 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2770 case IEEE80211_AMPDU_RX_STOP:
e1623446 2771 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2772 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2773 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2774 return 0;
2775 else
2776 return ret;
d783b061 2777 case IEEE80211_AMPDU_TX_START:
e1623446 2778 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2779 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2780 case IEEE80211_AMPDU_TX_STOP:
e1623446 2781 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2782 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2783 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2784 return 0;
2785 else
2786 return ret;
d783b061 2787 default:
e1623446 2788 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2789 return -EINVAL;
2790 break;
2791 }
2792 return 0;
2793}
9f58671e 2794
5b9f8cd3 2795static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2796 struct ieee80211_low_level_stats *stats)
2797{
bf403db8
EK
2798 struct iwl_priv *priv = hw->priv;
2799
2800 priv = hw->priv;
e1623446
TW
2801 IWL_DEBUG_MAC80211(priv, "enter\n");
2802 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2803
2804 return 0;
2805}
2806
6ab10ff8
JB
2807static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
2808 struct ieee80211_vif *vif,
2809 enum sta_notify_cmd cmd,
2810 struct ieee80211_sta *sta)
2811{
2812 struct iwl_priv *priv = hw->priv;
2813 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2814 int sta_id;
2815
2816 /*
2817 * TODO: We really should use this callback to
2818 * actually maintain the station table in
2819 * the device.
2820 */
2821
2822 switch (cmd) {
2823 case STA_NOTIFY_ADD:
2824 atomic_set(&sta_priv->pending_frames, 0);
2825 if (vif->type == NL80211_IFTYPE_AP)
2826 sta_priv->client = true;
2827 break;
2828 case STA_NOTIFY_SLEEP:
2829 WARN_ON(!sta_priv->client);
2830 sta_priv->asleep = true;
2831 if (atomic_read(&sta_priv->pending_frames) > 0)
2832 ieee80211_sta_block_awake(hw, sta, true);
2833 break;
2834 case STA_NOTIFY_AWAKE:
2835 WARN_ON(!sta_priv->client);
2836 sta_priv->asleep = false;
2837 sta_id = iwl_find_station(priv, sta->addr);
2838 if (sta_id != IWL_INVALID_STATION)
2839 iwl_sta_modify_ps_wake(priv, sta_id);
2840 break;
2841 default:
2842 break;
2843 }
2844}
2845
b481de9c
ZY
2846/*****************************************************************************
2847 *
2848 * sysfs attributes
2849 *
2850 *****************************************************************************/
2851
0a6857e7 2852#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2853
2854/*
2855 * The following adds a new attribute to the sysfs representation
c3a739fa 2856 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2857 * used for controlling the debug level.
2858 *
2859 * See the level definitions in iwl for details.
a562a9dd 2860 *
3d816c77
RC
2861 * The debug_level being managed using sysfs below is a per device debug
2862 * level that is used instead of the global debug level if it (the per
2863 * device debug level) is set.
b481de9c 2864 */
8cf769c6
EK
2865static ssize_t show_debug_level(struct device *d,
2866 struct device_attribute *attr, char *buf)
b481de9c 2867{
3d816c77
RC
2868 struct iwl_priv *priv = dev_get_drvdata(d);
2869 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 2870}
8cf769c6
EK
2871static ssize_t store_debug_level(struct device *d,
2872 struct device_attribute *attr,
b481de9c
ZY
2873 const char *buf, size_t count)
2874{
928841b1 2875 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2876 unsigned long val;
2877 int ret;
b481de9c 2878
9257746f
TW
2879 ret = strict_strtoul(buf, 0, &val);
2880 if (ret)
978785a3 2881 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 2882 else {
3d816c77 2883 priv->debug_level = val;
20594eb0
WYG
2884 if (iwl_alloc_traffic_mem(priv))
2885 IWL_ERR(priv,
2886 "Not enough memory to generate traffic log\n");
2887 }
b481de9c
ZY
2888 return strnlen(buf, count);
2889}
2890
8cf769c6
EK
2891static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2892 show_debug_level, store_debug_level);
2893
b481de9c 2894
0a6857e7 2895#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2896
b481de9c
ZY
2897
2898static ssize_t show_temperature(struct device *d,
2899 struct device_attribute *attr, char *buf)
2900{
928841b1 2901 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2902
fee1247a 2903 if (!iwl_is_alive(priv))
b481de9c
ZY
2904 return -EAGAIN;
2905
91dbc5bd 2906 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2907}
2908
2909static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2910
b481de9c
ZY
2911static ssize_t show_tx_power(struct device *d,
2912 struct device_attribute *attr, char *buf)
2913{
928841b1 2914 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2915
2916 if (!iwl_is_ready_rf(priv))
2917 return sprintf(buf, "off\n");
2918 else
2919 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2920}
2921
2922static ssize_t store_tx_power(struct device *d,
2923 struct device_attribute *attr,
2924 const char *buf, size_t count)
2925{
928841b1 2926 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2927 unsigned long val;
2928 int ret;
b481de9c 2929
9257746f
TW
2930 ret = strict_strtoul(buf, 10, &val);
2931 if (ret)
978785a3 2932 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
2933 else {
2934 ret = iwl_set_tx_power(priv, val, false);
2935 if (ret)
2936 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2937 ret);
2938 else
2939 ret = count;
2940 }
2941 return ret;
b481de9c
ZY
2942}
2943
2944static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2945
2946static ssize_t show_flags(struct device *d,
2947 struct device_attribute *attr, char *buf)
2948{
928841b1 2949 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2950
2951 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2952}
2953
2954static ssize_t store_flags(struct device *d,
2955 struct device_attribute *attr,
2956 const char *buf, size_t count)
2957{
928841b1 2958 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2959 unsigned long val;
2960 u32 flags;
2961 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2962 if (ret)
9257746f
TW
2963 return ret;
2964 flags = (u32)val;
b481de9c
ZY
2965
2966 mutex_lock(&priv->mutex);
2967 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2968 /* Cancel any currently running scans... */
2a421b91 2969 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2970 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2971 else {
e1623446 2972 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2973 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2974 iwlcore_commit_rxon(priv);
b481de9c
ZY
2975 }
2976 }
2977 mutex_unlock(&priv->mutex);
2978
2979 return count;
2980}
2981
2982static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2983
2984static ssize_t show_filter_flags(struct device *d,
2985 struct device_attribute *attr, char *buf)
2986{
928841b1 2987 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2988
2989 return sprintf(buf, "0x%04X\n",
2990 le32_to_cpu(priv->active_rxon.filter_flags));
2991}
2992
2993static ssize_t store_filter_flags(struct device *d,
2994 struct device_attribute *attr,
2995 const char *buf, size_t count)
2996{
928841b1 2997 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2998 unsigned long val;
2999 u32 filter_flags;
3000 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 3001 if (ret)
9257746f
TW
3002 return ret;
3003 filter_flags = (u32)val;
b481de9c
ZY
3004
3005 mutex_lock(&priv->mutex);
3006 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
3007 /* Cancel any currently running scans... */
2a421b91 3008 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3009 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3010 else {
e1623446 3011 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
3012 "0x%04X\n", filter_flags);
3013 priv->staging_rxon.filter_flags =
3014 cpu_to_le32(filter_flags);
e0158e61 3015 iwlcore_commit_rxon(priv);
b481de9c
ZY
3016 }
3017 }
3018 mutex_unlock(&priv->mutex);
3019
3020 return count;
3021}
3022
3023static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3024 store_filter_flags);
3025
b481de9c
ZY
3026
3027static ssize_t show_statistics(struct device *d,
3028 struct device_attribute *attr, char *buf)
3029{
c79dd5b5 3030 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 3031 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 3032 u32 len = 0, ofs = 0;
3ac7f146 3033 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
3034 int rc = 0;
3035
fee1247a 3036 if (!iwl_is_alive(priv))
b481de9c
ZY
3037 return -EAGAIN;
3038
3039 mutex_lock(&priv->mutex);
ef8d5529 3040 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
3041 mutex_unlock(&priv->mutex);
3042
3043 if (rc) {
3044 len = sprintf(buf,
3045 "Error sending statistics request: 0x%08X\n", rc);
3046 return len;
3047 }
3048
3049 while (size && (PAGE_SIZE - len)) {
3050 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3051 PAGE_SIZE - len, 1);
3052 len = strlen(buf);
3053 if (PAGE_SIZE - len)
3054 buf[len++] = '\n';
3055
3056 ofs += 16;
3057 size -= min(size, 16U);
3058 }
3059
3060 return len;
3061}
3062
3063static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3064
01abfbb2
WYG
3065static ssize_t show_rts_ht_protection(struct device *d,
3066 struct device_attribute *attr, char *buf)
3067{
3068 struct iwl_priv *priv = dev_get_drvdata(d);
3069
3070 return sprintf(buf, "%s\n",
3071 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3072}
3073
3074static ssize_t store_rts_ht_protection(struct device *d,
3075 struct device_attribute *attr,
3076 const char *buf, size_t count)
3077{
3078 struct iwl_priv *priv = dev_get_drvdata(d);
3079 unsigned long val;
3080 int ret;
3081
3082 ret = strict_strtoul(buf, 10, &val);
3083 if (ret)
3084 IWL_INFO(priv, "Input is not in decimal form.\n");
3085 else {
3086 if (!iwl_is_associated(priv))
3087 priv->cfg->use_rts_for_ht = val ? true : false;
3088 else
3089 IWL_ERR(priv, "Sta associated with AP - "
3090 "Change protection mechanism is not allowed\n");
3091 ret = count;
3092 }
3093 return ret;
3094}
3095
3096static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3097 show_rts_ht_protection, store_rts_ht_protection);
3098
b481de9c 3099
b481de9c
ZY
3100/*****************************************************************************
3101 *
3102 * driver setup and teardown
3103 *
3104 *****************************************************************************/
3105
4e39317d 3106static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3107{
d21050c7 3108 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3109
3110 init_waitqueue_head(&priv->wait_command_queue);
3111
5b9f8cd3
EG
3112 INIT_WORK(&priv->up, iwl_bg_up);
3113 INIT_WORK(&priv->restart, iwl_bg_restart);
3114 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3115 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3116 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
3117 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3118 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3119
2a421b91 3120 iwl_setup_scan_deferred_work(priv);
bb8c093b 3121
4e39317d
EG
3122 if (priv->cfg->ops->lib->setup_deferred_work)
3123 priv->cfg->ops->lib->setup_deferred_work(priv);
3124
3125 init_timer(&priv->statistics_periodic);
3126 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3127 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3128
ef850d7c
MA
3129 if (!priv->cfg->use_isr_legacy)
3130 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3131 iwl_irq_tasklet, (unsigned long)priv);
3132 else
3133 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3134 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
3135}
3136
4e39317d 3137static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3138{
4e39317d
EG
3139 if (priv->cfg->ops->lib->cancel_deferred_work)
3140 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3141
3ae6a054 3142 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3143 cancel_delayed_work(&priv->scan_check);
3144 cancel_delayed_work(&priv->alive_start);
b481de9c 3145 cancel_work_sync(&priv->beacon_update);
4e39317d 3146 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
3147}
3148
89f186a8
RC
3149static void iwl_init_hw_rates(struct iwl_priv *priv,
3150 struct ieee80211_rate *rates)
3151{
3152 int i;
3153
3154 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3155 rates[i].bitrate = iwl_rates[i].ieee * 5;
3156 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3157 rates[i].hw_value_short = i;
3158 rates[i].flags = 0;
3159 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3160 /*
3161 * If CCK != 1M then set short preamble rate flag.
3162 */
3163 rates[i].flags |=
3164 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3165 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3166 }
3167 }
3168}
3169
3170static int iwl_init_drv(struct iwl_priv *priv)
3171{
3172 int ret;
3173
3174 priv->ibss_beacon = NULL;
3175
3176 spin_lock_init(&priv->lock);
3177 spin_lock_init(&priv->sta_lock);
3178 spin_lock_init(&priv->hcmd_lock);
3179
3180 INIT_LIST_HEAD(&priv->free_frames);
3181
3182 mutex_init(&priv->mutex);
3183
3184 /* Clear the driver's (not device's) station table */
3185 iwl_clear_stations_table(priv);
3186
3187 priv->ieee_channels = NULL;
3188 priv->ieee_rates = NULL;
3189 priv->band = IEEE80211_BAND_2GHZ;
3190
3191 priv->iw_mode = NL80211_IFTYPE_STATION;
3192
3193 /* Choose which receivers/antennas to use */
3194 if (priv->cfg->ops->hcmd->set_rxon_chain)
3195 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3196
3197 iwl_init_scan_params(priv);
3198
3199 iwl_reset_qos(priv);
3200
3201 priv->qos_data.qos_active = 0;
3202 priv->qos_data.qos_cap.val = 0;
3203
3204 priv->rates_mask = IWL_RATES_MASK;
3205 /* Set the tx_power_user_lmt to the lowest power level
3206 * this value will get overwritten by channel max power avg
3207 * from eeprom */
3208 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3209
3210 ret = iwl_init_channel_map(priv);
3211 if (ret) {
3212 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3213 goto err;
3214 }
3215
3216 ret = iwlcore_init_geos(priv);
3217 if (ret) {
3218 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3219 goto err_free_channel_map;
3220 }
3221 iwl_init_hw_rates(priv, priv->ieee_rates);
3222
3223 return 0;
3224
3225err_free_channel_map:
3226 iwl_free_channel_map(priv);
3227err:
3228 return ret;
3229}
3230
3231static void iwl_uninit_drv(struct iwl_priv *priv)
3232{
3233 iwl_calib_free_results(priv);
3234 iwlcore_free_geos(priv);
3235 iwl_free_channel_map(priv);
3236 kfree(priv->scan);
3237}
3238
5b9f8cd3 3239static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
3240 &dev_attr_flags.attr,
3241 &dev_attr_filter_flags.attr,
b481de9c 3242 &dev_attr_statistics.attr,
b481de9c 3243 &dev_attr_temperature.attr,
b481de9c 3244 &dev_attr_tx_power.attr,
01abfbb2 3245 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3246#ifdef CONFIG_IWLWIFI_DEBUG
3247 &dev_attr_debug_level.attr,
3248#endif
b481de9c
ZY
3249 NULL
3250};
3251
5b9f8cd3 3252static struct attribute_group iwl_attribute_group = {
b481de9c 3253 .name = NULL, /* put in device directory */
5b9f8cd3 3254 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3255};
3256
5b9f8cd3
EG
3257static struct ieee80211_ops iwl_hw_ops = {
3258 .tx = iwl_mac_tx,
3259 .start = iwl_mac_start,
3260 .stop = iwl_mac_stop,
3261 .add_interface = iwl_mac_add_interface,
3262 .remove_interface = iwl_mac_remove_interface,
3263 .config = iwl_mac_config,
5b9f8cd3
EG
3264 .configure_filter = iwl_configure_filter,
3265 .set_key = iwl_mac_set_key,
3266 .update_tkip_key = iwl_mac_update_tkip_key,
3267 .get_stats = iwl_mac_get_stats,
3268 .get_tx_stats = iwl_mac_get_tx_stats,
3269 .conf_tx = iwl_mac_conf_tx,
3270 .reset_tsf = iwl_mac_reset_tsf,
3271 .bss_info_changed = iwl_bss_info_changed,
3272 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB
3273 .hw_scan = iwl_mac_hw_scan,
3274 .sta_notify = iwl_mac_sta_notify,
b481de9c
ZY
3275};
3276
5b9f8cd3 3277static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3278{
3279 int err = 0;
c79dd5b5 3280 struct iwl_priv *priv;
b481de9c 3281 struct ieee80211_hw *hw;
82b9a121 3282 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3283 unsigned long flags;
6cd0b1cb 3284 u16 pci_cmd;
b481de9c 3285
316c30d9
AK
3286 /************************
3287 * 1. Allocating HW data
3288 ************************/
3289
6440adb5
BC
3290 /* Disabling hardware scan means that mac80211 will perform scans
3291 * "the hard way", rather than using device's scan. */
1ea87396 3292 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3293 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3294 dev_printk(KERN_DEBUG, &(pdev->dev),
3295 "Disabling hw_scan\n");
5b9f8cd3 3296 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3297 }
3298
5b9f8cd3 3299 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3300 if (!hw) {
b481de9c
ZY
3301 err = -ENOMEM;
3302 goto out;
3303 }
1d0a082d
AK
3304 priv = hw->priv;
3305 /* At this point both hw and priv are allocated. */
3306
b481de9c
ZY
3307 SET_IEEE80211_DEV(hw, &pdev->dev);
3308
e1623446 3309 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3310 priv->cfg = cfg;
b481de9c 3311 priv->pci_dev = pdev;
40cefda9 3312 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3313
0a6857e7 3314#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3315 atomic_set(&priv->restrict_refcnt, 0);
3316#endif
20594eb0
WYG
3317 if (iwl_alloc_traffic_mem(priv))
3318 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3319
316c30d9
AK
3320 /**************************
3321 * 2. Initializing PCI bus
3322 **************************/
3323 if (pci_enable_device(pdev)) {
3324 err = -ENODEV;
3325 goto out_ieee80211_free_hw;
3326 }
3327
3328 pci_set_master(pdev);
3329
093d874c 3330 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3331 if (!err)
093d874c 3332 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3333 if (err) {
093d874c 3334 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3335 if (!err)
093d874c 3336 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3337 /* both attempts failed: */
316c30d9 3338 if (err) {
978785a3 3339 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3340 goto out_pci_disable_device;
cc2a8ea8 3341 }
316c30d9
AK
3342 }
3343
3344 err = pci_request_regions(pdev, DRV_NAME);
3345 if (err)
3346 goto out_pci_disable_device;
3347
3348 pci_set_drvdata(pdev, priv);
3349
316c30d9
AK
3350
3351 /***********************
3352 * 3. Read REV register
3353 ***********************/
3354 priv->hw_base = pci_iomap(pdev, 0, 0);
3355 if (!priv->hw_base) {
3356 err = -ENODEV;
3357 goto out_pci_release_regions;
3358 }
3359
e1623446 3360 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3361 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3362 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3363
a8b50a0a
MA
3364 /* this spin lock will be used in apm_ops.init and EEPROM access
3365 * we should init now
3366 */
3367 spin_lock_init(&priv->reg_lock);
b661c819 3368 iwl_hw_detect(priv);
978785a3 3369 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3370 priv->cfg->name, priv->hw_rev);
316c30d9 3371
e7b63581
TW
3372 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3373 * PCI Tx retries from interfering with C3 CPU state */
3374 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3375
086ed117
MA
3376 iwl_prepare_card_hw(priv);
3377 if (!priv->hw_ready) {
3378 IWL_WARN(priv, "Failed, HW not ready\n");
3379 goto out_iounmap;
3380 }
3381
91238714
TW
3382 /*****************
3383 * 4. Read EEPROM
3384 *****************/
316c30d9
AK
3385 /* Read the EEPROM */
3386 err = iwl_eeprom_init(priv);
3387 if (err) {
15b1687c 3388 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3389 goto out_iounmap;
3390 }
8614f360
TW
3391 err = iwl_eeprom_check_version(priv);
3392 if (err)
c8f16138 3393 goto out_free_eeprom;
8614f360 3394
02883017 3395 /* extract MAC Address */
316c30d9 3396 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3397 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3398 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3399
3400 /************************
3401 * 5. Setup HW constants
3402 ************************/
da154e30 3403 if (iwl_set_hw_params(priv)) {
15b1687c 3404 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3405 goto out_free_eeprom;
316c30d9
AK
3406 }
3407
3408 /*******************
6ba87956 3409 * 6. Setup priv
316c30d9 3410 *******************/
b481de9c 3411
6ba87956 3412 err = iwl_init_drv(priv);
bf85ea4f 3413 if (err)
399f4900 3414 goto out_free_eeprom;
bf85ea4f 3415 /* At this point both hw and priv are initialized. */
316c30d9 3416
316c30d9 3417 /********************
09f9bf79 3418 * 7. Setup services
316c30d9 3419 ********************/
0359facc 3420 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3421 iwl_disable_interrupts(priv);
0359facc 3422 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3423
6cd0b1cb
HS
3424 pci_enable_msi(priv->pci_dev);
3425
ef850d7c
MA
3426 iwl_alloc_isr_ict(priv);
3427 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3428 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3429 if (err) {
3430 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3431 goto out_disable_msi;
3432 }
5b9f8cd3 3433 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3434 if (err) {
15b1687c 3435 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3436 goto out_free_irq;
316c30d9
AK
3437 }
3438
4e39317d 3439 iwl_setup_deferred_work(priv);
653fa4a0 3440 iwl_setup_rx_handlers(priv);
316c30d9 3441
6ba87956 3442 /**********************************
09f9bf79 3443 * 8. Setup and register mac80211
6ba87956
TW
3444 **********************************/
3445
6cd0b1cb
HS
3446 /* enable interrupts if needed: hw bug w/a */
3447 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3448 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3449 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3450 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3451 }
3452
3453 iwl_enable_interrupts(priv);
3454
6ba87956
TW
3455 err = iwl_setup_mac(priv);
3456 if (err)
3457 goto out_remove_sysfs;
3458
3459 err = iwl_dbgfs_register(priv, DRV_NAME);
3460 if (err)
a75fbe8d 3461 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3462
6cd0b1cb
HS
3463 /* If platform's RF_KILL switch is NOT set to KILL */
3464 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3465 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3466 else
3467 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3468
a60e77e5
JB
3469 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3470 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3471
58d0f361 3472 iwl_power_initialize(priv);
39b73fb1 3473 iwl_tt_initialize(priv);
b481de9c
ZY
3474 return 0;
3475
316c30d9 3476 out_remove_sysfs:
c8f16138
RC
3477 destroy_workqueue(priv->workqueue);
3478 priv->workqueue = NULL;
5b9f8cd3 3479 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3480 out_free_irq:
3481 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3482 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3483 out_disable_msi:
3484 pci_disable_msi(priv->pci_dev);
6ba87956 3485 iwl_uninit_drv(priv);
073d3f5f
TW
3486 out_free_eeprom:
3487 iwl_eeprom_free(priv);
b481de9c
ZY
3488 out_iounmap:
3489 pci_iounmap(pdev, priv->hw_base);
3490 out_pci_release_regions:
316c30d9 3491 pci_set_drvdata(pdev, NULL);
623d563e 3492 pci_release_regions(pdev);
b481de9c
ZY
3493 out_pci_disable_device:
3494 pci_disable_device(pdev);
b481de9c 3495 out_ieee80211_free_hw:
20594eb0 3496 iwl_free_traffic_mem(priv);
d7c76f4c 3497 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3498 out:
3499 return err;
3500}
3501
5b9f8cd3 3502static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3503{
c79dd5b5 3504 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3505 unsigned long flags;
b481de9c
ZY
3506
3507 if (!priv)
3508 return;
3509
e1623446 3510 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3511
67249625 3512 iwl_dbgfs_unregister(priv);
5b9f8cd3 3513 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3514
5b9f8cd3
EG
3515 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3516 * to be called and iwl_down since we are removing the device
0b124c31
GG
3517 * we need to set STATUS_EXIT_PENDING bit.
3518 */
3519 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3520 if (priv->mac80211_registered) {
3521 ieee80211_unregister_hw(priv->hw);
3522 priv->mac80211_registered = 0;
0b124c31 3523 } else {
5b9f8cd3 3524 iwl_down(priv);
c4f55232
RR
3525 }
3526
c166b25a
BC
3527 /*
3528 * Make sure device is reset to low power before unloading driver.
3529 * This may be redundant with iwl_down(), but there are paths to
3530 * run iwl_down() without calling apm_ops.stop(), and there are
3531 * paths to avoid running iwl_down() at all before leaving driver.
3532 * This (inexpensive) call *makes sure* device is reset.
3533 */
3534 priv->cfg->ops->lib->apm_ops.stop(priv);
3535
39b73fb1
WYG
3536 iwl_tt_exit(priv);
3537
0359facc
MA
3538 /* make sure we flush any pending irq or
3539 * tasklet for the driver
3540 */
3541 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3542 iwl_disable_interrupts(priv);
0359facc
MA
3543 spin_unlock_irqrestore(&priv->lock, flags);
3544
3545 iwl_synchronize_irq(priv);
3546
5b9f8cd3 3547 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3548
3549 if (priv->rxq.bd)
a55360e4 3550 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3551 iwl_hw_txq_ctx_free(priv);
b481de9c 3552
c587de0b 3553 iwl_clear_stations_table(priv);
073d3f5f 3554 iwl_eeprom_free(priv);
b481de9c 3555
b481de9c 3556
948c171c
MA
3557 /*netif_stop_queue(dev); */
3558 flush_workqueue(priv->workqueue);
3559
5b9f8cd3 3560 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3561 * priv->workqueue... so we can't take down the workqueue
3562 * until now... */
3563 destroy_workqueue(priv->workqueue);
3564 priv->workqueue = NULL;
20594eb0 3565 iwl_free_traffic_mem(priv);
b481de9c 3566
6cd0b1cb
HS
3567 free_irq(priv->pci_dev->irq, priv);
3568 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3569 pci_iounmap(pdev, priv->hw_base);
3570 pci_release_regions(pdev);
3571 pci_disable_device(pdev);
3572 pci_set_drvdata(pdev, NULL);
3573
6ba87956 3574 iwl_uninit_drv(priv);
b481de9c 3575
ef850d7c
MA
3576 iwl_free_isr_ict(priv);
3577
b481de9c
ZY
3578 if (priv->ibss_beacon)
3579 dev_kfree_skb(priv->ibss_beacon);
3580
3581 ieee80211_free_hw(priv->hw);
3582}
3583
b481de9c
ZY
3584
3585/*****************************************************************************
3586 *
3587 * driver and module entry point
3588 *
3589 *****************************************************************************/
3590
fed9017e
RR
3591/* Hardware specific file defines the PCI IDs table for that hardware module */
3592static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3593#ifdef CONFIG_IWL4965
fed9017e
RR
3594 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3595 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3596#endif /* CONFIG_IWL4965 */
5a6a256e 3597#ifdef CONFIG_IWL5000
ac592574
WYG
3598/* 5100 Series WiFi */
3599 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3600 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3601 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3602 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3603 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3604 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3605 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3606 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3607 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3608 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3609 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3610 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3611 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3612 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3613 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3614 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3615 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3616 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3617 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3618 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3619 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3620 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3621 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3622 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3623
3624/* 5300 Series WiFi */
3625 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3626 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3627 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3628 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3629 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3630 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3631 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3632 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3633 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3634 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3635 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3636 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3637
3638/* 5350 Series WiFi/WiMax */
3639 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3640 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3641 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3642
3643/* 5150 Series Wifi/WiMax */
3644 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3645 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3646 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3647 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3648 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3649 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3650
3651 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3652 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3653 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3654 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG
3655
3656/* 6x00 Series */
5953a62e
WYG
3657 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3658 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3659 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3660 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3661 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3662 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3663 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3664 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3665 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3666 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3667
3668/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3669 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3670 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3671 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3672 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3673 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3674 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3675
77dcb6a9 3676/* 1000 Series WiFi */
4bd0914f
WYG
3677 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3678 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3679 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3680 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3681 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3682 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3683 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3684 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3685 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3686 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3687 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3688 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3689#endif /* CONFIG_IWL5000 */
7100e924 3690
fed9017e
RR
3691 {0}
3692};
3693MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3694
3695static struct pci_driver iwl_driver = {
b481de9c 3696 .name = DRV_NAME,
fed9017e 3697 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3698 .probe = iwl_pci_probe,
3699 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3700#ifdef CONFIG_PM
5b9f8cd3
EG
3701 .suspend = iwl_pci_suspend,
3702 .resume = iwl_pci_resume,
b481de9c
ZY
3703#endif
3704};
3705
5b9f8cd3 3706static int __init iwl_init(void)
b481de9c
ZY
3707{
3708
3709 int ret;
3710 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3711 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3712
e227ceac 3713 ret = iwlagn_rate_control_register();
897e1cf2 3714 if (ret) {
a3139c59
SO
3715 printk(KERN_ERR DRV_NAME
3716 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3717 return ret;
3718 }
3719
fed9017e 3720 ret = pci_register_driver(&iwl_driver);
b481de9c 3721 if (ret) {
a3139c59 3722 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3723 goto error_register;
b481de9c 3724 }
b481de9c
ZY
3725
3726 return ret;
897e1cf2 3727
897e1cf2 3728error_register:
e227ceac 3729 iwlagn_rate_control_unregister();
897e1cf2 3730 return ret;
b481de9c
ZY
3731}
3732
5b9f8cd3 3733static void __exit iwl_exit(void)
b481de9c 3734{
fed9017e 3735 pci_unregister_driver(&iwl_driver);
e227ceac 3736 iwlagn_rate_control_unregister();
b481de9c
ZY
3737}
3738
5b9f8cd3
EG
3739module_exit(iwl_exit);
3740module_init(iwl_init);
a562a9dd
RC
3741
3742#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3743module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3744MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3745module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3746MODULE_PARM_DESC(debug, "debug output mask");
3747#endif
3748