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Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
b481de9c ZY |
43 | #include <net/mac80211.h> |
44 | ||
45 | #include <asm/div64.h> | |
46 | ||
a3139c59 SO |
47 | #define DRV_NAME "iwlagn" |
48 | ||
6bc913bd | 49 | #include "iwl-eeprom.h" |
3e0d4cb1 | 50 | #include "iwl-dev.h" |
fee1247a | 51 | #include "iwl-core.h" |
3395f6e9 | 52 | #include "iwl-io.h" |
b481de9c | 53 | #include "iwl-helpers.h" |
6974e363 | 54 | #include "iwl-sta.h" |
f0832f13 | 55 | #include "iwl-calib.h" |
b481de9c | 56 | |
416e1438 | 57 | |
b481de9c ZY |
58 | /****************************************************************************** |
59 | * | |
60 | * module boiler plate | |
61 | * | |
62 | ******************************************************************************/ | |
63 | ||
b481de9c ZY |
64 | /* |
65 | * module name, copyright, version, etc. | |
b481de9c | 66 | */ |
d783b061 | 67 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 68 | |
0a6857e7 | 69 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
70 | #define VD "d" |
71 | #else | |
72 | #define VD | |
73 | #endif | |
74 | ||
80bc5393 | 75 | #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT |
b481de9c ZY |
76 | #define VS "s" |
77 | #else | |
78 | #define VS | |
79 | #endif | |
80 | ||
df48c323 | 81 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 87 | MODULE_LICENSE("GPL"); |
4fc22b21 | 88 | MODULE_ALIAS("iwl4965"); |
b481de9c | 89 | |
b481de9c | 90 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 91 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
92 | * the functionality provided here |
93 | */ | |
94 | ||
95 | /**************************************************************/ | |
96 | ||
b481de9c | 97 | /** |
5b9f8cd3 | 98 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 99 | * |
01ebd063 | 100 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
101 | * the active_rxon structure is updated with the new data. This |
102 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
103 | * a HW tune is required based on the RXON structure changes. | |
104 | */ | |
e0158e61 | 105 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
106 | { |
107 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 108 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
109 | int ret; |
110 | bool new_assoc = | |
111 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 112 | |
fee1247a | 113 | if (!iwl_is_alive(priv)) |
43d59b32 | 114 | return -EBUSY; |
b481de9c ZY |
115 | |
116 | /* always get timestamp with Rx frame */ | |
117 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
118 | ||
8ccde88a | 119 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 120 | if (ret) { |
15b1687c | 121 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
122 | return -EINVAL; |
123 | } | |
124 | ||
125 | /* If we don't need to send a full RXON, we can use | |
5b9f8cd3 | 126 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 127 | * and other flags for the current radio configuration. */ |
54559703 | 128 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
129 | ret = iwl_send_rxon_assoc(priv); |
130 | if (ret) { | |
15b1687c | 131 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 132 | return ret; |
b481de9c ZY |
133 | } |
134 | ||
135 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
136 | return 0; |
137 | } | |
138 | ||
139 | /* station table will be cleared */ | |
140 | priv->assoc_station_added = 0; | |
141 | ||
b481de9c ZY |
142 | /* If we are currently associated and the new config requires |
143 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
144 | * we must clear the associated from the active configuration | |
145 | * before we apply the new config */ | |
43d59b32 | 146 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 147 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
148 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
149 | ||
43d59b32 | 150 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 151 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
152 | &priv->active_rxon); |
153 | ||
154 | /* If the mask clearing failed then we set | |
155 | * active_rxon back to what it was previously */ | |
43d59b32 | 156 | if (ret) { |
b481de9c | 157 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 158 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 159 | return ret; |
b481de9c | 160 | } |
b481de9c ZY |
161 | } |
162 | ||
e1623446 | 163 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
164 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
165 | "* channel = %d\n" | |
e174961c | 166 | "* bssid = %pM\n", |
43d59b32 | 167 | (new_assoc ? "" : "out"), |
b481de9c | 168 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 169 | priv->staging_rxon.bssid_addr); |
b481de9c | 170 | |
90e8e424 | 171 | iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto); |
43d59b32 EG |
172 | |
173 | /* Apply the new configuration | |
174 | * RXON unassoc clears the station table in uCode, send it before | |
175 | * we add the bcast station. If assoc bit is set, we will send RXON | |
176 | * after having added the bcast and bssid station. | |
177 | */ | |
178 | if (!new_assoc) { | |
179 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 180 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 181 | if (ret) { |
15b1687c | 182 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
183 | return ret; |
184 | } | |
185 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
186 | } |
187 | ||
c587de0b | 188 | iwl_clear_stations_table(priv); |
556f8db7 | 189 | |
19cc1087 | 190 | priv->start_calib = 0; |
b481de9c | 191 | |
b481de9c | 192 | /* Add the broadcast address so we can send broadcast frames */ |
4f40e4d9 | 193 | if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) == |
43d59b32 | 194 | IWL_INVALID_STATION) { |
15b1687c | 195 | IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n"); |
b481de9c ZY |
196 | return -EIO; |
197 | } | |
198 | ||
199 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
200 | * add the IWL_AP_ID to the station rate table */ | |
9185159d | 201 | if (new_assoc) { |
05c914fe | 202 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
9185159d TW |
203 | ret = iwl_rxon_add_station(priv, |
204 | priv->active_rxon.bssid_addr, 1); | |
205 | if (ret == IWL_INVALID_STATION) { | |
15b1687c WT |
206 | IWL_ERR(priv, |
207 | "Error adding AP address for TX.\n"); | |
9185159d TW |
208 | return -EIO; |
209 | } | |
210 | priv->assoc_station_added = 1; | |
211 | if (priv->default_wep_key && | |
212 | iwl_send_static_wepkey_cmd(priv, 0)) | |
15b1687c WT |
213 | IWL_ERR(priv, |
214 | "Could not send WEP static key.\n"); | |
b481de9c | 215 | } |
43d59b32 | 216 | |
47eef9bd WYG |
217 | /* |
218 | * allow CTS-to-self if possible for new association. | |
219 | * this is relevant only for 5000 series and up, | |
220 | * but will not damage 4965 | |
221 | */ | |
222 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
223 | ||
43d59b32 EG |
224 | /* Apply the new configuration |
225 | * RXON assoc doesn't clear the station table in uCode, | |
226 | */ | |
227 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
228 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
229 | if (ret) { | |
15b1687c | 230 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
231 | return ret; |
232 | } | |
233 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
234 | } |
235 | ||
36da7d70 ZY |
236 | iwl_init_sensitivity(priv); |
237 | ||
238 | /* If we issue a new RXON command which required a tune then we must | |
239 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
240 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
241 | if (ret) { | |
15b1687c | 242 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
243 | return ret; |
244 | } | |
245 | ||
b481de9c ZY |
246 | return 0; |
247 | } | |
248 | ||
5b9f8cd3 | 249 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
250 | { |
251 | ||
45823531 AK |
252 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
253 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 254 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
255 | } |
256 | ||
fcab423d | 257 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
258 | { |
259 | struct list_head *element; | |
260 | ||
e1623446 | 261 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
262 | priv->frames_count); |
263 | ||
264 | while (!list_empty(&priv->free_frames)) { | |
265 | element = priv->free_frames.next; | |
266 | list_del(element); | |
fcab423d | 267 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
268 | priv->frames_count--; |
269 | } | |
270 | ||
271 | if (priv->frames_count) { | |
39aadf8c | 272 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
273 | priv->frames_count); |
274 | priv->frames_count = 0; | |
275 | } | |
276 | } | |
277 | ||
fcab423d | 278 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 279 | { |
fcab423d | 280 | struct iwl_frame *frame; |
b481de9c ZY |
281 | struct list_head *element; |
282 | if (list_empty(&priv->free_frames)) { | |
283 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
284 | if (!frame) { | |
15b1687c | 285 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
286 | return NULL; |
287 | } | |
288 | ||
289 | priv->frames_count++; | |
290 | return frame; | |
291 | } | |
292 | ||
293 | element = priv->free_frames.next; | |
294 | list_del(element); | |
fcab423d | 295 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
296 | } |
297 | ||
fcab423d | 298 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
299 | { |
300 | memset(frame, 0, sizeof(*frame)); | |
301 | list_add(&frame->list, &priv->free_frames); | |
302 | } | |
303 | ||
4bf64efd TW |
304 | static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv, |
305 | struct ieee80211_hdr *hdr, | |
73ec1cc2 | 306 | int left) |
b481de9c | 307 | { |
3109ece1 | 308 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
309 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
310 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
311 | return 0; |
312 | ||
313 | if (priv->ibss_beacon->len > left) | |
314 | return 0; | |
315 | ||
316 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
317 | ||
318 | return priv->ibss_beacon->len; | |
319 | } | |
320 | ||
5b9f8cd3 | 321 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
4bf64efd TW |
322 | struct iwl_frame *frame, u8 rate) |
323 | { | |
324 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
325 | unsigned int frame_size; | |
326 | ||
327 | tx_beacon_cmd = &frame->u.beacon; | |
328 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
329 | ||
330 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; | |
331 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
332 | ||
333 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, | |
4bf64efd TW |
334 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
335 | ||
336 | BUG_ON(frame_size > MAX_MPDU_SIZE); | |
337 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
338 | ||
339 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | |
340 | tx_beacon_cmd->tx.rate_n_flags = | |
341 | iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); | |
342 | else | |
343 | tx_beacon_cmd->tx.rate_n_flags = | |
344 | iwl_hw_set_rate_n_flags(rate, 0); | |
345 | ||
346 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
347 | TX_CMD_FLG_TSF_MSK | | |
348 | TX_CMD_FLG_STA_RATE_MSK; | |
349 | ||
350 | return sizeof(*tx_beacon_cmd) + frame_size; | |
351 | } | |
5b9f8cd3 | 352 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 353 | { |
fcab423d | 354 | struct iwl_frame *frame; |
b481de9c ZY |
355 | unsigned int frame_size; |
356 | int rc; | |
357 | u8 rate; | |
358 | ||
fcab423d | 359 | frame = iwl_get_free_frame(priv); |
b481de9c ZY |
360 | |
361 | if (!frame) { | |
15b1687c | 362 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
363 | "command.\n"); |
364 | return -ENOMEM; | |
365 | } | |
366 | ||
5b9f8cd3 | 367 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 368 | |
5b9f8cd3 | 369 | frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 370 | |
857485c0 | 371 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
372 | &frame->u.cmd[0]); |
373 | ||
fcab423d | 374 | iwl_free_frame(priv, frame); |
b481de9c ZY |
375 | |
376 | return rc; | |
377 | } | |
378 | ||
7aaa1d79 SO |
379 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
380 | { | |
381 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
382 | ||
383 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
384 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
385 | addr |= | |
386 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
387 | ||
388 | return addr; | |
389 | } | |
390 | ||
391 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
392 | { | |
393 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
394 | ||
395 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
396 | } | |
397 | ||
398 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
399 | dma_addr_t addr, u16 len) | |
400 | { | |
401 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
402 | u16 hi_n_len = len << 4; | |
403 | ||
404 | put_unaligned_le32(addr, &tb->lo); | |
405 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
406 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
407 | ||
408 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
409 | ||
410 | tfd->num_tbs = idx + 1; | |
411 | } | |
412 | ||
413 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
414 | { | |
415 | return tfd->num_tbs & 0x1f; | |
416 | } | |
417 | ||
418 | /** | |
419 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
420 | * @priv - driver private data | |
421 | * @txq - tx queue | |
422 | * | |
423 | * Does NOT advance any TFD circular buffer read/write indexes | |
424 | * Does NOT free the TFD itself (which is within circular buffer) | |
425 | */ | |
426 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
427 | { | |
59606ffa | 428 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
429 | struct iwl_tfd *tfd; |
430 | struct pci_dev *dev = priv->pci_dev; | |
431 | int index = txq->q.read_ptr; | |
432 | int i; | |
433 | int num_tbs; | |
434 | ||
435 | tfd = &tfd_tmp[index]; | |
436 | ||
437 | /* Sanity check on number of chunks */ | |
438 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
439 | ||
440 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
441 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
442 | /* @todo issue fatal error, it is quite serious situation */ | |
443 | return; | |
444 | } | |
445 | ||
446 | /* Unmap tx_cmd */ | |
447 | if (num_tbs) | |
448 | pci_unmap_single(dev, | |
c2acea8e JB |
449 | pci_unmap_addr(&txq->meta[index], mapping), |
450 | pci_unmap_len(&txq->meta[index], len), | |
96891cee | 451 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
452 | |
453 | /* Unmap chunks, if any. */ | |
454 | for (i = 1; i < num_tbs; i++) { | |
455 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
456 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
457 | ||
458 | if (txq->txb) { | |
459 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
460 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
461 | } | |
462 | } | |
463 | } | |
464 | ||
465 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
466 | struct iwl_tx_queue *txq, | |
467 | dma_addr_t addr, u16 len, | |
468 | u8 reset, u8 pad) | |
469 | { | |
470 | struct iwl_queue *q; | |
59606ffa | 471 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
472 | u32 num_tbs; |
473 | ||
474 | q = &txq->q; | |
59606ffa SO |
475 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
476 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
477 | |
478 | if (reset) | |
479 | memset(tfd, 0, sizeof(*tfd)); | |
480 | ||
481 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
482 | ||
483 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
484 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
485 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
486 | IWL_NUM_OF_TBS); | |
487 | return -EINVAL; | |
488 | } | |
489 | ||
490 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
491 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
492 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
493 | (unsigned long long)addr); | |
494 | ||
495 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
a8e74e27 SO |
500 | /* |
501 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
502 | * given Tx queue, and enable the DMA channel used for that queue. | |
503 | * | |
504 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
505 | * channels supported in hardware. | |
506 | */ | |
507 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
508 | struct iwl_tx_queue *txq) | |
509 | { | |
a8e74e27 SO |
510 | int txq_id = txq->q.id; |
511 | ||
a8e74e27 SO |
512 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
513 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
514 | txq->q.dma_addr >> 8); | |
515 | ||
a8e74e27 SO |
516 | return 0; |
517 | } | |
518 | ||
b481de9c ZY |
519 | /****************************************************************************** |
520 | * | |
521 | * Generic RX handler implementations | |
522 | * | |
523 | ******************************************************************************/ | |
885ba202 TW |
524 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
525 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 526 | { |
db11d634 | 527 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
885ba202 | 528 | struct iwl_alive_resp *palive; |
b481de9c ZY |
529 | struct delayed_work *pwork; |
530 | ||
531 | palive = &pkt->u.alive_frame; | |
532 | ||
e1623446 | 533 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
534 | "0x%01X 0x%01X\n", |
535 | palive->is_valid, palive->ver_type, | |
536 | palive->ver_subtype); | |
537 | ||
538 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 539 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
540 | memcpy(&priv->card_alive_init, |
541 | &pkt->u.alive_frame, | |
885ba202 | 542 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
543 | pwork = &priv->init_alive_start; |
544 | } else { | |
e1623446 | 545 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 546 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 547 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
548 | pwork = &priv->alive_start; |
549 | } | |
550 | ||
551 | /* We delay the ALIVE response by 5ms to | |
552 | * give the HW RF Kill time to activate... */ | |
553 | if (palive->is_valid == UCODE_VALID_OK) | |
554 | queue_delayed_work(priv->workqueue, pwork, | |
555 | msecs_to_jiffies(5)); | |
556 | else | |
39aadf8c | 557 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
558 | } |
559 | ||
5b9f8cd3 | 560 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 561 | { |
c79dd5b5 TW |
562 | struct iwl_priv *priv = |
563 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
564 | struct sk_buff *beacon; |
565 | ||
566 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 567 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
568 | |
569 | if (!beacon) { | |
15b1687c | 570 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
571 | return; |
572 | } | |
573 | ||
574 | mutex_lock(&priv->mutex); | |
575 | /* new beacon skb is allocated every time; dispose previous.*/ | |
576 | if (priv->ibss_beacon) | |
577 | dev_kfree_skb(priv->ibss_beacon); | |
578 | ||
579 | priv->ibss_beacon = beacon; | |
580 | mutex_unlock(&priv->mutex); | |
581 | ||
5b9f8cd3 | 582 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
583 | } |
584 | ||
4e39317d | 585 | /** |
5b9f8cd3 | 586 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
587 | * |
588 | * This callback is provided in order to send a statistics request. | |
589 | * | |
590 | * This timer function is continually reset to execute within | |
591 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
592 | * was received. We need to ensure we receive the statistics in order | |
593 | * to update the temperature used for calibrating the TXPOWER. | |
594 | */ | |
5b9f8cd3 | 595 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
596 | { |
597 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
598 | ||
599 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
600 | return; | |
601 | ||
61780ee3 MA |
602 | /* dont send host command if rf-kill is on */ |
603 | if (!iwl_is_ready_rf(priv)) | |
604 | return; | |
605 | ||
4e39317d EG |
606 | iwl_send_statistics_request(priv, CMD_ASYNC); |
607 | } | |
608 | ||
5b9f8cd3 | 609 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 610 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 611 | { |
0a6857e7 | 612 | #ifdef CONFIG_IWLWIFI_DEBUG |
db11d634 | 613 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
2aa6ab86 TW |
614 | struct iwl4965_beacon_notif *beacon = |
615 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 616 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 617 | |
e1623446 | 618 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 619 | "tsf %d %d rate %d\n", |
25a6572c | 620 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
621 | beacon->beacon_notify_hdr.failure_frame, |
622 | le32_to_cpu(beacon->ibss_mgr_status), | |
623 | le32_to_cpu(beacon->high_tsf), | |
624 | le32_to_cpu(beacon->low_tsf), rate); | |
625 | #endif | |
626 | ||
05c914fe | 627 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
628 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
629 | queue_work(priv->workqueue, &priv->beacon_update); | |
630 | } | |
631 | ||
b481de9c ZY |
632 | /* Handle notification from uCode that card's power state is changing |
633 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 634 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 635 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 636 | { |
db11d634 | 637 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
638 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
639 | unsigned long status = priv->status; | |
640 | ||
e1623446 | 641 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
642 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
643 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
644 | ||
645 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
646 | RF_CARD_DISABLED)) { | |
647 | ||
3395f6e9 | 648 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
649 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
650 | ||
a8b50a0a MA |
651 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
652 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
653 | |
654 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 655 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 656 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 657 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 658 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 659 | } |
39b73fb1 WYG |
660 | if (flags & RF_CARD_DISABLED) |
661 | iwl_tt_enter_ct_kill(priv); | |
b481de9c | 662 | } |
39b73fb1 WYG |
663 | if (!(flags & RF_CARD_DISABLED)) |
664 | iwl_tt_exit_ct_kill(priv); | |
b481de9c ZY |
665 | |
666 | if (flags & HW_CARD_DISABLED) | |
667 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
668 | else | |
669 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
670 | ||
671 | ||
b481de9c | 672 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 673 | iwl_scan_cancel(priv); |
b481de9c ZY |
674 | |
675 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
676 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
677 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
678 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
679 | else |
680 | wake_up_interruptible(&priv->wait_command_queue); | |
681 | } | |
682 | ||
5b9f8cd3 | 683 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 684 | { |
e2e3c57b | 685 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 686 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
687 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
688 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
689 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
690 | } else { | |
691 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
692 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
693 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
694 | } | |
695 | ||
a8b50a0a | 696 | return 0; |
e2e3c57b TW |
697 | } |
698 | ||
b481de9c | 699 | /** |
5b9f8cd3 | 700 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
701 | * |
702 | * Setup the RX handlers for each of the reply types sent from the uCode | |
703 | * to the host. | |
704 | * | |
705 | * This function chains into the hardware specific files for them to setup | |
706 | * any hardware specific handlers as well. | |
707 | */ | |
653fa4a0 | 708 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 709 | { |
885ba202 | 710 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
711 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
712 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
5b9f8cd3 | 713 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 714 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
715 | iwl_rx_pm_debug_statistics_notif; |
716 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 717 | |
9fbab516 BC |
718 | /* |
719 | * The same handler is used for both the REPLY to a discrete | |
720 | * statistics request from the host as well as for the periodic | |
721 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 722 | */ |
8f91aecb EG |
723 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics; |
724 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; | |
2a421b91 | 725 | |
21c339bf | 726 | iwl_setup_spectrum_handlers(priv); |
2a421b91 TW |
727 | iwl_setup_rx_scan_handlers(priv); |
728 | ||
37a44211 | 729 | /* status change handler */ |
5b9f8cd3 | 730 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 731 | |
c1354754 TW |
732 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
733 | iwl_rx_missed_beacon_notif; | |
37a44211 | 734 | /* Rx handlers */ |
1781a07f EG |
735 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy; |
736 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx; | |
653fa4a0 EG |
737 | /* block ack */ |
738 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba; | |
9fbab516 | 739 | /* Set up hardware specific Rx handlers */ |
d4789efe | 740 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
741 | } |
742 | ||
b481de9c | 743 | /** |
a55360e4 | 744 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
745 | * |
746 | * Uses the priv->rx_handlers callback function array to invoke | |
747 | * the appropriate handlers, including command responses, | |
748 | * frame-received notifications, and other notifications. | |
749 | */ | |
a55360e4 | 750 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 751 | { |
a55360e4 | 752 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 753 | struct iwl_rx_packet *pkt; |
a55360e4 | 754 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
755 | u32 r, i; |
756 | int reclaim; | |
757 | unsigned long flags; | |
5c0eef96 | 758 | u8 fill_rx = 0; |
d68ab680 | 759 | u32 count = 8; |
4752c93c | 760 | int total_empty; |
b481de9c | 761 | |
6440adb5 BC |
762 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
763 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 764 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
765 | i = rxq->read; |
766 | ||
767 | /* Rx interrupt, but nothing sent from uCode */ | |
768 | if (i == r) | |
e1623446 | 769 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 770 | |
4752c93c MA |
771 | /* calculate total frames need to be restock after handling RX */ |
772 | total_empty = r - priv->rxq.write_actual; | |
773 | if (total_empty < 0) | |
774 | total_empty += RX_QUEUE_SIZE; | |
775 | ||
776 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
777 | fill_rx = 1; |
778 | ||
b481de9c ZY |
779 | while (i != r) { |
780 | rxb = rxq->queue[i]; | |
781 | ||
9fbab516 | 782 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
783 | * then a bug has been introduced in the queue refilling |
784 | * routines -- catch it here */ | |
785 | BUG_ON(rxb == NULL); | |
786 | ||
787 | rxq->queue[i] = NULL; | |
788 | ||
df833b1d RC |
789 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
790 | priv->hw_params.rx_buf_size + 256, | |
791 | PCI_DMA_FROMDEVICE); | |
db11d634 | 792 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
793 | |
794 | /* Reclaim a command buffer only if this packet is a response | |
795 | * to a (driver-originated) command. | |
796 | * If the packet (e.g. Rx frame) originated from uCode, | |
797 | * there is no command buffer to reclaim. | |
798 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
799 | * but apparently a few don't get set; catch them here. */ | |
800 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
801 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 802 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 803 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 804 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
805 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
806 | (pkt->hdr.cmd != REPLY_TX); | |
807 | ||
808 | /* Based on type of command response or notification, | |
809 | * handle those that need handling via function in | |
5b9f8cd3 | 810 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 811 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 812 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 813 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
b481de9c | 814 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
a83b9141 | 815 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
b481de9c ZY |
816 | } else { |
817 | /* No handling needed */ | |
e1623446 | 818 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
819 | "r %d i %d No handler needed for %s, 0x%02x\n", |
820 | r, i, get_cmd_string(pkt->hdr.cmd), | |
821 | pkt->hdr.cmd); | |
822 | } | |
823 | ||
824 | if (reclaim) { | |
9fbab516 | 825 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 826 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
827 | * as we reclaim the driver command queue */ |
828 | if (rxb && rxb->skb) | |
17b88929 | 829 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 830 | else |
39aadf8c | 831 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
832 | } |
833 | ||
834 | /* For now we just don't re-use anything. We can tweak this | |
835 | * later to try and re-use notification packets and SKBs that | |
836 | * fail to Rx correctly */ | |
837 | if (rxb->skb != NULL) { | |
838 | priv->alloc_rxb_skb--; | |
839 | dev_kfree_skb_any(rxb->skb); | |
840 | rxb->skb = NULL; | |
841 | } | |
842 | ||
b481de9c ZY |
843 | spin_lock_irqsave(&rxq->lock, flags); |
844 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
845 | spin_unlock_irqrestore(&rxq->lock, flags); | |
846 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
847 | /* If there are a lot of unused frames, |
848 | * restock the Rx queue so ucode wont assert. */ | |
849 | if (fill_rx) { | |
850 | count++; | |
851 | if (count >= 8) { | |
852 | priv->rxq.read = i; | |
4752c93c | 853 | iwl_rx_replenish_now(priv); |
5c0eef96 MA |
854 | count = 0; |
855 | } | |
856 | } | |
b481de9c ZY |
857 | } |
858 | ||
859 | /* Backtrack one entry */ | |
860 | priv->rxq.read = i; | |
4752c93c MA |
861 | if (fill_rx) |
862 | iwl_rx_replenish_now(priv); | |
863 | else | |
864 | iwl_rx_queue_restock(priv); | |
a55360e4 | 865 | } |
a55360e4 | 866 | |
0359facc MA |
867 | /* call this function to flush any scheduled tasklet */ |
868 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
869 | { | |
a96a27f9 | 870 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
871 | synchronize_irq(priv->pci_dev->irq); |
872 | tasklet_kill(&priv->irq_tasklet); | |
873 | } | |
874 | ||
ef850d7c | 875 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
876 | { |
877 | u32 inta, handled = 0; | |
878 | u32 inta_fh; | |
879 | unsigned long flags; | |
0a6857e7 | 880 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
881 | u32 inta_mask; |
882 | #endif | |
883 | ||
884 | spin_lock_irqsave(&priv->lock, flags); | |
885 | ||
886 | /* Ack/clear/reset pending uCode interrupts. | |
887 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
888 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
889 | inta = iwl_read32(priv, CSR_INT); |
890 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
891 | |
892 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
893 | * Any new interrupts that happen after this, either while we're | |
894 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
895 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
896 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 897 | |
0a6857e7 | 898 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 899 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 900 | /* just for debug */ |
3395f6e9 | 901 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 902 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
903 | inta, inta_mask, inta_fh); |
904 | } | |
905 | #endif | |
906 | ||
907 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
908 | * atomic, make sure that inta covers all the interrupts that | |
909 | * we've discovered, even if FH interrupt came in just after | |
910 | * reading CSR_INT. */ | |
6f83eaa1 | 911 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 912 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 913 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
914 | inta |= CSR_INT_BIT_FH_TX; |
915 | ||
916 | /* Now service all interrupt bits discovered above. */ | |
917 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 918 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
919 | |
920 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 921 | iwl_disable_interrupts(priv); |
b481de9c | 922 | |
a83b9141 | 923 | priv->isr_stats.hw++; |
5b9f8cd3 | 924 | iwl_irq_handle_error(priv); |
b481de9c ZY |
925 | |
926 | handled |= CSR_INT_BIT_HW_ERR; | |
927 | ||
928 | spin_unlock_irqrestore(&priv->lock, flags); | |
929 | ||
930 | return; | |
931 | } | |
932 | ||
0a6857e7 | 933 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 934 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 935 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 936 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 937 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 938 | "the frame/frames.\n"); |
a83b9141 WYG |
939 | priv->isr_stats.sch++; |
940 | } | |
b481de9c ZY |
941 | |
942 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 943 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 944 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
945 | priv->isr_stats.alive++; |
946 | } | |
b481de9c ZY |
947 | } |
948 | #endif | |
949 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 950 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 951 | |
9fbab516 | 952 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
953 | if (inta & CSR_INT_BIT_RF_KILL) { |
954 | int hw_rf_kill = 0; | |
3395f6e9 | 955 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
956 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
957 | hw_rf_kill = 1; | |
958 | ||
4c423a2b | 959 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 960 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 961 | |
a83b9141 WYG |
962 | priv->isr_stats.rfkill++; |
963 | ||
a9efa652 | 964 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
965 | * the driver allows loading the ucode even if the radio |
966 | * is killed. Hence update the killswitch state here. The | |
967 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 968 | */ |
6cd0b1cb HS |
969 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
970 | if (hw_rf_kill) | |
971 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
972 | else | |
973 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 974 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 975 | } |
b481de9c ZY |
976 | |
977 | handled |= CSR_INT_BIT_RF_KILL; | |
978 | } | |
979 | ||
9fbab516 | 980 | /* Chip got too hot and stopped itself */ |
b481de9c | 981 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 982 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 983 | priv->isr_stats.ctkill++; |
b481de9c ZY |
984 | handled |= CSR_INT_BIT_CT_KILL; |
985 | } | |
986 | ||
987 | /* Error detected by uCode */ | |
988 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
989 | IWL_ERR(priv, "Microcode SW error detected. " |
990 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
991 | priv->isr_stats.sw++; |
992 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 993 | iwl_irq_handle_error(priv); |
b481de9c ZY |
994 | handled |= CSR_INT_BIT_SW_ERR; |
995 | } | |
996 | ||
997 | /* uCode wakes up after power-down sleep */ | |
998 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 999 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1000 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
babcebfa TW |
1001 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1002 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1003 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1004 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1005 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1006 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1007 | |
a83b9141 WYG |
1008 | priv->isr_stats.wakeup++; |
1009 | ||
b481de9c ZY |
1010 | handled |= CSR_INT_BIT_WAKEUP; |
1011 | } | |
1012 | ||
1013 | /* All uCode command responses, including Tx command responses, | |
1014 | * Rx "responses" (frame-received notification), and other | |
1015 | * notifications from uCode come through here*/ | |
1016 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1017 | iwl_rx_handle(priv); |
a83b9141 | 1018 | priv->isr_stats.rx++; |
b481de9c ZY |
1019 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1020 | } | |
1021 | ||
1022 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1023 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
a83b9141 | 1024 | priv->isr_stats.tx++; |
b481de9c | 1025 | handled |= CSR_INT_BIT_FH_TX; |
dbb983b7 RR |
1026 | /* FH finished to write, send event */ |
1027 | priv->ucode_write_complete = 1; | |
1028 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1029 | } |
1030 | ||
a83b9141 | 1031 | if (inta & ~handled) { |
15b1687c | 1032 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1033 | priv->isr_stats.unhandled++; |
1034 | } | |
b481de9c | 1035 | |
40cefda9 | 1036 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1037 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1038 | inta & ~priv->inta_mask); |
39aadf8c | 1039 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1040 | } |
1041 | ||
1042 | /* Re-enable all interrupts */ | |
0359facc MA |
1043 | /* only Re-enable if diabled by irq */ |
1044 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1045 | iwl_enable_interrupts(priv); |
b481de9c | 1046 | |
0a6857e7 | 1047 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1048 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1049 | inta = iwl_read32(priv, CSR_INT); |
1050 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1051 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1052 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1053 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1054 | } | |
1055 | #endif | |
1056 | spin_unlock_irqrestore(&priv->lock, flags); | |
1057 | } | |
1058 | ||
ef850d7c MA |
1059 | /* tasklet for iwlagn interrupt */ |
1060 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1061 | { | |
1062 | u32 inta = 0; | |
1063 | u32 handled = 0; | |
1064 | unsigned long flags; | |
1065 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1066 | u32 inta_mask; | |
1067 | #endif | |
1068 | ||
1069 | spin_lock_irqsave(&priv->lock, flags); | |
1070 | ||
1071 | /* Ack/clear/reset pending uCode interrupts. | |
1072 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1073 | */ | |
1074 | iwl_write32(priv, CSR_INT, priv->inta); | |
1075 | ||
1076 | inta = priv->inta; | |
1077 | ||
1078 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1079 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1080 | /* just for debug */ |
1081 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1082 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1083 | inta, inta_mask); | |
1084 | } | |
1085 | #endif | |
1086 | /* saved interrupt in inta variable now we can reset priv->inta */ | |
1087 | priv->inta = 0; | |
1088 | ||
1089 | /* Now service all interrupt bits discovered above. */ | |
1090 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1091 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1092 | |
1093 | /* Tell the device to stop sending interrupts */ | |
1094 | iwl_disable_interrupts(priv); | |
1095 | ||
1096 | priv->isr_stats.hw++; | |
1097 | iwl_irq_handle_error(priv); | |
1098 | ||
1099 | handled |= CSR_INT_BIT_HW_ERR; | |
1100 | ||
1101 | spin_unlock_irqrestore(&priv->lock, flags); | |
1102 | ||
1103 | return; | |
1104 | } | |
1105 | ||
1106 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1107 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1108 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1109 | if (inta & CSR_INT_BIT_SCD) { | |
1110 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1111 | "the frame/frames.\n"); | |
1112 | priv->isr_stats.sch++; | |
1113 | } | |
1114 | ||
1115 | /* Alive notification via Rx interrupt will do the real work */ | |
1116 | if (inta & CSR_INT_BIT_ALIVE) { | |
1117 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1118 | priv->isr_stats.alive++; | |
1119 | } | |
1120 | } | |
1121 | #endif | |
1122 | /* Safely ignore these bits for debug checks below */ | |
1123 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1124 | ||
1125 | /* HW RF KILL switch toggled */ | |
1126 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1127 | int hw_rf_kill = 0; | |
1128 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1129 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1130 | hw_rf_kill = 1; | |
1131 | ||
4c423a2b | 1132 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1133 | hw_rf_kill ? "disable radio" : "enable radio"); |
1134 | ||
1135 | priv->isr_stats.rfkill++; | |
1136 | ||
1137 | /* driver only loads ucode once setting the interface up. | |
1138 | * the driver allows loading the ucode even if the radio | |
1139 | * is killed. Hence update the killswitch state here. The | |
1140 | * rfkill handler will care about restarting if needed. | |
1141 | */ | |
1142 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1143 | if (hw_rf_kill) | |
1144 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1145 | else | |
1146 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1147 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1148 | } |
1149 | ||
1150 | handled |= CSR_INT_BIT_RF_KILL; | |
1151 | } | |
1152 | ||
1153 | /* Chip got too hot and stopped itself */ | |
1154 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1155 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1156 | priv->isr_stats.ctkill++; | |
1157 | handled |= CSR_INT_BIT_CT_KILL; | |
1158 | } | |
1159 | ||
1160 | /* Error detected by uCode */ | |
1161 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1162 | IWL_ERR(priv, "Microcode SW error detected. " | |
1163 | " Restarting 0x%X.\n", inta); | |
1164 | priv->isr_stats.sw++; | |
1165 | priv->isr_stats.sw_err = inta; | |
1166 | iwl_irq_handle_error(priv); | |
1167 | handled |= CSR_INT_BIT_SW_ERR; | |
1168 | } | |
1169 | ||
1170 | /* uCode wakes up after power-down sleep */ | |
1171 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1172 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1173 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
1174 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); | |
1175 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1176 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1177 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1178 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1179 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
1180 | ||
1181 | priv->isr_stats.wakeup++; | |
1182 | ||
1183 | handled |= CSR_INT_BIT_WAKEUP; | |
1184 | } | |
1185 | ||
1186 | /* All uCode command responses, including Tx command responses, | |
1187 | * Rx "responses" (frame-received notification), and other | |
1188 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1189 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1190 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1191 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1192 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1193 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1194 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1195 | CSR49_FH_INT_RX_MASK); | |
1196 | } | |
1197 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1198 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1199 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1200 | } | |
1201 | /* Sending RX interrupt require many steps to be done in the | |
1202 | * the device: | |
1203 | * 1- write interrupt to current index in ICT table. | |
1204 | * 2- dma RX frame. | |
1205 | * 3- update RX shared data to indicate last write index. | |
1206 | * 4- send interrupt. | |
1207 | * This could lead to RX race, driver could receive RX interrupt | |
1208 | * but the shared data changes does not reflect this. | |
1209 | * this could lead to RX race, RX periodic will solve this race | |
1210 | */ | |
1211 | iwl_write32(priv, CSR_INT_PERIODIC_REG, | |
1212 | CSR_INT_PERIODIC_DIS); | |
ef850d7c | 1213 | iwl_rx_handle(priv); |
40cefda9 MA |
1214 | /* Only set RX periodic if real RX is received. */ |
1215 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1216 | iwl_write32(priv, CSR_INT_PERIODIC_REG, | |
1217 | CSR_INT_PERIODIC_ENA); | |
1218 | ||
ef850d7c | 1219 | priv->isr_stats.rx++; |
ef850d7c MA |
1220 | } |
1221 | ||
1222 | if (inta & CSR_INT_BIT_FH_TX) { | |
1223 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
1224 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); | |
1225 | priv->isr_stats.tx++; | |
1226 | handled |= CSR_INT_BIT_FH_TX; | |
1227 | /* FH finished to write, send event */ | |
1228 | priv->ucode_write_complete = 1; | |
1229 | wake_up_interruptible(&priv->wait_command_queue); | |
1230 | } | |
1231 | ||
1232 | if (inta & ~handled) { | |
1233 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1234 | priv->isr_stats.unhandled++; | |
1235 | } | |
1236 | ||
40cefda9 | 1237 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1238 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1239 | inta & ~priv->inta_mask); |
ef850d7c MA |
1240 | } |
1241 | ||
1242 | ||
1243 | /* Re-enable all interrupts */ | |
1244 | /* only Re-enable if diabled by irq */ | |
1245 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1246 | iwl_enable_interrupts(priv); | |
1247 | ||
1248 | spin_unlock_irqrestore(&priv->lock, flags); | |
1249 | ||
1250 | } | |
1251 | ||
a83b9141 | 1252 | |
b481de9c ZY |
1253 | /****************************************************************************** |
1254 | * | |
1255 | * uCode download functions | |
1256 | * | |
1257 | ******************************************************************************/ | |
1258 | ||
5b9f8cd3 | 1259 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1260 | { |
98c92211 TW |
1261 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1262 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1263 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1264 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1265 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1266 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1267 | } |
1268 | ||
5b9f8cd3 | 1269 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1270 | { |
1271 | /* Remove all resets to allow NIC to operate */ | |
1272 | iwl_write32(priv, CSR_RESET, 0); | |
1273 | } | |
1274 | ||
1275 | ||
b481de9c | 1276 | /** |
5b9f8cd3 | 1277 | * iwl_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
1278 | * |
1279 | * Copy into buffers for card to fetch via bus-mastering | |
1280 | */ | |
5b9f8cd3 | 1281 | static int iwl_read_ucode(struct iwl_priv *priv) |
b481de9c | 1282 | { |
cc0f555d | 1283 | struct iwl_ucode_header *ucode; |
a0987a8d | 1284 | int ret = -EINVAL, index; |
b481de9c | 1285 | const struct firmware *ucode_raw; |
a0987a8d RC |
1286 | const char *name_pre = priv->cfg->fw_name_pre; |
1287 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
1288 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
1289 | char buf[25]; | |
b481de9c ZY |
1290 | u8 *src; |
1291 | size_t len; | |
cc0f555d JS |
1292 | u32 api_ver, build; |
1293 | u32 inst_size, data_size, init_size, init_data_size, boot_size; | |
abdc2d62 | 1294 | u16 eeprom_ver; |
b481de9c ZY |
1295 | |
1296 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
1297 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
1298 | for (index = api_max; index >= api_min; index--) { |
1299 | sprintf(buf, "%s%d%s", name_pre, index, ".ucode"); | |
1300 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
1301 | if (ret < 0) { | |
15b1687c | 1302 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
1303 | buf, ret); |
1304 | if (ret == -ENOENT) | |
1305 | continue; | |
1306 | else | |
1307 | goto error; | |
1308 | } else { | |
1309 | if (index < api_max) | |
15b1687c WT |
1310 | IWL_ERR(priv, "Loaded firmware %s, " |
1311 | "which is deprecated. " | |
1312 | "Please use API v%u instead.\n", | |
a0987a8d | 1313 | buf, api_max); |
15b1687c | 1314 | |
e1623446 | 1315 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n", |
a0987a8d RC |
1316 | buf, ucode_raw->size); |
1317 | break; | |
1318 | } | |
b481de9c ZY |
1319 | } |
1320 | ||
a0987a8d RC |
1321 | if (ret < 0) |
1322 | goto error; | |
b481de9c | 1323 | |
cc0f555d JS |
1324 | /* Make sure that we got at least the v1 header! */ |
1325 | if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) { | |
15b1687c | 1326 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 1327 | ret = -EINVAL; |
b481de9c ZY |
1328 | goto err_release; |
1329 | } | |
1330 | ||
1331 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1332 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1333 | |
c02b3acd | 1334 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 1335 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
cc0f555d JS |
1336 | build = priv->cfg->ops->ucode->get_build(ucode, api_ver); |
1337 | inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver); | |
1338 | data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver); | |
1339 | init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver); | |
1340 | init_data_size = | |
1341 | priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver); | |
1342 | boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver); | |
1343 | src = priv->cfg->ops->ucode->get_data(ucode, api_ver); | |
b481de9c | 1344 | |
a0987a8d RC |
1345 | /* api_ver should match the api version forming part of the |
1346 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 1347 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
1348 | |
1349 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 1350 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1351 | "Driver supports v%u, firmware is v%u.\n", |
1352 | api_max, api_ver); | |
1353 | priv->ucode_ver = 0; | |
1354 | ret = -EINVAL; | |
1355 | goto err_release; | |
1356 | } | |
1357 | if (api_ver != api_max) | |
978785a3 | 1358 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1359 | "got v%u. New firmware can be obtained " |
1360 | "from http://www.intellinuxwireless.org.\n", | |
1361 | api_max, api_ver); | |
1362 | ||
978785a3 TW |
1363 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
1364 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1365 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1366 | IWL_UCODE_API(priv->ucode_ver), | |
1367 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d | 1368 | |
cc0f555d JS |
1369 | if (build) |
1370 | IWL_DEBUG_INFO(priv, "Build %u\n", build); | |
1371 | ||
abdc2d62 JS |
1372 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); |
1373 | IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n", | |
1374 | (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) | |
1375 | ? "OTP" : "EEPROM", eeprom_ver); | |
1376 | ||
e1623446 | 1377 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 1378 | priv->ucode_ver); |
e1623446 | 1379 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
b481de9c | 1380 | inst_size); |
e1623446 | 1381 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", |
b481de9c | 1382 | data_size); |
e1623446 | 1383 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", |
b481de9c | 1384 | init_size); |
e1623446 | 1385 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", |
b481de9c | 1386 | init_data_size); |
e1623446 | 1387 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", |
b481de9c ZY |
1388 | boot_size); |
1389 | ||
1390 | /* Verify size of file vs. image size info in file's header */ | |
cc0f555d JS |
1391 | if (ucode_raw->size != |
1392 | priv->cfg->ops->ucode->get_header_size(api_ver) + | |
b481de9c ZY |
1393 | inst_size + data_size + init_size + |
1394 | init_data_size + boot_size) { | |
1395 | ||
cc0f555d JS |
1396 | IWL_DEBUG_INFO(priv, |
1397 | "uCode file size %d does not match expected size\n", | |
1398 | (int)ucode_raw->size); | |
90e759d1 | 1399 | ret = -EINVAL; |
b481de9c ZY |
1400 | goto err_release; |
1401 | } | |
1402 | ||
1403 | /* Verify that uCode images will fit in card's SRAM */ | |
099b40b7 | 1404 | if (inst_size > priv->hw_params.max_inst_size) { |
e1623446 | 1405 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
1406 | inst_size); |
1407 | ret = -EINVAL; | |
b481de9c ZY |
1408 | goto err_release; |
1409 | } | |
1410 | ||
099b40b7 | 1411 | if (data_size > priv->hw_params.max_data_size) { |
e1623446 | 1412 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
1413 | data_size); |
1414 | ret = -EINVAL; | |
b481de9c ZY |
1415 | goto err_release; |
1416 | } | |
099b40b7 | 1417 | if (init_size > priv->hw_params.max_inst_size) { |
e1623446 TW |
1418 | IWL_INFO(priv, "uCode init instr len %d too large to fit in\n", |
1419 | init_size); | |
90e759d1 | 1420 | ret = -EINVAL; |
b481de9c ZY |
1421 | goto err_release; |
1422 | } | |
099b40b7 | 1423 | if (init_data_size > priv->hw_params.max_data_size) { |
e1623446 | 1424 | IWL_INFO(priv, "uCode init data len %d too large to fit in\n", |
90e759d1 TW |
1425 | init_data_size); |
1426 | ret = -EINVAL; | |
b481de9c ZY |
1427 | goto err_release; |
1428 | } | |
099b40b7 | 1429 | if (boot_size > priv->hw_params.max_bsm_size) { |
e1623446 TW |
1430 | IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n", |
1431 | boot_size); | |
90e759d1 | 1432 | ret = -EINVAL; |
b481de9c ZY |
1433 | goto err_release; |
1434 | } | |
1435 | ||
1436 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1437 | ||
1438 | /* Runtime instructions and 2 copies of data: | |
1439 | * 1) unmodified from disk | |
1440 | * 2) backup cache for save/restore during power-downs */ | |
1441 | priv->ucode_code.len = inst_size; | |
98c92211 | 1442 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
1443 | |
1444 | priv->ucode_data.len = data_size; | |
98c92211 | 1445 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
1446 | |
1447 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 1448 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1449 | |
1f304e4e ZY |
1450 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1451 | !priv->ucode_data_backup.v_addr) | |
1452 | goto err_pci_alloc; | |
1453 | ||
b481de9c | 1454 | /* Initialization instructions and data */ |
90e759d1 TW |
1455 | if (init_size && init_data_size) { |
1456 | priv->ucode_init.len = init_size; | |
98c92211 | 1457 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
1458 | |
1459 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 1460 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1461 | |
1462 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1463 | goto err_pci_alloc; | |
1464 | } | |
b481de9c ZY |
1465 | |
1466 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
1467 | if (boot_size) { |
1468 | priv->ucode_boot.len = boot_size; | |
98c92211 | 1469 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1470 | |
90e759d1 TW |
1471 | if (!priv->ucode_boot.v_addr) |
1472 | goto err_pci_alloc; | |
1473 | } | |
b481de9c ZY |
1474 | |
1475 | /* Copy images into buffers for card's bus-master reads ... */ | |
1476 | ||
1477 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 1478 | len = inst_size; |
e1623446 | 1479 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c | 1480 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
1481 | src += len; |
1482 | ||
e1623446 | 1483 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1484 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1485 | ||
1486 | /* Runtime data (2nd block) | |
5b9f8cd3 | 1487 | * NOTE: Copy into backup buffer will be done in iwl_up() */ |
cc0f555d | 1488 | len = data_size; |
e1623446 | 1489 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
1490 | memcpy(priv->ucode_data.v_addr, src, len); |
1491 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 1492 | src += len; |
b481de9c ZY |
1493 | |
1494 | /* Initialization instructions (3rd block) */ | |
1495 | if (init_size) { | |
cc0f555d | 1496 | len = init_size; |
e1623446 | 1497 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
90e759d1 | 1498 | len); |
b481de9c | 1499 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 1500 | src += len; |
b481de9c ZY |
1501 | } |
1502 | ||
1503 | /* Initialization data (4th block) */ | |
1504 | if (init_data_size) { | |
cc0f555d | 1505 | len = init_data_size; |
e1623446 | 1506 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
90e759d1 | 1507 | len); |
b481de9c | 1508 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 1509 | src += len; |
b481de9c ZY |
1510 | } |
1511 | ||
1512 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 1513 | len = boot_size; |
e1623446 | 1514 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
1515 | memcpy(priv->ucode_boot.v_addr, src, len); |
1516 | ||
1517 | /* We have our copies now, allow OS release its copies */ | |
1518 | release_firmware(ucode_raw); | |
1519 | return 0; | |
1520 | ||
1521 | err_pci_alloc: | |
15b1687c | 1522 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 1523 | ret = -ENOMEM; |
5b9f8cd3 | 1524 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
1525 | |
1526 | err_release: | |
1527 | release_firmware(ucode_raw); | |
1528 | ||
1529 | error: | |
90e759d1 | 1530 | return ret; |
b481de9c ZY |
1531 | } |
1532 | ||
b7a79404 RC |
1533 | #ifdef CONFIG_IWLWIFI_DEBUG |
1534 | static const char *desc_lookup_text[] = { | |
1535 | "OK", | |
1536 | "FAIL", | |
1537 | "BAD_PARAM", | |
1538 | "BAD_CHECKSUM", | |
1539 | "NMI_INTERRUPT_WDG", | |
1540 | "SYSASSERT", | |
1541 | "FATAL_ERROR", | |
1542 | "BAD_COMMAND", | |
1543 | "HW_ERROR_TUNE_LOCK", | |
1544 | "HW_ERROR_TEMPERATURE", | |
1545 | "ILLEGAL_CHAN_FREQ", | |
1546 | "VCC_NOT_STABLE", | |
1547 | "FH_ERROR", | |
1548 | "NMI_INTERRUPT_HOST", | |
1549 | "NMI_INTERRUPT_ACTION_PT", | |
1550 | "NMI_INTERRUPT_UNKNOWN", | |
1551 | "UCODE_VERSION_MISMATCH", | |
1552 | "HW_ERROR_ABS_LOCK", | |
1553 | "HW_ERROR_CAL_LOCK_FAIL", | |
1554 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1555 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1556 | "NMI_TRM_HW_ER", | |
1557 | "NMI_INTERRUPT_TRM", | |
1558 | "NMI_INTERRUPT_BREAK_POINT" | |
1559 | "DEBUG_0", | |
1560 | "DEBUG_1", | |
1561 | "DEBUG_2", | |
1562 | "DEBUG_3", | |
1563 | "UNKNOWN" | |
1564 | }; | |
1565 | ||
1566 | static const char *desc_lookup(int i) | |
1567 | { | |
1568 | int max = ARRAY_SIZE(desc_lookup_text) - 1; | |
1569 | ||
1570 | if (i < 0 || i > max) | |
1571 | i = max; | |
1572 | ||
1573 | return desc_lookup_text[i]; | |
1574 | } | |
1575 | ||
1576 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1577 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1578 | ||
1579 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1580 | { | |
1581 | u32 data2, line; | |
1582 | u32 desc, time, count, base, data1; | |
1583 | u32 blink1, blink2, ilink1, ilink2; | |
1584 | ||
1585 | if (priv->ucode_type == UCODE_INIT) | |
1586 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
1587 | else | |
1588 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1589 | ||
1590 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
1591 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); | |
1592 | return; | |
1593 | } | |
1594 | ||
1595 | count = iwl_read_targ_mem(priv, base); | |
1596 | ||
1597 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
1598 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
1599 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1600 | priv->status, count); | |
1601 | } | |
1602 | ||
1603 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
1604 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
1605 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
1606 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
1607 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
1608 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
1609 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
1610 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
1611 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
1612 | ||
1613 | IWL_ERR(priv, "Desc Time " | |
1614 | "data1 data2 line\n"); | |
1615 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", | |
1616 | desc_lookup(desc), desc, time, data1, data2, line); | |
1617 | IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n"); | |
1618 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
1619 | ilink1, ilink2); | |
1620 | ||
1621 | } | |
1622 | ||
1623 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
1624 | ||
1625 | /** | |
1626 | * iwl_print_event_log - Dump error event log to syslog | |
1627 | * | |
1628 | */ | |
1629 | static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | |
1630 | u32 num_events, u32 mode) | |
1631 | { | |
1632 | u32 i; | |
1633 | u32 base; /* SRAM byte address of event log header */ | |
1634 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1635 | u32 ptr; /* SRAM byte address of log data */ | |
1636 | u32 ev, time, data; /* event log data */ | |
1637 | ||
1638 | if (num_events == 0) | |
1639 | return; | |
1640 | if (priv->ucode_type == UCODE_INIT) | |
1641 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1642 | else | |
1643 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1644 | ||
1645 | if (mode == 0) | |
1646 | event_size = 2 * sizeof(u32); | |
1647 | else | |
1648 | event_size = 3 * sizeof(u32); | |
1649 | ||
1650 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1651 | ||
1652 | /* "time" is actually "data" for mode 0 (no timestamp). | |
1653 | * place event id # at far right for easier visual parsing. */ | |
1654 | for (i = 0; i < num_events; i++) { | |
1655 | ev = iwl_read_targ_mem(priv, ptr); | |
1656 | ptr += sizeof(u32); | |
1657 | time = iwl_read_targ_mem(priv, ptr); | |
1658 | ptr += sizeof(u32); | |
1659 | if (mode == 0) { | |
1660 | /* data, ev */ | |
1661 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev); | |
1662 | } else { | |
1663 | data = iwl_read_targ_mem(priv, ptr); | |
1664 | ptr += sizeof(u32); | |
1665 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
1666 | time, data, ev); | |
1667 | } | |
1668 | } | |
1669 | } | |
1670 | ||
1671 | void iwl_dump_nic_event_log(struct iwl_priv *priv) | |
1672 | { | |
1673 | u32 base; /* SRAM byte address of event log header */ | |
1674 | u32 capacity; /* event log capacity in # entries */ | |
1675 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1676 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1677 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1678 | u32 size; /* # entries that we'll print */ | |
1679 | ||
1680 | if (priv->ucode_type == UCODE_INIT) | |
1681 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1682 | else | |
1683 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1684 | ||
1685 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
1686 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); | |
1687 | return; | |
1688 | } | |
1689 | ||
1690 | /* event log header */ | |
1691 | capacity = iwl_read_targ_mem(priv, base); | |
1692 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1693 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1694 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
1695 | ||
1696 | size = num_wraps ? capacity : next_entry; | |
1697 | ||
1698 | /* bail out if nothing in log */ | |
1699 | if (size == 0) { | |
1700 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
1701 | return; | |
1702 | } | |
1703 | ||
1704 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", | |
1705 | size, num_wraps); | |
1706 | ||
1707 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
1708 | * i.e the next one that uCode would fill. */ | |
1709 | if (num_wraps) | |
1710 | iwl_print_event_log(priv, next_entry, | |
1711 | capacity - next_entry, mode); | |
1712 | /* (then/else) start at top of log */ | |
1713 | iwl_print_event_log(priv, 0, next_entry, mode); | |
1714 | ||
1715 | } | |
1716 | #endif | |
1717 | ||
b481de9c | 1718 | /** |
4a4a9e81 | 1719 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 1720 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 1721 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 1722 | */ |
4a4a9e81 | 1723 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 1724 | { |
57aab75a | 1725 | int ret = 0; |
b481de9c | 1726 | |
e1623446 | 1727 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
1728 | |
1729 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
1730 | /* We had an error bringing up the hardware, so take it | |
1731 | * all the way back down so we can try again */ | |
e1623446 | 1732 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
1733 | goto restart; |
1734 | } | |
1735 | ||
1736 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
1737 | * This is a paranoid check, because we would not have gotten the | |
1738 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 1739 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
1740 | /* Runtime instruction load was bad; |
1741 | * take it all the way back down so we can try again */ | |
e1623446 | 1742 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
1743 | goto restart; |
1744 | } | |
1745 | ||
c587de0b | 1746 | iwl_clear_stations_table(priv); |
57aab75a TW |
1747 | ret = priv->cfg->ops->lib->alive_notify(priv); |
1748 | if (ret) { | |
39aadf8c WT |
1749 | IWL_WARN(priv, |
1750 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
1751 | goto restart; |
1752 | } | |
1753 | ||
5b9f8cd3 | 1754 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
1755 | set_bit(STATUS_ALIVE, &priv->status); |
1756 | ||
fee1247a | 1757 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
1758 | return; |
1759 | ||
36d6825b | 1760 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
1761 | |
1762 | priv->active_rate = priv->rates_mask; | |
1763 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
1764 | ||
2f748dec WYG |
1765 | /* Configure Tx antenna selection based on H/W config */ |
1766 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
1767 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
1768 | ||
3109ece1 | 1769 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
1770 | struct iwl_rxon_cmd *active_rxon = |
1771 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
1772 | /* apply any changes in staging */ |
1773 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
1774 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
1775 | } else { | |
1776 | /* Initialize our rx_config data */ | |
5b9f8cd3 | 1777 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
45823531 AK |
1778 | |
1779 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
1780 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
1781 | ||
b481de9c ZY |
1782 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1783 | } | |
1784 | ||
9fbab516 | 1785 | /* Configure Bluetooth device coexistence support */ |
5b9f8cd3 | 1786 | iwl_send_bt_config(priv); |
b481de9c | 1787 | |
4a4a9e81 TW |
1788 | iwl_reset_run_time_calib(priv); |
1789 | ||
b481de9c | 1790 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 1791 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
1792 | |
1793 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 1794 | iwl_rf_kill_ct_config(priv); |
5a66926a | 1795 | |
fe00b5a5 RC |
1796 | iwl_leds_register(priv); |
1797 | ||
e1623446 | 1798 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 1799 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 1800 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 1801 | |
e312c24c | 1802 | iwl_power_update_mode(priv, true); |
c46fbefa | 1803 | |
ada17513 MA |
1804 | /* reassociate for ADHOC mode */ |
1805 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
1806 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
1807 | priv->vif); | |
1808 | if (beacon) | |
1809 | iwl_mac_beacon_update(priv->hw, beacon); | |
1810 | } | |
1811 | ||
1812 | ||
c46fbefa | 1813 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
5b9f8cd3 | 1814 | iwl_set_mode(priv, priv->iw_mode); |
c46fbefa | 1815 | |
b481de9c ZY |
1816 | return; |
1817 | ||
1818 | restart: | |
1819 | queue_work(priv->workqueue, &priv->restart); | |
1820 | } | |
1821 | ||
4e39317d | 1822 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 1823 | |
5b9f8cd3 | 1824 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1825 | { |
1826 | unsigned long flags; | |
1827 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 1828 | |
e1623446 | 1829 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 1830 | |
b481de9c ZY |
1831 | if (!exit_pending) |
1832 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
1833 | ||
ab53d8af MA |
1834 | iwl_leds_unregister(priv); |
1835 | ||
c587de0b | 1836 | iwl_clear_stations_table(priv); |
b481de9c ZY |
1837 | |
1838 | /* Unblock any waiting calls */ | |
1839 | wake_up_interruptible_all(&priv->wait_command_queue); | |
1840 | ||
b481de9c ZY |
1841 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
1842 | * exiting the module */ | |
1843 | if (!exit_pending) | |
1844 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
1845 | ||
1846 | /* stop and reset the on-board processor */ | |
3395f6e9 | 1847 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
1848 | |
1849 | /* tell the device to stop sending interrupts */ | |
0359facc | 1850 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 1851 | iwl_disable_interrupts(priv); |
0359facc MA |
1852 | spin_unlock_irqrestore(&priv->lock, flags); |
1853 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
1854 | |
1855 | if (priv->mac80211_registered) | |
1856 | ieee80211_stop_queues(priv->hw); | |
1857 | ||
5b9f8cd3 | 1858 | /* If we have not previously called iwl_init() then |
a60e77e5 | 1859 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 1860 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
1861 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1862 | STATUS_RF_KILL_HW | | |
9788864e RC |
1863 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1864 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
1865 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
1866 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
1867 | goto exit; |
1868 | } | |
1869 | ||
6da3a13e | 1870 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 1871 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
1872 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1873 | STATUS_RF_KILL_HW | | |
9788864e RC |
1874 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1875 | STATUS_GEO_CONFIGURED | | |
b481de9c | 1876 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
1877 | STATUS_FW_ERROR | |
1878 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
1879 | STATUS_EXIT_PENDING; | |
b481de9c | 1880 | |
ef850d7c MA |
1881 | /* device going down, Stop using ICT table */ |
1882 | iwl_disable_ict(priv); | |
b481de9c | 1883 | spin_lock_irqsave(&priv->lock, flags); |
3395f6e9 | 1884 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 1885 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
1886 | spin_unlock_irqrestore(&priv->lock, flags); |
1887 | ||
da1bc453 | 1888 | iwl_txq_ctx_stop(priv); |
b3bbacb7 | 1889 | iwl_rxq_stop(priv); |
b481de9c | 1890 | |
a8b50a0a MA |
1891 | iwl_write_prph(priv, APMG_CLK_DIS_REG, |
1892 | APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
1893 | |
1894 | udelay(5); | |
1895 | ||
7f066108 | 1896 | /* FIXME: apm_ops.suspend(priv) */ |
6da3a13e | 1897 | if (exit_pending) |
d535311e GG |
1898 | priv->cfg->ops->lib->apm_ops.stop(priv); |
1899 | else | |
1900 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
b481de9c | 1901 | exit: |
885ba202 | 1902 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
1903 | |
1904 | if (priv->ibss_beacon) | |
1905 | dev_kfree_skb(priv->ibss_beacon); | |
1906 | priv->ibss_beacon = NULL; | |
1907 | ||
1908 | /* clear out any free frames */ | |
fcab423d | 1909 | iwl_clear_free_frames(priv); |
b481de9c ZY |
1910 | } |
1911 | ||
5b9f8cd3 | 1912 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1913 | { |
1914 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1915 | __iwl_down(priv); |
b481de9c | 1916 | mutex_unlock(&priv->mutex); |
b24d22b1 | 1917 | |
4e39317d | 1918 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
1919 | } |
1920 | ||
086ed117 MA |
1921 | #define HW_READY_TIMEOUT (50) |
1922 | ||
1923 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
1924 | { | |
1925 | int ret = 0; | |
1926 | ||
1927 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1928 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
1929 | ||
1930 | /* See if we got it */ | |
1931 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1932 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1933 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1934 | HW_READY_TIMEOUT); | |
1935 | if (ret != -ETIMEDOUT) | |
1936 | priv->hw_ready = true; | |
1937 | else | |
1938 | priv->hw_ready = false; | |
1939 | ||
1940 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
1941 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
1942 | return ret; | |
1943 | } | |
1944 | ||
1945 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
1946 | { | |
1947 | int ret = 0; | |
1948 | ||
1949 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n"); | |
1950 | ||
3354a0f6 MA |
1951 | ret = iwl_set_hw_ready(priv); |
1952 | if (priv->hw_ready) | |
1953 | return ret; | |
1954 | ||
1955 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
1956 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
1957 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
1958 | ||
1959 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1960 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
1961 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
1962 | ||
3354a0f6 | 1963 | /* HW should be ready by now, check again. */ |
086ed117 MA |
1964 | if (ret != -ETIMEDOUT) |
1965 | iwl_set_hw_ready(priv); | |
1966 | ||
1967 | return ret; | |
1968 | } | |
1969 | ||
b481de9c ZY |
1970 | #define MAX_HW_RESTARTS 5 |
1971 | ||
5b9f8cd3 | 1972 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 1973 | { |
57aab75a TW |
1974 | int i; |
1975 | int ret; | |
b481de9c ZY |
1976 | |
1977 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 1978 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
1979 | return -EIO; |
1980 | } | |
1981 | ||
e903fbd4 | 1982 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 1983 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
1984 | return -EIO; |
1985 | } | |
1986 | ||
086ed117 MA |
1987 | iwl_prepare_card_hw(priv); |
1988 | ||
1989 | if (!priv->hw_ready) { | |
1990 | IWL_WARN(priv, "Exit HW not ready\n"); | |
1991 | return -EIO; | |
1992 | } | |
1993 | ||
e655b9f0 | 1994 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 1995 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 1996 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1997 | else |
e655b9f0 | 1998 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1999 | |
c1842d61 | 2000 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
2001 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
2002 | ||
5b9f8cd3 | 2003 | iwl_enable_interrupts(priv); |
a60e77e5 | 2004 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 2005 | return 0; |
b481de9c ZY |
2006 | } |
2007 | ||
3395f6e9 | 2008 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2009 | |
1053d35f | 2010 | ret = iwl_hw_nic_init(priv); |
57aab75a | 2011 | if (ret) { |
15b1687c | 2012 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 2013 | return ret; |
b481de9c ZY |
2014 | } |
2015 | ||
2016 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2017 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2018 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2019 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2020 | ||
2021 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 2022 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 2023 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2024 | |
2025 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2026 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2027 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2028 | |
2029 | /* Copy original ucode data image from disk into backup cache. | |
2030 | * This will be used to initialize the on-board processor's | |
2031 | * data SRAM for a clean start when the runtime program first loads. */ | |
2032 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2033 | priv->ucode_data.len); |
b481de9c | 2034 | |
b481de9c ZY |
2035 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2036 | ||
c587de0b | 2037 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2038 | |
2039 | /* load bootstrap state machine, | |
2040 | * load bootstrap program into processor's memory, | |
2041 | * prepare to load the "initialize" uCode */ | |
57aab75a | 2042 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 2043 | |
57aab75a | 2044 | if (ret) { |
15b1687c WT |
2045 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
2046 | ret); | |
b481de9c ZY |
2047 | continue; |
2048 | } | |
2049 | ||
2050 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 2051 | iwl_nic_start(priv); |
b481de9c | 2052 | |
e1623446 | 2053 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2054 | |
2055 | return 0; | |
2056 | } | |
2057 | ||
2058 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 2059 | __iwl_down(priv); |
64e72c3e | 2060 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2061 | |
2062 | /* tried to restart and config the device for as long as our | |
2063 | * patience could withstand */ | |
15b1687c | 2064 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2065 | return -EIO; |
2066 | } | |
2067 | ||
2068 | ||
2069 | /***************************************************************************** | |
2070 | * | |
2071 | * Workqueue callbacks | |
2072 | * | |
2073 | *****************************************************************************/ | |
2074 | ||
4a4a9e81 | 2075 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2076 | { |
c79dd5b5 TW |
2077 | struct iwl_priv *priv = |
2078 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2079 | |
2080 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2081 | return; | |
2082 | ||
2083 | mutex_lock(&priv->mutex); | |
f3ccc08c | 2084 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
2085 | mutex_unlock(&priv->mutex); |
2086 | } | |
2087 | ||
4a4a9e81 | 2088 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 2089 | { |
c79dd5b5 TW |
2090 | struct iwl_priv *priv = |
2091 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2092 | |
2093 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2094 | return; | |
2095 | ||
258c44a0 MA |
2096 | /* enable dram interrupt */ |
2097 | iwl_reset_ict(priv); | |
2098 | ||
b481de9c | 2099 | mutex_lock(&priv->mutex); |
4a4a9e81 | 2100 | iwl_alive_start(priv); |
b481de9c ZY |
2101 | mutex_unlock(&priv->mutex); |
2102 | } | |
2103 | ||
16e727e8 EG |
2104 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2105 | { | |
2106 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
2107 | run_time_calib_work); | |
2108 | ||
2109 | mutex_lock(&priv->mutex); | |
2110 | ||
2111 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
2112 | test_bit(STATUS_SCANNING, &priv->status)) { | |
2113 | mutex_unlock(&priv->mutex); | |
2114 | return; | |
2115 | } | |
2116 | ||
2117 | if (priv->start_calib) { | |
2118 | iwl_chain_noise_calibration(priv, &priv->statistics); | |
2119 | ||
2120 | iwl_sensitivity_calibration(priv, &priv->statistics); | |
2121 | } | |
2122 | ||
2123 | mutex_unlock(&priv->mutex); | |
2124 | return; | |
2125 | } | |
2126 | ||
5b9f8cd3 | 2127 | static void iwl_bg_up(struct work_struct *data) |
b481de9c | 2128 | { |
c79dd5b5 | 2129 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
2130 | |
2131 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2132 | return; | |
2133 | ||
2134 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2135 | __iwl_up(priv); |
b481de9c ZY |
2136 | mutex_unlock(&priv->mutex); |
2137 | } | |
2138 | ||
5b9f8cd3 | 2139 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2140 | { |
c79dd5b5 | 2141 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2142 | |
2143 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2144 | return; | |
2145 | ||
19cc1087 JB |
2146 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2147 | mutex_lock(&priv->mutex); | |
2148 | priv->vif = NULL; | |
2149 | priv->is_open = 0; | |
2150 | mutex_unlock(&priv->mutex); | |
2151 | iwl_down(priv); | |
2152 | ieee80211_restart_hw(priv->hw); | |
2153 | } else { | |
2154 | iwl_down(priv); | |
2155 | queue_work(priv->workqueue, &priv->up); | |
2156 | } | |
b481de9c ZY |
2157 | } |
2158 | ||
5b9f8cd3 | 2159 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2160 | { |
c79dd5b5 TW |
2161 | struct iwl_priv *priv = |
2162 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2163 | |
2164 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2165 | return; | |
2166 | ||
2167 | mutex_lock(&priv->mutex); | |
a55360e4 | 2168 | iwl_rx_replenish(priv); |
b481de9c ZY |
2169 | mutex_unlock(&priv->mutex); |
2170 | } | |
2171 | ||
7878a5a4 MA |
2172 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
2173 | ||
5bbe233b | 2174 | void iwl_post_associate(struct iwl_priv *priv) |
b481de9c | 2175 | { |
b481de9c | 2176 | struct ieee80211_conf *conf = NULL; |
857485c0 | 2177 | int ret = 0; |
1ff50bda | 2178 | unsigned long flags; |
b481de9c | 2179 | |
05c914fe | 2180 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 2181 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
2182 | return; |
2183 | } | |
2184 | ||
e1623446 | 2185 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
e174961c | 2186 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
2187 | |
2188 | ||
2189 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2190 | return; | |
2191 | ||
b481de9c | 2192 | |
508e32e1 | 2193 | if (!priv->vif || !priv->is_open) |
948c171c | 2194 | return; |
508e32e1 | 2195 | |
2a421b91 | 2196 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 2197 | |
b481de9c ZY |
2198 | conf = ieee80211_get_hw_conf(priv->hw); |
2199 | ||
2200 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2201 | iwlcore_commit_rxon(priv); |
b481de9c | 2202 | |
3195c1f3 | 2203 | iwl_setup_rxon_timing(priv); |
857485c0 | 2204 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2205 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2206 | if (ret) |
39aadf8c | 2207 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2208 | "Attempting to continue.\n"); |
2209 | ||
2210 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2211 | ||
42eb7c64 | 2212 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 2213 | |
45823531 AK |
2214 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2215 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2216 | ||
b481de9c ZY |
2217 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
2218 | ||
e1623446 | 2219 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
2220 | priv->assoc_id, priv->beacon_int); |
2221 | ||
2222 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2223 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2224 | else | |
2225 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2226 | ||
2227 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2228 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2229 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2230 | else | |
2231 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2232 | ||
05c914fe | 2233 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2234 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
2235 | ||
2236 | } | |
2237 | ||
e0158e61 | 2238 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2239 | |
2240 | switch (priv->iw_mode) { | |
05c914fe | 2241 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2242 | break; |
2243 | ||
05c914fe | 2244 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 2245 | |
c46fbefa AK |
2246 | /* assume default assoc id */ |
2247 | priv->assoc_id = 1; | |
b481de9c | 2248 | |
4f40e4d9 | 2249 | iwl_rxon_add_station(priv, priv->bssid, 0); |
5b9f8cd3 | 2250 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2251 | |
2252 | break; | |
2253 | ||
2254 | default: | |
15b1687c | 2255 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 2256 | __func__, priv->iw_mode); |
b481de9c ZY |
2257 | break; |
2258 | } | |
2259 | ||
05c914fe | 2260 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2261 | priv->assoc_station_added = 1; |
2262 | ||
1ff50bda EG |
2263 | spin_lock_irqsave(&priv->lock, flags); |
2264 | iwl_activate_qos(priv, 0); | |
2265 | spin_unlock_irqrestore(&priv->lock, flags); | |
292ae174 | 2266 | |
04816448 GE |
2267 | /* the chain noise calibration will enabled PM upon completion |
2268 | * If chain noise has already been run, then we need to enable | |
2269 | * power management here */ | |
2270 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
e312c24c | 2271 | iwl_power_update_mode(priv, false); |
c90a74ba EG |
2272 | |
2273 | /* Enable Rx differential gain and sensitivity calibrations */ | |
2274 | iwl_chain_noise_reset(priv); | |
2275 | priv->start_calib = 1; | |
2276 | ||
508e32e1 RC |
2277 | } |
2278 | ||
b481de9c ZY |
2279 | /***************************************************************************** |
2280 | * | |
2281 | * mac80211 entry point functions | |
2282 | * | |
2283 | *****************************************************************************/ | |
2284 | ||
154b25ce | 2285 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2286 | |
5b9f8cd3 | 2287 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2288 | { |
c79dd5b5 | 2289 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2290 | int ret; |
b481de9c | 2291 | |
e1623446 | 2292 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2293 | |
2294 | /* we should be verifying the device is ready to be opened */ | |
2295 | mutex_lock(&priv->mutex); | |
2296 | ||
5a66926a ZY |
2297 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
2298 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 2299 | |
5a66926a | 2300 | if (!priv->ucode_code.len) { |
5b9f8cd3 | 2301 | ret = iwl_read_ucode(priv); |
5a66926a | 2302 | if (ret) { |
15b1687c | 2303 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a | 2304 | mutex_unlock(&priv->mutex); |
6cd0b1cb | 2305 | return ret; |
5a66926a ZY |
2306 | } |
2307 | } | |
b481de9c | 2308 | |
5b9f8cd3 | 2309 | ret = __iwl_up(priv); |
5a66926a | 2310 | |
b481de9c | 2311 | mutex_unlock(&priv->mutex); |
5a66926a | 2312 | |
e655b9f0 | 2313 | if (ret) |
6cd0b1cb | 2314 | return ret; |
e655b9f0 | 2315 | |
c1842d61 TW |
2316 | if (iwl_is_rfkill(priv)) |
2317 | goto out; | |
2318 | ||
e1623446 | 2319 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2320 | |
fe9b6b72 | 2321 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2322 | * mac80211 will not be run successfully. */ |
154b25ce EG |
2323 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
2324 | test_bit(STATUS_READY, &priv->status), | |
2325 | UCODE_READY_TIMEOUT); | |
2326 | if (!ret) { | |
2327 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 2328 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 2329 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 2330 | return -ETIMEDOUT; |
5a66926a | 2331 | } |
fe9b6b72 | 2332 | } |
0a078ffa | 2333 | |
c1842d61 | 2334 | out: |
0a078ffa | 2335 | priv->is_open = 1; |
e1623446 | 2336 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2337 | return 0; |
2338 | } | |
2339 | ||
5b9f8cd3 | 2340 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2341 | { |
c79dd5b5 | 2342 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2343 | |
e1623446 | 2344 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2345 | |
19cc1087 | 2346 | if (!priv->is_open) |
e655b9f0 | 2347 | return; |
e655b9f0 | 2348 | |
b481de9c | 2349 | priv->is_open = 0; |
5a66926a | 2350 | |
5bddf549 | 2351 | if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) { |
e655b9f0 ZY |
2352 | /* stop mac, cancel any scan request and clear |
2353 | * RXON_FILTER_ASSOC_MSK BIT | |
2354 | */ | |
5a66926a | 2355 | mutex_lock(&priv->mutex); |
2a421b91 | 2356 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2357 | mutex_unlock(&priv->mutex); |
fde3571f MA |
2358 | } |
2359 | ||
5b9f8cd3 | 2360 | iwl_down(priv); |
5a66926a ZY |
2361 | |
2362 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
2363 | |
2364 | /* enable interrupts again in order to receive rfkill changes */ | |
2365 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
2366 | iwl_enable_interrupts(priv); | |
948c171c | 2367 | |
e1623446 | 2368 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2369 | } |
2370 | ||
5b9f8cd3 | 2371 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2372 | { |
c79dd5b5 | 2373 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2374 | |
e1623446 | 2375 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2376 | |
e1623446 | 2377 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2378 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2379 | |
e039fa4a | 2380 | if (iwl_tx_skb(priv, skb)) |
b481de9c ZY |
2381 | dev_kfree_skb_any(skb); |
2382 | ||
e1623446 | 2383 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 2384 | return NETDEV_TX_OK; |
b481de9c ZY |
2385 | } |
2386 | ||
60690a6a | 2387 | void iwl_config_ap(struct iwl_priv *priv) |
b481de9c | 2388 | { |
857485c0 | 2389 | int ret = 0; |
1ff50bda | 2390 | unsigned long flags; |
b481de9c | 2391 | |
d986bcd1 | 2392 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
2393 | return; |
2394 | ||
2395 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 2396 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
2397 | |
2398 | /* RXON - unassoc (to set timing command) */ | |
2399 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2400 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2401 | |
2402 | /* RXON Timing */ | |
3195c1f3 | 2403 | iwl_setup_rxon_timing(priv); |
857485c0 | 2404 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2405 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2406 | if (ret) |
39aadf8c | 2407 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2408 | "Attempting to continue.\n"); |
2409 | ||
45823531 AK |
2410 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2411 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c ZY |
2412 | |
2413 | /* FIXME: what should be the assoc_id for AP? */ | |
2414 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
2415 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2416 | priv->staging_rxon.flags |= | |
2417 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2418 | else | |
2419 | priv->staging_rxon.flags &= | |
2420 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2421 | ||
2422 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2423 | if (priv->assoc_capability & | |
2424 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2425 | priv->staging_rxon.flags |= | |
2426 | RXON_FLG_SHORT_SLOT_MSK; | |
2427 | else | |
2428 | priv->staging_rxon.flags &= | |
2429 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2430 | ||
05c914fe | 2431 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2432 | priv->staging_rxon.flags &= |
2433 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2434 | } | |
2435 | /* restore RXON assoc */ | |
2436 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2437 | iwlcore_commit_rxon(priv); |
1ff50bda EG |
2438 | spin_lock_irqsave(&priv->lock, flags); |
2439 | iwl_activate_qos(priv, 1); | |
2440 | spin_unlock_irqrestore(&priv->lock, flags); | |
4f40e4d9 | 2441 | iwl_rxon_add_station(priv, iwl_bcast_addr, 0); |
e1493deb | 2442 | } |
5b9f8cd3 | 2443 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2444 | |
2445 | /* FIXME - we need to add code here to detect a totally new | |
2446 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
2447 | * clear sta table, add BCAST sta... */ | |
2448 | } | |
2449 | ||
5b9f8cd3 | 2450 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
ab885f8c EG |
2451 | struct ieee80211_key_conf *keyconf, const u8 *addr, |
2452 | u32 iv32, u16 *phase1key) | |
2453 | { | |
ab885f8c | 2454 | |
9f58671e | 2455 | struct iwl_priv *priv = hw->priv; |
e1623446 | 2456 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2457 | |
9f58671e | 2458 | iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key); |
ab885f8c | 2459 | |
e1623446 | 2460 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2461 | } |
2462 | ||
5b9f8cd3 | 2463 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
2464 | struct ieee80211_vif *vif, |
2465 | struct ieee80211_sta *sta, | |
b481de9c ZY |
2466 | struct ieee80211_key_conf *key) |
2467 | { | |
c79dd5b5 | 2468 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
2469 | const u8 *addr; |
2470 | int ret; | |
2471 | u8 sta_id; | |
2472 | bool is_default_wep_key = false; | |
b481de9c | 2473 | |
e1623446 | 2474 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2475 | |
90e8e424 | 2476 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 2477 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2478 | return -EOPNOTSUPP; |
2479 | } | |
42986796 | 2480 | addr = sta ? sta->addr : iwl_bcast_addr; |
c587de0b | 2481 | sta_id = iwl_find_station(priv, addr); |
6974e363 | 2482 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 2483 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
e174961c | 2484 | addr); |
6974e363 | 2485 | return -EINVAL; |
b481de9c | 2486 | |
deb09c43 | 2487 | } |
b481de9c | 2488 | |
6974e363 | 2489 | mutex_lock(&priv->mutex); |
2a421b91 | 2490 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 EG |
2491 | mutex_unlock(&priv->mutex); |
2492 | ||
2493 | /* If we are getting WEP group key and we didn't receive any key mapping | |
2494 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2495 | * in 1X mode. | |
2496 | * In legacy wep mode, we use another host command to the uCode */ | |
5425e490 | 2497 | if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id && |
05c914fe | 2498 | priv->iw_mode != NL80211_IFTYPE_AP) { |
6974e363 EG |
2499 | if (cmd == SET_KEY) |
2500 | is_default_wep_key = !priv->key_mapping_key; | |
2501 | else | |
ccc038ab EG |
2502 | is_default_wep_key = |
2503 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2504 | } |
052c4b9f | 2505 | |
b481de9c | 2506 | switch (cmd) { |
deb09c43 | 2507 | case SET_KEY: |
6974e363 EG |
2508 | if (is_default_wep_key) |
2509 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 2510 | else |
7480513f | 2511 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 2512 | |
e1623446 | 2513 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2514 | break; |
2515 | case DISABLE_KEY: | |
6974e363 EG |
2516 | if (is_default_wep_key) |
2517 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 2518 | else |
3ec47732 | 2519 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 2520 | |
e1623446 | 2521 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2522 | break; |
2523 | default: | |
deb09c43 | 2524 | ret = -EINVAL; |
b481de9c ZY |
2525 | } |
2526 | ||
e1623446 | 2527 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2528 | |
deb09c43 | 2529 | return ret; |
b481de9c ZY |
2530 | } |
2531 | ||
5b9f8cd3 | 2532 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
d783b061 | 2533 | enum ieee80211_ampdu_mlme_action action, |
17741cdc | 2534 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
d783b061 TW |
2535 | { |
2536 | struct iwl_priv *priv = hw->priv; | |
5c2207c6 | 2537 | int ret; |
d783b061 | 2538 | |
e1623446 | 2539 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2540 | sta->addr, tid); |
d783b061 TW |
2541 | |
2542 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2543 | return -EACCES; | |
2544 | ||
2545 | switch (action) { | |
2546 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2547 | IWL_DEBUG_HT(priv, "start Rx\n"); |
9f58671e | 2548 | return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn); |
d783b061 | 2549 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2550 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
5c2207c6 WYG |
2551 | ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid); |
2552 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2553 | return 0; | |
2554 | else | |
2555 | return ret; | |
d783b061 | 2556 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2557 | IWL_DEBUG_HT(priv, "start Tx\n"); |
17741cdc | 2558 | return iwl_tx_agg_start(priv, sta->addr, tid, ssn); |
d783b061 | 2559 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2560 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
5c2207c6 WYG |
2561 | ret = iwl_tx_agg_stop(priv, sta->addr, tid); |
2562 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2563 | return 0; | |
2564 | else | |
2565 | return ret; | |
d783b061 | 2566 | default: |
e1623446 | 2567 | IWL_DEBUG_HT(priv, "unknown\n"); |
d783b061 TW |
2568 | return -EINVAL; |
2569 | break; | |
2570 | } | |
2571 | return 0; | |
2572 | } | |
9f58671e | 2573 | |
5b9f8cd3 | 2574 | static int iwl_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2575 | struct ieee80211_low_level_stats *stats) |
2576 | { | |
bf403db8 EK |
2577 | struct iwl_priv *priv = hw->priv; |
2578 | ||
2579 | priv = hw->priv; | |
e1623446 TW |
2580 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
2581 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
b481de9c ZY |
2582 | |
2583 | return 0; | |
2584 | } | |
2585 | ||
b481de9c ZY |
2586 | /***************************************************************************** |
2587 | * | |
2588 | * sysfs attributes | |
2589 | * | |
2590 | *****************************************************************************/ | |
2591 | ||
0a6857e7 | 2592 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2593 | |
2594 | /* | |
2595 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 2596 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
2597 | * used for controlling the debug level. |
2598 | * | |
2599 | * See the level definitions in iwl for details. | |
a562a9dd | 2600 | * |
3d816c77 RC |
2601 | * The debug_level being managed using sysfs below is a per device debug |
2602 | * level that is used instead of the global debug level if it (the per | |
2603 | * device debug level) is set. | |
b481de9c | 2604 | */ |
8cf769c6 EK |
2605 | static ssize_t show_debug_level(struct device *d, |
2606 | struct device_attribute *attr, char *buf) | |
b481de9c | 2607 | { |
3d816c77 RC |
2608 | struct iwl_priv *priv = dev_get_drvdata(d); |
2609 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 2610 | } |
8cf769c6 EK |
2611 | static ssize_t store_debug_level(struct device *d, |
2612 | struct device_attribute *attr, | |
b481de9c ZY |
2613 | const char *buf, size_t count) |
2614 | { | |
928841b1 | 2615 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2616 | unsigned long val; |
2617 | int ret; | |
b481de9c | 2618 | |
9257746f TW |
2619 | ret = strict_strtoul(buf, 0, &val); |
2620 | if (ret) | |
978785a3 | 2621 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 2622 | else { |
3d816c77 | 2623 | priv->debug_level = val; |
20594eb0 WYG |
2624 | if (iwl_alloc_traffic_mem(priv)) |
2625 | IWL_ERR(priv, | |
2626 | "Not enough memory to generate traffic log\n"); | |
2627 | } | |
b481de9c ZY |
2628 | return strnlen(buf, count); |
2629 | } | |
2630 | ||
8cf769c6 EK |
2631 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
2632 | show_debug_level, store_debug_level); | |
2633 | ||
b481de9c | 2634 | |
0a6857e7 | 2635 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 2636 | |
b481de9c ZY |
2637 | |
2638 | static ssize_t show_temperature(struct device *d, | |
2639 | struct device_attribute *attr, char *buf) | |
2640 | { | |
928841b1 | 2641 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 2642 | |
fee1247a | 2643 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2644 | return -EAGAIN; |
2645 | ||
91dbc5bd | 2646 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
2647 | } |
2648 | ||
2649 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
2650 | ||
b481de9c ZY |
2651 | static ssize_t show_tx_power(struct device *d, |
2652 | struct device_attribute *attr, char *buf) | |
2653 | { | |
928841b1 | 2654 | struct iwl_priv *priv = dev_get_drvdata(d); |
91f39e8e JS |
2655 | |
2656 | if (!iwl_is_ready_rf(priv)) | |
2657 | return sprintf(buf, "off\n"); | |
2658 | else | |
2659 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
2660 | } |
2661 | ||
2662 | static ssize_t store_tx_power(struct device *d, | |
2663 | struct device_attribute *attr, | |
2664 | const char *buf, size_t count) | |
2665 | { | |
928841b1 | 2666 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2667 | unsigned long val; |
2668 | int ret; | |
b481de9c | 2669 | |
9257746f TW |
2670 | ret = strict_strtoul(buf, 10, &val); |
2671 | if (ret) | |
978785a3 | 2672 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
5eadd94b WYG |
2673 | else { |
2674 | ret = iwl_set_tx_power(priv, val, false); | |
2675 | if (ret) | |
2676 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
2677 | ret); | |
2678 | else | |
2679 | ret = count; | |
2680 | } | |
2681 | return ret; | |
b481de9c ZY |
2682 | } |
2683 | ||
2684 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
2685 | ||
2686 | static ssize_t show_flags(struct device *d, | |
2687 | struct device_attribute *attr, char *buf) | |
2688 | { | |
928841b1 | 2689 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
2690 | |
2691 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
2692 | } | |
2693 | ||
2694 | static ssize_t store_flags(struct device *d, | |
2695 | struct device_attribute *attr, | |
2696 | const char *buf, size_t count) | |
2697 | { | |
928841b1 | 2698 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2699 | unsigned long val; |
2700 | u32 flags; | |
2701 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2702 | if (ret) |
9257746f TW |
2703 | return ret; |
2704 | flags = (u32)val; | |
b481de9c ZY |
2705 | |
2706 | mutex_lock(&priv->mutex); | |
2707 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
2708 | /* Cancel any currently running scans... */ | |
2a421b91 | 2709 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2710 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2711 | else { |
e1623446 | 2712 | IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags); |
b481de9c | 2713 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 2714 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2715 | } |
2716 | } | |
2717 | mutex_unlock(&priv->mutex); | |
2718 | ||
2719 | return count; | |
2720 | } | |
2721 | ||
2722 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
2723 | ||
2724 | static ssize_t show_filter_flags(struct device *d, | |
2725 | struct device_attribute *attr, char *buf) | |
2726 | { | |
928841b1 | 2727 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
2728 | |
2729 | return sprintf(buf, "0x%04X\n", | |
2730 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
2731 | } | |
2732 | ||
2733 | static ssize_t store_filter_flags(struct device *d, | |
2734 | struct device_attribute *attr, | |
2735 | const char *buf, size_t count) | |
2736 | { | |
928841b1 | 2737 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2738 | unsigned long val; |
2739 | u32 filter_flags; | |
2740 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2741 | if (ret) |
9257746f TW |
2742 | return ret; |
2743 | filter_flags = (u32)val; | |
b481de9c ZY |
2744 | |
2745 | mutex_lock(&priv->mutex); | |
2746 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
2747 | /* Cancel any currently running scans... */ | |
2a421b91 | 2748 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2749 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2750 | else { |
e1623446 | 2751 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c ZY |
2752 | "0x%04X\n", filter_flags); |
2753 | priv->staging_rxon.filter_flags = | |
2754 | cpu_to_le32(filter_flags); | |
e0158e61 | 2755 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2756 | } |
2757 | } | |
2758 | mutex_unlock(&priv->mutex); | |
2759 | ||
2760 | return count; | |
2761 | } | |
2762 | ||
2763 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
2764 | store_filter_flags); | |
2765 | ||
b481de9c ZY |
2766 | |
2767 | static ssize_t show_statistics(struct device *d, | |
2768 | struct device_attribute *attr, char *buf) | |
2769 | { | |
c79dd5b5 | 2770 | struct iwl_priv *priv = dev_get_drvdata(d); |
8f91aecb | 2771 | u32 size = sizeof(struct iwl_notif_statistics); |
b481de9c | 2772 | u32 len = 0, ofs = 0; |
3ac7f146 | 2773 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
2774 | int rc = 0; |
2775 | ||
fee1247a | 2776 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2777 | return -EAGAIN; |
2778 | ||
2779 | mutex_lock(&priv->mutex); | |
49ea8596 | 2780 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
2781 | mutex_unlock(&priv->mutex); |
2782 | ||
2783 | if (rc) { | |
2784 | len = sprintf(buf, | |
2785 | "Error sending statistics request: 0x%08X\n", rc); | |
2786 | return len; | |
2787 | } | |
2788 | ||
2789 | while (size && (PAGE_SIZE - len)) { | |
2790 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
2791 | PAGE_SIZE - len, 1); | |
2792 | len = strlen(buf); | |
2793 | if (PAGE_SIZE - len) | |
2794 | buf[len++] = '\n'; | |
2795 | ||
2796 | ofs += 16; | |
2797 | size -= min(size, 16U); | |
2798 | } | |
2799 | ||
2800 | return len; | |
2801 | } | |
2802 | ||
2803 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
2804 | ||
01abfbb2 WYG |
2805 | static ssize_t show_rts_ht_protection(struct device *d, |
2806 | struct device_attribute *attr, char *buf) | |
2807 | { | |
2808 | struct iwl_priv *priv = dev_get_drvdata(d); | |
2809 | ||
2810 | return sprintf(buf, "%s\n", | |
2811 | priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self"); | |
2812 | } | |
2813 | ||
2814 | static ssize_t store_rts_ht_protection(struct device *d, | |
2815 | struct device_attribute *attr, | |
2816 | const char *buf, size_t count) | |
2817 | { | |
2818 | struct iwl_priv *priv = dev_get_drvdata(d); | |
2819 | unsigned long val; | |
2820 | int ret; | |
2821 | ||
2822 | ret = strict_strtoul(buf, 10, &val); | |
2823 | if (ret) | |
2824 | IWL_INFO(priv, "Input is not in decimal form.\n"); | |
2825 | else { | |
2826 | if (!iwl_is_associated(priv)) | |
2827 | priv->cfg->use_rts_for_ht = val ? true : false; | |
2828 | else | |
2829 | IWL_ERR(priv, "Sta associated with AP - " | |
2830 | "Change protection mechanism is not allowed\n"); | |
2831 | ret = count; | |
2832 | } | |
2833 | return ret; | |
2834 | } | |
2835 | ||
2836 | static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO, | |
2837 | show_rts_ht_protection, store_rts_ht_protection); | |
2838 | ||
b481de9c | 2839 | |
b481de9c ZY |
2840 | /***************************************************************************** |
2841 | * | |
2842 | * driver setup and teardown | |
2843 | * | |
2844 | *****************************************************************************/ | |
2845 | ||
4e39317d | 2846 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 2847 | { |
d21050c7 | 2848 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
2849 | |
2850 | init_waitqueue_head(&priv->wait_command_queue); | |
2851 | ||
5b9f8cd3 EG |
2852 | INIT_WORK(&priv->up, iwl_bg_up); |
2853 | INIT_WORK(&priv->restart, iwl_bg_restart); | |
2854 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 2855 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 2856 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
2857 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
2858 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 2859 | |
2a421b91 | 2860 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 2861 | |
4e39317d EG |
2862 | if (priv->cfg->ops->lib->setup_deferred_work) |
2863 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
2864 | ||
2865 | init_timer(&priv->statistics_periodic); | |
2866 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 2867 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 2868 | |
ef850d7c MA |
2869 | if (!priv->cfg->use_isr_legacy) |
2870 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
2871 | iwl_irq_tasklet, (unsigned long)priv); | |
2872 | else | |
2873 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
2874 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
2875 | } |
2876 | ||
4e39317d | 2877 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 2878 | { |
4e39317d EG |
2879 | if (priv->cfg->ops->lib->cancel_deferred_work) |
2880 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 2881 | |
3ae6a054 | 2882 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
2883 | cancel_delayed_work(&priv->scan_check); |
2884 | cancel_delayed_work(&priv->alive_start); | |
b481de9c | 2885 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 2886 | del_timer_sync(&priv->statistics_periodic); |
b481de9c ZY |
2887 | } |
2888 | ||
5b9f8cd3 | 2889 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c ZY |
2890 | &dev_attr_flags.attr, |
2891 | &dev_attr_filter_flags.attr, | |
b481de9c | 2892 | &dev_attr_statistics.attr, |
b481de9c | 2893 | &dev_attr_temperature.attr, |
b481de9c | 2894 | &dev_attr_tx_power.attr, |
01abfbb2 | 2895 | &dev_attr_rts_ht_protection.attr, |
8cf769c6 EK |
2896 | #ifdef CONFIG_IWLWIFI_DEBUG |
2897 | &dev_attr_debug_level.attr, | |
2898 | #endif | |
b481de9c ZY |
2899 | NULL |
2900 | }; | |
2901 | ||
5b9f8cd3 | 2902 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 2903 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 2904 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
2905 | }; |
2906 | ||
5b9f8cd3 EG |
2907 | static struct ieee80211_ops iwl_hw_ops = { |
2908 | .tx = iwl_mac_tx, | |
2909 | .start = iwl_mac_start, | |
2910 | .stop = iwl_mac_stop, | |
2911 | .add_interface = iwl_mac_add_interface, | |
2912 | .remove_interface = iwl_mac_remove_interface, | |
2913 | .config = iwl_mac_config, | |
5b9f8cd3 EG |
2914 | .configure_filter = iwl_configure_filter, |
2915 | .set_key = iwl_mac_set_key, | |
2916 | .update_tkip_key = iwl_mac_update_tkip_key, | |
2917 | .get_stats = iwl_mac_get_stats, | |
2918 | .get_tx_stats = iwl_mac_get_tx_stats, | |
2919 | .conf_tx = iwl_mac_conf_tx, | |
2920 | .reset_tsf = iwl_mac_reset_tsf, | |
2921 | .bss_info_changed = iwl_bss_info_changed, | |
2922 | .ampdu_action = iwl_mac_ampdu_action, | |
cb43dc25 | 2923 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
2924 | }; |
2925 | ||
5b9f8cd3 | 2926 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
2927 | { |
2928 | int err = 0; | |
c79dd5b5 | 2929 | struct iwl_priv *priv; |
b481de9c | 2930 | struct ieee80211_hw *hw; |
82b9a121 | 2931 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 2932 | unsigned long flags; |
6cd0b1cb | 2933 | u16 pci_cmd; |
b481de9c | 2934 | |
316c30d9 AK |
2935 | /************************ |
2936 | * 1. Allocating HW data | |
2937 | ************************/ | |
2938 | ||
6440adb5 BC |
2939 | /* Disabling hardware scan means that mac80211 will perform scans |
2940 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 2941 | if (cfg->mod_params->disable_hw_scan) { |
a562a9dd | 2942 | if (iwl_debug_level & IWL_DL_INFO) |
bf403db8 EK |
2943 | dev_printk(KERN_DEBUG, &(pdev->dev), |
2944 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 2945 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
2946 | } |
2947 | ||
5b9f8cd3 | 2948 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 2949 | if (!hw) { |
b481de9c ZY |
2950 | err = -ENOMEM; |
2951 | goto out; | |
2952 | } | |
1d0a082d AK |
2953 | priv = hw->priv; |
2954 | /* At this point both hw and priv are allocated. */ | |
2955 | ||
b481de9c ZY |
2956 | SET_IEEE80211_DEV(hw, &pdev->dev); |
2957 | ||
e1623446 | 2958 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 2959 | priv->cfg = cfg; |
b481de9c | 2960 | priv->pci_dev = pdev; |
40cefda9 | 2961 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 2962 | |
0a6857e7 | 2963 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2964 | atomic_set(&priv->restrict_refcnt, 0); |
2965 | #endif | |
20594eb0 WYG |
2966 | if (iwl_alloc_traffic_mem(priv)) |
2967 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 2968 | |
316c30d9 AK |
2969 | /************************** |
2970 | * 2. Initializing PCI bus | |
2971 | **************************/ | |
2972 | if (pci_enable_device(pdev)) { | |
2973 | err = -ENODEV; | |
2974 | goto out_ieee80211_free_hw; | |
2975 | } | |
2976 | ||
2977 | pci_set_master(pdev); | |
2978 | ||
093d874c | 2979 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 2980 | if (!err) |
093d874c | 2981 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 2982 | if (err) { |
093d874c | 2983 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2984 | if (!err) |
093d874c | 2985 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2986 | /* both attempts failed: */ |
316c30d9 | 2987 | if (err) { |
978785a3 | 2988 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 2989 | goto out_pci_disable_device; |
cc2a8ea8 | 2990 | } |
316c30d9 AK |
2991 | } |
2992 | ||
2993 | err = pci_request_regions(pdev, DRV_NAME); | |
2994 | if (err) | |
2995 | goto out_pci_disable_device; | |
2996 | ||
2997 | pci_set_drvdata(pdev, priv); | |
2998 | ||
316c30d9 AK |
2999 | |
3000 | /*********************** | |
3001 | * 3. Read REV register | |
3002 | ***********************/ | |
3003 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3004 | if (!priv->hw_base) { | |
3005 | err = -ENODEV; | |
3006 | goto out_pci_release_regions; | |
3007 | } | |
3008 | ||
e1623446 | 3009 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 3010 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3011 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 3012 | |
a8b50a0a MA |
3013 | /* this spin lock will be used in apm_ops.init and EEPROM access |
3014 | * we should init now | |
3015 | */ | |
3016 | spin_lock_init(&priv->reg_lock); | |
b661c819 | 3017 | iwl_hw_detect(priv); |
978785a3 | 3018 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", |
b661c819 | 3019 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 3020 | |
e7b63581 TW |
3021 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3022 | * PCI Tx retries from interfering with C3 CPU state */ | |
3023 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3024 | ||
086ed117 MA |
3025 | iwl_prepare_card_hw(priv); |
3026 | if (!priv->hw_ready) { | |
3027 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
3028 | goto out_iounmap; | |
3029 | } | |
3030 | ||
91238714 TW |
3031 | /* amp init */ |
3032 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
316c30d9 | 3033 | if (err < 0) { |
808ff697 | 3034 | IWL_ERR(priv, "Failed to init APMG\n"); |
316c30d9 AK |
3035 | goto out_iounmap; |
3036 | } | |
91238714 TW |
3037 | /***************** |
3038 | * 4. Read EEPROM | |
3039 | *****************/ | |
316c30d9 AK |
3040 | /* Read the EEPROM */ |
3041 | err = iwl_eeprom_init(priv); | |
3042 | if (err) { | |
15b1687c | 3043 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
3044 | goto out_iounmap; |
3045 | } | |
8614f360 TW |
3046 | err = iwl_eeprom_check_version(priv); |
3047 | if (err) | |
c8f16138 | 3048 | goto out_free_eeprom; |
8614f360 | 3049 | |
02883017 | 3050 | /* extract MAC Address */ |
316c30d9 | 3051 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e1623446 | 3052 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
3053 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
3054 | ||
3055 | /************************ | |
3056 | * 5. Setup HW constants | |
3057 | ************************/ | |
da154e30 | 3058 | if (iwl_set_hw_params(priv)) { |
15b1687c | 3059 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3060 | goto out_free_eeprom; |
316c30d9 AK |
3061 | } |
3062 | ||
3063 | /******************* | |
6ba87956 | 3064 | * 6. Setup priv |
316c30d9 | 3065 | *******************/ |
b481de9c | 3066 | |
6ba87956 | 3067 | err = iwl_init_drv(priv); |
bf85ea4f | 3068 | if (err) |
399f4900 | 3069 | goto out_free_eeprom; |
bf85ea4f | 3070 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 3071 | |
316c30d9 | 3072 | /******************** |
09f9bf79 | 3073 | * 7. Setup services |
316c30d9 | 3074 | ********************/ |
0359facc | 3075 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 3076 | iwl_disable_interrupts(priv); |
0359facc | 3077 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 3078 | |
6cd0b1cb HS |
3079 | pci_enable_msi(priv->pci_dev); |
3080 | ||
ef850d7c MA |
3081 | iwl_alloc_isr_ict(priv); |
3082 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
3083 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
3084 | if (err) { |
3085 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3086 | goto out_disable_msi; | |
3087 | } | |
5b9f8cd3 | 3088 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 3089 | if (err) { |
15b1687c | 3090 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
795cc0ad | 3091 | goto out_free_irq; |
316c30d9 AK |
3092 | } |
3093 | ||
4e39317d | 3094 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3095 | iwl_setup_rx_handlers(priv); |
316c30d9 | 3096 | |
6ba87956 | 3097 | /********************************** |
09f9bf79 | 3098 | * 8. Setup and register mac80211 |
6ba87956 TW |
3099 | **********************************/ |
3100 | ||
6cd0b1cb HS |
3101 | /* enable interrupts if needed: hw bug w/a */ |
3102 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
3103 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3104 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3105 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3106 | } | |
3107 | ||
3108 | iwl_enable_interrupts(priv); | |
3109 | ||
6ba87956 TW |
3110 | err = iwl_setup_mac(priv); |
3111 | if (err) | |
3112 | goto out_remove_sysfs; | |
3113 | ||
3114 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
3115 | if (err) | |
a75fbe8d | 3116 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); |
6ba87956 | 3117 | |
6cd0b1cb HS |
3118 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3119 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3120 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3121 | else | |
3122 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3123 | |
a60e77e5 JB |
3124 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3125 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3126 | |
58d0f361 | 3127 | iwl_power_initialize(priv); |
39b73fb1 | 3128 | iwl_tt_initialize(priv); |
b481de9c ZY |
3129 | return 0; |
3130 | ||
316c30d9 | 3131 | out_remove_sysfs: |
c8f16138 RC |
3132 | destroy_workqueue(priv->workqueue); |
3133 | priv->workqueue = NULL; | |
5b9f8cd3 | 3134 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
795cc0ad HS |
3135 | out_free_irq: |
3136 | free_irq(priv->pci_dev->irq, priv); | |
ef850d7c | 3137 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
3138 | out_disable_msi: |
3139 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 3140 | iwl_uninit_drv(priv); |
073d3f5f TW |
3141 | out_free_eeprom: |
3142 | iwl_eeprom_free(priv); | |
b481de9c ZY |
3143 | out_iounmap: |
3144 | pci_iounmap(pdev, priv->hw_base); | |
3145 | out_pci_release_regions: | |
316c30d9 | 3146 | pci_set_drvdata(pdev, NULL); |
623d563e | 3147 | pci_release_regions(pdev); |
b481de9c ZY |
3148 | out_pci_disable_device: |
3149 | pci_disable_device(pdev); | |
b481de9c ZY |
3150 | out_ieee80211_free_hw: |
3151 | ieee80211_free_hw(priv->hw); | |
20594eb0 | 3152 | iwl_free_traffic_mem(priv); |
b481de9c ZY |
3153 | out: |
3154 | return err; | |
3155 | } | |
3156 | ||
5b9f8cd3 | 3157 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 3158 | { |
c79dd5b5 | 3159 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 3160 | unsigned long flags; |
b481de9c ZY |
3161 | |
3162 | if (!priv) | |
3163 | return; | |
3164 | ||
e1623446 | 3165 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 3166 | |
67249625 | 3167 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 3168 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 3169 | |
5b9f8cd3 EG |
3170 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3171 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3172 | * we need to set STATUS_EXIT_PENDING bit. |
3173 | */ | |
3174 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
3175 | if (priv->mac80211_registered) { |
3176 | ieee80211_unregister_hw(priv->hw); | |
3177 | priv->mac80211_registered = 0; | |
0b124c31 | 3178 | } else { |
5b9f8cd3 | 3179 | iwl_down(priv); |
c4f55232 RR |
3180 | } |
3181 | ||
39b73fb1 WYG |
3182 | iwl_tt_exit(priv); |
3183 | ||
0359facc MA |
3184 | /* make sure we flush any pending irq or |
3185 | * tasklet for the driver | |
3186 | */ | |
3187 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3188 | iwl_disable_interrupts(priv); |
0359facc MA |
3189 | spin_unlock_irqrestore(&priv->lock, flags); |
3190 | ||
3191 | iwl_synchronize_irq(priv); | |
3192 | ||
5b9f8cd3 | 3193 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3194 | |
3195 | if (priv->rxq.bd) | |
a55360e4 | 3196 | iwl_rx_queue_free(priv, &priv->rxq); |
1053d35f | 3197 | iwl_hw_txq_ctx_free(priv); |
b481de9c | 3198 | |
c587de0b | 3199 | iwl_clear_stations_table(priv); |
073d3f5f | 3200 | iwl_eeprom_free(priv); |
b481de9c | 3201 | |
b481de9c | 3202 | |
948c171c MA |
3203 | /*netif_stop_queue(dev); */ |
3204 | flush_workqueue(priv->workqueue); | |
3205 | ||
5b9f8cd3 | 3206 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3207 | * priv->workqueue... so we can't take down the workqueue |
3208 | * until now... */ | |
3209 | destroy_workqueue(priv->workqueue); | |
3210 | priv->workqueue = NULL; | |
20594eb0 | 3211 | iwl_free_traffic_mem(priv); |
b481de9c | 3212 | |
6cd0b1cb HS |
3213 | free_irq(priv->pci_dev->irq, priv); |
3214 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3215 | pci_iounmap(pdev, priv->hw_base); |
3216 | pci_release_regions(pdev); | |
3217 | pci_disable_device(pdev); | |
3218 | pci_set_drvdata(pdev, NULL); | |
3219 | ||
6ba87956 | 3220 | iwl_uninit_drv(priv); |
b481de9c | 3221 | |
ef850d7c MA |
3222 | iwl_free_isr_ict(priv); |
3223 | ||
b481de9c ZY |
3224 | if (priv->ibss_beacon) |
3225 | dev_kfree_skb(priv->ibss_beacon); | |
3226 | ||
3227 | ieee80211_free_hw(priv->hw); | |
3228 | } | |
3229 | ||
b481de9c ZY |
3230 | |
3231 | /***************************************************************************** | |
3232 | * | |
3233 | * driver and module entry point | |
3234 | * | |
3235 | *****************************************************************************/ | |
3236 | ||
fed9017e RR |
3237 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
3238 | static struct pci_device_id iwl_hw_card_ids[] = { | |
4fc22b21 | 3239 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
3240 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
3241 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 3242 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 3243 | #ifdef CONFIG_IWL5000 |
47408639 EK |
3244 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)}, |
3245 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)}, | |
3246 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, | |
3247 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, | |
3248 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, | |
3249 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, | |
5a6a256e | 3250 | {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)}, |
47408639 EK |
3251 | {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)}, |
3252 | {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)}, | |
3253 | {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)}, | |
e96a8495 TW |
3254 | /* 5350 WiFi/WiMax */ |
3255 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, | |
3256 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, | |
3257 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, | |
7100e924 TW |
3258 | /* 5150 Wifi/WiMax */ |
3259 | {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
3260 | {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
e1228374 | 3261 | /* 6000/6050 Series */ |
65b7998a WYG |
3262 | {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)}, |
3263 | {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)}, | |
e1228374 | 3264 | {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)}, |
65b7998a | 3265 | {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)}, |
e1228374 | 3266 | {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)}, |
65b7998a | 3267 | {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)}, |
e1228374 JS |
3268 | {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)}, |
3269 | {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
3270 | {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)}, | |
3271 | {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
77dcb6a9 | 3272 | /* 1000 Series WiFi */ |
4bd0914f WYG |
3273 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
3274 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
3275 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
3276 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
3277 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
3278 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
3279 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
3280 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
3281 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
3282 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
3283 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
3284 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
5a6a256e | 3285 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 3286 | |
fed9017e RR |
3287 | {0} |
3288 | }; | |
3289 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
3290 | ||
3291 | static struct pci_driver iwl_driver = { | |
b481de9c | 3292 | .name = DRV_NAME, |
fed9017e | 3293 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
3294 | .probe = iwl_pci_probe, |
3295 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 3296 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
3297 | .suspend = iwl_pci_suspend, |
3298 | .resume = iwl_pci_resume, | |
b481de9c ZY |
3299 | #endif |
3300 | }; | |
3301 | ||
5b9f8cd3 | 3302 | static int __init iwl_init(void) |
b481de9c ZY |
3303 | { |
3304 | ||
3305 | int ret; | |
3306 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3307 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3308 | |
e227ceac | 3309 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3310 | if (ret) { |
a3139c59 SO |
3311 | printk(KERN_ERR DRV_NAME |
3312 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
3313 | return ret; |
3314 | } | |
3315 | ||
fed9017e | 3316 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 3317 | if (ret) { |
a3139c59 | 3318 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 3319 | goto error_register; |
b481de9c | 3320 | } |
b481de9c ZY |
3321 | |
3322 | return ret; | |
897e1cf2 | 3323 | |
897e1cf2 | 3324 | error_register: |
e227ceac | 3325 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3326 | return ret; |
b481de9c ZY |
3327 | } |
3328 | ||
5b9f8cd3 | 3329 | static void __exit iwl_exit(void) |
b481de9c | 3330 | { |
fed9017e | 3331 | pci_unregister_driver(&iwl_driver); |
e227ceac | 3332 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3333 | } |
3334 | ||
5b9f8cd3 EG |
3335 | module_exit(iwl_exit); |
3336 | module_init(iwl_init); | |
a562a9dd RC |
3337 | |
3338 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 3339 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); |
a562a9dd | 3340 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); |
4e30cb69 | 3341 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
3342 | MODULE_PARM_DESC(debug, "debug output mask"); |
3343 | #endif | |
3344 |