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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
b481de9c ZY |
35 | #include <linux/dma-mapping.h> |
36 | #include <linux/delay.h> | |
d43c36dc | 37 | #include <linux/sched.h> |
b481de9c ZY |
38 | #include <linux/skbuff.h> |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/wireless.h> | |
41 | #include <linux/firmware.h> | |
b481de9c ZY |
42 | #include <linux/etherdevice.h> |
43 | #include <linux/if_arp.h> | |
44 | ||
b481de9c ZY |
45 | #include <net/mac80211.h> |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
a3139c59 SO |
49 | #define DRV_NAME "iwlagn" |
50 | ||
6bc913bd | 51 | #include "iwl-eeprom.h" |
3e0d4cb1 | 52 | #include "iwl-dev.h" |
fee1247a | 53 | #include "iwl-core.h" |
3395f6e9 | 54 | #include "iwl-io.h" |
b481de9c | 55 | #include "iwl-helpers.h" |
6974e363 | 56 | #include "iwl-sta.h" |
f0832f13 | 57 | #include "iwl-calib.h" |
b481de9c | 58 | |
416e1438 | 59 | |
b481de9c ZY |
60 | /****************************************************************************** |
61 | * | |
62 | * module boiler plate | |
63 | * | |
64 | ******************************************************************************/ | |
65 | ||
b481de9c ZY |
66 | /* |
67 | * module name, copyright, version, etc. | |
b481de9c | 68 | */ |
d783b061 | 69 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 70 | |
0a6857e7 | 71 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
72 | #define VD "d" |
73 | #else | |
74 | #define VD | |
75 | #endif | |
76 | ||
81963d68 | 77 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 78 | |
b481de9c ZY |
79 | |
80 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
81 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 82 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 83 | MODULE_LICENSE("GPL"); |
4fc22b21 | 84 | MODULE_ALIAS("iwl4965"); |
b481de9c | 85 | |
b481de9c | 86 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 87 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
88 | * the functionality provided here |
89 | */ | |
90 | ||
91 | /**************************************************************/ | |
92 | ||
b481de9c | 93 | /** |
5b9f8cd3 | 94 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 95 | * |
01ebd063 | 96 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
97 | * the active_rxon structure is updated with the new data. This |
98 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
99 | * a HW tune is required based on the RXON structure changes. | |
100 | */ | |
e0158e61 | 101 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
102 | { |
103 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 104 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
105 | int ret; |
106 | bool new_assoc = | |
107 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 108 | |
fee1247a | 109 | if (!iwl_is_alive(priv)) |
43d59b32 | 110 | return -EBUSY; |
b481de9c ZY |
111 | |
112 | /* always get timestamp with Rx frame */ | |
113 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
114 | ||
8ccde88a | 115 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 116 | if (ret) { |
15b1687c | 117 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
118 | return -EINVAL; |
119 | } | |
120 | ||
0924e519 WYG |
121 | /* |
122 | * receive commit_rxon request | |
123 | * abort any previous channel switch if still in process | |
124 | */ | |
125 | if (priv->switch_rxon.switch_in_progress && | |
126 | (priv->switch_rxon.channel != priv->staging_rxon.channel)) { | |
127 | IWL_DEBUG_11H(priv, "abort channel switch on %d\n", | |
128 | le16_to_cpu(priv->switch_rxon.channel)); | |
129 | priv->switch_rxon.switch_in_progress = false; | |
130 | } | |
131 | ||
b481de9c | 132 | /* If we don't need to send a full RXON, we can use |
5b9f8cd3 | 133 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 134 | * and other flags for the current radio configuration. */ |
54559703 | 135 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
136 | ret = iwl_send_rxon_assoc(priv); |
137 | if (ret) { | |
15b1687c | 138 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 139 | return ret; |
b481de9c ZY |
140 | } |
141 | ||
142 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
a643565e | 143 | iwl_print_rx_config_cmd(priv); |
b481de9c ZY |
144 | return 0; |
145 | } | |
146 | ||
147 | /* station table will be cleared */ | |
148 | priv->assoc_station_added = 0; | |
149 | ||
b481de9c ZY |
150 | /* If we are currently associated and the new config requires |
151 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
152 | * we must clear the associated from the active configuration | |
153 | * before we apply the new config */ | |
43d59b32 | 154 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 155 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
156 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
157 | ||
43d59b32 | 158 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 159 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
160 | &priv->active_rxon); |
161 | ||
162 | /* If the mask clearing failed then we set | |
163 | * active_rxon back to what it was previously */ | |
43d59b32 | 164 | if (ret) { |
b481de9c | 165 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 166 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 167 | return ret; |
b481de9c | 168 | } |
b481de9c ZY |
169 | } |
170 | ||
e1623446 | 171 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
172 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
173 | "* channel = %d\n" | |
e174961c | 174 | "* bssid = %pM\n", |
43d59b32 | 175 | (new_assoc ? "" : "out"), |
b481de9c | 176 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 177 | priv->staging_rxon.bssid_addr); |
b481de9c | 178 | |
90e8e424 | 179 | iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto); |
43d59b32 EG |
180 | |
181 | /* Apply the new configuration | |
182 | * RXON unassoc clears the station table in uCode, send it before | |
183 | * we add the bcast station. If assoc bit is set, we will send RXON | |
184 | * after having added the bcast and bssid station. | |
185 | */ | |
186 | if (!new_assoc) { | |
187 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 188 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 189 | if (ret) { |
15b1687c | 190 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
191 | return ret; |
192 | } | |
193 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
194 | } |
195 | ||
c587de0b | 196 | iwl_clear_stations_table(priv); |
556f8db7 | 197 | |
19cc1087 | 198 | priv->start_calib = 0; |
b481de9c | 199 | |
b481de9c | 200 | /* Add the broadcast address so we can send broadcast frames */ |
3459ab5a RC |
201 | priv->cfg->ops->lib->add_bcast_station(priv); |
202 | ||
b481de9c ZY |
203 | |
204 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
205 | * add the IWL_AP_ID to the station rate table */ | |
9185159d | 206 | if (new_assoc) { |
05c914fe | 207 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
9185159d TW |
208 | ret = iwl_rxon_add_station(priv, |
209 | priv->active_rxon.bssid_addr, 1); | |
210 | if (ret == IWL_INVALID_STATION) { | |
15b1687c WT |
211 | IWL_ERR(priv, |
212 | "Error adding AP address for TX.\n"); | |
9185159d TW |
213 | return -EIO; |
214 | } | |
215 | priv->assoc_station_added = 1; | |
216 | if (priv->default_wep_key && | |
217 | iwl_send_static_wepkey_cmd(priv, 0)) | |
15b1687c WT |
218 | IWL_ERR(priv, |
219 | "Could not send WEP static key.\n"); | |
b481de9c | 220 | } |
43d59b32 | 221 | |
47eef9bd WYG |
222 | /* |
223 | * allow CTS-to-self if possible for new association. | |
224 | * this is relevant only for 5000 series and up, | |
225 | * but will not damage 4965 | |
226 | */ | |
227 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
228 | ||
43d59b32 EG |
229 | /* Apply the new configuration |
230 | * RXON assoc doesn't clear the station table in uCode, | |
231 | */ | |
232 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
233 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
234 | if (ret) { | |
15b1687c | 235 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
236 | return ret; |
237 | } | |
238 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c | 239 | } |
a643565e | 240 | iwl_print_rx_config_cmd(priv); |
b481de9c | 241 | |
36da7d70 ZY |
242 | iwl_init_sensitivity(priv); |
243 | ||
244 | /* If we issue a new RXON command which required a tune then we must | |
245 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
246 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
247 | if (ret) { | |
15b1687c | 248 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
249 | return ret; |
250 | } | |
251 | ||
b481de9c ZY |
252 | return 0; |
253 | } | |
254 | ||
5b9f8cd3 | 255 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
256 | { |
257 | ||
45823531 AK |
258 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
259 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 260 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
261 | } |
262 | ||
fcab423d | 263 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
264 | { |
265 | struct list_head *element; | |
266 | ||
e1623446 | 267 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
268 | priv->frames_count); |
269 | ||
270 | while (!list_empty(&priv->free_frames)) { | |
271 | element = priv->free_frames.next; | |
272 | list_del(element); | |
fcab423d | 273 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
274 | priv->frames_count--; |
275 | } | |
276 | ||
277 | if (priv->frames_count) { | |
39aadf8c | 278 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
279 | priv->frames_count); |
280 | priv->frames_count = 0; | |
281 | } | |
282 | } | |
283 | ||
fcab423d | 284 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 285 | { |
fcab423d | 286 | struct iwl_frame *frame; |
b481de9c ZY |
287 | struct list_head *element; |
288 | if (list_empty(&priv->free_frames)) { | |
289 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
290 | if (!frame) { | |
15b1687c | 291 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
292 | return NULL; |
293 | } | |
294 | ||
295 | priv->frames_count++; | |
296 | return frame; | |
297 | } | |
298 | ||
299 | element = priv->free_frames.next; | |
300 | list_del(element); | |
fcab423d | 301 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
302 | } |
303 | ||
fcab423d | 304 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
305 | { |
306 | memset(frame, 0, sizeof(*frame)); | |
307 | list_add(&frame->list, &priv->free_frames); | |
308 | } | |
309 | ||
47ff65c4 | 310 | static u32 iwl_fill_beacon_frame(struct iwl_priv *priv, |
4bf64efd | 311 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 312 | int left) |
b481de9c | 313 | { |
3109ece1 | 314 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
315 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
316 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
317 | return 0; |
318 | ||
319 | if (priv->ibss_beacon->len > left) | |
320 | return 0; | |
321 | ||
322 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
323 | ||
324 | return priv->ibss_beacon->len; | |
325 | } | |
326 | ||
47ff65c4 DH |
327 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
328 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
329 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, | |
330 | u8 *beacon, u32 frame_size) | |
331 | { | |
332 | u16 tim_idx; | |
333 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
334 | ||
335 | /* | |
336 | * The index is relative to frame start but we start looking at the | |
337 | * variable-length part of the beacon. | |
338 | */ | |
339 | tim_idx = mgmt->u.beacon.variable - beacon; | |
340 | ||
341 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
342 | while ((tim_idx < (frame_size - 2)) && | |
343 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
344 | tim_idx += beacon[tim_idx+1] + 2; | |
345 | ||
346 | /* If TIM field was found, set variables */ | |
347 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
348 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
349 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
350 | } else | |
351 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
352 | } | |
353 | ||
5b9f8cd3 | 354 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
47ff65c4 | 355 | struct iwl_frame *frame) |
4bf64efd TW |
356 | { |
357 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
47ff65c4 DH |
358 | u32 frame_size; |
359 | u32 rate_flags; | |
360 | u32 rate; | |
361 | /* | |
362 | * We have to set up the TX command, the TX Beacon command, and the | |
363 | * beacon contents. | |
364 | */ | |
4bf64efd | 365 | |
47ff65c4 | 366 | /* Initialize memory */ |
4bf64efd TW |
367 | tx_beacon_cmd = &frame->u.beacon; |
368 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
369 | ||
47ff65c4 | 370 | /* Set up TX beacon contents */ |
4bf64efd | 371 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, |
4bf64efd | 372 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
47ff65c4 DH |
373 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
374 | return 0; | |
4bf64efd | 375 | |
47ff65c4 | 376 | /* Set up TX command fields */ |
4bf64efd | 377 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
47ff65c4 DH |
378 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; |
379 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
380 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
381 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 382 | |
47ff65c4 DH |
383 | /* Set up TX beacon command fields */ |
384 | iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, | |
385 | frame_size); | |
4bf64efd | 386 | |
47ff65c4 DH |
387 | /* Set up packet rate and flags */ |
388 | rate = iwl_rate_get_lowest_plcp(priv); | |
389 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant); | |
390 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); | |
391 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
392 | rate_flags |= RATE_MCS_CCK_MSK; | |
393 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
394 | rate_flags); | |
4bf64efd TW |
395 | |
396 | return sizeof(*tx_beacon_cmd) + frame_size; | |
397 | } | |
5b9f8cd3 | 398 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 399 | { |
fcab423d | 400 | struct iwl_frame *frame; |
b481de9c ZY |
401 | unsigned int frame_size; |
402 | int rc; | |
b481de9c | 403 | |
fcab423d | 404 | frame = iwl_get_free_frame(priv); |
b481de9c | 405 | if (!frame) { |
15b1687c | 406 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
407 | "command.\n"); |
408 | return -ENOMEM; | |
409 | } | |
410 | ||
47ff65c4 DH |
411 | frame_size = iwl_hw_get_beacon_cmd(priv, frame); |
412 | if (!frame_size) { | |
413 | IWL_ERR(priv, "Error configuring the beacon command\n"); | |
414 | iwl_free_frame(priv, frame); | |
415 | return -EINVAL; | |
416 | } | |
b481de9c | 417 | |
857485c0 | 418 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
419 | &frame->u.cmd[0]); |
420 | ||
fcab423d | 421 | iwl_free_frame(priv, frame); |
b481de9c ZY |
422 | |
423 | return rc; | |
424 | } | |
425 | ||
7aaa1d79 SO |
426 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
427 | { | |
428 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
429 | ||
430 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
431 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
432 | addr |= | |
433 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
434 | ||
435 | return addr; | |
436 | } | |
437 | ||
438 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
439 | { | |
440 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
441 | ||
442 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
443 | } | |
444 | ||
445 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
446 | dma_addr_t addr, u16 len) | |
447 | { | |
448 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
449 | u16 hi_n_len = len << 4; | |
450 | ||
451 | put_unaligned_le32(addr, &tb->lo); | |
452 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
453 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
454 | ||
455 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
456 | ||
457 | tfd->num_tbs = idx + 1; | |
458 | } | |
459 | ||
460 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
461 | { | |
462 | return tfd->num_tbs & 0x1f; | |
463 | } | |
464 | ||
465 | /** | |
466 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
467 | * @priv - driver private data | |
468 | * @txq - tx queue | |
469 | * | |
470 | * Does NOT advance any TFD circular buffer read/write indexes | |
471 | * Does NOT free the TFD itself (which is within circular buffer) | |
472 | */ | |
473 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
474 | { | |
59606ffa | 475 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
476 | struct iwl_tfd *tfd; |
477 | struct pci_dev *dev = priv->pci_dev; | |
478 | int index = txq->q.read_ptr; | |
479 | int i; | |
480 | int num_tbs; | |
481 | ||
482 | tfd = &tfd_tmp[index]; | |
483 | ||
484 | /* Sanity check on number of chunks */ | |
485 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
486 | ||
487 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
488 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
489 | /* @todo issue fatal error, it is quite serious situation */ | |
490 | return; | |
491 | } | |
492 | ||
493 | /* Unmap tx_cmd */ | |
494 | if (num_tbs) | |
495 | pci_unmap_single(dev, | |
c2acea8e JB |
496 | pci_unmap_addr(&txq->meta[index], mapping), |
497 | pci_unmap_len(&txq->meta[index], len), | |
96891cee | 498 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
499 | |
500 | /* Unmap chunks, if any. */ | |
501 | for (i = 1; i < num_tbs; i++) { | |
502 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
503 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
504 | ||
505 | if (txq->txb) { | |
506 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
507 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
508 | } | |
509 | } | |
510 | } | |
511 | ||
512 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
513 | struct iwl_tx_queue *txq, | |
514 | dma_addr_t addr, u16 len, | |
515 | u8 reset, u8 pad) | |
516 | { | |
517 | struct iwl_queue *q; | |
59606ffa | 518 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
519 | u32 num_tbs; |
520 | ||
521 | q = &txq->q; | |
59606ffa SO |
522 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
523 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
524 | |
525 | if (reset) | |
526 | memset(tfd, 0, sizeof(*tfd)); | |
527 | ||
528 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
529 | ||
530 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
531 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
532 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
533 | IWL_NUM_OF_TBS); | |
534 | return -EINVAL; | |
535 | } | |
536 | ||
537 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
538 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
539 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
540 | (unsigned long long)addr); | |
541 | ||
542 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
a8e74e27 SO |
547 | /* |
548 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
549 | * given Tx queue, and enable the DMA channel used for that queue. | |
550 | * | |
551 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
552 | * channels supported in hardware. | |
553 | */ | |
554 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
555 | struct iwl_tx_queue *txq) | |
556 | { | |
a8e74e27 SO |
557 | int txq_id = txq->q.id; |
558 | ||
a8e74e27 SO |
559 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
560 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
561 | txq->q.dma_addr >> 8); | |
562 | ||
a8e74e27 SO |
563 | return 0; |
564 | } | |
565 | ||
b481de9c ZY |
566 | /****************************************************************************** |
567 | * | |
568 | * Generic RX handler implementations | |
569 | * | |
570 | ******************************************************************************/ | |
885ba202 TW |
571 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
572 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 573 | { |
2f301227 | 574 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
885ba202 | 575 | struct iwl_alive_resp *palive; |
b481de9c ZY |
576 | struct delayed_work *pwork; |
577 | ||
578 | palive = &pkt->u.alive_frame; | |
579 | ||
e1623446 | 580 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
581 | "0x%01X 0x%01X\n", |
582 | palive->is_valid, palive->ver_type, | |
583 | palive->ver_subtype); | |
584 | ||
585 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 586 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
587 | memcpy(&priv->card_alive_init, |
588 | &pkt->u.alive_frame, | |
885ba202 | 589 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
590 | pwork = &priv->init_alive_start; |
591 | } else { | |
e1623446 | 592 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 593 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 594 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
595 | pwork = &priv->alive_start; |
596 | } | |
597 | ||
598 | /* We delay the ALIVE response by 5ms to | |
599 | * give the HW RF Kill time to activate... */ | |
600 | if (palive->is_valid == UCODE_VALID_OK) | |
601 | queue_delayed_work(priv->workqueue, pwork, | |
602 | msecs_to_jiffies(5)); | |
603 | else | |
39aadf8c | 604 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
605 | } |
606 | ||
5b9f8cd3 | 607 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 608 | { |
c79dd5b5 TW |
609 | struct iwl_priv *priv = |
610 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
611 | struct sk_buff *beacon; |
612 | ||
613 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 614 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
615 | |
616 | if (!beacon) { | |
15b1687c | 617 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
618 | return; |
619 | } | |
620 | ||
621 | mutex_lock(&priv->mutex); | |
622 | /* new beacon skb is allocated every time; dispose previous.*/ | |
623 | if (priv->ibss_beacon) | |
624 | dev_kfree_skb(priv->ibss_beacon); | |
625 | ||
626 | priv->ibss_beacon = beacon; | |
627 | mutex_unlock(&priv->mutex); | |
628 | ||
5b9f8cd3 | 629 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
630 | } |
631 | ||
4e39317d | 632 | /** |
5b9f8cd3 | 633 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
634 | * |
635 | * This callback is provided in order to send a statistics request. | |
636 | * | |
637 | * This timer function is continually reset to execute within | |
638 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
639 | * was received. We need to ensure we receive the statistics in order | |
640 | * to update the temperature used for calibrating the TXPOWER. | |
641 | */ | |
5b9f8cd3 | 642 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
643 | { |
644 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
645 | ||
646 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
647 | return; | |
648 | ||
61780ee3 MA |
649 | /* dont send host command if rf-kill is on */ |
650 | if (!iwl_is_ready_rf(priv)) | |
651 | return; | |
652 | ||
ef8d5529 | 653 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
654 | } |
655 | ||
a9e1cb6a WYG |
656 | |
657 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
658 | u32 start_idx, u32 num_events, | |
659 | u32 mode) | |
660 | { | |
661 | u32 i; | |
662 | u32 ptr; /* SRAM byte address of log data */ | |
663 | u32 ev, time, data; /* event log data */ | |
664 | unsigned long reg_flags; | |
665 | ||
666 | if (mode == 0) | |
667 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
668 | else | |
669 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
670 | ||
671 | /* Make sure device is powered up for SRAM reads */ | |
672 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
673 | if (iwl_grab_nic_access(priv)) { | |
674 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
675 | return; | |
676 | } | |
677 | ||
678 | /* Set starting address; reads will auto-increment */ | |
679 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
680 | rmb(); | |
681 | ||
682 | /* | |
683 | * "time" is actually "data" for mode 0 (no timestamp). | |
684 | * place event id # at far right for easier visual parsing. | |
685 | */ | |
686 | for (i = 0; i < num_events; i++) { | |
687 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
688 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
689 | if (mode == 0) { | |
690 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
691 | 0, time, ev); | |
692 | } else { | |
693 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
694 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
695 | time, data, ev); | |
696 | } | |
697 | } | |
698 | /* Allow device to power down */ | |
699 | iwl_release_nic_access(priv); | |
700 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
701 | } | |
702 | ||
875295f1 | 703 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
704 | { |
705 | u32 capacity; /* event log capacity in # entries */ | |
706 | u32 base; /* SRAM byte address of event log header */ | |
707 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
708 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
709 | u32 next_entry; /* index of next entry to be written by uCode */ | |
710 | ||
711 | if (priv->ucode_type == UCODE_INIT) | |
712 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
713 | else | |
714 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
715 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
716 | capacity = iwl_read_targ_mem(priv, base); | |
717 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
718 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
719 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
720 | } else | |
721 | return; | |
722 | ||
723 | if (num_wraps == priv->event_log.num_wraps) { | |
724 | iwl_print_cont_event_trace(priv, | |
725 | base, priv->event_log.next_entry, | |
726 | next_entry - priv->event_log.next_entry, | |
727 | mode); | |
728 | priv->event_log.non_wraps_count++; | |
729 | } else { | |
730 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
731 | priv->event_log.wraps_more_count++; | |
732 | else | |
733 | priv->event_log.wraps_once_count++; | |
734 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
735 | num_wraps - priv->event_log.num_wraps, | |
736 | next_entry, priv->event_log.next_entry); | |
737 | if (next_entry < priv->event_log.next_entry) { | |
738 | iwl_print_cont_event_trace(priv, base, | |
739 | priv->event_log.next_entry, | |
740 | capacity - priv->event_log.next_entry, | |
741 | mode); | |
742 | ||
743 | iwl_print_cont_event_trace(priv, base, 0, | |
744 | next_entry, mode); | |
745 | } else { | |
746 | iwl_print_cont_event_trace(priv, base, | |
747 | next_entry, capacity - next_entry, | |
748 | mode); | |
749 | ||
750 | iwl_print_cont_event_trace(priv, base, 0, | |
751 | next_entry, mode); | |
752 | } | |
753 | } | |
754 | priv->event_log.num_wraps = num_wraps; | |
755 | priv->event_log.next_entry = next_entry; | |
756 | } | |
757 | ||
758 | /** | |
759 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
760 | * | |
761 | * The timer is continually set to execute every | |
762 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
763 | * this function is to perform continuous uCode event logging operation | |
764 | * if enabled | |
765 | */ | |
766 | static void iwl_bg_ucode_trace(unsigned long data) | |
767 | { | |
768 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
769 | ||
770 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
771 | return; | |
772 | ||
773 | if (priv->event_log.ucode_trace) { | |
774 | iwl_continuous_event_trace(priv); | |
775 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
776 | mod_timer(&priv->ucode_trace, | |
777 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
778 | } | |
779 | } | |
780 | ||
5b9f8cd3 | 781 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 782 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 783 | { |
0a6857e7 | 784 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 785 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
2aa6ab86 TW |
786 | struct iwl4965_beacon_notif *beacon = |
787 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 788 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 789 | |
e1623446 | 790 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 791 | "tsf %d %d rate %d\n", |
25a6572c | 792 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
793 | beacon->beacon_notify_hdr.failure_frame, |
794 | le32_to_cpu(beacon->ibss_mgr_status), | |
795 | le32_to_cpu(beacon->high_tsf), | |
796 | le32_to_cpu(beacon->low_tsf), rate); | |
797 | #endif | |
798 | ||
05c914fe | 799 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
800 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
801 | queue_work(priv->workqueue, &priv->beacon_update); | |
802 | } | |
803 | ||
b481de9c ZY |
804 | /* Handle notification from uCode that card's power state is changing |
805 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 806 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 807 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 808 | { |
2f301227 | 809 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
810 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
811 | unsigned long status = priv->status; | |
812 | ||
3a41bbd5 | 813 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n", |
b481de9c | 814 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
3a41bbd5 WYG |
815 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", |
816 | (flags & CT_CARD_DISABLED) ? | |
817 | "Reached" : "Not reached"); | |
b481de9c ZY |
818 | |
819 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3a41bbd5 | 820 | CT_CARD_DISABLED)) { |
b481de9c | 821 | |
3395f6e9 | 822 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
823 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
824 | ||
a8b50a0a MA |
825 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
826 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
827 | |
828 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 829 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 830 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 831 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 832 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 833 | } |
3a41bbd5 | 834 | if (flags & CT_CARD_DISABLED) |
39b73fb1 | 835 | iwl_tt_enter_ct_kill(priv); |
b481de9c | 836 | } |
3a41bbd5 | 837 | if (!(flags & CT_CARD_DISABLED)) |
39b73fb1 | 838 | iwl_tt_exit_ct_kill(priv); |
b481de9c ZY |
839 | |
840 | if (flags & HW_CARD_DISABLED) | |
841 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
842 | else | |
843 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
844 | ||
845 | ||
b481de9c | 846 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 847 | iwl_scan_cancel(priv); |
b481de9c ZY |
848 | |
849 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
850 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
851 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
852 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
853 | else |
854 | wake_up_interruptible(&priv->wait_command_queue); | |
855 | } | |
856 | ||
5b9f8cd3 | 857 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 858 | { |
e2e3c57b | 859 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 860 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
861 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
862 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
863 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
864 | } else { | |
865 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
866 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
867 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
868 | } | |
869 | ||
a8b50a0a | 870 | return 0; |
e2e3c57b TW |
871 | } |
872 | ||
b481de9c | 873 | /** |
5b9f8cd3 | 874 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
875 | * |
876 | * Setup the RX handlers for each of the reply types sent from the uCode | |
877 | * to the host. | |
878 | * | |
879 | * This function chains into the hardware specific files for them to setup | |
880 | * any hardware specific handlers as well. | |
881 | */ | |
653fa4a0 | 882 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 883 | { |
885ba202 | 884 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
885 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
886 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
81963d68 RC |
887 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
888 | iwl_rx_spectrum_measure_notif; | |
5b9f8cd3 | 889 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 890 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
891 | iwl_rx_pm_debug_statistics_notif; |
892 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 893 | |
9fbab516 BC |
894 | /* |
895 | * The same handler is used for both the REPLY to a discrete | |
896 | * statistics request from the host as well as for the periodic | |
897 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 898 | */ |
ef8d5529 | 899 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics; |
8f91aecb | 900 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; |
2a421b91 TW |
901 | |
902 | iwl_setup_rx_scan_handlers(priv); | |
903 | ||
37a44211 | 904 | /* status change handler */ |
5b9f8cd3 | 905 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 906 | |
c1354754 TW |
907 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
908 | iwl_rx_missed_beacon_notif; | |
37a44211 | 909 | /* Rx handlers */ |
1781a07f EG |
910 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy; |
911 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx; | |
653fa4a0 EG |
912 | /* block ack */ |
913 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba; | |
9fbab516 | 914 | /* Set up hardware specific Rx handlers */ |
d4789efe | 915 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
916 | } |
917 | ||
b481de9c | 918 | /** |
a55360e4 | 919 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
920 | * |
921 | * Uses the priv->rx_handlers callback function array to invoke | |
922 | * the appropriate handlers, including command responses, | |
923 | * frame-received notifications, and other notifications. | |
924 | */ | |
a55360e4 | 925 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 926 | { |
a55360e4 | 927 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 928 | struct iwl_rx_packet *pkt; |
a55360e4 | 929 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
930 | u32 r, i; |
931 | int reclaim; | |
932 | unsigned long flags; | |
5c0eef96 | 933 | u8 fill_rx = 0; |
d68ab680 | 934 | u32 count = 8; |
4752c93c | 935 | int total_empty; |
b481de9c | 936 | |
6440adb5 BC |
937 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
938 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 939 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
940 | i = rxq->read; |
941 | ||
942 | /* Rx interrupt, but nothing sent from uCode */ | |
943 | if (i == r) | |
e1623446 | 944 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 945 | |
4752c93c | 946 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 947 | total_empty = r - rxq->write_actual; |
4752c93c MA |
948 | if (total_empty < 0) |
949 | total_empty += RX_QUEUE_SIZE; | |
950 | ||
951 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
952 | fill_rx = 1; |
953 | ||
b481de9c ZY |
954 | while (i != r) { |
955 | rxb = rxq->queue[i]; | |
956 | ||
9fbab516 | 957 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
958 | * then a bug has been introduced in the queue refilling |
959 | * routines -- catch it here */ | |
960 | BUG_ON(rxb == NULL); | |
961 | ||
962 | rxq->queue[i] = NULL; | |
963 | ||
2f301227 ZY |
964 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
965 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
966 | PCI_DMA_FROMDEVICE); | |
967 | pkt = rxb_addr(rxb); | |
b481de9c | 968 | |
be1a71a1 JB |
969 | trace_iwlwifi_dev_rx(priv, pkt, |
970 | le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); | |
971 | ||
b481de9c ZY |
972 | /* Reclaim a command buffer only if this packet is a response |
973 | * to a (driver-originated) command. | |
974 | * If the packet (e.g. Rx frame) originated from uCode, | |
975 | * there is no command buffer to reclaim. | |
976 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
977 | * but apparently a few don't get set; catch them here. */ | |
978 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
979 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 980 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 981 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 982 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
983 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
984 | (pkt->hdr.cmd != REPLY_TX); | |
985 | ||
986 | /* Based on type of command response or notification, | |
987 | * handle those that need handling via function in | |
5b9f8cd3 | 988 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 989 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 990 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 991 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 992 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 993 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
994 | } else { |
995 | /* No handling needed */ | |
e1623446 | 996 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
997 | "r %d i %d No handler needed for %s, 0x%02x\n", |
998 | r, i, get_cmd_string(pkt->hdr.cmd), | |
999 | pkt->hdr.cmd); | |
1000 | } | |
1001 | ||
29b1b268 ZY |
1002 | /* |
1003 | * XXX: After here, we should always check rxb->page | |
1004 | * against NULL before touching it or its virtual | |
1005 | * memory (pkt). Because some rx_handler might have | |
1006 | * already taken or freed the pages. | |
1007 | */ | |
1008 | ||
b481de9c | 1009 | if (reclaim) { |
2f301227 ZY |
1010 | /* Invoke any callbacks, transfer the buffer to caller, |
1011 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 1012 | * as we reclaim the driver command queue */ |
29b1b268 | 1013 | if (rxb->page) |
17b88929 | 1014 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1015 | else |
39aadf8c | 1016 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1017 | } |
1018 | ||
7300515d ZY |
1019 | /* Reuse the page if possible. For notification packets and |
1020 | * SKBs that fail to Rx correctly, add them back into the | |
1021 | * rx_free list for reuse later. */ | |
1022 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1023 | if (rxb->page != NULL) { |
7300515d ZY |
1024 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
1025 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
1026 | PCI_DMA_FROMDEVICE); | |
1027 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1028 | rxq->free_count++; | |
1029 | } else | |
1030 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 1031 | |
b481de9c | 1032 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 1033 | |
b481de9c | 1034 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
1035 | /* If there are a lot of unused frames, |
1036 | * restock the Rx queue so ucode wont assert. */ | |
1037 | if (fill_rx) { | |
1038 | count++; | |
1039 | if (count >= 8) { | |
7300515d | 1040 | rxq->read = i; |
4752c93c | 1041 | iwl_rx_replenish_now(priv); |
5c0eef96 MA |
1042 | count = 0; |
1043 | } | |
1044 | } | |
b481de9c ZY |
1045 | } |
1046 | ||
1047 | /* Backtrack one entry */ | |
7300515d | 1048 | rxq->read = i; |
4752c93c MA |
1049 | if (fill_rx) |
1050 | iwl_rx_replenish_now(priv); | |
1051 | else | |
1052 | iwl_rx_queue_restock(priv); | |
a55360e4 | 1053 | } |
a55360e4 | 1054 | |
0359facc MA |
1055 | /* call this function to flush any scheduled tasklet */ |
1056 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
1057 | { | |
a96a27f9 | 1058 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1059 | synchronize_irq(priv->pci_dev->irq); |
1060 | tasklet_kill(&priv->irq_tasklet); | |
1061 | } | |
1062 | ||
ef850d7c | 1063 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
1064 | { |
1065 | u32 inta, handled = 0; | |
1066 | u32 inta_fh; | |
1067 | unsigned long flags; | |
c2e61da2 | 1068 | u32 i; |
0a6857e7 | 1069 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1070 | u32 inta_mask; |
1071 | #endif | |
1072 | ||
1073 | spin_lock_irqsave(&priv->lock, flags); | |
1074 | ||
1075 | /* Ack/clear/reset pending uCode interrupts. | |
1076 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1077 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
1078 | inta = iwl_read32(priv, CSR_INT); |
1079 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1080 | |
1081 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1082 | * Any new interrupts that happen after this, either while we're | |
1083 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
1084 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1085 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1086 | |
0a6857e7 | 1087 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1088 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1089 | /* just for debug */ |
3395f6e9 | 1090 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1091 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1092 | inta, inta_mask, inta_fh); |
1093 | } | |
1094 | #endif | |
1095 | ||
2f301227 ZY |
1096 | spin_unlock_irqrestore(&priv->lock, flags); |
1097 | ||
b481de9c ZY |
1098 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1099 | * atomic, make sure that inta covers all the interrupts that | |
1100 | * we've discovered, even if FH interrupt came in just after | |
1101 | * reading CSR_INT. */ | |
6f83eaa1 | 1102 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 1103 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1104 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
1105 | inta |= CSR_INT_BIT_FH_TX; |
1106 | ||
1107 | /* Now service all interrupt bits discovered above. */ | |
1108 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1109 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1110 | |
1111 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 1112 | iwl_disable_interrupts(priv); |
b481de9c | 1113 | |
a83b9141 | 1114 | priv->isr_stats.hw++; |
5b9f8cd3 | 1115 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1116 | |
1117 | handled |= CSR_INT_BIT_HW_ERR; | |
1118 | ||
b481de9c ZY |
1119 | return; |
1120 | } | |
1121 | ||
0a6857e7 | 1122 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1123 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1124 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 1125 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1126 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1127 | "the frame/frames.\n"); |
a83b9141 WYG |
1128 | priv->isr_stats.sch++; |
1129 | } | |
b481de9c ZY |
1130 | |
1131 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 1132 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1133 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
1134 | priv->isr_stats.alive++; |
1135 | } | |
b481de9c ZY |
1136 | } |
1137 | #endif | |
1138 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1139 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1140 | |
9fbab516 | 1141 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1142 | if (inta & CSR_INT_BIT_RF_KILL) { |
1143 | int hw_rf_kill = 0; | |
3395f6e9 | 1144 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1145 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1146 | hw_rf_kill = 1; | |
1147 | ||
4c423a2b | 1148 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1149 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1150 | |
a83b9141 WYG |
1151 | priv->isr_stats.rfkill++; |
1152 | ||
a9efa652 | 1153 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1154 | * the driver allows loading the ucode even if the radio |
1155 | * is killed. Hence update the killswitch state here. The | |
1156 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1157 | */ |
6cd0b1cb HS |
1158 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1159 | if (hw_rf_kill) | |
1160 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1161 | else | |
1162 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1163 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 1164 | } |
b481de9c ZY |
1165 | |
1166 | handled |= CSR_INT_BIT_RF_KILL; | |
1167 | } | |
1168 | ||
9fbab516 | 1169 | /* Chip got too hot and stopped itself */ |
b481de9c | 1170 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1171 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 1172 | priv->isr_stats.ctkill++; |
b481de9c ZY |
1173 | handled |= CSR_INT_BIT_CT_KILL; |
1174 | } | |
1175 | ||
1176 | /* Error detected by uCode */ | |
1177 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1178 | IWL_ERR(priv, "Microcode SW error detected. " |
1179 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
1180 | priv->isr_stats.sw++; |
1181 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 1182 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1183 | handled |= CSR_INT_BIT_SW_ERR; |
1184 | } | |
1185 | ||
c2e61da2 BC |
1186 | /* |
1187 | * uCode wakes up after power-down sleep. | |
1188 | * Tell device about any new tx or host commands enqueued, | |
1189 | * and about any Rx buffers made available while asleep. | |
1190 | */ | |
b481de9c | 1191 | if (inta & CSR_INT_BIT_WAKEUP) { |
e1623446 | 1192 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1193 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
c2e61da2 BC |
1194 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1195 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
a83b9141 | 1196 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1197 | handled |= CSR_INT_BIT_WAKEUP; |
1198 | } | |
1199 | ||
1200 | /* All uCode command responses, including Tx command responses, | |
1201 | * Rx "responses" (frame-received notification), and other | |
1202 | * notifications from uCode come through here*/ | |
1203 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1204 | iwl_rx_handle(priv); |
a83b9141 | 1205 | priv->isr_stats.rx++; |
b481de9c ZY |
1206 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1207 | } | |
1208 | ||
c72cd19f | 1209 | /* This "Tx" DMA channel is used only for loading uCode */ |
b481de9c | 1210 | if (inta & CSR_INT_BIT_FH_TX) { |
c72cd19f | 1211 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
a83b9141 | 1212 | priv->isr_stats.tx++; |
b481de9c | 1213 | handled |= CSR_INT_BIT_FH_TX; |
c72cd19f | 1214 | /* Wake up uCode load routine, now that load is complete */ |
dbb983b7 RR |
1215 | priv->ucode_write_complete = 1; |
1216 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1217 | } |
1218 | ||
a83b9141 | 1219 | if (inta & ~handled) { |
15b1687c | 1220 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1221 | priv->isr_stats.unhandled++; |
1222 | } | |
b481de9c | 1223 | |
40cefda9 | 1224 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1225 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1226 | inta & ~priv->inta_mask); |
39aadf8c | 1227 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1228 | } |
1229 | ||
1230 | /* Re-enable all interrupts */ | |
0359facc MA |
1231 | /* only Re-enable if diabled by irq */ |
1232 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1233 | iwl_enable_interrupts(priv); |
b481de9c | 1234 | |
0a6857e7 | 1235 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1236 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1237 | inta = iwl_read32(priv, CSR_INT); |
1238 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1239 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1240 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1241 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1242 | } | |
1243 | #endif | |
b481de9c ZY |
1244 | } |
1245 | ||
ef850d7c MA |
1246 | /* tasklet for iwlagn interrupt */ |
1247 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1248 | { | |
1249 | u32 inta = 0; | |
1250 | u32 handled = 0; | |
1251 | unsigned long flags; | |
8756990f | 1252 | u32 i; |
ef850d7c MA |
1253 | #ifdef CONFIG_IWLWIFI_DEBUG |
1254 | u32 inta_mask; | |
1255 | #endif | |
1256 | ||
1257 | spin_lock_irqsave(&priv->lock, flags); | |
1258 | ||
1259 | /* Ack/clear/reset pending uCode interrupts. | |
1260 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1261 | */ | |
1262 | iwl_write32(priv, CSR_INT, priv->inta); | |
1263 | ||
1264 | inta = priv->inta; | |
1265 | ||
1266 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1267 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1268 | /* just for debug */ |
1269 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1270 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1271 | inta, inta_mask); | |
1272 | } | |
1273 | #endif | |
2f301227 ZY |
1274 | |
1275 | spin_unlock_irqrestore(&priv->lock, flags); | |
1276 | ||
ef850d7c MA |
1277 | /* saved interrupt in inta variable now we can reset priv->inta */ |
1278 | priv->inta = 0; | |
1279 | ||
1280 | /* Now service all interrupt bits discovered above. */ | |
1281 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1282 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1283 | |
1284 | /* Tell the device to stop sending interrupts */ | |
1285 | iwl_disable_interrupts(priv); | |
1286 | ||
1287 | priv->isr_stats.hw++; | |
1288 | iwl_irq_handle_error(priv); | |
1289 | ||
1290 | handled |= CSR_INT_BIT_HW_ERR; | |
1291 | ||
ef850d7c MA |
1292 | return; |
1293 | } | |
1294 | ||
1295 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1296 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1297 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1298 | if (inta & CSR_INT_BIT_SCD) { | |
1299 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1300 | "the frame/frames.\n"); | |
1301 | priv->isr_stats.sch++; | |
1302 | } | |
1303 | ||
1304 | /* Alive notification via Rx interrupt will do the real work */ | |
1305 | if (inta & CSR_INT_BIT_ALIVE) { | |
1306 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1307 | priv->isr_stats.alive++; | |
1308 | } | |
1309 | } | |
1310 | #endif | |
1311 | /* Safely ignore these bits for debug checks below */ | |
1312 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1313 | ||
1314 | /* HW RF KILL switch toggled */ | |
1315 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1316 | int hw_rf_kill = 0; | |
1317 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1318 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1319 | hw_rf_kill = 1; | |
1320 | ||
4c423a2b | 1321 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1322 | hw_rf_kill ? "disable radio" : "enable radio"); |
1323 | ||
1324 | priv->isr_stats.rfkill++; | |
1325 | ||
1326 | /* driver only loads ucode once setting the interface up. | |
1327 | * the driver allows loading the ucode even if the radio | |
1328 | * is killed. Hence update the killswitch state here. The | |
1329 | * rfkill handler will care about restarting if needed. | |
1330 | */ | |
1331 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1332 | if (hw_rf_kill) | |
1333 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1334 | else | |
1335 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1336 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1337 | } |
1338 | ||
1339 | handled |= CSR_INT_BIT_RF_KILL; | |
1340 | } | |
1341 | ||
1342 | /* Chip got too hot and stopped itself */ | |
1343 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1344 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1345 | priv->isr_stats.ctkill++; | |
1346 | handled |= CSR_INT_BIT_CT_KILL; | |
1347 | } | |
1348 | ||
1349 | /* Error detected by uCode */ | |
1350 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1351 | IWL_ERR(priv, "Microcode SW error detected. " | |
1352 | " Restarting 0x%X.\n", inta); | |
1353 | priv->isr_stats.sw++; | |
1354 | priv->isr_stats.sw_err = inta; | |
1355 | iwl_irq_handle_error(priv); | |
1356 | handled |= CSR_INT_BIT_SW_ERR; | |
1357 | } | |
1358 | ||
1359 | /* uCode wakes up after power-down sleep */ | |
1360 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1361 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1362 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
1363 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1364 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
1365 | |
1366 | priv->isr_stats.wakeup++; | |
1367 | ||
1368 | handled |= CSR_INT_BIT_WAKEUP; | |
1369 | } | |
1370 | ||
1371 | /* All uCode command responses, including Tx command responses, | |
1372 | * Rx "responses" (frame-received notification), and other | |
1373 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1374 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1375 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1376 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1377 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1378 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1379 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1380 | CSR49_FH_INT_RX_MASK); | |
1381 | } | |
1382 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1383 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1384 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1385 | } | |
1386 | /* Sending RX interrupt require many steps to be done in the | |
1387 | * the device: | |
1388 | * 1- write interrupt to current index in ICT table. | |
1389 | * 2- dma RX frame. | |
1390 | * 3- update RX shared data to indicate last write index. | |
1391 | * 4- send interrupt. | |
1392 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
1393 | * but the shared data changes does not reflect this; |
1394 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 1395 | */ |
74ba67ed BC |
1396 | |
1397 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1398 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 1399 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 1400 | iwl_rx_handle(priv); |
74ba67ed BC |
1401 | |
1402 | /* | |
1403 | * Enable periodic interrupt in 8 msec only if we received | |
1404 | * real RX interrupt (instead of just periodic int), to catch | |
1405 | * any dangling Rx interrupt. If it was just the periodic | |
1406 | * interrupt, there was no dangling Rx activity, and no need | |
1407 | * to extend the periodic interrupt; one-shot is enough. | |
1408 | */ | |
40cefda9 | 1409 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 1410 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
1411 | CSR_INT_PERIODIC_ENA); |
1412 | ||
ef850d7c | 1413 | priv->isr_stats.rx++; |
ef850d7c MA |
1414 | } |
1415 | ||
c72cd19f | 1416 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c MA |
1417 | if (inta & CSR_INT_BIT_FH_TX) { |
1418 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
c72cd19f | 1419 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
1420 | priv->isr_stats.tx++; |
1421 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 1422 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
1423 | priv->ucode_write_complete = 1; |
1424 | wake_up_interruptible(&priv->wait_command_queue); | |
1425 | } | |
1426 | ||
1427 | if (inta & ~handled) { | |
1428 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1429 | priv->isr_stats.unhandled++; | |
1430 | } | |
1431 | ||
40cefda9 | 1432 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1433 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1434 | inta & ~priv->inta_mask); |
ef850d7c MA |
1435 | } |
1436 | ||
ef850d7c MA |
1437 | /* Re-enable all interrupts */ |
1438 | /* only Re-enable if diabled by irq */ | |
1439 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1440 | iwl_enable_interrupts(priv); | |
ef850d7c MA |
1441 | } |
1442 | ||
a83b9141 | 1443 | |
b481de9c ZY |
1444 | /****************************************************************************** |
1445 | * | |
1446 | * uCode download functions | |
1447 | * | |
1448 | ******************************************************************************/ | |
1449 | ||
5b9f8cd3 | 1450 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1451 | { |
98c92211 TW |
1452 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1453 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1454 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1455 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1456 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1457 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1458 | } |
1459 | ||
5b9f8cd3 | 1460 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1461 | { |
1462 | /* Remove all resets to allow NIC to operate */ | |
1463 | iwl_write32(priv, CSR_RESET, 0); | |
1464 | } | |
1465 | ||
1466 | ||
b08dfd04 JB |
1467 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
1468 | static int iwl_mac_setup_register(struct iwl_priv *priv); | |
1469 | ||
1470 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) | |
1471 | { | |
1472 | const char *name_pre = priv->cfg->fw_name_pre; | |
1473 | ||
1474 | if (first) | |
1475 | priv->fw_index = priv->cfg->ucode_api_max; | |
1476 | else | |
1477 | priv->fw_index--; | |
1478 | ||
1479 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1480 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1481 | return -ENOENT; | |
1482 | } | |
1483 | ||
1484 | sprintf(priv->firmware_name, "%s%d%s", | |
1485 | name_pre, priv->fw_index, ".ucode"); | |
1486 | ||
1487 | IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n", | |
1488 | priv->firmware_name); | |
1489 | ||
1490 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
1491 | &priv->pci_dev->dev, GFP_KERNEL, priv, | |
1492 | iwl_ucode_callback); | |
1493 | } | |
1494 | ||
b481de9c | 1495 | /** |
b08dfd04 | 1496 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 1497 | * |
b08dfd04 JB |
1498 | * If loaded successfully, copies the firmware into buffers |
1499 | * for the card to fetch (via DMA). | |
b481de9c | 1500 | */ |
b08dfd04 | 1501 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 1502 | { |
b08dfd04 | 1503 | struct iwl_priv *priv = context; |
cc0f555d | 1504 | struct iwl_ucode_header *ucode; |
a0987a8d RC |
1505 | const unsigned int api_max = priv->cfg->ucode_api_max; |
1506 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
b481de9c ZY |
1507 | u8 *src; |
1508 | size_t len; | |
cc0f555d JS |
1509 | u32 api_ver, build; |
1510 | u32 inst_size, data_size, init_size, init_data_size, boot_size; | |
b08dfd04 | 1511 | int err; |
abdc2d62 | 1512 | u16 eeprom_ver; |
b481de9c | 1513 | |
b08dfd04 JB |
1514 | if (!ucode_raw) { |
1515 | IWL_ERR(priv, "request for firmware file '%s' failed.\n", | |
1516 | priv->firmware_name); | |
1517 | goto try_again; | |
b481de9c ZY |
1518 | } |
1519 | ||
b08dfd04 JB |
1520 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
1521 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 1522 | |
cc0f555d JS |
1523 | /* Make sure that we got at least the v1 header! */ |
1524 | if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) { | |
15b1687c | 1525 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 1526 | goto try_again; |
b481de9c ZY |
1527 | } |
1528 | ||
1529 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1530 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1531 | |
c02b3acd | 1532 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 1533 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
cc0f555d JS |
1534 | build = priv->cfg->ops->ucode->get_build(ucode, api_ver); |
1535 | inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver); | |
1536 | data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver); | |
1537 | init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver); | |
1538 | init_data_size = | |
1539 | priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver); | |
1540 | boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver); | |
1541 | src = priv->cfg->ops->ucode->get_data(ucode, api_ver); | |
b481de9c | 1542 | |
a0987a8d RC |
1543 | /* api_ver should match the api version forming part of the |
1544 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 1545 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
1546 | |
1547 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 1548 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1549 | "Driver supports v%u, firmware is v%u.\n", |
1550 | api_max, api_ver); | |
b08dfd04 | 1551 | goto try_again; |
a0987a8d | 1552 | } |
b08dfd04 | 1553 | |
a0987a8d | 1554 | if (api_ver != api_max) |
978785a3 | 1555 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1556 | "got v%u. New firmware can be obtained " |
1557 | "from http://www.intellinuxwireless.org.\n", | |
1558 | api_max, api_ver); | |
1559 | ||
978785a3 TW |
1560 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
1561 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1562 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1563 | IWL_UCODE_API(priv->ucode_ver), | |
1564 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d | 1565 | |
5ebeb5a6 RC |
1566 | snprintf(priv->hw->wiphy->fw_version, |
1567 | sizeof(priv->hw->wiphy->fw_version), | |
1568 | "%u.%u.%u.%u", | |
1569 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1570 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1571 | IWL_UCODE_API(priv->ucode_ver), | |
1572 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
1573 | ||
cc0f555d JS |
1574 | if (build) |
1575 | IWL_DEBUG_INFO(priv, "Build %u\n", build); | |
1576 | ||
abdc2d62 JS |
1577 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); |
1578 | IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n", | |
1579 | (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) | |
1580 | ? "OTP" : "EEPROM", eeprom_ver); | |
1581 | ||
e1623446 | 1582 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 1583 | priv->ucode_ver); |
e1623446 | 1584 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
b481de9c | 1585 | inst_size); |
e1623446 | 1586 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", |
b481de9c | 1587 | data_size); |
e1623446 | 1588 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", |
b481de9c | 1589 | init_size); |
e1623446 | 1590 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", |
b481de9c | 1591 | init_data_size); |
e1623446 | 1592 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", |
b481de9c ZY |
1593 | boot_size); |
1594 | ||
b08dfd04 JB |
1595 | /* |
1596 | * For any of the failures below (before allocating pci memory) | |
1597 | * we will try to load a version with a smaller API -- maybe the | |
1598 | * user just got a corrupted version of the latest API. | |
1599 | */ | |
1600 | ||
b481de9c | 1601 | /* Verify size of file vs. image size info in file's header */ |
cc0f555d JS |
1602 | if (ucode_raw->size != |
1603 | priv->cfg->ops->ucode->get_header_size(api_ver) + | |
b481de9c ZY |
1604 | inst_size + data_size + init_size + |
1605 | init_data_size + boot_size) { | |
1606 | ||
cc0f555d JS |
1607 | IWL_DEBUG_INFO(priv, |
1608 | "uCode file size %d does not match expected size\n", | |
1609 | (int)ucode_raw->size); | |
b08dfd04 | 1610 | goto try_again; |
b481de9c ZY |
1611 | } |
1612 | ||
1613 | /* Verify that uCode images will fit in card's SRAM */ | |
099b40b7 | 1614 | if (inst_size > priv->hw_params.max_inst_size) { |
e1623446 | 1615 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 | 1616 | inst_size); |
b08dfd04 | 1617 | goto try_again; |
b481de9c ZY |
1618 | } |
1619 | ||
099b40b7 | 1620 | if (data_size > priv->hw_params.max_data_size) { |
e1623446 | 1621 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 | 1622 | data_size); |
b08dfd04 | 1623 | goto try_again; |
b481de9c | 1624 | } |
099b40b7 | 1625 | if (init_size > priv->hw_params.max_inst_size) { |
e1623446 TW |
1626 | IWL_INFO(priv, "uCode init instr len %d too large to fit in\n", |
1627 | init_size); | |
b08dfd04 | 1628 | goto try_again; |
b481de9c | 1629 | } |
099b40b7 | 1630 | if (init_data_size > priv->hw_params.max_data_size) { |
e1623446 | 1631 | IWL_INFO(priv, "uCode init data len %d too large to fit in\n", |
90e759d1 | 1632 | init_data_size); |
b08dfd04 | 1633 | goto try_again; |
b481de9c | 1634 | } |
099b40b7 | 1635 | if (boot_size > priv->hw_params.max_bsm_size) { |
e1623446 TW |
1636 | IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n", |
1637 | boot_size); | |
b08dfd04 | 1638 | goto try_again; |
b481de9c ZY |
1639 | } |
1640 | ||
1641 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1642 | ||
1643 | /* Runtime instructions and 2 copies of data: | |
1644 | * 1) unmodified from disk | |
1645 | * 2) backup cache for save/restore during power-downs */ | |
1646 | priv->ucode_code.len = inst_size; | |
98c92211 | 1647 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
1648 | |
1649 | priv->ucode_data.len = data_size; | |
98c92211 | 1650 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
1651 | |
1652 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 1653 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1654 | |
1f304e4e ZY |
1655 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1656 | !priv->ucode_data_backup.v_addr) | |
1657 | goto err_pci_alloc; | |
1658 | ||
b481de9c | 1659 | /* Initialization instructions and data */ |
90e759d1 TW |
1660 | if (init_size && init_data_size) { |
1661 | priv->ucode_init.len = init_size; | |
98c92211 | 1662 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
1663 | |
1664 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 1665 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1666 | |
1667 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1668 | goto err_pci_alloc; | |
1669 | } | |
b481de9c ZY |
1670 | |
1671 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
1672 | if (boot_size) { |
1673 | priv->ucode_boot.len = boot_size; | |
98c92211 | 1674 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1675 | |
90e759d1 TW |
1676 | if (!priv->ucode_boot.v_addr) |
1677 | goto err_pci_alloc; | |
1678 | } | |
b481de9c ZY |
1679 | |
1680 | /* Copy images into buffers for card's bus-master reads ... */ | |
1681 | ||
1682 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 1683 | len = inst_size; |
e1623446 | 1684 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c | 1685 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
1686 | src += len; |
1687 | ||
e1623446 | 1688 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1689 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1690 | ||
1691 | /* Runtime data (2nd block) | |
5b9f8cd3 | 1692 | * NOTE: Copy into backup buffer will be done in iwl_up() */ |
cc0f555d | 1693 | len = data_size; |
e1623446 | 1694 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
1695 | memcpy(priv->ucode_data.v_addr, src, len); |
1696 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 1697 | src += len; |
b481de9c ZY |
1698 | |
1699 | /* Initialization instructions (3rd block) */ | |
1700 | if (init_size) { | |
cc0f555d | 1701 | len = init_size; |
e1623446 | 1702 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
90e759d1 | 1703 | len); |
b481de9c | 1704 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 1705 | src += len; |
b481de9c ZY |
1706 | } |
1707 | ||
1708 | /* Initialization data (4th block) */ | |
1709 | if (init_data_size) { | |
cc0f555d | 1710 | len = init_data_size; |
e1623446 | 1711 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
90e759d1 | 1712 | len); |
b481de9c | 1713 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 1714 | src += len; |
b481de9c ZY |
1715 | } |
1716 | ||
1717 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 1718 | len = boot_size; |
e1623446 | 1719 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
1720 | memcpy(priv->ucode_boot.v_addr, src, len); |
1721 | ||
b08dfd04 JB |
1722 | /************************************************** |
1723 | * This is still part of probe() in a sense... | |
1724 | * | |
1725 | * 9. Setup and register with mac80211 and debugfs | |
1726 | **************************************************/ | |
1727 | err = iwl_mac_setup_register(priv); | |
1728 | if (err) | |
1729 | goto out_unbind; | |
1730 | ||
1731 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
1732 | if (err) | |
1733 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
1734 | ||
b481de9c ZY |
1735 | /* We have our copies now, allow OS release its copies */ |
1736 | release_firmware(ucode_raw); | |
b08dfd04 JB |
1737 | return; |
1738 | ||
1739 | try_again: | |
1740 | /* try next, if any */ | |
1741 | if (iwl_request_firmware(priv, false)) | |
1742 | goto out_unbind; | |
1743 | release_firmware(ucode_raw); | |
1744 | return; | |
b481de9c ZY |
1745 | |
1746 | err_pci_alloc: | |
15b1687c | 1747 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
5b9f8cd3 | 1748 | iwl_dealloc_ucode_pci(priv); |
b08dfd04 JB |
1749 | out_unbind: |
1750 | device_release_driver(&priv->pci_dev->dev); | |
b481de9c | 1751 | release_firmware(ucode_raw); |
b481de9c ZY |
1752 | } |
1753 | ||
b7a79404 RC |
1754 | static const char *desc_lookup_text[] = { |
1755 | "OK", | |
1756 | "FAIL", | |
1757 | "BAD_PARAM", | |
1758 | "BAD_CHECKSUM", | |
1759 | "NMI_INTERRUPT_WDG", | |
1760 | "SYSASSERT", | |
1761 | "FATAL_ERROR", | |
1762 | "BAD_COMMAND", | |
1763 | "HW_ERROR_TUNE_LOCK", | |
1764 | "HW_ERROR_TEMPERATURE", | |
1765 | "ILLEGAL_CHAN_FREQ", | |
1766 | "VCC_NOT_STABLE", | |
1767 | "FH_ERROR", | |
1768 | "NMI_INTERRUPT_HOST", | |
1769 | "NMI_INTERRUPT_ACTION_PT", | |
1770 | "NMI_INTERRUPT_UNKNOWN", | |
1771 | "UCODE_VERSION_MISMATCH", | |
1772 | "HW_ERROR_ABS_LOCK", | |
1773 | "HW_ERROR_CAL_LOCK_FAIL", | |
1774 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1775 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1776 | "NMI_TRM_HW_ER", | |
1777 | "NMI_INTERRUPT_TRM", | |
1778 | "NMI_INTERRUPT_BREAK_POINT" | |
1779 | "DEBUG_0", | |
1780 | "DEBUG_1", | |
1781 | "DEBUG_2", | |
1782 | "DEBUG_3", | |
a7fce6ee | 1783 | "ADVANCED SYSASSERT" |
b7a79404 RC |
1784 | }; |
1785 | ||
1786 | static const char *desc_lookup(int i) | |
1787 | { | |
1788 | int max = ARRAY_SIZE(desc_lookup_text) - 1; | |
1789 | ||
1790 | if (i < 0 || i > max) | |
1791 | i = max; | |
1792 | ||
1793 | return desc_lookup_text[i]; | |
1794 | } | |
1795 | ||
1796 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1797 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1798 | ||
1799 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1800 | { | |
1801 | u32 data2, line; | |
1802 | u32 desc, time, count, base, data1; | |
1803 | u32 blink1, blink2, ilink1, ilink2; | |
1804 | ||
1805 | if (priv->ucode_type == UCODE_INIT) | |
1806 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
1807 | else | |
1808 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1809 | ||
1810 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
1811 | IWL_ERR(priv, |
1812 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
1813 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
b7a79404 RC |
1814 | return; |
1815 | } | |
1816 | ||
1817 | count = iwl_read_targ_mem(priv, base); | |
1818 | ||
1819 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
1820 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
1821 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1822 | priv->status, count); | |
1823 | } | |
1824 | ||
1825 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
1826 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
1827 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
1828 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
1829 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
1830 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
1831 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
1832 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
1833 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
1834 | ||
be1a71a1 JB |
1835 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
1836 | blink1, blink2, ilink1, ilink2); | |
1837 | ||
b7a79404 RC |
1838 | IWL_ERR(priv, "Desc Time " |
1839 | "data1 data2 line\n"); | |
1840 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", | |
1841 | desc_lookup(desc), desc, time, data1, data2, line); | |
1842 | IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n"); | |
1843 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
1844 | ilink1, ilink2); | |
1845 | ||
1846 | } | |
1847 | ||
1848 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
1849 | ||
1850 | /** | |
1851 | * iwl_print_event_log - Dump error event log to syslog | |
1852 | * | |
1853 | */ | |
b03d7d0f WYG |
1854 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
1855 | u32 num_events, u32 mode, | |
1856 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
1857 | { |
1858 | u32 i; | |
1859 | u32 base; /* SRAM byte address of event log header */ | |
1860 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1861 | u32 ptr; /* SRAM byte address of log data */ | |
1862 | u32 ev, time, data; /* event log data */ | |
e5854471 | 1863 | unsigned long reg_flags; |
b7a79404 RC |
1864 | |
1865 | if (num_events == 0) | |
b03d7d0f | 1866 | return pos; |
b7a79404 RC |
1867 | if (priv->ucode_type == UCODE_INIT) |
1868 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1869 | else | |
1870 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1871 | ||
1872 | if (mode == 0) | |
1873 | event_size = 2 * sizeof(u32); | |
1874 | else | |
1875 | event_size = 3 * sizeof(u32); | |
1876 | ||
1877 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1878 | ||
e5854471 BC |
1879 | /* Make sure device is powered up for SRAM reads */ |
1880 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
1881 | iwl_grab_nic_access(priv); | |
1882 | ||
1883 | /* Set starting address; reads will auto-increment */ | |
1884 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
1885 | rmb(); | |
1886 | ||
b7a79404 RC |
1887 | /* "time" is actually "data" for mode 0 (no timestamp). |
1888 | * place event id # at far right for easier visual parsing. */ | |
1889 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
1890 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
1891 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
1892 | if (mode == 0) { |
1893 | /* data, ev */ | |
b03d7d0f WYG |
1894 | if (bufsz) { |
1895 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1896 | "EVT_LOG:0x%08x:%04u\n", | |
1897 | time, ev); | |
1898 | } else { | |
1899 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
1900 | time, ev); | |
1901 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
1902 | time, ev); | |
1903 | } | |
b7a79404 | 1904 | } else { |
e5854471 | 1905 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
1906 | if (bufsz) { |
1907 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1908 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
1909 | time, data, ev); | |
1910 | } else { | |
1911 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 1912 | time, data, ev); |
b03d7d0f WYG |
1913 | trace_iwlwifi_dev_ucode_event(priv, time, |
1914 | data, ev); | |
1915 | } | |
b7a79404 RC |
1916 | } |
1917 | } | |
e5854471 BC |
1918 | |
1919 | /* Allow device to power down */ | |
1920 | iwl_release_nic_access(priv); | |
1921 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 1922 | return pos; |
b7a79404 RC |
1923 | } |
1924 | ||
c341ddb2 WYG |
1925 | /** |
1926 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
1927 | */ | |
b03d7d0f WYG |
1928 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
1929 | u32 num_wraps, u32 next_entry, | |
1930 | u32 size, u32 mode, | |
1931 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
1932 | { |
1933 | /* | |
1934 | * display the newest DEFAULT_LOG_ENTRIES entries | |
1935 | * i.e the entries just before the next ont that uCode would fill. | |
1936 | */ | |
1937 | if (num_wraps) { | |
1938 | if (next_entry < size) { | |
b03d7d0f WYG |
1939 | pos = iwl_print_event_log(priv, |
1940 | capacity - (size - next_entry), | |
1941 | size - next_entry, mode, | |
1942 | pos, buf, bufsz); | |
1943 | pos = iwl_print_event_log(priv, 0, | |
1944 | next_entry, mode, | |
1945 | pos, buf, bufsz); | |
c341ddb2 | 1946 | } else |
b03d7d0f WYG |
1947 | pos = iwl_print_event_log(priv, next_entry - size, |
1948 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 1949 | } else { |
b03d7d0f WYG |
1950 | if (next_entry < size) { |
1951 | pos = iwl_print_event_log(priv, 0, next_entry, | |
1952 | mode, pos, buf, bufsz); | |
1953 | } else { | |
1954 | pos = iwl_print_event_log(priv, next_entry - size, | |
1955 | size, mode, pos, buf, bufsz); | |
1956 | } | |
c341ddb2 | 1957 | } |
b03d7d0f | 1958 | return pos; |
c341ddb2 WYG |
1959 | } |
1960 | ||
84c40692 BC |
1961 | /* For sanity check only. Actual size is determined by uCode, typ. 512 */ |
1962 | #define MAX_EVENT_LOG_SIZE (512) | |
1963 | ||
c341ddb2 WYG |
1964 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
1965 | ||
b03d7d0f WYG |
1966 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
1967 | char **buf, bool display) | |
b7a79404 RC |
1968 | { |
1969 | u32 base; /* SRAM byte address of event log header */ | |
1970 | u32 capacity; /* event log capacity in # entries */ | |
1971 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1972 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1973 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1974 | u32 size; /* # entries that we'll print */ | |
b03d7d0f WYG |
1975 | int pos = 0; |
1976 | size_t bufsz = 0; | |
b7a79404 RC |
1977 | |
1978 | if (priv->ucode_type == UCODE_INIT) | |
1979 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1980 | else | |
1981 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1982 | ||
1983 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
1984 | IWL_ERR(priv, |
1985 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
1986 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
937c397e | 1987 | return -EINVAL; |
b7a79404 RC |
1988 | } |
1989 | ||
1990 | /* event log header */ | |
1991 | capacity = iwl_read_targ_mem(priv, base); | |
1992 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1993 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1994 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
1995 | ||
84c40692 BC |
1996 | if (capacity > MAX_EVENT_LOG_SIZE) { |
1997 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", | |
1998 | capacity, MAX_EVENT_LOG_SIZE); | |
1999 | capacity = MAX_EVENT_LOG_SIZE; | |
2000 | } | |
2001 | ||
2002 | if (next_entry > MAX_EVENT_LOG_SIZE) { | |
2003 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", | |
2004 | next_entry, MAX_EVENT_LOG_SIZE); | |
2005 | next_entry = MAX_EVENT_LOG_SIZE; | |
2006 | } | |
2007 | ||
b7a79404 RC |
2008 | size = num_wraps ? capacity : next_entry; |
2009 | ||
2010 | /* bail out if nothing in log */ | |
2011 | if (size == 0) { | |
2012 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 2013 | return pos; |
b7a79404 RC |
2014 | } |
2015 | ||
c341ddb2 | 2016 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 2017 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
2018 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
2019 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2020 | #else | |
2021 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
2022 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2023 | #endif | |
2024 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
2025 | size); | |
b7a79404 | 2026 | |
c341ddb2 | 2027 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
2028 | if (display) { |
2029 | if (full_log) | |
2030 | bufsz = capacity * 48; | |
2031 | else | |
2032 | bufsz = size * 48; | |
2033 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
2034 | if (!*buf) | |
937c397e | 2035 | return -ENOMEM; |
b03d7d0f | 2036 | } |
c341ddb2 WYG |
2037 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
2038 | /* | |
2039 | * if uCode has wrapped back to top of log, | |
2040 | * start at the oldest entry, | |
2041 | * i.e the next one that uCode would fill. | |
2042 | */ | |
2043 | if (num_wraps) | |
b03d7d0f WYG |
2044 | pos = iwl_print_event_log(priv, next_entry, |
2045 | capacity - next_entry, mode, | |
2046 | pos, buf, bufsz); | |
c341ddb2 | 2047 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
2048 | pos = iwl_print_event_log(priv, 0, |
2049 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 2050 | } else |
b03d7d0f WYG |
2051 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2052 | next_entry, size, mode, | |
2053 | pos, buf, bufsz); | |
c341ddb2 | 2054 | #else |
b03d7d0f WYG |
2055 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2056 | next_entry, size, mode, | |
2057 | pos, buf, bufsz); | |
b7a79404 | 2058 | #endif |
b03d7d0f | 2059 | return pos; |
c341ddb2 | 2060 | } |
b7a79404 | 2061 | |
b481de9c | 2062 | /** |
4a4a9e81 | 2063 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2064 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 2065 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 2066 | */ |
4a4a9e81 | 2067 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 2068 | { |
57aab75a | 2069 | int ret = 0; |
b481de9c | 2070 | |
e1623446 | 2071 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2072 | |
2073 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2074 | /* We had an error bringing up the hardware, so take it | |
2075 | * all the way back down so we can try again */ | |
e1623446 | 2076 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2077 | goto restart; |
2078 | } | |
2079 | ||
2080 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2081 | * This is a paranoid check, because we would not have gotten the | |
2082 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 2083 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
2084 | /* Runtime instruction load was bad; |
2085 | * take it all the way back down so we can try again */ | |
e1623446 | 2086 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2087 | goto restart; |
2088 | } | |
2089 | ||
c587de0b | 2090 | iwl_clear_stations_table(priv); |
57aab75a TW |
2091 | ret = priv->cfg->ops->lib->alive_notify(priv); |
2092 | if (ret) { | |
39aadf8c WT |
2093 | IWL_WARN(priv, |
2094 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
2095 | goto restart; |
2096 | } | |
2097 | ||
5b9f8cd3 | 2098 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
2099 | set_bit(STATUS_ALIVE, &priv->status); |
2100 | ||
fee1247a | 2101 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2102 | return; |
2103 | ||
36d6825b | 2104 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
2105 | |
2106 | priv->active_rate = priv->rates_mask; | |
2107 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
2108 | ||
2f748dec WYG |
2109 | /* Configure Tx antenna selection based on H/W config */ |
2110 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2111 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2112 | ||
3109ece1 | 2113 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
2114 | struct iwl_rxon_cmd *active_rxon = |
2115 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
2116 | /* apply any changes in staging */ |
2117 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
2118 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2119 | } else { | |
2120 | /* Initialize our rx_config data */ | |
5b9f8cd3 | 2121 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
45823531 AK |
2122 | |
2123 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2124 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2125 | ||
b481de9c ZY |
2126 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
2127 | } | |
2128 | ||
9fbab516 | 2129 | /* Configure Bluetooth device coexistence support */ |
5b9f8cd3 | 2130 | iwl_send_bt_config(priv); |
b481de9c | 2131 | |
4a4a9e81 TW |
2132 | iwl_reset_run_time_calib(priv); |
2133 | ||
b481de9c | 2134 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 2135 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2136 | |
2137 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2138 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2139 | |
e932a609 | 2140 | iwl_leds_init(priv); |
fe00b5a5 | 2141 | |
e1623446 | 2142 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2143 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2144 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2145 | |
e312c24c | 2146 | iwl_power_update_mode(priv, true); |
c46fbefa | 2147 | |
ada17513 MA |
2148 | /* reassociate for ADHOC mode */ |
2149 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
2150 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
2151 | priv->vif); | |
2152 | if (beacon) | |
2153 | iwl_mac_beacon_update(priv->hw, beacon); | |
2154 | } | |
2155 | ||
2156 | ||
c46fbefa | 2157 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
5b9f8cd3 | 2158 | iwl_set_mode(priv, priv->iw_mode); |
c46fbefa | 2159 | |
b481de9c ZY |
2160 | return; |
2161 | ||
2162 | restart: | |
2163 | queue_work(priv->workqueue, &priv->restart); | |
2164 | } | |
2165 | ||
4e39317d | 2166 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2167 | |
5b9f8cd3 | 2168 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2169 | { |
2170 | unsigned long flags; | |
2171 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2172 | |
e1623446 | 2173 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2174 | |
b481de9c ZY |
2175 | if (!exit_pending) |
2176 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2177 | ||
c587de0b | 2178 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2179 | |
2180 | /* Unblock any waiting calls */ | |
2181 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2182 | ||
b481de9c ZY |
2183 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2184 | * exiting the module */ | |
2185 | if (!exit_pending) | |
2186 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2187 | ||
2188 | /* stop and reset the on-board processor */ | |
3395f6e9 | 2189 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2190 | |
2191 | /* tell the device to stop sending interrupts */ | |
0359facc | 2192 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2193 | iwl_disable_interrupts(priv); |
0359facc MA |
2194 | spin_unlock_irqrestore(&priv->lock, flags); |
2195 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2196 | |
2197 | if (priv->mac80211_registered) | |
2198 | ieee80211_stop_queues(priv->hw); | |
2199 | ||
5b9f8cd3 | 2200 | /* If we have not previously called iwl_init() then |
a60e77e5 | 2201 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 2202 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2203 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2204 | STATUS_RF_KILL_HW | | |
9788864e RC |
2205 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2206 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
2207 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2208 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2209 | goto exit; |
2210 | } | |
2211 | ||
6da3a13e | 2212 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2213 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2214 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2215 | STATUS_RF_KILL_HW | | |
9788864e RC |
2216 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2217 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2218 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2219 | STATUS_FW_ERROR | |
2220 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2221 | STATUS_EXIT_PENDING; | |
b481de9c | 2222 | |
ef850d7c MA |
2223 | /* device going down, Stop using ICT table */ |
2224 | iwl_disable_ict(priv); | |
b481de9c | 2225 | |
da1bc453 | 2226 | iwl_txq_ctx_stop(priv); |
b3bbacb7 | 2227 | iwl_rxq_stop(priv); |
b481de9c | 2228 | |
309e731a BC |
2229 | /* Power-down device's busmaster DMA clocks */ |
2230 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2231 | udelay(5); |
2232 | ||
309e731a BC |
2233 | /* Make sure (redundant) we've released our request to stay awake */ |
2234 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
2235 | ||
4d2ccdb9 BC |
2236 | /* Stop the device, and put it in low power state */ |
2237 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
2238 | ||
b481de9c | 2239 | exit: |
885ba202 | 2240 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2241 | |
2242 | if (priv->ibss_beacon) | |
2243 | dev_kfree_skb(priv->ibss_beacon); | |
2244 | priv->ibss_beacon = NULL; | |
2245 | ||
2246 | /* clear out any free frames */ | |
fcab423d | 2247 | iwl_clear_free_frames(priv); |
b481de9c ZY |
2248 | } |
2249 | ||
5b9f8cd3 | 2250 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2251 | { |
2252 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2253 | __iwl_down(priv); |
b481de9c | 2254 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2255 | |
4e39317d | 2256 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2257 | } |
2258 | ||
086ed117 MA |
2259 | #define HW_READY_TIMEOUT (50) |
2260 | ||
2261 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
2262 | { | |
2263 | int ret = 0; | |
2264 | ||
2265 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2266 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2267 | ||
2268 | /* See if we got it */ | |
2269 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2270 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2271 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2272 | HW_READY_TIMEOUT); | |
2273 | if (ret != -ETIMEDOUT) | |
2274 | priv->hw_ready = true; | |
2275 | else | |
2276 | priv->hw_ready = false; | |
2277 | ||
2278 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
2279 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
2280 | return ret; | |
2281 | } | |
2282 | ||
2283 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
2284 | { | |
2285 | int ret = 0; | |
2286 | ||
2287 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n"); | |
2288 | ||
3354a0f6 MA |
2289 | ret = iwl_set_hw_ready(priv); |
2290 | if (priv->hw_ready) | |
2291 | return ret; | |
2292 | ||
2293 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2294 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2295 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2296 | ||
2297 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2298 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2299 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2300 | ||
3354a0f6 | 2301 | /* HW should be ready by now, check again. */ |
086ed117 MA |
2302 | if (ret != -ETIMEDOUT) |
2303 | iwl_set_hw_ready(priv); | |
2304 | ||
2305 | return ret; | |
2306 | } | |
2307 | ||
b481de9c ZY |
2308 | #define MAX_HW_RESTARTS 5 |
2309 | ||
5b9f8cd3 | 2310 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2311 | { |
57aab75a TW |
2312 | int i; |
2313 | int ret; | |
b481de9c ZY |
2314 | |
2315 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2316 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2317 | return -EIO; |
2318 | } | |
2319 | ||
e903fbd4 | 2320 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2321 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
2322 | return -EIO; |
2323 | } | |
2324 | ||
086ed117 MA |
2325 | iwl_prepare_card_hw(priv); |
2326 | ||
2327 | if (!priv->hw_ready) { | |
2328 | IWL_WARN(priv, "Exit HW not ready\n"); | |
2329 | return -EIO; | |
2330 | } | |
2331 | ||
e655b9f0 | 2332 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 2333 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 2334 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2335 | else |
e655b9f0 | 2336 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2337 | |
c1842d61 | 2338 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
2339 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
2340 | ||
5b9f8cd3 | 2341 | iwl_enable_interrupts(priv); |
a60e77e5 | 2342 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 2343 | return 0; |
b481de9c ZY |
2344 | } |
2345 | ||
3395f6e9 | 2346 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2347 | |
1053d35f | 2348 | ret = iwl_hw_nic_init(priv); |
57aab75a | 2349 | if (ret) { |
15b1687c | 2350 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 2351 | return ret; |
b481de9c ZY |
2352 | } |
2353 | ||
2354 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2355 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2356 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2357 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2358 | ||
2359 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 2360 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 2361 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2362 | |
2363 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2364 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2365 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2366 | |
2367 | /* Copy original ucode data image from disk into backup cache. | |
2368 | * This will be used to initialize the on-board processor's | |
2369 | * data SRAM for a clean start when the runtime program first loads. */ | |
2370 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2371 | priv->ucode_data.len); |
b481de9c | 2372 | |
b481de9c ZY |
2373 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2374 | ||
c587de0b | 2375 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2376 | |
2377 | /* load bootstrap state machine, | |
2378 | * load bootstrap program into processor's memory, | |
2379 | * prepare to load the "initialize" uCode */ | |
57aab75a | 2380 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 2381 | |
57aab75a | 2382 | if (ret) { |
15b1687c WT |
2383 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
2384 | ret); | |
b481de9c ZY |
2385 | continue; |
2386 | } | |
2387 | ||
2388 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 2389 | iwl_nic_start(priv); |
b481de9c | 2390 | |
e1623446 | 2391 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2392 | |
2393 | return 0; | |
2394 | } | |
2395 | ||
2396 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 2397 | __iwl_down(priv); |
64e72c3e | 2398 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2399 | |
2400 | /* tried to restart and config the device for as long as our | |
2401 | * patience could withstand */ | |
15b1687c | 2402 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2403 | return -EIO; |
2404 | } | |
2405 | ||
2406 | ||
2407 | /***************************************************************************** | |
2408 | * | |
2409 | * Workqueue callbacks | |
2410 | * | |
2411 | *****************************************************************************/ | |
2412 | ||
4a4a9e81 | 2413 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2414 | { |
c79dd5b5 TW |
2415 | struct iwl_priv *priv = |
2416 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2417 | |
2418 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2419 | return; | |
2420 | ||
2421 | mutex_lock(&priv->mutex); | |
f3ccc08c | 2422 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
2423 | mutex_unlock(&priv->mutex); |
2424 | } | |
2425 | ||
4a4a9e81 | 2426 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 2427 | { |
c79dd5b5 TW |
2428 | struct iwl_priv *priv = |
2429 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2430 | |
2431 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2432 | return; | |
2433 | ||
258c44a0 MA |
2434 | /* enable dram interrupt */ |
2435 | iwl_reset_ict(priv); | |
2436 | ||
b481de9c | 2437 | mutex_lock(&priv->mutex); |
4a4a9e81 | 2438 | iwl_alive_start(priv); |
b481de9c ZY |
2439 | mutex_unlock(&priv->mutex); |
2440 | } | |
2441 | ||
16e727e8 EG |
2442 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2443 | { | |
2444 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
2445 | run_time_calib_work); | |
2446 | ||
2447 | mutex_lock(&priv->mutex); | |
2448 | ||
2449 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
2450 | test_bit(STATUS_SCANNING, &priv->status)) { | |
2451 | mutex_unlock(&priv->mutex); | |
2452 | return; | |
2453 | } | |
2454 | ||
2455 | if (priv->start_calib) { | |
2456 | iwl_chain_noise_calibration(priv, &priv->statistics); | |
2457 | ||
2458 | iwl_sensitivity_calibration(priv, &priv->statistics); | |
2459 | } | |
2460 | ||
2461 | mutex_unlock(&priv->mutex); | |
2462 | return; | |
2463 | } | |
2464 | ||
5b9f8cd3 | 2465 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2466 | { |
c79dd5b5 | 2467 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2468 | |
2469 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2470 | return; | |
2471 | ||
19cc1087 JB |
2472 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2473 | mutex_lock(&priv->mutex); | |
2474 | priv->vif = NULL; | |
2475 | priv->is_open = 0; | |
2476 | mutex_unlock(&priv->mutex); | |
2477 | iwl_down(priv); | |
2478 | ieee80211_restart_hw(priv->hw); | |
2479 | } else { | |
2480 | iwl_down(priv); | |
80676518 JB |
2481 | |
2482 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2483 | return; | |
2484 | ||
2485 | mutex_lock(&priv->mutex); | |
2486 | __iwl_up(priv); | |
2487 | mutex_unlock(&priv->mutex); | |
19cc1087 | 2488 | } |
b481de9c ZY |
2489 | } |
2490 | ||
5b9f8cd3 | 2491 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2492 | { |
c79dd5b5 TW |
2493 | struct iwl_priv *priv = |
2494 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2495 | |
2496 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2497 | return; | |
2498 | ||
2499 | mutex_lock(&priv->mutex); | |
a55360e4 | 2500 | iwl_rx_replenish(priv); |
b481de9c ZY |
2501 | mutex_unlock(&priv->mutex); |
2502 | } | |
2503 | ||
7878a5a4 MA |
2504 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
2505 | ||
5bbe233b | 2506 | void iwl_post_associate(struct iwl_priv *priv) |
b481de9c | 2507 | { |
b481de9c | 2508 | struct ieee80211_conf *conf = NULL; |
857485c0 | 2509 | int ret = 0; |
1ff50bda | 2510 | unsigned long flags; |
b481de9c | 2511 | |
05c914fe | 2512 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 2513 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
2514 | return; |
2515 | } | |
2516 | ||
e1623446 | 2517 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
e174961c | 2518 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
2519 | |
2520 | ||
2521 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2522 | return; | |
2523 | ||
b481de9c | 2524 | |
508e32e1 | 2525 | if (!priv->vif || !priv->is_open) |
948c171c | 2526 | return; |
508e32e1 | 2527 | |
2a421b91 | 2528 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 2529 | |
b481de9c ZY |
2530 | conf = ieee80211_get_hw_conf(priv->hw); |
2531 | ||
2532 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2533 | iwlcore_commit_rxon(priv); |
b481de9c | 2534 | |
3195c1f3 | 2535 | iwl_setup_rxon_timing(priv); |
857485c0 | 2536 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2537 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2538 | if (ret) |
39aadf8c | 2539 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2540 | "Attempting to continue.\n"); |
2541 | ||
2542 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2543 | ||
42eb7c64 | 2544 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 2545 | |
45823531 AK |
2546 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2547 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2548 | ||
b481de9c ZY |
2549 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
2550 | ||
e1623446 | 2551 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
2552 | priv->assoc_id, priv->beacon_int); |
2553 | ||
2554 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2555 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2556 | else | |
2557 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2558 | ||
2559 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2560 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2561 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2562 | else | |
2563 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2564 | ||
05c914fe | 2565 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2566 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
2567 | ||
2568 | } | |
2569 | ||
e0158e61 | 2570 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2571 | |
2572 | switch (priv->iw_mode) { | |
05c914fe | 2573 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2574 | break; |
2575 | ||
05c914fe | 2576 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 2577 | |
c46fbefa AK |
2578 | /* assume default assoc id */ |
2579 | priv->assoc_id = 1; | |
b481de9c | 2580 | |
4f40e4d9 | 2581 | iwl_rxon_add_station(priv, priv->bssid, 0); |
5b9f8cd3 | 2582 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2583 | |
2584 | break; | |
2585 | ||
2586 | default: | |
15b1687c | 2587 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 2588 | __func__, priv->iw_mode); |
b481de9c ZY |
2589 | break; |
2590 | } | |
2591 | ||
05c914fe | 2592 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2593 | priv->assoc_station_added = 1; |
2594 | ||
1ff50bda EG |
2595 | spin_lock_irqsave(&priv->lock, flags); |
2596 | iwl_activate_qos(priv, 0); | |
2597 | spin_unlock_irqrestore(&priv->lock, flags); | |
292ae174 | 2598 | |
04816448 GE |
2599 | /* the chain noise calibration will enabled PM upon completion |
2600 | * If chain noise has already been run, then we need to enable | |
2601 | * power management here */ | |
2602 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
e312c24c | 2603 | iwl_power_update_mode(priv, false); |
c90a74ba EG |
2604 | |
2605 | /* Enable Rx differential gain and sensitivity calibrations */ | |
2606 | iwl_chain_noise_reset(priv); | |
2607 | priv->start_calib = 1; | |
2608 | ||
508e32e1 RC |
2609 | } |
2610 | ||
b481de9c ZY |
2611 | /***************************************************************************** |
2612 | * | |
2613 | * mac80211 entry point functions | |
2614 | * | |
2615 | *****************************************************************************/ | |
2616 | ||
154b25ce | 2617 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2618 | |
f0b6e2e8 RC |
2619 | /* |
2620 | * Not a mac80211 entry point function, but it fits in with all the | |
2621 | * other mac80211 functions grouped here. | |
2622 | */ | |
158bea07 | 2623 | static int iwl_mac_setup_register(struct iwl_priv *priv) |
f0b6e2e8 RC |
2624 | { |
2625 | int ret; | |
2626 | struct ieee80211_hw *hw = priv->hw; | |
2627 | hw->rate_control_algorithm = "iwl-agn-rs"; | |
2628 | ||
2629 | /* Tell mac80211 our characteristics */ | |
2630 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
2631 | IEEE80211_HW_NOISE_DBM | | |
2632 | IEEE80211_HW_AMPDU_AGGREGATION | | |
2633 | IEEE80211_HW_SPECTRUM_MGMT; | |
2634 | ||
2635 | if (!priv->cfg->broken_powersave) | |
2636 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | |
2637 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
2638 | ||
ba37a3d0 JB |
2639 | if (priv->cfg->sku & IWL_SKU_N) |
2640 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
2641 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
2642 | ||
8d9698b3 | 2643 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
f0b6e2e8 RC |
2644 | hw->wiphy->interface_modes = |
2645 | BIT(NL80211_IFTYPE_STATION) | | |
2646 | BIT(NL80211_IFTYPE_ADHOC); | |
2647 | ||
5be83de5 JB |
2648 | hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY | |
2649 | WIPHY_FLAG_DISABLE_BEACON_HINTS; | |
f0b6e2e8 RC |
2650 | |
2651 | /* | |
2652 | * For now, disable PS by default because it affects | |
2653 | * RX performance significantly. | |
2654 | */ | |
5be83de5 | 2655 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
f0b6e2e8 | 2656 | |
1382c71c | 2657 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
f0b6e2e8 RC |
2658 | /* we create the 802.11 header and a zero-length SSID element */ |
2659 | hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; | |
2660 | ||
2661 | /* Default value; 4 EDCA QOS priorities */ | |
2662 | hw->queues = 4; | |
2663 | ||
2664 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
2665 | ||
2666 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
2667 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
2668 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2669 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
2670 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
2671 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
2672 | ||
2673 | ret = ieee80211_register_hw(priv->hw); | |
2674 | if (ret) { | |
2675 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
2676 | return ret; | |
2677 | } | |
2678 | priv->mac80211_registered = 1; | |
2679 | ||
2680 | return 0; | |
2681 | } | |
2682 | ||
2683 | ||
5b9f8cd3 | 2684 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2685 | { |
c79dd5b5 | 2686 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2687 | int ret; |
b481de9c | 2688 | |
e1623446 | 2689 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2690 | |
2691 | /* we should be verifying the device is ready to be opened */ | |
2692 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2693 | ret = __iwl_up(priv); |
b481de9c | 2694 | mutex_unlock(&priv->mutex); |
5a66926a | 2695 | |
e655b9f0 | 2696 | if (ret) |
6cd0b1cb | 2697 | return ret; |
e655b9f0 | 2698 | |
c1842d61 TW |
2699 | if (iwl_is_rfkill(priv)) |
2700 | goto out; | |
2701 | ||
e1623446 | 2702 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2703 | |
fe9b6b72 | 2704 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2705 | * mac80211 will not be run successfully. */ |
154b25ce EG |
2706 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
2707 | test_bit(STATUS_READY, &priv->status), | |
2708 | UCODE_READY_TIMEOUT); | |
2709 | if (!ret) { | |
2710 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 2711 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 2712 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 2713 | return -ETIMEDOUT; |
5a66926a | 2714 | } |
fe9b6b72 | 2715 | } |
0a078ffa | 2716 | |
e932a609 JB |
2717 | iwl_led_start(priv); |
2718 | ||
c1842d61 | 2719 | out: |
0a078ffa | 2720 | priv->is_open = 1; |
e1623446 | 2721 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2722 | return 0; |
2723 | } | |
2724 | ||
5b9f8cd3 | 2725 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2726 | { |
c79dd5b5 | 2727 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2728 | |
e1623446 | 2729 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2730 | |
19cc1087 | 2731 | if (!priv->is_open) |
e655b9f0 | 2732 | return; |
e655b9f0 | 2733 | |
b481de9c | 2734 | priv->is_open = 0; |
5a66926a | 2735 | |
5bddf549 | 2736 | if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) { |
e655b9f0 ZY |
2737 | /* stop mac, cancel any scan request and clear |
2738 | * RXON_FILTER_ASSOC_MSK BIT | |
2739 | */ | |
5a66926a | 2740 | mutex_lock(&priv->mutex); |
2a421b91 | 2741 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2742 | mutex_unlock(&priv->mutex); |
fde3571f MA |
2743 | } |
2744 | ||
5b9f8cd3 | 2745 | iwl_down(priv); |
5a66926a ZY |
2746 | |
2747 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
2748 | |
2749 | /* enable interrupts again in order to receive rfkill changes */ | |
2750 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
2751 | iwl_enable_interrupts(priv); | |
948c171c | 2752 | |
e1623446 | 2753 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2754 | } |
2755 | ||
5b9f8cd3 | 2756 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2757 | { |
c79dd5b5 | 2758 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2759 | |
e1623446 | 2760 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2761 | |
e1623446 | 2762 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2763 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2764 | |
e039fa4a | 2765 | if (iwl_tx_skb(priv, skb)) |
b481de9c ZY |
2766 | dev_kfree_skb_any(skb); |
2767 | ||
e1623446 | 2768 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 2769 | return NETDEV_TX_OK; |
b481de9c ZY |
2770 | } |
2771 | ||
60690a6a | 2772 | void iwl_config_ap(struct iwl_priv *priv) |
b481de9c | 2773 | { |
857485c0 | 2774 | int ret = 0; |
1ff50bda | 2775 | unsigned long flags; |
b481de9c | 2776 | |
d986bcd1 | 2777 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
2778 | return; |
2779 | ||
2780 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 2781 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
2782 | |
2783 | /* RXON - unassoc (to set timing command) */ | |
2784 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2785 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2786 | |
2787 | /* RXON Timing */ | |
3195c1f3 | 2788 | iwl_setup_rxon_timing(priv); |
857485c0 | 2789 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2790 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2791 | if (ret) |
39aadf8c | 2792 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2793 | "Attempting to continue.\n"); |
2794 | ||
f513dfff DH |
2795 | /* AP has all antennas */ |
2796 | priv->chain_noise_data.active_chains = | |
2797 | priv->hw_params.valid_rx_ant; | |
2798 | iwl_set_rxon_ht(priv, &priv->current_ht_config); | |
45823531 AK |
2799 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2800 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c ZY |
2801 | |
2802 | /* FIXME: what should be the assoc_id for AP? */ | |
2803 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
2804 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2805 | priv->staging_rxon.flags |= | |
2806 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2807 | else | |
2808 | priv->staging_rxon.flags &= | |
2809 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2810 | ||
2811 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2812 | if (priv->assoc_capability & | |
2813 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2814 | priv->staging_rxon.flags |= | |
2815 | RXON_FLG_SHORT_SLOT_MSK; | |
2816 | else | |
2817 | priv->staging_rxon.flags &= | |
2818 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2819 | ||
05c914fe | 2820 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2821 | priv->staging_rxon.flags &= |
2822 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2823 | } | |
2824 | /* restore RXON assoc */ | |
2825 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2826 | iwlcore_commit_rxon(priv); |
f513dfff | 2827 | iwl_reset_qos(priv); |
1ff50bda EG |
2828 | spin_lock_irqsave(&priv->lock, flags); |
2829 | iwl_activate_qos(priv, 1); | |
2830 | spin_unlock_irqrestore(&priv->lock, flags); | |
9a9ca65f | 2831 | iwl_add_bcast_station(priv); |
e1493deb | 2832 | } |
5b9f8cd3 | 2833 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2834 | |
2835 | /* FIXME - we need to add code here to detect a totally new | |
2836 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
2837 | * clear sta table, add BCAST sta... */ | |
2838 | } | |
2839 | ||
5b9f8cd3 | 2840 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
b3fbdcf4 JB |
2841 | struct ieee80211_vif *vif, |
2842 | struct ieee80211_key_conf *keyconf, | |
2843 | struct ieee80211_sta *sta, | |
2844 | u32 iv32, u16 *phase1key) | |
ab885f8c | 2845 | { |
ab885f8c | 2846 | |
9f58671e | 2847 | struct iwl_priv *priv = hw->priv; |
e1623446 | 2848 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2849 | |
b3fbdcf4 JB |
2850 | iwl_update_tkip_key(priv, keyconf, |
2851 | sta ? sta->addr : iwl_bcast_addr, | |
2852 | iv32, phase1key); | |
ab885f8c | 2853 | |
e1623446 | 2854 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2855 | } |
2856 | ||
5b9f8cd3 | 2857 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
2858 | struct ieee80211_vif *vif, |
2859 | struct ieee80211_sta *sta, | |
b481de9c ZY |
2860 | struct ieee80211_key_conf *key) |
2861 | { | |
c79dd5b5 | 2862 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
2863 | const u8 *addr; |
2864 | int ret; | |
2865 | u8 sta_id; | |
2866 | bool is_default_wep_key = false; | |
b481de9c | 2867 | |
e1623446 | 2868 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2869 | |
90e8e424 | 2870 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 2871 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2872 | return -EOPNOTSUPP; |
2873 | } | |
42986796 | 2874 | addr = sta ? sta->addr : iwl_bcast_addr; |
c587de0b | 2875 | sta_id = iwl_find_station(priv, addr); |
6974e363 | 2876 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 2877 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
e174961c | 2878 | addr); |
6974e363 | 2879 | return -EINVAL; |
b481de9c | 2880 | |
deb09c43 | 2881 | } |
b481de9c | 2882 | |
6974e363 | 2883 | mutex_lock(&priv->mutex); |
2a421b91 | 2884 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 EG |
2885 | mutex_unlock(&priv->mutex); |
2886 | ||
2887 | /* If we are getting WEP group key and we didn't receive any key mapping | |
2888 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2889 | * in 1X mode. | |
2890 | * In legacy wep mode, we use another host command to the uCode */ | |
5425e490 | 2891 | if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id && |
05c914fe | 2892 | priv->iw_mode != NL80211_IFTYPE_AP) { |
6974e363 EG |
2893 | if (cmd == SET_KEY) |
2894 | is_default_wep_key = !priv->key_mapping_key; | |
2895 | else | |
ccc038ab EG |
2896 | is_default_wep_key = |
2897 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2898 | } |
052c4b9f | 2899 | |
b481de9c | 2900 | switch (cmd) { |
deb09c43 | 2901 | case SET_KEY: |
6974e363 EG |
2902 | if (is_default_wep_key) |
2903 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 2904 | else |
7480513f | 2905 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 2906 | |
e1623446 | 2907 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2908 | break; |
2909 | case DISABLE_KEY: | |
6974e363 EG |
2910 | if (is_default_wep_key) |
2911 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 2912 | else |
3ec47732 | 2913 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 2914 | |
e1623446 | 2915 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2916 | break; |
2917 | default: | |
deb09c43 | 2918 | ret = -EINVAL; |
b481de9c ZY |
2919 | } |
2920 | ||
e1623446 | 2921 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2922 | |
deb09c43 | 2923 | return ret; |
b481de9c ZY |
2924 | } |
2925 | ||
5b9f8cd3 | 2926 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2927 | struct ieee80211_vif *vif, |
d783b061 | 2928 | enum ieee80211_ampdu_mlme_action action, |
17741cdc | 2929 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
d783b061 TW |
2930 | { |
2931 | struct iwl_priv *priv = hw->priv; | |
5c2207c6 | 2932 | int ret; |
d783b061 | 2933 | |
e1623446 | 2934 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2935 | sta->addr, tid); |
d783b061 TW |
2936 | |
2937 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2938 | return -EACCES; | |
2939 | ||
2940 | switch (action) { | |
2941 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2942 | IWL_DEBUG_HT(priv, "start Rx\n"); |
9f58671e | 2943 | return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn); |
d783b061 | 2944 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2945 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
5c2207c6 WYG |
2946 | ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid); |
2947 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2948 | return 0; | |
2949 | else | |
2950 | return ret; | |
d783b061 | 2951 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2952 | IWL_DEBUG_HT(priv, "start Tx\n"); |
ab9bdc34 | 2953 | return iwl_tx_agg_start(priv, sta->addr, tid, ssn); |
d783b061 | 2954 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2955 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
5c2207c6 WYG |
2956 | ret = iwl_tx_agg_stop(priv, sta->addr, tid); |
2957 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2958 | return 0; | |
2959 | else | |
2960 | return ret; | |
f0527971 WYG |
2961 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
2962 | /* do nothing */ | |
2963 | return -EOPNOTSUPP; | |
d783b061 | 2964 | default: |
e1623446 | 2965 | IWL_DEBUG_HT(priv, "unknown\n"); |
d783b061 TW |
2966 | return -EINVAL; |
2967 | break; | |
2968 | } | |
2969 | return 0; | |
2970 | } | |
9f58671e | 2971 | |
5b9f8cd3 | 2972 | static int iwl_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2973 | struct ieee80211_low_level_stats *stats) |
2974 | { | |
bf403db8 EK |
2975 | struct iwl_priv *priv = hw->priv; |
2976 | ||
2977 | priv = hw->priv; | |
e1623446 TW |
2978 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
2979 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
b481de9c ZY |
2980 | |
2981 | return 0; | |
2982 | } | |
2983 | ||
6ab10ff8 JB |
2984 | static void iwl_mac_sta_notify(struct ieee80211_hw *hw, |
2985 | struct ieee80211_vif *vif, | |
2986 | enum sta_notify_cmd cmd, | |
2987 | struct ieee80211_sta *sta) | |
2988 | { | |
2989 | struct iwl_priv *priv = hw->priv; | |
2990 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
2991 | int sta_id; | |
2992 | ||
2993 | /* | |
2994 | * TODO: We really should use this callback to | |
2995 | * actually maintain the station table in | |
2996 | * the device. | |
2997 | */ | |
2998 | ||
2999 | switch (cmd) { | |
3000 | case STA_NOTIFY_ADD: | |
3001 | atomic_set(&sta_priv->pending_frames, 0); | |
3002 | if (vif->type == NL80211_IFTYPE_AP) | |
3003 | sta_priv->client = true; | |
3004 | break; | |
3005 | case STA_NOTIFY_SLEEP: | |
3006 | WARN_ON(!sta_priv->client); | |
3007 | sta_priv->asleep = true; | |
3008 | if (atomic_read(&sta_priv->pending_frames) > 0) | |
3009 | ieee80211_sta_block_awake(hw, sta, true); | |
3010 | break; | |
3011 | case STA_NOTIFY_AWAKE: | |
3012 | WARN_ON(!sta_priv->client); | |
49dcc819 DH |
3013 | if (!sta_priv->asleep) |
3014 | break; | |
6ab10ff8 JB |
3015 | sta_priv->asleep = false; |
3016 | sta_id = iwl_find_station(priv, sta->addr); | |
3017 | if (sta_id != IWL_INVALID_STATION) | |
3018 | iwl_sta_modify_ps_wake(priv, sta_id); | |
3019 | break; | |
3020 | default: | |
3021 | break; | |
3022 | } | |
3023 | } | |
3024 | ||
b481de9c ZY |
3025 | /***************************************************************************** |
3026 | * | |
3027 | * sysfs attributes | |
3028 | * | |
3029 | *****************************************************************************/ | |
3030 | ||
0a6857e7 | 3031 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3032 | |
3033 | /* | |
3034 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 3035 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
3036 | * used for controlling the debug level. |
3037 | * | |
3038 | * See the level definitions in iwl for details. | |
a562a9dd | 3039 | * |
3d816c77 RC |
3040 | * The debug_level being managed using sysfs below is a per device debug |
3041 | * level that is used instead of the global debug level if it (the per | |
3042 | * device debug level) is set. | |
b481de9c | 3043 | */ |
8cf769c6 EK |
3044 | static ssize_t show_debug_level(struct device *d, |
3045 | struct device_attribute *attr, char *buf) | |
b481de9c | 3046 | { |
3d816c77 RC |
3047 | struct iwl_priv *priv = dev_get_drvdata(d); |
3048 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 3049 | } |
8cf769c6 EK |
3050 | static ssize_t store_debug_level(struct device *d, |
3051 | struct device_attribute *attr, | |
b481de9c ZY |
3052 | const char *buf, size_t count) |
3053 | { | |
928841b1 | 3054 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
3055 | unsigned long val; |
3056 | int ret; | |
b481de9c | 3057 | |
9257746f TW |
3058 | ret = strict_strtoul(buf, 0, &val); |
3059 | if (ret) | |
978785a3 | 3060 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 3061 | else { |
3d816c77 | 3062 | priv->debug_level = val; |
20594eb0 WYG |
3063 | if (iwl_alloc_traffic_mem(priv)) |
3064 | IWL_ERR(priv, | |
3065 | "Not enough memory to generate traffic log\n"); | |
3066 | } | |
b481de9c ZY |
3067 | return strnlen(buf, count); |
3068 | } | |
3069 | ||
8cf769c6 EK |
3070 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3071 | show_debug_level, store_debug_level); | |
3072 | ||
b481de9c | 3073 | |
0a6857e7 | 3074 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3075 | |
b481de9c ZY |
3076 | |
3077 | static ssize_t show_temperature(struct device *d, | |
3078 | struct device_attribute *attr, char *buf) | |
3079 | { | |
928841b1 | 3080 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3081 | |
fee1247a | 3082 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3083 | return -EAGAIN; |
3084 | ||
91dbc5bd | 3085 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
3086 | } |
3087 | ||
3088 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3089 | ||
b481de9c ZY |
3090 | static ssize_t show_tx_power(struct device *d, |
3091 | struct device_attribute *attr, char *buf) | |
3092 | { | |
928841b1 | 3093 | struct iwl_priv *priv = dev_get_drvdata(d); |
91f39e8e JS |
3094 | |
3095 | if (!iwl_is_ready_rf(priv)) | |
3096 | return sprintf(buf, "off\n"); | |
3097 | else | |
3098 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
3099 | } |
3100 | ||
3101 | static ssize_t store_tx_power(struct device *d, | |
3102 | struct device_attribute *attr, | |
3103 | const char *buf, size_t count) | |
3104 | { | |
928841b1 | 3105 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
3106 | unsigned long val; |
3107 | int ret; | |
b481de9c | 3108 | |
9257746f TW |
3109 | ret = strict_strtoul(buf, 10, &val); |
3110 | if (ret) | |
978785a3 | 3111 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
5eadd94b WYG |
3112 | else { |
3113 | ret = iwl_set_tx_power(priv, val, false); | |
3114 | if (ret) | |
3115 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
3116 | ret); | |
3117 | else | |
3118 | ret = count; | |
3119 | } | |
3120 | return ret; | |
b481de9c ZY |
3121 | } |
3122 | ||
3123 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3124 | ||
3125 | static ssize_t show_flags(struct device *d, | |
3126 | struct device_attribute *attr, char *buf) | |
3127 | { | |
928841b1 | 3128 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3129 | |
3130 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
3131 | } | |
3132 | ||
3133 | static ssize_t store_flags(struct device *d, | |
3134 | struct device_attribute *attr, | |
3135 | const char *buf, size_t count) | |
3136 | { | |
928841b1 | 3137 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
3138 | unsigned long val; |
3139 | u32 flags; | |
3140 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 3141 | if (ret) |
9257746f TW |
3142 | return ret; |
3143 | flags = (u32)val; | |
b481de9c ZY |
3144 | |
3145 | mutex_lock(&priv->mutex); | |
3146 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
3147 | /* Cancel any currently running scans... */ | |
2a421b91 | 3148 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3149 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3150 | else { |
e1623446 | 3151 | IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags); |
b481de9c | 3152 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 3153 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3154 | } |
3155 | } | |
3156 | mutex_unlock(&priv->mutex); | |
3157 | ||
3158 | return count; | |
3159 | } | |
3160 | ||
3161 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
3162 | ||
3163 | static ssize_t show_filter_flags(struct device *d, | |
3164 | struct device_attribute *attr, char *buf) | |
3165 | { | |
928841b1 | 3166 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3167 | |
3168 | return sprintf(buf, "0x%04X\n", | |
3169 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
3170 | } | |
3171 | ||
3172 | static ssize_t store_filter_flags(struct device *d, | |
3173 | struct device_attribute *attr, | |
3174 | const char *buf, size_t count) | |
3175 | { | |
928841b1 | 3176 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
3177 | unsigned long val; |
3178 | u32 filter_flags; | |
3179 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 3180 | if (ret) |
9257746f TW |
3181 | return ret; |
3182 | filter_flags = (u32)val; | |
b481de9c ZY |
3183 | |
3184 | mutex_lock(&priv->mutex); | |
3185 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
3186 | /* Cancel any currently running scans... */ | |
2a421b91 | 3187 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3188 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3189 | else { |
e1623446 | 3190 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c ZY |
3191 | "0x%04X\n", filter_flags); |
3192 | priv->staging_rxon.filter_flags = | |
3193 | cpu_to_le32(filter_flags); | |
e0158e61 | 3194 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3195 | } |
3196 | } | |
3197 | mutex_unlock(&priv->mutex); | |
3198 | ||
3199 | return count; | |
3200 | } | |
3201 | ||
3202 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
3203 | store_filter_flags); | |
3204 | ||
b481de9c ZY |
3205 | |
3206 | static ssize_t show_statistics(struct device *d, | |
3207 | struct device_attribute *attr, char *buf) | |
3208 | { | |
c79dd5b5 | 3209 | struct iwl_priv *priv = dev_get_drvdata(d); |
8f91aecb | 3210 | u32 size = sizeof(struct iwl_notif_statistics); |
b481de9c | 3211 | u32 len = 0, ofs = 0; |
3ac7f146 | 3212 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
3213 | int rc = 0; |
3214 | ||
fee1247a | 3215 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3216 | return -EAGAIN; |
3217 | ||
3218 | mutex_lock(&priv->mutex); | |
ef8d5529 | 3219 | rc = iwl_send_statistics_request(priv, CMD_SYNC, false); |
b481de9c ZY |
3220 | mutex_unlock(&priv->mutex); |
3221 | ||
3222 | if (rc) { | |
3223 | len = sprintf(buf, | |
3224 | "Error sending statistics request: 0x%08X\n", rc); | |
3225 | return len; | |
3226 | } | |
3227 | ||
3228 | while (size && (PAGE_SIZE - len)) { | |
3229 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3230 | PAGE_SIZE - len, 1); | |
3231 | len = strlen(buf); | |
3232 | if (PAGE_SIZE - len) | |
3233 | buf[len++] = '\n'; | |
3234 | ||
3235 | ofs += 16; | |
3236 | size -= min(size, 16U); | |
3237 | } | |
3238 | ||
3239 | return len; | |
3240 | } | |
3241 | ||
3242 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
3243 | ||
01abfbb2 WYG |
3244 | static ssize_t show_rts_ht_protection(struct device *d, |
3245 | struct device_attribute *attr, char *buf) | |
3246 | { | |
3247 | struct iwl_priv *priv = dev_get_drvdata(d); | |
3248 | ||
3249 | return sprintf(buf, "%s\n", | |
3250 | priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self"); | |
3251 | } | |
3252 | ||
3253 | static ssize_t store_rts_ht_protection(struct device *d, | |
3254 | struct device_attribute *attr, | |
3255 | const char *buf, size_t count) | |
3256 | { | |
3257 | struct iwl_priv *priv = dev_get_drvdata(d); | |
3258 | unsigned long val; | |
3259 | int ret; | |
3260 | ||
3261 | ret = strict_strtoul(buf, 10, &val); | |
3262 | if (ret) | |
3263 | IWL_INFO(priv, "Input is not in decimal form.\n"); | |
3264 | else { | |
3265 | if (!iwl_is_associated(priv)) | |
3266 | priv->cfg->use_rts_for_ht = val ? true : false; | |
3267 | else | |
3268 | IWL_ERR(priv, "Sta associated with AP - " | |
3269 | "Change protection mechanism is not allowed\n"); | |
3270 | ret = count; | |
3271 | } | |
3272 | return ret; | |
3273 | } | |
3274 | ||
3275 | static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO, | |
3276 | show_rts_ht_protection, store_rts_ht_protection); | |
3277 | ||
b481de9c | 3278 | |
b481de9c ZY |
3279 | /***************************************************************************** |
3280 | * | |
3281 | * driver setup and teardown | |
3282 | * | |
3283 | *****************************************************************************/ | |
3284 | ||
4e39317d | 3285 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3286 | { |
d21050c7 | 3287 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3288 | |
3289 | init_waitqueue_head(&priv->wait_command_queue); | |
3290 | ||
5b9f8cd3 EG |
3291 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3292 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3293 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3294 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
3295 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
3296 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 3297 | |
2a421b91 | 3298 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3299 | |
4e39317d EG |
3300 | if (priv->cfg->ops->lib->setup_deferred_work) |
3301 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3302 | ||
3303 | init_timer(&priv->statistics_periodic); | |
3304 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3305 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3306 | |
a9e1cb6a WYG |
3307 | init_timer(&priv->ucode_trace); |
3308 | priv->ucode_trace.data = (unsigned long)priv; | |
3309 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3310 | ||
ef850d7c MA |
3311 | if (!priv->cfg->use_isr_legacy) |
3312 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3313 | iwl_irq_tasklet, (unsigned long)priv); | |
3314 | else | |
3315 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3316 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
3317 | } |
3318 | ||
4e39317d | 3319 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3320 | { |
4e39317d EG |
3321 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3322 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3323 | |
3ae6a054 | 3324 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
3325 | cancel_delayed_work(&priv->scan_check); |
3326 | cancel_delayed_work(&priv->alive_start); | |
b481de9c | 3327 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 3328 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 3329 | del_timer_sync(&priv->ucode_trace); |
b481de9c ZY |
3330 | } |
3331 | ||
89f186a8 RC |
3332 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
3333 | struct ieee80211_rate *rates) | |
3334 | { | |
3335 | int i; | |
3336 | ||
3337 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
3338 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
3339 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
3340 | rates[i].hw_value_short = i; | |
3341 | rates[i].flags = 0; | |
3342 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
3343 | /* | |
3344 | * If CCK != 1M then set short preamble rate flag. | |
3345 | */ | |
3346 | rates[i].flags |= | |
3347 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
3348 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
3349 | } | |
3350 | } | |
3351 | } | |
3352 | ||
3353 | static int iwl_init_drv(struct iwl_priv *priv) | |
3354 | { | |
3355 | int ret; | |
3356 | ||
3357 | priv->ibss_beacon = NULL; | |
3358 | ||
89f186a8 RC |
3359 | spin_lock_init(&priv->sta_lock); |
3360 | spin_lock_init(&priv->hcmd_lock); | |
3361 | ||
3362 | INIT_LIST_HEAD(&priv->free_frames); | |
3363 | ||
3364 | mutex_init(&priv->mutex); | |
d2dfe6df | 3365 | mutex_init(&priv->sync_cmd_mutex); |
89f186a8 RC |
3366 | |
3367 | /* Clear the driver's (not device's) station table */ | |
3368 | iwl_clear_stations_table(priv); | |
3369 | ||
3370 | priv->ieee_channels = NULL; | |
3371 | priv->ieee_rates = NULL; | |
3372 | priv->band = IEEE80211_BAND_2GHZ; | |
3373 | ||
3374 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 3375 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 3376 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
89f186a8 | 3377 | |
8a472da4 WYG |
3378 | /* initialize force reset */ |
3379 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
3380 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
3381 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
3382 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 RC |
3383 | |
3384 | /* Choose which receivers/antennas to use */ | |
3385 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
3386 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
3387 | ||
3388 | iwl_init_scan_params(priv); | |
3389 | ||
3390 | iwl_reset_qos(priv); | |
3391 | ||
3392 | priv->qos_data.qos_active = 0; | |
3393 | priv->qos_data.qos_cap.val = 0; | |
3394 | ||
3395 | priv->rates_mask = IWL_RATES_MASK; | |
3396 | /* Set the tx_power_user_lmt to the lowest power level | |
3397 | * this value will get overwritten by channel max power avg | |
3398 | * from eeprom */ | |
3399 | priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN; | |
3400 | ||
3401 | ret = iwl_init_channel_map(priv); | |
3402 | if (ret) { | |
3403 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3404 | goto err; | |
3405 | } | |
3406 | ||
3407 | ret = iwlcore_init_geos(priv); | |
3408 | if (ret) { | |
3409 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3410 | goto err_free_channel_map; | |
3411 | } | |
3412 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
3413 | ||
3414 | return 0; | |
3415 | ||
3416 | err_free_channel_map: | |
3417 | iwl_free_channel_map(priv); | |
3418 | err: | |
3419 | return ret; | |
3420 | } | |
3421 | ||
3422 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
3423 | { | |
3424 | iwl_calib_free_results(priv); | |
3425 | iwlcore_free_geos(priv); | |
3426 | iwl_free_channel_map(priv); | |
3427 | kfree(priv->scan); | |
3428 | } | |
3429 | ||
5b9f8cd3 | 3430 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c ZY |
3431 | &dev_attr_flags.attr, |
3432 | &dev_attr_filter_flags.attr, | |
b481de9c | 3433 | &dev_attr_statistics.attr, |
b481de9c | 3434 | &dev_attr_temperature.attr, |
b481de9c | 3435 | &dev_attr_tx_power.attr, |
01abfbb2 | 3436 | &dev_attr_rts_ht_protection.attr, |
8cf769c6 EK |
3437 | #ifdef CONFIG_IWLWIFI_DEBUG |
3438 | &dev_attr_debug_level.attr, | |
3439 | #endif | |
b481de9c ZY |
3440 | NULL |
3441 | }; | |
3442 | ||
5b9f8cd3 | 3443 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 3444 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 3445 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
3446 | }; |
3447 | ||
5b9f8cd3 EG |
3448 | static struct ieee80211_ops iwl_hw_ops = { |
3449 | .tx = iwl_mac_tx, | |
3450 | .start = iwl_mac_start, | |
3451 | .stop = iwl_mac_stop, | |
3452 | .add_interface = iwl_mac_add_interface, | |
3453 | .remove_interface = iwl_mac_remove_interface, | |
3454 | .config = iwl_mac_config, | |
5b9f8cd3 EG |
3455 | .configure_filter = iwl_configure_filter, |
3456 | .set_key = iwl_mac_set_key, | |
3457 | .update_tkip_key = iwl_mac_update_tkip_key, | |
3458 | .get_stats = iwl_mac_get_stats, | |
5b9f8cd3 EG |
3459 | .conf_tx = iwl_mac_conf_tx, |
3460 | .reset_tsf = iwl_mac_reset_tsf, | |
3461 | .bss_info_changed = iwl_bss_info_changed, | |
3462 | .ampdu_action = iwl_mac_ampdu_action, | |
6ab10ff8 JB |
3463 | .hw_scan = iwl_mac_hw_scan, |
3464 | .sta_notify = iwl_mac_sta_notify, | |
b481de9c ZY |
3465 | }; |
3466 | ||
5b9f8cd3 | 3467 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3468 | { |
3469 | int err = 0; | |
c79dd5b5 | 3470 | struct iwl_priv *priv; |
b481de9c | 3471 | struct ieee80211_hw *hw; |
82b9a121 | 3472 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 3473 | unsigned long flags; |
6cd0b1cb | 3474 | u16 pci_cmd; |
b481de9c | 3475 | |
316c30d9 AK |
3476 | /************************ |
3477 | * 1. Allocating HW data | |
3478 | ************************/ | |
3479 | ||
6440adb5 BC |
3480 | /* Disabling hardware scan means that mac80211 will perform scans |
3481 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 3482 | if (cfg->mod_params->disable_hw_scan) { |
a562a9dd | 3483 | if (iwl_debug_level & IWL_DL_INFO) |
bf403db8 EK |
3484 | dev_printk(KERN_DEBUG, &(pdev->dev), |
3485 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 3486 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
3487 | } |
3488 | ||
5b9f8cd3 | 3489 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 3490 | if (!hw) { |
b481de9c ZY |
3491 | err = -ENOMEM; |
3492 | goto out; | |
3493 | } | |
1d0a082d AK |
3494 | priv = hw->priv; |
3495 | /* At this point both hw and priv are allocated. */ | |
3496 | ||
b481de9c ZY |
3497 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3498 | ||
e1623446 | 3499 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 3500 | priv->cfg = cfg; |
b481de9c | 3501 | priv->pci_dev = pdev; |
40cefda9 | 3502 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 3503 | |
0a6857e7 | 3504 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3505 | atomic_set(&priv->restrict_refcnt, 0); |
3506 | #endif | |
20594eb0 WYG |
3507 | if (iwl_alloc_traffic_mem(priv)) |
3508 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3509 | |
316c30d9 AK |
3510 | /************************** |
3511 | * 2. Initializing PCI bus | |
3512 | **************************/ | |
3513 | if (pci_enable_device(pdev)) { | |
3514 | err = -ENODEV; | |
3515 | goto out_ieee80211_free_hw; | |
3516 | } | |
3517 | ||
3518 | pci_set_master(pdev); | |
3519 | ||
093d874c | 3520 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 3521 | if (!err) |
093d874c | 3522 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 3523 | if (err) { |
093d874c | 3524 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3525 | if (!err) |
093d874c | 3526 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3527 | /* both attempts failed: */ |
316c30d9 | 3528 | if (err) { |
978785a3 | 3529 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 3530 | goto out_pci_disable_device; |
cc2a8ea8 | 3531 | } |
316c30d9 AK |
3532 | } |
3533 | ||
3534 | err = pci_request_regions(pdev, DRV_NAME); | |
3535 | if (err) | |
3536 | goto out_pci_disable_device; | |
3537 | ||
3538 | pci_set_drvdata(pdev, priv); | |
3539 | ||
316c30d9 AK |
3540 | |
3541 | /*********************** | |
3542 | * 3. Read REV register | |
3543 | ***********************/ | |
3544 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3545 | if (!priv->hw_base) { | |
3546 | err = -ENODEV; | |
3547 | goto out_pci_release_regions; | |
3548 | } | |
3549 | ||
e1623446 | 3550 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 3551 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3552 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 3553 | |
731a29b7 | 3554 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
3555 | * we should init now |
3556 | */ | |
3557 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 3558 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
3559 | |
3560 | /* | |
3561 | * stop and reset the on-board processor just in case it is in a | |
3562 | * strange state ... like being left stranded by a primary kernel | |
3563 | * and this is now the kdump kernel trying to start up | |
3564 | */ | |
3565 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
3566 | ||
b661c819 | 3567 | iwl_hw_detect(priv); |
978785a3 | 3568 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", |
b661c819 | 3569 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 3570 | |
e7b63581 TW |
3571 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3572 | * PCI Tx retries from interfering with C3 CPU state */ | |
3573 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3574 | ||
086ed117 MA |
3575 | iwl_prepare_card_hw(priv); |
3576 | if (!priv->hw_ready) { | |
3577 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
3578 | goto out_iounmap; | |
3579 | } | |
3580 | ||
91238714 TW |
3581 | /***************** |
3582 | * 4. Read EEPROM | |
3583 | *****************/ | |
316c30d9 AK |
3584 | /* Read the EEPROM */ |
3585 | err = iwl_eeprom_init(priv); | |
3586 | if (err) { | |
15b1687c | 3587 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
3588 | goto out_iounmap; |
3589 | } | |
8614f360 TW |
3590 | err = iwl_eeprom_check_version(priv); |
3591 | if (err) | |
c8f16138 | 3592 | goto out_free_eeprom; |
8614f360 | 3593 | |
02883017 | 3594 | /* extract MAC Address */ |
316c30d9 | 3595 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e1623446 | 3596 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
3597 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
3598 | ||
3599 | /************************ | |
3600 | * 5. Setup HW constants | |
3601 | ************************/ | |
da154e30 | 3602 | if (iwl_set_hw_params(priv)) { |
15b1687c | 3603 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3604 | goto out_free_eeprom; |
316c30d9 AK |
3605 | } |
3606 | ||
3607 | /******************* | |
6ba87956 | 3608 | * 6. Setup priv |
316c30d9 | 3609 | *******************/ |
b481de9c | 3610 | |
6ba87956 | 3611 | err = iwl_init_drv(priv); |
bf85ea4f | 3612 | if (err) |
399f4900 | 3613 | goto out_free_eeprom; |
bf85ea4f | 3614 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 3615 | |
316c30d9 | 3616 | /******************** |
09f9bf79 | 3617 | * 7. Setup services |
316c30d9 | 3618 | ********************/ |
0359facc | 3619 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 3620 | iwl_disable_interrupts(priv); |
0359facc | 3621 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 3622 | |
6cd0b1cb HS |
3623 | pci_enable_msi(priv->pci_dev); |
3624 | ||
ef850d7c MA |
3625 | iwl_alloc_isr_ict(priv); |
3626 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
3627 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
3628 | if (err) { |
3629 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3630 | goto out_disable_msi; | |
3631 | } | |
5b9f8cd3 | 3632 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 3633 | if (err) { |
15b1687c | 3634 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
795cc0ad | 3635 | goto out_free_irq; |
316c30d9 AK |
3636 | } |
3637 | ||
4e39317d | 3638 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3639 | iwl_setup_rx_handlers(priv); |
316c30d9 | 3640 | |
158bea07 JB |
3641 | /********************************************* |
3642 | * 8. Enable interrupts and read RFKILL state | |
3643 | *********************************************/ | |
6ba87956 | 3644 | |
6cd0b1cb HS |
3645 | /* enable interrupts if needed: hw bug w/a */ |
3646 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
3647 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3648 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3649 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3650 | } | |
3651 | ||
3652 | iwl_enable_interrupts(priv); | |
3653 | ||
6cd0b1cb HS |
3654 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3655 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3656 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3657 | else | |
3658 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3659 | |
a60e77e5 JB |
3660 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3661 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3662 | |
58d0f361 | 3663 | iwl_power_initialize(priv); |
39b73fb1 | 3664 | iwl_tt_initialize(priv); |
158bea07 | 3665 | |
b08dfd04 | 3666 | err = iwl_request_firmware(priv, true); |
158bea07 JB |
3667 | if (err) |
3668 | goto out_remove_sysfs; | |
3669 | ||
b481de9c ZY |
3670 | return 0; |
3671 | ||
316c30d9 | 3672 | out_remove_sysfs: |
c8f16138 RC |
3673 | destroy_workqueue(priv->workqueue); |
3674 | priv->workqueue = NULL; | |
5b9f8cd3 | 3675 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
795cc0ad HS |
3676 | out_free_irq: |
3677 | free_irq(priv->pci_dev->irq, priv); | |
ef850d7c | 3678 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
3679 | out_disable_msi: |
3680 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 3681 | iwl_uninit_drv(priv); |
073d3f5f TW |
3682 | out_free_eeprom: |
3683 | iwl_eeprom_free(priv); | |
b481de9c ZY |
3684 | out_iounmap: |
3685 | pci_iounmap(pdev, priv->hw_base); | |
3686 | out_pci_release_regions: | |
316c30d9 | 3687 | pci_set_drvdata(pdev, NULL); |
623d563e | 3688 | pci_release_regions(pdev); |
b481de9c ZY |
3689 | out_pci_disable_device: |
3690 | pci_disable_device(pdev); | |
b481de9c | 3691 | out_ieee80211_free_hw: |
20594eb0 | 3692 | iwl_free_traffic_mem(priv); |
d7c76f4c | 3693 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
3694 | out: |
3695 | return err; | |
3696 | } | |
3697 | ||
5b9f8cd3 | 3698 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 3699 | { |
c79dd5b5 | 3700 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 3701 | unsigned long flags; |
b481de9c ZY |
3702 | |
3703 | if (!priv) | |
3704 | return; | |
3705 | ||
e1623446 | 3706 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 3707 | |
67249625 | 3708 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 3709 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 3710 | |
5b9f8cd3 EG |
3711 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3712 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3713 | * we need to set STATUS_EXIT_PENDING bit. |
3714 | */ | |
3715 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
3716 | if (priv->mac80211_registered) { |
3717 | ieee80211_unregister_hw(priv->hw); | |
3718 | priv->mac80211_registered = 0; | |
0b124c31 | 3719 | } else { |
5b9f8cd3 | 3720 | iwl_down(priv); |
c4f55232 RR |
3721 | } |
3722 | ||
c166b25a BC |
3723 | /* |
3724 | * Make sure device is reset to low power before unloading driver. | |
3725 | * This may be redundant with iwl_down(), but there are paths to | |
3726 | * run iwl_down() without calling apm_ops.stop(), and there are | |
3727 | * paths to avoid running iwl_down() at all before leaving driver. | |
3728 | * This (inexpensive) call *makes sure* device is reset. | |
3729 | */ | |
3730 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
3731 | ||
39b73fb1 WYG |
3732 | iwl_tt_exit(priv); |
3733 | ||
0359facc MA |
3734 | /* make sure we flush any pending irq or |
3735 | * tasklet for the driver | |
3736 | */ | |
3737 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3738 | iwl_disable_interrupts(priv); |
0359facc MA |
3739 | spin_unlock_irqrestore(&priv->lock, flags); |
3740 | ||
3741 | iwl_synchronize_irq(priv); | |
3742 | ||
5b9f8cd3 | 3743 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3744 | |
3745 | if (priv->rxq.bd) | |
a55360e4 | 3746 | iwl_rx_queue_free(priv, &priv->rxq); |
1053d35f | 3747 | iwl_hw_txq_ctx_free(priv); |
b481de9c | 3748 | |
c587de0b | 3749 | iwl_clear_stations_table(priv); |
073d3f5f | 3750 | iwl_eeprom_free(priv); |
b481de9c | 3751 | |
b481de9c | 3752 | |
948c171c MA |
3753 | /*netif_stop_queue(dev); */ |
3754 | flush_workqueue(priv->workqueue); | |
3755 | ||
5b9f8cd3 | 3756 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3757 | * priv->workqueue... so we can't take down the workqueue |
3758 | * until now... */ | |
3759 | destroy_workqueue(priv->workqueue); | |
3760 | priv->workqueue = NULL; | |
20594eb0 | 3761 | iwl_free_traffic_mem(priv); |
b481de9c | 3762 | |
6cd0b1cb HS |
3763 | free_irq(priv->pci_dev->irq, priv); |
3764 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3765 | pci_iounmap(pdev, priv->hw_base); |
3766 | pci_release_regions(pdev); | |
3767 | pci_disable_device(pdev); | |
3768 | pci_set_drvdata(pdev, NULL); | |
3769 | ||
6ba87956 | 3770 | iwl_uninit_drv(priv); |
b481de9c | 3771 | |
ef850d7c MA |
3772 | iwl_free_isr_ict(priv); |
3773 | ||
b481de9c ZY |
3774 | if (priv->ibss_beacon) |
3775 | dev_kfree_skb(priv->ibss_beacon); | |
3776 | ||
3777 | ieee80211_free_hw(priv->hw); | |
3778 | } | |
3779 | ||
b481de9c ZY |
3780 | |
3781 | /***************************************************************************** | |
3782 | * | |
3783 | * driver and module entry point | |
3784 | * | |
3785 | *****************************************************************************/ | |
3786 | ||
fed9017e | 3787 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
a3aa1884 | 3788 | static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = { |
4fc22b21 | 3789 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
3790 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
3791 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 3792 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 3793 | #ifdef CONFIG_IWL5000 |
ac592574 WYG |
3794 | /* 5100 Series WiFi */ |
3795 | {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ | |
3796 | {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3797 | {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ | |
3798 | {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3799 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3800 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3801 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ | |
3802 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3803 | {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */ | |
3804 | {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3805 | {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */ | |
3806 | {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3807 | {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3808 | {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3809 | {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */ | |
3810 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3811 | {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */ | |
3812 | {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3813 | {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */ | |
3814 | {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3815 | {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3816 | {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3817 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */ | |
3818 | {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3819 | ||
3820 | /* 5300 Series WiFi */ | |
3821 | {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */ | |
3822 | {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3823 | {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */ | |
3824 | {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3825 | {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */ | |
3826 | {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3827 | {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */ | |
3828 | {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3829 | {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */ | |
3830 | {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3831 | {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */ | |
3832 | {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3833 | ||
3834 | /* 5350 Series WiFi/WiMax */ | |
3835 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */ | |
3836 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */ | |
3837 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */ | |
3838 | ||
3839 | /* 5150 Series Wifi/WiMax */ | |
3840 | {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */ | |
3841 | {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
3842 | {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */ | |
3843 | {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
3844 | {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */ | |
3845 | {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
3846 | ||
3847 | {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */ | |
3848 | {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
3849 | {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */ | |
3850 | {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
5953a62e WYG |
3851 | |
3852 | /* 6x00 Series */ | |
5953a62e WYG |
3853 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, |
3854 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
3855 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
3856 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
3857 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
3858 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
3859 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
3860 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
3861 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
3862 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
3863 | ||
3864 | /* 6x50 WiFi/WiMax Series */ | |
5953a62e WYG |
3865 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, |
3866 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
3867 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
3868 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
5953a62e WYG |
3869 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, |
3870 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
3871 | ||
77dcb6a9 | 3872 | /* 1000 Series WiFi */ |
4bd0914f WYG |
3873 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
3874 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
3875 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
3876 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
3877 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
3878 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
3879 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
3880 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
3881 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
3882 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
3883 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
3884 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
5a6a256e | 3885 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 3886 | |
fed9017e RR |
3887 | {0} |
3888 | }; | |
3889 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
3890 | ||
3891 | static struct pci_driver iwl_driver = { | |
b481de9c | 3892 | .name = DRV_NAME, |
fed9017e | 3893 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
3894 | .probe = iwl_pci_probe, |
3895 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 3896 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
3897 | .suspend = iwl_pci_suspend, |
3898 | .resume = iwl_pci_resume, | |
b481de9c ZY |
3899 | #endif |
3900 | }; | |
3901 | ||
5b9f8cd3 | 3902 | static int __init iwl_init(void) |
b481de9c ZY |
3903 | { |
3904 | ||
3905 | int ret; | |
3906 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3907 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3908 | |
e227ceac | 3909 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3910 | if (ret) { |
a3139c59 SO |
3911 | printk(KERN_ERR DRV_NAME |
3912 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
3913 | return ret; |
3914 | } | |
3915 | ||
fed9017e | 3916 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 3917 | if (ret) { |
a3139c59 | 3918 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 3919 | goto error_register; |
b481de9c | 3920 | } |
b481de9c ZY |
3921 | |
3922 | return ret; | |
897e1cf2 | 3923 | |
897e1cf2 | 3924 | error_register: |
e227ceac | 3925 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3926 | return ret; |
b481de9c ZY |
3927 | } |
3928 | ||
5b9f8cd3 | 3929 | static void __exit iwl_exit(void) |
b481de9c | 3930 | { |
fed9017e | 3931 | pci_unregister_driver(&iwl_driver); |
e227ceac | 3932 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3933 | } |
3934 | ||
5b9f8cd3 EG |
3935 | module_exit(iwl_exit); |
3936 | module_init(iwl_init); | |
a562a9dd RC |
3937 | |
3938 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 3939 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); |
a562a9dd | 3940 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); |
4e30cb69 | 3941 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
3942 | MODULE_PARM_DESC(debug, "debug output mask"); |
3943 | #endif | |
3944 |