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Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
b481de9c ZY |
43 | #include <net/mac80211.h> |
44 | ||
45 | #include <asm/div64.h> | |
46 | ||
a3139c59 SO |
47 | #define DRV_NAME "iwlagn" |
48 | ||
6bc913bd | 49 | #include "iwl-eeprom.h" |
3e0d4cb1 | 50 | #include "iwl-dev.h" |
fee1247a | 51 | #include "iwl-core.h" |
3395f6e9 | 52 | #include "iwl-io.h" |
b481de9c | 53 | #include "iwl-helpers.h" |
6974e363 | 54 | #include "iwl-sta.h" |
f0832f13 | 55 | #include "iwl-calib.h" |
b481de9c | 56 | |
416e1438 | 57 | |
b481de9c ZY |
58 | /****************************************************************************** |
59 | * | |
60 | * module boiler plate | |
61 | * | |
62 | ******************************************************************************/ | |
63 | ||
b481de9c ZY |
64 | /* |
65 | * module name, copyright, version, etc. | |
b481de9c | 66 | */ |
d783b061 | 67 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 68 | |
0a6857e7 | 69 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
70 | #define VD "d" |
71 | #else | |
72 | #define VD | |
73 | #endif | |
74 | ||
80bc5393 | 75 | #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT |
b481de9c ZY |
76 | #define VS "s" |
77 | #else | |
78 | #define VS | |
79 | #endif | |
80 | ||
df48c323 | 81 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 87 | MODULE_LICENSE("GPL"); |
4fc22b21 | 88 | MODULE_ALIAS("iwl4965"); |
b481de9c | 89 | |
b481de9c | 90 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 91 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
92 | * the functionality provided here |
93 | */ | |
94 | ||
95 | /**************************************************************/ | |
96 | ||
b481de9c | 97 | /** |
5b9f8cd3 | 98 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 99 | * |
01ebd063 | 100 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
101 | * the active_rxon structure is updated with the new data. This |
102 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
103 | * a HW tune is required based on the RXON structure changes. | |
104 | */ | |
e0158e61 | 105 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
106 | { |
107 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 108 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
109 | int ret; |
110 | bool new_assoc = | |
111 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 112 | |
fee1247a | 113 | if (!iwl_is_alive(priv)) |
43d59b32 | 114 | return -EBUSY; |
b481de9c ZY |
115 | |
116 | /* always get timestamp with Rx frame */ | |
117 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
118 | ||
8ccde88a | 119 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 120 | if (ret) { |
15b1687c | 121 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
122 | return -EINVAL; |
123 | } | |
124 | ||
125 | /* If we don't need to send a full RXON, we can use | |
5b9f8cd3 | 126 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 127 | * and other flags for the current radio configuration. */ |
54559703 | 128 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
129 | ret = iwl_send_rxon_assoc(priv); |
130 | if (ret) { | |
15b1687c | 131 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 132 | return ret; |
b481de9c ZY |
133 | } |
134 | ||
135 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
136 | return 0; |
137 | } | |
138 | ||
139 | /* station table will be cleared */ | |
140 | priv->assoc_station_added = 0; | |
141 | ||
b481de9c ZY |
142 | /* If we are currently associated and the new config requires |
143 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
144 | * we must clear the associated from the active configuration | |
145 | * before we apply the new config */ | |
43d59b32 | 146 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 147 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
148 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
149 | ||
43d59b32 | 150 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 151 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
152 | &priv->active_rxon); |
153 | ||
154 | /* If the mask clearing failed then we set | |
155 | * active_rxon back to what it was previously */ | |
43d59b32 | 156 | if (ret) { |
b481de9c | 157 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 158 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 159 | return ret; |
b481de9c | 160 | } |
b481de9c ZY |
161 | } |
162 | ||
e1623446 | 163 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
164 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
165 | "* channel = %d\n" | |
e174961c | 166 | "* bssid = %pM\n", |
43d59b32 | 167 | (new_assoc ? "" : "out"), |
b481de9c | 168 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 169 | priv->staging_rxon.bssid_addr); |
b481de9c | 170 | |
90e8e424 | 171 | iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto); |
43d59b32 EG |
172 | |
173 | /* Apply the new configuration | |
174 | * RXON unassoc clears the station table in uCode, send it before | |
175 | * we add the bcast station. If assoc bit is set, we will send RXON | |
176 | * after having added the bcast and bssid station. | |
177 | */ | |
178 | if (!new_assoc) { | |
179 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 180 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 181 | if (ret) { |
15b1687c | 182 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
183 | return ret; |
184 | } | |
185 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
186 | } |
187 | ||
c587de0b | 188 | iwl_clear_stations_table(priv); |
556f8db7 | 189 | |
19cc1087 | 190 | priv->start_calib = 0; |
b481de9c | 191 | |
b481de9c | 192 | /* Add the broadcast address so we can send broadcast frames */ |
4f40e4d9 | 193 | if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) == |
43d59b32 | 194 | IWL_INVALID_STATION) { |
15b1687c | 195 | IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n"); |
b481de9c ZY |
196 | return -EIO; |
197 | } | |
198 | ||
199 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
200 | * add the IWL_AP_ID to the station rate table */ | |
9185159d | 201 | if (new_assoc) { |
05c914fe | 202 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
9185159d TW |
203 | ret = iwl_rxon_add_station(priv, |
204 | priv->active_rxon.bssid_addr, 1); | |
205 | if (ret == IWL_INVALID_STATION) { | |
15b1687c WT |
206 | IWL_ERR(priv, |
207 | "Error adding AP address for TX.\n"); | |
9185159d TW |
208 | return -EIO; |
209 | } | |
210 | priv->assoc_station_added = 1; | |
211 | if (priv->default_wep_key && | |
212 | iwl_send_static_wepkey_cmd(priv, 0)) | |
15b1687c WT |
213 | IWL_ERR(priv, |
214 | "Could not send WEP static key.\n"); | |
b481de9c | 215 | } |
43d59b32 | 216 | |
47eef9bd WYG |
217 | /* |
218 | * allow CTS-to-self if possible for new association. | |
219 | * this is relevant only for 5000 series and up, | |
220 | * but will not damage 4965 | |
221 | */ | |
222 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
223 | ||
43d59b32 EG |
224 | /* Apply the new configuration |
225 | * RXON assoc doesn't clear the station table in uCode, | |
226 | */ | |
227 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
228 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
229 | if (ret) { | |
15b1687c | 230 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
231 | return ret; |
232 | } | |
233 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
234 | } |
235 | ||
36da7d70 ZY |
236 | iwl_init_sensitivity(priv); |
237 | ||
238 | /* If we issue a new RXON command which required a tune then we must | |
239 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
240 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
241 | if (ret) { | |
15b1687c | 242 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
243 | return ret; |
244 | } | |
245 | ||
b481de9c ZY |
246 | return 0; |
247 | } | |
248 | ||
5b9f8cd3 | 249 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
250 | { |
251 | ||
45823531 AK |
252 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
253 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 254 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
255 | } |
256 | ||
fcab423d | 257 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
258 | { |
259 | struct list_head *element; | |
260 | ||
e1623446 | 261 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
262 | priv->frames_count); |
263 | ||
264 | while (!list_empty(&priv->free_frames)) { | |
265 | element = priv->free_frames.next; | |
266 | list_del(element); | |
fcab423d | 267 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
268 | priv->frames_count--; |
269 | } | |
270 | ||
271 | if (priv->frames_count) { | |
39aadf8c | 272 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
273 | priv->frames_count); |
274 | priv->frames_count = 0; | |
275 | } | |
276 | } | |
277 | ||
fcab423d | 278 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 279 | { |
fcab423d | 280 | struct iwl_frame *frame; |
b481de9c ZY |
281 | struct list_head *element; |
282 | if (list_empty(&priv->free_frames)) { | |
283 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
284 | if (!frame) { | |
15b1687c | 285 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
286 | return NULL; |
287 | } | |
288 | ||
289 | priv->frames_count++; | |
290 | return frame; | |
291 | } | |
292 | ||
293 | element = priv->free_frames.next; | |
294 | list_del(element); | |
fcab423d | 295 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
296 | } |
297 | ||
fcab423d | 298 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
299 | { |
300 | memset(frame, 0, sizeof(*frame)); | |
301 | list_add(&frame->list, &priv->free_frames); | |
302 | } | |
303 | ||
4bf64efd TW |
304 | static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv, |
305 | struct ieee80211_hdr *hdr, | |
73ec1cc2 | 306 | int left) |
b481de9c | 307 | { |
3109ece1 | 308 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
309 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
310 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
311 | return 0; |
312 | ||
313 | if (priv->ibss_beacon->len > left) | |
314 | return 0; | |
315 | ||
316 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
317 | ||
318 | return priv->ibss_beacon->len; | |
319 | } | |
320 | ||
5b9f8cd3 | 321 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
4bf64efd TW |
322 | struct iwl_frame *frame, u8 rate) |
323 | { | |
324 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
325 | unsigned int frame_size; | |
326 | ||
327 | tx_beacon_cmd = &frame->u.beacon; | |
328 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
329 | ||
330 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; | |
331 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
332 | ||
333 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, | |
4bf64efd TW |
334 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
335 | ||
336 | BUG_ON(frame_size > MAX_MPDU_SIZE); | |
337 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
338 | ||
339 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | |
340 | tx_beacon_cmd->tx.rate_n_flags = | |
341 | iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); | |
342 | else | |
343 | tx_beacon_cmd->tx.rate_n_flags = | |
344 | iwl_hw_set_rate_n_flags(rate, 0); | |
345 | ||
346 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
347 | TX_CMD_FLG_TSF_MSK | | |
348 | TX_CMD_FLG_STA_RATE_MSK; | |
349 | ||
350 | return sizeof(*tx_beacon_cmd) + frame_size; | |
351 | } | |
5b9f8cd3 | 352 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 353 | { |
fcab423d | 354 | struct iwl_frame *frame; |
b481de9c ZY |
355 | unsigned int frame_size; |
356 | int rc; | |
357 | u8 rate; | |
358 | ||
fcab423d | 359 | frame = iwl_get_free_frame(priv); |
b481de9c ZY |
360 | |
361 | if (!frame) { | |
15b1687c | 362 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
363 | "command.\n"); |
364 | return -ENOMEM; | |
365 | } | |
366 | ||
5b9f8cd3 | 367 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 368 | |
5b9f8cd3 | 369 | frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 370 | |
857485c0 | 371 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
372 | &frame->u.cmd[0]); |
373 | ||
fcab423d | 374 | iwl_free_frame(priv, frame); |
b481de9c ZY |
375 | |
376 | return rc; | |
377 | } | |
378 | ||
7aaa1d79 SO |
379 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
380 | { | |
381 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
382 | ||
383 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
384 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
385 | addr |= | |
386 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
387 | ||
388 | return addr; | |
389 | } | |
390 | ||
391 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
392 | { | |
393 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
394 | ||
395 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
396 | } | |
397 | ||
398 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
399 | dma_addr_t addr, u16 len) | |
400 | { | |
401 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
402 | u16 hi_n_len = len << 4; | |
403 | ||
404 | put_unaligned_le32(addr, &tb->lo); | |
405 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
406 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
407 | ||
408 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
409 | ||
410 | tfd->num_tbs = idx + 1; | |
411 | } | |
412 | ||
413 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
414 | { | |
415 | return tfd->num_tbs & 0x1f; | |
416 | } | |
417 | ||
418 | /** | |
419 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
420 | * @priv - driver private data | |
421 | * @txq - tx queue | |
422 | * | |
423 | * Does NOT advance any TFD circular buffer read/write indexes | |
424 | * Does NOT free the TFD itself (which is within circular buffer) | |
425 | */ | |
426 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
427 | { | |
59606ffa | 428 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
429 | struct iwl_tfd *tfd; |
430 | struct pci_dev *dev = priv->pci_dev; | |
431 | int index = txq->q.read_ptr; | |
432 | int i; | |
433 | int num_tbs; | |
434 | ||
435 | tfd = &tfd_tmp[index]; | |
436 | ||
437 | /* Sanity check on number of chunks */ | |
438 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
439 | ||
440 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
441 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
442 | /* @todo issue fatal error, it is quite serious situation */ | |
443 | return; | |
444 | } | |
445 | ||
446 | /* Unmap tx_cmd */ | |
447 | if (num_tbs) | |
448 | pci_unmap_single(dev, | |
c2acea8e JB |
449 | pci_unmap_addr(&txq->meta[index], mapping), |
450 | pci_unmap_len(&txq->meta[index], len), | |
96891cee | 451 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
452 | |
453 | /* Unmap chunks, if any. */ | |
454 | for (i = 1; i < num_tbs; i++) { | |
455 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
456 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
457 | ||
458 | if (txq->txb) { | |
459 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
460 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
461 | } | |
462 | } | |
463 | } | |
464 | ||
465 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
466 | struct iwl_tx_queue *txq, | |
467 | dma_addr_t addr, u16 len, | |
468 | u8 reset, u8 pad) | |
469 | { | |
470 | struct iwl_queue *q; | |
59606ffa | 471 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
472 | u32 num_tbs; |
473 | ||
474 | q = &txq->q; | |
59606ffa SO |
475 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
476 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
477 | |
478 | if (reset) | |
479 | memset(tfd, 0, sizeof(*tfd)); | |
480 | ||
481 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
482 | ||
483 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
484 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
485 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
486 | IWL_NUM_OF_TBS); | |
487 | return -EINVAL; | |
488 | } | |
489 | ||
490 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
491 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
492 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
493 | (unsigned long long)addr); | |
494 | ||
495 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
a8e74e27 SO |
500 | /* |
501 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
502 | * given Tx queue, and enable the DMA channel used for that queue. | |
503 | * | |
504 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
505 | * channels supported in hardware. | |
506 | */ | |
507 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
508 | struct iwl_tx_queue *txq) | |
509 | { | |
a8e74e27 SO |
510 | int txq_id = txq->q.id; |
511 | ||
a8e74e27 SO |
512 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
513 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
514 | txq->q.dma_addr >> 8); | |
515 | ||
a8e74e27 SO |
516 | return 0; |
517 | } | |
518 | ||
b481de9c ZY |
519 | /****************************************************************************** |
520 | * | |
521 | * Generic RX handler implementations | |
522 | * | |
523 | ******************************************************************************/ | |
885ba202 TW |
524 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
525 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 526 | { |
db11d634 | 527 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
885ba202 | 528 | struct iwl_alive_resp *palive; |
b481de9c ZY |
529 | struct delayed_work *pwork; |
530 | ||
531 | palive = &pkt->u.alive_frame; | |
532 | ||
e1623446 | 533 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
534 | "0x%01X 0x%01X\n", |
535 | palive->is_valid, palive->ver_type, | |
536 | palive->ver_subtype); | |
537 | ||
538 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 539 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
540 | memcpy(&priv->card_alive_init, |
541 | &pkt->u.alive_frame, | |
885ba202 | 542 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
543 | pwork = &priv->init_alive_start; |
544 | } else { | |
e1623446 | 545 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 546 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 547 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
548 | pwork = &priv->alive_start; |
549 | } | |
550 | ||
551 | /* We delay the ALIVE response by 5ms to | |
552 | * give the HW RF Kill time to activate... */ | |
553 | if (palive->is_valid == UCODE_VALID_OK) | |
554 | queue_delayed_work(priv->workqueue, pwork, | |
555 | msecs_to_jiffies(5)); | |
556 | else | |
39aadf8c | 557 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
558 | } |
559 | ||
5b9f8cd3 | 560 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 561 | { |
c79dd5b5 TW |
562 | struct iwl_priv *priv = |
563 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
564 | struct sk_buff *beacon; |
565 | ||
566 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 567 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
568 | |
569 | if (!beacon) { | |
15b1687c | 570 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
571 | return; |
572 | } | |
573 | ||
574 | mutex_lock(&priv->mutex); | |
575 | /* new beacon skb is allocated every time; dispose previous.*/ | |
576 | if (priv->ibss_beacon) | |
577 | dev_kfree_skb(priv->ibss_beacon); | |
578 | ||
579 | priv->ibss_beacon = beacon; | |
580 | mutex_unlock(&priv->mutex); | |
581 | ||
5b9f8cd3 | 582 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
583 | } |
584 | ||
4e39317d | 585 | /** |
5b9f8cd3 | 586 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
587 | * |
588 | * This callback is provided in order to send a statistics request. | |
589 | * | |
590 | * This timer function is continually reset to execute within | |
591 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
592 | * was received. We need to ensure we receive the statistics in order | |
593 | * to update the temperature used for calibrating the TXPOWER. | |
594 | */ | |
5b9f8cd3 | 595 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
596 | { |
597 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
598 | ||
599 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
600 | return; | |
601 | ||
61780ee3 MA |
602 | /* dont send host command if rf-kill is on */ |
603 | if (!iwl_is_ready_rf(priv)) | |
604 | return; | |
605 | ||
4e39317d EG |
606 | iwl_send_statistics_request(priv, CMD_ASYNC); |
607 | } | |
608 | ||
5b9f8cd3 | 609 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 610 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 611 | { |
0a6857e7 | 612 | #ifdef CONFIG_IWLWIFI_DEBUG |
db11d634 | 613 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
2aa6ab86 TW |
614 | struct iwl4965_beacon_notif *beacon = |
615 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 616 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 617 | |
e1623446 | 618 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 619 | "tsf %d %d rate %d\n", |
25a6572c | 620 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
621 | beacon->beacon_notify_hdr.failure_frame, |
622 | le32_to_cpu(beacon->ibss_mgr_status), | |
623 | le32_to_cpu(beacon->high_tsf), | |
624 | le32_to_cpu(beacon->low_tsf), rate); | |
625 | #endif | |
626 | ||
05c914fe | 627 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
628 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
629 | queue_work(priv->workqueue, &priv->beacon_update); | |
630 | } | |
631 | ||
b481de9c ZY |
632 | /* Handle notification from uCode that card's power state is changing |
633 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 634 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 635 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 636 | { |
db11d634 | 637 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
638 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
639 | unsigned long status = priv->status; | |
640 | ||
e1623446 | 641 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
642 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
643 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
644 | ||
645 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
646 | RF_CARD_DISABLED)) { | |
647 | ||
3395f6e9 | 648 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
649 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
650 | ||
a8b50a0a MA |
651 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
652 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
653 | |
654 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 655 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 656 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 657 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 658 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 659 | } |
39b73fb1 WYG |
660 | if (flags & RF_CARD_DISABLED) |
661 | iwl_tt_enter_ct_kill(priv); | |
b481de9c | 662 | } |
39b73fb1 WYG |
663 | if (!(flags & RF_CARD_DISABLED)) |
664 | iwl_tt_exit_ct_kill(priv); | |
b481de9c ZY |
665 | |
666 | if (flags & HW_CARD_DISABLED) | |
667 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
668 | else | |
669 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
670 | ||
671 | ||
b481de9c | 672 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 673 | iwl_scan_cancel(priv); |
b481de9c ZY |
674 | |
675 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
676 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
677 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
678 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
679 | else |
680 | wake_up_interruptible(&priv->wait_command_queue); | |
681 | } | |
682 | ||
5b9f8cd3 | 683 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 684 | { |
e2e3c57b | 685 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 686 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
687 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
688 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
689 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
690 | } else { | |
691 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
692 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
693 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
694 | } | |
695 | ||
a8b50a0a | 696 | return 0; |
e2e3c57b TW |
697 | } |
698 | ||
b481de9c | 699 | /** |
5b9f8cd3 | 700 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
701 | * |
702 | * Setup the RX handlers for each of the reply types sent from the uCode | |
703 | * to the host. | |
704 | * | |
705 | * This function chains into the hardware specific files for them to setup | |
706 | * any hardware specific handlers as well. | |
707 | */ | |
653fa4a0 | 708 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 709 | { |
885ba202 | 710 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
711 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
712 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
5b9f8cd3 | 713 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 714 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
715 | iwl_rx_pm_debug_statistics_notif; |
716 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 717 | |
9fbab516 BC |
718 | /* |
719 | * The same handler is used for both the REPLY to a discrete | |
720 | * statistics request from the host as well as for the periodic | |
721 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 722 | */ |
8f91aecb EG |
723 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics; |
724 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; | |
2a421b91 | 725 | |
21c339bf | 726 | iwl_setup_spectrum_handlers(priv); |
2a421b91 TW |
727 | iwl_setup_rx_scan_handlers(priv); |
728 | ||
37a44211 | 729 | /* status change handler */ |
5b9f8cd3 | 730 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 731 | |
c1354754 TW |
732 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
733 | iwl_rx_missed_beacon_notif; | |
37a44211 | 734 | /* Rx handlers */ |
1781a07f EG |
735 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy; |
736 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx; | |
653fa4a0 EG |
737 | /* block ack */ |
738 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba; | |
9fbab516 | 739 | /* Set up hardware specific Rx handlers */ |
d4789efe | 740 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
741 | } |
742 | ||
b481de9c | 743 | /** |
a55360e4 | 744 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
745 | * |
746 | * Uses the priv->rx_handlers callback function array to invoke | |
747 | * the appropriate handlers, including command responses, | |
748 | * frame-received notifications, and other notifications. | |
749 | */ | |
a55360e4 | 750 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 751 | { |
a55360e4 | 752 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 753 | struct iwl_rx_packet *pkt; |
a55360e4 | 754 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
755 | u32 r, i; |
756 | int reclaim; | |
757 | unsigned long flags; | |
5c0eef96 | 758 | u8 fill_rx = 0; |
d68ab680 | 759 | u32 count = 8; |
4752c93c | 760 | int total_empty; |
b481de9c | 761 | |
6440adb5 BC |
762 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
763 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 764 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
765 | i = rxq->read; |
766 | ||
767 | /* Rx interrupt, but nothing sent from uCode */ | |
768 | if (i == r) | |
e1623446 | 769 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 770 | |
4752c93c MA |
771 | /* calculate total frames need to be restock after handling RX */ |
772 | total_empty = r - priv->rxq.write_actual; | |
773 | if (total_empty < 0) | |
774 | total_empty += RX_QUEUE_SIZE; | |
775 | ||
776 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
777 | fill_rx = 1; |
778 | ||
b481de9c ZY |
779 | while (i != r) { |
780 | rxb = rxq->queue[i]; | |
781 | ||
9fbab516 | 782 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
783 | * then a bug has been introduced in the queue refilling |
784 | * routines -- catch it here */ | |
785 | BUG_ON(rxb == NULL); | |
786 | ||
787 | rxq->queue[i] = NULL; | |
788 | ||
df833b1d RC |
789 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
790 | priv->hw_params.rx_buf_size + 256, | |
791 | PCI_DMA_FROMDEVICE); | |
db11d634 | 792 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c | 793 | |
be1a71a1 JB |
794 | trace_iwlwifi_dev_rx(priv, pkt, |
795 | le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); | |
796 | ||
b481de9c ZY |
797 | /* Reclaim a command buffer only if this packet is a response |
798 | * to a (driver-originated) command. | |
799 | * If the packet (e.g. Rx frame) originated from uCode, | |
800 | * there is no command buffer to reclaim. | |
801 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
802 | * but apparently a few don't get set; catch them here. */ | |
803 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
804 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 805 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 806 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 807 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
808 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
809 | (pkt->hdr.cmd != REPLY_TX); | |
810 | ||
811 | /* Based on type of command response or notification, | |
812 | * handle those that need handling via function in | |
5b9f8cd3 | 813 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 814 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 815 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 816 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
b481de9c | 817 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
a83b9141 | 818 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
b481de9c ZY |
819 | } else { |
820 | /* No handling needed */ | |
e1623446 | 821 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
822 | "r %d i %d No handler needed for %s, 0x%02x\n", |
823 | r, i, get_cmd_string(pkt->hdr.cmd), | |
824 | pkt->hdr.cmd); | |
825 | } | |
826 | ||
827 | if (reclaim) { | |
9fbab516 | 828 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 829 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
830 | * as we reclaim the driver command queue */ |
831 | if (rxb && rxb->skb) | |
17b88929 | 832 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 833 | else |
39aadf8c | 834 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
835 | } |
836 | ||
837 | /* For now we just don't re-use anything. We can tweak this | |
838 | * later to try and re-use notification packets and SKBs that | |
839 | * fail to Rx correctly */ | |
840 | if (rxb->skb != NULL) { | |
841 | priv->alloc_rxb_skb--; | |
842 | dev_kfree_skb_any(rxb->skb); | |
843 | rxb->skb = NULL; | |
844 | } | |
845 | ||
b481de9c ZY |
846 | spin_lock_irqsave(&rxq->lock, flags); |
847 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
848 | spin_unlock_irqrestore(&rxq->lock, flags); | |
849 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
850 | /* If there are a lot of unused frames, |
851 | * restock the Rx queue so ucode wont assert. */ | |
852 | if (fill_rx) { | |
853 | count++; | |
854 | if (count >= 8) { | |
855 | priv->rxq.read = i; | |
4752c93c | 856 | iwl_rx_replenish_now(priv); |
5c0eef96 MA |
857 | count = 0; |
858 | } | |
859 | } | |
b481de9c ZY |
860 | } |
861 | ||
862 | /* Backtrack one entry */ | |
863 | priv->rxq.read = i; | |
4752c93c MA |
864 | if (fill_rx) |
865 | iwl_rx_replenish_now(priv); | |
866 | else | |
867 | iwl_rx_queue_restock(priv); | |
a55360e4 | 868 | } |
a55360e4 | 869 | |
0359facc MA |
870 | /* call this function to flush any scheduled tasklet */ |
871 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
872 | { | |
a96a27f9 | 873 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
874 | synchronize_irq(priv->pci_dev->irq); |
875 | tasklet_kill(&priv->irq_tasklet); | |
876 | } | |
877 | ||
ef850d7c | 878 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
879 | { |
880 | u32 inta, handled = 0; | |
881 | u32 inta_fh; | |
882 | unsigned long flags; | |
0a6857e7 | 883 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
884 | u32 inta_mask; |
885 | #endif | |
886 | ||
887 | spin_lock_irqsave(&priv->lock, flags); | |
888 | ||
889 | /* Ack/clear/reset pending uCode interrupts. | |
890 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
891 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
892 | inta = iwl_read32(priv, CSR_INT); |
893 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
894 | |
895 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
896 | * Any new interrupts that happen after this, either while we're | |
897 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
898 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
899 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 900 | |
0a6857e7 | 901 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 902 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 903 | /* just for debug */ |
3395f6e9 | 904 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 905 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
906 | inta, inta_mask, inta_fh); |
907 | } | |
908 | #endif | |
909 | ||
910 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
911 | * atomic, make sure that inta covers all the interrupts that | |
912 | * we've discovered, even if FH interrupt came in just after | |
913 | * reading CSR_INT. */ | |
6f83eaa1 | 914 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 915 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 916 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
917 | inta |= CSR_INT_BIT_FH_TX; |
918 | ||
919 | /* Now service all interrupt bits discovered above. */ | |
920 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 921 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
922 | |
923 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 924 | iwl_disable_interrupts(priv); |
b481de9c | 925 | |
a83b9141 | 926 | priv->isr_stats.hw++; |
5b9f8cd3 | 927 | iwl_irq_handle_error(priv); |
b481de9c ZY |
928 | |
929 | handled |= CSR_INT_BIT_HW_ERR; | |
930 | ||
931 | spin_unlock_irqrestore(&priv->lock, flags); | |
932 | ||
933 | return; | |
934 | } | |
935 | ||
0a6857e7 | 936 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 937 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 938 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 939 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 940 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 941 | "the frame/frames.\n"); |
a83b9141 WYG |
942 | priv->isr_stats.sch++; |
943 | } | |
b481de9c ZY |
944 | |
945 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 946 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 947 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
948 | priv->isr_stats.alive++; |
949 | } | |
b481de9c ZY |
950 | } |
951 | #endif | |
952 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 953 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 954 | |
9fbab516 | 955 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
956 | if (inta & CSR_INT_BIT_RF_KILL) { |
957 | int hw_rf_kill = 0; | |
3395f6e9 | 958 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
959 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
960 | hw_rf_kill = 1; | |
961 | ||
4c423a2b | 962 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 963 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 964 | |
a83b9141 WYG |
965 | priv->isr_stats.rfkill++; |
966 | ||
a9efa652 | 967 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
968 | * the driver allows loading the ucode even if the radio |
969 | * is killed. Hence update the killswitch state here. The | |
970 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 971 | */ |
6cd0b1cb HS |
972 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
973 | if (hw_rf_kill) | |
974 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
975 | else | |
976 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 977 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 978 | } |
b481de9c ZY |
979 | |
980 | handled |= CSR_INT_BIT_RF_KILL; | |
981 | } | |
982 | ||
9fbab516 | 983 | /* Chip got too hot and stopped itself */ |
b481de9c | 984 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 985 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 986 | priv->isr_stats.ctkill++; |
b481de9c ZY |
987 | handled |= CSR_INT_BIT_CT_KILL; |
988 | } | |
989 | ||
990 | /* Error detected by uCode */ | |
991 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
992 | IWL_ERR(priv, "Microcode SW error detected. " |
993 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
994 | priv->isr_stats.sw++; |
995 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 996 | iwl_irq_handle_error(priv); |
b481de9c ZY |
997 | handled |= CSR_INT_BIT_SW_ERR; |
998 | } | |
999 | ||
1000 | /* uCode wakes up after power-down sleep */ | |
1001 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1002 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1003 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
babcebfa TW |
1004 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1005 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1006 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1007 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1008 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1009 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1010 | |
a83b9141 WYG |
1011 | priv->isr_stats.wakeup++; |
1012 | ||
b481de9c ZY |
1013 | handled |= CSR_INT_BIT_WAKEUP; |
1014 | } | |
1015 | ||
1016 | /* All uCode command responses, including Tx command responses, | |
1017 | * Rx "responses" (frame-received notification), and other | |
1018 | * notifications from uCode come through here*/ | |
1019 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1020 | iwl_rx_handle(priv); |
a83b9141 | 1021 | priv->isr_stats.rx++; |
b481de9c ZY |
1022 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1023 | } | |
1024 | ||
1025 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1026 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
a83b9141 | 1027 | priv->isr_stats.tx++; |
b481de9c | 1028 | handled |= CSR_INT_BIT_FH_TX; |
dbb983b7 RR |
1029 | /* FH finished to write, send event */ |
1030 | priv->ucode_write_complete = 1; | |
1031 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1032 | } |
1033 | ||
a83b9141 | 1034 | if (inta & ~handled) { |
15b1687c | 1035 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1036 | priv->isr_stats.unhandled++; |
1037 | } | |
b481de9c | 1038 | |
40cefda9 | 1039 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1040 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1041 | inta & ~priv->inta_mask); |
39aadf8c | 1042 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1043 | } |
1044 | ||
1045 | /* Re-enable all interrupts */ | |
0359facc MA |
1046 | /* only Re-enable if diabled by irq */ |
1047 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1048 | iwl_enable_interrupts(priv); |
b481de9c | 1049 | |
0a6857e7 | 1050 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1051 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1052 | inta = iwl_read32(priv, CSR_INT); |
1053 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1054 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1055 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1056 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1057 | } | |
1058 | #endif | |
1059 | spin_unlock_irqrestore(&priv->lock, flags); | |
1060 | } | |
1061 | ||
ef850d7c MA |
1062 | /* tasklet for iwlagn interrupt */ |
1063 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1064 | { | |
1065 | u32 inta = 0; | |
1066 | u32 handled = 0; | |
1067 | unsigned long flags; | |
1068 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1069 | u32 inta_mask; | |
1070 | #endif | |
1071 | ||
1072 | spin_lock_irqsave(&priv->lock, flags); | |
1073 | ||
1074 | /* Ack/clear/reset pending uCode interrupts. | |
1075 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1076 | */ | |
1077 | iwl_write32(priv, CSR_INT, priv->inta); | |
1078 | ||
1079 | inta = priv->inta; | |
1080 | ||
1081 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1082 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1083 | /* just for debug */ |
1084 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1085 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1086 | inta, inta_mask); | |
1087 | } | |
1088 | #endif | |
1089 | /* saved interrupt in inta variable now we can reset priv->inta */ | |
1090 | priv->inta = 0; | |
1091 | ||
1092 | /* Now service all interrupt bits discovered above. */ | |
1093 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1094 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1095 | |
1096 | /* Tell the device to stop sending interrupts */ | |
1097 | iwl_disable_interrupts(priv); | |
1098 | ||
1099 | priv->isr_stats.hw++; | |
1100 | iwl_irq_handle_error(priv); | |
1101 | ||
1102 | handled |= CSR_INT_BIT_HW_ERR; | |
1103 | ||
1104 | spin_unlock_irqrestore(&priv->lock, flags); | |
1105 | ||
1106 | return; | |
1107 | } | |
1108 | ||
1109 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1110 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1111 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1112 | if (inta & CSR_INT_BIT_SCD) { | |
1113 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1114 | "the frame/frames.\n"); | |
1115 | priv->isr_stats.sch++; | |
1116 | } | |
1117 | ||
1118 | /* Alive notification via Rx interrupt will do the real work */ | |
1119 | if (inta & CSR_INT_BIT_ALIVE) { | |
1120 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1121 | priv->isr_stats.alive++; | |
1122 | } | |
1123 | } | |
1124 | #endif | |
1125 | /* Safely ignore these bits for debug checks below */ | |
1126 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1127 | ||
1128 | /* HW RF KILL switch toggled */ | |
1129 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1130 | int hw_rf_kill = 0; | |
1131 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1132 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1133 | hw_rf_kill = 1; | |
1134 | ||
4c423a2b | 1135 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1136 | hw_rf_kill ? "disable radio" : "enable radio"); |
1137 | ||
1138 | priv->isr_stats.rfkill++; | |
1139 | ||
1140 | /* driver only loads ucode once setting the interface up. | |
1141 | * the driver allows loading the ucode even if the radio | |
1142 | * is killed. Hence update the killswitch state here. The | |
1143 | * rfkill handler will care about restarting if needed. | |
1144 | */ | |
1145 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1146 | if (hw_rf_kill) | |
1147 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1148 | else | |
1149 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1150 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1151 | } |
1152 | ||
1153 | handled |= CSR_INT_BIT_RF_KILL; | |
1154 | } | |
1155 | ||
1156 | /* Chip got too hot and stopped itself */ | |
1157 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1158 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1159 | priv->isr_stats.ctkill++; | |
1160 | handled |= CSR_INT_BIT_CT_KILL; | |
1161 | } | |
1162 | ||
1163 | /* Error detected by uCode */ | |
1164 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1165 | IWL_ERR(priv, "Microcode SW error detected. " | |
1166 | " Restarting 0x%X.\n", inta); | |
1167 | priv->isr_stats.sw++; | |
1168 | priv->isr_stats.sw_err = inta; | |
1169 | iwl_irq_handle_error(priv); | |
1170 | handled |= CSR_INT_BIT_SW_ERR; | |
1171 | } | |
1172 | ||
1173 | /* uCode wakes up after power-down sleep */ | |
1174 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1175 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1176 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
1177 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); | |
1178 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1179 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1180 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1181 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1182 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
1183 | ||
1184 | priv->isr_stats.wakeup++; | |
1185 | ||
1186 | handled |= CSR_INT_BIT_WAKEUP; | |
1187 | } | |
1188 | ||
1189 | /* All uCode command responses, including Tx command responses, | |
1190 | * Rx "responses" (frame-received notification), and other | |
1191 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1192 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1193 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1194 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1195 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1196 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1197 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1198 | CSR49_FH_INT_RX_MASK); | |
1199 | } | |
1200 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1201 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1202 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1203 | } | |
1204 | /* Sending RX interrupt require many steps to be done in the | |
1205 | * the device: | |
1206 | * 1- write interrupt to current index in ICT table. | |
1207 | * 2- dma RX frame. | |
1208 | * 3- update RX shared data to indicate last write index. | |
1209 | * 4- send interrupt. | |
1210 | * This could lead to RX race, driver could receive RX interrupt | |
1211 | * but the shared data changes does not reflect this. | |
1212 | * this could lead to RX race, RX periodic will solve this race | |
1213 | */ | |
1214 | iwl_write32(priv, CSR_INT_PERIODIC_REG, | |
1215 | CSR_INT_PERIODIC_DIS); | |
ef850d7c | 1216 | iwl_rx_handle(priv); |
40cefda9 MA |
1217 | /* Only set RX periodic if real RX is received. */ |
1218 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1219 | iwl_write32(priv, CSR_INT_PERIODIC_REG, | |
1220 | CSR_INT_PERIODIC_ENA); | |
1221 | ||
ef850d7c | 1222 | priv->isr_stats.rx++; |
ef850d7c MA |
1223 | } |
1224 | ||
1225 | if (inta & CSR_INT_BIT_FH_TX) { | |
1226 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
1227 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); | |
1228 | priv->isr_stats.tx++; | |
1229 | handled |= CSR_INT_BIT_FH_TX; | |
1230 | /* FH finished to write, send event */ | |
1231 | priv->ucode_write_complete = 1; | |
1232 | wake_up_interruptible(&priv->wait_command_queue); | |
1233 | } | |
1234 | ||
1235 | if (inta & ~handled) { | |
1236 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1237 | priv->isr_stats.unhandled++; | |
1238 | } | |
1239 | ||
40cefda9 | 1240 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1241 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1242 | inta & ~priv->inta_mask); |
ef850d7c MA |
1243 | } |
1244 | ||
1245 | ||
1246 | /* Re-enable all interrupts */ | |
1247 | /* only Re-enable if diabled by irq */ | |
1248 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1249 | iwl_enable_interrupts(priv); | |
1250 | ||
1251 | spin_unlock_irqrestore(&priv->lock, flags); | |
1252 | ||
1253 | } | |
1254 | ||
a83b9141 | 1255 | |
b481de9c ZY |
1256 | /****************************************************************************** |
1257 | * | |
1258 | * uCode download functions | |
1259 | * | |
1260 | ******************************************************************************/ | |
1261 | ||
5b9f8cd3 | 1262 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1263 | { |
98c92211 TW |
1264 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1265 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1266 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1267 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1268 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1269 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1270 | } |
1271 | ||
5b9f8cd3 | 1272 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1273 | { |
1274 | /* Remove all resets to allow NIC to operate */ | |
1275 | iwl_write32(priv, CSR_RESET, 0); | |
1276 | } | |
1277 | ||
1278 | ||
b481de9c | 1279 | /** |
5b9f8cd3 | 1280 | * iwl_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
1281 | * |
1282 | * Copy into buffers for card to fetch via bus-mastering | |
1283 | */ | |
5b9f8cd3 | 1284 | static int iwl_read_ucode(struct iwl_priv *priv) |
b481de9c | 1285 | { |
cc0f555d | 1286 | struct iwl_ucode_header *ucode; |
a0987a8d | 1287 | int ret = -EINVAL, index; |
b481de9c | 1288 | const struct firmware *ucode_raw; |
a0987a8d RC |
1289 | const char *name_pre = priv->cfg->fw_name_pre; |
1290 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
1291 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
1292 | char buf[25]; | |
b481de9c ZY |
1293 | u8 *src; |
1294 | size_t len; | |
cc0f555d JS |
1295 | u32 api_ver, build; |
1296 | u32 inst_size, data_size, init_size, init_data_size, boot_size; | |
abdc2d62 | 1297 | u16 eeprom_ver; |
b481de9c ZY |
1298 | |
1299 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
1300 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
1301 | for (index = api_max; index >= api_min; index--) { |
1302 | sprintf(buf, "%s%d%s", name_pre, index, ".ucode"); | |
1303 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
1304 | if (ret < 0) { | |
15b1687c | 1305 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
1306 | buf, ret); |
1307 | if (ret == -ENOENT) | |
1308 | continue; | |
1309 | else | |
1310 | goto error; | |
1311 | } else { | |
1312 | if (index < api_max) | |
15b1687c WT |
1313 | IWL_ERR(priv, "Loaded firmware %s, " |
1314 | "which is deprecated. " | |
1315 | "Please use API v%u instead.\n", | |
a0987a8d | 1316 | buf, api_max); |
15b1687c | 1317 | |
e1623446 | 1318 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n", |
a0987a8d RC |
1319 | buf, ucode_raw->size); |
1320 | break; | |
1321 | } | |
b481de9c ZY |
1322 | } |
1323 | ||
a0987a8d RC |
1324 | if (ret < 0) |
1325 | goto error; | |
b481de9c | 1326 | |
cc0f555d JS |
1327 | /* Make sure that we got at least the v1 header! */ |
1328 | if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) { | |
15b1687c | 1329 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 1330 | ret = -EINVAL; |
b481de9c ZY |
1331 | goto err_release; |
1332 | } | |
1333 | ||
1334 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1335 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1336 | |
c02b3acd | 1337 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 1338 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
cc0f555d JS |
1339 | build = priv->cfg->ops->ucode->get_build(ucode, api_ver); |
1340 | inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver); | |
1341 | data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver); | |
1342 | init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver); | |
1343 | init_data_size = | |
1344 | priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver); | |
1345 | boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver); | |
1346 | src = priv->cfg->ops->ucode->get_data(ucode, api_ver); | |
b481de9c | 1347 | |
a0987a8d RC |
1348 | /* api_ver should match the api version forming part of the |
1349 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 1350 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
1351 | |
1352 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 1353 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1354 | "Driver supports v%u, firmware is v%u.\n", |
1355 | api_max, api_ver); | |
1356 | priv->ucode_ver = 0; | |
1357 | ret = -EINVAL; | |
1358 | goto err_release; | |
1359 | } | |
1360 | if (api_ver != api_max) | |
978785a3 | 1361 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1362 | "got v%u. New firmware can be obtained " |
1363 | "from http://www.intellinuxwireless.org.\n", | |
1364 | api_max, api_ver); | |
1365 | ||
978785a3 TW |
1366 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
1367 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1368 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1369 | IWL_UCODE_API(priv->ucode_ver), | |
1370 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d | 1371 | |
cc0f555d JS |
1372 | if (build) |
1373 | IWL_DEBUG_INFO(priv, "Build %u\n", build); | |
1374 | ||
abdc2d62 JS |
1375 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); |
1376 | IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n", | |
1377 | (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) | |
1378 | ? "OTP" : "EEPROM", eeprom_ver); | |
1379 | ||
e1623446 | 1380 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 1381 | priv->ucode_ver); |
e1623446 | 1382 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
b481de9c | 1383 | inst_size); |
e1623446 | 1384 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", |
b481de9c | 1385 | data_size); |
e1623446 | 1386 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", |
b481de9c | 1387 | init_size); |
e1623446 | 1388 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", |
b481de9c | 1389 | init_data_size); |
e1623446 | 1390 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", |
b481de9c ZY |
1391 | boot_size); |
1392 | ||
1393 | /* Verify size of file vs. image size info in file's header */ | |
cc0f555d JS |
1394 | if (ucode_raw->size != |
1395 | priv->cfg->ops->ucode->get_header_size(api_ver) + | |
b481de9c ZY |
1396 | inst_size + data_size + init_size + |
1397 | init_data_size + boot_size) { | |
1398 | ||
cc0f555d JS |
1399 | IWL_DEBUG_INFO(priv, |
1400 | "uCode file size %d does not match expected size\n", | |
1401 | (int)ucode_raw->size); | |
90e759d1 | 1402 | ret = -EINVAL; |
b481de9c ZY |
1403 | goto err_release; |
1404 | } | |
1405 | ||
1406 | /* Verify that uCode images will fit in card's SRAM */ | |
099b40b7 | 1407 | if (inst_size > priv->hw_params.max_inst_size) { |
e1623446 | 1408 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
1409 | inst_size); |
1410 | ret = -EINVAL; | |
b481de9c ZY |
1411 | goto err_release; |
1412 | } | |
1413 | ||
099b40b7 | 1414 | if (data_size > priv->hw_params.max_data_size) { |
e1623446 | 1415 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
1416 | data_size); |
1417 | ret = -EINVAL; | |
b481de9c ZY |
1418 | goto err_release; |
1419 | } | |
099b40b7 | 1420 | if (init_size > priv->hw_params.max_inst_size) { |
e1623446 TW |
1421 | IWL_INFO(priv, "uCode init instr len %d too large to fit in\n", |
1422 | init_size); | |
90e759d1 | 1423 | ret = -EINVAL; |
b481de9c ZY |
1424 | goto err_release; |
1425 | } | |
099b40b7 | 1426 | if (init_data_size > priv->hw_params.max_data_size) { |
e1623446 | 1427 | IWL_INFO(priv, "uCode init data len %d too large to fit in\n", |
90e759d1 TW |
1428 | init_data_size); |
1429 | ret = -EINVAL; | |
b481de9c ZY |
1430 | goto err_release; |
1431 | } | |
099b40b7 | 1432 | if (boot_size > priv->hw_params.max_bsm_size) { |
e1623446 TW |
1433 | IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n", |
1434 | boot_size); | |
90e759d1 | 1435 | ret = -EINVAL; |
b481de9c ZY |
1436 | goto err_release; |
1437 | } | |
1438 | ||
1439 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1440 | ||
1441 | /* Runtime instructions and 2 copies of data: | |
1442 | * 1) unmodified from disk | |
1443 | * 2) backup cache for save/restore during power-downs */ | |
1444 | priv->ucode_code.len = inst_size; | |
98c92211 | 1445 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
1446 | |
1447 | priv->ucode_data.len = data_size; | |
98c92211 | 1448 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
1449 | |
1450 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 1451 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1452 | |
1f304e4e ZY |
1453 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1454 | !priv->ucode_data_backup.v_addr) | |
1455 | goto err_pci_alloc; | |
1456 | ||
b481de9c | 1457 | /* Initialization instructions and data */ |
90e759d1 TW |
1458 | if (init_size && init_data_size) { |
1459 | priv->ucode_init.len = init_size; | |
98c92211 | 1460 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
1461 | |
1462 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 1463 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1464 | |
1465 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1466 | goto err_pci_alloc; | |
1467 | } | |
b481de9c ZY |
1468 | |
1469 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
1470 | if (boot_size) { |
1471 | priv->ucode_boot.len = boot_size; | |
98c92211 | 1472 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1473 | |
90e759d1 TW |
1474 | if (!priv->ucode_boot.v_addr) |
1475 | goto err_pci_alloc; | |
1476 | } | |
b481de9c ZY |
1477 | |
1478 | /* Copy images into buffers for card's bus-master reads ... */ | |
1479 | ||
1480 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 1481 | len = inst_size; |
e1623446 | 1482 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c | 1483 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
1484 | src += len; |
1485 | ||
e1623446 | 1486 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1487 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1488 | ||
1489 | /* Runtime data (2nd block) | |
5b9f8cd3 | 1490 | * NOTE: Copy into backup buffer will be done in iwl_up() */ |
cc0f555d | 1491 | len = data_size; |
e1623446 | 1492 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
1493 | memcpy(priv->ucode_data.v_addr, src, len); |
1494 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 1495 | src += len; |
b481de9c ZY |
1496 | |
1497 | /* Initialization instructions (3rd block) */ | |
1498 | if (init_size) { | |
cc0f555d | 1499 | len = init_size; |
e1623446 | 1500 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
90e759d1 | 1501 | len); |
b481de9c | 1502 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 1503 | src += len; |
b481de9c ZY |
1504 | } |
1505 | ||
1506 | /* Initialization data (4th block) */ | |
1507 | if (init_data_size) { | |
cc0f555d | 1508 | len = init_data_size; |
e1623446 | 1509 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
90e759d1 | 1510 | len); |
b481de9c | 1511 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 1512 | src += len; |
b481de9c ZY |
1513 | } |
1514 | ||
1515 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 1516 | len = boot_size; |
e1623446 | 1517 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
1518 | memcpy(priv->ucode_boot.v_addr, src, len); |
1519 | ||
1520 | /* We have our copies now, allow OS release its copies */ | |
1521 | release_firmware(ucode_raw); | |
1522 | return 0; | |
1523 | ||
1524 | err_pci_alloc: | |
15b1687c | 1525 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 1526 | ret = -ENOMEM; |
5b9f8cd3 | 1527 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
1528 | |
1529 | err_release: | |
1530 | release_firmware(ucode_raw); | |
1531 | ||
1532 | error: | |
90e759d1 | 1533 | return ret; |
b481de9c ZY |
1534 | } |
1535 | ||
b7a79404 RC |
1536 | #ifdef CONFIG_IWLWIFI_DEBUG |
1537 | static const char *desc_lookup_text[] = { | |
1538 | "OK", | |
1539 | "FAIL", | |
1540 | "BAD_PARAM", | |
1541 | "BAD_CHECKSUM", | |
1542 | "NMI_INTERRUPT_WDG", | |
1543 | "SYSASSERT", | |
1544 | "FATAL_ERROR", | |
1545 | "BAD_COMMAND", | |
1546 | "HW_ERROR_TUNE_LOCK", | |
1547 | "HW_ERROR_TEMPERATURE", | |
1548 | "ILLEGAL_CHAN_FREQ", | |
1549 | "VCC_NOT_STABLE", | |
1550 | "FH_ERROR", | |
1551 | "NMI_INTERRUPT_HOST", | |
1552 | "NMI_INTERRUPT_ACTION_PT", | |
1553 | "NMI_INTERRUPT_UNKNOWN", | |
1554 | "UCODE_VERSION_MISMATCH", | |
1555 | "HW_ERROR_ABS_LOCK", | |
1556 | "HW_ERROR_CAL_LOCK_FAIL", | |
1557 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1558 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1559 | "NMI_TRM_HW_ER", | |
1560 | "NMI_INTERRUPT_TRM", | |
1561 | "NMI_INTERRUPT_BREAK_POINT" | |
1562 | "DEBUG_0", | |
1563 | "DEBUG_1", | |
1564 | "DEBUG_2", | |
1565 | "DEBUG_3", | |
1566 | "UNKNOWN" | |
1567 | }; | |
1568 | ||
1569 | static const char *desc_lookup(int i) | |
1570 | { | |
1571 | int max = ARRAY_SIZE(desc_lookup_text) - 1; | |
1572 | ||
1573 | if (i < 0 || i > max) | |
1574 | i = max; | |
1575 | ||
1576 | return desc_lookup_text[i]; | |
1577 | } | |
1578 | ||
1579 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1580 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1581 | ||
1582 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1583 | { | |
1584 | u32 data2, line; | |
1585 | u32 desc, time, count, base, data1; | |
1586 | u32 blink1, blink2, ilink1, ilink2; | |
1587 | ||
1588 | if (priv->ucode_type == UCODE_INIT) | |
1589 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
1590 | else | |
1591 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1592 | ||
1593 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
1594 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); | |
1595 | return; | |
1596 | } | |
1597 | ||
1598 | count = iwl_read_targ_mem(priv, base); | |
1599 | ||
1600 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
1601 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
1602 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1603 | priv->status, count); | |
1604 | } | |
1605 | ||
1606 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
1607 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
1608 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
1609 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
1610 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
1611 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
1612 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
1613 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
1614 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
1615 | ||
be1a71a1 JB |
1616 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
1617 | blink1, blink2, ilink1, ilink2); | |
1618 | ||
b7a79404 RC |
1619 | IWL_ERR(priv, "Desc Time " |
1620 | "data1 data2 line\n"); | |
1621 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", | |
1622 | desc_lookup(desc), desc, time, data1, data2, line); | |
1623 | IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n"); | |
1624 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
1625 | ilink1, ilink2); | |
1626 | ||
1627 | } | |
1628 | ||
1629 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
1630 | ||
1631 | /** | |
1632 | * iwl_print_event_log - Dump error event log to syslog | |
1633 | * | |
1634 | */ | |
1635 | static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | |
1636 | u32 num_events, u32 mode) | |
1637 | { | |
1638 | u32 i; | |
1639 | u32 base; /* SRAM byte address of event log header */ | |
1640 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1641 | u32 ptr; /* SRAM byte address of log data */ | |
1642 | u32 ev, time, data; /* event log data */ | |
1643 | ||
1644 | if (num_events == 0) | |
1645 | return; | |
1646 | if (priv->ucode_type == UCODE_INIT) | |
1647 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1648 | else | |
1649 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1650 | ||
1651 | if (mode == 0) | |
1652 | event_size = 2 * sizeof(u32); | |
1653 | else | |
1654 | event_size = 3 * sizeof(u32); | |
1655 | ||
1656 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1657 | ||
1658 | /* "time" is actually "data" for mode 0 (no timestamp). | |
1659 | * place event id # at far right for easier visual parsing. */ | |
1660 | for (i = 0; i < num_events; i++) { | |
1661 | ev = iwl_read_targ_mem(priv, ptr); | |
1662 | ptr += sizeof(u32); | |
1663 | time = iwl_read_targ_mem(priv, ptr); | |
1664 | ptr += sizeof(u32); | |
1665 | if (mode == 0) { | |
1666 | /* data, ev */ | |
be1a71a1 | 1667 | trace_iwlwifi_dev_ucode_event(priv, 0, time, ev); |
b7a79404 RC |
1668 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev); |
1669 | } else { | |
1670 | data = iwl_read_targ_mem(priv, ptr); | |
1671 | ptr += sizeof(u32); | |
1672 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
1673 | time, data, ev); | |
be1a71a1 | 1674 | trace_iwlwifi_dev_ucode_event(priv, time, data, ev); |
b7a79404 RC |
1675 | } |
1676 | } | |
1677 | } | |
1678 | ||
1679 | void iwl_dump_nic_event_log(struct iwl_priv *priv) | |
1680 | { | |
1681 | u32 base; /* SRAM byte address of event log header */ | |
1682 | u32 capacity; /* event log capacity in # entries */ | |
1683 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1684 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1685 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1686 | u32 size; /* # entries that we'll print */ | |
1687 | ||
1688 | if (priv->ucode_type == UCODE_INIT) | |
1689 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1690 | else | |
1691 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1692 | ||
1693 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
1694 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); | |
1695 | return; | |
1696 | } | |
1697 | ||
1698 | /* event log header */ | |
1699 | capacity = iwl_read_targ_mem(priv, base); | |
1700 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1701 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1702 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
1703 | ||
1704 | size = num_wraps ? capacity : next_entry; | |
1705 | ||
1706 | /* bail out if nothing in log */ | |
1707 | if (size == 0) { | |
1708 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
1709 | return; | |
1710 | } | |
1711 | ||
1712 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", | |
1713 | size, num_wraps); | |
1714 | ||
1715 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
1716 | * i.e the next one that uCode would fill. */ | |
1717 | if (num_wraps) | |
1718 | iwl_print_event_log(priv, next_entry, | |
1719 | capacity - next_entry, mode); | |
1720 | /* (then/else) start at top of log */ | |
1721 | iwl_print_event_log(priv, 0, next_entry, mode); | |
1722 | ||
1723 | } | |
1724 | #endif | |
1725 | ||
b481de9c | 1726 | /** |
4a4a9e81 | 1727 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 1728 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 1729 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 1730 | */ |
4a4a9e81 | 1731 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 1732 | { |
57aab75a | 1733 | int ret = 0; |
b481de9c | 1734 | |
e1623446 | 1735 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
1736 | |
1737 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
1738 | /* We had an error bringing up the hardware, so take it | |
1739 | * all the way back down so we can try again */ | |
e1623446 | 1740 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
1741 | goto restart; |
1742 | } | |
1743 | ||
1744 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
1745 | * This is a paranoid check, because we would not have gotten the | |
1746 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 1747 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
1748 | /* Runtime instruction load was bad; |
1749 | * take it all the way back down so we can try again */ | |
e1623446 | 1750 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
1751 | goto restart; |
1752 | } | |
1753 | ||
c587de0b | 1754 | iwl_clear_stations_table(priv); |
57aab75a TW |
1755 | ret = priv->cfg->ops->lib->alive_notify(priv); |
1756 | if (ret) { | |
39aadf8c WT |
1757 | IWL_WARN(priv, |
1758 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
1759 | goto restart; |
1760 | } | |
1761 | ||
5b9f8cd3 | 1762 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
1763 | set_bit(STATUS_ALIVE, &priv->status); |
1764 | ||
fee1247a | 1765 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
1766 | return; |
1767 | ||
36d6825b | 1768 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
1769 | |
1770 | priv->active_rate = priv->rates_mask; | |
1771 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
1772 | ||
2f748dec WYG |
1773 | /* Configure Tx antenna selection based on H/W config */ |
1774 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
1775 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
1776 | ||
3109ece1 | 1777 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
1778 | struct iwl_rxon_cmd *active_rxon = |
1779 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
1780 | /* apply any changes in staging */ |
1781 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
1782 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
1783 | } else { | |
1784 | /* Initialize our rx_config data */ | |
5b9f8cd3 | 1785 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
45823531 AK |
1786 | |
1787 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
1788 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
1789 | ||
b481de9c ZY |
1790 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1791 | } | |
1792 | ||
9fbab516 | 1793 | /* Configure Bluetooth device coexistence support */ |
5b9f8cd3 | 1794 | iwl_send_bt_config(priv); |
b481de9c | 1795 | |
4a4a9e81 TW |
1796 | iwl_reset_run_time_calib(priv); |
1797 | ||
b481de9c | 1798 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 1799 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
1800 | |
1801 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 1802 | iwl_rf_kill_ct_config(priv); |
5a66926a | 1803 | |
fe00b5a5 RC |
1804 | iwl_leds_register(priv); |
1805 | ||
e1623446 | 1806 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 1807 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 1808 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 1809 | |
e312c24c | 1810 | iwl_power_update_mode(priv, true); |
c46fbefa | 1811 | |
ada17513 MA |
1812 | /* reassociate for ADHOC mode */ |
1813 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
1814 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
1815 | priv->vif); | |
1816 | if (beacon) | |
1817 | iwl_mac_beacon_update(priv->hw, beacon); | |
1818 | } | |
1819 | ||
1820 | ||
c46fbefa | 1821 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
5b9f8cd3 | 1822 | iwl_set_mode(priv, priv->iw_mode); |
c46fbefa | 1823 | |
b481de9c ZY |
1824 | return; |
1825 | ||
1826 | restart: | |
1827 | queue_work(priv->workqueue, &priv->restart); | |
1828 | } | |
1829 | ||
4e39317d | 1830 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 1831 | |
5b9f8cd3 | 1832 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1833 | { |
1834 | unsigned long flags; | |
1835 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 1836 | |
e1623446 | 1837 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 1838 | |
b481de9c ZY |
1839 | if (!exit_pending) |
1840 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
1841 | ||
ab53d8af MA |
1842 | iwl_leds_unregister(priv); |
1843 | ||
c587de0b | 1844 | iwl_clear_stations_table(priv); |
b481de9c ZY |
1845 | |
1846 | /* Unblock any waiting calls */ | |
1847 | wake_up_interruptible_all(&priv->wait_command_queue); | |
1848 | ||
b481de9c ZY |
1849 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
1850 | * exiting the module */ | |
1851 | if (!exit_pending) | |
1852 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
1853 | ||
1854 | /* stop and reset the on-board processor */ | |
3395f6e9 | 1855 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
1856 | |
1857 | /* tell the device to stop sending interrupts */ | |
0359facc | 1858 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 1859 | iwl_disable_interrupts(priv); |
0359facc MA |
1860 | spin_unlock_irqrestore(&priv->lock, flags); |
1861 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
1862 | |
1863 | if (priv->mac80211_registered) | |
1864 | ieee80211_stop_queues(priv->hw); | |
1865 | ||
5b9f8cd3 | 1866 | /* If we have not previously called iwl_init() then |
a60e77e5 | 1867 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 1868 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
1869 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1870 | STATUS_RF_KILL_HW | | |
9788864e RC |
1871 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1872 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
1873 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
1874 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
1875 | goto exit; |
1876 | } | |
1877 | ||
6da3a13e | 1878 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 1879 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
1880 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1881 | STATUS_RF_KILL_HW | | |
9788864e RC |
1882 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1883 | STATUS_GEO_CONFIGURED | | |
b481de9c | 1884 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
1885 | STATUS_FW_ERROR | |
1886 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
1887 | STATUS_EXIT_PENDING; | |
b481de9c | 1888 | |
ef850d7c MA |
1889 | /* device going down, Stop using ICT table */ |
1890 | iwl_disable_ict(priv); | |
b481de9c | 1891 | spin_lock_irqsave(&priv->lock, flags); |
3395f6e9 | 1892 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 1893 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
1894 | spin_unlock_irqrestore(&priv->lock, flags); |
1895 | ||
da1bc453 | 1896 | iwl_txq_ctx_stop(priv); |
b3bbacb7 | 1897 | iwl_rxq_stop(priv); |
b481de9c | 1898 | |
a8b50a0a MA |
1899 | iwl_write_prph(priv, APMG_CLK_DIS_REG, |
1900 | APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
1901 | |
1902 | udelay(5); | |
1903 | ||
7f066108 | 1904 | /* FIXME: apm_ops.suspend(priv) */ |
6da3a13e | 1905 | if (exit_pending) |
d535311e GG |
1906 | priv->cfg->ops->lib->apm_ops.stop(priv); |
1907 | else | |
1908 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
b481de9c | 1909 | exit: |
885ba202 | 1910 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
1911 | |
1912 | if (priv->ibss_beacon) | |
1913 | dev_kfree_skb(priv->ibss_beacon); | |
1914 | priv->ibss_beacon = NULL; | |
1915 | ||
1916 | /* clear out any free frames */ | |
fcab423d | 1917 | iwl_clear_free_frames(priv); |
b481de9c ZY |
1918 | } |
1919 | ||
5b9f8cd3 | 1920 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1921 | { |
1922 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1923 | __iwl_down(priv); |
b481de9c | 1924 | mutex_unlock(&priv->mutex); |
b24d22b1 | 1925 | |
4e39317d | 1926 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
1927 | } |
1928 | ||
086ed117 MA |
1929 | #define HW_READY_TIMEOUT (50) |
1930 | ||
1931 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
1932 | { | |
1933 | int ret = 0; | |
1934 | ||
1935 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1936 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
1937 | ||
1938 | /* See if we got it */ | |
1939 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1940 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1941 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1942 | HW_READY_TIMEOUT); | |
1943 | if (ret != -ETIMEDOUT) | |
1944 | priv->hw_ready = true; | |
1945 | else | |
1946 | priv->hw_ready = false; | |
1947 | ||
1948 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
1949 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
1950 | return ret; | |
1951 | } | |
1952 | ||
1953 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
1954 | { | |
1955 | int ret = 0; | |
1956 | ||
1957 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n"); | |
1958 | ||
3354a0f6 MA |
1959 | ret = iwl_set_hw_ready(priv); |
1960 | if (priv->hw_ready) | |
1961 | return ret; | |
1962 | ||
1963 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
1964 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
1965 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
1966 | ||
1967 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1968 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
1969 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
1970 | ||
3354a0f6 | 1971 | /* HW should be ready by now, check again. */ |
086ed117 MA |
1972 | if (ret != -ETIMEDOUT) |
1973 | iwl_set_hw_ready(priv); | |
1974 | ||
1975 | return ret; | |
1976 | } | |
1977 | ||
b481de9c ZY |
1978 | #define MAX_HW_RESTARTS 5 |
1979 | ||
5b9f8cd3 | 1980 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 1981 | { |
57aab75a TW |
1982 | int i; |
1983 | int ret; | |
b481de9c ZY |
1984 | |
1985 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 1986 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
1987 | return -EIO; |
1988 | } | |
1989 | ||
e903fbd4 | 1990 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 1991 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
1992 | return -EIO; |
1993 | } | |
1994 | ||
086ed117 MA |
1995 | iwl_prepare_card_hw(priv); |
1996 | ||
1997 | if (!priv->hw_ready) { | |
1998 | IWL_WARN(priv, "Exit HW not ready\n"); | |
1999 | return -EIO; | |
2000 | } | |
2001 | ||
e655b9f0 | 2002 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 2003 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 2004 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2005 | else |
e655b9f0 | 2006 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2007 | |
c1842d61 | 2008 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
2009 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
2010 | ||
5b9f8cd3 | 2011 | iwl_enable_interrupts(priv); |
a60e77e5 | 2012 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 2013 | return 0; |
b481de9c ZY |
2014 | } |
2015 | ||
3395f6e9 | 2016 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2017 | |
1053d35f | 2018 | ret = iwl_hw_nic_init(priv); |
57aab75a | 2019 | if (ret) { |
15b1687c | 2020 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 2021 | return ret; |
b481de9c ZY |
2022 | } |
2023 | ||
2024 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2025 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2026 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2027 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2028 | ||
2029 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 2030 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 2031 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2032 | |
2033 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2034 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2035 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2036 | |
2037 | /* Copy original ucode data image from disk into backup cache. | |
2038 | * This will be used to initialize the on-board processor's | |
2039 | * data SRAM for a clean start when the runtime program first loads. */ | |
2040 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2041 | priv->ucode_data.len); |
b481de9c | 2042 | |
b481de9c ZY |
2043 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2044 | ||
c587de0b | 2045 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2046 | |
2047 | /* load bootstrap state machine, | |
2048 | * load bootstrap program into processor's memory, | |
2049 | * prepare to load the "initialize" uCode */ | |
57aab75a | 2050 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 2051 | |
57aab75a | 2052 | if (ret) { |
15b1687c WT |
2053 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
2054 | ret); | |
b481de9c ZY |
2055 | continue; |
2056 | } | |
2057 | ||
2058 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 2059 | iwl_nic_start(priv); |
b481de9c | 2060 | |
e1623446 | 2061 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2062 | |
2063 | return 0; | |
2064 | } | |
2065 | ||
2066 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 2067 | __iwl_down(priv); |
64e72c3e | 2068 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2069 | |
2070 | /* tried to restart and config the device for as long as our | |
2071 | * patience could withstand */ | |
15b1687c | 2072 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2073 | return -EIO; |
2074 | } | |
2075 | ||
2076 | ||
2077 | /***************************************************************************** | |
2078 | * | |
2079 | * Workqueue callbacks | |
2080 | * | |
2081 | *****************************************************************************/ | |
2082 | ||
4a4a9e81 | 2083 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2084 | { |
c79dd5b5 TW |
2085 | struct iwl_priv *priv = |
2086 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2087 | |
2088 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2089 | return; | |
2090 | ||
2091 | mutex_lock(&priv->mutex); | |
f3ccc08c | 2092 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
2093 | mutex_unlock(&priv->mutex); |
2094 | } | |
2095 | ||
4a4a9e81 | 2096 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 2097 | { |
c79dd5b5 TW |
2098 | struct iwl_priv *priv = |
2099 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2100 | |
2101 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2102 | return; | |
2103 | ||
258c44a0 MA |
2104 | /* enable dram interrupt */ |
2105 | iwl_reset_ict(priv); | |
2106 | ||
b481de9c | 2107 | mutex_lock(&priv->mutex); |
4a4a9e81 | 2108 | iwl_alive_start(priv); |
b481de9c ZY |
2109 | mutex_unlock(&priv->mutex); |
2110 | } | |
2111 | ||
16e727e8 EG |
2112 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2113 | { | |
2114 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
2115 | run_time_calib_work); | |
2116 | ||
2117 | mutex_lock(&priv->mutex); | |
2118 | ||
2119 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
2120 | test_bit(STATUS_SCANNING, &priv->status)) { | |
2121 | mutex_unlock(&priv->mutex); | |
2122 | return; | |
2123 | } | |
2124 | ||
2125 | if (priv->start_calib) { | |
2126 | iwl_chain_noise_calibration(priv, &priv->statistics); | |
2127 | ||
2128 | iwl_sensitivity_calibration(priv, &priv->statistics); | |
2129 | } | |
2130 | ||
2131 | mutex_unlock(&priv->mutex); | |
2132 | return; | |
2133 | } | |
2134 | ||
5b9f8cd3 | 2135 | static void iwl_bg_up(struct work_struct *data) |
b481de9c | 2136 | { |
c79dd5b5 | 2137 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
2138 | |
2139 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2140 | return; | |
2141 | ||
2142 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2143 | __iwl_up(priv); |
b481de9c ZY |
2144 | mutex_unlock(&priv->mutex); |
2145 | } | |
2146 | ||
5b9f8cd3 | 2147 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2148 | { |
c79dd5b5 | 2149 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2150 | |
2151 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2152 | return; | |
2153 | ||
19cc1087 JB |
2154 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2155 | mutex_lock(&priv->mutex); | |
2156 | priv->vif = NULL; | |
2157 | priv->is_open = 0; | |
2158 | mutex_unlock(&priv->mutex); | |
2159 | iwl_down(priv); | |
2160 | ieee80211_restart_hw(priv->hw); | |
2161 | } else { | |
2162 | iwl_down(priv); | |
2163 | queue_work(priv->workqueue, &priv->up); | |
2164 | } | |
b481de9c ZY |
2165 | } |
2166 | ||
5b9f8cd3 | 2167 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2168 | { |
c79dd5b5 TW |
2169 | struct iwl_priv *priv = |
2170 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2171 | |
2172 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2173 | return; | |
2174 | ||
2175 | mutex_lock(&priv->mutex); | |
a55360e4 | 2176 | iwl_rx_replenish(priv); |
b481de9c ZY |
2177 | mutex_unlock(&priv->mutex); |
2178 | } | |
2179 | ||
7878a5a4 MA |
2180 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
2181 | ||
5bbe233b | 2182 | void iwl_post_associate(struct iwl_priv *priv) |
b481de9c | 2183 | { |
b481de9c | 2184 | struct ieee80211_conf *conf = NULL; |
857485c0 | 2185 | int ret = 0; |
1ff50bda | 2186 | unsigned long flags; |
b481de9c | 2187 | |
05c914fe | 2188 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 2189 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
2190 | return; |
2191 | } | |
2192 | ||
e1623446 | 2193 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
e174961c | 2194 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
2195 | |
2196 | ||
2197 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2198 | return; | |
2199 | ||
b481de9c | 2200 | |
508e32e1 | 2201 | if (!priv->vif || !priv->is_open) |
948c171c | 2202 | return; |
508e32e1 | 2203 | |
2a421b91 | 2204 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 2205 | |
b481de9c ZY |
2206 | conf = ieee80211_get_hw_conf(priv->hw); |
2207 | ||
2208 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2209 | iwlcore_commit_rxon(priv); |
b481de9c | 2210 | |
3195c1f3 | 2211 | iwl_setup_rxon_timing(priv); |
857485c0 | 2212 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2213 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2214 | if (ret) |
39aadf8c | 2215 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2216 | "Attempting to continue.\n"); |
2217 | ||
2218 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2219 | ||
42eb7c64 | 2220 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 2221 | |
45823531 AK |
2222 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2223 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2224 | ||
b481de9c ZY |
2225 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
2226 | ||
e1623446 | 2227 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
2228 | priv->assoc_id, priv->beacon_int); |
2229 | ||
2230 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2231 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2232 | else | |
2233 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2234 | ||
2235 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2236 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2237 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2238 | else | |
2239 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2240 | ||
05c914fe | 2241 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2242 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
2243 | ||
2244 | } | |
2245 | ||
e0158e61 | 2246 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2247 | |
2248 | switch (priv->iw_mode) { | |
05c914fe | 2249 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2250 | break; |
2251 | ||
05c914fe | 2252 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 2253 | |
c46fbefa AK |
2254 | /* assume default assoc id */ |
2255 | priv->assoc_id = 1; | |
b481de9c | 2256 | |
4f40e4d9 | 2257 | iwl_rxon_add_station(priv, priv->bssid, 0); |
5b9f8cd3 | 2258 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2259 | |
2260 | break; | |
2261 | ||
2262 | default: | |
15b1687c | 2263 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 2264 | __func__, priv->iw_mode); |
b481de9c ZY |
2265 | break; |
2266 | } | |
2267 | ||
05c914fe | 2268 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2269 | priv->assoc_station_added = 1; |
2270 | ||
1ff50bda EG |
2271 | spin_lock_irqsave(&priv->lock, flags); |
2272 | iwl_activate_qos(priv, 0); | |
2273 | spin_unlock_irqrestore(&priv->lock, flags); | |
292ae174 | 2274 | |
04816448 GE |
2275 | /* the chain noise calibration will enabled PM upon completion |
2276 | * If chain noise has already been run, then we need to enable | |
2277 | * power management here */ | |
2278 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
e312c24c | 2279 | iwl_power_update_mode(priv, false); |
c90a74ba EG |
2280 | |
2281 | /* Enable Rx differential gain and sensitivity calibrations */ | |
2282 | iwl_chain_noise_reset(priv); | |
2283 | priv->start_calib = 1; | |
2284 | ||
508e32e1 RC |
2285 | } |
2286 | ||
b481de9c ZY |
2287 | /***************************************************************************** |
2288 | * | |
2289 | * mac80211 entry point functions | |
2290 | * | |
2291 | *****************************************************************************/ | |
2292 | ||
154b25ce | 2293 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2294 | |
5b9f8cd3 | 2295 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2296 | { |
c79dd5b5 | 2297 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2298 | int ret; |
b481de9c | 2299 | |
e1623446 | 2300 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2301 | |
2302 | /* we should be verifying the device is ready to be opened */ | |
2303 | mutex_lock(&priv->mutex); | |
2304 | ||
5a66926a ZY |
2305 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
2306 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 2307 | |
5a66926a | 2308 | if (!priv->ucode_code.len) { |
5b9f8cd3 | 2309 | ret = iwl_read_ucode(priv); |
5a66926a | 2310 | if (ret) { |
15b1687c | 2311 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a | 2312 | mutex_unlock(&priv->mutex); |
6cd0b1cb | 2313 | return ret; |
5a66926a ZY |
2314 | } |
2315 | } | |
b481de9c | 2316 | |
5b9f8cd3 | 2317 | ret = __iwl_up(priv); |
5a66926a | 2318 | |
b481de9c | 2319 | mutex_unlock(&priv->mutex); |
5a66926a | 2320 | |
e655b9f0 | 2321 | if (ret) |
6cd0b1cb | 2322 | return ret; |
e655b9f0 | 2323 | |
c1842d61 TW |
2324 | if (iwl_is_rfkill(priv)) |
2325 | goto out; | |
2326 | ||
e1623446 | 2327 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2328 | |
fe9b6b72 | 2329 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2330 | * mac80211 will not be run successfully. */ |
154b25ce EG |
2331 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
2332 | test_bit(STATUS_READY, &priv->status), | |
2333 | UCODE_READY_TIMEOUT); | |
2334 | if (!ret) { | |
2335 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 2336 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 2337 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 2338 | return -ETIMEDOUT; |
5a66926a | 2339 | } |
fe9b6b72 | 2340 | } |
0a078ffa | 2341 | |
c1842d61 | 2342 | out: |
0a078ffa | 2343 | priv->is_open = 1; |
e1623446 | 2344 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2345 | return 0; |
2346 | } | |
2347 | ||
5b9f8cd3 | 2348 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2349 | { |
c79dd5b5 | 2350 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2351 | |
e1623446 | 2352 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2353 | |
19cc1087 | 2354 | if (!priv->is_open) |
e655b9f0 | 2355 | return; |
e655b9f0 | 2356 | |
b481de9c | 2357 | priv->is_open = 0; |
5a66926a | 2358 | |
5bddf549 | 2359 | if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) { |
e655b9f0 ZY |
2360 | /* stop mac, cancel any scan request and clear |
2361 | * RXON_FILTER_ASSOC_MSK BIT | |
2362 | */ | |
5a66926a | 2363 | mutex_lock(&priv->mutex); |
2a421b91 | 2364 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2365 | mutex_unlock(&priv->mutex); |
fde3571f MA |
2366 | } |
2367 | ||
5b9f8cd3 | 2368 | iwl_down(priv); |
5a66926a ZY |
2369 | |
2370 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
2371 | |
2372 | /* enable interrupts again in order to receive rfkill changes */ | |
2373 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
2374 | iwl_enable_interrupts(priv); | |
948c171c | 2375 | |
e1623446 | 2376 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2377 | } |
2378 | ||
5b9f8cd3 | 2379 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2380 | { |
c79dd5b5 | 2381 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2382 | |
e1623446 | 2383 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2384 | |
e1623446 | 2385 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2386 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2387 | |
e039fa4a | 2388 | if (iwl_tx_skb(priv, skb)) |
b481de9c ZY |
2389 | dev_kfree_skb_any(skb); |
2390 | ||
e1623446 | 2391 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 2392 | return NETDEV_TX_OK; |
b481de9c ZY |
2393 | } |
2394 | ||
60690a6a | 2395 | void iwl_config_ap(struct iwl_priv *priv) |
b481de9c | 2396 | { |
857485c0 | 2397 | int ret = 0; |
1ff50bda | 2398 | unsigned long flags; |
b481de9c | 2399 | |
d986bcd1 | 2400 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
2401 | return; |
2402 | ||
2403 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 2404 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
2405 | |
2406 | /* RXON - unassoc (to set timing command) */ | |
2407 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2408 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2409 | |
2410 | /* RXON Timing */ | |
3195c1f3 | 2411 | iwl_setup_rxon_timing(priv); |
857485c0 | 2412 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2413 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2414 | if (ret) |
39aadf8c | 2415 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2416 | "Attempting to continue.\n"); |
2417 | ||
45823531 AK |
2418 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2419 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c ZY |
2420 | |
2421 | /* FIXME: what should be the assoc_id for AP? */ | |
2422 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
2423 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2424 | priv->staging_rxon.flags |= | |
2425 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2426 | else | |
2427 | priv->staging_rxon.flags &= | |
2428 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2429 | ||
2430 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2431 | if (priv->assoc_capability & | |
2432 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2433 | priv->staging_rxon.flags |= | |
2434 | RXON_FLG_SHORT_SLOT_MSK; | |
2435 | else | |
2436 | priv->staging_rxon.flags &= | |
2437 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2438 | ||
05c914fe | 2439 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2440 | priv->staging_rxon.flags &= |
2441 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2442 | } | |
2443 | /* restore RXON assoc */ | |
2444 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2445 | iwlcore_commit_rxon(priv); |
1ff50bda EG |
2446 | spin_lock_irqsave(&priv->lock, flags); |
2447 | iwl_activate_qos(priv, 1); | |
2448 | spin_unlock_irqrestore(&priv->lock, flags); | |
4f40e4d9 | 2449 | iwl_rxon_add_station(priv, iwl_bcast_addr, 0); |
e1493deb | 2450 | } |
5b9f8cd3 | 2451 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2452 | |
2453 | /* FIXME - we need to add code here to detect a totally new | |
2454 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
2455 | * clear sta table, add BCAST sta... */ | |
2456 | } | |
2457 | ||
5b9f8cd3 | 2458 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
ab885f8c EG |
2459 | struct ieee80211_key_conf *keyconf, const u8 *addr, |
2460 | u32 iv32, u16 *phase1key) | |
2461 | { | |
ab885f8c | 2462 | |
9f58671e | 2463 | struct iwl_priv *priv = hw->priv; |
e1623446 | 2464 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2465 | |
9f58671e | 2466 | iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key); |
ab885f8c | 2467 | |
e1623446 | 2468 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2469 | } |
2470 | ||
5b9f8cd3 | 2471 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
2472 | struct ieee80211_vif *vif, |
2473 | struct ieee80211_sta *sta, | |
b481de9c ZY |
2474 | struct ieee80211_key_conf *key) |
2475 | { | |
c79dd5b5 | 2476 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
2477 | const u8 *addr; |
2478 | int ret; | |
2479 | u8 sta_id; | |
2480 | bool is_default_wep_key = false; | |
b481de9c | 2481 | |
e1623446 | 2482 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2483 | |
90e8e424 | 2484 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 2485 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2486 | return -EOPNOTSUPP; |
2487 | } | |
42986796 | 2488 | addr = sta ? sta->addr : iwl_bcast_addr; |
c587de0b | 2489 | sta_id = iwl_find_station(priv, addr); |
6974e363 | 2490 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 2491 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
e174961c | 2492 | addr); |
6974e363 | 2493 | return -EINVAL; |
b481de9c | 2494 | |
deb09c43 | 2495 | } |
b481de9c | 2496 | |
6974e363 | 2497 | mutex_lock(&priv->mutex); |
2a421b91 | 2498 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 EG |
2499 | mutex_unlock(&priv->mutex); |
2500 | ||
2501 | /* If we are getting WEP group key and we didn't receive any key mapping | |
2502 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2503 | * in 1X mode. | |
2504 | * In legacy wep mode, we use another host command to the uCode */ | |
5425e490 | 2505 | if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id && |
05c914fe | 2506 | priv->iw_mode != NL80211_IFTYPE_AP) { |
6974e363 EG |
2507 | if (cmd == SET_KEY) |
2508 | is_default_wep_key = !priv->key_mapping_key; | |
2509 | else | |
ccc038ab EG |
2510 | is_default_wep_key = |
2511 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2512 | } |
052c4b9f | 2513 | |
b481de9c | 2514 | switch (cmd) { |
deb09c43 | 2515 | case SET_KEY: |
6974e363 EG |
2516 | if (is_default_wep_key) |
2517 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 2518 | else |
7480513f | 2519 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 2520 | |
e1623446 | 2521 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2522 | break; |
2523 | case DISABLE_KEY: | |
6974e363 EG |
2524 | if (is_default_wep_key) |
2525 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 2526 | else |
3ec47732 | 2527 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 2528 | |
e1623446 | 2529 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2530 | break; |
2531 | default: | |
deb09c43 | 2532 | ret = -EINVAL; |
b481de9c ZY |
2533 | } |
2534 | ||
e1623446 | 2535 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2536 | |
deb09c43 | 2537 | return ret; |
b481de9c ZY |
2538 | } |
2539 | ||
5b9f8cd3 | 2540 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
d783b061 | 2541 | enum ieee80211_ampdu_mlme_action action, |
17741cdc | 2542 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
d783b061 TW |
2543 | { |
2544 | struct iwl_priv *priv = hw->priv; | |
5c2207c6 | 2545 | int ret; |
d783b061 | 2546 | |
e1623446 | 2547 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2548 | sta->addr, tid); |
d783b061 TW |
2549 | |
2550 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2551 | return -EACCES; | |
2552 | ||
2553 | switch (action) { | |
2554 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2555 | IWL_DEBUG_HT(priv, "start Rx\n"); |
9f58671e | 2556 | return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn); |
d783b061 | 2557 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2558 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
5c2207c6 WYG |
2559 | ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid); |
2560 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2561 | return 0; | |
2562 | else | |
2563 | return ret; | |
d783b061 | 2564 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2565 | IWL_DEBUG_HT(priv, "start Tx\n"); |
17741cdc | 2566 | return iwl_tx_agg_start(priv, sta->addr, tid, ssn); |
d783b061 | 2567 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2568 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
5c2207c6 WYG |
2569 | ret = iwl_tx_agg_stop(priv, sta->addr, tid); |
2570 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2571 | return 0; | |
2572 | else | |
2573 | return ret; | |
d783b061 | 2574 | default: |
e1623446 | 2575 | IWL_DEBUG_HT(priv, "unknown\n"); |
d783b061 TW |
2576 | return -EINVAL; |
2577 | break; | |
2578 | } | |
2579 | return 0; | |
2580 | } | |
9f58671e | 2581 | |
5b9f8cd3 | 2582 | static int iwl_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2583 | struct ieee80211_low_level_stats *stats) |
2584 | { | |
bf403db8 EK |
2585 | struct iwl_priv *priv = hw->priv; |
2586 | ||
2587 | priv = hw->priv; | |
e1623446 TW |
2588 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
2589 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
b481de9c ZY |
2590 | |
2591 | return 0; | |
2592 | } | |
2593 | ||
b481de9c ZY |
2594 | /***************************************************************************** |
2595 | * | |
2596 | * sysfs attributes | |
2597 | * | |
2598 | *****************************************************************************/ | |
2599 | ||
0a6857e7 | 2600 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2601 | |
2602 | /* | |
2603 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 2604 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
2605 | * used for controlling the debug level. |
2606 | * | |
2607 | * See the level definitions in iwl for details. | |
a562a9dd | 2608 | * |
3d816c77 RC |
2609 | * The debug_level being managed using sysfs below is a per device debug |
2610 | * level that is used instead of the global debug level if it (the per | |
2611 | * device debug level) is set. | |
b481de9c | 2612 | */ |
8cf769c6 EK |
2613 | static ssize_t show_debug_level(struct device *d, |
2614 | struct device_attribute *attr, char *buf) | |
b481de9c | 2615 | { |
3d816c77 RC |
2616 | struct iwl_priv *priv = dev_get_drvdata(d); |
2617 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 2618 | } |
8cf769c6 EK |
2619 | static ssize_t store_debug_level(struct device *d, |
2620 | struct device_attribute *attr, | |
b481de9c ZY |
2621 | const char *buf, size_t count) |
2622 | { | |
928841b1 | 2623 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2624 | unsigned long val; |
2625 | int ret; | |
b481de9c | 2626 | |
9257746f TW |
2627 | ret = strict_strtoul(buf, 0, &val); |
2628 | if (ret) | |
978785a3 | 2629 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 2630 | else { |
3d816c77 | 2631 | priv->debug_level = val; |
20594eb0 WYG |
2632 | if (iwl_alloc_traffic_mem(priv)) |
2633 | IWL_ERR(priv, | |
2634 | "Not enough memory to generate traffic log\n"); | |
2635 | } | |
b481de9c ZY |
2636 | return strnlen(buf, count); |
2637 | } | |
2638 | ||
8cf769c6 EK |
2639 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
2640 | show_debug_level, store_debug_level); | |
2641 | ||
b481de9c | 2642 | |
0a6857e7 | 2643 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 2644 | |
b481de9c ZY |
2645 | |
2646 | static ssize_t show_temperature(struct device *d, | |
2647 | struct device_attribute *attr, char *buf) | |
2648 | { | |
928841b1 | 2649 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 2650 | |
fee1247a | 2651 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2652 | return -EAGAIN; |
2653 | ||
91dbc5bd | 2654 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
2655 | } |
2656 | ||
2657 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
2658 | ||
b481de9c ZY |
2659 | static ssize_t show_tx_power(struct device *d, |
2660 | struct device_attribute *attr, char *buf) | |
2661 | { | |
928841b1 | 2662 | struct iwl_priv *priv = dev_get_drvdata(d); |
91f39e8e JS |
2663 | |
2664 | if (!iwl_is_ready_rf(priv)) | |
2665 | return sprintf(buf, "off\n"); | |
2666 | else | |
2667 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
2668 | } |
2669 | ||
2670 | static ssize_t store_tx_power(struct device *d, | |
2671 | struct device_attribute *attr, | |
2672 | const char *buf, size_t count) | |
2673 | { | |
928841b1 | 2674 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2675 | unsigned long val; |
2676 | int ret; | |
b481de9c | 2677 | |
9257746f TW |
2678 | ret = strict_strtoul(buf, 10, &val); |
2679 | if (ret) | |
978785a3 | 2680 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
5eadd94b WYG |
2681 | else { |
2682 | ret = iwl_set_tx_power(priv, val, false); | |
2683 | if (ret) | |
2684 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
2685 | ret); | |
2686 | else | |
2687 | ret = count; | |
2688 | } | |
2689 | return ret; | |
b481de9c ZY |
2690 | } |
2691 | ||
2692 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
2693 | ||
2694 | static ssize_t show_flags(struct device *d, | |
2695 | struct device_attribute *attr, char *buf) | |
2696 | { | |
928841b1 | 2697 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
2698 | |
2699 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
2700 | } | |
2701 | ||
2702 | static ssize_t store_flags(struct device *d, | |
2703 | struct device_attribute *attr, | |
2704 | const char *buf, size_t count) | |
2705 | { | |
928841b1 | 2706 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2707 | unsigned long val; |
2708 | u32 flags; | |
2709 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2710 | if (ret) |
9257746f TW |
2711 | return ret; |
2712 | flags = (u32)val; | |
b481de9c ZY |
2713 | |
2714 | mutex_lock(&priv->mutex); | |
2715 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
2716 | /* Cancel any currently running scans... */ | |
2a421b91 | 2717 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2718 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2719 | else { |
e1623446 | 2720 | IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags); |
b481de9c | 2721 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 2722 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2723 | } |
2724 | } | |
2725 | mutex_unlock(&priv->mutex); | |
2726 | ||
2727 | return count; | |
2728 | } | |
2729 | ||
2730 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
2731 | ||
2732 | static ssize_t show_filter_flags(struct device *d, | |
2733 | struct device_attribute *attr, char *buf) | |
2734 | { | |
928841b1 | 2735 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
2736 | |
2737 | return sprintf(buf, "0x%04X\n", | |
2738 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
2739 | } | |
2740 | ||
2741 | static ssize_t store_filter_flags(struct device *d, | |
2742 | struct device_attribute *attr, | |
2743 | const char *buf, size_t count) | |
2744 | { | |
928841b1 | 2745 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2746 | unsigned long val; |
2747 | u32 filter_flags; | |
2748 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2749 | if (ret) |
9257746f TW |
2750 | return ret; |
2751 | filter_flags = (u32)val; | |
b481de9c ZY |
2752 | |
2753 | mutex_lock(&priv->mutex); | |
2754 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
2755 | /* Cancel any currently running scans... */ | |
2a421b91 | 2756 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2757 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2758 | else { |
e1623446 | 2759 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c ZY |
2760 | "0x%04X\n", filter_flags); |
2761 | priv->staging_rxon.filter_flags = | |
2762 | cpu_to_le32(filter_flags); | |
e0158e61 | 2763 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2764 | } |
2765 | } | |
2766 | mutex_unlock(&priv->mutex); | |
2767 | ||
2768 | return count; | |
2769 | } | |
2770 | ||
2771 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
2772 | store_filter_flags); | |
2773 | ||
b481de9c ZY |
2774 | |
2775 | static ssize_t show_statistics(struct device *d, | |
2776 | struct device_attribute *attr, char *buf) | |
2777 | { | |
c79dd5b5 | 2778 | struct iwl_priv *priv = dev_get_drvdata(d); |
8f91aecb | 2779 | u32 size = sizeof(struct iwl_notif_statistics); |
b481de9c | 2780 | u32 len = 0, ofs = 0; |
3ac7f146 | 2781 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
2782 | int rc = 0; |
2783 | ||
fee1247a | 2784 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2785 | return -EAGAIN; |
2786 | ||
2787 | mutex_lock(&priv->mutex); | |
49ea8596 | 2788 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
2789 | mutex_unlock(&priv->mutex); |
2790 | ||
2791 | if (rc) { | |
2792 | len = sprintf(buf, | |
2793 | "Error sending statistics request: 0x%08X\n", rc); | |
2794 | return len; | |
2795 | } | |
2796 | ||
2797 | while (size && (PAGE_SIZE - len)) { | |
2798 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
2799 | PAGE_SIZE - len, 1); | |
2800 | len = strlen(buf); | |
2801 | if (PAGE_SIZE - len) | |
2802 | buf[len++] = '\n'; | |
2803 | ||
2804 | ofs += 16; | |
2805 | size -= min(size, 16U); | |
2806 | } | |
2807 | ||
2808 | return len; | |
2809 | } | |
2810 | ||
2811 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
2812 | ||
01abfbb2 WYG |
2813 | static ssize_t show_rts_ht_protection(struct device *d, |
2814 | struct device_attribute *attr, char *buf) | |
2815 | { | |
2816 | struct iwl_priv *priv = dev_get_drvdata(d); | |
2817 | ||
2818 | return sprintf(buf, "%s\n", | |
2819 | priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self"); | |
2820 | } | |
2821 | ||
2822 | static ssize_t store_rts_ht_protection(struct device *d, | |
2823 | struct device_attribute *attr, | |
2824 | const char *buf, size_t count) | |
2825 | { | |
2826 | struct iwl_priv *priv = dev_get_drvdata(d); | |
2827 | unsigned long val; | |
2828 | int ret; | |
2829 | ||
2830 | ret = strict_strtoul(buf, 10, &val); | |
2831 | if (ret) | |
2832 | IWL_INFO(priv, "Input is not in decimal form.\n"); | |
2833 | else { | |
2834 | if (!iwl_is_associated(priv)) | |
2835 | priv->cfg->use_rts_for_ht = val ? true : false; | |
2836 | else | |
2837 | IWL_ERR(priv, "Sta associated with AP - " | |
2838 | "Change protection mechanism is not allowed\n"); | |
2839 | ret = count; | |
2840 | } | |
2841 | return ret; | |
2842 | } | |
2843 | ||
2844 | static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO, | |
2845 | show_rts_ht_protection, store_rts_ht_protection); | |
2846 | ||
b481de9c | 2847 | |
b481de9c ZY |
2848 | /***************************************************************************** |
2849 | * | |
2850 | * driver setup and teardown | |
2851 | * | |
2852 | *****************************************************************************/ | |
2853 | ||
4e39317d | 2854 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 2855 | { |
d21050c7 | 2856 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
2857 | |
2858 | init_waitqueue_head(&priv->wait_command_queue); | |
2859 | ||
5b9f8cd3 EG |
2860 | INIT_WORK(&priv->up, iwl_bg_up); |
2861 | INIT_WORK(&priv->restart, iwl_bg_restart); | |
2862 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 2863 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 2864 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
2865 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
2866 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 2867 | |
2a421b91 | 2868 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 2869 | |
4e39317d EG |
2870 | if (priv->cfg->ops->lib->setup_deferred_work) |
2871 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
2872 | ||
2873 | init_timer(&priv->statistics_periodic); | |
2874 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 2875 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 2876 | |
ef850d7c MA |
2877 | if (!priv->cfg->use_isr_legacy) |
2878 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
2879 | iwl_irq_tasklet, (unsigned long)priv); | |
2880 | else | |
2881 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
2882 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
2883 | } |
2884 | ||
4e39317d | 2885 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 2886 | { |
4e39317d EG |
2887 | if (priv->cfg->ops->lib->cancel_deferred_work) |
2888 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 2889 | |
3ae6a054 | 2890 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
2891 | cancel_delayed_work(&priv->scan_check); |
2892 | cancel_delayed_work(&priv->alive_start); | |
b481de9c | 2893 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 2894 | del_timer_sync(&priv->statistics_periodic); |
b481de9c ZY |
2895 | } |
2896 | ||
5b9f8cd3 | 2897 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c ZY |
2898 | &dev_attr_flags.attr, |
2899 | &dev_attr_filter_flags.attr, | |
b481de9c | 2900 | &dev_attr_statistics.attr, |
b481de9c | 2901 | &dev_attr_temperature.attr, |
b481de9c | 2902 | &dev_attr_tx_power.attr, |
01abfbb2 | 2903 | &dev_attr_rts_ht_protection.attr, |
8cf769c6 EK |
2904 | #ifdef CONFIG_IWLWIFI_DEBUG |
2905 | &dev_attr_debug_level.attr, | |
2906 | #endif | |
b481de9c ZY |
2907 | NULL |
2908 | }; | |
2909 | ||
5b9f8cd3 | 2910 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 2911 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 2912 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
2913 | }; |
2914 | ||
5b9f8cd3 EG |
2915 | static struct ieee80211_ops iwl_hw_ops = { |
2916 | .tx = iwl_mac_tx, | |
2917 | .start = iwl_mac_start, | |
2918 | .stop = iwl_mac_stop, | |
2919 | .add_interface = iwl_mac_add_interface, | |
2920 | .remove_interface = iwl_mac_remove_interface, | |
2921 | .config = iwl_mac_config, | |
5b9f8cd3 EG |
2922 | .configure_filter = iwl_configure_filter, |
2923 | .set_key = iwl_mac_set_key, | |
2924 | .update_tkip_key = iwl_mac_update_tkip_key, | |
2925 | .get_stats = iwl_mac_get_stats, | |
2926 | .get_tx_stats = iwl_mac_get_tx_stats, | |
2927 | .conf_tx = iwl_mac_conf_tx, | |
2928 | .reset_tsf = iwl_mac_reset_tsf, | |
2929 | .bss_info_changed = iwl_bss_info_changed, | |
2930 | .ampdu_action = iwl_mac_ampdu_action, | |
cb43dc25 | 2931 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
2932 | }; |
2933 | ||
5b9f8cd3 | 2934 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
2935 | { |
2936 | int err = 0; | |
c79dd5b5 | 2937 | struct iwl_priv *priv; |
b481de9c | 2938 | struct ieee80211_hw *hw; |
82b9a121 | 2939 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 2940 | unsigned long flags; |
6cd0b1cb | 2941 | u16 pci_cmd; |
b481de9c | 2942 | |
316c30d9 AK |
2943 | /************************ |
2944 | * 1. Allocating HW data | |
2945 | ************************/ | |
2946 | ||
6440adb5 BC |
2947 | /* Disabling hardware scan means that mac80211 will perform scans |
2948 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 2949 | if (cfg->mod_params->disable_hw_scan) { |
a562a9dd | 2950 | if (iwl_debug_level & IWL_DL_INFO) |
bf403db8 EK |
2951 | dev_printk(KERN_DEBUG, &(pdev->dev), |
2952 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 2953 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
2954 | } |
2955 | ||
5b9f8cd3 | 2956 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 2957 | if (!hw) { |
b481de9c ZY |
2958 | err = -ENOMEM; |
2959 | goto out; | |
2960 | } | |
1d0a082d AK |
2961 | priv = hw->priv; |
2962 | /* At this point both hw and priv are allocated. */ | |
2963 | ||
b481de9c ZY |
2964 | SET_IEEE80211_DEV(hw, &pdev->dev); |
2965 | ||
e1623446 | 2966 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 2967 | priv->cfg = cfg; |
b481de9c | 2968 | priv->pci_dev = pdev; |
40cefda9 | 2969 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 2970 | |
0a6857e7 | 2971 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2972 | atomic_set(&priv->restrict_refcnt, 0); |
2973 | #endif | |
20594eb0 WYG |
2974 | if (iwl_alloc_traffic_mem(priv)) |
2975 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 2976 | |
316c30d9 AK |
2977 | /************************** |
2978 | * 2. Initializing PCI bus | |
2979 | **************************/ | |
2980 | if (pci_enable_device(pdev)) { | |
2981 | err = -ENODEV; | |
2982 | goto out_ieee80211_free_hw; | |
2983 | } | |
2984 | ||
2985 | pci_set_master(pdev); | |
2986 | ||
093d874c | 2987 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 2988 | if (!err) |
093d874c | 2989 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 2990 | if (err) { |
093d874c | 2991 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2992 | if (!err) |
093d874c | 2993 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2994 | /* both attempts failed: */ |
316c30d9 | 2995 | if (err) { |
978785a3 | 2996 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 2997 | goto out_pci_disable_device; |
cc2a8ea8 | 2998 | } |
316c30d9 AK |
2999 | } |
3000 | ||
3001 | err = pci_request_regions(pdev, DRV_NAME); | |
3002 | if (err) | |
3003 | goto out_pci_disable_device; | |
3004 | ||
3005 | pci_set_drvdata(pdev, priv); | |
3006 | ||
316c30d9 AK |
3007 | |
3008 | /*********************** | |
3009 | * 3. Read REV register | |
3010 | ***********************/ | |
3011 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3012 | if (!priv->hw_base) { | |
3013 | err = -ENODEV; | |
3014 | goto out_pci_release_regions; | |
3015 | } | |
3016 | ||
e1623446 | 3017 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 3018 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3019 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 3020 | |
a8b50a0a MA |
3021 | /* this spin lock will be used in apm_ops.init and EEPROM access |
3022 | * we should init now | |
3023 | */ | |
3024 | spin_lock_init(&priv->reg_lock); | |
b661c819 | 3025 | iwl_hw_detect(priv); |
978785a3 | 3026 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", |
b661c819 | 3027 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 3028 | |
e7b63581 TW |
3029 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3030 | * PCI Tx retries from interfering with C3 CPU state */ | |
3031 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3032 | ||
086ed117 MA |
3033 | iwl_prepare_card_hw(priv); |
3034 | if (!priv->hw_ready) { | |
3035 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
3036 | goto out_iounmap; | |
3037 | } | |
3038 | ||
91238714 TW |
3039 | /* amp init */ |
3040 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
316c30d9 | 3041 | if (err < 0) { |
808ff697 | 3042 | IWL_ERR(priv, "Failed to init APMG\n"); |
316c30d9 AK |
3043 | goto out_iounmap; |
3044 | } | |
91238714 TW |
3045 | /***************** |
3046 | * 4. Read EEPROM | |
3047 | *****************/ | |
316c30d9 AK |
3048 | /* Read the EEPROM */ |
3049 | err = iwl_eeprom_init(priv); | |
3050 | if (err) { | |
15b1687c | 3051 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
3052 | goto out_iounmap; |
3053 | } | |
8614f360 TW |
3054 | err = iwl_eeprom_check_version(priv); |
3055 | if (err) | |
c8f16138 | 3056 | goto out_free_eeprom; |
8614f360 | 3057 | |
02883017 | 3058 | /* extract MAC Address */ |
316c30d9 | 3059 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e1623446 | 3060 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
3061 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
3062 | ||
3063 | /************************ | |
3064 | * 5. Setup HW constants | |
3065 | ************************/ | |
da154e30 | 3066 | if (iwl_set_hw_params(priv)) { |
15b1687c | 3067 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3068 | goto out_free_eeprom; |
316c30d9 AK |
3069 | } |
3070 | ||
3071 | /******************* | |
6ba87956 | 3072 | * 6. Setup priv |
316c30d9 | 3073 | *******************/ |
b481de9c | 3074 | |
6ba87956 | 3075 | err = iwl_init_drv(priv); |
bf85ea4f | 3076 | if (err) |
399f4900 | 3077 | goto out_free_eeprom; |
bf85ea4f | 3078 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 3079 | |
316c30d9 | 3080 | /******************** |
09f9bf79 | 3081 | * 7. Setup services |
316c30d9 | 3082 | ********************/ |
0359facc | 3083 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 3084 | iwl_disable_interrupts(priv); |
0359facc | 3085 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 3086 | |
6cd0b1cb HS |
3087 | pci_enable_msi(priv->pci_dev); |
3088 | ||
ef850d7c MA |
3089 | iwl_alloc_isr_ict(priv); |
3090 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
3091 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
3092 | if (err) { |
3093 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3094 | goto out_disable_msi; | |
3095 | } | |
5b9f8cd3 | 3096 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 3097 | if (err) { |
15b1687c | 3098 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
795cc0ad | 3099 | goto out_free_irq; |
316c30d9 AK |
3100 | } |
3101 | ||
4e39317d | 3102 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3103 | iwl_setup_rx_handlers(priv); |
316c30d9 | 3104 | |
6ba87956 | 3105 | /********************************** |
09f9bf79 | 3106 | * 8. Setup and register mac80211 |
6ba87956 TW |
3107 | **********************************/ |
3108 | ||
6cd0b1cb HS |
3109 | /* enable interrupts if needed: hw bug w/a */ |
3110 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
3111 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3112 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3113 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3114 | } | |
3115 | ||
3116 | iwl_enable_interrupts(priv); | |
3117 | ||
6ba87956 TW |
3118 | err = iwl_setup_mac(priv); |
3119 | if (err) | |
3120 | goto out_remove_sysfs; | |
3121 | ||
3122 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
3123 | if (err) | |
a75fbe8d | 3124 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); |
6ba87956 | 3125 | |
6cd0b1cb HS |
3126 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3127 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3128 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3129 | else | |
3130 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3131 | |
a60e77e5 JB |
3132 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3133 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3134 | |
58d0f361 | 3135 | iwl_power_initialize(priv); |
39b73fb1 | 3136 | iwl_tt_initialize(priv); |
b481de9c ZY |
3137 | return 0; |
3138 | ||
316c30d9 | 3139 | out_remove_sysfs: |
c8f16138 RC |
3140 | destroy_workqueue(priv->workqueue); |
3141 | priv->workqueue = NULL; | |
5b9f8cd3 | 3142 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
795cc0ad HS |
3143 | out_free_irq: |
3144 | free_irq(priv->pci_dev->irq, priv); | |
ef850d7c | 3145 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
3146 | out_disable_msi: |
3147 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 3148 | iwl_uninit_drv(priv); |
073d3f5f TW |
3149 | out_free_eeprom: |
3150 | iwl_eeprom_free(priv); | |
b481de9c ZY |
3151 | out_iounmap: |
3152 | pci_iounmap(pdev, priv->hw_base); | |
3153 | out_pci_release_regions: | |
316c30d9 | 3154 | pci_set_drvdata(pdev, NULL); |
623d563e | 3155 | pci_release_regions(pdev); |
b481de9c ZY |
3156 | out_pci_disable_device: |
3157 | pci_disable_device(pdev); | |
b481de9c ZY |
3158 | out_ieee80211_free_hw: |
3159 | ieee80211_free_hw(priv->hw); | |
20594eb0 | 3160 | iwl_free_traffic_mem(priv); |
b481de9c ZY |
3161 | out: |
3162 | return err; | |
3163 | } | |
3164 | ||
5b9f8cd3 | 3165 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 3166 | { |
c79dd5b5 | 3167 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 3168 | unsigned long flags; |
b481de9c ZY |
3169 | |
3170 | if (!priv) | |
3171 | return; | |
3172 | ||
e1623446 | 3173 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 3174 | |
67249625 | 3175 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 3176 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 3177 | |
5b9f8cd3 EG |
3178 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3179 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3180 | * we need to set STATUS_EXIT_PENDING bit. |
3181 | */ | |
3182 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
3183 | if (priv->mac80211_registered) { |
3184 | ieee80211_unregister_hw(priv->hw); | |
3185 | priv->mac80211_registered = 0; | |
0b124c31 | 3186 | } else { |
5b9f8cd3 | 3187 | iwl_down(priv); |
c4f55232 RR |
3188 | } |
3189 | ||
39b73fb1 WYG |
3190 | iwl_tt_exit(priv); |
3191 | ||
0359facc MA |
3192 | /* make sure we flush any pending irq or |
3193 | * tasklet for the driver | |
3194 | */ | |
3195 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3196 | iwl_disable_interrupts(priv); |
0359facc MA |
3197 | spin_unlock_irqrestore(&priv->lock, flags); |
3198 | ||
3199 | iwl_synchronize_irq(priv); | |
3200 | ||
5b9f8cd3 | 3201 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3202 | |
3203 | if (priv->rxq.bd) | |
a55360e4 | 3204 | iwl_rx_queue_free(priv, &priv->rxq); |
1053d35f | 3205 | iwl_hw_txq_ctx_free(priv); |
b481de9c | 3206 | |
c587de0b | 3207 | iwl_clear_stations_table(priv); |
073d3f5f | 3208 | iwl_eeprom_free(priv); |
b481de9c | 3209 | |
b481de9c | 3210 | |
948c171c MA |
3211 | /*netif_stop_queue(dev); */ |
3212 | flush_workqueue(priv->workqueue); | |
3213 | ||
5b9f8cd3 | 3214 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3215 | * priv->workqueue... so we can't take down the workqueue |
3216 | * until now... */ | |
3217 | destroy_workqueue(priv->workqueue); | |
3218 | priv->workqueue = NULL; | |
20594eb0 | 3219 | iwl_free_traffic_mem(priv); |
b481de9c | 3220 | |
6cd0b1cb HS |
3221 | free_irq(priv->pci_dev->irq, priv); |
3222 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3223 | pci_iounmap(pdev, priv->hw_base); |
3224 | pci_release_regions(pdev); | |
3225 | pci_disable_device(pdev); | |
3226 | pci_set_drvdata(pdev, NULL); | |
3227 | ||
6ba87956 | 3228 | iwl_uninit_drv(priv); |
b481de9c | 3229 | |
ef850d7c MA |
3230 | iwl_free_isr_ict(priv); |
3231 | ||
b481de9c ZY |
3232 | if (priv->ibss_beacon) |
3233 | dev_kfree_skb(priv->ibss_beacon); | |
3234 | ||
3235 | ieee80211_free_hw(priv->hw); | |
3236 | } | |
3237 | ||
b481de9c ZY |
3238 | |
3239 | /***************************************************************************** | |
3240 | * | |
3241 | * driver and module entry point | |
3242 | * | |
3243 | *****************************************************************************/ | |
3244 | ||
fed9017e RR |
3245 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
3246 | static struct pci_device_id iwl_hw_card_ids[] = { | |
4fc22b21 | 3247 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
3248 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
3249 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 3250 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 3251 | #ifdef CONFIG_IWL5000 |
47408639 EK |
3252 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)}, |
3253 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)}, | |
3254 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, | |
3255 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, | |
3256 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, | |
3257 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, | |
5a6a256e | 3258 | {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)}, |
47408639 EK |
3259 | {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)}, |
3260 | {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)}, | |
3261 | {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)}, | |
e96a8495 TW |
3262 | /* 5350 WiFi/WiMax */ |
3263 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, | |
3264 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, | |
3265 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, | |
7100e924 TW |
3266 | /* 5150 Wifi/WiMax */ |
3267 | {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
3268 | {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
5953a62e WYG |
3269 | |
3270 | /* 6x00 Series */ | |
3271 | {IWL_PCI_DEVICE(0x008D, 0x1301, iwl6000h_2agn_cfg)}, | |
3272 | {IWL_PCI_DEVICE(0x008D, 0x1321, iwl6000h_2agn_cfg)}, | |
3273 | {IWL_PCI_DEVICE(0x008D, 0x1326, iwl6000h_2abg_cfg)}, | |
3274 | {IWL_PCI_DEVICE(0x008D, 0x1306, iwl6000h_2abg_cfg)}, | |
3275 | {IWL_PCI_DEVICE(0x008D, 0x1307, iwl6000h_2bg_cfg)}, | |
3276 | {IWL_PCI_DEVICE(0x008E, 0x1311, iwl6000h_2agn_cfg)}, | |
3277 | {IWL_PCI_DEVICE(0x008E, 0x1316, iwl6000h_2abg_cfg)}, | |
3278 | ||
3279 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, | |
3280 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
3281 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
3282 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
3283 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
3284 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
3285 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
3286 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
3287 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
3288 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
3289 | ||
3290 | /* 6x50 WiFi/WiMax Series */ | |
3291 | {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)}, | |
3292 | {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)}, | |
3293 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, | |
3294 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
3295 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
3296 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
3297 | {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)}, | |
3298 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, | |
3299 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
3300 | ||
77dcb6a9 | 3301 | /* 1000 Series WiFi */ |
4bd0914f WYG |
3302 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
3303 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
3304 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
3305 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
3306 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
3307 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
3308 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
3309 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
3310 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
3311 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
3312 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
3313 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
5a6a256e | 3314 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 3315 | |
fed9017e RR |
3316 | {0} |
3317 | }; | |
3318 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
3319 | ||
3320 | static struct pci_driver iwl_driver = { | |
b481de9c | 3321 | .name = DRV_NAME, |
fed9017e | 3322 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
3323 | .probe = iwl_pci_probe, |
3324 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 3325 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
3326 | .suspend = iwl_pci_suspend, |
3327 | .resume = iwl_pci_resume, | |
b481de9c ZY |
3328 | #endif |
3329 | }; | |
3330 | ||
5b9f8cd3 | 3331 | static int __init iwl_init(void) |
b481de9c ZY |
3332 | { |
3333 | ||
3334 | int ret; | |
3335 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3336 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3337 | |
e227ceac | 3338 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3339 | if (ret) { |
a3139c59 SO |
3340 | printk(KERN_ERR DRV_NAME |
3341 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
3342 | return ret; |
3343 | } | |
3344 | ||
fed9017e | 3345 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 3346 | if (ret) { |
a3139c59 | 3347 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 3348 | goto error_register; |
b481de9c | 3349 | } |
b481de9c ZY |
3350 | |
3351 | return ret; | |
897e1cf2 | 3352 | |
897e1cf2 | 3353 | error_register: |
e227ceac | 3354 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3355 | return ret; |
b481de9c ZY |
3356 | } |
3357 | ||
5b9f8cd3 | 3358 | static void __exit iwl_exit(void) |
b481de9c | 3359 | { |
fed9017e | 3360 | pci_unregister_driver(&iwl_driver); |
e227ceac | 3361 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3362 | } |
3363 | ||
5b9f8cd3 EG |
3364 | module_exit(iwl_exit); |
3365 | module_init(iwl_init); | |
a562a9dd RC |
3366 | |
3367 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 3368 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); |
a562a9dd | 3369 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); |
4e30cb69 | 3370 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
3371 | MODULE_PARM_DESC(debug, "debug output mask"); |
3372 | #endif | |
3373 |