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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
c96c31e4 JP |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
b481de9c ZY |
32 | #include <linux/kernel.h> |
33 | #include <linux/module.h> | |
b481de9c ZY |
34 | #include <linux/init.h> |
35 | #include <linux/pci.h> | |
1a7123cd | 36 | #include <linux/pci-aspm.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
b481de9c ZY |
38 | #include <linux/dma-mapping.h> |
39 | #include <linux/delay.h> | |
d43c36dc | 40 | #include <linux/sched.h> |
b481de9c ZY |
41 | #include <linux/skbuff.h> |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/wireless.h> | |
44 | #include <linux/firmware.h> | |
b481de9c ZY |
45 | #include <linux/etherdevice.h> |
46 | #include <linux/if_arp.h> | |
47 | ||
b481de9c ZY |
48 | #include <net/mac80211.h> |
49 | ||
50 | #include <asm/div64.h> | |
51 | ||
a3139c59 SO |
52 | #define DRV_NAME "iwlagn" |
53 | ||
6bc913bd | 54 | #include "iwl-eeprom.h" |
3e0d4cb1 | 55 | #include "iwl-dev.h" |
fee1247a | 56 | #include "iwl-core.h" |
3395f6e9 | 57 | #include "iwl-io.h" |
b481de9c | 58 | #include "iwl-helpers.h" |
6974e363 | 59 | #include "iwl-sta.h" |
f0832f13 | 60 | #include "iwl-calib.h" |
a1175124 | 61 | #include "iwl-agn.h" |
b481de9c | 62 | |
416e1438 | 63 | |
b481de9c ZY |
64 | /****************************************************************************** |
65 | * | |
66 | * module boiler plate | |
67 | * | |
68 | ******************************************************************************/ | |
69 | ||
b481de9c ZY |
70 | /* |
71 | * module name, copyright, version, etc. | |
b481de9c | 72 | */ |
d783b061 | 73 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 74 | |
0a6857e7 | 75 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
76 | #define VD "d" |
77 | #else | |
78 | #define VD | |
79 | #endif | |
80 | ||
81963d68 | 81 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 87 | MODULE_LICENSE("GPL"); |
4fc22b21 | 88 | MODULE_ALIAS("iwl4965"); |
b481de9c | 89 | |
bee008b7 | 90 | static int iwlagn_ant_coupling; |
f37837c9 | 91 | static bool iwlagn_bt_ch_announce = 1; |
bee008b7 | 92 | |
b481de9c | 93 | /** |
5b9f8cd3 | 94 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 95 | * |
01ebd063 | 96 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
97 | * the active_rxon structure is updated with the new data. This |
98 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
99 | * a HW tune is required based on the RXON structure changes. | |
100 | */ | |
246ed355 | 101 | int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
b481de9c ZY |
102 | { |
103 | /* cast away the const for active_rxon in this function */ | |
246ed355 | 104 | struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active; |
43d59b32 EG |
105 | int ret; |
106 | bool new_assoc = | |
246ed355 | 107 | !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK); |
b481de9c | 108 | |
fee1247a | 109 | if (!iwl_is_alive(priv)) |
43d59b32 | 110 | return -EBUSY; |
b481de9c ZY |
111 | |
112 | /* always get timestamp with Rx frame */ | |
246ed355 | 113 | ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK; |
b481de9c | 114 | |
246ed355 | 115 | ret = iwl_check_rxon_cmd(priv, ctx); |
43d59b32 | 116 | if (ret) { |
15b1687c | 117 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
118 | return -EINVAL; |
119 | } | |
120 | ||
0924e519 WYG |
121 | /* |
122 | * receive commit_rxon request | |
123 | * abort any previous channel switch if still in process | |
124 | */ | |
125 | if (priv->switch_rxon.switch_in_progress && | |
246ed355 | 126 | (priv->switch_rxon.channel != ctx->staging.channel)) { |
0924e519 WYG |
127 | IWL_DEBUG_11H(priv, "abort channel switch on %d\n", |
128 | le16_to_cpu(priv->switch_rxon.channel)); | |
79d07325 | 129 | iwl_chswitch_done(priv, false); |
0924e519 WYG |
130 | } |
131 | ||
b481de9c | 132 | /* If we don't need to send a full RXON, we can use |
5b9f8cd3 | 133 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 134 | * and other flags for the current radio configuration. */ |
246ed355 JB |
135 | if (!iwl_full_rxon_required(priv, ctx)) { |
136 | ret = iwl_send_rxon_assoc(priv, ctx); | |
43d59b32 | 137 | if (ret) { |
15b1687c | 138 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 139 | return ret; |
b481de9c ZY |
140 | } |
141 | ||
246ed355 JB |
142 | memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon)); |
143 | iwl_print_rx_config_cmd(priv, ctx); | |
b481de9c ZY |
144 | return 0; |
145 | } | |
146 | ||
b481de9c ZY |
147 | /* If we are currently associated and the new config requires |
148 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
149 | * we must clear the associated from the active configuration | |
150 | * before we apply the new config */ | |
246ed355 | 151 | if (iwl_is_associated_ctx(ctx) && new_assoc) { |
e1623446 | 152 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
153 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
154 | ||
8f2d3d2a | 155 | ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd, |
246ed355 JB |
156 | sizeof(struct iwl_rxon_cmd), |
157 | active_rxon); | |
b481de9c ZY |
158 | |
159 | /* If the mask clearing failed then we set | |
160 | * active_rxon back to what it was previously */ | |
43d59b32 | 161 | if (ret) { |
b481de9c | 162 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 163 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 164 | return ret; |
b481de9c | 165 | } |
dcef732c JB |
166 | iwl_clear_ucode_stations(priv, ctx); |
167 | iwl_restore_stations(priv, ctx); | |
335348b1 JB |
168 | ret = iwl_restore_default_wep_keys(priv); |
169 | if (ret) { | |
170 | IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret); | |
171 | return ret; | |
172 | } | |
b481de9c ZY |
173 | } |
174 | ||
e1623446 | 175 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
176 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
177 | "* channel = %d\n" | |
e174961c | 178 | "* bssid = %pM\n", |
43d59b32 | 179 | (new_assoc ? "" : "out"), |
246ed355 JB |
180 | le16_to_cpu(ctx->staging.channel), |
181 | ctx->staging.bssid_addr); | |
b481de9c | 182 | |
246ed355 | 183 | iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto); |
43d59b32 EG |
184 | |
185 | /* Apply the new configuration | |
7e246191 RC |
186 | * RXON unassoc clears the station table in uCode so restoration of |
187 | * stations is needed after it (the RXON command) completes | |
43d59b32 EG |
188 | */ |
189 | if (!new_assoc) { | |
8f2d3d2a | 190 | ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd, |
246ed355 | 191 | sizeof(struct iwl_rxon_cmd), &ctx->staging); |
43d59b32 | 192 | if (ret) { |
15b1687c | 193 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
194 | return ret; |
195 | } | |
91dd6c27 | 196 | IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n"); |
246ed355 | 197 | memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon)); |
dcef732c JB |
198 | iwl_clear_ucode_stations(priv, ctx); |
199 | iwl_restore_stations(priv, ctx); | |
335348b1 JB |
200 | ret = iwl_restore_default_wep_keys(priv); |
201 | if (ret) { | |
202 | IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret); | |
203 | return ret; | |
204 | } | |
b481de9c ZY |
205 | } |
206 | ||
19cc1087 | 207 | priv->start_calib = 0; |
9185159d | 208 | if (new_assoc) { |
43d59b32 EG |
209 | /* Apply the new configuration |
210 | * RXON assoc doesn't clear the station table in uCode, | |
211 | */ | |
8f2d3d2a | 212 | ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd, |
246ed355 | 213 | sizeof(struct iwl_rxon_cmd), &ctx->staging); |
43d59b32 | 214 | if (ret) { |
15b1687c | 215 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
216 | return ret; |
217 | } | |
246ed355 | 218 | memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon)); |
b481de9c | 219 | } |
246ed355 | 220 | iwl_print_rx_config_cmd(priv, ctx); |
b481de9c | 221 | |
36da7d70 ZY |
222 | iwl_init_sensitivity(priv); |
223 | ||
224 | /* If we issue a new RXON command which required a tune then we must | |
225 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
226 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
227 | if (ret) { | |
15b1687c | 228 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
229 | return ret; |
230 | } | |
231 | ||
b481de9c ZY |
232 | return 0; |
233 | } | |
234 | ||
5b9f8cd3 | 235 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f | 236 | { |
246ed355 | 237 | struct iwl_rxon_context *ctx; |
5da4b55f | 238 | |
246ed355 JB |
239 | if (priv->cfg->ops->hcmd->set_rxon_chain) { |
240 | for_each_context(priv, ctx) { | |
241 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
242 | iwlcore_commit_rxon(priv, ctx); | |
243 | } | |
244 | } | |
5da4b55f MA |
245 | } |
246 | ||
fcab423d | 247 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
248 | { |
249 | struct list_head *element; | |
250 | ||
e1623446 | 251 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
252 | priv->frames_count); |
253 | ||
254 | while (!list_empty(&priv->free_frames)) { | |
255 | element = priv->free_frames.next; | |
256 | list_del(element); | |
fcab423d | 257 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
258 | priv->frames_count--; |
259 | } | |
260 | ||
261 | if (priv->frames_count) { | |
39aadf8c | 262 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
263 | priv->frames_count); |
264 | priv->frames_count = 0; | |
265 | } | |
266 | } | |
267 | ||
fcab423d | 268 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 269 | { |
fcab423d | 270 | struct iwl_frame *frame; |
b481de9c ZY |
271 | struct list_head *element; |
272 | if (list_empty(&priv->free_frames)) { | |
273 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
274 | if (!frame) { | |
15b1687c | 275 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
276 | return NULL; |
277 | } | |
278 | ||
279 | priv->frames_count++; | |
280 | return frame; | |
281 | } | |
282 | ||
283 | element = priv->free_frames.next; | |
284 | list_del(element); | |
fcab423d | 285 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
286 | } |
287 | ||
fcab423d | 288 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
289 | { |
290 | memset(frame, 0, sizeof(*frame)); | |
291 | list_add(&frame->list, &priv->free_frames); | |
292 | } | |
293 | ||
47ff65c4 | 294 | static u32 iwl_fill_beacon_frame(struct iwl_priv *priv, |
4bf64efd | 295 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 296 | int left) |
b481de9c | 297 | { |
6abbe554 | 298 | if (!priv->ibss_beacon) |
b481de9c ZY |
299 | return 0; |
300 | ||
301 | if (priv->ibss_beacon->len > left) | |
302 | return 0; | |
303 | ||
304 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
305 | ||
306 | return priv->ibss_beacon->len; | |
307 | } | |
308 | ||
47ff65c4 DH |
309 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
310 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
311 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, | |
312 | u8 *beacon, u32 frame_size) | |
313 | { | |
314 | u16 tim_idx; | |
315 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
316 | ||
317 | /* | |
318 | * The index is relative to frame start but we start looking at the | |
319 | * variable-length part of the beacon. | |
320 | */ | |
321 | tim_idx = mgmt->u.beacon.variable - beacon; | |
322 | ||
323 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
324 | while ((tim_idx < (frame_size - 2)) && | |
325 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
326 | tim_idx += beacon[tim_idx+1] + 2; | |
327 | ||
328 | /* If TIM field was found, set variables */ | |
329 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
330 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
331 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
332 | } else | |
333 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
334 | } | |
335 | ||
5b9f8cd3 | 336 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
47ff65c4 | 337 | struct iwl_frame *frame) |
4bf64efd TW |
338 | { |
339 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
47ff65c4 DH |
340 | u32 frame_size; |
341 | u32 rate_flags; | |
342 | u32 rate; | |
343 | /* | |
344 | * We have to set up the TX command, the TX Beacon command, and the | |
345 | * beacon contents. | |
346 | */ | |
4bf64efd | 347 | |
47ff65c4 | 348 | /* Initialize memory */ |
4bf64efd TW |
349 | tx_beacon_cmd = &frame->u.beacon; |
350 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
351 | ||
47ff65c4 | 352 | /* Set up TX beacon contents */ |
4bf64efd | 353 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, |
4bf64efd | 354 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
47ff65c4 DH |
355 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
356 | return 0; | |
4bf64efd | 357 | |
47ff65c4 | 358 | /* Set up TX command fields */ |
4bf64efd | 359 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
a194e324 JB |
360 | #warning "Use proper STA ID" |
361 | tx_beacon_cmd->tx.sta_id = | |
362 | priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id; | |
47ff65c4 DH |
363 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
364 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
365 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 366 | |
47ff65c4 DH |
367 | /* Set up TX beacon command fields */ |
368 | iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, | |
369 | frame_size); | |
4bf64efd | 370 | |
47ff65c4 DH |
371 | /* Set up packet rate and flags */ |
372 | rate = iwl_rate_get_lowest_plcp(priv); | |
0e1654fa JB |
373 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, |
374 | priv->hw_params.valid_tx_ant); | |
47ff65c4 DH |
375 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); |
376 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
377 | rate_flags |= RATE_MCS_CCK_MSK; | |
378 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
379 | rate_flags); | |
4bf64efd TW |
380 | |
381 | return sizeof(*tx_beacon_cmd) + frame_size; | |
382 | } | |
5b9f8cd3 | 383 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 384 | { |
fcab423d | 385 | struct iwl_frame *frame; |
b481de9c ZY |
386 | unsigned int frame_size; |
387 | int rc; | |
b481de9c | 388 | |
fcab423d | 389 | frame = iwl_get_free_frame(priv); |
b481de9c | 390 | if (!frame) { |
15b1687c | 391 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
392 | "command.\n"); |
393 | return -ENOMEM; | |
394 | } | |
395 | ||
47ff65c4 DH |
396 | frame_size = iwl_hw_get_beacon_cmd(priv, frame); |
397 | if (!frame_size) { | |
398 | IWL_ERR(priv, "Error configuring the beacon command\n"); | |
399 | iwl_free_frame(priv, frame); | |
400 | return -EINVAL; | |
401 | } | |
b481de9c | 402 | |
857485c0 | 403 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
404 | &frame->u.cmd[0]); |
405 | ||
fcab423d | 406 | iwl_free_frame(priv, frame); |
b481de9c ZY |
407 | |
408 | return rc; | |
409 | } | |
410 | ||
7aaa1d79 SO |
411 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
412 | { | |
413 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
414 | ||
415 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
416 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
417 | addr |= | |
418 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
419 | ||
420 | return addr; | |
421 | } | |
422 | ||
423 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
424 | { | |
425 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
426 | ||
427 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
428 | } | |
429 | ||
430 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
431 | dma_addr_t addr, u16 len) | |
432 | { | |
433 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
434 | u16 hi_n_len = len << 4; | |
435 | ||
436 | put_unaligned_le32(addr, &tb->lo); | |
437 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
438 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
439 | ||
440 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
441 | ||
442 | tfd->num_tbs = idx + 1; | |
443 | } | |
444 | ||
445 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
446 | { | |
447 | return tfd->num_tbs & 0x1f; | |
448 | } | |
449 | ||
450 | /** | |
451 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
452 | * @priv - driver private data | |
453 | * @txq - tx queue | |
454 | * | |
455 | * Does NOT advance any TFD circular buffer read/write indexes | |
456 | * Does NOT free the TFD itself (which is within circular buffer) | |
457 | */ | |
458 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
459 | { | |
59606ffa | 460 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
461 | struct iwl_tfd *tfd; |
462 | struct pci_dev *dev = priv->pci_dev; | |
463 | int index = txq->q.read_ptr; | |
464 | int i; | |
465 | int num_tbs; | |
466 | ||
467 | tfd = &tfd_tmp[index]; | |
468 | ||
469 | /* Sanity check on number of chunks */ | |
470 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
471 | ||
472 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
473 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
474 | /* @todo issue fatal error, it is quite serious situation */ | |
475 | return; | |
476 | } | |
477 | ||
478 | /* Unmap tx_cmd */ | |
479 | if (num_tbs) | |
480 | pci_unmap_single(dev, | |
2e724443 FT |
481 | dma_unmap_addr(&txq->meta[index], mapping), |
482 | dma_unmap_len(&txq->meta[index], len), | |
96891cee | 483 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
484 | |
485 | /* Unmap chunks, if any. */ | |
ff0d91c3 | 486 | for (i = 1; i < num_tbs; i++) |
7aaa1d79 SO |
487 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), |
488 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
489 | ||
ff0d91c3 JB |
490 | /* free SKB */ |
491 | if (txq->txb) { | |
492 | struct sk_buff *skb; | |
6f80240e | 493 | |
ff0d91c3 | 494 | skb = txq->txb[txq->q.read_ptr].skb; |
6f80240e | 495 | |
ff0d91c3 JB |
496 | /* can be called from irqs-disabled context */ |
497 | if (skb) { | |
498 | dev_kfree_skb_any(skb); | |
499 | txq->txb[txq->q.read_ptr].skb = NULL; | |
7aaa1d79 SO |
500 | } |
501 | } | |
502 | } | |
503 | ||
504 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
505 | struct iwl_tx_queue *txq, | |
506 | dma_addr_t addr, u16 len, | |
507 | u8 reset, u8 pad) | |
508 | { | |
509 | struct iwl_queue *q; | |
59606ffa | 510 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
511 | u32 num_tbs; |
512 | ||
513 | q = &txq->q; | |
59606ffa SO |
514 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
515 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
516 | |
517 | if (reset) | |
518 | memset(tfd, 0, sizeof(*tfd)); | |
519 | ||
520 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
521 | ||
522 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
523 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
524 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
525 | IWL_NUM_OF_TBS); | |
526 | return -EINVAL; | |
527 | } | |
528 | ||
529 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
530 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
531 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
532 | (unsigned long long)addr); | |
533 | ||
534 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
a8e74e27 SO |
539 | /* |
540 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
541 | * given Tx queue, and enable the DMA channel used for that queue. | |
542 | * | |
543 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
544 | * channels supported in hardware. | |
545 | */ | |
546 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
547 | struct iwl_tx_queue *txq) | |
548 | { | |
a8e74e27 SO |
549 | int txq_id = txq->q.id; |
550 | ||
a8e74e27 SO |
551 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
552 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
553 | txq->q.dma_addr >> 8); | |
554 | ||
a8e74e27 SO |
555 | return 0; |
556 | } | |
557 | ||
b481de9c ZY |
558 | /****************************************************************************** |
559 | * | |
560 | * Generic RX handler implementations | |
561 | * | |
562 | ******************************************************************************/ | |
885ba202 TW |
563 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
564 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 565 | { |
2f301227 | 566 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
885ba202 | 567 | struct iwl_alive_resp *palive; |
b481de9c ZY |
568 | struct delayed_work *pwork; |
569 | ||
570 | palive = &pkt->u.alive_frame; | |
571 | ||
e1623446 | 572 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
573 | "0x%01X 0x%01X\n", |
574 | palive->is_valid, palive->ver_type, | |
575 | palive->ver_subtype); | |
576 | ||
577 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 578 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
579 | memcpy(&priv->card_alive_init, |
580 | &pkt->u.alive_frame, | |
885ba202 | 581 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
582 | pwork = &priv->init_alive_start; |
583 | } else { | |
e1623446 | 584 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 585 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 586 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
587 | pwork = &priv->alive_start; |
588 | } | |
589 | ||
590 | /* We delay the ALIVE response by 5ms to | |
591 | * give the HW RF Kill time to activate... */ | |
592 | if (palive->is_valid == UCODE_VALID_OK) | |
593 | queue_delayed_work(priv->workqueue, pwork, | |
594 | msecs_to_jiffies(5)); | |
595 | else | |
39aadf8c | 596 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
597 | } |
598 | ||
5b9f8cd3 | 599 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 600 | { |
c79dd5b5 TW |
601 | struct iwl_priv *priv = |
602 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
603 | struct sk_buff *beacon; |
604 | ||
605 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 606 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
607 | |
608 | if (!beacon) { | |
15b1687c | 609 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
610 | return; |
611 | } | |
612 | ||
613 | mutex_lock(&priv->mutex); | |
614 | /* new beacon skb is allocated every time; dispose previous.*/ | |
615 | if (priv->ibss_beacon) | |
616 | dev_kfree_skb(priv->ibss_beacon); | |
617 | ||
618 | priv->ibss_beacon = beacon; | |
619 | mutex_unlock(&priv->mutex); | |
620 | ||
5b9f8cd3 | 621 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
622 | } |
623 | ||
fbba9410 WYG |
624 | static void iwl_bg_bt_runtime_config(struct work_struct *work) |
625 | { | |
626 | struct iwl_priv *priv = | |
627 | container_of(work, struct iwl_priv, bt_runtime_config); | |
628 | ||
629 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
630 | return; | |
631 | ||
632 | /* dont send host command if rf-kill is on */ | |
633 | if (!iwl_is_ready_rf(priv)) | |
634 | return; | |
635 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
636 | } | |
637 | ||
bee008b7 WYG |
638 | static void iwl_bg_bt_full_concurrency(struct work_struct *work) |
639 | { | |
640 | struct iwl_priv *priv = | |
641 | container_of(work, struct iwl_priv, bt_full_concurrency); | |
246ed355 | 642 | struct iwl_rxon_context *ctx; |
bee008b7 WYG |
643 | |
644 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
645 | return; | |
646 | ||
647 | /* dont send host command if rf-kill is on */ | |
648 | if (!iwl_is_ready_rf(priv)) | |
649 | return; | |
650 | ||
651 | IWL_DEBUG_INFO(priv, "BT coex in %s mode\n", | |
652 | priv->bt_full_concurrent ? | |
653 | "full concurrency" : "3-wire"); | |
654 | ||
655 | /* | |
656 | * LQ & RXON updated cmds must be sent before BT Config cmd | |
657 | * to avoid 3-wire collisions | |
658 | */ | |
246ed355 JB |
659 | mutex_lock(&priv->mutex); |
660 | for_each_context(priv, ctx) { | |
661 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
662 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
663 | iwlcore_commit_rxon(priv, ctx); | |
664 | } | |
665 | mutex_unlock(&priv->mutex); | |
bee008b7 WYG |
666 | |
667 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
668 | } | |
669 | ||
4e39317d | 670 | /** |
5b9f8cd3 | 671 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
672 | * |
673 | * This callback is provided in order to send a statistics request. | |
674 | * | |
675 | * This timer function is continually reset to execute within | |
676 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
677 | * was received. We need to ensure we receive the statistics in order | |
678 | * to update the temperature used for calibrating the TXPOWER. | |
679 | */ | |
5b9f8cd3 | 680 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
681 | { |
682 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
683 | ||
684 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
685 | return; | |
686 | ||
61780ee3 MA |
687 | /* dont send host command if rf-kill is on */ |
688 | if (!iwl_is_ready_rf(priv)) | |
689 | return; | |
690 | ||
ef8d5529 | 691 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
692 | } |
693 | ||
a9e1cb6a WYG |
694 | |
695 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
696 | u32 start_idx, u32 num_events, | |
697 | u32 mode) | |
698 | { | |
699 | u32 i; | |
700 | u32 ptr; /* SRAM byte address of log data */ | |
701 | u32 ev, time, data; /* event log data */ | |
702 | unsigned long reg_flags; | |
703 | ||
704 | if (mode == 0) | |
705 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
706 | else | |
707 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
708 | ||
709 | /* Make sure device is powered up for SRAM reads */ | |
710 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
711 | if (iwl_grab_nic_access(priv)) { | |
712 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
713 | return; | |
714 | } | |
715 | ||
716 | /* Set starting address; reads will auto-increment */ | |
717 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
718 | rmb(); | |
719 | ||
720 | /* | |
721 | * "time" is actually "data" for mode 0 (no timestamp). | |
722 | * place event id # at far right for easier visual parsing. | |
723 | */ | |
724 | for (i = 0; i < num_events; i++) { | |
725 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
726 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
727 | if (mode == 0) { | |
728 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
729 | 0, time, ev); | |
730 | } else { | |
731 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
732 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
733 | time, data, ev); | |
734 | } | |
735 | } | |
736 | /* Allow device to power down */ | |
737 | iwl_release_nic_access(priv); | |
738 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
739 | } | |
740 | ||
875295f1 | 741 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
742 | { |
743 | u32 capacity; /* event log capacity in # entries */ | |
744 | u32 base; /* SRAM byte address of event log header */ | |
745 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
746 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
747 | u32 next_entry; /* index of next entry to be written by uCode */ | |
748 | ||
749 | if (priv->ucode_type == UCODE_INIT) | |
750 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
751 | else | |
752 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
753 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
754 | capacity = iwl_read_targ_mem(priv, base); | |
755 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
756 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
757 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
758 | } else | |
759 | return; | |
760 | ||
761 | if (num_wraps == priv->event_log.num_wraps) { | |
762 | iwl_print_cont_event_trace(priv, | |
763 | base, priv->event_log.next_entry, | |
764 | next_entry - priv->event_log.next_entry, | |
765 | mode); | |
766 | priv->event_log.non_wraps_count++; | |
767 | } else { | |
768 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
769 | priv->event_log.wraps_more_count++; | |
770 | else | |
771 | priv->event_log.wraps_once_count++; | |
772 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
773 | num_wraps - priv->event_log.num_wraps, | |
774 | next_entry, priv->event_log.next_entry); | |
775 | if (next_entry < priv->event_log.next_entry) { | |
776 | iwl_print_cont_event_trace(priv, base, | |
777 | priv->event_log.next_entry, | |
778 | capacity - priv->event_log.next_entry, | |
779 | mode); | |
780 | ||
781 | iwl_print_cont_event_trace(priv, base, 0, | |
782 | next_entry, mode); | |
783 | } else { | |
784 | iwl_print_cont_event_trace(priv, base, | |
785 | next_entry, capacity - next_entry, | |
786 | mode); | |
787 | ||
788 | iwl_print_cont_event_trace(priv, base, 0, | |
789 | next_entry, mode); | |
790 | } | |
791 | } | |
792 | priv->event_log.num_wraps = num_wraps; | |
793 | priv->event_log.next_entry = next_entry; | |
794 | } | |
795 | ||
796 | /** | |
797 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
798 | * | |
799 | * The timer is continually set to execute every | |
800 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
801 | * this function is to perform continuous uCode event logging operation | |
802 | * if enabled | |
803 | */ | |
804 | static void iwl_bg_ucode_trace(unsigned long data) | |
805 | { | |
806 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
807 | ||
808 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
809 | return; | |
810 | ||
811 | if (priv->event_log.ucode_trace) { | |
812 | iwl_continuous_event_trace(priv); | |
813 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
814 | mod_timer(&priv->ucode_trace, | |
815 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
816 | } | |
817 | } | |
818 | ||
5b9f8cd3 | 819 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 820 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 821 | { |
2f301227 | 822 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
2aa6ab86 TW |
823 | struct iwl4965_beacon_notif *beacon = |
824 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
a85d7cca | 825 | #ifdef CONFIG_IWLWIFI_DEBUG |
e7d326ac | 826 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 827 | |
e1623446 | 828 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 829 | "tsf %d %d rate %d\n", |
25a6572c | 830 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
831 | beacon->beacon_notify_hdr.failure_frame, |
832 | le32_to_cpu(beacon->ibss_mgr_status), | |
833 | le32_to_cpu(beacon->high_tsf), | |
834 | le32_to_cpu(beacon->low_tsf), rate); | |
835 | #endif | |
836 | ||
a85d7cca JB |
837 | priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); |
838 | ||
05c914fe | 839 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
840 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
841 | queue_work(priv->workqueue, &priv->beacon_update); | |
842 | } | |
843 | ||
b481de9c ZY |
844 | /* Handle notification from uCode that card's power state is changing |
845 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 846 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 847 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 848 | { |
2f301227 | 849 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
850 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
851 | unsigned long status = priv->status; | |
852 | ||
3a41bbd5 | 853 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n", |
b481de9c | 854 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
3a41bbd5 WYG |
855 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", |
856 | (flags & CT_CARD_DISABLED) ? | |
857 | "Reached" : "Not reached"); | |
b481de9c ZY |
858 | |
859 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3a41bbd5 | 860 | CT_CARD_DISABLED)) { |
b481de9c | 861 | |
3395f6e9 | 862 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
863 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
864 | ||
a8b50a0a MA |
865 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
866 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
867 | |
868 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 869 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 870 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 871 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 872 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 873 | } |
3a41bbd5 | 874 | if (flags & CT_CARD_DISABLED) |
39b73fb1 | 875 | iwl_tt_enter_ct_kill(priv); |
b481de9c | 876 | } |
3a41bbd5 | 877 | if (!(flags & CT_CARD_DISABLED)) |
39b73fb1 | 878 | iwl_tt_exit_ct_kill(priv); |
b481de9c ZY |
879 | |
880 | if (flags & HW_CARD_DISABLED) | |
881 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
882 | else | |
883 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
884 | ||
885 | ||
b481de9c | 886 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 887 | iwl_scan_cancel(priv); |
b481de9c ZY |
888 | |
889 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
890 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
891 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
892 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
893 | else |
894 | wake_up_interruptible(&priv->wait_command_queue); | |
895 | } | |
896 | ||
5b9f8cd3 | 897 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 898 | { |
e2e3c57b | 899 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 900 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
901 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
902 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
903 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
904 | } else { | |
905 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
906 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
907 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
908 | } | |
909 | ||
a8b50a0a | 910 | return 0; |
e2e3c57b TW |
911 | } |
912 | ||
65550636 WYG |
913 | static void iwl_bg_tx_flush(struct work_struct *work) |
914 | { | |
915 | struct iwl_priv *priv = | |
916 | container_of(work, struct iwl_priv, tx_flush); | |
917 | ||
918 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
919 | return; | |
920 | ||
921 | /* do nothing if rf-kill is on */ | |
922 | if (!iwl_is_ready_rf(priv)) | |
923 | return; | |
924 | ||
925 | if (priv->cfg->ops->lib->txfifo_flush) { | |
926 | IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n"); | |
927 | iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL); | |
928 | } | |
929 | } | |
930 | ||
b481de9c | 931 | /** |
5b9f8cd3 | 932 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
933 | * |
934 | * Setup the RX handlers for each of the reply types sent from the uCode | |
935 | * to the host. | |
936 | * | |
937 | * This function chains into the hardware specific files for them to setup | |
938 | * any hardware specific handlers as well. | |
939 | */ | |
653fa4a0 | 940 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 941 | { |
885ba202 | 942 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
943 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
944 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
81963d68 RC |
945 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
946 | iwl_rx_spectrum_measure_notif; | |
5b9f8cd3 | 947 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 948 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
949 | iwl_rx_pm_debug_statistics_notif; |
950 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 951 | |
9fbab516 BC |
952 | /* |
953 | * The same handler is used for both the REPLY to a discrete | |
954 | * statistics request from the host as well as for the periodic | |
955 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 956 | */ |
ef8d5529 | 957 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics; |
8f91aecb | 958 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; |
2a421b91 TW |
959 | |
960 | iwl_setup_rx_scan_handlers(priv); | |
961 | ||
37a44211 | 962 | /* status change handler */ |
5b9f8cd3 | 963 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 964 | |
c1354754 TW |
965 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
966 | iwl_rx_missed_beacon_notif; | |
37a44211 | 967 | /* Rx handlers */ |
8d801080 WYG |
968 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy; |
969 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx; | |
653fa4a0 | 970 | /* block ack */ |
74bcdb33 | 971 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba; |
9fbab516 | 972 | /* Set up hardware specific Rx handlers */ |
d4789efe | 973 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
974 | } |
975 | ||
b481de9c | 976 | /** |
a55360e4 | 977 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
978 | * |
979 | * Uses the priv->rx_handlers callback function array to invoke | |
980 | * the appropriate handlers, including command responses, | |
981 | * frame-received notifications, and other notifications. | |
982 | */ | |
a55360e4 | 983 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 984 | { |
a55360e4 | 985 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 986 | struct iwl_rx_packet *pkt; |
a55360e4 | 987 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
988 | u32 r, i; |
989 | int reclaim; | |
990 | unsigned long flags; | |
5c0eef96 | 991 | u8 fill_rx = 0; |
d68ab680 | 992 | u32 count = 8; |
4752c93c | 993 | int total_empty; |
b481de9c | 994 | |
6440adb5 BC |
995 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
996 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 997 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
998 | i = rxq->read; |
999 | ||
1000 | /* Rx interrupt, but nothing sent from uCode */ | |
1001 | if (i == r) | |
e1623446 | 1002 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 1003 | |
4752c93c | 1004 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 1005 | total_empty = r - rxq->write_actual; |
4752c93c MA |
1006 | if (total_empty < 0) |
1007 | total_empty += RX_QUEUE_SIZE; | |
1008 | ||
1009 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
1010 | fill_rx = 1; |
1011 | ||
b481de9c | 1012 | while (i != r) { |
f4989d9b JB |
1013 | int len; |
1014 | ||
b481de9c ZY |
1015 | rxb = rxq->queue[i]; |
1016 | ||
9fbab516 | 1017 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
1018 | * then a bug has been introduced in the queue refilling |
1019 | * routines -- catch it here */ | |
1020 | BUG_ON(rxb == NULL); | |
1021 | ||
1022 | rxq->queue[i] = NULL; | |
1023 | ||
2f301227 ZY |
1024 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
1025 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1026 | PCI_DMA_FROMDEVICE); | |
1027 | pkt = rxb_addr(rxb); | |
b481de9c | 1028 | |
f4989d9b JB |
1029 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
1030 | len += sizeof(u32); /* account for status word */ | |
1031 | trace_iwlwifi_dev_rx(priv, pkt, len); | |
be1a71a1 | 1032 | |
b481de9c ZY |
1033 | /* Reclaim a command buffer only if this packet is a response |
1034 | * to a (driver-originated) command. | |
1035 | * If the packet (e.g. Rx frame) originated from uCode, | |
1036 | * there is no command buffer to reclaim. | |
1037 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1038 | * but apparently a few don't get set; catch them here. */ | |
1039 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1040 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 1041 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 1042 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 1043 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
1044 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
1045 | (pkt->hdr.cmd != REPLY_TX); | |
1046 | ||
1047 | /* Based on type of command response or notification, | |
1048 | * handle those that need handling via function in | |
5b9f8cd3 | 1049 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 1050 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 1051 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 1052 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 1053 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 1054 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
1055 | } else { |
1056 | /* No handling needed */ | |
e1623446 | 1057 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
1058 | "r %d i %d No handler needed for %s, 0x%02x\n", |
1059 | r, i, get_cmd_string(pkt->hdr.cmd), | |
1060 | pkt->hdr.cmd); | |
1061 | } | |
1062 | ||
29b1b268 ZY |
1063 | /* |
1064 | * XXX: After here, we should always check rxb->page | |
1065 | * against NULL before touching it or its virtual | |
1066 | * memory (pkt). Because some rx_handler might have | |
1067 | * already taken or freed the pages. | |
1068 | */ | |
1069 | ||
b481de9c | 1070 | if (reclaim) { |
2f301227 ZY |
1071 | /* Invoke any callbacks, transfer the buffer to caller, |
1072 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 1073 | * as we reclaim the driver command queue */ |
29b1b268 | 1074 | if (rxb->page) |
17b88929 | 1075 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1076 | else |
39aadf8c | 1077 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1078 | } |
1079 | ||
7300515d ZY |
1080 | /* Reuse the page if possible. For notification packets and |
1081 | * SKBs that fail to Rx correctly, add them back into the | |
1082 | * rx_free list for reuse later. */ | |
1083 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1084 | if (rxb->page != NULL) { |
7300515d ZY |
1085 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
1086 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
1087 | PCI_DMA_FROMDEVICE); | |
1088 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1089 | rxq->free_count++; | |
1090 | } else | |
1091 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 1092 | |
b481de9c | 1093 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 1094 | |
b481de9c | 1095 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
1096 | /* If there are a lot of unused frames, |
1097 | * restock the Rx queue so ucode wont assert. */ | |
1098 | if (fill_rx) { | |
1099 | count++; | |
1100 | if (count >= 8) { | |
7300515d | 1101 | rxq->read = i; |
54b81550 | 1102 | iwlagn_rx_replenish_now(priv); |
5c0eef96 MA |
1103 | count = 0; |
1104 | } | |
1105 | } | |
b481de9c ZY |
1106 | } |
1107 | ||
1108 | /* Backtrack one entry */ | |
7300515d | 1109 | rxq->read = i; |
4752c93c | 1110 | if (fill_rx) |
54b81550 | 1111 | iwlagn_rx_replenish_now(priv); |
4752c93c | 1112 | else |
54b81550 | 1113 | iwlagn_rx_queue_restock(priv); |
a55360e4 | 1114 | } |
a55360e4 | 1115 | |
0359facc MA |
1116 | /* call this function to flush any scheduled tasklet */ |
1117 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
1118 | { | |
a96a27f9 | 1119 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1120 | synchronize_irq(priv->pci_dev->irq); |
1121 | tasklet_kill(&priv->irq_tasklet); | |
1122 | } | |
1123 | ||
ef850d7c | 1124 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
1125 | { |
1126 | u32 inta, handled = 0; | |
1127 | u32 inta_fh; | |
1128 | unsigned long flags; | |
c2e61da2 | 1129 | u32 i; |
0a6857e7 | 1130 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1131 | u32 inta_mask; |
1132 | #endif | |
1133 | ||
1134 | spin_lock_irqsave(&priv->lock, flags); | |
1135 | ||
1136 | /* Ack/clear/reset pending uCode interrupts. | |
1137 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1138 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
1139 | inta = iwl_read32(priv, CSR_INT); |
1140 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1141 | |
1142 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1143 | * Any new interrupts that happen after this, either while we're | |
1144 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
1145 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1146 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1147 | |
0a6857e7 | 1148 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1149 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1150 | /* just for debug */ |
3395f6e9 | 1151 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1152 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1153 | inta, inta_mask, inta_fh); |
1154 | } | |
1155 | #endif | |
1156 | ||
2f301227 ZY |
1157 | spin_unlock_irqrestore(&priv->lock, flags); |
1158 | ||
b481de9c ZY |
1159 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1160 | * atomic, make sure that inta covers all the interrupts that | |
1161 | * we've discovered, even if FH interrupt came in just after | |
1162 | * reading CSR_INT. */ | |
6f83eaa1 | 1163 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 1164 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1165 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
1166 | inta |= CSR_INT_BIT_FH_TX; |
1167 | ||
1168 | /* Now service all interrupt bits discovered above. */ | |
1169 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1170 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1171 | |
1172 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 1173 | iwl_disable_interrupts(priv); |
b481de9c | 1174 | |
a83b9141 | 1175 | priv->isr_stats.hw++; |
5b9f8cd3 | 1176 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1177 | |
1178 | handled |= CSR_INT_BIT_HW_ERR; | |
1179 | ||
b481de9c ZY |
1180 | return; |
1181 | } | |
1182 | ||
0a6857e7 | 1183 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1184 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1185 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 1186 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1187 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1188 | "the frame/frames.\n"); |
a83b9141 WYG |
1189 | priv->isr_stats.sch++; |
1190 | } | |
b481de9c ZY |
1191 | |
1192 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 1193 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1194 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
1195 | priv->isr_stats.alive++; |
1196 | } | |
b481de9c ZY |
1197 | } |
1198 | #endif | |
1199 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1200 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1201 | |
9fbab516 | 1202 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1203 | if (inta & CSR_INT_BIT_RF_KILL) { |
1204 | int hw_rf_kill = 0; | |
3395f6e9 | 1205 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1206 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1207 | hw_rf_kill = 1; | |
1208 | ||
4c423a2b | 1209 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1210 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1211 | |
a83b9141 WYG |
1212 | priv->isr_stats.rfkill++; |
1213 | ||
a9efa652 | 1214 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1215 | * the driver allows loading the ucode even if the radio |
1216 | * is killed. Hence update the killswitch state here. The | |
1217 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1218 | */ |
6cd0b1cb HS |
1219 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1220 | if (hw_rf_kill) | |
1221 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1222 | else | |
1223 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1224 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 1225 | } |
b481de9c ZY |
1226 | |
1227 | handled |= CSR_INT_BIT_RF_KILL; | |
1228 | } | |
1229 | ||
9fbab516 | 1230 | /* Chip got too hot and stopped itself */ |
b481de9c | 1231 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1232 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 1233 | priv->isr_stats.ctkill++; |
b481de9c ZY |
1234 | handled |= CSR_INT_BIT_CT_KILL; |
1235 | } | |
1236 | ||
1237 | /* Error detected by uCode */ | |
1238 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1239 | IWL_ERR(priv, "Microcode SW error detected. " |
1240 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
1241 | priv->isr_stats.sw++; |
1242 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 1243 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1244 | handled |= CSR_INT_BIT_SW_ERR; |
1245 | } | |
1246 | ||
c2e61da2 BC |
1247 | /* |
1248 | * uCode wakes up after power-down sleep. | |
1249 | * Tell device about any new tx or host commands enqueued, | |
1250 | * and about any Rx buffers made available while asleep. | |
1251 | */ | |
b481de9c | 1252 | if (inta & CSR_INT_BIT_WAKEUP) { |
e1623446 | 1253 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1254 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
c2e61da2 BC |
1255 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1256 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
a83b9141 | 1257 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1258 | handled |= CSR_INT_BIT_WAKEUP; |
1259 | } | |
1260 | ||
1261 | /* All uCode command responses, including Tx command responses, | |
1262 | * Rx "responses" (frame-received notification), and other | |
1263 | * notifications from uCode come through here*/ | |
1264 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1265 | iwl_rx_handle(priv); |
a83b9141 | 1266 | priv->isr_stats.rx++; |
b481de9c ZY |
1267 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1268 | } | |
1269 | ||
c72cd19f | 1270 | /* This "Tx" DMA channel is used only for loading uCode */ |
b481de9c | 1271 | if (inta & CSR_INT_BIT_FH_TX) { |
c72cd19f | 1272 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
a83b9141 | 1273 | priv->isr_stats.tx++; |
b481de9c | 1274 | handled |= CSR_INT_BIT_FH_TX; |
c72cd19f | 1275 | /* Wake up uCode load routine, now that load is complete */ |
dbb983b7 RR |
1276 | priv->ucode_write_complete = 1; |
1277 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1278 | } |
1279 | ||
a83b9141 | 1280 | if (inta & ~handled) { |
15b1687c | 1281 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1282 | priv->isr_stats.unhandled++; |
1283 | } | |
b481de9c | 1284 | |
40cefda9 | 1285 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1286 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1287 | inta & ~priv->inta_mask); |
39aadf8c | 1288 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1289 | } |
1290 | ||
1291 | /* Re-enable all interrupts */ | |
0359facc MA |
1292 | /* only Re-enable if diabled by irq */ |
1293 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1294 | iwl_enable_interrupts(priv); |
b481de9c | 1295 | |
0a6857e7 | 1296 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1297 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1298 | inta = iwl_read32(priv, CSR_INT); |
1299 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1300 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1301 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1302 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1303 | } | |
1304 | #endif | |
b481de9c ZY |
1305 | } |
1306 | ||
ef850d7c MA |
1307 | /* tasklet for iwlagn interrupt */ |
1308 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1309 | { | |
1310 | u32 inta = 0; | |
1311 | u32 handled = 0; | |
1312 | unsigned long flags; | |
8756990f | 1313 | u32 i; |
ef850d7c MA |
1314 | #ifdef CONFIG_IWLWIFI_DEBUG |
1315 | u32 inta_mask; | |
1316 | #endif | |
1317 | ||
1318 | spin_lock_irqsave(&priv->lock, flags); | |
1319 | ||
1320 | /* Ack/clear/reset pending uCode interrupts. | |
1321 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1322 | */ | |
48a6be6a SZ |
1323 | /* There is a hardware bug in the interrupt mask function that some |
1324 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
1325 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
1326 | * ICT interrupt handling mechanism has another bug that might cause | |
1327 | * these unmasked interrupts fail to be detected. We workaround the | |
1328 | * hardware bugs here by ACKing all the possible interrupts so that | |
1329 | * interrupt coalescing can still be achieved. | |
1330 | */ | |
4a35ecf8 | 1331 | iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask); |
ef850d7c | 1332 | |
a4c8b2a6 | 1333 | inta = priv->_agn.inta; |
ef850d7c MA |
1334 | |
1335 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1336 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1337 | /* just for debug */ |
1338 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1339 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1340 | inta, inta_mask); | |
1341 | } | |
1342 | #endif | |
2f301227 ZY |
1343 | |
1344 | spin_unlock_irqrestore(&priv->lock, flags); | |
1345 | ||
a4c8b2a6 JB |
1346 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ |
1347 | priv->_agn.inta = 0; | |
ef850d7c MA |
1348 | |
1349 | /* Now service all interrupt bits discovered above. */ | |
1350 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1351 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1352 | |
1353 | /* Tell the device to stop sending interrupts */ | |
1354 | iwl_disable_interrupts(priv); | |
1355 | ||
1356 | priv->isr_stats.hw++; | |
1357 | iwl_irq_handle_error(priv); | |
1358 | ||
1359 | handled |= CSR_INT_BIT_HW_ERR; | |
1360 | ||
ef850d7c MA |
1361 | return; |
1362 | } | |
1363 | ||
1364 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1365 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1366 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1367 | if (inta & CSR_INT_BIT_SCD) { | |
1368 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1369 | "the frame/frames.\n"); | |
1370 | priv->isr_stats.sch++; | |
1371 | } | |
1372 | ||
1373 | /* Alive notification via Rx interrupt will do the real work */ | |
1374 | if (inta & CSR_INT_BIT_ALIVE) { | |
1375 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1376 | priv->isr_stats.alive++; | |
1377 | } | |
1378 | } | |
1379 | #endif | |
1380 | /* Safely ignore these bits for debug checks below */ | |
1381 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1382 | ||
1383 | /* HW RF KILL switch toggled */ | |
1384 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1385 | int hw_rf_kill = 0; | |
1386 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1387 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1388 | hw_rf_kill = 1; | |
1389 | ||
4c423a2b | 1390 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1391 | hw_rf_kill ? "disable radio" : "enable radio"); |
1392 | ||
1393 | priv->isr_stats.rfkill++; | |
1394 | ||
1395 | /* driver only loads ucode once setting the interface up. | |
1396 | * the driver allows loading the ucode even if the radio | |
1397 | * is killed. Hence update the killswitch state here. The | |
1398 | * rfkill handler will care about restarting if needed. | |
1399 | */ | |
1400 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1401 | if (hw_rf_kill) | |
1402 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1403 | else | |
1404 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1405 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1406 | } |
1407 | ||
1408 | handled |= CSR_INT_BIT_RF_KILL; | |
1409 | } | |
1410 | ||
1411 | /* Chip got too hot and stopped itself */ | |
1412 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1413 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1414 | priv->isr_stats.ctkill++; | |
1415 | handled |= CSR_INT_BIT_CT_KILL; | |
1416 | } | |
1417 | ||
1418 | /* Error detected by uCode */ | |
1419 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1420 | IWL_ERR(priv, "Microcode SW error detected. " | |
1421 | " Restarting 0x%X.\n", inta); | |
1422 | priv->isr_stats.sw++; | |
1423 | priv->isr_stats.sw_err = inta; | |
1424 | iwl_irq_handle_error(priv); | |
1425 | handled |= CSR_INT_BIT_SW_ERR; | |
1426 | } | |
1427 | ||
1428 | /* uCode wakes up after power-down sleep */ | |
1429 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1430 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1431 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
1432 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1433 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
1434 | |
1435 | priv->isr_stats.wakeup++; | |
1436 | ||
1437 | handled |= CSR_INT_BIT_WAKEUP; | |
1438 | } | |
1439 | ||
1440 | /* All uCode command responses, including Tx command responses, | |
1441 | * Rx "responses" (frame-received notification), and other | |
1442 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1443 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1444 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1445 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1446 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1447 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1448 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1449 | CSR49_FH_INT_RX_MASK); | |
1450 | } | |
1451 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1452 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1453 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1454 | } | |
1455 | /* Sending RX interrupt require many steps to be done in the | |
1456 | * the device: | |
1457 | * 1- write interrupt to current index in ICT table. | |
1458 | * 2- dma RX frame. | |
1459 | * 3- update RX shared data to indicate last write index. | |
1460 | * 4- send interrupt. | |
1461 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
1462 | * but the shared data changes does not reflect this; |
1463 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 1464 | */ |
74ba67ed BC |
1465 | |
1466 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1467 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 1468 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 1469 | iwl_rx_handle(priv); |
74ba67ed BC |
1470 | |
1471 | /* | |
1472 | * Enable periodic interrupt in 8 msec only if we received | |
1473 | * real RX interrupt (instead of just periodic int), to catch | |
1474 | * any dangling Rx interrupt. If it was just the periodic | |
1475 | * interrupt, there was no dangling Rx activity, and no need | |
1476 | * to extend the periodic interrupt; one-shot is enough. | |
1477 | */ | |
40cefda9 | 1478 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 1479 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
1480 | CSR_INT_PERIODIC_ENA); |
1481 | ||
ef850d7c | 1482 | priv->isr_stats.rx++; |
ef850d7c MA |
1483 | } |
1484 | ||
c72cd19f | 1485 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c MA |
1486 | if (inta & CSR_INT_BIT_FH_TX) { |
1487 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
c72cd19f | 1488 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
1489 | priv->isr_stats.tx++; |
1490 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 1491 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
1492 | priv->ucode_write_complete = 1; |
1493 | wake_up_interruptible(&priv->wait_command_queue); | |
1494 | } | |
1495 | ||
1496 | if (inta & ~handled) { | |
1497 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1498 | priv->isr_stats.unhandled++; | |
1499 | } | |
1500 | ||
40cefda9 | 1501 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1502 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1503 | inta & ~priv->inta_mask); |
ef850d7c MA |
1504 | } |
1505 | ||
ef850d7c MA |
1506 | /* Re-enable all interrupts */ |
1507 | /* only Re-enable if diabled by irq */ | |
1508 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1509 | iwl_enable_interrupts(priv); | |
ef850d7c MA |
1510 | } |
1511 | ||
872c8ddc WYG |
1512 | /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */ |
1513 | #define ACK_CNT_RATIO (50) | |
1514 | #define BA_TIMEOUT_CNT (5) | |
1515 | #define BA_TIMEOUT_MAX (16) | |
1516 | ||
1517 | /** | |
1518 | * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries. | |
1519 | * | |
1520 | * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding | |
1521 | * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal | |
1522 | * operation state. | |
1523 | */ | |
1524 | bool iwl_good_ack_health(struct iwl_priv *priv, | |
1525 | struct iwl_rx_packet *pkt) | |
1526 | { | |
1527 | bool rc = true; | |
1528 | int actual_ack_cnt_delta, expected_ack_cnt_delta; | |
1529 | int ba_timeout_delta; | |
1530 | ||
1531 | actual_ack_cnt_delta = | |
1532 | le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) - | |
f3aebeee | 1533 | le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt); |
872c8ddc WYG |
1534 | expected_ack_cnt_delta = |
1535 | le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) - | |
f3aebeee | 1536 | le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt); |
872c8ddc WYG |
1537 | ba_timeout_delta = |
1538 | le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) - | |
f3aebeee | 1539 | le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout); |
872c8ddc WYG |
1540 | if ((priv->_agn.agg_tids_count > 0) && |
1541 | (expected_ack_cnt_delta > 0) && | |
1542 | (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta) | |
1543 | < ACK_CNT_RATIO) && | |
1544 | (ba_timeout_delta > BA_TIMEOUT_CNT)) { | |
1545 | IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d," | |
1546 | " expected_ack_cnt = %d\n", | |
1547 | actual_ack_cnt_delta, expected_ack_cnt_delta); | |
1548 | ||
d73e4923 JB |
1549 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1550 | /* | |
1551 | * This is ifdef'ed on DEBUGFS because otherwise the | |
1552 | * statistics aren't available. If DEBUGFS is set but | |
1553 | * DEBUG is not, these will just compile out. | |
1554 | */ | |
872c8ddc | 1555 | IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n", |
f3aebeee | 1556 | priv->_agn.delta_statistics.tx.rx_detected_cnt); |
872c8ddc WYG |
1557 | IWL_DEBUG_RADIO(priv, |
1558 | "ack_or_ba_timeout_collision delta = %d\n", | |
f3aebeee | 1559 | priv->_agn.delta_statistics.tx. |
872c8ddc WYG |
1560 | ack_or_ba_timeout_collision); |
1561 | #endif | |
1562 | IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n", | |
1563 | ba_timeout_delta); | |
1564 | if (!actual_ack_cnt_delta && | |
1565 | (ba_timeout_delta >= BA_TIMEOUT_MAX)) | |
1566 | rc = false; | |
1567 | } | |
1568 | return rc; | |
1569 | } | |
1570 | ||
a83b9141 | 1571 | |
7d47618a EG |
1572 | /***************************************************************************** |
1573 | * | |
1574 | * sysfs attributes | |
1575 | * | |
1576 | *****************************************************************************/ | |
1577 | ||
1578 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1579 | ||
1580 | /* | |
1581 | * The following adds a new attribute to the sysfs representation | |
1582 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) | |
1583 | * used for controlling the debug level. | |
1584 | * | |
1585 | * See the level definitions in iwl for details. | |
1586 | * | |
1587 | * The debug_level being managed using sysfs below is a per device debug | |
1588 | * level that is used instead of the global debug level if it (the per | |
1589 | * device debug level) is set. | |
1590 | */ | |
1591 | static ssize_t show_debug_level(struct device *d, | |
1592 | struct device_attribute *attr, char *buf) | |
1593 | { | |
1594 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1595 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
1596 | } | |
1597 | static ssize_t store_debug_level(struct device *d, | |
1598 | struct device_attribute *attr, | |
1599 | const char *buf, size_t count) | |
1600 | { | |
1601 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1602 | unsigned long val; | |
1603 | int ret; | |
1604 | ||
1605 | ret = strict_strtoul(buf, 0, &val); | |
1606 | if (ret) | |
1607 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); | |
1608 | else { | |
1609 | priv->debug_level = val; | |
1610 | if (iwl_alloc_traffic_mem(priv)) | |
1611 | IWL_ERR(priv, | |
1612 | "Not enough memory to generate traffic log\n"); | |
1613 | } | |
1614 | return strnlen(buf, count); | |
1615 | } | |
1616 | ||
1617 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
1618 | show_debug_level, store_debug_level); | |
1619 | ||
1620 | ||
1621 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
1622 | ||
1623 | ||
1624 | static ssize_t show_temperature(struct device *d, | |
1625 | struct device_attribute *attr, char *buf) | |
1626 | { | |
1627 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1628 | ||
1629 | if (!iwl_is_alive(priv)) | |
1630 | return -EAGAIN; | |
1631 | ||
1632 | return sprintf(buf, "%d\n", priv->temperature); | |
1633 | } | |
1634 | ||
1635 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
1636 | ||
1637 | static ssize_t show_tx_power(struct device *d, | |
1638 | struct device_attribute *attr, char *buf) | |
1639 | { | |
1640 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1641 | ||
1642 | if (!iwl_is_ready_rf(priv)) | |
1643 | return sprintf(buf, "off\n"); | |
1644 | else | |
1645 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
1646 | } | |
1647 | ||
1648 | static ssize_t store_tx_power(struct device *d, | |
1649 | struct device_attribute *attr, | |
1650 | const char *buf, size_t count) | |
1651 | { | |
1652 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1653 | unsigned long val; | |
1654 | int ret; | |
1655 | ||
1656 | ret = strict_strtoul(buf, 10, &val); | |
1657 | if (ret) | |
1658 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); | |
1659 | else { | |
1660 | ret = iwl_set_tx_power(priv, val, false); | |
1661 | if (ret) | |
1662 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
1663 | ret); | |
1664 | else | |
1665 | ret = count; | |
1666 | } | |
1667 | return ret; | |
1668 | } | |
1669 | ||
1670 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
1671 | ||
7d47618a EG |
1672 | static struct attribute *iwl_sysfs_entries[] = { |
1673 | &dev_attr_temperature.attr, | |
1674 | &dev_attr_tx_power.attr, | |
7d47618a EG |
1675 | #ifdef CONFIG_IWLWIFI_DEBUG |
1676 | &dev_attr_debug_level.attr, | |
1677 | #endif | |
1678 | NULL | |
1679 | }; | |
1680 | ||
1681 | static struct attribute_group iwl_attribute_group = { | |
1682 | .name = NULL, /* put in device directory */ | |
1683 | .attrs = iwl_sysfs_entries, | |
1684 | }; | |
1685 | ||
b481de9c ZY |
1686 | /****************************************************************************** |
1687 | * | |
1688 | * uCode download functions | |
1689 | * | |
1690 | ******************************************************************************/ | |
1691 | ||
5b9f8cd3 | 1692 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1693 | { |
98c92211 TW |
1694 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1695 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1696 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1697 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1698 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1699 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1700 | } |
1701 | ||
5b9f8cd3 | 1702 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1703 | { |
1704 | /* Remove all resets to allow NIC to operate */ | |
1705 | iwl_write32(priv, CSR_RESET, 0); | |
1706 | } | |
1707 | ||
dd7a2509 JB |
1708 | struct iwlagn_ucode_capabilities { |
1709 | u32 max_probe_length; | |
6a822d06 | 1710 | u32 standard_phy_calibration_size; |
dd7a2509 | 1711 | }; |
edcdf8b2 | 1712 | |
b08dfd04 | 1713 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
dd7a2509 JB |
1714 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
1715 | struct iwlagn_ucode_capabilities *capa); | |
b08dfd04 | 1716 | |
39396085 JS |
1717 | #define UCODE_EXPERIMENTAL_INDEX 100 |
1718 | #define UCODE_EXPERIMENTAL_TAG "exp" | |
1719 | ||
b08dfd04 JB |
1720 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) |
1721 | { | |
1722 | const char *name_pre = priv->cfg->fw_name_pre; | |
39396085 | 1723 | char tag[8]; |
b08dfd04 | 1724 | |
39396085 JS |
1725 | if (first) { |
1726 | #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE | |
1727 | priv->fw_index = UCODE_EXPERIMENTAL_INDEX; | |
1728 | strcpy(tag, UCODE_EXPERIMENTAL_TAG); | |
1729 | } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) { | |
1730 | #endif | |
b08dfd04 | 1731 | priv->fw_index = priv->cfg->ucode_api_max; |
39396085 JS |
1732 | sprintf(tag, "%d", priv->fw_index); |
1733 | } else { | |
b08dfd04 | 1734 | priv->fw_index--; |
39396085 JS |
1735 | sprintf(tag, "%d", priv->fw_index); |
1736 | } | |
b08dfd04 JB |
1737 | |
1738 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1739 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1740 | return -ENOENT; | |
1741 | } | |
1742 | ||
39396085 | 1743 | sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); |
b08dfd04 | 1744 | |
39396085 JS |
1745 | IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n", |
1746 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1747 | ? "EXPERIMENTAL " : "", | |
b08dfd04 JB |
1748 | priv->firmware_name); |
1749 | ||
1750 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
1751 | &priv->pci_dev->dev, GFP_KERNEL, priv, | |
1752 | iwl_ucode_callback); | |
1753 | } | |
1754 | ||
0e9a44dc JB |
1755 | struct iwlagn_firmware_pieces { |
1756 | const void *inst, *data, *init, *init_data, *boot; | |
1757 | size_t inst_size, data_size, init_size, init_data_size, boot_size; | |
1758 | ||
1759 | u32 build; | |
b2e640d4 JB |
1760 | |
1761 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1762 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
0e9a44dc JB |
1763 | }; |
1764 | ||
1765 | static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |
1766 | const struct firmware *ucode_raw, | |
1767 | struct iwlagn_firmware_pieces *pieces) | |
1768 | { | |
1769 | struct iwl_ucode_header *ucode = (void *)ucode_raw->data; | |
1770 | u32 api_ver, hdr_size; | |
1771 | const u8 *src; | |
1772 | ||
1773 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1774 | api_ver = IWL_UCODE_API(priv->ucode_ver); | |
1775 | ||
1776 | switch (api_ver) { | |
1777 | default: | |
1778 | /* | |
1779 | * 4965 doesn't revision the firmware file format | |
1780 | * along with the API version, it always uses v1 | |
1781 | * file format. | |
1782 | */ | |
1783 | if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) != | |
1784 | CSR_HW_REV_TYPE_4965) { | |
1785 | hdr_size = 28; | |
1786 | if (ucode_raw->size < hdr_size) { | |
1787 | IWL_ERR(priv, "File size too small!\n"); | |
1788 | return -EINVAL; | |
1789 | } | |
1790 | pieces->build = le32_to_cpu(ucode->u.v2.build); | |
1791 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | |
1792 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | |
1793 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | |
1794 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | |
1795 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | |
1796 | src = ucode->u.v2.data; | |
1797 | break; | |
1798 | } | |
1799 | /* fall through for 4965 */ | |
1800 | case 0: | |
1801 | case 1: | |
1802 | case 2: | |
1803 | hdr_size = 24; | |
1804 | if (ucode_raw->size < hdr_size) { | |
1805 | IWL_ERR(priv, "File size too small!\n"); | |
1806 | return -EINVAL; | |
1807 | } | |
1808 | pieces->build = 0; | |
1809 | pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size); | |
1810 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); | |
1811 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); | |
1812 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); | |
1813 | pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size); | |
1814 | src = ucode->u.v1.data; | |
1815 | break; | |
1816 | } | |
1817 | ||
1818 | /* Verify size of file vs. image size info in file's header */ | |
1819 | if (ucode_raw->size != hdr_size + pieces->inst_size + | |
1820 | pieces->data_size + pieces->init_size + | |
1821 | pieces->init_data_size + pieces->boot_size) { | |
1822 | ||
1823 | IWL_ERR(priv, | |
1824 | "uCode file size %d does not match expected size\n", | |
1825 | (int)ucode_raw->size); | |
1826 | return -EINVAL; | |
1827 | } | |
1828 | ||
1829 | pieces->inst = src; | |
1830 | src += pieces->inst_size; | |
1831 | pieces->data = src; | |
1832 | src += pieces->data_size; | |
1833 | pieces->init = src; | |
1834 | src += pieces->init_size; | |
1835 | pieces->init_data = src; | |
1836 | src += pieces->init_data_size; | |
1837 | pieces->boot = src; | |
1838 | src += pieces->boot_size; | |
1839 | ||
1840 | return 0; | |
1841 | } | |
1842 | ||
dd7a2509 JB |
1843 | static int iwlagn_wanted_ucode_alternative = 1; |
1844 | ||
1845 | static int iwlagn_load_firmware(struct iwl_priv *priv, | |
1846 | const struct firmware *ucode_raw, | |
1847 | struct iwlagn_firmware_pieces *pieces, | |
1848 | struct iwlagn_ucode_capabilities *capa) | |
1849 | { | |
1850 | struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data; | |
1851 | struct iwl_ucode_tlv *tlv; | |
1852 | size_t len = ucode_raw->size; | |
1853 | const u8 *data; | |
1854 | int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp; | |
1855 | u64 alternatives; | |
ad8d8333 WYG |
1856 | u32 tlv_len; |
1857 | enum iwl_ucode_tlv_type tlv_type; | |
1858 | const u8 *tlv_data; | |
dd7a2509 | 1859 | |
ad8d8333 WYG |
1860 | if (len < sizeof(*ucode)) { |
1861 | IWL_ERR(priv, "uCode has invalid length: %zd\n", len); | |
dd7a2509 | 1862 | return -EINVAL; |
ad8d8333 | 1863 | } |
dd7a2509 | 1864 | |
ad8d8333 WYG |
1865 | if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) { |
1866 | IWL_ERR(priv, "invalid uCode magic: 0X%x\n", | |
1867 | le32_to_cpu(ucode->magic)); | |
dd7a2509 | 1868 | return -EINVAL; |
ad8d8333 | 1869 | } |
dd7a2509 JB |
1870 | |
1871 | /* | |
1872 | * Check which alternatives are present, and "downgrade" | |
1873 | * when the chosen alternative is not present, warning | |
1874 | * the user when that happens. Some files may not have | |
1875 | * any alternatives, so don't warn in that case. | |
1876 | */ | |
1877 | alternatives = le64_to_cpu(ucode->alternatives); | |
1878 | tmp = wanted_alternative; | |
1879 | if (wanted_alternative > 63) | |
1880 | wanted_alternative = 63; | |
1881 | while (wanted_alternative && !(alternatives & BIT(wanted_alternative))) | |
1882 | wanted_alternative--; | |
1883 | if (wanted_alternative && wanted_alternative != tmp) | |
1884 | IWL_WARN(priv, | |
1885 | "uCode alternative %d not available, choosing %d\n", | |
1886 | tmp, wanted_alternative); | |
1887 | ||
1888 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1889 | pieces->build = le32_to_cpu(ucode->build); | |
1890 | data = ucode->data; | |
1891 | ||
1892 | len -= sizeof(*ucode); | |
1893 | ||
704da534 | 1894 | while (len >= sizeof(*tlv)) { |
dd7a2509 | 1895 | u16 tlv_alt; |
dd7a2509 JB |
1896 | |
1897 | len -= sizeof(*tlv); | |
1898 | tlv = (void *)data; | |
1899 | ||
1900 | tlv_len = le32_to_cpu(tlv->length); | |
1901 | tlv_type = le16_to_cpu(tlv->type); | |
1902 | tlv_alt = le16_to_cpu(tlv->alternative); | |
1903 | tlv_data = tlv->data; | |
1904 | ||
ad8d8333 WYG |
1905 | if (len < tlv_len) { |
1906 | IWL_ERR(priv, "invalid TLV len: %zd/%u\n", | |
1907 | len, tlv_len); | |
dd7a2509 | 1908 | return -EINVAL; |
ad8d8333 | 1909 | } |
dd7a2509 JB |
1910 | len -= ALIGN(tlv_len, 4); |
1911 | data += sizeof(*tlv) + ALIGN(tlv_len, 4); | |
1912 | ||
1913 | /* | |
1914 | * Alternative 0 is always valid. | |
1915 | * | |
1916 | * Skip alternative TLVs that are not selected. | |
1917 | */ | |
1918 | if (tlv_alt != 0 && tlv_alt != wanted_alternative) | |
1919 | continue; | |
1920 | ||
1921 | switch (tlv_type) { | |
1922 | case IWL_UCODE_TLV_INST: | |
1923 | pieces->inst = tlv_data; | |
1924 | pieces->inst_size = tlv_len; | |
1925 | break; | |
1926 | case IWL_UCODE_TLV_DATA: | |
1927 | pieces->data = tlv_data; | |
1928 | pieces->data_size = tlv_len; | |
1929 | break; | |
1930 | case IWL_UCODE_TLV_INIT: | |
1931 | pieces->init = tlv_data; | |
1932 | pieces->init_size = tlv_len; | |
1933 | break; | |
1934 | case IWL_UCODE_TLV_INIT_DATA: | |
1935 | pieces->init_data = tlv_data; | |
1936 | pieces->init_data_size = tlv_len; | |
1937 | break; | |
1938 | case IWL_UCODE_TLV_BOOT: | |
1939 | pieces->boot = tlv_data; | |
1940 | pieces->boot_size = tlv_len; | |
1941 | break; | |
1942 | case IWL_UCODE_TLV_PROBE_MAX_LEN: | |
704da534 JB |
1943 | if (tlv_len != sizeof(u32)) |
1944 | goto invalid_tlv_len; | |
1945 | capa->max_probe_length = | |
ad8d8333 | 1946 | le32_to_cpup((__le32 *)tlv_data); |
dd7a2509 | 1947 | break; |
b2e640d4 | 1948 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: |
704da534 JB |
1949 | if (tlv_len != sizeof(u32)) |
1950 | goto invalid_tlv_len; | |
1951 | pieces->init_evtlog_ptr = | |
ad8d8333 | 1952 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1953 | break; |
1954 | case IWL_UCODE_TLV_INIT_EVTLOG_SIZE: | |
704da534 JB |
1955 | if (tlv_len != sizeof(u32)) |
1956 | goto invalid_tlv_len; | |
1957 | pieces->init_evtlog_size = | |
ad8d8333 | 1958 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1959 | break; |
1960 | case IWL_UCODE_TLV_INIT_ERRLOG_PTR: | |
704da534 JB |
1961 | if (tlv_len != sizeof(u32)) |
1962 | goto invalid_tlv_len; | |
1963 | pieces->init_errlog_ptr = | |
ad8d8333 | 1964 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1965 | break; |
1966 | case IWL_UCODE_TLV_RUNT_EVTLOG_PTR: | |
704da534 JB |
1967 | if (tlv_len != sizeof(u32)) |
1968 | goto invalid_tlv_len; | |
1969 | pieces->inst_evtlog_ptr = | |
ad8d8333 | 1970 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1971 | break; |
1972 | case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE: | |
704da534 JB |
1973 | if (tlv_len != sizeof(u32)) |
1974 | goto invalid_tlv_len; | |
1975 | pieces->inst_evtlog_size = | |
ad8d8333 | 1976 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1977 | break; |
1978 | case IWL_UCODE_TLV_RUNT_ERRLOG_PTR: | |
704da534 JB |
1979 | if (tlv_len != sizeof(u32)) |
1980 | goto invalid_tlv_len; | |
1981 | pieces->inst_errlog_ptr = | |
ad8d8333 | 1982 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 | 1983 | break; |
c8312fac WYG |
1984 | case IWL_UCODE_TLV_ENHANCE_SENS_TBL: |
1985 | if (tlv_len) | |
704da534 JB |
1986 | goto invalid_tlv_len; |
1987 | priv->enhance_sensitivity_table = true; | |
c8312fac | 1988 | break; |
6a822d06 | 1989 | case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE: |
704da534 JB |
1990 | if (tlv_len != sizeof(u32)) |
1991 | goto invalid_tlv_len; | |
1992 | capa->standard_phy_calibration_size = | |
6a822d06 WYG |
1993 | le32_to_cpup((__le32 *)tlv_data); |
1994 | break; | |
dd7a2509 | 1995 | default: |
ad8d8333 | 1996 | IWL_WARN(priv, "unknown TLV: %d\n", tlv_type); |
dd7a2509 JB |
1997 | break; |
1998 | } | |
1999 | } | |
2000 | ||
ad8d8333 WYG |
2001 | if (len) { |
2002 | IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len); | |
2003 | iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len); | |
704da534 | 2004 | return -EINVAL; |
ad8d8333 | 2005 | } |
dd7a2509 | 2006 | |
704da534 JB |
2007 | return 0; |
2008 | ||
2009 | invalid_tlv_len: | |
2010 | IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len); | |
2011 | iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len); | |
2012 | ||
2013 | return -EINVAL; | |
dd7a2509 JB |
2014 | } |
2015 | ||
b481de9c | 2016 | /** |
b08dfd04 | 2017 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 2018 | * |
b08dfd04 JB |
2019 | * If loaded successfully, copies the firmware into buffers |
2020 | * for the card to fetch (via DMA). | |
b481de9c | 2021 | */ |
b08dfd04 | 2022 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 2023 | { |
b08dfd04 | 2024 | struct iwl_priv *priv = context; |
cc0f555d | 2025 | struct iwl_ucode_header *ucode; |
0e9a44dc JB |
2026 | int err; |
2027 | struct iwlagn_firmware_pieces pieces; | |
a0987a8d RC |
2028 | const unsigned int api_max = priv->cfg->ucode_api_max; |
2029 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
0e9a44dc | 2030 | u32 api_ver; |
3e4de761 | 2031 | char buildstr[25]; |
0e9a44dc | 2032 | u32 build; |
dd7a2509 JB |
2033 | struct iwlagn_ucode_capabilities ucode_capa = { |
2034 | .max_probe_length = 200, | |
6a822d06 WYG |
2035 | .standard_phy_calibration_size = |
2036 | IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE, | |
dd7a2509 | 2037 | }; |
0e9a44dc JB |
2038 | |
2039 | memset(&pieces, 0, sizeof(pieces)); | |
b481de9c | 2040 | |
b08dfd04 | 2041 | if (!ucode_raw) { |
39396085 JS |
2042 | if (priv->fw_index <= priv->cfg->ucode_api_max) |
2043 | IWL_ERR(priv, | |
2044 | "request for firmware file '%s' failed.\n", | |
2045 | priv->firmware_name); | |
b08dfd04 | 2046 | goto try_again; |
b481de9c ZY |
2047 | } |
2048 | ||
b08dfd04 JB |
2049 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
2050 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 2051 | |
22adba2a JB |
2052 | /* Make sure that we got at least the API version number */ |
2053 | if (ucode_raw->size < 4) { | |
15b1687c | 2054 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 2055 | goto try_again; |
b481de9c ZY |
2056 | } |
2057 | ||
2058 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 2059 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 2060 | |
0e9a44dc JB |
2061 | if (ucode->ver) |
2062 | err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces); | |
2063 | else | |
dd7a2509 JB |
2064 | err = iwlagn_load_firmware(priv, ucode_raw, &pieces, |
2065 | &ucode_capa); | |
22adba2a | 2066 | |
0e9a44dc JB |
2067 | if (err) |
2068 | goto try_again; | |
b481de9c | 2069 | |
a0987a8d | 2070 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
0e9a44dc | 2071 | build = pieces.build; |
a0987a8d | 2072 | |
0e9a44dc JB |
2073 | /* |
2074 | * api_ver should match the api version forming part of the | |
2075 | * firmware filename ... but we don't check for that and only rely | |
2076 | * on the API version read from firmware header from here on forward | |
2077 | */ | |
a0987a8d | 2078 | if (api_ver < api_min || api_ver > api_max) { |
15b1687c | 2079 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
2080 | "Driver supports v%u, firmware is v%u.\n", |
2081 | api_max, api_ver); | |
b08dfd04 | 2082 | goto try_again; |
a0987a8d | 2083 | } |
b08dfd04 | 2084 | |
a0987a8d | 2085 | if (api_ver != api_max) |
978785a3 | 2086 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
2087 | "got v%u. New firmware can be obtained " |
2088 | "from http://www.intellinuxwireless.org.\n", | |
2089 | api_max, api_ver); | |
2090 | ||
3e4de761 | 2091 | if (build) |
39396085 JS |
2092 | sprintf(buildstr, " build %u%s", build, |
2093 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
2094 | ? " (EXP)" : ""); | |
3e4de761 JB |
2095 | else |
2096 | buildstr[0] = '\0'; | |
2097 | ||
2098 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n", | |
2099 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2100 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2101 | IWL_UCODE_API(priv->ucode_ver), | |
2102 | IWL_UCODE_SERIAL(priv->ucode_ver), | |
2103 | buildstr); | |
a0987a8d | 2104 | |
5ebeb5a6 RC |
2105 | snprintf(priv->hw->wiphy->fw_version, |
2106 | sizeof(priv->hw->wiphy->fw_version), | |
3e4de761 | 2107 | "%u.%u.%u.%u%s", |
5ebeb5a6 RC |
2108 | IWL_UCODE_MAJOR(priv->ucode_ver), |
2109 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2110 | IWL_UCODE_API(priv->ucode_ver), | |
3e4de761 JB |
2111 | IWL_UCODE_SERIAL(priv->ucode_ver), |
2112 | buildstr); | |
b481de9c | 2113 | |
b08dfd04 JB |
2114 | /* |
2115 | * For any of the failures below (before allocating pci memory) | |
2116 | * we will try to load a version with a smaller API -- maybe the | |
2117 | * user just got a corrupted version of the latest API. | |
2118 | */ | |
2119 | ||
0e9a44dc JB |
2120 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
2121 | priv->ucode_ver); | |
2122 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n", | |
2123 | pieces.inst_size); | |
2124 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n", | |
2125 | pieces.data_size); | |
2126 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n", | |
2127 | pieces.init_size); | |
2128 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", | |
2129 | pieces.init_data_size); | |
2130 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n", | |
2131 | pieces.boot_size); | |
b481de9c ZY |
2132 | |
2133 | /* Verify that uCode images will fit in card's SRAM */ | |
0e9a44dc JB |
2134 | if (pieces.inst_size > priv->hw_params.max_inst_size) { |
2135 | IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n", | |
2136 | pieces.inst_size); | |
b08dfd04 | 2137 | goto try_again; |
b481de9c ZY |
2138 | } |
2139 | ||
0e9a44dc JB |
2140 | if (pieces.data_size > priv->hw_params.max_data_size) { |
2141 | IWL_ERR(priv, "uCode data len %Zd too large to fit in\n", | |
2142 | pieces.data_size); | |
b08dfd04 | 2143 | goto try_again; |
b481de9c | 2144 | } |
0e9a44dc JB |
2145 | |
2146 | if (pieces.init_size > priv->hw_params.max_inst_size) { | |
2147 | IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n", | |
2148 | pieces.init_size); | |
b08dfd04 | 2149 | goto try_again; |
b481de9c | 2150 | } |
0e9a44dc JB |
2151 | |
2152 | if (pieces.init_data_size > priv->hw_params.max_data_size) { | |
2153 | IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n", | |
2154 | pieces.init_data_size); | |
b08dfd04 | 2155 | goto try_again; |
b481de9c | 2156 | } |
0e9a44dc JB |
2157 | |
2158 | if (pieces.boot_size > priv->hw_params.max_bsm_size) { | |
2159 | IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n", | |
2160 | pieces.boot_size); | |
b08dfd04 | 2161 | goto try_again; |
b481de9c ZY |
2162 | } |
2163 | ||
2164 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2165 | ||
2166 | /* Runtime instructions and 2 copies of data: | |
2167 | * 1) unmodified from disk | |
2168 | * 2) backup cache for save/restore during power-downs */ | |
0e9a44dc | 2169 | priv->ucode_code.len = pieces.inst_size; |
98c92211 | 2170 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c | 2171 | |
0e9a44dc | 2172 | priv->ucode_data.len = pieces.data_size; |
98c92211 | 2173 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c | 2174 | |
0e9a44dc | 2175 | priv->ucode_data_backup.len = pieces.data_size; |
98c92211 | 2176 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2177 | |
1f304e4e ZY |
2178 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2179 | !priv->ucode_data_backup.v_addr) | |
2180 | goto err_pci_alloc; | |
2181 | ||
b481de9c | 2182 | /* Initialization instructions and data */ |
0e9a44dc JB |
2183 | if (pieces.init_size && pieces.init_data_size) { |
2184 | priv->ucode_init.len = pieces.init_size; | |
98c92211 | 2185 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 | 2186 | |
0e9a44dc | 2187 | priv->ucode_init_data.len = pieces.init_data_size; |
98c92211 | 2188 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2189 | |
2190 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2191 | goto err_pci_alloc; | |
2192 | } | |
b481de9c ZY |
2193 | |
2194 | /* Bootstrap (instructions only, no data) */ | |
0e9a44dc JB |
2195 | if (pieces.boot_size) { |
2196 | priv->ucode_boot.len = pieces.boot_size; | |
98c92211 | 2197 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2198 | |
90e759d1 TW |
2199 | if (!priv->ucode_boot.v_addr) |
2200 | goto err_pci_alloc; | |
2201 | } | |
b481de9c | 2202 | |
b2e640d4 JB |
2203 | /* Now that we can no longer fail, copy information */ |
2204 | ||
2205 | /* | |
2206 | * The (size - 16) / 12 formula is based on the information recorded | |
2207 | * for each event, which is of mode 1 (including timestamp) for all | |
2208 | * new microcodes that include this information. | |
2209 | */ | |
2210 | priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr; | |
2211 | if (pieces.init_evtlog_size) | |
2212 | priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12; | |
2213 | else | |
2214 | priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size; | |
2215 | priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr; | |
2216 | priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr; | |
2217 | if (pieces.inst_evtlog_size) | |
2218 | priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12; | |
2219 | else | |
2220 | priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size; | |
2221 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; | |
2222 | ||
b481de9c ZY |
2223 | /* Copy images into buffers for card's bus-master reads ... */ |
2224 | ||
2225 | /* Runtime instructions (first block of data in file) */ | |
0e9a44dc JB |
2226 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", |
2227 | pieces.inst_size); | |
2228 | memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size); | |
cc0f555d | 2229 | |
e1623446 | 2230 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2231 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2232 | ||
0e9a44dc JB |
2233 | /* |
2234 | * Runtime data | |
2235 | * NOTE: Copy into backup buffer will be done in iwl_up() | |
2236 | */ | |
2237 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", | |
2238 | pieces.data_size); | |
2239 | memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size); | |
2240 | memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size); | |
2241 | ||
2242 | /* Initialization instructions */ | |
2243 | if (pieces.init_size) { | |
e1623446 | 2244 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
0e9a44dc JB |
2245 | pieces.init_size); |
2246 | memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size); | |
b481de9c ZY |
2247 | } |
2248 | ||
0e9a44dc JB |
2249 | /* Initialization data */ |
2250 | if (pieces.init_data_size) { | |
e1623446 | 2251 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
0e9a44dc JB |
2252 | pieces.init_data_size); |
2253 | memcpy(priv->ucode_init_data.v_addr, pieces.init_data, | |
2254 | pieces.init_data_size); | |
b481de9c ZY |
2255 | } |
2256 | ||
0e9a44dc JB |
2257 | /* Bootstrap instructions */ |
2258 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", | |
2259 | pieces.boot_size); | |
2260 | memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size); | |
b481de9c | 2261 | |
6a822d06 WYG |
2262 | /* |
2263 | * figure out the offset of chain noise reset and gain commands | |
2264 | * base on the size of standard phy calibration commands table size | |
2265 | */ | |
2266 | if (ucode_capa.standard_phy_calibration_size > | |
2267 | IWL_MAX_PHY_CALIBRATE_TBL_SIZE) | |
2268 | ucode_capa.standard_phy_calibration_size = | |
2269 | IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE; | |
2270 | ||
2271 | priv->_agn.phy_calib_chain_noise_reset_cmd = | |
2272 | ucode_capa.standard_phy_calibration_size; | |
2273 | priv->_agn.phy_calib_chain_noise_gain_cmd = | |
2274 | ucode_capa.standard_phy_calibration_size + 1; | |
2275 | ||
b08dfd04 JB |
2276 | /************************************************** |
2277 | * This is still part of probe() in a sense... | |
2278 | * | |
2279 | * 9. Setup and register with mac80211 and debugfs | |
2280 | **************************************************/ | |
dd7a2509 | 2281 | err = iwl_mac_setup_register(priv, &ucode_capa); |
b08dfd04 JB |
2282 | if (err) |
2283 | goto out_unbind; | |
2284 | ||
2285 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
2286 | if (err) | |
2287 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
2288 | ||
7d47618a EG |
2289 | err = sysfs_create_group(&priv->pci_dev->dev.kobj, |
2290 | &iwl_attribute_group); | |
2291 | if (err) { | |
2292 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); | |
2293 | goto out_unbind; | |
2294 | } | |
2295 | ||
b481de9c ZY |
2296 | /* We have our copies now, allow OS release its copies */ |
2297 | release_firmware(ucode_raw); | |
a15707d8 | 2298 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 JB |
2299 | return; |
2300 | ||
2301 | try_again: | |
2302 | /* try next, if any */ | |
2303 | if (iwl_request_firmware(priv, false)) | |
2304 | goto out_unbind; | |
2305 | release_firmware(ucode_raw); | |
2306 | return; | |
b481de9c ZY |
2307 | |
2308 | err_pci_alloc: | |
15b1687c | 2309 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
5b9f8cd3 | 2310 | iwl_dealloc_ucode_pci(priv); |
b08dfd04 | 2311 | out_unbind: |
a15707d8 | 2312 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 | 2313 | device_release_driver(&priv->pci_dev->dev); |
b481de9c | 2314 | release_firmware(ucode_raw); |
b481de9c ZY |
2315 | } |
2316 | ||
b7a79404 RC |
2317 | static const char *desc_lookup_text[] = { |
2318 | "OK", | |
2319 | "FAIL", | |
2320 | "BAD_PARAM", | |
2321 | "BAD_CHECKSUM", | |
2322 | "NMI_INTERRUPT_WDG", | |
2323 | "SYSASSERT", | |
2324 | "FATAL_ERROR", | |
2325 | "BAD_COMMAND", | |
2326 | "HW_ERROR_TUNE_LOCK", | |
2327 | "HW_ERROR_TEMPERATURE", | |
2328 | "ILLEGAL_CHAN_FREQ", | |
2329 | "VCC_NOT_STABLE", | |
2330 | "FH_ERROR", | |
2331 | "NMI_INTERRUPT_HOST", | |
2332 | "NMI_INTERRUPT_ACTION_PT", | |
2333 | "NMI_INTERRUPT_UNKNOWN", | |
2334 | "UCODE_VERSION_MISMATCH", | |
2335 | "HW_ERROR_ABS_LOCK", | |
2336 | "HW_ERROR_CAL_LOCK_FAIL", | |
2337 | "NMI_INTERRUPT_INST_ACTION_PT", | |
2338 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
2339 | "NMI_TRM_HW_ER", | |
2340 | "NMI_INTERRUPT_TRM", | |
2341 | "NMI_INTERRUPT_BREAK_POINT" | |
2342 | "DEBUG_0", | |
2343 | "DEBUG_1", | |
2344 | "DEBUG_2", | |
2345 | "DEBUG_3", | |
b7a79404 RC |
2346 | }; |
2347 | ||
4b58645c JS |
2348 | static struct { char *name; u8 num; } advanced_lookup[] = { |
2349 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
2350 | { "SYSASSERT", 0x35 }, | |
2351 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
2352 | { "BAD_COMMAND", 0x38 }, | |
2353 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
2354 | { "FATAL_ERROR", 0x3D }, | |
2355 | { "NMI_TRM_HW_ERR", 0x46 }, | |
2356 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
2357 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
2358 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
2359 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
2360 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
2361 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
2362 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
2363 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
2364 | { "ADVANCED_SYSASSERT", 0 }, | |
2365 | }; | |
2366 | ||
2367 | static const char *desc_lookup(u32 num) | |
b7a79404 | 2368 | { |
4b58645c JS |
2369 | int i; |
2370 | int max = ARRAY_SIZE(desc_lookup_text); | |
b7a79404 | 2371 | |
4b58645c JS |
2372 | if (num < max) |
2373 | return desc_lookup_text[num]; | |
b7a79404 | 2374 | |
4b58645c JS |
2375 | max = ARRAY_SIZE(advanced_lookup) - 1; |
2376 | for (i = 0; i < max; i++) { | |
2377 | if (advanced_lookup[i].num == num) | |
2378 | break;; | |
2379 | } | |
2380 | return advanced_lookup[i].name; | |
b7a79404 RC |
2381 | } |
2382 | ||
2383 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
2384 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
2385 | ||
2386 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
2387 | { | |
2388 | u32 data2, line; | |
2389 | u32 desc, time, count, base, data1; | |
2390 | u32 blink1, blink2, ilink1, ilink2; | |
461ef382 | 2391 | u32 pc, hcmd; |
b7a79404 | 2392 | |
b2e640d4 | 2393 | if (priv->ucode_type == UCODE_INIT) { |
b7a79404 | 2394 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); |
b2e640d4 JB |
2395 | if (!base) |
2396 | base = priv->_agn.init_errlog_ptr; | |
2397 | } else { | |
b7a79404 | 2398 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); |
b2e640d4 JB |
2399 | if (!base) |
2400 | base = priv->_agn.inst_errlog_ptr; | |
2401 | } | |
b7a79404 RC |
2402 | |
2403 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2404 | IWL_ERR(priv, |
2405 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
2406 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
b7a79404 RC |
2407 | return; |
2408 | } | |
2409 | ||
2410 | count = iwl_read_targ_mem(priv, base); | |
2411 | ||
2412 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
2413 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
2414 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
2415 | priv->status, count); | |
2416 | } | |
2417 | ||
2418 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
461ef382 | 2419 | pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32)); |
b7a79404 RC |
2420 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); |
2421 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
2422 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
2423 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
2424 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
2425 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
2426 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
2427 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
461ef382 | 2428 | hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32)); |
b7a79404 | 2429 | |
be1a71a1 JB |
2430 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
2431 | blink1, blink2, ilink1, ilink2); | |
2432 | ||
87563715 | 2433 | IWL_ERR(priv, "Desc Time " |
b7a79404 | 2434 | "data1 data2 line\n"); |
87563715 | 2435 | IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", |
b7a79404 | 2436 | desc_lookup(desc), desc, time, data1, data2, line); |
461ef382 WYG |
2437 | IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n"); |
2438 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", | |
2439 | pc, blink1, blink2, ilink1, ilink2, hcmd); | |
b7a79404 RC |
2440 | } |
2441 | ||
2442 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
2443 | ||
2444 | /** | |
2445 | * iwl_print_event_log - Dump error event log to syslog | |
2446 | * | |
2447 | */ | |
b03d7d0f WYG |
2448 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
2449 | u32 num_events, u32 mode, | |
2450 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
2451 | { |
2452 | u32 i; | |
2453 | u32 base; /* SRAM byte address of event log header */ | |
2454 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
2455 | u32 ptr; /* SRAM byte address of log data */ | |
2456 | u32 ev, time, data; /* event log data */ | |
e5854471 | 2457 | unsigned long reg_flags; |
b7a79404 RC |
2458 | |
2459 | if (num_events == 0) | |
b03d7d0f | 2460 | return pos; |
b2e640d4 JB |
2461 | |
2462 | if (priv->ucode_type == UCODE_INIT) { | |
b7a79404 | 2463 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
b2e640d4 JB |
2464 | if (!base) |
2465 | base = priv->_agn.init_evtlog_ptr; | |
2466 | } else { | |
b7a79404 | 2467 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
b2e640d4 JB |
2468 | if (!base) |
2469 | base = priv->_agn.inst_evtlog_ptr; | |
2470 | } | |
b7a79404 RC |
2471 | |
2472 | if (mode == 0) | |
2473 | event_size = 2 * sizeof(u32); | |
2474 | else | |
2475 | event_size = 3 * sizeof(u32); | |
2476 | ||
2477 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
2478 | ||
e5854471 BC |
2479 | /* Make sure device is powered up for SRAM reads */ |
2480 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
2481 | iwl_grab_nic_access(priv); | |
2482 | ||
2483 | /* Set starting address; reads will auto-increment */ | |
2484 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
2485 | rmb(); | |
2486 | ||
b7a79404 RC |
2487 | /* "time" is actually "data" for mode 0 (no timestamp). |
2488 | * place event id # at far right for easier visual parsing. */ | |
2489 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
2490 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
2491 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
2492 | if (mode == 0) { |
2493 | /* data, ev */ | |
b03d7d0f WYG |
2494 | if (bufsz) { |
2495 | pos += scnprintf(*buf + pos, bufsz - pos, | |
2496 | "EVT_LOG:0x%08x:%04u\n", | |
2497 | time, ev); | |
2498 | } else { | |
2499 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
2500 | time, ev); | |
2501 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
2502 | time, ev); | |
2503 | } | |
b7a79404 | 2504 | } else { |
e5854471 | 2505 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
2506 | if (bufsz) { |
2507 | pos += scnprintf(*buf + pos, bufsz - pos, | |
2508 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
2509 | time, data, ev); | |
2510 | } else { | |
2511 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 2512 | time, data, ev); |
b03d7d0f WYG |
2513 | trace_iwlwifi_dev_ucode_event(priv, time, |
2514 | data, ev); | |
2515 | } | |
b7a79404 RC |
2516 | } |
2517 | } | |
e5854471 BC |
2518 | |
2519 | /* Allow device to power down */ | |
2520 | iwl_release_nic_access(priv); | |
2521 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 2522 | return pos; |
b7a79404 RC |
2523 | } |
2524 | ||
c341ddb2 WYG |
2525 | /** |
2526 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
2527 | */ | |
b03d7d0f WYG |
2528 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
2529 | u32 num_wraps, u32 next_entry, | |
2530 | u32 size, u32 mode, | |
2531 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
2532 | { |
2533 | /* | |
2534 | * display the newest DEFAULT_LOG_ENTRIES entries | |
2535 | * i.e the entries just before the next ont that uCode would fill. | |
2536 | */ | |
2537 | if (num_wraps) { | |
2538 | if (next_entry < size) { | |
b03d7d0f WYG |
2539 | pos = iwl_print_event_log(priv, |
2540 | capacity - (size - next_entry), | |
2541 | size - next_entry, mode, | |
2542 | pos, buf, bufsz); | |
2543 | pos = iwl_print_event_log(priv, 0, | |
2544 | next_entry, mode, | |
2545 | pos, buf, bufsz); | |
c341ddb2 | 2546 | } else |
b03d7d0f WYG |
2547 | pos = iwl_print_event_log(priv, next_entry - size, |
2548 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 2549 | } else { |
b03d7d0f WYG |
2550 | if (next_entry < size) { |
2551 | pos = iwl_print_event_log(priv, 0, next_entry, | |
2552 | mode, pos, buf, bufsz); | |
2553 | } else { | |
2554 | pos = iwl_print_event_log(priv, next_entry - size, | |
2555 | size, mode, pos, buf, bufsz); | |
2556 | } | |
c341ddb2 | 2557 | } |
b03d7d0f | 2558 | return pos; |
c341ddb2 WYG |
2559 | } |
2560 | ||
c341ddb2 WYG |
2561 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
2562 | ||
b03d7d0f WYG |
2563 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
2564 | char **buf, bool display) | |
b7a79404 RC |
2565 | { |
2566 | u32 base; /* SRAM byte address of event log header */ | |
2567 | u32 capacity; /* event log capacity in # entries */ | |
2568 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
2569 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
2570 | u32 next_entry; /* index of next entry to be written by uCode */ | |
2571 | u32 size; /* # entries that we'll print */ | |
b2e640d4 | 2572 | u32 logsize; |
b03d7d0f WYG |
2573 | int pos = 0; |
2574 | size_t bufsz = 0; | |
b7a79404 | 2575 | |
b2e640d4 | 2576 | if (priv->ucode_type == UCODE_INIT) { |
b7a79404 | 2577 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
b2e640d4 JB |
2578 | logsize = priv->_agn.init_evtlog_size; |
2579 | if (!base) | |
2580 | base = priv->_agn.init_evtlog_ptr; | |
2581 | } else { | |
b7a79404 | 2582 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
b2e640d4 JB |
2583 | logsize = priv->_agn.inst_evtlog_size; |
2584 | if (!base) | |
2585 | base = priv->_agn.inst_evtlog_ptr; | |
2586 | } | |
b7a79404 RC |
2587 | |
2588 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2589 | IWL_ERR(priv, |
2590 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
2591 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
937c397e | 2592 | return -EINVAL; |
b7a79404 RC |
2593 | } |
2594 | ||
2595 | /* event log header */ | |
2596 | capacity = iwl_read_targ_mem(priv, base); | |
2597 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
2598 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
2599 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
2600 | ||
b2e640d4 | 2601 | if (capacity > logsize) { |
84c40692 | 2602 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
b2e640d4 JB |
2603 | capacity, logsize); |
2604 | capacity = logsize; | |
84c40692 BC |
2605 | } |
2606 | ||
b2e640d4 | 2607 | if (next_entry > logsize) { |
84c40692 | 2608 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
b2e640d4 JB |
2609 | next_entry, logsize); |
2610 | next_entry = logsize; | |
84c40692 BC |
2611 | } |
2612 | ||
b7a79404 RC |
2613 | size = num_wraps ? capacity : next_entry; |
2614 | ||
2615 | /* bail out if nothing in log */ | |
2616 | if (size == 0) { | |
2617 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 2618 | return pos; |
b7a79404 RC |
2619 | } |
2620 | ||
f37837c9 WYG |
2621 | /* enable/disable bt channel announcement */ |
2622 | priv->bt_ch_announce = iwlagn_bt_ch_announce; | |
2623 | ||
c341ddb2 | 2624 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 2625 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
2626 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
2627 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2628 | #else | |
2629 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
2630 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2631 | #endif | |
2632 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
2633 | size); | |
b7a79404 | 2634 | |
c341ddb2 | 2635 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
2636 | if (display) { |
2637 | if (full_log) | |
2638 | bufsz = capacity * 48; | |
2639 | else | |
2640 | bufsz = size * 48; | |
2641 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
2642 | if (!*buf) | |
937c397e | 2643 | return -ENOMEM; |
b03d7d0f | 2644 | } |
c341ddb2 WYG |
2645 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
2646 | /* | |
2647 | * if uCode has wrapped back to top of log, | |
2648 | * start at the oldest entry, | |
2649 | * i.e the next one that uCode would fill. | |
2650 | */ | |
2651 | if (num_wraps) | |
b03d7d0f WYG |
2652 | pos = iwl_print_event_log(priv, next_entry, |
2653 | capacity - next_entry, mode, | |
2654 | pos, buf, bufsz); | |
c341ddb2 | 2655 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
2656 | pos = iwl_print_event_log(priv, 0, |
2657 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 2658 | } else |
b03d7d0f WYG |
2659 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2660 | next_entry, size, mode, | |
2661 | pos, buf, bufsz); | |
c341ddb2 | 2662 | #else |
b03d7d0f WYG |
2663 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2664 | next_entry, size, mode, | |
2665 | pos, buf, bufsz); | |
b7a79404 | 2666 | #endif |
b03d7d0f | 2667 | return pos; |
c341ddb2 | 2668 | } |
b7a79404 | 2669 | |
0975cc8f WYG |
2670 | static void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
2671 | { | |
2672 | struct iwl_ct_kill_config cmd; | |
2673 | struct iwl_ct_kill_throttling_config adv_cmd; | |
2674 | unsigned long flags; | |
2675 | int ret = 0; | |
2676 | ||
2677 | spin_lock_irqsave(&priv->lock, flags); | |
2678 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
2679 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | |
2680 | spin_unlock_irqrestore(&priv->lock, flags); | |
2681 | priv->thermal_throttle.ct_kill_toggle = false; | |
2682 | ||
2683 | if (priv->cfg->support_ct_kill_exit) { | |
2684 | adv_cmd.critical_temperature_enter = | |
2685 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2686 | adv_cmd.critical_temperature_exit = | |
2687 | cpu_to_le32(priv->hw_params.ct_kill_exit_threshold); | |
2688 | ||
2689 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2690 | sizeof(adv_cmd), &adv_cmd); | |
2691 | if (ret) | |
2692 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2693 | else | |
2694 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2695 | "succeeded, " | |
2696 | "critical temperature enter is %d," | |
2697 | "exit is %d\n", | |
2698 | priv->hw_params.ct_kill_threshold, | |
2699 | priv->hw_params.ct_kill_exit_threshold); | |
2700 | } else { | |
2701 | cmd.critical_temperature_R = | |
2702 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2703 | ||
2704 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2705 | sizeof(cmd), &cmd); | |
2706 | if (ret) | |
2707 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2708 | else | |
2709 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2710 | "succeeded, " | |
2711 | "critical temperature is %d\n", | |
2712 | priv->hw_params.ct_kill_threshold); | |
2713 | } | |
2714 | } | |
2715 | ||
b481de9c | 2716 | /** |
4a4a9e81 | 2717 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2718 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 2719 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 2720 | */ |
4a4a9e81 | 2721 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 2722 | { |
57aab75a | 2723 | int ret = 0; |
246ed355 | 2724 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 2725 | |
e1623446 | 2726 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2727 | |
2728 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2729 | /* We had an error bringing up the hardware, so take it | |
2730 | * all the way back down so we can try again */ | |
e1623446 | 2731 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2732 | goto restart; |
2733 | } | |
2734 | ||
2735 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2736 | * This is a paranoid check, because we would not have gotten the | |
2737 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 2738 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
2739 | /* Runtime instruction load was bad; |
2740 | * take it all the way back down so we can try again */ | |
e1623446 | 2741 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2742 | goto restart; |
2743 | } | |
2744 | ||
57aab75a TW |
2745 | ret = priv->cfg->ops->lib->alive_notify(priv); |
2746 | if (ret) { | |
39aadf8c WT |
2747 | IWL_WARN(priv, |
2748 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
2749 | goto restart; |
2750 | } | |
2751 | ||
5b9f8cd3 | 2752 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
2753 | set_bit(STATUS_ALIVE, &priv->status); |
2754 | ||
b74e31a9 WYG |
2755 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
2756 | /* Enable timer to monitor the driver queues */ | |
2757 | mod_timer(&priv->monitor_recover, | |
2758 | jiffies + | |
2759 | msecs_to_jiffies(priv->cfg->monitor_recover_period)); | |
2760 | } | |
2761 | ||
fee1247a | 2762 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2763 | return; |
2764 | ||
36d6825b | 2765 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2766 | |
470ab2dd | 2767 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2768 | |
2f748dec WYG |
2769 | /* Configure Tx antenna selection based on H/W config */ |
2770 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2771 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2772 | ||
246ed355 | 2773 | if (iwl_is_associated_ctx(ctx)) { |
c1adf9fb | 2774 | struct iwl_rxon_cmd *active_rxon = |
246ed355 | 2775 | (struct iwl_rxon_cmd *)&ctx->active; |
019fb97d | 2776 | /* apply any changes in staging */ |
246ed355 | 2777 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2778 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2779 | } else { | |
2780 | /* Initialize our rx_config data */ | |
1dda6d28 | 2781 | iwl_connection_init_rx_config(priv, NULL); |
45823531 AK |
2782 | |
2783 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 | 2784 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); |
b481de9c ZY |
2785 | } |
2786 | ||
aeb4a2ee WYG |
2787 | if (!priv->cfg->advanced_bt_coexist) { |
2788 | /* Configure Bluetooth device coexistence support */ | |
2789 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
2790 | } | |
b481de9c | 2791 | |
4a4a9e81 TW |
2792 | iwl_reset_run_time_calib(priv); |
2793 | ||
b481de9c | 2794 | /* Configure the adapter for unassociated operation */ |
246ed355 | 2795 | iwlcore_commit_rxon(priv, ctx); |
b481de9c ZY |
2796 | |
2797 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2798 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2799 | |
e932a609 | 2800 | iwl_leds_init(priv); |
fe00b5a5 | 2801 | |
e1623446 | 2802 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2803 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2804 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2805 | |
e312c24c | 2806 | iwl_power_update_mode(priv, true); |
7e246191 RC |
2807 | IWL_DEBUG_INFO(priv, "Updated power mode\n"); |
2808 | ||
c46fbefa | 2809 | |
b481de9c ZY |
2810 | return; |
2811 | ||
2812 | restart: | |
2813 | queue_work(priv->workqueue, &priv->restart); | |
2814 | } | |
2815 | ||
4e39317d | 2816 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2817 | |
5b9f8cd3 | 2818 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2819 | { |
2820 | unsigned long flags; | |
2821 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2822 | |
e1623446 | 2823 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2824 | |
b481de9c ZY |
2825 | if (!exit_pending) |
2826 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2827 | ||
b62177a0 SG |
2828 | /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set |
2829 | * to prevent rearm timer */ | |
2830 | if (priv->cfg->ops->lib->recover_from_tx_stall) | |
2831 | del_timer_sync(&priv->monitor_recover); | |
2832 | ||
dcef732c | 2833 | iwl_clear_ucode_stations(priv, NULL); |
a194e324 | 2834 | iwl_dealloc_bcast_stations(priv); |
db125c78 | 2835 | iwl_clear_driver_stations(priv); |
b481de9c | 2836 | |
a1174138 | 2837 | /* reset BT coex data */ |
da5dbb97 | 2838 | priv->bt_status = 0; |
a4b96cc4 | 2839 | priv->bt_traffic_load = priv->cfg->bt_init_traffic_load; |
a1174138 | 2840 | priv->bt_sco_active = false; |
bee008b7 WYG |
2841 | priv->bt_full_concurrent = false; |
2842 | priv->bt_ci_compliance = 0; | |
a1174138 | 2843 | |
b481de9c ZY |
2844 | /* Unblock any waiting calls */ |
2845 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2846 | ||
b481de9c ZY |
2847 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2848 | * exiting the module */ | |
2849 | if (!exit_pending) | |
2850 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2851 | ||
2852 | /* stop and reset the on-board processor */ | |
3395f6e9 | 2853 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2854 | |
2855 | /* tell the device to stop sending interrupts */ | |
0359facc | 2856 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2857 | iwl_disable_interrupts(priv); |
0359facc MA |
2858 | spin_unlock_irqrestore(&priv->lock, flags); |
2859 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2860 | |
2861 | if (priv->mac80211_registered) | |
2862 | ieee80211_stop_queues(priv->hw); | |
2863 | ||
5b9f8cd3 | 2864 | /* If we have not previously called iwl_init() then |
a60e77e5 | 2865 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 2866 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2867 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2868 | STATUS_RF_KILL_HW | | |
9788864e RC |
2869 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2870 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
2871 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2872 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2873 | goto exit; |
2874 | } | |
2875 | ||
6da3a13e | 2876 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2877 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2878 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2879 | STATUS_RF_KILL_HW | | |
9788864e RC |
2880 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2881 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2882 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2883 | STATUS_FW_ERROR | |
2884 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2885 | STATUS_EXIT_PENDING; | |
b481de9c | 2886 | |
ef850d7c MA |
2887 | /* device going down, Stop using ICT table */ |
2888 | iwl_disable_ict(priv); | |
b481de9c | 2889 | |
74bcdb33 | 2890 | iwlagn_txq_ctx_stop(priv); |
54b81550 | 2891 | iwlagn_rxq_stop(priv); |
b481de9c | 2892 | |
309e731a BC |
2893 | /* Power-down device's busmaster DMA clocks */ |
2894 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2895 | udelay(5); |
2896 | ||
309e731a BC |
2897 | /* Make sure (redundant) we've released our request to stay awake */ |
2898 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
2899 | ||
4d2ccdb9 BC |
2900 | /* Stop the device, and put it in low power state */ |
2901 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
2902 | ||
b481de9c | 2903 | exit: |
885ba202 | 2904 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2905 | |
2906 | if (priv->ibss_beacon) | |
2907 | dev_kfree_skb(priv->ibss_beacon); | |
2908 | priv->ibss_beacon = NULL; | |
2909 | ||
2910 | /* clear out any free frames */ | |
fcab423d | 2911 | iwl_clear_free_frames(priv); |
b481de9c ZY |
2912 | } |
2913 | ||
5b9f8cd3 | 2914 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2915 | { |
2916 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2917 | __iwl_down(priv); |
b481de9c | 2918 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2919 | |
4e39317d | 2920 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2921 | } |
2922 | ||
086ed117 MA |
2923 | #define HW_READY_TIMEOUT (50) |
2924 | ||
2925 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
2926 | { | |
2927 | int ret = 0; | |
2928 | ||
2929 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2930 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2931 | ||
2932 | /* See if we got it */ | |
2933 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2934 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2935 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2936 | HW_READY_TIMEOUT); | |
2937 | if (ret != -ETIMEDOUT) | |
2938 | priv->hw_ready = true; | |
2939 | else | |
2940 | priv->hw_ready = false; | |
2941 | ||
2942 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
2943 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
2944 | return ret; | |
2945 | } | |
2946 | ||
2947 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
2948 | { | |
2949 | int ret = 0; | |
2950 | ||
91dd6c27 | 2951 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n"); |
086ed117 | 2952 | |
3354a0f6 MA |
2953 | ret = iwl_set_hw_ready(priv); |
2954 | if (priv->hw_ready) | |
2955 | return ret; | |
2956 | ||
2957 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2958 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2959 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2960 | ||
2961 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2962 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2963 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2964 | ||
3354a0f6 | 2965 | /* HW should be ready by now, check again. */ |
086ed117 MA |
2966 | if (ret != -ETIMEDOUT) |
2967 | iwl_set_hw_ready(priv); | |
2968 | ||
2969 | return ret; | |
2970 | } | |
2971 | ||
b481de9c ZY |
2972 | #define MAX_HW_RESTARTS 5 |
2973 | ||
5b9f8cd3 | 2974 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2975 | { |
a194e324 | 2976 | struct iwl_rxon_context *ctx; |
57aab75a TW |
2977 | int i; |
2978 | int ret; | |
b481de9c ZY |
2979 | |
2980 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2981 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2982 | return -EIO; |
2983 | } | |
2984 | ||
e903fbd4 | 2985 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2986 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
2987 | return -EIO; |
2988 | } | |
2989 | ||
a194e324 JB |
2990 | for_each_context(priv, ctx) { |
2991 | ret = iwl_alloc_bcast_station(priv, ctx, true); | |
2992 | if (ret) { | |
2993 | iwl_dealloc_bcast_stations(priv); | |
2994 | return ret; | |
2995 | } | |
2996 | } | |
2c810ccd | 2997 | |
086ed117 MA |
2998 | iwl_prepare_card_hw(priv); |
2999 | ||
3000 | if (!priv->hw_ready) { | |
3001 | IWL_WARN(priv, "Exit HW not ready\n"); | |
3002 | return -EIO; | |
3003 | } | |
3004 | ||
e655b9f0 | 3005 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 3006 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 3007 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 3008 | else |
e655b9f0 | 3009 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 3010 | |
c1842d61 | 3011 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
3012 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
3013 | ||
5b9f8cd3 | 3014 | iwl_enable_interrupts(priv); |
a60e77e5 | 3015 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 3016 | return 0; |
b481de9c ZY |
3017 | } |
3018 | ||
3395f6e9 | 3019 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 3020 | |
13bb9483 | 3021 | /* must be initialised before iwl_hw_nic_init */ |
751ca305 JB |
3022 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
3023 | priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM; | |
3024 | else | |
3025 | priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM; | |
13bb9483 | 3026 | |
74bcdb33 | 3027 | ret = iwlagn_hw_nic_init(priv); |
57aab75a | 3028 | if (ret) { |
15b1687c | 3029 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 3030 | return ret; |
b481de9c ZY |
3031 | } |
3032 | ||
3033 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
3034 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
3035 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
3036 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3037 | ||
3038 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 3039 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 3040 | iwl_enable_interrupts(priv); |
b481de9c ZY |
3041 | |
3042 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
3043 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
3044 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
3045 | |
3046 | /* Copy original ucode data image from disk into backup cache. | |
3047 | * This will be used to initialize the on-board processor's | |
3048 | * data SRAM for a clean start when the runtime program first loads. */ | |
3049 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 3050 | priv->ucode_data.len); |
b481de9c | 3051 | |
b481de9c ZY |
3052 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
3053 | ||
b481de9c ZY |
3054 | /* load bootstrap state machine, |
3055 | * load bootstrap program into processor's memory, | |
3056 | * prepare to load the "initialize" uCode */ | |
57aab75a | 3057 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 3058 | |
57aab75a | 3059 | if (ret) { |
15b1687c WT |
3060 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
3061 | ret); | |
b481de9c ZY |
3062 | continue; |
3063 | } | |
3064 | ||
3065 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 3066 | iwl_nic_start(priv); |
b481de9c | 3067 | |
e1623446 | 3068 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
3069 | |
3070 | return 0; | |
3071 | } | |
3072 | ||
3073 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 3074 | __iwl_down(priv); |
64e72c3e | 3075 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
3076 | |
3077 | /* tried to restart and config the device for as long as our | |
3078 | * patience could withstand */ | |
15b1687c | 3079 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
3080 | return -EIO; |
3081 | } | |
3082 | ||
3083 | ||
3084 | /***************************************************************************** | |
3085 | * | |
3086 | * Workqueue callbacks | |
3087 | * | |
3088 | *****************************************************************************/ | |
3089 | ||
4a4a9e81 | 3090 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 3091 | { |
c79dd5b5 TW |
3092 | struct iwl_priv *priv = |
3093 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
3094 | |
3095 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3096 | return; | |
3097 | ||
3098 | mutex_lock(&priv->mutex); | |
f3ccc08c | 3099 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
3100 | mutex_unlock(&priv->mutex); |
3101 | } | |
3102 | ||
4a4a9e81 | 3103 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 3104 | { |
c79dd5b5 TW |
3105 | struct iwl_priv *priv = |
3106 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
3107 | |
3108 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3109 | return; | |
3110 | ||
258c44a0 MA |
3111 | /* enable dram interrupt */ |
3112 | iwl_reset_ict(priv); | |
3113 | ||
b481de9c | 3114 | mutex_lock(&priv->mutex); |
4a4a9e81 | 3115 | iwl_alive_start(priv); |
b481de9c ZY |
3116 | mutex_unlock(&priv->mutex); |
3117 | } | |
3118 | ||
16e727e8 EG |
3119 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
3120 | { | |
3121 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
3122 | run_time_calib_work); | |
3123 | ||
3124 | mutex_lock(&priv->mutex); | |
3125 | ||
3126 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
3127 | test_bit(STATUS_SCANNING, &priv->status)) { | |
3128 | mutex_unlock(&priv->mutex); | |
3129 | return; | |
3130 | } | |
3131 | ||
3132 | if (priv->start_calib) { | |
7980fba5 WYG |
3133 | if (priv->cfg->bt_statistics) { |
3134 | iwl_chain_noise_calibration(priv, | |
3135 | (void *)&priv->_agn.statistics_bt); | |
3136 | iwl_sensitivity_calibration(priv, | |
3137 | (void *)&priv->_agn.statistics_bt); | |
3138 | } else { | |
3139 | iwl_chain_noise_calibration(priv, | |
3140 | (void *)&priv->_agn.statistics); | |
3141 | iwl_sensitivity_calibration(priv, | |
3142 | (void *)&priv->_agn.statistics); | |
3143 | } | |
16e727e8 EG |
3144 | } |
3145 | ||
3146 | mutex_unlock(&priv->mutex); | |
16e727e8 EG |
3147 | } |
3148 | ||
5b9f8cd3 | 3149 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 3150 | { |
c79dd5b5 | 3151 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
3152 | |
3153 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3154 | return; | |
3155 | ||
19cc1087 | 3156 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
bee008b7 WYG |
3157 | bool bt_sco, bt_full_concurrent; |
3158 | u8 bt_ci_compliance; | |
511b082d | 3159 | u8 bt_load; |
da5dbb97 | 3160 | u8 bt_status; |
511b082d | 3161 | |
19cc1087 JB |
3162 | mutex_lock(&priv->mutex); |
3163 | priv->vif = NULL; | |
3164 | priv->is_open = 0; | |
511b082d JB |
3165 | |
3166 | /* | |
3167 | * __iwl_down() will clear the BT status variables, | |
3168 | * which is correct, but when we restart we really | |
3169 | * want to keep them so restore them afterwards. | |
3170 | * | |
3171 | * The restart process will later pick them up and | |
3172 | * re-configure the hw when we reconfigure the BT | |
3173 | * command. | |
3174 | */ | |
3175 | bt_sco = priv->bt_sco_active; | |
bee008b7 WYG |
3176 | bt_full_concurrent = priv->bt_full_concurrent; |
3177 | bt_ci_compliance = priv->bt_ci_compliance; | |
511b082d | 3178 | bt_load = priv->bt_traffic_load; |
da5dbb97 | 3179 | bt_status = priv->bt_status; |
511b082d | 3180 | |
a1174138 | 3181 | __iwl_down(priv); |
511b082d JB |
3182 | |
3183 | priv->bt_sco_active = bt_sco; | |
bee008b7 WYG |
3184 | priv->bt_full_concurrent = bt_full_concurrent; |
3185 | priv->bt_ci_compliance = bt_ci_compliance; | |
511b082d | 3186 | priv->bt_traffic_load = bt_load; |
da5dbb97 | 3187 | priv->bt_status = bt_status; |
511b082d | 3188 | |
19cc1087 | 3189 | mutex_unlock(&priv->mutex); |
a1174138 | 3190 | iwl_cancel_deferred_work(priv); |
19cc1087 JB |
3191 | ieee80211_restart_hw(priv->hw); |
3192 | } else { | |
3193 | iwl_down(priv); | |
80676518 JB |
3194 | |
3195 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3196 | return; | |
3197 | ||
3198 | mutex_lock(&priv->mutex); | |
3199 | __iwl_up(priv); | |
3200 | mutex_unlock(&priv->mutex); | |
19cc1087 | 3201 | } |
b481de9c ZY |
3202 | } |
3203 | ||
5b9f8cd3 | 3204 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 3205 | { |
c79dd5b5 TW |
3206 | struct iwl_priv *priv = |
3207 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
3208 | |
3209 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3210 | return; | |
3211 | ||
3212 | mutex_lock(&priv->mutex); | |
54b81550 | 3213 | iwlagn_rx_replenish(priv); |
b481de9c ZY |
3214 | mutex_unlock(&priv->mutex); |
3215 | } | |
3216 | ||
7878a5a4 MA |
3217 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
3218 | ||
1dda6d28 | 3219 | void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 3220 | { |
246ed355 | 3221 | struct iwl_rxon_context *ctx; |
b481de9c | 3222 | struct ieee80211_conf *conf = NULL; |
857485c0 | 3223 | int ret = 0; |
b481de9c | 3224 | |
1dda6d28 JB |
3225 | if (!vif || !priv->is_open) |
3226 | return; | |
3227 | ||
246ed355 JB |
3228 | ctx = iwl_rxon_ctx_from_vif(vif); |
3229 | ||
1dda6d28 | 3230 | if (vif->type == NL80211_IFTYPE_AP) { |
15b1687c | 3231 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
3232 | return; |
3233 | } | |
3234 | ||
b481de9c ZY |
3235 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
3236 | return; | |
3237 | ||
2a421b91 | 3238 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 3239 | |
b481de9c ZY |
3240 | conf = ieee80211_get_hw_conf(priv->hw); |
3241 | ||
246ed355 JB |
3242 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
3243 | iwlcore_commit_rxon(priv, ctx); | |
b481de9c | 3244 | |
948f5a2f | 3245 | ret = iwl_send_rxon_timing(priv, vif); |
857485c0 | 3246 | if (ret) |
8f2d3d2a | 3247 | IWL_WARN(priv, "RXON timing - " |
b481de9c ZY |
3248 | "Attempting to continue.\n"); |
3249 | ||
246ed355 | 3250 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 3251 | |
42eb7c64 | 3252 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 3253 | |
45823531 | 3254 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
246ed355 | 3255 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); |
45823531 | 3256 | |
246ed355 | 3257 | ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid); |
b481de9c | 3258 | |
e1623446 | 3259 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
1dda6d28 | 3260 | vif->bss_conf.aid, vif->bss_conf.beacon_int); |
b481de9c | 3261 | |
c213d745 | 3262 | if (vif->bss_conf.use_short_preamble) |
246ed355 | 3263 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3264 | else |
246ed355 | 3265 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3266 | |
246ed355 | 3267 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) { |
c213d745 | 3268 | if (vif->bss_conf.use_short_slot) |
246ed355 | 3269 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3270 | else |
246ed355 | 3271 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3272 | } |
3273 | ||
246ed355 | 3274 | iwlcore_commit_rxon(priv, ctx); |
b481de9c | 3275 | |
fe6b23dd | 3276 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
246ed355 | 3277 | vif->bss_conf.aid, ctx->active.bssid_addr); |
fe6b23dd | 3278 | |
1dda6d28 | 3279 | switch (vif->type) { |
05c914fe | 3280 | case NL80211_IFTYPE_STATION: |
b481de9c | 3281 | break; |
05c914fe | 3282 | case NL80211_IFTYPE_ADHOC: |
5b9f8cd3 | 3283 | iwl_send_beacon_cmd(priv); |
b481de9c | 3284 | break; |
b481de9c | 3285 | default: |
15b1687c | 3286 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
1dda6d28 | 3287 | __func__, vif->type); |
b481de9c ZY |
3288 | break; |
3289 | } | |
3290 | ||
04816448 GE |
3291 | /* the chain noise calibration will enabled PM upon completion |
3292 | * If chain noise has already been run, then we need to enable | |
3293 | * power management here */ | |
3294 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
e312c24c | 3295 | iwl_power_update_mode(priv, false); |
c90a74ba EG |
3296 | |
3297 | /* Enable Rx differential gain and sensitivity calibrations */ | |
3298 | iwl_chain_noise_reset(priv); | |
3299 | priv->start_calib = 1; | |
3300 | ||
508e32e1 RC |
3301 | } |
3302 | ||
b481de9c ZY |
3303 | /***************************************************************************** |
3304 | * | |
3305 | * mac80211 entry point functions | |
3306 | * | |
3307 | *****************************************************************************/ | |
3308 | ||
154b25ce | 3309 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 3310 | |
f0b6e2e8 RC |
3311 | /* |
3312 | * Not a mac80211 entry point function, but it fits in with all the | |
3313 | * other mac80211 functions grouped here. | |
3314 | */ | |
dd7a2509 JB |
3315 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
3316 | struct iwlagn_ucode_capabilities *capa) | |
f0b6e2e8 RC |
3317 | { |
3318 | int ret; | |
3319 | struct ieee80211_hw *hw = priv->hw; | |
3320 | hw->rate_control_algorithm = "iwl-agn-rs"; | |
3321 | ||
3322 | /* Tell mac80211 our characteristics */ | |
3323 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
f0b6e2e8 RC |
3324 | IEEE80211_HW_AMPDU_AGGREGATION | |
3325 | IEEE80211_HW_SPECTRUM_MGMT; | |
3326 | ||
3327 | if (!priv->cfg->broken_powersave) | |
3328 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | |
3329 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
3330 | ||
ba37a3d0 JB |
3331 | if (priv->cfg->sku & IWL_SKU_N) |
3332 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
3333 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
3334 | ||
8d9698b3 | 3335 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
fd1af15d JB |
3336 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
3337 | ||
f0b6e2e8 RC |
3338 | hw->wiphy->interface_modes = |
3339 | BIT(NL80211_IFTYPE_STATION) | | |
3340 | BIT(NL80211_IFTYPE_ADHOC); | |
3341 | ||
f6c8f152 | 3342 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
5be83de5 | 3343 | WIPHY_FLAG_DISABLE_BEACON_HINTS; |
f0b6e2e8 RC |
3344 | |
3345 | /* | |
3346 | * For now, disable PS by default because it affects | |
3347 | * RX performance significantly. | |
3348 | */ | |
5be83de5 | 3349 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
f0b6e2e8 | 3350 | |
1382c71c | 3351 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
f0b6e2e8 | 3352 | /* we create the 802.11 header and a zero-length SSID element */ |
dd7a2509 | 3353 | hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2; |
f0b6e2e8 RC |
3354 | |
3355 | /* Default value; 4 EDCA QOS priorities */ | |
3356 | hw->queues = 4; | |
3357 | ||
3358 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
3359 | ||
3360 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
3361 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3362 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
3363 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
3364 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3365 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
3366 | ||
3367 | ret = ieee80211_register_hw(priv->hw); | |
3368 | if (ret) { | |
3369 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
3370 | return ret; | |
3371 | } | |
3372 | priv->mac80211_registered = 1; | |
3373 | ||
3374 | return 0; | |
3375 | } | |
3376 | ||
3377 | ||
5b9f8cd3 | 3378 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3379 | { |
c79dd5b5 | 3380 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3381 | int ret; |
b481de9c | 3382 | |
e1623446 | 3383 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3384 | |
3385 | /* we should be verifying the device is ready to be opened */ | |
3386 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 3387 | ret = __iwl_up(priv); |
b481de9c | 3388 | mutex_unlock(&priv->mutex); |
5a66926a | 3389 | |
e655b9f0 | 3390 | if (ret) |
6cd0b1cb | 3391 | return ret; |
e655b9f0 | 3392 | |
c1842d61 TW |
3393 | if (iwl_is_rfkill(priv)) |
3394 | goto out; | |
3395 | ||
e1623446 | 3396 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 3397 | |
fe9b6b72 | 3398 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 3399 | * mac80211 will not be run successfully. */ |
154b25ce EG |
3400 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
3401 | test_bit(STATUS_READY, &priv->status), | |
3402 | UCODE_READY_TIMEOUT); | |
3403 | if (!ret) { | |
3404 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 3405 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 3406 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 3407 | return -ETIMEDOUT; |
5a66926a | 3408 | } |
fe9b6b72 | 3409 | } |
0a078ffa | 3410 | |
e932a609 JB |
3411 | iwl_led_start(priv); |
3412 | ||
c1842d61 | 3413 | out: |
0a078ffa | 3414 | priv->is_open = 1; |
e1623446 | 3415 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3416 | return 0; |
3417 | } | |
3418 | ||
5b9f8cd3 | 3419 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3420 | { |
c79dd5b5 | 3421 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3422 | |
e1623446 | 3423 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 3424 | |
19cc1087 | 3425 | if (!priv->is_open) |
e655b9f0 | 3426 | return; |
e655b9f0 | 3427 | |
b481de9c | 3428 | priv->is_open = 0; |
5a66926a | 3429 | |
5bddf549 | 3430 | if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) { |
e655b9f0 ZY |
3431 | /* stop mac, cancel any scan request and clear |
3432 | * RXON_FILTER_ASSOC_MSK BIT | |
3433 | */ | |
5a66926a | 3434 | mutex_lock(&priv->mutex); |
2a421b91 | 3435 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 3436 | mutex_unlock(&priv->mutex); |
fde3571f MA |
3437 | } |
3438 | ||
5b9f8cd3 | 3439 | iwl_down(priv); |
5a66926a ZY |
3440 | |
3441 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
3442 | |
3443 | /* enable interrupts again in order to receive rfkill changes */ | |
3444 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
3445 | iwl_enable_interrupts(priv); | |
948c171c | 3446 | |
e1623446 | 3447 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3448 | } |
3449 | ||
5b9f8cd3 | 3450 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3451 | { |
c79dd5b5 | 3452 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3453 | |
e1623446 | 3454 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 3455 | |
e1623446 | 3456 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3457 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3458 | |
74bcdb33 | 3459 | if (iwlagn_tx_skb(priv, skb)) |
b481de9c ZY |
3460 | dev_kfree_skb_any(skb); |
3461 | ||
e1623446 | 3462 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 3463 | return NETDEV_TX_OK; |
b481de9c ZY |
3464 | } |
3465 | ||
1dda6d28 | 3466 | void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 3467 | { |
246ed355 | 3468 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); |
857485c0 | 3469 | int ret = 0; |
b481de9c | 3470 | |
d986bcd1 | 3471 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3472 | return; |
3473 | ||
3474 | /* The following should be done only at AP bring up */ | |
246ed355 | 3475 | if (!iwl_is_associated_ctx(ctx)) { |
b481de9c ZY |
3476 | |
3477 | /* RXON - unassoc (to set timing command) */ | |
246ed355 JB |
3478 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
3479 | iwlcore_commit_rxon(priv, ctx); | |
b481de9c ZY |
3480 | |
3481 | /* RXON Timing */ | |
948f5a2f | 3482 | ret = iwl_send_rxon_timing(priv, vif); |
857485c0 | 3483 | if (ret) |
8f2d3d2a | 3484 | IWL_WARN(priv, "RXON timing failed - " |
b481de9c ZY |
3485 | "Attempting to continue.\n"); |
3486 | ||
f513dfff DH |
3487 | /* AP has all antennas */ |
3488 | priv->chain_noise_data.active_chains = | |
3489 | priv->hw_params.valid_rx_ant; | |
3490 | iwl_set_rxon_ht(priv, &priv->current_ht_config); | |
45823531 | 3491 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
246ed355 | 3492 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); |
b481de9c | 3493 | |
246ed355 | 3494 | ctx->staging.assoc_id = 0; |
1dda6d28 | 3495 | |
c213d745 | 3496 | if (vif->bss_conf.use_short_preamble) |
246ed355 | 3497 | ctx->staging.flags |= |
b481de9c ZY |
3498 | RXON_FLG_SHORT_PREAMBLE_MSK; |
3499 | else | |
246ed355 | 3500 | ctx->staging.flags &= |
b481de9c ZY |
3501 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
3502 | ||
246ed355 | 3503 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) { |
c213d745 | 3504 | if (vif->bss_conf.use_short_slot) |
246ed355 | 3505 | ctx->staging.flags |= |
b481de9c ZY |
3506 | RXON_FLG_SHORT_SLOT_MSK; |
3507 | else | |
246ed355 | 3508 | ctx->staging.flags &= |
b481de9c | 3509 | ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3510 | } |
3511 | /* restore RXON assoc */ | |
246ed355 JB |
3512 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
3513 | iwlcore_commit_rxon(priv, ctx); | |
e1493deb | 3514 | } |
5b9f8cd3 | 3515 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
3516 | |
3517 | /* FIXME - we need to add code here to detect a totally new | |
3518 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3519 | * clear sta table, add BCAST sta... */ | |
3520 | } | |
3521 | ||
5b9f8cd3 | 3522 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
b3fbdcf4 JB |
3523 | struct ieee80211_vif *vif, |
3524 | struct ieee80211_key_conf *keyconf, | |
3525 | struct ieee80211_sta *sta, | |
3526 | u32 iv32, u16 *phase1key) | |
ab885f8c | 3527 | { |
ab885f8c | 3528 | |
9f58671e | 3529 | struct iwl_priv *priv = hw->priv; |
a194e324 JB |
3530 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
3531 | ||
e1623446 | 3532 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 3533 | |
a194e324 | 3534 | iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta, |
b3fbdcf4 | 3535 | iv32, phase1key); |
ab885f8c | 3536 | |
e1623446 | 3537 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
3538 | } |
3539 | ||
5b9f8cd3 | 3540 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3541 | struct ieee80211_vif *vif, |
3542 | struct ieee80211_sta *sta, | |
b481de9c ZY |
3543 | struct ieee80211_key_conf *key) |
3544 | { | |
c79dd5b5 | 3545 | struct iwl_priv *priv = hw->priv; |
a194e324 | 3546 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
42986796 WT |
3547 | int ret; |
3548 | u8 sta_id; | |
3549 | bool is_default_wep_key = false; | |
b481de9c | 3550 | |
e1623446 | 3551 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3552 | |
90e8e424 | 3553 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 3554 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3555 | return -EOPNOTSUPP; |
3556 | } | |
b481de9c | 3557 | |
a194e324 | 3558 | sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta); |
0af8bcae JB |
3559 | if (sta_id == IWL_INVALID_STATION) |
3560 | return -EINVAL; | |
b481de9c | 3561 | |
6974e363 | 3562 | mutex_lock(&priv->mutex); |
2a421b91 | 3563 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 | 3564 | |
a90178fa JB |
3565 | /* |
3566 | * If we are getting WEP group key and we didn't receive any key mapping | |
6974e363 EG |
3567 | * so far, we are in legacy wep mode (group key only), otherwise we are |
3568 | * in 1X mode. | |
a90178fa JB |
3569 | * In legacy wep mode, we use another host command to the uCode. |
3570 | */ | |
97359d12 JB |
3571 | if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || |
3572 | key->cipher == WLAN_CIPHER_SUITE_WEP104) && | |
54c8067a | 3573 | !sta) { |
6974e363 EG |
3574 | if (cmd == SET_KEY) |
3575 | is_default_wep_key = !priv->key_mapping_key; | |
3576 | else | |
ccc038ab EG |
3577 | is_default_wep_key = |
3578 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 3579 | } |
052c4b9f | 3580 | |
b481de9c | 3581 | switch (cmd) { |
deb09c43 | 3582 | case SET_KEY: |
6974e363 EG |
3583 | if (is_default_wep_key) |
3584 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 3585 | else |
a194e324 JB |
3586 | ret = iwl_set_dynamic_key(priv, vif_priv->ctx, |
3587 | key, sta_id); | |
deb09c43 | 3588 | |
e1623446 | 3589 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
3590 | break; |
3591 | case DISABLE_KEY: | |
6974e363 EG |
3592 | if (is_default_wep_key) |
3593 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 3594 | else |
3ec47732 | 3595 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 3596 | |
e1623446 | 3597 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
3598 | break; |
3599 | default: | |
deb09c43 | 3600 | ret = -EINVAL; |
b481de9c ZY |
3601 | } |
3602 | ||
72e15d71 | 3603 | mutex_unlock(&priv->mutex); |
e1623446 | 3604 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3605 | |
deb09c43 | 3606 | return ret; |
b481de9c ZY |
3607 | } |
3608 | ||
5b9f8cd3 | 3609 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 3610 | struct ieee80211_vif *vif, |
832f47e3 JB |
3611 | enum ieee80211_ampdu_mlme_action action, |
3612 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) | |
d783b061 TW |
3613 | { |
3614 | struct iwl_priv *priv = hw->priv; | |
4620fefa | 3615 | int ret = -EINVAL; |
d783b061 | 3616 | |
e1623446 | 3617 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 3618 | sta->addr, tid); |
d783b061 TW |
3619 | |
3620 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
3621 | return -EACCES; | |
3622 | ||
4620fefa JB |
3623 | mutex_lock(&priv->mutex); |
3624 | ||
d783b061 TW |
3625 | switch (action) { |
3626 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 3627 | IWL_DEBUG_HT(priv, "start Rx\n"); |
4620fefa JB |
3628 | ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn); |
3629 | break; | |
d783b061 | 3630 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 3631 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
619753ff | 3632 | ret = iwl_sta_rx_agg_stop(priv, sta, tid); |
5c2207c6 | 3633 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa JB |
3634 | ret = 0; |
3635 | break; | |
d783b061 | 3636 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 3637 | IWL_DEBUG_HT(priv, "start Tx\n"); |
619753ff | 3638 | ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn); |
d5a0ffa3 WYG |
3639 | if (ret == 0) { |
3640 | priv->_agn.agg_tids_count++; | |
3641 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3642 | priv->_agn.agg_tids_count); | |
3643 | } | |
4620fefa | 3644 | break; |
d783b061 | 3645 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 3646 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
619753ff | 3647 | ret = iwlagn_tx_agg_stop(priv, vif, sta, tid); |
d5a0ffa3 WYG |
3648 | if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { |
3649 | priv->_agn.agg_tids_count--; | |
3650 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3651 | priv->_agn.agg_tids_count); | |
3652 | } | |
5c2207c6 | 3653 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa | 3654 | ret = 0; |
94597ab2 JB |
3655 | if (priv->cfg->use_rts_for_aggregation) { |
3656 | struct iwl_station_priv *sta_priv = | |
3657 | (void *) sta->drv_priv; | |
3658 | /* | |
3659 | * switch off RTS/CTS if it was previously enabled | |
3660 | */ | |
3661 | ||
3662 | sta_priv->lq_sta.lq.general_params.flags &= | |
3663 | ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
3664 | iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq, | |
3665 | CMD_ASYNC, false); | |
3666 | } | |
4620fefa | 3667 | break; |
f0527971 | 3668 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
94597ab2 JB |
3669 | if (priv->cfg->use_rts_for_aggregation) { |
3670 | struct iwl_station_priv *sta_priv = | |
3671 | (void *) sta->drv_priv; | |
3672 | ||
cfecc6b4 WYG |
3673 | /* |
3674 | * switch to RTS/CTS if it is the prefer protection | |
3675 | * method for HT traffic | |
3676 | */ | |
94597ab2 JB |
3677 | |
3678 | sta_priv->lq_sta.lq.general_params.flags |= | |
3679 | LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
3680 | iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq, | |
3681 | CMD_ASYNC, false); | |
cfecc6b4 WYG |
3682 | } |
3683 | ret = 0; | |
d783b061 TW |
3684 | break; |
3685 | } | |
4620fefa JB |
3686 | mutex_unlock(&priv->mutex); |
3687 | ||
3688 | return ret; | |
d783b061 | 3689 | } |
9f58671e | 3690 | |
6ab10ff8 JB |
3691 | static void iwl_mac_sta_notify(struct ieee80211_hw *hw, |
3692 | struct ieee80211_vif *vif, | |
3693 | enum sta_notify_cmd cmd, | |
3694 | struct ieee80211_sta *sta) | |
3695 | { | |
3696 | struct iwl_priv *priv = hw->priv; | |
3697 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
3698 | int sta_id; | |
3699 | ||
6ab10ff8 | 3700 | switch (cmd) { |
6ab10ff8 JB |
3701 | case STA_NOTIFY_SLEEP: |
3702 | WARN_ON(!sta_priv->client); | |
3703 | sta_priv->asleep = true; | |
3704 | if (atomic_read(&sta_priv->pending_frames) > 0) | |
3705 | ieee80211_sta_block_awake(hw, sta, true); | |
3706 | break; | |
3707 | case STA_NOTIFY_AWAKE: | |
3708 | WARN_ON(!sta_priv->client); | |
49dcc819 DH |
3709 | if (!sta_priv->asleep) |
3710 | break; | |
6ab10ff8 | 3711 | sta_priv->asleep = false; |
2a87c26b | 3712 | sta_id = iwl_sta_id(sta); |
6ab10ff8 JB |
3713 | if (sta_id != IWL_INVALID_STATION) |
3714 | iwl_sta_modify_ps_wake(priv, sta_id); | |
3715 | break; | |
3716 | default: | |
3717 | break; | |
3718 | } | |
3719 | } | |
3720 | ||
fe6b23dd RC |
3721 | static int iwlagn_mac_sta_add(struct ieee80211_hw *hw, |
3722 | struct ieee80211_vif *vif, | |
3723 | struct ieee80211_sta *sta) | |
3724 | { | |
3725 | struct iwl_priv *priv = hw->priv; | |
3726 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
a194e324 | 3727 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
eafdfbd3 | 3728 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
3729 | int ret; |
3730 | u8 sta_id; | |
3731 | ||
3732 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
3733 | sta->addr); | |
da5ae1cf RC |
3734 | mutex_lock(&priv->mutex); |
3735 | IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n", | |
3736 | sta->addr); | |
3737 | sta_priv->common.sta_id = IWL_INVALID_STATION; | |
fe6b23dd RC |
3738 | |
3739 | atomic_set(&sta_priv->pending_frames, 0); | |
3740 | if (vif->type == NL80211_IFTYPE_AP) | |
3741 | sta_priv->client = true; | |
3742 | ||
a194e324 JB |
3743 | ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr, |
3744 | is_ap, &sta->ht_cap, &sta_id); | |
fe6b23dd RC |
3745 | if (ret) { |
3746 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3747 | sta->addr, ret); | |
3748 | /* Should we return success if return code is EEXIST ? */ | |
da5ae1cf | 3749 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3750 | return ret; |
3751 | } | |
3752 | ||
fd1af15d JB |
3753 | sta_priv->common.sta_id = sta_id; |
3754 | ||
fe6b23dd | 3755 | /* Initialize rate scaling */ |
91dd6c27 | 3756 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
3757 | sta->addr); |
3758 | iwl_rs_rate_init(priv, sta, sta_id); | |
da5ae1cf | 3759 | mutex_unlock(&priv->mutex); |
fe6b23dd | 3760 | |
fd1af15d | 3761 | return 0; |
fe6b23dd RC |
3762 | } |
3763 | ||
79d07325 WYG |
3764 | static void iwl_mac_channel_switch(struct ieee80211_hw *hw, |
3765 | struct ieee80211_channel_switch *ch_switch) | |
3766 | { | |
3767 | struct iwl_priv *priv = hw->priv; | |
3768 | const struct iwl_channel_info *ch_info; | |
3769 | struct ieee80211_conf *conf = &hw->conf; | |
aa2dc6b5 | 3770 | struct ieee80211_channel *channel = ch_switch->channel; |
79d07325 | 3771 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; |
246ed355 JB |
3772 | /* |
3773 | * MULTI-FIXME | |
3774 | * When we add support for multiple interfaces, we need to | |
3775 | * revisit this. The channel switch command in the device | |
3776 | * only affects the BSS context, but what does that really | |
3777 | * mean? And what if we get a CSA on the second interface? | |
3778 | * This needs a lot of work. | |
3779 | */ | |
3780 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
79d07325 WYG |
3781 | u16 ch; |
3782 | unsigned long flags = 0; | |
3783 | ||
3784 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3785 | ||
3786 | if (iwl_is_rfkill(priv)) | |
3787 | goto out_exit; | |
3788 | ||
3789 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
3790 | test_bit(STATUS_SCANNING, &priv->status)) | |
3791 | goto out_exit; | |
3792 | ||
246ed355 | 3793 | if (!iwl_is_associated_ctx(ctx)) |
79d07325 WYG |
3794 | goto out_exit; |
3795 | ||
3796 | /* channel switch in progress */ | |
3797 | if (priv->switch_rxon.switch_in_progress == true) | |
3798 | goto out_exit; | |
3799 | ||
3800 | mutex_lock(&priv->mutex); | |
3801 | if (priv->cfg->ops->lib->set_channel_switch) { | |
3802 | ||
aa2dc6b5 | 3803 | ch = channel->hw_value; |
246ed355 | 3804 | if (le16_to_cpu(ctx->active.channel) != ch) { |
79d07325 | 3805 | ch_info = iwl_get_channel_info(priv, |
aa2dc6b5 | 3806 | channel->band, |
79d07325 WYG |
3807 | ch); |
3808 | if (!is_channel_valid(ch_info)) { | |
3809 | IWL_DEBUG_MAC80211(priv, "invalid channel\n"); | |
3810 | goto out; | |
3811 | } | |
3812 | spin_lock_irqsave(&priv->lock, flags); | |
3813 | ||
3814 | priv->current_ht_config.smps = conf->smps_mode; | |
3815 | ||
3816 | /* Configure HT40 channels */ | |
3817 | ht_conf->is_ht = conf_is_ht(conf); | |
3818 | if (ht_conf->is_ht) { | |
3819 | if (conf_is_ht40_minus(conf)) { | |
3820 | ht_conf->extension_chan_offset = | |
3821 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; | |
3822 | ht_conf->is_40mhz = true; | |
3823 | } else if (conf_is_ht40_plus(conf)) { | |
3824 | ht_conf->extension_chan_offset = | |
3825 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; | |
3826 | ht_conf->is_40mhz = true; | |
3827 | } else { | |
3828 | ht_conf->extension_chan_offset = | |
3829 | IEEE80211_HT_PARAM_CHA_SEC_NONE; | |
3830 | ht_conf->is_40mhz = false; | |
3831 | } | |
3832 | } else | |
3833 | ht_conf->is_40mhz = false; | |
3834 | ||
246ed355 JB |
3835 | if ((le16_to_cpu(ctx->staging.channel) != ch)) |
3836 | ctx->staging.flags = 0; | |
79d07325 | 3837 | |
246ed355 | 3838 | iwl_set_rxon_channel(priv, channel, ctx); |
79d07325 | 3839 | iwl_set_rxon_ht(priv, ht_conf); |
246ed355 | 3840 | iwl_set_flags_for_band(priv, ctx, channel->band, |
79d07325 WYG |
3841 | priv->vif); |
3842 | spin_unlock_irqrestore(&priv->lock, flags); | |
3843 | ||
3844 | iwl_set_rate(priv); | |
3845 | /* | |
3846 | * at this point, staging_rxon has the | |
3847 | * configuration for channel switch | |
3848 | */ | |
3849 | if (priv->cfg->ops->lib->set_channel_switch(priv, | |
3850 | ch_switch)) | |
3851 | priv->switch_rxon.switch_in_progress = false; | |
3852 | } | |
3853 | } | |
3854 | out: | |
3855 | mutex_unlock(&priv->mutex); | |
3856 | out_exit: | |
3857 | if (!priv->switch_rxon.switch_in_progress) | |
3858 | ieee80211_chswitch_done(priv->vif, false); | |
3859 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
3860 | } | |
3861 | ||
8b8ab9d5 JB |
3862 | static void iwlagn_configure_filter(struct ieee80211_hw *hw, |
3863 | unsigned int changed_flags, | |
3864 | unsigned int *total_flags, | |
3865 | u64 multicast) | |
3866 | { | |
3867 | struct iwl_priv *priv = hw->priv; | |
3868 | __le32 filter_or = 0, filter_nand = 0; | |
246ed355 | 3869 | struct iwl_rxon_context *ctx; |
8b8ab9d5 JB |
3870 | |
3871 | #define CHK(test, flag) do { \ | |
3872 | if (*total_flags & (test)) \ | |
3873 | filter_or |= (flag); \ | |
3874 | else \ | |
3875 | filter_nand |= (flag); \ | |
3876 | } while (0) | |
3877 | ||
3878 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", | |
3879 | changed_flags, *total_flags); | |
3880 | ||
3881 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
3882 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK); | |
3883 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); | |
3884 | ||
3885 | #undef CHK | |
3886 | ||
3887 | mutex_lock(&priv->mutex); | |
3888 | ||
246ed355 JB |
3889 | for_each_context(priv, ctx) { |
3890 | ctx->staging.filter_flags &= ~filter_nand; | |
3891 | ctx->staging.filter_flags |= filter_or; | |
3892 | iwlcore_commit_rxon(priv, ctx); | |
3893 | } | |
8b8ab9d5 JB |
3894 | |
3895 | mutex_unlock(&priv->mutex); | |
3896 | ||
3897 | /* | |
3898 | * Receiving all multicast frames is always enabled by the | |
3899 | * default flags setup in iwl_connection_init_rx_config() | |
3900 | * since we currently do not support programming multicast | |
3901 | * filters into the device. | |
3902 | */ | |
3903 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
3904 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
3905 | } | |
3906 | ||
716c74b0 WYG |
3907 | static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop) |
3908 | { | |
3909 | struct iwl_priv *priv = hw->priv; | |
3910 | ||
3911 | mutex_lock(&priv->mutex); | |
3912 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3913 | ||
3914 | /* do not support "flush" */ | |
3915 | if (!priv->cfg->ops->lib->txfifo_flush) | |
3916 | goto done; | |
3917 | ||
3918 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
3919 | IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n"); | |
3920 | goto done; | |
3921 | } | |
3922 | if (iwl_is_rfkill(priv)) { | |
3923 | IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n"); | |
3924 | goto done; | |
3925 | } | |
3926 | ||
3927 | /* | |
3928 | * mac80211 will not push any more frames for transmit | |
3929 | * until the flush is completed | |
3930 | */ | |
3931 | if (drop) { | |
3932 | IWL_DEBUG_MAC80211(priv, "send flush command\n"); | |
3933 | if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) { | |
3934 | IWL_ERR(priv, "flush request fail\n"); | |
3935 | goto done; | |
3936 | } | |
3937 | } | |
3938 | IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n"); | |
3939 | iwlagn_wait_tx_queue_empty(priv); | |
3940 | done: | |
3941 | mutex_unlock(&priv->mutex); | |
3942 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
3943 | } | |
3944 | ||
b481de9c ZY |
3945 | /***************************************************************************** |
3946 | * | |
3947 | * driver setup and teardown | |
3948 | * | |
3949 | *****************************************************************************/ | |
3950 | ||
4e39317d | 3951 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3952 | { |
d21050c7 | 3953 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3954 | |
3955 | init_waitqueue_head(&priv->wait_command_queue); | |
3956 | ||
5b9f8cd3 EG |
3957 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3958 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3959 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3960 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
65550636 | 3961 | INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush); |
bee008b7 | 3962 | INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency); |
fbba9410 | 3963 | INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config); |
4a4a9e81 TW |
3964 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
3965 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 3966 | |
2a421b91 | 3967 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3968 | |
4e39317d EG |
3969 | if (priv->cfg->ops->lib->setup_deferred_work) |
3970 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3971 | ||
3972 | init_timer(&priv->statistics_periodic); | |
3973 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3974 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3975 | |
a9e1cb6a WYG |
3976 | init_timer(&priv->ucode_trace); |
3977 | priv->ucode_trace.data = (unsigned long)priv; | |
3978 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3979 | ||
b74e31a9 WYG |
3980 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
3981 | init_timer(&priv->monitor_recover); | |
3982 | priv->monitor_recover.data = (unsigned long)priv; | |
3983 | priv->monitor_recover.function = | |
3984 | priv->cfg->ops->lib->recover_from_tx_stall; | |
3985 | } | |
3986 | ||
ef850d7c MA |
3987 | if (!priv->cfg->use_isr_legacy) |
3988 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3989 | iwl_irq_tasklet, (unsigned long)priv); | |
3990 | else | |
3991 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3992 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
3993 | } |
3994 | ||
4e39317d | 3995 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3996 | { |
4e39317d EG |
3997 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3998 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3999 | |
3ae6a054 | 4000 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c | 4001 | cancel_delayed_work(&priv->scan_check); |
88be0264 | 4002 | cancel_work_sync(&priv->start_internal_scan); |
b481de9c | 4003 | cancel_delayed_work(&priv->alive_start); |
815e629b | 4004 | cancel_work_sync(&priv->run_time_calib_work); |
b481de9c | 4005 | cancel_work_sync(&priv->beacon_update); |
bee008b7 | 4006 | cancel_work_sync(&priv->bt_full_concurrency); |
fbba9410 | 4007 | cancel_work_sync(&priv->bt_runtime_config); |
4e39317d | 4008 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 4009 | del_timer_sync(&priv->ucode_trace); |
b481de9c ZY |
4010 | } |
4011 | ||
89f186a8 RC |
4012 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
4013 | struct ieee80211_rate *rates) | |
4014 | { | |
4015 | int i; | |
4016 | ||
4017 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
4018 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
4019 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
4020 | rates[i].hw_value_short = i; | |
4021 | rates[i].flags = 0; | |
4022 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
4023 | /* | |
4024 | * If CCK != 1M then set short preamble rate flag. | |
4025 | */ | |
4026 | rates[i].flags |= | |
4027 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
4028 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
4029 | } | |
4030 | } | |
4031 | } | |
4032 | ||
4033 | static int iwl_init_drv(struct iwl_priv *priv) | |
4034 | { | |
4035 | int ret; | |
4036 | ||
4037 | priv->ibss_beacon = NULL; | |
4038 | ||
89f186a8 RC |
4039 | spin_lock_init(&priv->sta_lock); |
4040 | spin_lock_init(&priv->hcmd_lock); | |
4041 | ||
4042 | INIT_LIST_HEAD(&priv->free_frames); | |
4043 | ||
4044 | mutex_init(&priv->mutex); | |
d2dfe6df | 4045 | mutex_init(&priv->sync_cmd_mutex); |
89f186a8 | 4046 | |
89f186a8 RC |
4047 | priv->ieee_channels = NULL; |
4048 | priv->ieee_rates = NULL; | |
4049 | priv->band = IEEE80211_BAND_2GHZ; | |
4050 | ||
4051 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 4052 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 4053 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
d5a0ffa3 | 4054 | priv->_agn.agg_tids_count = 0; |
89f186a8 | 4055 | |
8a472da4 WYG |
4056 | /* initialize force reset */ |
4057 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
4058 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
4059 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
4060 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 RC |
4061 | |
4062 | /* Choose which receivers/antennas to use */ | |
4063 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 JB |
4064 | priv->cfg->ops->hcmd->set_rxon_chain(priv, |
4065 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
89f186a8 RC |
4066 | |
4067 | iwl_init_scan_params(priv); | |
4068 | ||
22bf59a0 WYG |
4069 | /* init bt coex */ |
4070 | if (priv->cfg->advanced_bt_coexist) { | |
b6e116e8 WYG |
4071 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; |
4072 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
4073 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
22bf59a0 WYG |
4074 | priv->bt_on_thresh = BT_ON_THRESHOLD_DEF; |
4075 | priv->bt_duration = BT_DURATION_LIMIT_DEF; | |
4076 | priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF; | |
4077 | priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF; | |
4078 | } | |
4079 | ||
89f186a8 RC |
4080 | /* Set the tx_power_user_lmt to the lowest power level |
4081 | * this value will get overwritten by channel max power avg | |
4082 | * from eeprom */ | |
b744cb79 | 4083 | priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
89f186a8 RC |
4084 | |
4085 | ret = iwl_init_channel_map(priv); | |
4086 | if (ret) { | |
4087 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
4088 | goto err; | |
4089 | } | |
4090 | ||
4091 | ret = iwlcore_init_geos(priv); | |
4092 | if (ret) { | |
4093 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
4094 | goto err_free_channel_map; | |
4095 | } | |
4096 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
4097 | ||
4098 | return 0; | |
4099 | ||
4100 | err_free_channel_map: | |
4101 | iwl_free_channel_map(priv); | |
4102 | err: | |
4103 | return ret; | |
4104 | } | |
4105 | ||
4106 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
4107 | { | |
4108 | iwl_calib_free_results(priv); | |
4109 | iwlcore_free_geos(priv); | |
4110 | iwl_free_channel_map(priv); | |
811ecc99 | 4111 | kfree(priv->scan_cmd); |
89f186a8 RC |
4112 | } |
4113 | ||
5b9f8cd3 EG |
4114 | static struct ieee80211_ops iwl_hw_ops = { |
4115 | .tx = iwl_mac_tx, | |
4116 | .start = iwl_mac_start, | |
4117 | .stop = iwl_mac_stop, | |
4118 | .add_interface = iwl_mac_add_interface, | |
4119 | .remove_interface = iwl_mac_remove_interface, | |
4120 | .config = iwl_mac_config, | |
8b8ab9d5 | 4121 | .configure_filter = iwlagn_configure_filter, |
5b9f8cd3 EG |
4122 | .set_key = iwl_mac_set_key, |
4123 | .update_tkip_key = iwl_mac_update_tkip_key, | |
5b9f8cd3 EG |
4124 | .conf_tx = iwl_mac_conf_tx, |
4125 | .reset_tsf = iwl_mac_reset_tsf, | |
4126 | .bss_info_changed = iwl_bss_info_changed, | |
4127 | .ampdu_action = iwl_mac_ampdu_action, | |
6ab10ff8 JB |
4128 | .hw_scan = iwl_mac_hw_scan, |
4129 | .sta_notify = iwl_mac_sta_notify, | |
fe6b23dd RC |
4130 | .sta_add = iwlagn_mac_sta_add, |
4131 | .sta_remove = iwl_mac_sta_remove, | |
79d07325 | 4132 | .channel_switch = iwl_mac_channel_switch, |
716c74b0 | 4133 | .flush = iwl_mac_flush, |
a85d7cca | 4134 | .tx_last_beacon = iwl_mac_tx_last_beacon, |
b481de9c ZY |
4135 | }; |
4136 | ||
3867fe04 WYG |
4137 | static void iwl_hw_detect(struct iwl_priv *priv) |
4138 | { | |
4139 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); | |
4140 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); | |
4141 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id); | |
49ded76b | 4142 | IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id); |
3867fe04 WYG |
4143 | } |
4144 | ||
07d4f1ad WYG |
4145 | static int iwl_set_hw_params(struct iwl_priv *priv) |
4146 | { | |
4147 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; | |
4148 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
4149 | if (priv->cfg->mod_params->amsdu_size_8K) | |
4150 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K); | |
4151 | else | |
4152 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K); | |
4153 | ||
4154 | priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL; | |
4155 | ||
4156 | if (priv->cfg->mod_params->disable_11n) | |
4157 | priv->cfg->sku &= ~IWL_SKU_N; | |
4158 | ||
4159 | /* Device-specific setup */ | |
4160 | return priv->cfg->ops->lib->set_hw_params(priv); | |
4161 | } | |
4162 | ||
5b9f8cd3 | 4163 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c | 4164 | { |
246ed355 | 4165 | int err = 0, i; |
c79dd5b5 | 4166 | struct iwl_priv *priv; |
b481de9c | 4167 | struct ieee80211_hw *hw; |
82b9a121 | 4168 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 4169 | unsigned long flags; |
c6fa17ed | 4170 | u16 pci_cmd, num_mac; |
b481de9c | 4171 | |
316c30d9 AK |
4172 | /************************ |
4173 | * 1. Allocating HW data | |
4174 | ************************/ | |
4175 | ||
6440adb5 BC |
4176 | /* Disabling hardware scan means that mac80211 will perform scans |
4177 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 4178 | if (cfg->mod_params->disable_hw_scan) { |
a562a9dd | 4179 | if (iwl_debug_level & IWL_DL_INFO) |
bf403db8 EK |
4180 | dev_printk(KERN_DEBUG, &(pdev->dev), |
4181 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 4182 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
4183 | } |
4184 | ||
5b9f8cd3 | 4185 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 4186 | if (!hw) { |
b481de9c ZY |
4187 | err = -ENOMEM; |
4188 | goto out; | |
4189 | } | |
1d0a082d AK |
4190 | priv = hw->priv; |
4191 | /* At this point both hw and priv are allocated. */ | |
4192 | ||
246ed355 JB |
4193 | /* |
4194 | * The default context is always valid, | |
4195 | * more may be discovered when firmware | |
4196 | * is loaded. | |
4197 | */ | |
4198 | priv->valid_contexts = BIT(IWL_RXON_CTX_BSS); | |
4199 | ||
4200 | for (i = 0; i < NUM_IWL_RXON_CTX; i++) | |
4201 | priv->contexts[i].ctxid = i; | |
4202 | ||
8f2d3d2a JB |
4203 | priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON; |
4204 | priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING; | |
4205 | priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC; | |
8dfdb9d5 | 4206 | priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM; |
8f2d3d2a JB |
4207 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 1); |
4208 | ||
b481de9c ZY |
4209 | SET_IEEE80211_DEV(hw, &pdev->dev); |
4210 | ||
e1623446 | 4211 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 4212 | priv->cfg = cfg; |
b481de9c | 4213 | priv->pci_dev = pdev; |
40cefda9 | 4214 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 4215 | |
bee008b7 WYG |
4216 | /* is antenna coupling more than 35dB ? */ |
4217 | priv->bt_ant_couple_ok = | |
4218 | (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ? | |
4219 | true : false; | |
4220 | ||
f37837c9 WYG |
4221 | /* enable/disable bt channel announcement */ |
4222 | priv->bt_ch_announce = iwlagn_bt_ch_announce; | |
4223 | ||
20594eb0 WYG |
4224 | if (iwl_alloc_traffic_mem(priv)) |
4225 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 4226 | |
316c30d9 AK |
4227 | /************************** |
4228 | * 2. Initializing PCI bus | |
4229 | **************************/ | |
1a7123cd JL |
4230 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
4231 | PCIE_LINK_STATE_CLKPM); | |
4232 | ||
316c30d9 AK |
4233 | if (pci_enable_device(pdev)) { |
4234 | err = -ENODEV; | |
4235 | goto out_ieee80211_free_hw; | |
4236 | } | |
4237 | ||
4238 | pci_set_master(pdev); | |
4239 | ||
093d874c | 4240 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 4241 | if (!err) |
093d874c | 4242 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 4243 | if (err) { |
093d874c | 4244 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 4245 | if (!err) |
093d874c | 4246 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 4247 | /* both attempts failed: */ |
316c30d9 | 4248 | if (err) { |
978785a3 | 4249 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 4250 | goto out_pci_disable_device; |
cc2a8ea8 | 4251 | } |
316c30d9 AK |
4252 | } |
4253 | ||
4254 | err = pci_request_regions(pdev, DRV_NAME); | |
4255 | if (err) | |
4256 | goto out_pci_disable_device; | |
4257 | ||
4258 | pci_set_drvdata(pdev, priv); | |
4259 | ||
316c30d9 AK |
4260 | |
4261 | /*********************** | |
4262 | * 3. Read REV register | |
4263 | ***********************/ | |
4264 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
4265 | if (!priv->hw_base) { | |
4266 | err = -ENODEV; | |
4267 | goto out_pci_release_regions; | |
4268 | } | |
4269 | ||
e1623446 | 4270 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 4271 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 4272 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 4273 | |
731a29b7 | 4274 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
4275 | * we should init now |
4276 | */ | |
4277 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 4278 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
4279 | |
4280 | /* | |
4281 | * stop and reset the on-board processor just in case it is in a | |
4282 | * strange state ... like being left stranded by a primary kernel | |
4283 | * and this is now the kdump kernel trying to start up | |
4284 | */ | |
4285 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
4286 | ||
b661c819 | 4287 | iwl_hw_detect(priv); |
c11362c0 | 4288 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
b661c819 | 4289 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 4290 | |
e7b63581 TW |
4291 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4292 | * PCI Tx retries from interfering with C3 CPU state */ | |
4293 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
4294 | ||
086ed117 MA |
4295 | iwl_prepare_card_hw(priv); |
4296 | if (!priv->hw_ready) { | |
4297 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
4298 | goto out_iounmap; | |
4299 | } | |
4300 | ||
91238714 TW |
4301 | /***************** |
4302 | * 4. Read EEPROM | |
4303 | *****************/ | |
316c30d9 AK |
4304 | /* Read the EEPROM */ |
4305 | err = iwl_eeprom_init(priv); | |
4306 | if (err) { | |
15b1687c | 4307 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
4308 | goto out_iounmap; |
4309 | } | |
8614f360 TW |
4310 | err = iwl_eeprom_check_version(priv); |
4311 | if (err) | |
c8f16138 | 4312 | goto out_free_eeprom; |
8614f360 | 4313 | |
02883017 | 4314 | /* extract MAC Address */ |
c6fa17ed WYG |
4315 | iwl_eeprom_get_mac(priv, priv->addresses[0].addr); |
4316 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr); | |
4317 | priv->hw->wiphy->addresses = priv->addresses; | |
4318 | priv->hw->wiphy->n_addresses = 1; | |
4319 | num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS); | |
4320 | if (num_mac > 1) { | |
4321 | memcpy(priv->addresses[1].addr, priv->addresses[0].addr, | |
4322 | ETH_ALEN); | |
4323 | priv->addresses[1].addr[5]++; | |
4324 | priv->hw->wiphy->n_addresses++; | |
4325 | } | |
316c30d9 AK |
4326 | |
4327 | /************************ | |
4328 | * 5. Setup HW constants | |
4329 | ************************/ | |
da154e30 | 4330 | if (iwl_set_hw_params(priv)) { |
15b1687c | 4331 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 4332 | goto out_free_eeprom; |
316c30d9 AK |
4333 | } |
4334 | ||
4335 | /******************* | |
6ba87956 | 4336 | * 6. Setup priv |
316c30d9 | 4337 | *******************/ |
b481de9c | 4338 | |
6ba87956 | 4339 | err = iwl_init_drv(priv); |
bf85ea4f | 4340 | if (err) |
399f4900 | 4341 | goto out_free_eeprom; |
bf85ea4f | 4342 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 4343 | |
316c30d9 | 4344 | /******************** |
09f9bf79 | 4345 | * 7. Setup services |
316c30d9 | 4346 | ********************/ |
0359facc | 4347 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 4348 | iwl_disable_interrupts(priv); |
0359facc | 4349 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 4350 | |
6cd0b1cb HS |
4351 | pci_enable_msi(priv->pci_dev); |
4352 | ||
ef850d7c MA |
4353 | iwl_alloc_isr_ict(priv); |
4354 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
4355 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
4356 | if (err) { |
4357 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4358 | goto out_disable_msi; | |
4359 | } | |
316c30d9 | 4360 | |
4e39317d | 4361 | iwl_setup_deferred_work(priv); |
653fa4a0 | 4362 | iwl_setup_rx_handlers(priv); |
316c30d9 | 4363 | |
158bea07 JB |
4364 | /********************************************* |
4365 | * 8. Enable interrupts and read RFKILL state | |
4366 | *********************************************/ | |
6ba87956 | 4367 | |
6cd0b1cb HS |
4368 | /* enable interrupts if needed: hw bug w/a */ |
4369 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
4370 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
4371 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
4372 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
4373 | } | |
4374 | ||
4375 | iwl_enable_interrupts(priv); | |
4376 | ||
6cd0b1cb HS |
4377 | /* If platform's RF_KILL switch is NOT set to KILL */ |
4378 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
4379 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
4380 | else | |
4381 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 4382 | |
a60e77e5 JB |
4383 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
4384 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 4385 | |
58d0f361 | 4386 | iwl_power_initialize(priv); |
39b73fb1 | 4387 | iwl_tt_initialize(priv); |
158bea07 | 4388 | |
a15707d8 | 4389 | init_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 4390 | |
b08dfd04 | 4391 | err = iwl_request_firmware(priv, true); |
158bea07 | 4392 | if (err) |
7d47618a | 4393 | goto out_destroy_workqueue; |
158bea07 | 4394 | |
b481de9c ZY |
4395 | return 0; |
4396 | ||
7d47618a | 4397 | out_destroy_workqueue: |
c8f16138 RC |
4398 | destroy_workqueue(priv->workqueue); |
4399 | priv->workqueue = NULL; | |
795cc0ad | 4400 | free_irq(priv->pci_dev->irq, priv); |
ef850d7c | 4401 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
4402 | out_disable_msi: |
4403 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 4404 | iwl_uninit_drv(priv); |
073d3f5f TW |
4405 | out_free_eeprom: |
4406 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4407 | out_iounmap: |
4408 | pci_iounmap(pdev, priv->hw_base); | |
4409 | out_pci_release_regions: | |
316c30d9 | 4410 | pci_set_drvdata(pdev, NULL); |
623d563e | 4411 | pci_release_regions(pdev); |
b481de9c ZY |
4412 | out_pci_disable_device: |
4413 | pci_disable_device(pdev); | |
b481de9c | 4414 | out_ieee80211_free_hw: |
20594eb0 | 4415 | iwl_free_traffic_mem(priv); |
d7c76f4c | 4416 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
4417 | out: |
4418 | return err; | |
4419 | } | |
4420 | ||
5b9f8cd3 | 4421 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 4422 | { |
c79dd5b5 | 4423 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4424 | unsigned long flags; |
b481de9c ZY |
4425 | |
4426 | if (!priv) | |
4427 | return; | |
4428 | ||
a15707d8 | 4429 | wait_for_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 4430 | |
e1623446 | 4431 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4432 | |
67249625 | 4433 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 4434 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 4435 | |
5b9f8cd3 EG |
4436 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
4437 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
4438 | * we need to set STATUS_EXIT_PENDING bit. |
4439 | */ | |
4440 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
4441 | if (priv->mac80211_registered) { |
4442 | ieee80211_unregister_hw(priv->hw); | |
4443 | priv->mac80211_registered = 0; | |
0b124c31 | 4444 | } else { |
5b9f8cd3 | 4445 | iwl_down(priv); |
c4f55232 RR |
4446 | } |
4447 | ||
c166b25a BC |
4448 | /* |
4449 | * Make sure device is reset to low power before unloading driver. | |
4450 | * This may be redundant with iwl_down(), but there are paths to | |
4451 | * run iwl_down() without calling apm_ops.stop(), and there are | |
4452 | * paths to avoid running iwl_down() at all before leaving driver. | |
4453 | * This (inexpensive) call *makes sure* device is reset. | |
4454 | */ | |
4455 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
4456 | ||
39b73fb1 WYG |
4457 | iwl_tt_exit(priv); |
4458 | ||
0359facc MA |
4459 | /* make sure we flush any pending irq or |
4460 | * tasklet for the driver | |
4461 | */ | |
4462 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 4463 | iwl_disable_interrupts(priv); |
0359facc MA |
4464 | spin_unlock_irqrestore(&priv->lock, flags); |
4465 | ||
4466 | iwl_synchronize_irq(priv); | |
4467 | ||
5b9f8cd3 | 4468 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
4469 | |
4470 | if (priv->rxq.bd) | |
54b81550 | 4471 | iwlagn_rx_queue_free(priv, &priv->rxq); |
74bcdb33 | 4472 | iwlagn_hw_txq_ctx_free(priv); |
b481de9c | 4473 | |
073d3f5f | 4474 | iwl_eeprom_free(priv); |
b481de9c | 4475 | |
b481de9c | 4476 | |
948c171c MA |
4477 | /*netif_stop_queue(dev); */ |
4478 | flush_workqueue(priv->workqueue); | |
4479 | ||
5b9f8cd3 | 4480 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
4481 | * priv->workqueue... so we can't take down the workqueue |
4482 | * until now... */ | |
4483 | destroy_workqueue(priv->workqueue); | |
4484 | priv->workqueue = NULL; | |
20594eb0 | 4485 | iwl_free_traffic_mem(priv); |
b481de9c | 4486 | |
6cd0b1cb HS |
4487 | free_irq(priv->pci_dev->irq, priv); |
4488 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
4489 | pci_iounmap(pdev, priv->hw_base); |
4490 | pci_release_regions(pdev); | |
4491 | pci_disable_device(pdev); | |
4492 | pci_set_drvdata(pdev, NULL); | |
4493 | ||
6ba87956 | 4494 | iwl_uninit_drv(priv); |
b481de9c | 4495 | |
ef850d7c MA |
4496 | iwl_free_isr_ict(priv); |
4497 | ||
b481de9c ZY |
4498 | if (priv->ibss_beacon) |
4499 | dev_kfree_skb(priv->ibss_beacon); | |
4500 | ||
4501 | ieee80211_free_hw(priv->hw); | |
4502 | } | |
4503 | ||
b481de9c ZY |
4504 | |
4505 | /***************************************************************************** | |
4506 | * | |
4507 | * driver and module entry point | |
4508 | * | |
4509 | *****************************************************************************/ | |
4510 | ||
fed9017e | 4511 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
a3aa1884 | 4512 | static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = { |
4fc22b21 | 4513 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
4514 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
4515 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 4516 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 4517 | #ifdef CONFIG_IWL5000 |
ac592574 WYG |
4518 | /* 5100 Series WiFi */ |
4519 | {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ | |
4520 | {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4521 | {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ | |
4522 | {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4523 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4524 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4525 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ | |
4526 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4527 | {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */ | |
4528 | {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4529 | {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */ | |
4530 | {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4531 | {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4532 | {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4533 | {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */ | |
4534 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4535 | {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */ | |
4536 | {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4537 | {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */ | |
4538 | {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4539 | {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4540 | {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4541 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */ | |
4542 | {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4543 | ||
4544 | /* 5300 Series WiFi */ | |
4545 | {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */ | |
4546 | {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4547 | {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */ | |
4548 | {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4549 | {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */ | |
4550 | {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4551 | {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */ | |
4552 | {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4553 | {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */ | |
4554 | {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4555 | {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */ | |
4556 | {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4557 | ||
4558 | /* 5350 Series WiFi/WiMax */ | |
4559 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */ | |
4560 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */ | |
4561 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */ | |
4562 | ||
4563 | /* 5150 Series Wifi/WiMax */ | |
4564 | {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */ | |
4565 | {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4566 | {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */ | |
4567 | {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
4568 | {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */ | |
4569 | {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4570 | ||
4571 | {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */ | |
4572 | {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4573 | {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */ | |
4574 | {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
5953a62e WYG |
4575 | |
4576 | /* 6x00 Series */ | |
5953a62e WYG |
4577 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, |
4578 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
4579 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
4580 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
4581 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
4582 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
4583 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
4584 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
4585 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
4586 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
4b3e8062 | 4587 | |
95b13014 SZ |
4588 | /* 6x00 Series Gen2a */ |
4589 | {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)}, | |
4590 | {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)}, | |
4591 | {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)}, | |
1808972f SZ |
4592 | {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)}, |
4593 | {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)}, | |
4594 | {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)}, | |
4595 | {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)}, | |
9f6e1baf SZ |
4596 | {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)}, |
4597 | {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)}, | |
4598 | {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)}, | |
4599 | {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)}, | |
4600 | {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)}, | |
4601 | {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)}, | |
4602 | {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)}, | |
1808972f SZ |
4603 | |
4604 | /* 6x00 Series Gen2b */ | |
4605 | {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)}, | |
4606 | {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)}, | |
4607 | {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)}, | |
4608 | {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)}, | |
4609 | {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)}, | |
4610 | {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)}, | |
4611 | {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)}, | |
4612 | {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)}, | |
4613 | {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)}, | |
4614 | {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)}, | |
4615 | {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)}, | |
9f6e1baf SZ |
4616 | {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)}, |
4617 | {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)}, | |
4618 | {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)}, | |
4619 | {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)}, | |
4620 | {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)}, | |
4621 | {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)}, | |
4622 | {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)}, | |
4623 | {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)}, | |
4624 | {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)}, | |
4625 | {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)}, | |
4626 | {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)}, | |
4627 | {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)}, | |
4628 | {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)}, | |
4629 | {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)}, | |
4630 | {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)}, | |
4631 | {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)}, | |
4632 | {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)}, | |
5953a62e WYG |
4633 | |
4634 | /* 6x50 WiFi/WiMax Series */ | |
5953a62e WYG |
4635 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, |
4636 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
4637 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
4638 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
5953a62e WYG |
4639 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, |
4640 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
4641 | ||
03264339 SZ |
4642 | /* 6x50 WiFi/WiMax Series Gen2 */ |
4643 | {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)}, | |
4644 | {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)}, | |
4645 | {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)}, | |
4646 | {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)}, | |
4647 | {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)}, | |
4648 | {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)}, | |
4649 | ||
77dcb6a9 | 4650 | /* 1000 Series WiFi */ |
4bd0914f WYG |
4651 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
4652 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
4653 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
4654 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
4655 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
4656 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
4657 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
4658 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
4659 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
4660 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
4661 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
4662 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
5a6a256e | 4663 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 4664 | |
fed9017e RR |
4665 | {0} |
4666 | }; | |
4667 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
4668 | ||
4669 | static struct pci_driver iwl_driver = { | |
b481de9c | 4670 | .name = DRV_NAME, |
fed9017e | 4671 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
4672 | .probe = iwl_pci_probe, |
4673 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 4674 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
4675 | .suspend = iwl_pci_suspend, |
4676 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4677 | #endif |
4678 | }; | |
4679 | ||
5b9f8cd3 | 4680 | static int __init iwl_init(void) |
b481de9c ZY |
4681 | { |
4682 | ||
4683 | int ret; | |
c96c31e4 JP |
4684 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); |
4685 | pr_info(DRV_COPYRIGHT "\n"); | |
897e1cf2 | 4686 | |
e227ceac | 4687 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 4688 | if (ret) { |
c96c31e4 | 4689 | pr_err("Unable to register rate control algorithm: %d\n", ret); |
897e1cf2 RC |
4690 | return ret; |
4691 | } | |
4692 | ||
fed9017e | 4693 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 4694 | if (ret) { |
c96c31e4 | 4695 | pr_err("Unable to initialize PCI module\n"); |
897e1cf2 | 4696 | goto error_register; |
b481de9c | 4697 | } |
b481de9c ZY |
4698 | |
4699 | return ret; | |
897e1cf2 | 4700 | |
897e1cf2 | 4701 | error_register: |
e227ceac | 4702 | iwlagn_rate_control_unregister(); |
897e1cf2 | 4703 | return ret; |
b481de9c ZY |
4704 | } |
4705 | ||
5b9f8cd3 | 4706 | static void __exit iwl_exit(void) |
b481de9c | 4707 | { |
fed9017e | 4708 | pci_unregister_driver(&iwl_driver); |
e227ceac | 4709 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
4710 | } |
4711 | ||
5b9f8cd3 EG |
4712 | module_exit(iwl_exit); |
4713 | module_init(iwl_init); | |
a562a9dd RC |
4714 | |
4715 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 4716 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); |
a562a9dd | 4717 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); |
4e30cb69 | 4718 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
4719 | MODULE_PARM_DESC(debug, "debug output mask"); |
4720 | #endif | |
4721 | ||
2b068618 WYG |
4722 | module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO); |
4723 | MODULE_PARM_DESC(swcrypto50, | |
4724 | "using crypto in software (default 0 [hardware]) (deprecated)"); | |
4725 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); | |
4726 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | |
4727 | module_param_named(queues_num50, | |
4728 | iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
4729 | MODULE_PARM_DESC(queues_num50, | |
4730 | "number of hw queues in 50xx series (deprecated)"); | |
4731 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
4732 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
4733 | module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
4734 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)"); | |
4735 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
4736 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
4737 | module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K, | |
4738 | int, S_IRUGO); | |
4739 | MODULE_PARM_DESC(amsdu_size_8K50, | |
4740 | "enable 8K amsdu size in 50XX series (deprecated)"); | |
4741 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, | |
4742 | int, S_IRUGO); | |
4743 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
4744 | module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
4745 | MODULE_PARM_DESC(fw_restart50, | |
4746 | "restart firmware in case of error (deprecated)"); | |
4747 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
4748 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | |
4749 | module_param_named( | |
4750 | disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO); | |
4751 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); | |
dd7a2509 JB |
4752 | |
4753 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | |
4754 | S_IRUGO); | |
4755 | MODULE_PARM_DESC(ucode_alternative, | |
4756 | "specify ucode alternative to use from ucode file"); | |
bee008b7 WYG |
4757 | |
4758 | module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO); | |
4759 | MODULE_PARM_DESC(antenna_coupling, | |
4760 | "specify antenna coupling in dB (defualt: 0 dB)"); | |
f37837c9 WYG |
4761 | |
4762 | module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO); | |
4763 | MODULE_PARM_DESC(bt_ch_announce, | |
4764 | "Enable BT channel announcement mode (default: enable)"); |