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iwl3945: use iwl_get_sta_id from iwlwifi
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CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
b481de9c
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
b481de9c
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
b481de9c
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
a326a5d0
EG
118 /* allow CTS-to-self if possible. this is relevant only for
119 * 5000, but will not damage 4965 */
120 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
b481de9c 121
8ccde88a 122 ret = iwl_check_rxon_cmd(priv);
43d59b32 123 if (ret) {
15b1687c 124 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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125 return -EINVAL;
126 }
127
128 /* If we don't need to send a full RXON, we can use
5b9f8cd3 129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 130 * and other flags for the current radio configuration. */
54559703 131 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
15b1687c 134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 135 return ret;
b481de9c
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136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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139 return 0;
140 }
141
142 /* station table will be cleared */
143 priv->assoc_station_added = 0;
144
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145 /* If we are currently associated and the new config requires
146 * an RXON_ASSOC and the new config wants the associated mask enabled,
147 * we must clear the associated from the active configuration
148 * before we apply the new config */
43d59b32 149 if (iwl_is_associated(priv) && new_assoc) {
e1623446 150 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
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151 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
152
43d59b32 153 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 154 sizeof(struct iwl_rxon_cmd),
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155 &priv->active_rxon);
156
157 /* If the mask clearing failed then we set
158 * active_rxon back to what it was previously */
43d59b32 159 if (ret) {
b481de9c 160 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 161 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 162 return ret;
b481de9c 163 }
b481de9c
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164 }
165
e1623446 166 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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167 "* with%s RXON_FILTER_ASSOC_MSK\n"
168 "* channel = %d\n"
e174961c 169 "* bssid = %pM\n",
43d59b32 170 (new_assoc ? "" : "out"),
b481de9c 171 le16_to_cpu(priv->staging_rxon.channel),
e174961c 172 priv->staging_rxon.bssid_addr);
b481de9c 173
5b9f8cd3 174 iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
43d59b32
EG
175
176 /* Apply the new configuration
177 * RXON unassoc clears the station table in uCode, send it before
178 * we add the bcast station. If assoc bit is set, we will send RXON
179 * after having added the bcast and bssid station.
180 */
181 if (!new_assoc) {
182 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 183 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 184 if (ret) {
15b1687c 185 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
186 return ret;
187 }
188 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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189 }
190
e11bc028 191 priv->cfg->ops->smgmt->clear_station_table(priv);
556f8db7 192
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193 if (!priv->error_recovering)
194 priv->start_calib = 0;
195
b481de9c 196 /* Add the broadcast address so we can send broadcast frames */
4f40e4d9 197 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
43d59b32 198 IWL_INVALID_STATION) {
15b1687c 199 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
b481de9c
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200 return -EIO;
201 }
202
203 /* If we have set the ASSOC_MSK and we are in BSS mode then
204 * add the IWL_AP_ID to the station rate table */
9185159d 205 if (new_assoc) {
05c914fe 206 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
207 ret = iwl_rxon_add_station(priv,
208 priv->active_rxon.bssid_addr, 1);
209 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
210 IWL_ERR(priv,
211 "Error adding AP address for TX.\n");
9185159d
TW
212 return -EIO;
213 }
214 priv->assoc_station_added = 1;
215 if (priv->default_wep_key &&
216 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
217 IWL_ERR(priv,
218 "Could not send WEP static key.\n");
b481de9c 219 }
43d59b32
EG
220
221 /* Apply the new configuration
222 * RXON assoc doesn't clear the station table in uCode,
223 */
224 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
225 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
226 if (ret) {
15b1687c 227 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
228 return ret;
229 }
230 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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231 }
232
36da7d70
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233 iwl_init_sensitivity(priv);
234
235 /* If we issue a new RXON command which required a tune then we must
236 * send a new TXPOWER command or we won't be able to Tx any frames */
237 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
238 if (ret) {
15b1687c 239 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
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240 return ret;
241 }
242
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243 return 0;
244}
245
5b9f8cd3 246void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
247{
248
c7de35cd 249 iwl_set_rxon_chain(priv);
e0158e61 250 iwlcore_commit_rxon(priv);
5da4b55f
MA
251}
252
fcab423d 253static void iwl_clear_free_frames(struct iwl_priv *priv)
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254{
255 struct list_head *element;
256
e1623446 257 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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258 priv->frames_count);
259
260 while (!list_empty(&priv->free_frames)) {
261 element = priv->free_frames.next;
262 list_del(element);
fcab423d 263 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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264 priv->frames_count--;
265 }
266
267 if (priv->frames_count) {
39aadf8c 268 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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269 priv->frames_count);
270 priv->frames_count = 0;
271 }
272}
273
fcab423d 274static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 275{
fcab423d 276 struct iwl_frame *frame;
b481de9c
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277 struct list_head *element;
278 if (list_empty(&priv->free_frames)) {
279 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
280 if (!frame) {
15b1687c 281 IWL_ERR(priv, "Could not allocate frame!\n");
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282 return NULL;
283 }
284
285 priv->frames_count++;
286 return frame;
287 }
288
289 element = priv->free_frames.next;
290 list_del(element);
fcab423d 291 return list_entry(element, struct iwl_frame, list);
b481de9c
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292}
293
fcab423d 294static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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295{
296 memset(frame, 0, sizeof(*frame));
297 list_add(&frame->list, &priv->free_frames);
298}
299
4bf64efd
TW
300static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
301 struct ieee80211_hdr *hdr,
73ec1cc2 302 int left)
b481de9c 303{
3109ece1 304 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
305 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
306 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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307 return 0;
308
309 if (priv->ibss_beacon->len > left)
310 return 0;
311
312 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
313
314 return priv->ibss_beacon->len;
315}
316
5b9f8cd3 317static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
318 struct iwl_frame *frame, u8 rate)
319{
320 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
321 unsigned int frame_size;
322
323 tx_beacon_cmd = &frame->u.beacon;
324 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
325
326 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
327 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
328
329 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
330 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
331
332 BUG_ON(frame_size > MAX_MPDU_SIZE);
333 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
334
335 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
336 tx_beacon_cmd->tx.rate_n_flags =
337 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
338 else
339 tx_beacon_cmd->tx.rate_n_flags =
340 iwl_hw_set_rate_n_flags(rate, 0);
341
342 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
343 TX_CMD_FLG_TSF_MSK |
344 TX_CMD_FLG_STA_RATE_MSK;
345
346 return sizeof(*tx_beacon_cmd) + frame_size;
347}
5b9f8cd3 348static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 349{
fcab423d 350 struct iwl_frame *frame;
b481de9c
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351 unsigned int frame_size;
352 int rc;
353 u8 rate;
354
fcab423d 355 frame = iwl_get_free_frame(priv);
b481de9c
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356
357 if (!frame) {
15b1687c 358 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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359 "command.\n");
360 return -ENOMEM;
361 }
362
5b9f8cd3 363 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 364
5b9f8cd3 365 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 366
857485c0 367 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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368 &frame->u.cmd[0]);
369
fcab423d 370 iwl_free_frame(priv, frame);
b481de9c
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371
372 return rc;
373}
374
7aaa1d79
SO
375static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
376{
377 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
378
379 dma_addr_t addr = get_unaligned_le32(&tb->lo);
380 if (sizeof(dma_addr_t) > sizeof(u32))
381 addr |=
382 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
383
384 return addr;
385}
386
387static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
388{
389 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
390
391 return le16_to_cpu(tb->hi_n_len) >> 4;
392}
393
394static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
395 dma_addr_t addr, u16 len)
396{
397 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
398 u16 hi_n_len = len << 4;
399
400 put_unaligned_le32(addr, &tb->lo);
401 if (sizeof(dma_addr_t) > sizeof(u32))
402 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
403
404 tb->hi_n_len = cpu_to_le16(hi_n_len);
405
406 tfd->num_tbs = idx + 1;
407}
408
409static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
410{
411 return tfd->num_tbs & 0x1f;
412}
413
414/**
415 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
416 * @priv - driver private data
417 * @txq - tx queue
418 *
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
421 */
422void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
423{
59606ffa 424 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
425 struct iwl_tfd *tfd;
426 struct pci_dev *dev = priv->pci_dev;
427 int index = txq->q.read_ptr;
428 int i;
429 int num_tbs;
430
431 tfd = &tfd_tmp[index];
432
433 /* Sanity check on number of chunks */
434 num_tbs = iwl_tfd_get_num_tbs(tfd);
435
436 if (num_tbs >= IWL_NUM_OF_TBS) {
437 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
438 /* @todo issue fatal error, it is quite serious situation */
439 return;
440 }
441
442 /* Unmap tx_cmd */
443 if (num_tbs)
444 pci_unmap_single(dev,
445 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
446 pci_unmap_len(&txq->cmd[index]->meta, len),
96891cee 447 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
448
449 /* Unmap chunks, if any. */
450 for (i = 1; i < num_tbs; i++) {
451 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
452 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
453
454 if (txq->txb) {
455 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
456 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
457 }
458 }
459}
460
461int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
462 struct iwl_tx_queue *txq,
463 dma_addr_t addr, u16 len,
464 u8 reset, u8 pad)
465{
466 struct iwl_queue *q;
59606ffa 467 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
468 u32 num_tbs;
469
470 q = &txq->q;
59606ffa
SO
471 tfd_tmp = (struct iwl_tfd *)txq->tfds;
472 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
473
474 if (reset)
475 memset(tfd, 0, sizeof(*tfd));
476
477 num_tbs = iwl_tfd_get_num_tbs(tfd);
478
479 /* Each TFD can point to a maximum 20 Tx buffers */
480 if (num_tbs >= IWL_NUM_OF_TBS) {
481 IWL_ERR(priv, "Error can not send more than %d chunks\n",
482 IWL_NUM_OF_TBS);
483 return -EINVAL;
484 }
485
486 BUG_ON(addr & ~DMA_BIT_MASK(36));
487 if (unlikely(addr & ~IWL_TX_DMA_MASK))
488 IWL_ERR(priv, "Unaligned address = %llx\n",
489 (unsigned long long)addr);
490
491 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
492
493 return 0;
494}
495
a8e74e27
SO
496/*
497 * Tell nic where to find circular buffer of Tx Frame Descriptors for
498 * given Tx queue, and enable the DMA channel used for that queue.
499 *
500 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
501 * channels supported in hardware.
502 */
503int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq)
505{
506 int ret;
507 unsigned long flags;
508 int txq_id = txq->q.id;
509
510 spin_lock_irqsave(&priv->lock, flags);
511 ret = iwl_grab_nic_access(priv);
512 if (ret) {
513 spin_unlock_irqrestore(&priv->lock, flags);
514 return ret;
515 }
516
517 /* Circular buffer (TFD queue in DRAM) physical base address */
518 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
519 txq->q.dma_addr >> 8);
520
521 iwl_release_nic_access(priv);
522 spin_unlock_irqrestore(&priv->lock, flags);
523
524 return 0;
525}
526
527
b481de9c
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528/******************************************************************************
529 *
530 * Misc. internal state and helper functions
531 *
532 ******************************************************************************/
b481de9c 533
b481de9c 534#define MAX_UCODE_BEACON_INTERVAL 4096
b481de9c 535
3195c1f3 536static u16 iwl_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY
537{
538 u16 new_val = 0;
539 u16 beacon_factor = 0;
540
3195c1f3
TW
541 beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
542 / MAX_UCODE_BEACON_INTERVAL;
b481de9c
ZY
543 new_val = beacon_val / beacon_factor;
544
41d2f291
JL
545 if (!new_val)
546 new_val = MAX_UCODE_BEACON_INTERVAL;
547
3195c1f3 548 return new_val;
b481de9c
ZY
549}
550
3195c1f3 551static void iwl_setup_rxon_timing(struct iwl_priv *priv)
b481de9c 552{
3195c1f3
TW
553 u64 tsf;
554 s32 interval_tm, rem;
b481de9c
ZY
555 unsigned long flags;
556 struct ieee80211_conf *conf = NULL;
557 u16 beacon_int = 0;
558
559 conf = ieee80211_get_hw_conf(priv->hw);
560
561 spin_lock_irqsave(&priv->lock, flags);
3195c1f3 562 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b5d7be5e 563 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
b481de9c 564
05c914fe 565 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
3195c1f3 566 beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
b481de9c
ZY
567 priv->rxon_timing.atim_window = 0;
568 } else {
3195c1f3
TW
569 beacon_int = iwl_adjust_beacon_interval(conf->beacon_int);
570
b481de9c
ZY
571 /* TODO: we need to get atim_window from upper stack
572 * for now we set to 0 */
573 priv->rxon_timing.atim_window = 0;
574 }
575
3195c1f3 576 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
b481de9c 577
3195c1f3
TW
578 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
579 interval_tm = beacon_int * 1024;
580 rem = do_div(tsf, interval_tm);
581 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
582
583 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 584 IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
3195c1f3
TW
585 le16_to_cpu(priv->rxon_timing.beacon_interval),
586 le32_to_cpu(priv->rxon_timing.beacon_init_val),
587 le16_to_cpu(priv->rxon_timing.atim_window));
b481de9c
ZY
588}
589
5b9f8cd3 590static int iwl_set_mode(struct iwl_priv *priv, int mode)
b481de9c 591{
5b9f8cd3 592 iwl_connection_init_rx_config(priv, mode);
8ccde88a 593 iwl_set_rxon_chain(priv);
b481de9c
ZY
594 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
595
e11bc028 596 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c 597
fde3571f 598 /* dont commit rxon if rf-kill is on*/
fee1247a 599 if (!iwl_is_ready_rf(priv))
fde3571f
MA
600 return -EAGAIN;
601
602 cancel_delayed_work(&priv->scan_check);
2a421b91 603 if (iwl_scan_cancel_timeout(priv, 100)) {
39aadf8c 604 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
e1623446 605 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
fde3571f
MA
606 return -EAGAIN;
607 }
608
e0158e61 609 iwlcore_commit_rxon(priv);
b481de9c
ZY
610
611 return 0;
612}
613
b481de9c
ZY
614/******************************************************************************
615 *
616 * Generic RX handler implementations
617 *
618 ******************************************************************************/
885ba202
TW
619static void iwl_rx_reply_alive(struct iwl_priv *priv,
620 struct iwl_rx_mem_buffer *rxb)
b481de9c 621{
db11d634 622 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
885ba202 623 struct iwl_alive_resp *palive;
b481de9c
ZY
624 struct delayed_work *pwork;
625
626 palive = &pkt->u.alive_frame;
627
e1623446 628 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
629 "0x%01X 0x%01X\n",
630 palive->is_valid, palive->ver_type,
631 palive->ver_subtype);
632
633 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 634 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
635 memcpy(&priv->card_alive_init,
636 &pkt->u.alive_frame,
885ba202 637 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
638 pwork = &priv->init_alive_start;
639 } else {
e1623446 640 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 641 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 642 sizeof(struct iwl_alive_resp));
b481de9c
ZY
643 pwork = &priv->alive_start;
644 }
645
646 /* We delay the ALIVE response by 5ms to
647 * give the HW RF Kill time to activate... */
648 if (palive->is_valid == UCODE_VALID_OK)
649 queue_delayed_work(priv->workqueue, pwork,
650 msecs_to_jiffies(5));
651 else
39aadf8c 652 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
653}
654
5b9f8cd3 655static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 656{
c79dd5b5
TW
657 struct iwl_priv *priv =
658 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
659 struct sk_buff *beacon;
660
661 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 662 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
663
664 if (!beacon) {
15b1687c 665 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
666 return;
667 }
668
669 mutex_lock(&priv->mutex);
670 /* new beacon skb is allocated every time; dispose previous.*/
671 if (priv->ibss_beacon)
672 dev_kfree_skb(priv->ibss_beacon);
673
674 priv->ibss_beacon = beacon;
675 mutex_unlock(&priv->mutex);
676
5b9f8cd3 677 iwl_send_beacon_cmd(priv);
b481de9c
ZY
678}
679
4e39317d 680/**
5b9f8cd3 681 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
682 *
683 * This callback is provided in order to send a statistics request.
684 *
685 * This timer function is continually reset to execute within
686 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
687 * was received. We need to ensure we receive the statistics in order
688 * to update the temperature used for calibrating the TXPOWER.
689 */
5b9f8cd3 690static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
691{
692 struct iwl_priv *priv = (struct iwl_priv *)data;
693
694 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
695 return;
696
61780ee3
MA
697 /* dont send host command if rf-kill is on */
698 if (!iwl_is_ready_rf(priv))
699 return;
700
4e39317d
EG
701 iwl_send_statistics_request(priv, CMD_ASYNC);
702}
703
5b9f8cd3 704static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 705 struct iwl_rx_mem_buffer *rxb)
b481de9c 706{
0a6857e7 707#ifdef CONFIG_IWLWIFI_DEBUG
db11d634 708 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86
TW
709 struct iwl4965_beacon_notif *beacon =
710 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 711 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 712
e1623446 713 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 714 "tsf %d %d rate %d\n",
25a6572c 715 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
716 beacon->beacon_notify_hdr.failure_frame,
717 le32_to_cpu(beacon->ibss_mgr_status),
718 le32_to_cpu(beacon->high_tsf),
719 le32_to_cpu(beacon->low_tsf), rate);
720#endif
721
05c914fe 722 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
723 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
724 queue_work(priv->workqueue, &priv->beacon_update);
725}
726
b481de9c
ZY
727/* Handle notification from uCode that card's power state is changing
728 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 729static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 730 struct iwl_rx_mem_buffer *rxb)
b481de9c 731{
db11d634 732 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
733 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
734 unsigned long status = priv->status;
735
e1623446 736 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
737 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
738 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
739
740 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
741 RF_CARD_DISABLED)) {
742
3395f6e9 743 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
744 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
745
3395f6e9
TW
746 if (!iwl_grab_nic_access(priv)) {
747 iwl_write_direct32(
b481de9c
ZY
748 priv, HBUS_TARG_MBX_C,
749 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
750
3395f6e9 751 iwl_release_nic_access(priv);
b481de9c
ZY
752 }
753
754 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 755 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 756 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3395f6e9
TW
757 if (!iwl_grab_nic_access(priv)) {
758 iwl_write_direct32(
b481de9c
ZY
759 priv, HBUS_TARG_MBX_C,
760 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
761
3395f6e9 762 iwl_release_nic_access(priv);
b481de9c
ZY
763 }
764 }
765
766 if (flags & RF_CARD_DISABLED) {
3395f6e9 767 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c 768 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
3395f6e9
TW
769 iwl_read32(priv, CSR_UCODE_DRV_GP1);
770 if (!iwl_grab_nic_access(priv))
771 iwl_release_nic_access(priv);
b481de9c
ZY
772 }
773 }
774
775 if (flags & HW_CARD_DISABLED)
776 set_bit(STATUS_RF_KILL_HW, &priv->status);
777 else
778 clear_bit(STATUS_RF_KILL_HW, &priv->status);
779
780
781 if (flags & SW_CARD_DISABLED)
782 set_bit(STATUS_RF_KILL_SW, &priv->status);
783 else
784 clear_bit(STATUS_RF_KILL_SW, &priv->status);
785
786 if (!(flags & RXON_CARD_DISABLED))
2a421b91 787 iwl_scan_cancel(priv);
b481de9c
ZY
788
789 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
790 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
791 (test_bit(STATUS_RF_KILL_SW, &status) !=
792 test_bit(STATUS_RF_KILL_SW, &priv->status)))
793 queue_work(priv->workqueue, &priv->rf_kill);
794 else
795 wake_up_interruptible(&priv->wait_command_queue);
796}
797
5b9f8cd3 798int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b
TW
799{
800 int ret;
801 unsigned long flags;
802
803 spin_lock_irqsave(&priv->lock, flags);
804 ret = iwl_grab_nic_access(priv);
805 if (ret)
806 goto err;
807
808 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 809 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
810 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
811 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
812 ~APMG_PS_CTRL_MSK_PWR_SRC);
813 } else {
814 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
815 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
816 ~APMG_PS_CTRL_MSK_PWR_SRC);
817 }
818
819 iwl_release_nic_access(priv);
820err:
821 spin_unlock_irqrestore(&priv->lock, flags);
822 return ret;
823}
824
b481de9c 825/**
5b9f8cd3 826 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
827 *
828 * Setup the RX handlers for each of the reply types sent from the uCode
829 * to the host.
830 *
831 * This function chains into the hardware specific files for them to setup
832 * any hardware specific handlers as well.
833 */
653fa4a0 834static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 835{
885ba202 836 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
837 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
838 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 839 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 840 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
841 iwl_rx_pm_debug_statistics_notif;
842 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 843
9fbab516
BC
844 /*
845 * The same handler is used for both the REPLY to a discrete
846 * statistics request from the host as well as for the periodic
847 * statistics notifications (after received beacons) from the uCode.
b481de9c 848 */
8f91aecb
EG
849 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
850 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 851
21c339bf 852 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
853 iwl_setup_rx_scan_handlers(priv);
854
37a44211 855 /* status change handler */
5b9f8cd3 856 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 857
c1354754
TW
858 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
859 iwl_rx_missed_beacon_notif;
37a44211 860 /* Rx handlers */
1781a07f
EG
861 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
862 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
863 /* block ack */
864 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 865 /* Set up hardware specific Rx handlers */
d4789efe 866 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
867}
868
b481de9c 869/**
a55360e4 870 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
871 *
872 * Uses the priv->rx_handlers callback function array to invoke
873 * the appropriate handlers, including command responses,
874 * frame-received notifications, and other notifications.
875 */
a55360e4 876void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 877{
a55360e4 878 struct iwl_rx_mem_buffer *rxb;
db11d634 879 struct iwl_rx_packet *pkt;
a55360e4 880 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
881 u32 r, i;
882 int reclaim;
883 unsigned long flags;
5c0eef96 884 u8 fill_rx = 0;
d68ab680 885 u32 count = 8;
b481de9c 886
6440adb5
BC
887 /* uCode's read index (stored in shared DRAM) indicates the last Rx
888 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 889 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
890 i = rxq->read;
891
892 /* Rx interrupt, but nothing sent from uCode */
893 if (i == r)
e1623446 894 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 895
a55360e4 896 if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
897 fill_rx = 1;
898
b481de9c
ZY
899 while (i != r) {
900 rxb = rxq->queue[i];
901
9fbab516 902 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
903 * then a bug has been introduced in the queue refilling
904 * routines -- catch it here */
905 BUG_ON(rxb == NULL);
906
907 rxq->queue[i] = NULL;
908
e91af0af
JB
909 dma_sync_single_range_for_cpu(
910 &priv->pci_dev->dev, rxb->real_dma_addr,
911 rxb->aligned_dma_addr - rxb->real_dma_addr,
912 priv->hw_params.rx_buf_size,
913 PCI_DMA_FROMDEVICE);
db11d634 914 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
915
916 /* Reclaim a command buffer only if this packet is a response
917 * to a (driver-originated) command.
918 * If the packet (e.g. Rx frame) originated from uCode,
919 * there is no command buffer to reclaim.
920 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
921 * but apparently a few don't get set; catch them here. */
922 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
923 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 924 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 925 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 926 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
927 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
928 (pkt->hdr.cmd != REPLY_TX);
929
930 /* Based on type of command response or notification,
931 * handle those that need handling via function in
5b9f8cd3 932 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 933 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 934 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 935 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
b481de9c
ZY
936 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
937 } else {
938 /* No handling needed */
e1623446 939 IWL_DEBUG_RX(priv,
b481de9c
ZY
940 "r %d i %d No handler needed for %s, 0x%02x\n",
941 r, i, get_cmd_string(pkt->hdr.cmd),
942 pkt->hdr.cmd);
943 }
944
945 if (reclaim) {
9fbab516 946 /* Invoke any callbacks, transfer the skb to caller, and
857485c0 947 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
948 * as we reclaim the driver command queue */
949 if (rxb && rxb->skb)
17b88929 950 iwl_tx_cmd_complete(priv, rxb);
b481de9c 951 else
39aadf8c 952 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
953 }
954
955 /* For now we just don't re-use anything. We can tweak this
956 * later to try and re-use notification packets and SKBs that
957 * fail to Rx correctly */
958 if (rxb->skb != NULL) {
959 priv->alloc_rxb_skb--;
960 dev_kfree_skb_any(rxb->skb);
961 rxb->skb = NULL;
962 }
963
4018517a
JB
964 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
965 priv->hw_params.rx_buf_size + 256,
9ee1ba47 966 PCI_DMA_FROMDEVICE);
b481de9c
ZY
967 spin_lock_irqsave(&rxq->lock, flags);
968 list_add_tail(&rxb->list, &priv->rxq.rx_used);
969 spin_unlock_irqrestore(&rxq->lock, flags);
970 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
971 /* If there are a lot of unused frames,
972 * restock the Rx queue so ucode wont assert. */
973 if (fill_rx) {
974 count++;
975 if (count >= 8) {
976 priv->rxq.read = i;
f1bc4ac6 977 iwl_rx_queue_restock(priv);
5c0eef96
MA
978 count = 0;
979 }
980 }
b481de9c
ZY
981 }
982
983 /* Backtrack one entry */
984 priv->rxq.read = i;
a55360e4
TW
985 iwl_rx_queue_restock(priv);
986}
a55360e4 987
0359facc
MA
988/* call this function to flush any scheduled tasklet */
989static inline void iwl_synchronize_irq(struct iwl_priv *priv)
990{
a96a27f9 991 /* wait to make sure we flush pending tasklet*/
0359facc
MA
992 synchronize_irq(priv->pci_dev->irq);
993 tasklet_kill(&priv->irq_tasklet);
994}
995
5b9f8cd3 996static void iwl_error_recovery(struct iwl_priv *priv)
b481de9c
ZY
997{
998 unsigned long flags;
999
1000 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
1001 sizeof(priv->staging_rxon));
1002 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 1003 iwlcore_commit_rxon(priv);
b481de9c 1004
4f40e4d9 1005 iwl_rxon_add_station(priv, priv->bssid, 1);
b481de9c
ZY
1006
1007 spin_lock_irqsave(&priv->lock, flags);
1008 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
1009 priv->error_recovering = 0;
1010 spin_unlock_irqrestore(&priv->lock, flags);
1011}
1012
5b9f8cd3 1013static void iwl_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1014{
1015 u32 inta, handled = 0;
1016 u32 inta_fh;
1017 unsigned long flags;
0a6857e7 1018#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1019 u32 inta_mask;
1020#endif
1021
1022 spin_lock_irqsave(&priv->lock, flags);
1023
1024 /* Ack/clear/reset pending uCode interrupts.
1025 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1026 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
1027 inta = iwl_read32(priv, CSR_INT);
1028 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1029
1030 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1031 * Any new interrupts that happen after this, either while we're
1032 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
1033 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1034 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1035
0a6857e7 1036#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1037 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 1038 /* just for debug */
3395f6e9 1039 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1040 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1041 inta, inta_mask, inta_fh);
1042 }
1043#endif
1044
1045 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1046 * atomic, make sure that inta covers all the interrupts that
1047 * we've discovered, even if FH interrupt came in just after
1048 * reading CSR_INT. */
6f83eaa1 1049 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1050 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1051 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
1052 inta |= CSR_INT_BIT_FH_TX;
1053
1054 /* Now service all interrupt bits discovered above. */
1055 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 1056 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY
1057
1058 /* Tell the device to stop sending interrupts */
5b9f8cd3 1059 iwl_disable_interrupts(priv);
b481de9c 1060
5b9f8cd3 1061 iwl_irq_handle_error(priv);
b481de9c
ZY
1062
1063 handled |= CSR_INT_BIT_HW_ERR;
1064
1065 spin_unlock_irqrestore(&priv->lock, flags);
1066
1067 return;
1068 }
1069
0a6857e7 1070#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1071 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 1072 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e 1073 if (inta & CSR_INT_BIT_SCD)
e1623446 1074 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1075 "the frame/frames.\n");
b481de9c
ZY
1076
1077 /* Alive notification via Rx interrupt will do the real work */
1078 if (inta & CSR_INT_BIT_ALIVE)
e1623446 1079 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
b481de9c
ZY
1080 }
1081#endif
1082 /* Safely ignore these bits for debug checks below */
25c03d8e 1083 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1084
9fbab516 1085 /* HW RF KILL switch toggled */
b481de9c
ZY
1086 if (inta & CSR_INT_BIT_RF_KILL) {
1087 int hw_rf_kill = 0;
3395f6e9 1088 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1089 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1090 hw_rf_kill = 1;
1091
e1623446 1092 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1093 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1094
a9efa652 1095 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1096 * the driver allows loading the ucode even if the radio
1097 * is killed. Hence update the killswitch state here. The
1098 * rfkill handler will care about restarting if needed.
a9efa652 1099 */
6cd0b1cb
HS
1100 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1101 if (hw_rf_kill)
1102 set_bit(STATUS_RF_KILL_HW, &priv->status);
1103 else
1104 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1105 queue_work(priv->workqueue, &priv->rf_kill);
edb34228 1106 }
b481de9c
ZY
1107
1108 handled |= CSR_INT_BIT_RF_KILL;
1109 }
1110
9fbab516 1111 /* Chip got too hot and stopped itself */
b481de9c 1112 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1113 IWL_ERR(priv, "Microcode CT kill error detected.\n");
b481de9c
ZY
1114 handled |= CSR_INT_BIT_CT_KILL;
1115 }
1116
1117 /* Error detected by uCode */
1118 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1119 IWL_ERR(priv, "Microcode SW error detected. "
1120 " Restarting 0x%X.\n", inta);
5b9f8cd3 1121 iwl_irq_handle_error(priv);
b481de9c
ZY
1122 handled |= CSR_INT_BIT_SW_ERR;
1123 }
1124
1125 /* uCode wakes up after power-down sleep */
1126 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1127 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1128 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
babcebfa
TW
1129 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1130 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1131 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1132 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1133 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1134 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY
1135
1136 handled |= CSR_INT_BIT_WAKEUP;
1137 }
1138
1139 /* All uCode command responses, including Tx command responses,
1140 * Rx "responses" (frame-received notification), and other
1141 * notifications from uCode come through here*/
1142 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1143 iwl_rx_handle(priv);
b481de9c
ZY
1144 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1145 }
1146
1147 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1148 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
b481de9c 1149 handled |= CSR_INT_BIT_FH_TX;
dbb983b7
RR
1150 /* FH finished to write, send event */
1151 priv->ucode_write_complete = 1;
1152 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1153 }
1154
1155 if (inta & ~handled)
15b1687c 1156 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
b481de9c
ZY
1157
1158 if (inta & ~CSR_INI_SET_MASK) {
39aadf8c 1159 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
b481de9c 1160 inta & ~CSR_INI_SET_MASK);
39aadf8c 1161 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1162 }
1163
1164 /* Re-enable all interrupts */
0359facc
MA
1165 /* only Re-enable if diabled by irq */
1166 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1167 iwl_enable_interrupts(priv);
b481de9c 1168
0a6857e7 1169#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1170 if (priv->debug_level & (IWL_DL_ISR)) {
3395f6e9
TW
1171 inta = iwl_read32(priv, CSR_INT);
1172 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1173 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1174 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1175 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1176 }
1177#endif
1178 spin_unlock_irqrestore(&priv->lock, flags);
1179}
1180
b481de9c
ZY
1181/******************************************************************************
1182 *
1183 * uCode download functions
1184 *
1185 ******************************************************************************/
1186
5b9f8cd3 1187static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1188{
98c92211
TW
1189 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1190 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1191 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1192 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1193 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1194 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1195}
1196
5b9f8cd3 1197static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1198{
1199 /* Remove all resets to allow NIC to operate */
1200 iwl_write32(priv, CSR_RESET, 0);
1201}
1202
1203
b481de9c 1204/**
5b9f8cd3 1205 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1206 *
1207 * Copy into buffers for card to fetch via bus-mastering
1208 */
5b9f8cd3 1209static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1210{
14b3d338 1211 struct iwl_ucode *ucode;
a0987a8d 1212 int ret = -EINVAL, index;
b481de9c 1213 const struct firmware *ucode_raw;
a0987a8d
RC
1214 const char *name_pre = priv->cfg->fw_name_pre;
1215 const unsigned int api_max = priv->cfg->ucode_api_max;
1216 const unsigned int api_min = priv->cfg->ucode_api_min;
1217 char buf[25];
b481de9c
ZY
1218 u8 *src;
1219 size_t len;
a0987a8d 1220 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
1221
1222 /* Ask kernel firmware_class module to get the boot firmware off disk.
1223 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1224 for (index = api_max; index >= api_min; index--) {
1225 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1226 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1227 if (ret < 0) {
15b1687c 1228 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1229 buf, ret);
1230 if (ret == -ENOENT)
1231 continue;
1232 else
1233 goto error;
1234 } else {
1235 if (index < api_max)
15b1687c
WT
1236 IWL_ERR(priv, "Loaded firmware %s, "
1237 "which is deprecated. "
1238 "Please use API v%u instead.\n",
a0987a8d 1239 buf, api_max);
15b1687c 1240
e1623446 1241 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1242 buf, ucode_raw->size);
1243 break;
1244 }
b481de9c
ZY
1245 }
1246
a0987a8d
RC
1247 if (ret < 0)
1248 goto error;
b481de9c
ZY
1249
1250 /* Make sure that we got at least our header! */
1251 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 1252 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1253 ret = -EINVAL;
b481de9c
ZY
1254 goto err_release;
1255 }
1256
1257 /* Data from ucode file: header followed by uCode images */
1258 ucode = (void *)ucode_raw->data;
1259
c02b3acd 1260 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1261 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY
1262 inst_size = le32_to_cpu(ucode->inst_size);
1263 data_size = le32_to_cpu(ucode->data_size);
1264 init_size = le32_to_cpu(ucode->init_size);
1265 init_data_size = le32_to_cpu(ucode->init_data_size);
1266 boot_size = le32_to_cpu(ucode->boot_size);
1267
a0987a8d
RC
1268 /* api_ver should match the api version forming part of the
1269 * firmware filename ... but we don't check for that and only rely
877d0310 1270 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1271
1272 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1273 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1274 "Driver supports v%u, firmware is v%u.\n",
1275 api_max, api_ver);
1276 priv->ucode_ver = 0;
1277 ret = -EINVAL;
1278 goto err_release;
1279 }
1280 if (api_ver != api_max)
978785a3 1281 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1282 "got v%u. New firmware can be obtained "
1283 "from http://www.intellinuxwireless.org.\n",
1284 api_max, api_ver);
1285
978785a3
TW
1286 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1287 IWL_UCODE_MAJOR(priv->ucode_ver),
1288 IWL_UCODE_MINOR(priv->ucode_ver),
1289 IWL_UCODE_API(priv->ucode_ver),
1290 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1291
e1623446 1292 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1293 priv->ucode_ver);
e1623446 1294 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1295 inst_size);
e1623446 1296 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1297 data_size);
e1623446 1298 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1299 init_size);
e1623446 1300 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1301 init_data_size);
e1623446 1302 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1303 boot_size);
1304
1305 /* Verify size of file vs. image size info in file's header */
1306 if (ucode_raw->size < sizeof(*ucode) +
1307 inst_size + data_size + init_size +
1308 init_data_size + boot_size) {
1309
e1623446 1310 IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
b481de9c 1311 (int)ucode_raw->size);
90e759d1 1312 ret = -EINVAL;
b481de9c
ZY
1313 goto err_release;
1314 }
1315
1316 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1317 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1318 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1319 inst_size);
1320 ret = -EINVAL;
b481de9c
ZY
1321 goto err_release;
1322 }
1323
099b40b7 1324 if (data_size > priv->hw_params.max_data_size) {
e1623446 1325 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1326 data_size);
1327 ret = -EINVAL;
b481de9c
ZY
1328 goto err_release;
1329 }
099b40b7 1330 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1331 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1332 init_size);
90e759d1 1333 ret = -EINVAL;
b481de9c
ZY
1334 goto err_release;
1335 }
099b40b7 1336 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1337 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1338 init_data_size);
1339 ret = -EINVAL;
b481de9c
ZY
1340 goto err_release;
1341 }
099b40b7 1342 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1343 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1344 boot_size);
90e759d1 1345 ret = -EINVAL;
b481de9c
ZY
1346 goto err_release;
1347 }
1348
1349 /* Allocate ucode buffers for card's bus-master loading ... */
1350
1351 /* Runtime instructions and 2 copies of data:
1352 * 1) unmodified from disk
1353 * 2) backup cache for save/restore during power-downs */
1354 priv->ucode_code.len = inst_size;
98c92211 1355 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1356
1357 priv->ucode_data.len = data_size;
98c92211 1358 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1359
1360 priv->ucode_data_backup.len = data_size;
98c92211 1361 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1362
1f304e4e
ZY
1363 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1364 !priv->ucode_data_backup.v_addr)
1365 goto err_pci_alloc;
1366
b481de9c 1367 /* Initialization instructions and data */
90e759d1
TW
1368 if (init_size && init_data_size) {
1369 priv->ucode_init.len = init_size;
98c92211 1370 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1371
1372 priv->ucode_init_data.len = init_data_size;
98c92211 1373 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1374
1375 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1376 goto err_pci_alloc;
1377 }
b481de9c
ZY
1378
1379 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1380 if (boot_size) {
1381 priv->ucode_boot.len = boot_size;
98c92211 1382 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1383
90e759d1
TW
1384 if (!priv->ucode_boot.v_addr)
1385 goto err_pci_alloc;
1386 }
b481de9c
ZY
1387
1388 /* Copy images into buffers for card's bus-master reads ... */
1389
1390 /* Runtime instructions (first block of data in file) */
1391 src = &ucode->data[0];
1392 len = priv->ucode_code.len;
e1623446 1393 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1394 memcpy(priv->ucode_code.v_addr, src, len);
e1623446 1395 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1396 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1397
1398 /* Runtime data (2nd block)
5b9f8cd3 1399 * NOTE: Copy into backup buffer will be done in iwl_up() */
b481de9c
ZY
1400 src = &ucode->data[inst_size];
1401 len = priv->ucode_data.len;
e1623446 1402 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1403 memcpy(priv->ucode_data.v_addr, src, len);
1404 memcpy(priv->ucode_data_backup.v_addr, src, len);
1405
1406 /* Initialization instructions (3rd block) */
1407 if (init_size) {
1408 src = &ucode->data[inst_size + data_size];
1409 len = priv->ucode_init.len;
e1623446 1410 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1411 len);
b481de9c
ZY
1412 memcpy(priv->ucode_init.v_addr, src, len);
1413 }
1414
1415 /* Initialization data (4th block) */
1416 if (init_data_size) {
1417 src = &ucode->data[inst_size + data_size + init_size];
1418 len = priv->ucode_init_data.len;
e1623446 1419 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1420 len);
b481de9c
ZY
1421 memcpy(priv->ucode_init_data.v_addr, src, len);
1422 }
1423
1424 /* Bootstrap instructions (5th block) */
1425 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
1426 len = priv->ucode_boot.len;
e1623446 1427 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1428 memcpy(priv->ucode_boot.v_addr, src, len);
1429
1430 /* We have our copies now, allow OS release its copies */
1431 release_firmware(ucode_raw);
1432 return 0;
1433
1434 err_pci_alloc:
15b1687c 1435 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1436 ret = -ENOMEM;
5b9f8cd3 1437 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1438
1439 err_release:
1440 release_firmware(ucode_raw);
1441
1442 error:
90e759d1 1443 return ret;
b481de9c
ZY
1444}
1445
b481de9c 1446/**
4a4a9e81 1447 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1448 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1449 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1450 */
4a4a9e81 1451static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1452{
57aab75a 1453 int ret = 0;
b481de9c 1454
e1623446 1455 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1456
1457 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1458 /* We had an error bringing up the hardware, so take it
1459 * all the way back down so we can try again */
e1623446 1460 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1461 goto restart;
1462 }
1463
1464 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1465 * This is a paranoid check, because we would not have gotten the
1466 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1467 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1468 /* Runtime instruction load was bad;
1469 * take it all the way back down so we can try again */
e1623446 1470 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1471 goto restart;
1472 }
1473
e11bc028 1474 priv->cfg->ops->smgmt->clear_station_table(priv);
57aab75a
TW
1475 ret = priv->cfg->ops->lib->alive_notify(priv);
1476 if (ret) {
39aadf8c
WT
1477 IWL_WARN(priv,
1478 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1479 goto restart;
1480 }
1481
5b9f8cd3 1482 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1483 set_bit(STATUS_ALIVE, &priv->status);
1484
fee1247a 1485 if (iwl_is_rfkill(priv))
b481de9c
ZY
1486 return;
1487
36d6825b 1488 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1489
1490 priv->active_rate = priv->rates_mask;
1491 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1492
3109ece1 1493 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1494 struct iwl_rxon_cmd *active_rxon =
1495 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1496 /* apply any changes in staging */
1497 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1498 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1499 } else {
1500 /* Initialize our rx_config data */
5b9f8cd3 1501 iwl_connection_init_rx_config(priv, priv->iw_mode);
8ccde88a 1502 iwl_set_rxon_chain(priv);
b481de9c
ZY
1503 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1504 }
1505
9fbab516 1506 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1507 iwl_send_bt_config(priv);
b481de9c 1508
4a4a9e81
TW
1509 iwl_reset_run_time_calib(priv);
1510
b481de9c 1511 /* Configure the adapter for unassociated operation */
e0158e61 1512 iwlcore_commit_rxon(priv);
b481de9c
ZY
1513
1514 /* At this point, the NIC is initialized and operational */
47f4a587 1515 iwl_rf_kill_ct_config(priv);
5a66926a 1516
fe00b5a5
RC
1517 iwl_leds_register(priv);
1518
e1623446 1519 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1520 set_bit(STATUS_READY, &priv->status);
5a66926a 1521 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1522
1523 if (priv->error_recovering)
5b9f8cd3 1524 iwl_error_recovery(priv);
b481de9c 1525
58d0f361 1526 iwl_power_update_mode(priv, 1);
c46fbefa 1527
ada17513
MA
1528 /* reassociate for ADHOC mode */
1529 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1530 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1531 priv->vif);
1532 if (beacon)
1533 iwl_mac_beacon_update(priv->hw, beacon);
1534 }
1535
1536
c46fbefa 1537 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1538 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1539
b481de9c
ZY
1540 return;
1541
1542 restart:
1543 queue_work(priv->workqueue, &priv->restart);
1544}
1545
4e39317d 1546static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1547
5b9f8cd3 1548static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1549{
1550 unsigned long flags;
1551 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1552
e1623446 1553 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1554
b481de9c
ZY
1555 if (!exit_pending)
1556 set_bit(STATUS_EXIT_PENDING, &priv->status);
1557
ab53d8af
MA
1558 iwl_leds_unregister(priv);
1559
e11bc028 1560 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c
ZY
1561
1562 /* Unblock any waiting calls */
1563 wake_up_interruptible_all(&priv->wait_command_queue);
1564
b481de9c
ZY
1565 /* Wipe out the EXIT_PENDING status bit if we are not actually
1566 * exiting the module */
1567 if (!exit_pending)
1568 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1569
1570 /* stop and reset the on-board processor */
3395f6e9 1571 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1572
1573 /* tell the device to stop sending interrupts */
0359facc 1574 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1575 iwl_disable_interrupts(priv);
0359facc
MA
1576 spin_unlock_irqrestore(&priv->lock, flags);
1577 iwl_synchronize_irq(priv);
b481de9c
ZY
1578
1579 if (priv->mac80211_registered)
1580 ieee80211_stop_queues(priv->hw);
1581
5b9f8cd3 1582 /* If we have not previously called iwl_init() then
6da3a13e 1583 * clear all bits but the RF Kill bits and return */
fee1247a 1584 if (!iwl_is_init(priv)) {
b481de9c
ZY
1585 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1586 STATUS_RF_KILL_HW |
1587 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1588 STATUS_RF_KILL_SW |
9788864e
RC
1589 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1590 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1591 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1592 STATUS_EXIT_PENDING;
b481de9c
ZY
1593 goto exit;
1594 }
1595
6da3a13e
WYG
1596 /* ...otherwise clear out all the status bits but the RF Kill
1597 * bits and continue taking the NIC down. */
b481de9c
ZY
1598 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1599 STATUS_RF_KILL_HW |
1600 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1601 STATUS_RF_KILL_SW |
9788864e
RC
1602 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1603 STATUS_GEO_CONFIGURED |
b481de9c 1604 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1605 STATUS_FW_ERROR |
1606 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1607 STATUS_EXIT_PENDING;
b481de9c
ZY
1608
1609 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1610 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1611 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1612 spin_unlock_irqrestore(&priv->lock, flags);
1613
da1bc453 1614 iwl_txq_ctx_stop(priv);
b3bbacb7 1615 iwl_rxq_stop(priv);
b481de9c
ZY
1616
1617 spin_lock_irqsave(&priv->lock, flags);
3395f6e9
TW
1618 if (!iwl_grab_nic_access(priv)) {
1619 iwl_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 1620 APMG_CLK_VAL_DMA_CLK_RQT);
3395f6e9 1621 iwl_release_nic_access(priv);
b481de9c
ZY
1622 }
1623 spin_unlock_irqrestore(&priv->lock, flags);
1624
1625 udelay(5);
1626
7f066108 1627 /* FIXME: apm_ops.suspend(priv) */
6da3a13e 1628 if (exit_pending)
d535311e
GG
1629 priv->cfg->ops->lib->apm_ops.stop(priv);
1630 else
1631 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 1632 exit:
885ba202 1633 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1634
1635 if (priv->ibss_beacon)
1636 dev_kfree_skb(priv->ibss_beacon);
1637 priv->ibss_beacon = NULL;
1638
1639 /* clear out any free frames */
fcab423d 1640 iwl_clear_free_frames(priv);
b481de9c
ZY
1641}
1642
5b9f8cd3 1643static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1644{
1645 mutex_lock(&priv->mutex);
5b9f8cd3 1646 __iwl_down(priv);
b481de9c 1647 mutex_unlock(&priv->mutex);
b24d22b1 1648
4e39317d 1649 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1650}
1651
1652#define MAX_HW_RESTARTS 5
1653
5b9f8cd3 1654static int __iwl_up(struct iwl_priv *priv)
b481de9c 1655{
57aab75a
TW
1656 int i;
1657 int ret;
b481de9c
ZY
1658
1659 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 1660 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
1661 return -EIO;
1662 }
1663
e903fbd4 1664 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 1665 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
1666 return -EIO;
1667 }
1668
e655b9f0 1669 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 1670 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 1671 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1672 else
e655b9f0 1673 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1674
c1842d61 1675 if (iwl_is_rfkill(priv)) {
5b9f8cd3 1676 iwl_enable_interrupts(priv);
39aadf8c 1677 IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
3bff19c2 1678 test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
c1842d61 1679 return 0;
b481de9c
ZY
1680 }
1681
3395f6e9 1682 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 1683
1053d35f 1684 ret = iwl_hw_nic_init(priv);
57aab75a 1685 if (ret) {
15b1687c 1686 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 1687 return ret;
b481de9c
ZY
1688 }
1689
1690 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
1691 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1692 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
1693 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1694
1695 /* clear (again), then enable host interrupts */
3395f6e9 1696 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 1697 iwl_enable_interrupts(priv);
b481de9c
ZY
1698
1699 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
1700 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1701 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
1702
1703 /* Copy original ucode data image from disk into backup cache.
1704 * This will be used to initialize the on-board processor's
1705 * data SRAM for a clean start when the runtime program first loads. */
1706 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 1707 priv->ucode_data.len);
b481de9c 1708
b481de9c
ZY
1709 for (i = 0; i < MAX_HW_RESTARTS; i++) {
1710
e11bc028 1711 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c
ZY
1712
1713 /* load bootstrap state machine,
1714 * load bootstrap program into processor's memory,
1715 * prepare to load the "initialize" uCode */
57aab75a 1716 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 1717
57aab75a 1718 if (ret) {
15b1687c
WT
1719 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
1720 ret);
b481de9c
ZY
1721 continue;
1722 }
1723
f3d5b45b
EG
1724 /* Clear out the uCode error bit if it is set */
1725 clear_bit(STATUS_FW_ERROR, &priv->status);
1726
b481de9c 1727 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 1728 iwl_nic_start(priv);
b481de9c 1729
e1623446 1730 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
1731
1732 return 0;
1733 }
1734
1735 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 1736 __iwl_down(priv);
64e72c3e 1737 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
1738
1739 /* tried to restart and config the device for as long as our
1740 * patience could withstand */
15b1687c 1741 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
1742 return -EIO;
1743}
1744
1745
1746/*****************************************************************************
1747 *
1748 * Workqueue callbacks
1749 *
1750 *****************************************************************************/
1751
4a4a9e81 1752static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 1753{
c79dd5b5
TW
1754 struct iwl_priv *priv =
1755 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
1756
1757 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1758 return;
1759
1760 mutex_lock(&priv->mutex);
f3ccc08c 1761 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
1762 mutex_unlock(&priv->mutex);
1763}
1764
4a4a9e81 1765static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 1766{
c79dd5b5
TW
1767 struct iwl_priv *priv =
1768 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
1769
1770 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1771 return;
1772
1773 mutex_lock(&priv->mutex);
4a4a9e81 1774 iwl_alive_start(priv);
b481de9c
ZY
1775 mutex_unlock(&priv->mutex);
1776}
1777
16e727e8
EG
1778static void iwl_bg_run_time_calib_work(struct work_struct *work)
1779{
1780 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1781 run_time_calib_work);
1782
1783 mutex_lock(&priv->mutex);
1784
1785 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1786 test_bit(STATUS_SCANNING, &priv->status)) {
1787 mutex_unlock(&priv->mutex);
1788 return;
1789 }
1790
1791 if (priv->start_calib) {
1792 iwl_chain_noise_calibration(priv, &priv->statistics);
1793
1794 iwl_sensitivity_calibration(priv, &priv->statistics);
1795 }
1796
1797 mutex_unlock(&priv->mutex);
1798 return;
1799}
1800
5b9f8cd3 1801static void iwl_bg_up(struct work_struct *data)
b481de9c 1802{
c79dd5b5 1803 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
1804
1805 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1806 return;
1807
1808 mutex_lock(&priv->mutex);
5b9f8cd3 1809 __iwl_up(priv);
b481de9c 1810 mutex_unlock(&priv->mutex);
80fcc9e2 1811 iwl_rfkill_set_hw_state(priv);
b481de9c
ZY
1812}
1813
5b9f8cd3 1814static void iwl_bg_restart(struct work_struct *data)
b481de9c 1815{
c79dd5b5 1816 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
1817
1818 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1819 return;
1820
5b9f8cd3 1821 iwl_down(priv);
b481de9c
ZY
1822 queue_work(priv->workqueue, &priv->up);
1823}
1824
5b9f8cd3 1825static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 1826{
c79dd5b5
TW
1827 struct iwl_priv *priv =
1828 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
1829
1830 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1831 return;
1832
1833 mutex_lock(&priv->mutex);
a55360e4 1834 iwl_rx_replenish(priv);
b481de9c
ZY
1835 mutex_unlock(&priv->mutex);
1836}
1837
7878a5a4
MA
1838#define IWL_DELAY_NEXT_SCAN (HZ*2)
1839
5bbe233b 1840void iwl_post_associate(struct iwl_priv *priv)
b481de9c 1841{
b481de9c 1842 struct ieee80211_conf *conf = NULL;
857485c0 1843 int ret = 0;
1ff50bda 1844 unsigned long flags;
b481de9c 1845
05c914fe 1846 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 1847 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
1848 return;
1849 }
1850
e1623446 1851 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 1852 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
1853
1854
1855 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1856 return;
1857
b481de9c 1858
508e32e1 1859 if (!priv->vif || !priv->is_open)
948c171c 1860 return;
508e32e1 1861
c90a74ba 1862 iwl_power_cancel_timeout(priv);
2a421b91 1863 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 1864
b481de9c
ZY
1865 conf = ieee80211_get_hw_conf(priv->hw);
1866
1867 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 1868 iwlcore_commit_rxon(priv);
b481de9c 1869
3195c1f3 1870 iwl_setup_rxon_timing(priv);
857485c0 1871 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 1872 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 1873 if (ret)
39aadf8c 1874 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
1875 "Attempting to continue.\n");
1876
1877 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
1878
42eb7c64 1879 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 1880
c7de35cd 1881 iwl_set_rxon_chain(priv);
b481de9c
ZY
1882 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
1883
e1623446 1884 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
1885 priv->assoc_id, priv->beacon_int);
1886
1887 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
1888 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1889 else
1890 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1891
1892 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
1893 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1894 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1895 else
1896 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1897
05c914fe 1898 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
1899 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1900
1901 }
1902
e0158e61 1903 iwlcore_commit_rxon(priv);
b481de9c
ZY
1904
1905 switch (priv->iw_mode) {
05c914fe 1906 case NL80211_IFTYPE_STATION:
b481de9c
ZY
1907 break;
1908
05c914fe 1909 case NL80211_IFTYPE_ADHOC:
b481de9c 1910
c46fbefa
AK
1911 /* assume default assoc id */
1912 priv->assoc_id = 1;
b481de9c 1913
4f40e4d9 1914 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 1915 iwl_send_beacon_cmd(priv);
b481de9c
ZY
1916
1917 break;
1918
1919 default:
15b1687c 1920 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 1921 __func__, priv->iw_mode);
b481de9c
ZY
1922 break;
1923 }
1924
05c914fe 1925 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
1926 priv->assoc_station_added = 1;
1927
1ff50bda
EG
1928 spin_lock_irqsave(&priv->lock, flags);
1929 iwl_activate_qos(priv, 0);
1930 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 1931
04816448
GE
1932 /* the chain noise calibration will enabled PM upon completion
1933 * If chain noise has already been run, then we need to enable
1934 * power management here */
1935 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
1936 iwl_power_enable_management(priv);
c90a74ba
EG
1937
1938 /* Enable Rx differential gain and sensitivity calibrations */
1939 iwl_chain_noise_reset(priv);
1940 priv->start_calib = 1;
1941
508e32e1
RC
1942}
1943
b481de9c
ZY
1944/*****************************************************************************
1945 *
1946 * mac80211 entry point functions
1947 *
1948 *****************************************************************************/
1949
154b25ce 1950#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 1951
5b9f8cd3 1952static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 1953{
c79dd5b5 1954 struct iwl_priv *priv = hw->priv;
5a66926a 1955 int ret;
b481de9c 1956
e1623446 1957 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
1958
1959 /* we should be verifying the device is ready to be opened */
1960 mutex_lock(&priv->mutex);
1961
c1adf9fb 1962 memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
5a66926a
ZY
1963 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
1964 * ucode filename and max sizes are card-specific. */
b481de9c 1965
5a66926a 1966 if (!priv->ucode_code.len) {
5b9f8cd3 1967 ret = iwl_read_ucode(priv);
5a66926a 1968 if (ret) {
15b1687c 1969 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 1970 mutex_unlock(&priv->mutex);
6cd0b1cb 1971 return ret;
5a66926a
ZY
1972 }
1973 }
b481de9c 1974
5b9f8cd3 1975 ret = __iwl_up(priv);
5a66926a 1976
b481de9c 1977 mutex_unlock(&priv->mutex);
5a66926a 1978
80fcc9e2
AG
1979 iwl_rfkill_set_hw_state(priv);
1980
e655b9f0 1981 if (ret)
6cd0b1cb 1982 return ret;
e655b9f0 1983
c1842d61
TW
1984 if (iwl_is_rfkill(priv))
1985 goto out;
1986
e1623446 1987 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 1988
fe9b6b72 1989 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 1990 * mac80211 will not be run successfully. */
154b25ce
EG
1991 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
1992 test_bit(STATUS_READY, &priv->status),
1993 UCODE_READY_TIMEOUT);
1994 if (!ret) {
1995 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 1996 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 1997 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 1998 return -ETIMEDOUT;
5a66926a 1999 }
fe9b6b72 2000 }
0a078ffa 2001
c1842d61 2002out:
0a078ffa 2003 priv->is_open = 1;
e1623446 2004 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2005 return 0;
2006}
2007
5b9f8cd3 2008static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2009{
c79dd5b5 2010 struct iwl_priv *priv = hw->priv;
b481de9c 2011
e1623446 2012 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2013
e655b9f0 2014 if (!priv->is_open) {
e1623446 2015 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
2016 return;
2017 }
2018
b481de9c 2019 priv->is_open = 0;
5a66926a 2020
fee1247a 2021 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
2022 /* stop mac, cancel any scan request and clear
2023 * RXON_FILTER_ASSOC_MSK BIT
2024 */
5a66926a 2025 mutex_lock(&priv->mutex);
2a421b91 2026 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2027 mutex_unlock(&priv->mutex);
fde3571f
MA
2028 }
2029
5b9f8cd3 2030 iwl_down(priv);
5a66926a
ZY
2031
2032 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2033
2034 /* enable interrupts again in order to receive rfkill changes */
2035 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2036 iwl_enable_interrupts(priv);
948c171c 2037
e1623446 2038 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2039}
2040
5b9f8cd3 2041static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2042{
c79dd5b5 2043 struct iwl_priv *priv = hw->priv;
b481de9c 2044
e1623446 2045 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2046
e1623446 2047 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2048 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2049
e039fa4a 2050 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2051 dev_kfree_skb_any(skb);
2052
e1623446 2053 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2054 return NETDEV_TX_OK;
b481de9c
ZY
2055}
2056
5b9f8cd3 2057static int iwl_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY
2058 struct ieee80211_if_init_conf *conf)
2059{
c79dd5b5 2060 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
2061 unsigned long flags;
2062
e1623446 2063 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
b481de9c 2064
32bfd35d 2065 if (priv->vif) {
e1623446 2066 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
75849d28 2067 return -EOPNOTSUPP;
b481de9c
ZY
2068 }
2069
2070 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 2071 priv->vif = conf->vif;
60294de3 2072 priv->iw_mode = conf->type;
b481de9c
ZY
2073
2074 spin_unlock_irqrestore(&priv->lock, flags);
2075
2076 mutex_lock(&priv->mutex);
864792e3
TW
2077
2078 if (conf->mac_addr) {
e1623446 2079 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
864792e3
TW
2080 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2081 }
b481de9c 2082
5b9f8cd3 2083 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
c46fbefa
AK
2084 /* we are not ready, will run again when ready */
2085 set_bit(STATUS_MODE_PENDING, &priv->status);
5a66926a 2086
b481de9c
ZY
2087 mutex_unlock(&priv->mutex);
2088
e1623446 2089 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2090 return 0;
2091}
2092
2093/**
5b9f8cd3 2094 * iwl_mac_config - mac80211 config callback
b481de9c
ZY
2095 *
2096 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2097 * be set inappropriately and the driver currently sets the hardware up to
2098 * use it whenever needed.
2099 */
5b9f8cd3 2100static int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 2101{
c79dd5b5 2102 struct iwl_priv *priv = hw->priv;
bf85ea4f 2103 const struct iwl_channel_info *ch_info;
e8975581 2104 struct ieee80211_conf *conf = &hw->conf;
019fb97d 2105 unsigned long flags = 0;
76bb77e0 2106 int ret = 0;
019fb97d
MA
2107 u16 ch;
2108 int scan_active = 0;
b481de9c
ZY
2109
2110 mutex_lock(&priv->mutex);
019fb97d
MA
2111 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2112 conf->channel->hw_value, changed);
b481de9c 2113
019fb97d
MA
2114 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2115 test_bit(STATUS_SCANNING, &priv->status))) {
2116 scan_active = 1;
2117 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
64e72c3e
MA
2118 }
2119
14a08a7f 2120
019fb97d
MA
2121 /* during scanning mac80211 will delay channel setting until
2122 * scan finish with changed = 0
2123 */
2124 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2125 if (scan_active)
2126 goto set_ch_out;
2127
2128 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2129 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2130 if (!is_channel_valid(ch_info)) {
2131 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2132 ret = -EINVAL;
2133 goto set_ch_out;
2134 }
b481de9c 2135
019fb97d
MA
2136 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2137 !is_channel_ibss(ch_info)) {
2138 IWL_ERR(priv, "channel %d in band %d not "
2139 "IBSS channel\n",
2140 conf->channel->hw_value, conf->channel->band);
2141 ret = -EINVAL;
2142 goto set_ch_out;
2143 }
b481de9c 2144
019fb97d 2145 priv->current_ht_config.is_ht = conf_is_ht(conf);
b481de9c 2146
019fb97d 2147 spin_lock_irqsave(&priv->lock, flags);
398f9e76 2148
82a66bbb 2149
019fb97d
MA
2150 /* if we are switching from ht to 2.4 clear flags
2151 * from any ht related info since 2.4 does not
2152 * support ht */
2153 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2154 priv->staging_rxon.flags = 0;
b5d7be5e 2155
019fb97d 2156 iwl_set_rxon_channel(priv, conf->channel);
b481de9c 2157
019fb97d
MA
2158 iwl_set_flags_for_band(priv, conf->channel->band);
2159 spin_unlock_irqrestore(&priv->lock, flags);
2160 set_ch_out:
2161 /* The list of supported rates and rate mask can be different
2162 * for each band; since the band may have changed, reset
2163 * the rate mask to what mac80211 lists */
2164 iwl_set_rate(priv);
2165 }
b481de9c 2166
019fb97d
MA
2167 if (changed & IEEE80211_CONF_CHANGE_PS) {
2168 if (conf->flags & IEEE80211_CONF_PS)
2169 ret = iwl_power_set_user_mode(priv, IWL_POWER_INDEX_3);
2170 else
2171 ret = iwl_power_set_user_mode(priv, IWL_POWER_MODE_CAM);
2172 if (ret)
2173 IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
b481de9c 2174
019fb97d 2175 }
b481de9c 2176
019fb97d
MA
2177 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2178 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2179 priv->tx_power_user_lmt, conf->power_level);
b481de9c 2180
019fb97d
MA
2181 iwl_set_tx_power(priv, conf->power_level, false);
2182 }
2183
2184 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2185 iwl_set_rxon_chain(priv);
2186
2187 if (changed & IEEE80211_CONF_CHANGE_RADIO_ENABLED) {
2188 if (conf->radio_enabled &&
2189 iwl_radio_kill_sw_enable_radio(priv)) {
2190 IWL_DEBUG_MAC80211(priv, "leave - RF-KILL - "
2191 "waiting for uCode\n");
2192 goto out;
2193 }
2194
2195 if (!conf->radio_enabled)
2196 iwl_radio_kill_sw_disable_radio(priv);
b481de9c 2197 }
b481de9c 2198
b481de9c 2199 if (!conf->radio_enabled) {
e1623446 2200 IWL_DEBUG_MAC80211(priv, "leave - radio disabled\n");
76bb77e0 2201 goto out;
b481de9c
ZY
2202 }
2203
019fb97d
MA
2204 if (!iwl_is_ready(priv)) {
2205 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
76bb77e0 2206 goto out;
b481de9c
ZY
2207 }
2208
019fb97d
MA
2209 if (scan_active)
2210 goto out;
7b841727 2211
b481de9c
ZY
2212 if (memcmp(&priv->active_rxon,
2213 &priv->staging_rxon, sizeof(priv->staging_rxon)))
e0158e61 2214 iwlcore_commit_rxon(priv);
b481de9c 2215 else
e1623446 2216 IWL_DEBUG_INFO(priv, "No re-sending same RXON configuration.\n");
b481de9c 2217
b481de9c 2218
a0646470 2219out:
019fb97d 2220 IWL_DEBUG_MAC80211(priv, "leave\n");
5a66926a 2221 mutex_unlock(&priv->mutex);
76bb77e0 2222 return ret;
b481de9c
ZY
2223}
2224
5b9f8cd3 2225static void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2226{
857485c0 2227 int ret = 0;
1ff50bda 2228 unsigned long flags;
b481de9c 2229
d986bcd1 2230 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2231 return;
2232
2233 /* The following should be done only at AP bring up */
3195c1f3 2234 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2235
2236 /* RXON - unassoc (to set timing command) */
2237 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2238 iwlcore_commit_rxon(priv);
b481de9c
ZY
2239
2240 /* RXON Timing */
3195c1f3 2241 iwl_setup_rxon_timing(priv);
857485c0 2242 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2243 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2244 if (ret)
39aadf8c 2245 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2246 "Attempting to continue.\n");
2247
c7de35cd 2248 iwl_set_rxon_chain(priv);
b481de9c
ZY
2249
2250 /* FIXME: what should be the assoc_id for AP? */
2251 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2252 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2253 priv->staging_rxon.flags |=
2254 RXON_FLG_SHORT_PREAMBLE_MSK;
2255 else
2256 priv->staging_rxon.flags &=
2257 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2258
2259 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2260 if (priv->assoc_capability &
2261 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2262 priv->staging_rxon.flags |=
2263 RXON_FLG_SHORT_SLOT_MSK;
2264 else
2265 priv->staging_rxon.flags &=
2266 ~RXON_FLG_SHORT_SLOT_MSK;
2267
05c914fe 2268 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2269 priv->staging_rxon.flags &=
2270 ~RXON_FLG_SHORT_SLOT_MSK;
2271 }
2272 /* restore RXON assoc */
2273 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2274 iwlcore_commit_rxon(priv);
1ff50bda
EG
2275 spin_lock_irqsave(&priv->lock, flags);
2276 iwl_activate_qos(priv, 1);
2277 spin_unlock_irqrestore(&priv->lock, flags);
4f40e4d9 2278 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
e1493deb 2279 }
5b9f8cd3 2280 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2281
2282 /* FIXME - we need to add code here to detect a totally new
2283 * configuration, reset the AP, unassoc, rxon timing, assoc,
2284 * clear sta table, add BCAST sta... */
2285}
2286
9d139c81 2287
5b9f8cd3 2288static int iwl_mac_config_interface(struct ieee80211_hw *hw,
32bfd35d 2289 struct ieee80211_vif *vif,
b481de9c
ZY
2290 struct ieee80211_if_conf *conf)
2291{
c79dd5b5 2292 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
2293 int rc;
2294
2295 if (conf == NULL)
2296 return -EIO;
2297
b716bb91 2298 if (priv->vif != vif) {
e1623446 2299 IWL_DEBUG_MAC80211(priv, "leave - priv->vif != vif\n");
b716bb91
EG
2300 return 0;
2301 }
2302
05c914fe 2303 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB
2304 conf->changed & IEEE80211_IFCC_BEACON) {
2305 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2306 if (!beacon)
2307 return -ENOMEM;
ada17513 2308 mutex_lock(&priv->mutex);
5b9f8cd3 2309 rc = iwl_mac_beacon_update(hw, beacon);
ada17513 2310 mutex_unlock(&priv->mutex);
9d139c81
JB
2311 if (rc)
2312 return rc;
2313 }
2314
fee1247a 2315 if (!iwl_is_alive(priv))
5a66926a
ZY
2316 return -EAGAIN;
2317
b481de9c
ZY
2318 mutex_lock(&priv->mutex);
2319
b481de9c 2320 if (conf->bssid)
e1623446 2321 IWL_DEBUG_MAC80211(priv, "bssid: %pM\n", conf->bssid);
b481de9c 2322
4150c572
JB
2323/*
2324 * very dubious code was here; the probe filtering flag is never set:
2325 *
b481de9c
ZY
2326 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
2327 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 2328 */
b481de9c 2329
05c914fe 2330 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY
2331 if (!conf->bssid) {
2332 conf->bssid = priv->mac_addr;
2333 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e1623446 2334 IWL_DEBUG_MAC80211(priv, "bssid was set to: %pM\n",
e174961c 2335 conf->bssid);
b481de9c
ZY
2336 }
2337 if (priv->ibss_beacon)
2338 dev_kfree_skb(priv->ibss_beacon);
2339
9d139c81 2340 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY
2341 }
2342
fee1247a 2343 if (iwl_is_rfkill(priv))
fde3571f
MA
2344 goto done;
2345
b481de9c
ZY
2346 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
2347 !is_multicast_ether_addr(conf->bssid)) {
2348 /* If there is currently a HW scan going on in the background
2349 * then we need to cancel it else the RXON below will fail. */
2a421b91 2350 if (iwl_scan_cancel_timeout(priv, 100)) {
39aadf8c 2351 IWL_WARN(priv, "Aborted scan still in progress "
b481de9c 2352 "after 100ms\n");
e1623446 2353 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
b481de9c
ZY
2354 mutex_unlock(&priv->mutex);
2355 return -EAGAIN;
2356 }
2357 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
2358
2359 /* TODO: Audit driver for usage of these members and see
2360 * if mac80211 deprecates them (priv->bssid looks like it
2361 * shouldn't be there, but I haven't scanned the IBSS code
2362 * to verify) - jpk */
2363 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
2364
05c914fe 2365 if (priv->iw_mode == NL80211_IFTYPE_AP)
5b9f8cd3 2366 iwl_config_ap(priv);
b481de9c 2367 else {
e0158e61 2368 rc = iwlcore_commit_rxon(priv);
05c914fe 2369 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
4f40e4d9 2370 iwl_rxon_add_station(
b481de9c
ZY
2371 priv, priv->active_rxon.bssid_addr, 1);
2372 }
2373
2374 } else {
2a421b91 2375 iwl_scan_cancel_timeout(priv, 100);
b481de9c 2376 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2377 iwlcore_commit_rxon(priv);
b481de9c
ZY
2378 }
2379
fde3571f 2380 done:
e1623446 2381 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2382 mutex_unlock(&priv->mutex);
2383
2384 return 0;
2385}
2386
5b9f8cd3 2387static void iwl_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY
2388 struct ieee80211_if_init_conf *conf)
2389{
c79dd5b5 2390 struct iwl_priv *priv = hw->priv;
b481de9c 2391
e1623446 2392 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2393
2394 mutex_lock(&priv->mutex);
948c171c 2395
fee1247a 2396 if (iwl_is_ready_rf(priv)) {
2a421b91 2397 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2398 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2399 iwlcore_commit_rxon(priv);
fde3571f 2400 }
32bfd35d
JB
2401 if (priv->vif == conf->vif) {
2402 priv->vif = NULL;
b481de9c 2403 memset(priv->bssid, 0, ETH_ALEN);
b481de9c
ZY
2404 }
2405 mutex_unlock(&priv->mutex);
2406
e1623446 2407 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2408
2409}
471b3efd 2410
5b9f8cd3 2411static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2412 struct ieee80211_key_conf *keyconf, const u8 *addr,
2413 u32 iv32, u16 *phase1key)
2414{
ab885f8c 2415
9f58671e 2416 struct iwl_priv *priv = hw->priv;
e1623446 2417 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2418
9f58671e 2419 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2420
e1623446 2421 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2422}
2423
5b9f8cd3 2424static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2425 struct ieee80211_vif *vif,
2426 struct ieee80211_sta *sta,
b481de9c
ZY
2427 struct ieee80211_key_conf *key)
2428{
c79dd5b5 2429 struct iwl_priv *priv = hw->priv;
42986796
WT
2430 const u8 *addr;
2431 int ret;
2432 u8 sta_id;
2433 bool is_default_wep_key = false;
b481de9c 2434
e1623446 2435 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2436
099b40b7 2437 if (priv->hw_params.sw_crypto) {
e1623446 2438 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2439 return -EOPNOTSUPP;
2440 }
42986796 2441 addr = sta ? sta->addr : iwl_bcast_addr;
e11bc028 2442 sta_id = priv->cfg->ops->smgmt->find_station(priv, addr);
6974e363 2443 if (sta_id == IWL_INVALID_STATION) {
e1623446 2444 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2445 addr);
6974e363 2446 return -EINVAL;
b481de9c 2447
deb09c43 2448 }
b481de9c 2449
6974e363 2450 mutex_lock(&priv->mutex);
2a421b91 2451 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2452 mutex_unlock(&priv->mutex);
2453
2454 /* If we are getting WEP group key and we didn't receive any key mapping
2455 * so far, we are in legacy wep mode (group key only), otherwise we are
2456 * in 1X mode.
2457 * In legacy wep mode, we use another host command to the uCode */
5425e490 2458 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2459 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2460 if (cmd == SET_KEY)
2461 is_default_wep_key = !priv->key_mapping_key;
2462 else
ccc038ab
EG
2463 is_default_wep_key =
2464 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2465 }
052c4b9f 2466
b481de9c 2467 switch (cmd) {
deb09c43 2468 case SET_KEY:
6974e363
EG
2469 if (is_default_wep_key)
2470 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2471 else
7480513f 2472 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2473
e1623446 2474 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2475 break;
2476 case DISABLE_KEY:
6974e363
EG
2477 if (is_default_wep_key)
2478 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2479 else
3ec47732 2480 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2481
e1623446 2482 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2483 break;
2484 default:
deb09c43 2485 ret = -EINVAL;
b481de9c
ZY
2486 }
2487
e1623446 2488 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2489
deb09c43 2490 return ret;
b481de9c
ZY
2491}
2492
5b9f8cd3 2493static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2494 enum ieee80211_ampdu_mlme_action action,
17741cdc 2495 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2496{
2497 struct iwl_priv *priv = hw->priv;
5c2207c6 2498 int ret;
d783b061 2499
e1623446 2500 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2501 sta->addr, tid);
d783b061
TW
2502
2503 if (!(priv->cfg->sku & IWL_SKU_N))
2504 return -EACCES;
2505
2506 switch (action) {
2507 case IEEE80211_AMPDU_RX_START:
e1623446 2508 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2509 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2510 case IEEE80211_AMPDU_RX_STOP:
e1623446 2511 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2512 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2513 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2514 return 0;
2515 else
2516 return ret;
d783b061 2517 case IEEE80211_AMPDU_TX_START:
e1623446 2518 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2519 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2520 case IEEE80211_AMPDU_TX_STOP:
e1623446 2521 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2522 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2523 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2524 return 0;
2525 else
2526 return ret;
d783b061 2527 default:
e1623446 2528 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2529 return -EINVAL;
2530 break;
2531 }
2532 return 0;
2533}
9f58671e 2534
5b9f8cd3 2535static int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2536 struct ieee80211_tx_queue_stats *stats)
2537{
c79dd5b5 2538 struct iwl_priv *priv = hw->priv;
b481de9c 2539 int i, avail;
16466903 2540 struct iwl_tx_queue *txq;
443cfd45 2541 struct iwl_queue *q;
b481de9c
ZY
2542 unsigned long flags;
2543
e1623446 2544 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2545
fee1247a 2546 if (!iwl_is_ready_rf(priv)) {
e1623446 2547 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
b481de9c
ZY
2548 return -EIO;
2549 }
2550
2551 spin_lock_irqsave(&priv->lock, flags);
2552
2553 for (i = 0; i < AC_NUM; i++) {
2554 txq = &priv->txq[i];
2555 q = &txq->q;
443cfd45 2556 avail = iwl_queue_space(q);
b481de9c 2557
57ffc589
JB
2558 stats[i].len = q->n_window - avail;
2559 stats[i].limit = q->n_window - q->high_mark;
2560 stats[i].count = q->n_window;
b481de9c
ZY
2561
2562 }
2563 spin_unlock_irqrestore(&priv->lock, flags);
2564
e1623446 2565 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2566
2567 return 0;
2568}
2569
5b9f8cd3 2570static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2571 struct ieee80211_low_level_stats *stats)
2572{
bf403db8
EK
2573 struct iwl_priv *priv = hw->priv;
2574
2575 priv = hw->priv;
e1623446
TW
2576 IWL_DEBUG_MAC80211(priv, "enter\n");
2577 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2578
2579 return 0;
2580}
2581
5b9f8cd3 2582static void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 2583{
c79dd5b5 2584 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
2585 unsigned long flags;
2586
2587 mutex_lock(&priv->mutex);
e1623446 2588 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2589
b481de9c 2590 spin_lock_irqsave(&priv->lock, flags);
fd105e79 2591 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
b481de9c 2592 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c 2593
c7de35cd 2594 iwl_reset_qos(priv);
b481de9c 2595
b481de9c
ZY
2596 spin_lock_irqsave(&priv->lock, flags);
2597 priv->assoc_id = 0;
2598 priv->assoc_capability = 0;
b481de9c
ZY
2599 priv->assoc_station_added = 0;
2600
2601 /* new association get rid of ibss beacon skb */
2602 if (priv->ibss_beacon)
2603 dev_kfree_skb(priv->ibss_beacon);
2604
2605 priv->ibss_beacon = NULL;
2606
2607 priv->beacon_int = priv->hw->conf.beacon_int;
3109ece1 2608 priv->timestamp = 0;
05c914fe 2609 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY
2610 priv->beacon_int = 0;
2611
2612 spin_unlock_irqrestore(&priv->lock, flags);
2613
fee1247a 2614 if (!iwl_is_ready_rf(priv)) {
e1623446 2615 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
fde3571f
MA
2616 mutex_unlock(&priv->mutex);
2617 return;
2618 }
2619
052c4b9f 2620 /* we are restarting association process
2621 * clear RXON_FILTER_ASSOC_MSK bit
2622 */
05c914fe 2623 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2a421b91 2624 iwl_scan_cancel_timeout(priv, 100);
052c4b9f 2625 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2626 iwlcore_commit_rxon(priv);
052c4b9f 2627 }
2628
5da4b55f
MA
2629 iwl_power_update_mode(priv, 0);
2630
b481de9c 2631 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 2632 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
052c4b9f 2633
c90a74ba
EG
2634 /* switch to CAM during association period.
2635 * the ucode will block any association/authentication
2636 * frome during assiciation period if it can not hear
2637 * the AP because of PM. the timer enable PM back is
2638 * association do not complete
2639 */
2640 if (priv->hw->conf.channel->flags & (IEEE80211_CHAN_PASSIVE_SCAN |
2641 IEEE80211_CHAN_RADAR))
2642 iwl_power_disable_management(priv, 3000);
2643
e1623446 2644 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
b481de9c
ZY
2645 mutex_unlock(&priv->mutex);
2646 return;
2647 }
2648
5b9f8cd3 2649 iwl_set_rate(priv);
b481de9c
ZY
2650
2651 mutex_unlock(&priv->mutex);
2652
e1623446 2653 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2654}
2655
b481de9c 2656
b481de9c
ZY
2657/*****************************************************************************
2658 *
2659 * sysfs attributes
2660 *
2661 *****************************************************************************/
2662
0a6857e7 2663#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2664
2665/*
2666 * The following adds a new attribute to the sysfs representation
c3a739fa 2667 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2668 * used for controlling the debug level.
2669 *
2670 * See the level definitions in iwl for details.
2671 */
2672
8cf769c6
EK
2673static ssize_t show_debug_level(struct device *d,
2674 struct device_attribute *attr, char *buf)
b481de9c 2675{
8cf769c6
EK
2676 struct iwl_priv *priv = d->driver_data;
2677
2678 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 2679}
8cf769c6
EK
2680static ssize_t store_debug_level(struct device *d,
2681 struct device_attribute *attr,
b481de9c
ZY
2682 const char *buf, size_t count)
2683{
8cf769c6 2684 struct iwl_priv *priv = d->driver_data;
9257746f
TW
2685 unsigned long val;
2686 int ret;
b481de9c 2687
9257746f
TW
2688 ret = strict_strtoul(buf, 0, &val);
2689 if (ret)
978785a3 2690 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 2691 else
8cf769c6 2692 priv->debug_level = val;
b481de9c
ZY
2693
2694 return strnlen(buf, count);
2695}
2696
8cf769c6
EK
2697static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2698 show_debug_level, store_debug_level);
2699
b481de9c 2700
0a6857e7 2701#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2702
b481de9c 2703
bc6f59bc
TW
2704static ssize_t show_version(struct device *d,
2705 struct device_attribute *attr, char *buf)
2706{
2707 struct iwl_priv *priv = d->driver_data;
885ba202 2708 struct iwl_alive_resp *palive = &priv->card_alive;
f236a265
TW
2709 ssize_t pos = 0;
2710 u16 eeprom_ver;
bc6f59bc
TW
2711
2712 if (palive->is_valid)
f236a265
TW
2713 pos += sprintf(buf + pos,
2714 "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
2715 "fw type: 0x%01X 0x%01X\n",
bc6f59bc
TW
2716 palive->ucode_major, palive->ucode_minor,
2717 palive->sw_rev[0], palive->sw_rev[1],
2718 palive->ver_type, palive->ver_subtype);
bc6f59bc 2719 else
f236a265
TW
2720 pos += sprintf(buf + pos, "fw not loaded\n");
2721
2722 if (priv->eeprom) {
2723 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
2724 pos += sprintf(buf + pos, "EEPROM version: 0x%x\n",
2725 eeprom_ver);
2726 } else {
2727 pos += sprintf(buf + pos, "EEPROM not initialzed\n");
2728 }
2729
2730 return pos;
bc6f59bc
TW
2731}
2732
2733static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
2734
b481de9c
ZY
2735static ssize_t show_temperature(struct device *d,
2736 struct device_attribute *attr, char *buf)
2737{
c79dd5b5 2738 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 2739
fee1247a 2740 if (!iwl_is_alive(priv))
b481de9c
ZY
2741 return -EAGAIN;
2742
91dbc5bd 2743 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2744}
2745
2746static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2747
b481de9c
ZY
2748static ssize_t show_tx_power(struct device *d,
2749 struct device_attribute *attr, char *buf)
2750{
c79dd5b5 2751 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
91f39e8e
JS
2752
2753 if (!iwl_is_ready_rf(priv))
2754 return sprintf(buf, "off\n");
2755 else
2756 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2757}
2758
2759static ssize_t store_tx_power(struct device *d,
2760 struct device_attribute *attr,
2761 const char *buf, size_t count)
2762{
c79dd5b5 2763 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW
2764 unsigned long val;
2765 int ret;
b481de9c 2766
9257746f
TW
2767 ret = strict_strtoul(buf, 10, &val);
2768 if (ret)
978785a3 2769 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
b481de9c 2770 else
630fe9b6 2771 iwl_set_tx_power(priv, val, false);
b481de9c
ZY
2772
2773 return count;
2774}
2775
2776static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2777
2778static ssize_t show_flags(struct device *d,
2779 struct device_attribute *attr, char *buf)
2780{
c79dd5b5 2781 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
2782
2783 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2784}
2785
2786static ssize_t store_flags(struct device *d,
2787 struct device_attribute *attr,
2788 const char *buf, size_t count)
2789{
c79dd5b5 2790 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW
2791 unsigned long val;
2792 u32 flags;
2793 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2794 if (ret)
9257746f
TW
2795 return ret;
2796 flags = (u32)val;
b481de9c
ZY
2797
2798 mutex_lock(&priv->mutex);
2799 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2800 /* Cancel any currently running scans... */
2a421b91 2801 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2802 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2803 else {
e1623446 2804 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2805 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2806 iwlcore_commit_rxon(priv);
b481de9c
ZY
2807 }
2808 }
2809 mutex_unlock(&priv->mutex);
2810
2811 return count;
2812}
2813
2814static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2815
2816static ssize_t show_filter_flags(struct device *d,
2817 struct device_attribute *attr, char *buf)
2818{
c79dd5b5 2819 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
2820
2821 return sprintf(buf, "0x%04X\n",
2822 le32_to_cpu(priv->active_rxon.filter_flags));
2823}
2824
2825static ssize_t store_filter_flags(struct device *d,
2826 struct device_attribute *attr,
2827 const char *buf, size_t count)
2828{
c79dd5b5 2829 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW
2830 unsigned long val;
2831 u32 filter_flags;
2832 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2833 if (ret)
9257746f
TW
2834 return ret;
2835 filter_flags = (u32)val;
b481de9c
ZY
2836
2837 mutex_lock(&priv->mutex);
2838 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2839 /* Cancel any currently running scans... */
2a421b91 2840 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2841 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2842 else {
e1623446 2843 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2844 "0x%04X\n", filter_flags);
2845 priv->staging_rxon.filter_flags =
2846 cpu_to_le32(filter_flags);
e0158e61 2847 iwlcore_commit_rxon(priv);
b481de9c
ZY
2848 }
2849 }
2850 mutex_unlock(&priv->mutex);
2851
2852 return count;
2853}
2854
2855static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2856 store_filter_flags);
2857
b481de9c
ZY
2858static ssize_t store_power_level(struct device *d,
2859 struct device_attribute *attr,
2860 const char *buf, size_t count)
2861{
c79dd5b5 2862 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6 2863 int ret;
9257746f
TW
2864 unsigned long mode;
2865
b481de9c 2866
b481de9c
ZY
2867 mutex_lock(&priv->mutex);
2868
9257746f 2869 ret = strict_strtoul(buf, 10, &mode);
926f0b2e 2870 if (ret)
9257746f
TW
2871 goto out;
2872
298df1f6
EK
2873 ret = iwl_power_set_user_mode(priv, mode);
2874 if (ret) {
e1623446 2875 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
5da4b55f 2876 goto out;
b481de9c 2877 }
298df1f6 2878 ret = count;
b481de9c
ZY
2879
2880 out:
2881 mutex_unlock(&priv->mutex);
298df1f6 2882 return ret;
b481de9c
ZY
2883}
2884
b481de9c
ZY
2885static ssize_t show_power_level(struct device *d,
2886 struct device_attribute *attr, char *buf)
2887{
c79dd5b5 2888 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6
EK
2889 int mode = priv->power_data.user_power_setting;
2890 int system = priv->power_data.system_power_setting;
5da4b55f 2891 int level = priv->power_data.power_mode;
b481de9c
ZY
2892 char *p = buf;
2893
298df1f6
EK
2894 switch (system) {
2895 case IWL_POWER_SYS_AUTO:
2896 p += sprintf(p, "SYSTEM:auto");
b481de9c 2897 break;
298df1f6
EK
2898 case IWL_POWER_SYS_AC:
2899 p += sprintf(p, "SYSTEM:ac");
2900 break;
2901 case IWL_POWER_SYS_BATTERY:
2902 p += sprintf(p, "SYSTEM:battery");
b481de9c 2903 break;
b481de9c 2904 }
298df1f6 2905
c3056065
AK
2906 p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO) ?
2907 "fixed" : "auto");
298df1f6
EK
2908 p += sprintf(p, "\tINDEX:%d", level);
2909 p += sprintf(p, "\n");
3ac7f146 2910 return p - buf + 1;
b481de9c
ZY
2911}
2912
2913static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
2914 store_power_level);
2915
b481de9c
ZY
2916
2917static ssize_t show_statistics(struct device *d,
2918 struct device_attribute *attr, char *buf)
2919{
c79dd5b5 2920 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2921 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2922 u32 len = 0, ofs = 0;
3ac7f146 2923 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2924 int rc = 0;
2925
fee1247a 2926 if (!iwl_is_alive(priv))
b481de9c
ZY
2927 return -EAGAIN;
2928
2929 mutex_lock(&priv->mutex);
49ea8596 2930 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2931 mutex_unlock(&priv->mutex);
2932
2933 if (rc) {
2934 len = sprintf(buf,
2935 "Error sending statistics request: 0x%08X\n", rc);
2936 return len;
2937 }
2938
2939 while (size && (PAGE_SIZE - len)) {
2940 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2941 PAGE_SIZE - len, 1);
2942 len = strlen(buf);
2943 if (PAGE_SIZE - len)
2944 buf[len++] = '\n';
2945
2946 ofs += 16;
2947 size -= min(size, 16U);
2948 }
2949
2950 return len;
2951}
2952
2953static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2954
b481de9c 2955
b481de9c
ZY
2956/*****************************************************************************
2957 *
2958 * driver setup and teardown
2959 *
2960 *****************************************************************************/
2961
4e39317d 2962static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2963{
d21050c7 2964 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2965
2966 init_waitqueue_head(&priv->wait_command_queue);
2967
5b9f8cd3
EG
2968 INIT_WORK(&priv->up, iwl_bg_up);
2969 INIT_WORK(&priv->restart, iwl_bg_restart);
2970 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
2971 INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
2972 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2973 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2974 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2975 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2976
2a421b91 2977 iwl_setup_scan_deferred_work(priv);
c90a74ba 2978 iwl_setup_power_deferred_work(priv);
bb8c093b 2979
4e39317d
EG
2980 if (priv->cfg->ops->lib->setup_deferred_work)
2981 priv->cfg->ops->lib->setup_deferred_work(priv);
2982
2983 init_timer(&priv->statistics_periodic);
2984 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2985 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c
ZY
2986
2987 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
5b9f8cd3 2988 iwl_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
2989}
2990
4e39317d 2991static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2992{
4e39317d
EG
2993 if (priv->cfg->ops->lib->cancel_deferred_work)
2994 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 2995
3ae6a054 2996 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 2997 cancel_delayed_work(&priv->scan_check);
c90a74ba 2998 cancel_delayed_work_sync(&priv->set_power_save);
b481de9c 2999 cancel_delayed_work(&priv->alive_start);
b481de9c 3000 cancel_work_sync(&priv->beacon_update);
4e39317d 3001 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
3002}
3003
5b9f8cd3 3004static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
3005 &dev_attr_flags.attr,
3006 &dev_attr_filter_flags.attr,
b481de9c 3007 &dev_attr_power_level.attr,
b481de9c 3008 &dev_attr_statistics.attr,
b481de9c 3009 &dev_attr_temperature.attr,
b481de9c 3010 &dev_attr_tx_power.attr,
8cf769c6
EK
3011#ifdef CONFIG_IWLWIFI_DEBUG
3012 &dev_attr_debug_level.attr,
3013#endif
bc6f59bc 3014 &dev_attr_version.attr,
b481de9c
ZY
3015
3016 NULL
3017};
3018
5b9f8cd3 3019static struct attribute_group iwl_attribute_group = {
b481de9c 3020 .name = NULL, /* put in device directory */
5b9f8cd3 3021 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3022};
3023
5b9f8cd3
EG
3024static struct ieee80211_ops iwl_hw_ops = {
3025 .tx = iwl_mac_tx,
3026 .start = iwl_mac_start,
3027 .stop = iwl_mac_stop,
3028 .add_interface = iwl_mac_add_interface,
3029 .remove_interface = iwl_mac_remove_interface,
3030 .config = iwl_mac_config,
3031 .config_interface = iwl_mac_config_interface,
3032 .configure_filter = iwl_configure_filter,
3033 .set_key = iwl_mac_set_key,
3034 .update_tkip_key = iwl_mac_update_tkip_key,
3035 .get_stats = iwl_mac_get_stats,
3036 .get_tx_stats = iwl_mac_get_tx_stats,
3037 .conf_tx = iwl_mac_conf_tx,
3038 .reset_tsf = iwl_mac_reset_tsf,
3039 .bss_info_changed = iwl_bss_info_changed,
3040 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 3041 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3042};
3043
5b9f8cd3 3044static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3045{
3046 int err = 0;
c79dd5b5 3047 struct iwl_priv *priv;
b481de9c 3048 struct ieee80211_hw *hw;
82b9a121 3049 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3050 unsigned long flags;
6cd0b1cb 3051 u16 pci_cmd;
b481de9c 3052
316c30d9
AK
3053 /************************
3054 * 1. Allocating HW data
3055 ************************/
3056
6440adb5
BC
3057 /* Disabling hardware scan means that mac80211 will perform scans
3058 * "the hard way", rather than using device's scan. */
1ea87396 3059 if (cfg->mod_params->disable_hw_scan) {
bf403db8
EK
3060 if (cfg->mod_params->debug & IWL_DL_INFO)
3061 dev_printk(KERN_DEBUG, &(pdev->dev),
3062 "Disabling hw_scan\n");
5b9f8cd3 3063 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3064 }
3065
5b9f8cd3 3066 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3067 if (!hw) {
b481de9c
ZY
3068 err = -ENOMEM;
3069 goto out;
3070 }
1d0a082d
AK
3071 priv = hw->priv;
3072 /* At this point both hw and priv are allocated. */
3073
b481de9c
ZY
3074 SET_IEEE80211_DEV(hw, &pdev->dev);
3075
e1623446 3076 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3077 priv->cfg = cfg;
b481de9c 3078 priv->pci_dev = pdev;
316c30d9 3079
0a6857e7 3080#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 3081 priv->debug_level = priv->cfg->mod_params->debug;
b481de9c
ZY
3082 atomic_set(&priv->restrict_refcnt, 0);
3083#endif
b481de9c 3084
316c30d9
AK
3085 /**************************
3086 * 2. Initializing PCI bus
3087 **************************/
3088 if (pci_enable_device(pdev)) {
3089 err = -ENODEV;
3090 goto out_ieee80211_free_hw;
3091 }
3092
3093 pci_set_master(pdev);
3094
093d874c 3095 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3096 if (!err)
093d874c 3097 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3098 if (err) {
093d874c 3099 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3100 if (!err)
093d874c 3101 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3102 /* both attempts failed: */
316c30d9 3103 if (err) {
978785a3 3104 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3105 goto out_pci_disable_device;
cc2a8ea8 3106 }
316c30d9
AK
3107 }
3108
3109 err = pci_request_regions(pdev, DRV_NAME);
3110 if (err)
3111 goto out_pci_disable_device;
3112
3113 pci_set_drvdata(pdev, priv);
3114
316c30d9
AK
3115
3116 /***********************
3117 * 3. Read REV register
3118 ***********************/
3119 priv->hw_base = pci_iomap(pdev, 0, 0);
3120 if (!priv->hw_base) {
3121 err = -ENODEV;
3122 goto out_pci_release_regions;
3123 }
3124
e1623446 3125 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3126 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3127 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3128
b661c819 3129 iwl_hw_detect(priv);
978785a3 3130 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3131 priv->cfg->name, priv->hw_rev);
316c30d9 3132
e7b63581
TW
3133 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3134 * PCI Tx retries from interfering with C3 CPU state */
3135 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3136
91238714
TW
3137 /* amp init */
3138 err = priv->cfg->ops->lib->apm_ops.init(priv);
316c30d9 3139 if (err < 0) {
808ff697 3140 IWL_ERR(priv, "Failed to init APMG\n");
316c30d9
AK
3141 goto out_iounmap;
3142 }
91238714
TW
3143 /*****************
3144 * 4. Read EEPROM
3145 *****************/
316c30d9
AK
3146 /* Read the EEPROM */
3147 err = iwl_eeprom_init(priv);
3148 if (err) {
15b1687c 3149 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3150 goto out_iounmap;
3151 }
8614f360
TW
3152 err = iwl_eeprom_check_version(priv);
3153 if (err)
c8f16138 3154 goto out_free_eeprom;
8614f360 3155
02883017 3156 /* extract MAC Address */
316c30d9 3157 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3158 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3159 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3160
3161 /************************
3162 * 5. Setup HW constants
3163 ************************/
da154e30 3164 if (iwl_set_hw_params(priv)) {
15b1687c 3165 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3166 goto out_free_eeprom;
316c30d9
AK
3167 }
3168
3169 /*******************
6ba87956 3170 * 6. Setup priv
316c30d9 3171 *******************/
b481de9c 3172
6ba87956 3173 err = iwl_init_drv(priv);
bf85ea4f 3174 if (err)
399f4900 3175 goto out_free_eeprom;
bf85ea4f 3176 /* At this point both hw and priv are initialized. */
316c30d9
AK
3177
3178 /**********************************
3179 * 7. Initialize module parameters
3180 **********************************/
3181
3182 /* Disable radio (SW RF KILL) via parameter when loading driver */
1ea87396 3183 if (priv->cfg->mod_params->disable) {
316c30d9 3184 set_bit(STATUS_RF_KILL_SW, &priv->status);
e1623446 3185 IWL_DEBUG_INFO(priv, "Radio disabled.\n");
316c30d9
AK
3186 }
3187
316c30d9
AK
3188 /********************
3189 * 8. Setup services
3190 ********************/
0359facc 3191 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3192 iwl_disable_interrupts(priv);
0359facc 3193 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3194
6cd0b1cb
HS
3195 pci_enable_msi(priv->pci_dev);
3196
3197 err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED,
3198 DRV_NAME, priv);
3199 if (err) {
3200 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3201 goto out_disable_msi;
3202 }
5b9f8cd3 3203 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3204 if (err) {
15b1687c 3205 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3206 goto out_free_irq;
316c30d9
AK
3207 }
3208
4e39317d 3209 iwl_setup_deferred_work(priv);
653fa4a0 3210 iwl_setup_rx_handlers(priv);
316c30d9 3211
6ba87956 3212 /**********************************
6cd0b1cb 3213 * 9. Setup and register mac80211
6ba87956
TW
3214 **********************************/
3215
6cd0b1cb
HS
3216 /* enable interrupts if needed: hw bug w/a */
3217 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3218 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3219 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3220 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3221 }
3222
3223 iwl_enable_interrupts(priv);
3224
6ba87956
TW
3225 err = iwl_setup_mac(priv);
3226 if (err)
3227 goto out_remove_sysfs;
3228
3229 err = iwl_dbgfs_register(priv, DRV_NAME);
3230 if (err)
15b1687c 3231 IWL_ERR(priv, "failed to create debugfs files\n");
6ba87956 3232
6cd0b1cb
HS
3233 /* If platform's RF_KILL switch is NOT set to KILL */
3234 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3235 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3236 else
3237 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3238
58d0f361
EG
3239 err = iwl_rfkill_init(priv);
3240 if (err)
15b1687c 3241 IWL_ERR(priv, "Unable to initialize RFKILL system. "
58d0f361 3242 "Ignoring error: %d\n", err);
6cd0b1cb
HS
3243 else
3244 iwl_rfkill_set_hw_state(priv);
3245
58d0f361 3246 iwl_power_initialize(priv);
b481de9c
ZY
3247 return 0;
3248
316c30d9 3249 out_remove_sysfs:
c8f16138
RC
3250 destroy_workqueue(priv->workqueue);
3251 priv->workqueue = NULL;
5b9f8cd3 3252 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3253 out_free_irq:
3254 free_irq(priv->pci_dev->irq, priv);
6cd0b1cb
HS
3255 out_disable_msi:
3256 pci_disable_msi(priv->pci_dev);
6ba87956 3257 iwl_uninit_drv(priv);
073d3f5f
TW
3258 out_free_eeprom:
3259 iwl_eeprom_free(priv);
b481de9c
ZY
3260 out_iounmap:
3261 pci_iounmap(pdev, priv->hw_base);
3262 out_pci_release_regions:
316c30d9 3263 pci_set_drvdata(pdev, NULL);
623d563e 3264 pci_release_regions(pdev);
b481de9c
ZY
3265 out_pci_disable_device:
3266 pci_disable_device(pdev);
b481de9c
ZY
3267 out_ieee80211_free_hw:
3268 ieee80211_free_hw(priv->hw);
3269 out:
3270 return err;
3271}
3272
5b9f8cd3 3273static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3274{
c79dd5b5 3275 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3276 unsigned long flags;
b481de9c
ZY
3277
3278 if (!priv)
3279 return;
3280
e1623446 3281 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3282
67249625 3283 iwl_dbgfs_unregister(priv);
5b9f8cd3 3284 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3285
5b9f8cd3
EG
3286 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3287 * to be called and iwl_down since we are removing the device
0b124c31
GG
3288 * we need to set STATUS_EXIT_PENDING bit.
3289 */
3290 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3291 if (priv->mac80211_registered) {
3292 ieee80211_unregister_hw(priv->hw);
3293 priv->mac80211_registered = 0;
0b124c31 3294 } else {
5b9f8cd3 3295 iwl_down(priv);
c4f55232
RR
3296 }
3297
0359facc
MA
3298 /* make sure we flush any pending irq or
3299 * tasklet for the driver
3300 */
3301 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3302 iwl_disable_interrupts(priv);
0359facc
MA
3303 spin_unlock_irqrestore(&priv->lock, flags);
3304
3305 iwl_synchronize_irq(priv);
3306
58d0f361 3307 iwl_rfkill_unregister(priv);
5b9f8cd3 3308 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3309
3310 if (priv->rxq.bd)
a55360e4 3311 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3312 iwl_hw_txq_ctx_free(priv);
b481de9c 3313
e11bc028 3314 priv->cfg->ops->smgmt->clear_station_table(priv);
073d3f5f 3315 iwl_eeprom_free(priv);
b481de9c 3316
b481de9c 3317
948c171c
MA
3318 /*netif_stop_queue(dev); */
3319 flush_workqueue(priv->workqueue);
3320
5b9f8cd3 3321 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3322 * priv->workqueue... so we can't take down the workqueue
3323 * until now... */
3324 destroy_workqueue(priv->workqueue);
3325 priv->workqueue = NULL;
3326
6cd0b1cb
HS
3327 free_irq(priv->pci_dev->irq, priv);
3328 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3329 pci_iounmap(pdev, priv->hw_base);
3330 pci_release_regions(pdev);
3331 pci_disable_device(pdev);
3332 pci_set_drvdata(pdev, NULL);
3333
6ba87956 3334 iwl_uninit_drv(priv);
b481de9c
ZY
3335
3336 if (priv->ibss_beacon)
3337 dev_kfree_skb(priv->ibss_beacon);
3338
3339 ieee80211_free_hw(priv->hw);
3340}
3341
b481de9c
ZY
3342
3343/*****************************************************************************
3344 *
3345 * driver and module entry point
3346 *
3347 *****************************************************************************/
3348
fed9017e
RR
3349/* Hardware specific file defines the PCI IDs table for that hardware module */
3350static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3351#ifdef CONFIG_IWL4965
fed9017e
RR
3352 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3353 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3354#endif /* CONFIG_IWL4965 */
5a6a256e 3355#ifdef CONFIG_IWL5000
47408639
EK
3356 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3357 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3358 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3359 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3360 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3361 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3362 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3363 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3364 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3365 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3366/* 5350 WiFi/WiMax */
3367 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3368 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3369 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3370/* 5150 Wifi/WiMax */
3371 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3372 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
e1228374
JS
3373/* 6000/6050 Series */
3374 {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
3375 {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
3376 {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
3377 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
3378 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
3379 {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
3380 {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
3381 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3382 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3383 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3384 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
77dcb6a9
JS
3385/* 1000 Series WiFi */
3386 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
3387 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
5a6a256e 3388#endif /* CONFIG_IWL5000 */
7100e924 3389
fed9017e
RR
3390 {0}
3391};
3392MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3393
3394static struct pci_driver iwl_driver = {
b481de9c 3395 .name = DRV_NAME,
fed9017e 3396 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3397 .probe = iwl_pci_probe,
3398 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3399#ifdef CONFIG_PM
5b9f8cd3
EG
3400 .suspend = iwl_pci_suspend,
3401 .resume = iwl_pci_resume,
b481de9c
ZY
3402#endif
3403};
3404
5b9f8cd3 3405static int __init iwl_init(void)
b481de9c
ZY
3406{
3407
3408 int ret;
3409 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3410 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3411
e227ceac 3412 ret = iwlagn_rate_control_register();
897e1cf2 3413 if (ret) {
a3139c59
SO
3414 printk(KERN_ERR DRV_NAME
3415 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3416 return ret;
3417 }
3418
fed9017e 3419 ret = pci_register_driver(&iwl_driver);
b481de9c 3420 if (ret) {
a3139c59 3421 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3422 goto error_register;
b481de9c 3423 }
b481de9c
ZY
3424
3425 return ret;
897e1cf2 3426
897e1cf2 3427error_register:
e227ceac 3428 iwlagn_rate_control_unregister();
897e1cf2 3429 return ret;
b481de9c
ZY
3430}
3431
5b9f8cd3 3432static void __exit iwl_exit(void)
b481de9c 3433{
fed9017e 3434 pci_unregister_driver(&iwl_driver);
e227ceac 3435 iwlagn_rate_control_unregister();
b481de9c
ZY
3436}
3437
5b9f8cd3
EG
3438module_exit(iwl_exit);
3439module_init(iwl_init);