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iwlwifi: Convert to new PCI PM framework
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
0de76736 60#include "iwl-agn-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY		 64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY		 70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
bee008b7 90static int iwlagn_ant_coupling;
f37837c9 91static bool iwlagn_bt_ch_announce = 1;
bee008b7 92
b481de9c 93/**
7314c2b3 94 * iwlagn_commit_rxon - commit staging_rxon to hardware
b481de9c 95 *
01ebd063 96 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
100 */
7314c2b3 101int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
b481de9c
ZY		 102{
103 /* cast away the const for active_rxon in this function */
246ed355 104 struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
43d59b32
EG		 105 int ret;
106 bool new_assoc =
246ed355 107 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
b01efe43 108 bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 109
fee1247a 110 if (!iwl_is_alive(priv))
43d59b32 111 return -EBUSY;
b481de9c 112
763cc3bf
JB		 113 if (!ctx->is_active)
114 return 0;
115
b481de9c 116 /* always get timestamp with Rx frame */
246ed355 117 ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
b481de9c 118
246ed355 119 ret = iwl_check_rxon_cmd(priv, ctx);
43d59b32 120 if (ret) {
15b1687c 121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 122 return -EINVAL;
123 }
124
0924e519
WYG		 125 /*
126 * receive commit_rxon request
127 * abort any previous channel switch if still in process
128 */
129 if (priv->switch_rxon.switch_in_progress &&
246ed355 130 (priv->switch_rxon.channel != ctx->staging.channel)) {
0924e519
WYG		 131 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
132 le16_to_cpu(priv->switch_rxon.channel));
79d07325 133 iwl_chswitch_done(priv, false);
0924e519
WYG		 134 }
135
b481de9c 136 /* If we don't need to send a full RXON, we can use
5b9f8cd3 137 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 138 * and other flags for the current radio configuration. */
246ed355
JB		 139 if (!iwl_full_rxon_required(priv, ctx)) {
140 ret = iwl_send_rxon_assoc(priv, ctx);
43d59b32 141 if (ret) {
15b1687c 142 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 143 return ret;
b481de9c
ZY		 144 }
145
246ed355
JB		 146 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
147 iwl_print_rx_config_cmd(priv, ctx);
b481de9c
ZY		 148 return 0;
149 }
150
b481de9c
ZY		 151 /* If we are currently associated and the new config requires
152 * an RXON_ASSOC and the new config wants the associated mask enabled,
153 * we must clear the associated from the active configuration
154 * before we apply the new config */
246ed355 155 if (iwl_is_associated_ctx(ctx) && new_assoc) {
e1623446 156 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 157 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
158
8f2d3d2a 159 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355
JB		 160 sizeof(struct iwl_rxon_cmd),
161 active_rxon);
b481de9c
ZY		 162
163 /* If the mask clearing failed then we set
164 * active_rxon back to what it was previously */
43d59b32 165 if (ret) {
b481de9c 166 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 167 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 168 return ret;
b481de9c 169 }
dcef732c
JB		 170 iwl_clear_ucode_stations(priv, ctx);
171 iwl_restore_stations(priv, ctx);
c10afb6e 172 ret = iwl_restore_default_wep_keys(priv, ctx);
335348b1
JB		 173 if (ret) {
174 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
175 return ret;
176 }
b481de9c
ZY		 177 }
178
e1623446 179 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 180 "* with%s RXON_FILTER_ASSOC_MSK\n"
181 "* channel = %d\n"
e174961c 182 "* bssid = %pM\n",
43d59b32 183 (new_assoc ? "" : "out"),
246ed355
JB		 184 le16_to_cpu(ctx->staging.channel),
185 ctx->staging.bssid_addr);
b481de9c 186
246ed355 187 iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
43d59b32 188
b01efe43 189 if (!old_assoc) {
2491fa42
JB		 190 /*
191 * First of all, before setting associated, we need to
192 * send RXON timing so the device knows about the DTIM
193 * period and other timing values
194 */
47313e34 195 ret = iwl_send_rxon_timing(priv, ctx);
2491fa42
JB		 196 if (ret) {
197 IWL_ERR(priv, "Error setting RXON timing!\n");
198 return ret;
199 }
200 }
201
52a02d15
JB		 202 if (priv->cfg->ops->hcmd->set_pan_params) {
203 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
204 if (ret)
205 return ret;
206 }
207
43d59b32 208 /* Apply the new configuration
7e246191
RC		 209 * RXON unassoc clears the station table in uCode so restoration of
210 * stations is needed after it (the RXON command) completes
43d59b32
EG		 211 */
212 if (!new_assoc) {
8f2d3d2a 213 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 214 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 215 if (ret) {
15b1687c 216 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 217 return ret;
218 }
91dd6c27 219 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
246ed355 220 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
dcef732c
JB		 221 iwl_clear_ucode_stations(priv, ctx);
222 iwl_restore_stations(priv, ctx);
c10afb6e 223 ret = iwl_restore_default_wep_keys(priv, ctx);
335348b1
JB		 224 if (ret) {
225 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
226 return ret;
227 }
b481de9c 228 }
9185159d 229 if (new_assoc) {
8f1d9687 230 priv->start_calib = 0;
43d59b32
EG		 231 /* Apply the new configuration
232 * RXON assoc doesn't clear the station table in uCode,
233 */
8f2d3d2a 234 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 235 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 236 if (ret) {
15b1687c 237 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 238 return ret;
239 }
246ed355 240 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
b481de9c 241 }
246ed355 242 iwl_print_rx_config_cmd(priv, ctx);
b481de9c 243
36da7d70
ZY		 244 iwl_init_sensitivity(priv);
245
246 /* If we issue a new RXON command which required a tune then we must
247 * send a new TXPOWER command or we won't be able to Tx any frames */
a25a66ac
SG		 248 ret = priv->cfg->ops->lib->send_tx_power(priv);
249 if (ret)
15b1687c 250 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
a25a66ac 251 return ret;
b481de9c
ZY		 252}
253
5b9f8cd3 254void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 255{
246ed355 256 struct iwl_rxon_context *ctx;
5da4b55f 257
246ed355
JB		 258 if (priv->cfg->ops->hcmd->set_rxon_chain) {
259 for_each_context(priv, ctx) {
260 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
261 iwlcore_commit_rxon(priv, ctx);
262 }
263 }
5da4b55f
MA		 264}
265
fcab423d 266static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 267{
268 struct list_head *element;
269
e1623446 270 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 271 priv->frames_count);
272
273 while (!list_empty(&priv->free_frames)) {
274 element = priv->free_frames.next;
275 list_del(element);
fcab423d 276 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 277 priv->frames_count--;
278 }
279
280 if (priv->frames_count) {
39aadf8c 281 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 282 priv->frames_count);
283 priv->frames_count = 0;
284 }
285}
286
fcab423d 287static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 288{
fcab423d 289 struct iwl_frame *frame;
b481de9c
ZY		 290 struct list_head *element;
291 if (list_empty(&priv->free_frames)) {
292 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
293 if (!frame) {
15b1687c 294 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 295 return NULL;
296 }
297
298 priv->frames_count++;
299 return frame;
300 }
301
302 element = priv->free_frames.next;
303 list_del(element);
fcab423d 304 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 305}
306
fcab423d 307static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 308{
309 memset(frame, 0, sizeof(*frame));
310 list_add(&frame->list, &priv->free_frames);
311}
312
47ff65c4 313static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
77834543
JB		 314 struct ieee80211_hdr *hdr,
315 int left)
b481de9c 316{
77834543
JB		 317 lockdep_assert_held(&priv->mutex);
318
12e934dc 319 if (!priv->beacon_skb)
b481de9c
ZY		 320 return 0;
321
12e934dc 322 if (priv->beacon_skb->len > left)
b481de9c
ZY		 323 return 0;
324
12e934dc 325 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
b481de9c 326
12e934dc 327 return priv->beacon_skb->len;
b481de9c
ZY		 328}
329
47ff65c4
DH		 330/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
331static void iwl_set_beacon_tim(struct iwl_priv *priv,
77834543
JB		 332 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
333 u8 *beacon, u32 frame_size)
47ff65c4
DH		 334{
335 u16 tim_idx;
336 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
337
338 /*
339 * The index is relative to frame start but we start looking at the
340 * variable-length part of the beacon.
341 */
342 tim_idx = mgmt->u.beacon.variable - beacon;
343
344 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
345 while ((tim_idx < (frame_size - 2)) &&
346 (beacon[tim_idx] != WLAN_EID_TIM))
347 tim_idx += beacon[tim_idx+1] + 2;
348
349 /* If TIM field was found, set variables */
350 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
351 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
352 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
353 } else
354 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
355}
356
5b9f8cd3 357static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 358 struct iwl_frame *frame)
4bf64efd
TW		 359{
360 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 361 u32 frame_size;
362 u32 rate_flags;
363 u32 rate;
364 /*
365 * We have to set up the TX command, the TX Beacon command, and the
366 * beacon contents.
367 */
4bf64efd 368
76d04815
JB		 369 lockdep_assert_held(&priv->mutex);
370
371 if (!priv->beacon_ctx) {
372 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
950094cb 373 return 0;
76d04815
JB		 374 }
375
47ff65c4 376 /* Initialize memory */
4bf64efd
TW		 377 tx_beacon_cmd = &frame->u.beacon;
378 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
379
47ff65c4 380 /* Set up TX beacon contents */
4bf64efd 381 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 382 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 383 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
384 return 0;
40bbfd4c
JB		 385 if (!frame_size)
386 return 0;
4bf64efd 387
47ff65c4 388 /* Set up TX command fields */
4bf64efd 389 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
76d04815 390 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
47ff65c4
DH		 391 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
392 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
393 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 394
47ff65c4
DH		 395 /* Set up TX beacon command fields */
396 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
77834543 397 frame_size);
4bf64efd 398
47ff65c4 399 /* Set up packet rate and flags */
76d04815 400 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
0e1654fa
JB		 401 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
402 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 403 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
404 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
405 rate_flags |= RATE_MCS_CCK_MSK;
406 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
407 rate_flags);
4bf64efd
TW		 408
409 return sizeof(*tx_beacon_cmd) + frame_size;
410}
5b9f8cd3 411static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 412{
fcab423d 413 struct iwl_frame *frame;
b481de9c
ZY		 414 unsigned int frame_size;
415 int rc;
b481de9c 416
fcab423d 417 frame = iwl_get_free_frame(priv);
b481de9c 418 if (!frame) {
15b1687c 419 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 420 "command.\n");
421 return -ENOMEM;
422 }
423
47ff65c4
DH		 424 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
425 if (!frame_size) {
426 IWL_ERR(priv, "Error configuring the beacon command\n");
427 iwl_free_frame(priv, frame);
428 return -EINVAL;
429 }
b481de9c 430
857485c0 431 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 432 &frame->u.cmd[0]);
433
fcab423d 434 iwl_free_frame(priv, frame);
b481de9c
ZY		 435
436 return rc;
437}
438
7aaa1d79
SO		 439static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
440{
441 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
442
443 dma_addr_t addr = get_unaligned_le32(&tb->lo);
444 if (sizeof(dma_addr_t) > sizeof(u32))
445 addr |=
446 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
447
448 return addr;
449}
450
451static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
452{
453 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
454
455 return le16_to_cpu(tb->hi_n_len) >> 4;
456}
457
458static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
459 dma_addr_t addr, u16 len)
460{
461 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
462 u16 hi_n_len = len << 4;
463
464 put_unaligned_le32(addr, &tb->lo);
465 if (sizeof(dma_addr_t) > sizeof(u32))
466 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
467
468 tb->hi_n_len = cpu_to_le16(hi_n_len);
469
470 tfd->num_tbs = idx + 1;
471}
472
473static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
474{
475 return tfd->num_tbs & 0x1f;
476}
477
478/**
479 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
480 * @priv - driver private data
481 * @txq - tx queue
482 *
483 * Does NOT advance any TFD circular buffer read/write indexes
484 * Does NOT free the TFD itself (which is within circular buffer)
485 */
486void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
487{
59606ffa 488 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 489 struct iwl_tfd *tfd;
490 struct pci_dev *dev = priv->pci_dev;
491 int index = txq->q.read_ptr;
492 int i;
493 int num_tbs;
494
495 tfd = &tfd_tmp[index];
496
497 /* Sanity check on number of chunks */
498 num_tbs = iwl_tfd_get_num_tbs(tfd);
499
500 if (num_tbs >= IWL_NUM_OF_TBS) {
501 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
502 /* @todo issue fatal error, it is quite serious situation */
503 return;
504 }
505
506 /* Unmap tx_cmd */
507 if (num_tbs)
508 pci_unmap_single(dev,
2e724443
FT		 509 dma_unmap_addr(&txq->meta[index], mapping),
510 dma_unmap_len(&txq->meta[index], len),
96891cee 511 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 512
513 /* Unmap chunks, if any. */
ff0d91c3 514 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 515 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
516 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
517
ff0d91c3
JB		 518 /* free SKB */
519 if (txq->txb) {
520 struct sk_buff *skb;
6f80240e 521
ff0d91c3 522 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 523
ff0d91c3
JB		 524 /* can be called from irqs-disabled context */
525 if (skb) {
526 dev_kfree_skb_any(skb);
527 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 528 }
529 }
530}
531
532int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
533 struct iwl_tx_queue *txq,
534 dma_addr_t addr, u16 len,
535 u8 reset, u8 pad)
536{
537 struct iwl_queue *q;
59606ffa 538 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 539 u32 num_tbs;
540
541 q = &txq->q;
59606ffa
SO		 542 tfd_tmp = (struct iwl_tfd *)txq->tfds;
543 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 544
545 if (reset)
546 memset(tfd, 0, sizeof(*tfd));
547
548 num_tbs = iwl_tfd_get_num_tbs(tfd);
549
550 /* Each TFD can point to a maximum 20 Tx buffers */
551 if (num_tbs >= IWL_NUM_OF_TBS) {
552 IWL_ERR(priv, "Error can not send more than %d chunks\n",
553 IWL_NUM_OF_TBS);
554 return -EINVAL;
555 }
556
557 BUG_ON(addr & ~DMA_BIT_MASK(36));
558 if (unlikely(addr & ~IWL_TX_DMA_MASK))
559 IWL_ERR(priv, "Unaligned address = %llx\n",
560 (unsigned long long)addr);
561
562 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
563
564 return 0;
565}
566
a8e74e27
SO		 567/*
568 * Tell nic where to find circular buffer of Tx Frame Descriptors for
569 * given Tx queue, and enable the DMA channel used for that queue.
570 *
571 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
572 * channels supported in hardware.
573 */
574int iwl_hw_tx_queue_init(struct iwl_priv *priv,
575 struct iwl_tx_queue *txq)
576{
a8e74e27
SO		 577 int txq_id = txq->q.id;
578
a8e74e27
SO		 579 /* Circular buffer (TFD queue in DRAM) physical base address */
580 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
581 txq->q.dma_addr >> 8);
582
a8e74e27
SO		 583 return 0;
584}
585
b481de9c
ZY		 586/******************************************************************************
587 *
588 * Generic RX handler implementations
589 *
590 ******************************************************************************/
885ba202
TW		 591static void iwl_rx_reply_alive(struct iwl_priv *priv,
592 struct iwl_rx_mem_buffer *rxb)
b481de9c 593{
2f301227 594 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 595 struct iwl_alive_resp *palive;
b481de9c
ZY		 596 struct delayed_work *pwork;
597
598 palive = &pkt->u.alive_frame;
599
e1623446 600 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 601 "0x%01X 0x%01X\n",
602 palive->is_valid, palive->ver_type,
603 palive->ver_subtype);
604
605 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 606 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 607 memcpy(&priv->card_alive_init,
608 &pkt->u.alive_frame,
885ba202 609 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 610 pwork = &priv->init_alive_start;
611 } else {
e1623446 612 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 613 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 614 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 615 pwork = &priv->alive_start;
616 }
617
618 /* We delay the ALIVE response by 5ms to
619 * give the HW RF Kill time to activate... */
620 if (palive->is_valid == UCODE_VALID_OK)
621 queue_delayed_work(priv->workqueue, pwork,
622 msecs_to_jiffies(5));
623 else
39aadf8c 624 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 625}
626
5b9f8cd3 627static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 628{
c79dd5b5
TW		 629 struct iwl_priv *priv =
630 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 631 struct sk_buff *beacon;
632
76d04815
JB		 633 mutex_lock(&priv->mutex);
634 if (!priv->beacon_ctx) {
635 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
636 goto out;
637 }
b481de9c 638
60744f62
JB		 639 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
640 /*
641 * The ucode will send beacon notifications even in
642 * IBSS mode, but we don't want to process them. But
643 * we need to defer the type check to here due to
644 * requiring locking around the beacon_ctx access.
645 */
646 goto out;
647 }
648
76d04815
JB		 649 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
650 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
b481de9c 651 if (!beacon) {
77834543 652 IWL_ERR(priv, "update beacon failed -- keeping old\n");
76d04815 653 goto out;
b481de9c
ZY		 654 }
655
b481de9c 656 /* new beacon skb is allocated every time; dispose previous.*/
77834543 657 dev_kfree_skb(priv->beacon_skb);
b481de9c 658
12e934dc 659 priv->beacon_skb = beacon;
b481de9c 660
5b9f8cd3 661 iwl_send_beacon_cmd(priv);
76d04815
JB		 662 out:
663 mutex_unlock(&priv->mutex);
b481de9c
ZY		 664}
665
fbba9410
WYG		 666static void iwl_bg_bt_runtime_config(struct work_struct *work)
667{
668 struct iwl_priv *priv =
669 container_of(work, struct iwl_priv, bt_runtime_config);
670
671 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
672 return;
673
674 /* dont send host command if rf-kill is on */
675 if (!iwl_is_ready_rf(priv))
676 return;
677 priv->cfg->ops->hcmd->send_bt_config(priv);
678}
679
bee008b7
WYG		 680static void iwl_bg_bt_full_concurrency(struct work_struct *work)
681{
682 struct iwl_priv *priv =
683 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 684 struct iwl_rxon_context *ctx;
bee008b7
WYG		 685
686 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
687 return;
688
689 /* dont send host command if rf-kill is on */
690 if (!iwl_is_ready_rf(priv))
691 return;
692
693 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
694 priv->bt_full_concurrent ?
695 "full concurrency" : "3-wire");
696
697 /*
698 * LQ & RXON updated cmds must be sent before BT Config cmd
699 * to avoid 3-wire collisions
700 */
246ed355
JB		 701 mutex_lock(&priv->mutex);
702 for_each_context(priv, ctx) {
703 if (priv->cfg->ops->hcmd->set_rxon_chain)
704 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
705 iwlcore_commit_rxon(priv, ctx);
706 }
707 mutex_unlock(&priv->mutex);
bee008b7
WYG		 708
709 priv->cfg->ops->hcmd->send_bt_config(priv);
710}
711
4e39317d 712/**
5b9f8cd3 713 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 714 *
715 * This callback is provided in order to send a statistics request.
716 *
717 * This timer function is continually reset to execute within
718 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
719 * was received. We need to ensure we receive the statistics in order
720 * to update the temperature used for calibrating the TXPOWER.
721 */
5b9f8cd3 722static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 723{
724 struct iwl_priv *priv = (struct iwl_priv *)data;
725
726 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
727 return;
728
61780ee3
MA		 729 /* dont send host command if rf-kill is on */
730 if (!iwl_is_ready_rf(priv))
731 return;
732
ef8d5529 733 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 734}
735
a9e1cb6a
WYG		 736
737static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
738 u32 start_idx, u32 num_events,
739 u32 mode)
740{
741 u32 i;
742 u32 ptr; /* SRAM byte address of log data */
743 u32 ev, time, data; /* event log data */
744 unsigned long reg_flags;
745
746 if (mode == 0)
747 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
748 else
749 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
750
751 /* Make sure device is powered up for SRAM reads */
752 spin_lock_irqsave(&priv->reg_lock, reg_flags);
753 if (iwl_grab_nic_access(priv)) {
754 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
755 return;
756 }
757
758 /* Set starting address; reads will auto-increment */
759 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
760 rmb();
761
762 /*
763 * "time" is actually "data" for mode 0 (no timestamp).
764 * place event id # at far right for easier visual parsing.
765 */
766 for (i = 0; i < num_events; i++) {
767 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
768 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
769 if (mode == 0) {
770 trace_iwlwifi_dev_ucode_cont_event(priv,
771 0, time, ev);
772 } else {
773 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
774 trace_iwlwifi_dev_ucode_cont_event(priv,
775 time, data, ev);
776 }
777 }
778 /* Allow device to power down */
779 iwl_release_nic_access(priv);
780 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
781}
782
875295f1 783static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 784{
785 u32 capacity; /* event log capacity in # entries */
786 u32 base; /* SRAM byte address of event log header */
787 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
788 u32 num_wraps; /* # times uCode wrapped to top of log */
789 u32 next_entry; /* index of next entry to be written by uCode */
790
791 if (priv->ucode_type == UCODE_INIT)
792 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
793 else
794 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
795 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
796 capacity = iwl_read_targ_mem(priv, base);
797 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
798 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
799 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
800 } else
801 return;
802
803 if (num_wraps == priv->event_log.num_wraps) {
804 iwl_print_cont_event_trace(priv,
805 base, priv->event_log.next_entry,
806 next_entry - priv->event_log.next_entry,
807 mode);
808 priv->event_log.non_wraps_count++;
809 } else {
810 if ((num_wraps - priv->event_log.num_wraps) > 1)
811 priv->event_log.wraps_more_count++;
812 else
813 priv->event_log.wraps_once_count++;
814 trace_iwlwifi_dev_ucode_wrap_event(priv,
815 num_wraps - priv->event_log.num_wraps,
816 next_entry, priv->event_log.next_entry);
817 if (next_entry < priv->event_log.next_entry) {
818 iwl_print_cont_event_trace(priv, base,
819 priv->event_log.next_entry,
820 capacity - priv->event_log.next_entry,
821 mode);
822
823 iwl_print_cont_event_trace(priv, base, 0,
824 next_entry, mode);
825 } else {
826 iwl_print_cont_event_trace(priv, base,
827 next_entry, capacity - next_entry,
828 mode);
829
830 iwl_print_cont_event_trace(priv, base, 0,
831 next_entry, mode);
832 }
833 }
834 priv->event_log.num_wraps = num_wraps;
835 priv->event_log.next_entry = next_entry;
836}
837
838/**
839 * iwl_bg_ucode_trace - Timer callback to log ucode event
840 *
841 * The timer is continually set to execute every
842 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
843 * this function is to perform continuous uCode event logging operation
844 * if enabled
845 */
846static void iwl_bg_ucode_trace(unsigned long data)
847{
848 struct iwl_priv *priv = (struct iwl_priv *)data;
849
850 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
851 return;
852
853 if (priv->event_log.ucode_trace) {
854 iwl_continuous_event_trace(priv);
855 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
856 mod_timer(&priv->ucode_trace,
857 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
858 }
859}
860
5b9f8cd3 861static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 862 struct iwl_rx_mem_buffer *rxb)
b481de9c 863{
2f301227 864 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 865 struct iwl4965_beacon_notif *beacon =
866 (struct iwl4965_beacon_notif *)pkt->u.raw;
a85d7cca 867#ifdef CONFIG_IWLWIFI_DEBUG
e7d326ac 868 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 869
e1623446 870 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 871 "tsf %d %d rate %d\n",
25a6572c 872 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 873 beacon->beacon_notify_hdr.failure_frame,
874 le32_to_cpu(beacon->ibss_mgr_status),
875 le32_to_cpu(beacon->high_tsf),
876 le32_to_cpu(beacon->low_tsf), rate);
877#endif
878
a85d7cca
JB		 879 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
880
60744f62 881 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 882 queue_work(priv->workqueue, &priv->beacon_update);
883}
884
b481de9c
ZY		 885/* Handle notification from uCode that card's power state is changing
886 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 887static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 888 struct iwl_rx_mem_buffer *rxb)
b481de9c 889{
2f301227 890 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 891 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
892 unsigned long status = priv->status;
893
3a41bbd5 894 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 895 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 896 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
897 (flags & CT_CARD_DISABLED) ?
898 "Reached" : "Not reached");
b481de9c
ZY		 899
900 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 901 CT_CARD_DISABLED)) {
b481de9c 902
3395f6e9 903 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 904 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
905
a8b50a0a
MA		 906 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
907 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 908
909 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 910 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 911 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 912 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 913 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 914 }
3a41bbd5 915 if (flags & CT_CARD_DISABLED)
39b73fb1 916 iwl_tt_enter_ct_kill(priv);
b481de9c 917 }
3a41bbd5 918 if (!(flags & CT_CARD_DISABLED))
39b73fb1 919 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 920
921 if (flags & HW_CARD_DISABLED)
922 set_bit(STATUS_RF_KILL_HW, &priv->status);
923 else
924 clear_bit(STATUS_RF_KILL_HW, &priv->status);
925
926
b481de9c 927 if (!(flags & RXON_CARD_DISABLED))
2a421b91 928 iwl_scan_cancel(priv);
b481de9c
ZY		 929
930 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 931 test_bit(STATUS_RF_KILL_HW, &priv->status)))
932 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
933 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 934 else
935 wake_up_interruptible(&priv->wait_command_queue);
936}
937
65550636
WYG		 938static void iwl_bg_tx_flush(struct work_struct *work)
939{
940 struct iwl_priv *priv =
941 container_of(work, struct iwl_priv, tx_flush);
942
943 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
944 return;
945
946 /* do nothing if rf-kill is on */
947 if (!iwl_is_ready_rf(priv))
948 return;
949
950 if (priv->cfg->ops->lib->txfifo_flush) {
951 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
952 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
953 }
954}
955
b481de9c 956/**
5b9f8cd3 957 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 958 *
959 * Setup the RX handlers for each of the reply types sent from the uCode
960 * to the host.
961 *
962 * This function chains into the hardware specific files for them to setup
963 * any hardware specific handlers as well.
964 */
653fa4a0 965static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 966{
885ba202 967 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 968 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
969 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 970 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
971 iwl_rx_spectrum_measure_notif;
5b9f8cd3 972 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 973 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 974 iwl_rx_pm_debug_statistics_notif;
975 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 976
9fbab516
BC		 977 /*
978 * The same handler is used for both the REPLY to a discrete
979 * statistics request from the host as well as for the periodic
980 * statistics notifications (after received beacons) from the uCode.
b481de9c 981 */
ef8d5529 982 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 983 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 984
985 iwl_setup_rx_scan_handlers(priv);
986
37a44211 987 /* status change handler */
5b9f8cd3 988 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 989
c1354754
TW		 990 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
991 iwl_rx_missed_beacon_notif;
37a44211 992 /* Rx handlers */
8d801080
WYG		 993 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
994 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 995 /* block ack */
74bcdb33 996 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 997 /* Set up hardware specific Rx handlers */
d4789efe 998 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 999}
1000
b481de9c 1001/**
a55360e4 1002 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 1003 *
1004 * Uses the priv->rx_handlers callback function array to invoke
1005 * the appropriate handlers, including command responses,
1006 * frame-received notifications, and other notifications.
1007 */
a55360e4 1008void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 1009{
a55360e4 1010 struct iwl_rx_mem_buffer *rxb;
db11d634 1011 struct iwl_rx_packet *pkt;
a55360e4 1012 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 1013 u32 r, i;
1014 int reclaim;
1015 unsigned long flags;
5c0eef96 1016 u8 fill_rx = 0;
d68ab680 1017 u32 count = 8;
4752c93c 1018 int total_empty;
b481de9c 1019
6440adb5
BC		 1020 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1021 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 1022 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 1023 i = rxq->read;
1024
1025 /* Rx interrupt, but nothing sent from uCode */
1026 if (i == r)
e1623446 1027 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 1028
4752c93c 1029 /* calculate total frames need to be restock after handling RX */
7300515d 1030 total_empty = r - rxq->write_actual;
4752c93c
MA		 1031 if (total_empty < 0)
1032 total_empty += RX_QUEUE_SIZE;
1033
1034 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 1035 fill_rx = 1;
1036
b481de9c 1037 while (i != r) {
f4989d9b
JB		 1038 int len;
1039
b481de9c
ZY		 1040 rxb = rxq->queue[i];
1041
9fbab516 1042 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 1043 * then a bug has been introduced in the queue refilling
1044 * routines -- catch it here */
1045 BUG_ON(rxb == NULL);
1046
1047 rxq->queue[i] = NULL;
1048
2f301227
ZY		 1049 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1050 PAGE_SIZE << priv->hw_params.rx_page_order,
1051 PCI_DMA_FROMDEVICE);
1052 pkt = rxb_addr(rxb);
b481de9c 1053
f4989d9b
JB		 1054 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1055 len += sizeof(u32); /* account for status word */
1056 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 1057
b481de9c
ZY		 1058 /* Reclaim a command buffer only if this packet is a response
1059 * to a (driver-originated) command.
1060 * If the packet (e.g. Rx frame) originated from uCode,
1061 * there is no command buffer to reclaim.
1062 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1063 * but apparently a few don't get set; catch them here. */
1064 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1065 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 1066 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 1067 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 1068 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 1069 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1070 (pkt->hdr.cmd != REPLY_TX);
1071
1072 /* Based on type of command response or notification,
1073 * handle those that need handling via function in
5b9f8cd3 1074 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 1075 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1076 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1077 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 1078 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1079 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 1080 } else {
1081 /* No handling needed */
e1623446 1082 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1083 "r %d i %d No handler needed for %s, 0x%02x\n",
1084 r, i, get_cmd_string(pkt->hdr.cmd),
1085 pkt->hdr.cmd);
1086 }
1087
29b1b268
ZY		 1088 /*
1089 * XXX: After here, we should always check rxb->page
1090 * against NULL before touching it or its virtual
1091 * memory (pkt). Because some rx_handler might have
1092 * already taken or freed the pages.
1093 */
1094
b481de9c 1095 if (reclaim) {
2f301227
ZY		 1096 /* Invoke any callbacks, transfer the buffer to caller,
1097 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1098 * as we reclaim the driver command queue */
29b1b268 1099 if (rxb->page)
17b88929 1100 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1101 else
39aadf8c 1102 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1103 }
1104
7300515d
ZY		 1105 /* Reuse the page if possible. For notification packets and
1106 * SKBs that fail to Rx correctly, add them back into the
1107 * rx_free list for reuse later. */
1108 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1109 if (rxb->page != NULL) {
7300515d
ZY		 1110 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1111 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1112 PCI_DMA_FROMDEVICE);
1113 list_add_tail(&rxb->list, &rxq->rx_free);
1114 rxq->free_count++;
1115 } else
1116 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1117
b481de9c 1118 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1119
b481de9c 1120 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1121 /* If there are a lot of unused frames,
1122 * restock the Rx queue so ucode wont assert. */
1123 if (fill_rx) {
1124 count++;
1125 if (count >= 8) {
7300515d 1126 rxq->read = i;
54b81550 1127 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1128 count = 0;
1129 }
1130 }
b481de9c
ZY		 1131 }
1132
1133 /* Backtrack one entry */
7300515d 1134 rxq->read = i;
4752c93c 1135 if (fill_rx)
54b81550 1136 iwlagn_rx_replenish_now(priv);
4752c93c 1137 else
54b81550 1138 iwlagn_rx_queue_restock(priv);
a55360e4 1139}
a55360e4 1140
0359facc
MA		 1141/* call this function to flush any scheduled tasklet */
1142static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1143{
a96a27f9 1144 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1145 synchronize_irq(priv->pci_dev->irq);
1146 tasklet_kill(&priv->irq_tasklet);
1147}
1148
ef850d7c 1149static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1150{
1151 u32 inta, handled = 0;
1152 u32 inta_fh;
1153 unsigned long flags;
c2e61da2 1154 u32 i;
0a6857e7 1155#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1156 u32 inta_mask;
1157#endif
1158
1159 spin_lock_irqsave(&priv->lock, flags);
1160
1161 /* Ack/clear/reset pending uCode interrupts.
1162 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1163 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1164 inta = iwl_read32(priv, CSR_INT);
1165 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1166
1167 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1168 * Any new interrupts that happen after this, either while we're
1169 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1170 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1171 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1172
0a6857e7 1173#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1174 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1175 /* just for debug */
3395f6e9 1176 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1177 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1178 inta, inta_mask, inta_fh);
1179 }
1180#endif
1181
2f301227
ZY		 1182 spin_unlock_irqrestore(&priv->lock, flags);
1183
b481de9c
ZY		 1184 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1185 * atomic, make sure that inta covers all the interrupts that
1186 * we've discovered, even if FH interrupt came in just after
1187 * reading CSR_INT. */
6f83eaa1 1188 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1189 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1190 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1191 inta |= CSR_INT_BIT_FH_TX;
1192
1193 /* Now service all interrupt bits discovered above. */
1194 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1195 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1196
1197 /* Tell the device to stop sending interrupts */
5b9f8cd3 1198 iwl_disable_interrupts(priv);
b481de9c 1199
a83b9141 1200 priv->isr_stats.hw++;
5b9f8cd3 1201 iwl_irq_handle_error(priv);
b481de9c
ZY		 1202
1203 handled |= CSR_INT_BIT_HW_ERR;
1204
b481de9c
ZY		 1205 return;
1206 }
1207
0a6857e7 1208#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1209 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1210 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1211 if (inta & CSR_INT_BIT_SCD) {
e1623446 1212 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1213 "the frame/frames.\n");
a83b9141
WYG		 1214 priv->isr_stats.sch++;
1215 }
b481de9c
ZY		 1216
1217 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1218 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1219 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1220 priv->isr_stats.alive++;
1221 }
b481de9c
ZY		 1222 }
1223#endif
1224 /* Safely ignore these bits for debug checks below */
25c03d8e 1225 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1226
9fbab516 1227 /* HW RF KILL switch toggled */
b481de9c
ZY		 1228 if (inta & CSR_INT_BIT_RF_KILL) {
1229 int hw_rf_kill = 0;
3395f6e9 1230 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1231 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1232 hw_rf_kill = 1;
1233
4c423a2b 1234 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1235 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1236
a83b9141
WYG		 1237 priv->isr_stats.rfkill++;
1238
a9efa652 1239 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1240 * the driver allows loading the ucode even if the radio
1241 * is killed. Hence update the killswitch state here. The
1242 * rfkill handler will care about restarting if needed.
a9efa652 1243 */
6cd0b1cb
HS		 1244 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1245 if (hw_rf_kill)
1246 set_bit(STATUS_RF_KILL_HW, &priv->status);
1247 else
1248 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1249 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1250 }
b481de9c
ZY		 1251
1252 handled |= CSR_INT_BIT_RF_KILL;
1253 }
1254
9fbab516 1255 /* Chip got too hot and stopped itself */
b481de9c 1256 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1257 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1258 priv->isr_stats.ctkill++;
b481de9c
ZY		 1259 handled |= CSR_INT_BIT_CT_KILL;
1260 }
1261
1262 /* Error detected by uCode */
1263 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1264 IWL_ERR(priv, "Microcode SW error detected. "
1265 " Restarting 0x%X.\n", inta);
a83b9141 1266 priv->isr_stats.sw++;
5b9f8cd3 1267 iwl_irq_handle_error(priv);
b481de9c
ZY		 1268 handled |= CSR_INT_BIT_SW_ERR;
1269 }
1270
c2e61da2
BC		 1271 /*
1272 * uCode wakes up after power-down sleep.
1273 * Tell device about any new tx or host commands enqueued,
1274 * and about any Rx buffers made available while asleep.
1275 */
b481de9c 1276 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1277 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1278 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1279 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1280 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1281 priv->isr_stats.wakeup++;
b481de9c
ZY		 1282 handled |= CSR_INT_BIT_WAKEUP;
1283 }
1284
1285 /* All uCode command responses, including Tx command responses,
1286 * Rx "responses" (frame-received notification), and other
1287 * notifications from uCode come through here*/
1288 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1289 iwl_rx_handle(priv);
a83b9141 1290 priv->isr_stats.rx++;
b481de9c
ZY		 1291 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1292 }
1293
c72cd19f 1294 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1295 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1296 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1297 priv->isr_stats.tx++;
b481de9c 1298 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1299 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1300 priv->ucode_write_complete = 1;
1301 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1302 }
1303
a83b9141 1304 if (inta & ~handled) {
15b1687c 1305 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1306 priv->isr_stats.unhandled++;
1307 }
b481de9c 1308
40cefda9 1309 if (inta & ~(priv->inta_mask)) {
39aadf8c 1310 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1311 inta & ~priv->inta_mask);
39aadf8c 1312 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1313 }
1314
1315 /* Re-enable all interrupts */
0359facc
MA		 1316 /* only Re-enable if diabled by irq */
1317 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1318 iwl_enable_interrupts(priv);
b481de9c 1319
0a6857e7 1320#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1321 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1322 inta = iwl_read32(priv, CSR_INT);
1323 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1324 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1325 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1326 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1327 }
1328#endif
b481de9c
ZY		 1329}
1330
ef850d7c
MA		 1331/* tasklet for iwlagn interrupt */
1332static void iwl_irq_tasklet(struct iwl_priv *priv)
1333{
1334 u32 inta = 0;
1335 u32 handled = 0;
1336 unsigned long flags;
8756990f 1337 u32 i;
ef850d7c
MA		 1338#ifdef CONFIG_IWLWIFI_DEBUG
1339 u32 inta_mask;
1340#endif
1341
1342 spin_lock_irqsave(&priv->lock, flags);
1343
1344 /* Ack/clear/reset pending uCode interrupts.
1345 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1346 */
48a6be6a
SZ		 1347 /* There is a hardware bug in the interrupt mask function that some
1348 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1349 * they are disabled in the CSR_INT_MASK register. Furthermore the
1350 * ICT interrupt handling mechanism has another bug that might cause
1351 * these unmasked interrupts fail to be detected. We workaround the
1352 * hardware bugs here by ACKing all the possible interrupts so that
1353 * interrupt coalescing can still be achieved.
1354 */
4a35ecf8 1355 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1356
a4c8b2a6 1357 inta = priv->_agn.inta;
ef850d7c
MA		 1358
1359#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1360 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1361 /* just for debug */
1362 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1363 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1364 inta, inta_mask);
1365 }
1366#endif
2f301227
ZY		 1367
1368 spin_unlock_irqrestore(&priv->lock, flags);
1369
a4c8b2a6
JB		 1370 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1371 priv->_agn.inta = 0;
ef850d7c
MA		 1372
1373 /* Now service all interrupt bits discovered above. */
1374 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1375 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1376
1377 /* Tell the device to stop sending interrupts */
1378 iwl_disable_interrupts(priv);
1379
1380 priv->isr_stats.hw++;
1381 iwl_irq_handle_error(priv);
1382
1383 handled |= CSR_INT_BIT_HW_ERR;
1384
ef850d7c
MA		 1385 return;
1386 }
1387
1388#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1389 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1390 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1391 if (inta & CSR_INT_BIT_SCD) {
1392 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1393 "the frame/frames.\n");
1394 priv->isr_stats.sch++;
1395 }
1396
1397 /* Alive notification via Rx interrupt will do the real work */
1398 if (inta & CSR_INT_BIT_ALIVE) {
1399 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1400 priv->isr_stats.alive++;
1401 }
1402 }
1403#endif
1404 /* Safely ignore these bits for debug checks below */
1405 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1406
1407 /* HW RF KILL switch toggled */
1408 if (inta & CSR_INT_BIT_RF_KILL) {
1409 int hw_rf_kill = 0;
1410 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1411 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1412 hw_rf_kill = 1;
1413
4c423a2b 1414 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1415 hw_rf_kill ? "disable radio" : "enable radio");
1416
1417 priv->isr_stats.rfkill++;
1418
1419 /* driver only loads ucode once setting the interface up.
1420 * the driver allows loading the ucode even if the radio
1421 * is killed. Hence update the killswitch state here. The
1422 * rfkill handler will care about restarting if needed.
1423 */
1424 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1425 if (hw_rf_kill)
1426 set_bit(STATUS_RF_KILL_HW, &priv->status);
1427 else
1428 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1429 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1430 }
1431
1432 handled |= CSR_INT_BIT_RF_KILL;
1433 }
1434
1435 /* Chip got too hot and stopped itself */
1436 if (inta & CSR_INT_BIT_CT_KILL) {
1437 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1438 priv->isr_stats.ctkill++;
1439 handled |= CSR_INT_BIT_CT_KILL;
1440 }
1441
1442 /* Error detected by uCode */
1443 if (inta & CSR_INT_BIT_SW_ERR) {
1444 IWL_ERR(priv, "Microcode SW error detected. "
1445 " Restarting 0x%X.\n", inta);
1446 priv->isr_stats.sw++;
ef850d7c
MA		 1447 iwl_irq_handle_error(priv);
1448 handled |= CSR_INT_BIT_SW_ERR;
1449 }
1450
1451 /* uCode wakes up after power-down sleep */
1452 if (inta & CSR_INT_BIT_WAKEUP) {
1453 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1454 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1455 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1456 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1457
1458 priv->isr_stats.wakeup++;
1459
1460 handled |= CSR_INT_BIT_WAKEUP;
1461 }
1462
1463 /* All uCode command responses, including Tx command responses,
1464 * Rx "responses" (frame-received notification), and other
1465 * notifications from uCode come through here*/
40cefda9
MA		 1466 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1467 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1468 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1469 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1470 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1471 iwl_write32(priv, CSR_FH_INT_STATUS,
1472 CSR49_FH_INT_RX_MASK);
1473 }
1474 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1475 handled |= CSR_INT_BIT_RX_PERIODIC;
1476 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1477 }
1478 /* Sending RX interrupt require many steps to be done in the
1479 * the device:
1480 * 1- write interrupt to current index in ICT table.
1481 * 2- dma RX frame.
1482 * 3- update RX shared data to indicate last write index.
1483 * 4- send interrupt.
1484 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1485 * but the shared data changes does not reflect this;
1486 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1487 */
74ba67ed
BC		 1488
1489 /* Disable periodic interrupt; we use it as just a one-shot. */
1490 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1491 CSR_INT_PERIODIC_DIS);
ef850d7c 1492 iwl_rx_handle(priv);
74ba67ed
BC		 1493
1494 /*
1495 * Enable periodic interrupt in 8 msec only if we received
1496 * real RX interrupt (instead of just periodic int), to catch
1497 * any dangling Rx interrupt. If it was just the periodic
1498 * interrupt, there was no dangling Rx activity, and no need
1499 * to extend the periodic interrupt; one-shot is enough.
1500 */
40cefda9 1501 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1502 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1503 CSR_INT_PERIODIC_ENA);
1504
ef850d7c 1505 priv->isr_stats.rx++;
ef850d7c
MA		 1506 }
1507
c72cd19f 1508 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1509 if (inta & CSR_INT_BIT_FH_TX) {
1510 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1511 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1512 priv->isr_stats.tx++;
1513 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1514 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1515 priv->ucode_write_complete = 1;
1516 wake_up_interruptible(&priv->wait_command_queue);
1517 }
1518
1519 if (inta & ~handled) {
1520 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1521 priv->isr_stats.unhandled++;
1522 }
1523
40cefda9 1524 if (inta & ~(priv->inta_mask)) {
ef850d7c 1525 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1526 inta & ~priv->inta_mask);
ef850d7c
MA		 1527 }
1528
ef850d7c
MA		 1529 /* Re-enable all interrupts */
1530 /* only Re-enable if diabled by irq */
1531 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1532 iwl_enable_interrupts(priv);
ef850d7c
MA		 1533}
1534
872c8ddc
WYG		 1535/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1536#define ACK_CNT_RATIO (50)
1537#define BA_TIMEOUT_CNT (5)
1538#define BA_TIMEOUT_MAX (16)
1539
1540/**
1541 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1542 *
1543 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1544 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1545 * operation state.
1546 */
1547bool iwl_good_ack_health(struct iwl_priv *priv,
1548 struct iwl_rx_packet *pkt)
1549{
1550 bool rc = true;
1551 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1552 int ba_timeout_delta;
1553
1554 actual_ack_cnt_delta =
1555 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1556 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1557 expected_ack_cnt_delta =
1558 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1559 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1560 ba_timeout_delta =
1561 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1562 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1563 if ((priv->_agn.agg_tids_count > 0) &&
1564 (expected_ack_cnt_delta > 0) &&
1565 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1566 < ACK_CNT_RATIO) &&
1567 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1568 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1569 " expected_ack_cnt = %d\n",
1570 actual_ack_cnt_delta, expected_ack_cnt_delta);
1571
d73e4923
JB		 1572#ifdef CONFIG_IWLWIFI_DEBUGFS
1573 /*
1574 * This is ifdef'ed on DEBUGFS because otherwise the
1575 * statistics aren't available. If DEBUGFS is set but
1576 * DEBUG is not, these will just compile out.
1577 */
872c8ddc 1578 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1579 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1580 IWL_DEBUG_RADIO(priv,
1581 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1582 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1583 ack_or_ba_timeout_collision);
1584#endif
1585 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1586 ba_timeout_delta);
1587 if (!actual_ack_cnt_delta &&
1588 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1589 rc = false;
1590 }
1591 return rc;
1592}
1593
a83b9141 1594
7d47618a
EG		 1595/*****************************************************************************
1596 *
1597 * sysfs attributes
1598 *
1599 *****************************************************************************/
1600
1601#ifdef CONFIG_IWLWIFI_DEBUG
1602
1603/*
1604 * The following adds a new attribute to the sysfs representation
1605 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1606 * used for controlling the debug level.
1607 *
1608 * See the level definitions in iwl for details.
1609 *
1610 * The debug_level being managed using sysfs below is a per device debug
1611 * level that is used instead of the global debug level if it (the per
1612 * device debug level) is set.
1613 */
1614static ssize_t show_debug_level(struct device *d,
1615 struct device_attribute *attr, char *buf)
1616{
1617 struct iwl_priv *priv = dev_get_drvdata(d);
1618 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1619}
1620static ssize_t store_debug_level(struct device *d,
1621 struct device_attribute *attr,
1622 const char *buf, size_t count)
1623{
1624 struct iwl_priv *priv = dev_get_drvdata(d);
1625 unsigned long val;
1626 int ret;
1627
1628 ret = strict_strtoul(buf, 0, &val);
1629 if (ret)
1630 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1631 else {
1632 priv->debug_level = val;
1633 if (iwl_alloc_traffic_mem(priv))
1634 IWL_ERR(priv,
1635 "Not enough memory to generate traffic log\n");
1636 }
1637 return strnlen(buf, count);
1638}
1639
1640static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1641 show_debug_level, store_debug_level);
1642
1643
1644#endif /* CONFIG_IWLWIFI_DEBUG */
1645
1646
1647static ssize_t show_temperature(struct device *d,
1648 struct device_attribute *attr, char *buf)
1649{
1650 struct iwl_priv *priv = dev_get_drvdata(d);
1651
1652 if (!iwl_is_alive(priv))
1653 return -EAGAIN;
1654
1655 return sprintf(buf, "%d\n", priv->temperature);
1656}
1657
1658static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1659
1660static ssize_t show_tx_power(struct device *d,
1661 struct device_attribute *attr, char *buf)
1662{
1663 struct iwl_priv *priv = dev_get_drvdata(d);
1664
1665 if (!iwl_is_ready_rf(priv))
1666 return sprintf(buf, "off\n");
1667 else
1668 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1669}
1670
1671static ssize_t store_tx_power(struct device *d,
1672 struct device_attribute *attr,
1673 const char *buf, size_t count)
1674{
1675 struct iwl_priv *priv = dev_get_drvdata(d);
1676 unsigned long val;
1677 int ret;
1678
1679 ret = strict_strtoul(buf, 10, &val);
1680 if (ret)
1681 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1682 else {
1683 ret = iwl_set_tx_power(priv, val, false);
1684 if (ret)
1685 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1686 ret);
1687 else
1688 ret = count;
1689 }
1690 return ret;
1691}
1692
1693static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1694
7d47618a
EG		 1695static struct attribute *iwl_sysfs_entries[] = {
1696 &dev_attr_temperature.attr,
1697 &dev_attr_tx_power.attr,
7d47618a
EG		 1698#ifdef CONFIG_IWLWIFI_DEBUG
1699 &dev_attr_debug_level.attr,
1700#endif
1701 NULL
1702};
1703
1704static struct attribute_group iwl_attribute_group = {
1705 .name = NULL, /* put in device directory */
1706 .attrs = iwl_sysfs_entries,
1707};
1708
b481de9c
ZY		 1709/******************************************************************************
1710 *
1711 * uCode download functions
1712 *
1713 ******************************************************************************/
1714
5b9f8cd3 1715static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1716{
98c92211
TW		 1717 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1718 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1719 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1720 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1721 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1722 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1723}
1724
5b9f8cd3 1725static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1726{
1727 /* Remove all resets to allow NIC to operate */
1728 iwl_write32(priv, CSR_RESET, 0);
1729}
1730
dd7a2509
JB		 1731struct iwlagn_ucode_capabilities {
1732 u32 max_probe_length;
6a822d06 1733 u32 standard_phy_calibration_size;
ece9c4ee 1734 bool pan;
dd7a2509 1735};
edcdf8b2 1736
b08dfd04 1737static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1738static int iwl_mac_setup_register(struct iwl_priv *priv,
1739 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1740
39396085
JS		 1741#define UCODE_EXPERIMENTAL_INDEX 100
1742#define UCODE_EXPERIMENTAL_TAG "exp"
1743
b08dfd04
JB		 1744static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1745{
1746 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1747 char tag[8];
b08dfd04 1748
39396085
JS		 1749 if (first) {
1750#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1751 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1752 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1753 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1754#endif
b08dfd04 1755 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1756 sprintf(tag, "%d", priv->fw_index);
1757 } else {
b08dfd04 1758 priv->fw_index--;
39396085
JS		 1759 sprintf(tag, "%d", priv->fw_index);
1760 }
b08dfd04
JB		 1761
1762 if (priv->fw_index < priv->cfg->ucode_api_min) {
1763 IWL_ERR(priv, "no suitable firmware found!\n");
1764 return -ENOENT;
1765 }
1766
39396085 1767 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1768
39396085
JS		 1769 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1770 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1771 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1772 priv->firmware_name);
1773
1774 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1775 &priv->pci_dev->dev, GFP_KERNEL, priv,
1776 iwl_ucode_callback);
1777}
1778
0e9a44dc
JB		 1779struct iwlagn_firmware_pieces {
1780 const void *inst, *data, *init, *init_data, *boot;
1781 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1782
1783 u32 build;
b2e640d4
JB		 1784
1785 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1786 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1787};
1788
1789static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1790 const struct firmware *ucode_raw,
1791 struct iwlagn_firmware_pieces *pieces)
1792{
1793 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1794 u32 api_ver, hdr_size;
1795 const u8 *src;
1796
1797 priv->ucode_ver = le32_to_cpu(ucode->ver);
1798 api_ver = IWL_UCODE_API(priv->ucode_ver);
1799
1800 switch (api_ver) {
1801 default:
1802 /*
1803 * 4965 doesn't revision the firmware file format
1804 * along with the API version, it always uses v1
1805 * file format.
1806 */
1807 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1808 CSR_HW_REV_TYPE_4965) {
1809 hdr_size = 28;
1810 if (ucode_raw->size < hdr_size) {
1811 IWL_ERR(priv, "File size too small!\n");
1812 return -EINVAL;
1813 }
1814 pieces->build = le32_to_cpu(ucode->u.v2.build);
1815 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1816 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1817 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1818 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1819 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1820 src = ucode->u.v2.data;
1821 break;
1822 }
1823 /* fall through for 4965 */
1824 case 0:
1825 case 1:
1826 case 2:
1827 hdr_size = 24;
1828 if (ucode_raw->size < hdr_size) {
1829 IWL_ERR(priv, "File size too small!\n");
1830 return -EINVAL;
1831 }
1832 pieces->build = 0;
1833 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1834 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1835 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1836 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1837 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1838 src = ucode->u.v1.data;
1839 break;
1840 }
1841
1842 /* Verify size of file vs. image size info in file's header */
1843 if (ucode_raw->size != hdr_size + pieces->inst_size +
1844 pieces->data_size + pieces->init_size +
1845 pieces->init_data_size + pieces->boot_size) {
1846
1847 IWL_ERR(priv,
1848 "uCode file size %d does not match expected size\n",
1849 (int)ucode_raw->size);
1850 return -EINVAL;
1851 }
1852
1853 pieces->inst = src;
1854 src += pieces->inst_size;
1855 pieces->data = src;
1856 src += pieces->data_size;
1857 pieces->init = src;
1858 src += pieces->init_size;
1859 pieces->init_data = src;
1860 src += pieces->init_data_size;
1861 pieces->boot = src;
1862 src += pieces->boot_size;
1863
1864 return 0;
1865}
1866
dd7a2509
JB		 1867static int iwlagn_wanted_ucode_alternative = 1;
1868
1869static int iwlagn_load_firmware(struct iwl_priv *priv,
1870 const struct firmware *ucode_raw,
1871 struct iwlagn_firmware_pieces *pieces,
1872 struct iwlagn_ucode_capabilities *capa)
1873{
1874 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1875 struct iwl_ucode_tlv *tlv;
1876 size_t len = ucode_raw->size;
1877 const u8 *data;
1878 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1879 u64 alternatives;
ad8d8333
WYG		 1880 u32 tlv_len;
1881 enum iwl_ucode_tlv_type tlv_type;
1882 const u8 *tlv_data;
dd7a2509 1883
ad8d8333
WYG		 1884 if (len < sizeof(*ucode)) {
1885 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1886 return -EINVAL;
ad8d8333 1887 }
dd7a2509 1888
ad8d8333
WYG		 1889 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1890 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1891 le32_to_cpu(ucode->magic));
dd7a2509 1892 return -EINVAL;
ad8d8333 1893 }
dd7a2509
JB		 1894
1895 /*
1896 * Check which alternatives are present, and "downgrade"
1897 * when the chosen alternative is not present, warning
1898 * the user when that happens. Some files may not have
1899 * any alternatives, so don't warn in that case.
1900 */
1901 alternatives = le64_to_cpu(ucode->alternatives);
1902 tmp = wanted_alternative;
1903 if (wanted_alternative > 63)
1904 wanted_alternative = 63;
1905 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1906 wanted_alternative--;
1907 if (wanted_alternative && wanted_alternative != tmp)
1908 IWL_WARN(priv,
1909 "uCode alternative %d not available, choosing %d\n",
1910 tmp, wanted_alternative);
1911
1912 priv->ucode_ver = le32_to_cpu(ucode->ver);
1913 pieces->build = le32_to_cpu(ucode->build);
1914 data = ucode->data;
1915
1916 len -= sizeof(*ucode);
1917
704da534 1918 while (len >= sizeof(*tlv)) {
dd7a2509 1919 u16 tlv_alt;
dd7a2509
JB		 1920
1921 len -= sizeof(*tlv);
1922 tlv = (void *)data;
1923
1924 tlv_len = le32_to_cpu(tlv->length);
1925 tlv_type = le16_to_cpu(tlv->type);
1926 tlv_alt = le16_to_cpu(tlv->alternative);
1927 tlv_data = tlv->data;
1928
ad8d8333
WYG		 1929 if (len < tlv_len) {
1930 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1931 len, tlv_len);
dd7a2509 1932 return -EINVAL;
ad8d8333 1933 }
dd7a2509
JB		 1934 len -= ALIGN(tlv_len, 4);
1935 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1936
1937 /*
1938 * Alternative 0 is always valid.
1939 *
1940 * Skip alternative TLVs that are not selected.
1941 */
1942 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1943 continue;
1944
1945 switch (tlv_type) {
1946 case IWL_UCODE_TLV_INST:
1947 pieces->inst = tlv_data;
1948 pieces->inst_size = tlv_len;
1949 break;
1950 case IWL_UCODE_TLV_DATA:
1951 pieces->data = tlv_data;
1952 pieces->data_size = tlv_len;
1953 break;
1954 case IWL_UCODE_TLV_INIT:
1955 pieces->init = tlv_data;
1956 pieces->init_size = tlv_len;
1957 break;
1958 case IWL_UCODE_TLV_INIT_DATA:
1959 pieces->init_data = tlv_data;
1960 pieces->init_data_size = tlv_len;
1961 break;
1962 case IWL_UCODE_TLV_BOOT:
1963 pieces->boot = tlv_data;
1964 pieces->boot_size = tlv_len;
1965 break;
1966 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1967 if (tlv_len != sizeof(u32))
1968 goto invalid_tlv_len;
1969 capa->max_probe_length =
ad8d8333 1970 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1971 break;
ece9c4ee
JB		 1972 case IWL_UCODE_TLV_PAN:
1973 if (tlv_len)
1974 goto invalid_tlv_len;
1975 capa->pan = true;
1976 break;
b2e640d4 1977 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1978 if (tlv_len != sizeof(u32))
1979 goto invalid_tlv_len;
1980 pieces->init_evtlog_ptr =
ad8d8333 1981 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1982 break;
1983 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1984 if (tlv_len != sizeof(u32))
1985 goto invalid_tlv_len;
1986 pieces->init_evtlog_size =
ad8d8333 1987 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1988 break;
1989 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 1990 if (tlv_len != sizeof(u32))
1991 goto invalid_tlv_len;
1992 pieces->init_errlog_ptr =
ad8d8333 1993 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1994 break;
1995 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 1996 if (tlv_len != sizeof(u32))
1997 goto invalid_tlv_len;
1998 pieces->inst_evtlog_ptr =
ad8d8333 1999 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2000 break;
2001 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 2002 if (tlv_len != sizeof(u32))
2003 goto invalid_tlv_len;
2004 pieces->inst_evtlog_size =
ad8d8333 2005 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2006 break;
2007 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 2008 if (tlv_len != sizeof(u32))
2009 goto invalid_tlv_len;
2010 pieces->inst_errlog_ptr =
ad8d8333 2011 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 2012 break;
c8312fac
WYG		 2013 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2014 if (tlv_len)
704da534
JB		 2015 goto invalid_tlv_len;
2016 priv->enhance_sensitivity_table = true;
c8312fac 2017 break;
6a822d06 2018 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 2019 if (tlv_len != sizeof(u32))
2020 goto invalid_tlv_len;
2021 capa->standard_phy_calibration_size =
6a822d06
WYG		 2022 le32_to_cpup((__le32 *)tlv_data);
2023 break;
dd7a2509 2024 default:
ad8d8333 2025 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 2026 break;
2027 }
2028 }
2029
ad8d8333
WYG		 2030 if (len) {
2031 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2032 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 2033 return -EINVAL;
ad8d8333 2034 }
dd7a2509 2035
704da534
JB		 2036 return 0;
2037
2038 invalid_tlv_len:
2039 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2040 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2041
2042 return -EINVAL;
dd7a2509
JB		 2043}
2044
b481de9c 2045/**
b08dfd04 2046 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 2047 *
b08dfd04
JB		 2048 * If loaded successfully, copies the firmware into buffers
2049 * for the card to fetch (via DMA).
b481de9c 2050 */
b08dfd04 2051static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 2052{
b08dfd04 2053 struct iwl_priv *priv = context;
cc0f555d 2054 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 2055 int err;
2056 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 2057 const unsigned int api_max = priv->cfg->ucode_api_max;
2058 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 2059 u32 api_ver;
3e4de761 2060 char buildstr[25];
0e9a44dc 2061 u32 build;
dd7a2509
JB		 2062 struct iwlagn_ucode_capabilities ucode_capa = {
2063 .max_probe_length = 200,
6a822d06 2064 .standard_phy_calibration_size =
642454cc 2065 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 2066 };
0e9a44dc
JB		 2067
2068 memset(&pieces, 0, sizeof(pieces));
b481de9c 2069
b08dfd04 2070 if (!ucode_raw) {
39396085
JS		 2071 if (priv->fw_index <= priv->cfg->ucode_api_max)
2072 IWL_ERR(priv,
2073 "request for firmware file '%s' failed.\n",
2074 priv->firmware_name);
b08dfd04 2075 goto try_again;
b481de9c
ZY		 2076 }
2077
b08dfd04
JB		 2078 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2079 priv->firmware_name, ucode_raw->size);
b481de9c 2080
22adba2a
JB		 2081 /* Make sure that we got at least the API version number */
2082 if (ucode_raw->size < 4) {
15b1687c 2083 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 2084 goto try_again;
b481de9c
ZY		 2085 }
2086
2087 /* Data from ucode file: header followed by uCode images */
cc0f555d 2088 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2089
0e9a44dc
JB		 2090 if (ucode->ver)
2091 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2092 else
dd7a2509
JB		 2093 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2094 &ucode_capa);
22adba2a 2095
0e9a44dc
JB		 2096 if (err)
2097 goto try_again;
b481de9c 2098
a0987a8d 2099 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 2100 build = pieces.build;
a0987a8d 2101
0e9a44dc
JB		 2102 /*
2103 * api_ver should match the api version forming part of the
2104 * firmware filename ... but we don't check for that and only rely
2105 * on the API version read from firmware header from here on forward
2106 */
65cccfb0
WYG		 2107 /* no api version check required for experimental uCode */
2108 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
2109 if (api_ver < api_min || api_ver > api_max) {
2110 IWL_ERR(priv,
2111 "Driver unable to support your firmware API. "
2112 "Driver supports v%u, firmware is v%u.\n",
2113 api_max, api_ver);
2114 goto try_again;
2115 }
b08dfd04 2116
65cccfb0
WYG		 2117 if (api_ver != api_max)
2118 IWL_ERR(priv,
2119 "Firmware has old API version. Expected v%u, "
2120 "got v%u. New firmware can be obtained "
2121 "from http://www.intellinuxwireless.org.\n",
2122 api_max, api_ver);
2123 }
a0987a8d 2124
3e4de761 2125 if (build)
39396085
JS		 2126 sprintf(buildstr, " build %u%s", build,
2127 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2128 ? " (EXP)" : "");
3e4de761
JB		 2129 else
2130 buildstr[0] = '\0';
2131
2132 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2133 IWL_UCODE_MAJOR(priv->ucode_ver),
2134 IWL_UCODE_MINOR(priv->ucode_ver),
2135 IWL_UCODE_API(priv->ucode_ver),
2136 IWL_UCODE_SERIAL(priv->ucode_ver),
2137 buildstr);
a0987a8d 2138
5ebeb5a6
RC		 2139 snprintf(priv->hw->wiphy->fw_version,
2140 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2141 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2142 IWL_UCODE_MAJOR(priv->ucode_ver),
2143 IWL_UCODE_MINOR(priv->ucode_ver),
2144 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2145 IWL_UCODE_SERIAL(priv->ucode_ver),
2146 buildstr);
b481de9c 2147
b08dfd04
JB		 2148 /*
2149 * For any of the failures below (before allocating pci memory)
2150 * we will try to load a version with a smaller API -- maybe the
2151 * user just got a corrupted version of the latest API.
2152 */
2153
0e9a44dc
JB		 2154 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2155 priv->ucode_ver);
2156 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2157 pieces.inst_size);
2158 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2159 pieces.data_size);
2160 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2161 pieces.init_size);
2162 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2163 pieces.init_data_size);
2164 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2165 pieces.boot_size);
b481de9c
ZY		 2166
2167 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2168 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2169 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2170 pieces.inst_size);
b08dfd04 2171 goto try_again;
b481de9c
ZY		 2172 }
2173
0e9a44dc
JB		 2174 if (pieces.data_size > priv->hw_params.max_data_size) {
2175 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2176 pieces.data_size);
b08dfd04 2177 goto try_again;
b481de9c 2178 }
0e9a44dc
JB		 2179
2180 if (pieces.init_size > priv->hw_params.max_inst_size) {
2181 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2182 pieces.init_size);
b08dfd04 2183 goto try_again;
b481de9c 2184 }
0e9a44dc
JB		 2185
2186 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2187 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2188 pieces.init_data_size);
b08dfd04 2189 goto try_again;
b481de9c 2190 }
0e9a44dc
JB		 2191
2192 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2193 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2194 pieces.boot_size);
b08dfd04 2195 goto try_again;
b481de9c
ZY		 2196 }
2197
2198 /* Allocate ucode buffers for card's bus-master loading ... */
2199
2200 /* Runtime instructions and 2 copies of data:
2201 * 1) unmodified from disk
2202 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2203 priv->ucode_code.len = pieces.inst_size;
98c92211 2204 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2205
0e9a44dc 2206 priv->ucode_data.len = pieces.data_size;
98c92211 2207 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2208
0e9a44dc 2209 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2210 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2211
1f304e4e
ZY		 2212 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2213 !priv->ucode_data_backup.v_addr)
2214 goto err_pci_alloc;
2215
b481de9c 2216 /* Initialization instructions and data */
0e9a44dc
JB		 2217 if (pieces.init_size && pieces.init_data_size) {
2218 priv->ucode_init.len = pieces.init_size;
98c92211 2219 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2220
0e9a44dc 2221 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2222 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2223
2224 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2225 goto err_pci_alloc;
2226 }
b481de9c
ZY		 2227
2228 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2229 if (pieces.boot_size) {
2230 priv->ucode_boot.len = pieces.boot_size;
98c92211 2231 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2232
90e759d1
TW		 2233 if (!priv->ucode_boot.v_addr)
2234 goto err_pci_alloc;
2235 }
b481de9c 2236
b2e640d4
JB		 2237 /* Now that we can no longer fail, copy information */
2238
2239 /*
2240 * The (size - 16) / 12 formula is based on the information recorded
2241 * for each event, which is of mode 1 (including timestamp) for all
2242 * new microcodes that include this information.
2243 */
2244 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2245 if (pieces.init_evtlog_size)
2246 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2247 else
7cb1b088
WYG		 2248 priv->_agn.init_evtlog_size =
2249 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2250 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2251 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2252 if (pieces.inst_evtlog_size)
2253 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2254 else
7cb1b088
WYG		 2255 priv->_agn.inst_evtlog_size =
2256 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2257 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2258
ece9c4ee
JB		 2259 if (ucode_capa.pan) {
2260 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
c10afb6e 2261 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
ece9c4ee
JB		 2262 } else
2263 priv->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 2264
b481de9c
ZY		 2265 /* Copy images into buffers for card's bus-master reads ... */
2266
2267 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2268 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2269 pieces.inst_size);
2270 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2271
e1623446 2272 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2273 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2274
0e9a44dc
JB		 2275 /*
2276 * Runtime data
2277 * NOTE: Copy into backup buffer will be done in iwl_up()
2278 */
2279 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2280 pieces.data_size);
2281 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2282 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2283
2284 /* Initialization instructions */
2285 if (pieces.init_size) {
e1623446 2286 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2287 pieces.init_size);
2288 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2289 }
2290
0e9a44dc
JB		 2291 /* Initialization data */
2292 if (pieces.init_data_size) {
e1623446 2293 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2294 pieces.init_data_size);
2295 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2296 pieces.init_data_size);
b481de9c
ZY		 2297 }
2298
0e9a44dc
JB		 2299 /* Bootstrap instructions */
2300 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2301 pieces.boot_size);
2302 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2303
6a822d06
WYG		 2304 /*
2305 * figure out the offset of chain noise reset and gain commands
2306 * base on the size of standard phy calibration commands table size
2307 */
2308 if (ucode_capa.standard_phy_calibration_size >
2309 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2310 ucode_capa.standard_phy_calibration_size =
2311 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2312
2313 priv->_agn.phy_calib_chain_noise_reset_cmd =
2314 ucode_capa.standard_phy_calibration_size;
2315 priv->_agn.phy_calib_chain_noise_gain_cmd =
2316 ucode_capa.standard_phy_calibration_size + 1;
2317
b08dfd04
JB		 2318 /**************************************************
2319 * This is still part of probe() in a sense...
2320 *
2321 * 9. Setup and register with mac80211 and debugfs
2322 **************************************************/
dd7a2509 2323 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2324 if (err)
2325 goto out_unbind;
2326
2327 err = iwl_dbgfs_register(priv, DRV_NAME);
2328 if (err)
2329 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2330
7d47618a
EG		 2331 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2332 &iwl_attribute_group);
2333 if (err) {
2334 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2335 goto out_unbind;
2336 }
2337
b481de9c
ZY		 2338 /* We have our copies now, allow OS release its copies */
2339 release_firmware(ucode_raw);
a15707d8 2340 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2341 return;
2342
2343 try_again:
2344 /* try next, if any */
2345 if (iwl_request_firmware(priv, false))
2346 goto out_unbind;
2347 release_firmware(ucode_raw);
2348 return;
b481de9c
ZY		 2349
2350 err_pci_alloc:
15b1687c 2351 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2352 iwl_dealloc_ucode_pci(priv);
b08dfd04 2353 out_unbind:
a15707d8 2354 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2355 device_release_driver(&priv->pci_dev->dev);
b481de9c 2356 release_firmware(ucode_raw);
b481de9c
ZY		 2357}
2358
b7a79404
RC		 2359static const char *desc_lookup_text[] = {
2360 "OK",
2361 "FAIL",
2362 "BAD_PARAM",
2363 "BAD_CHECKSUM",
2364 "NMI_INTERRUPT_WDG",
2365 "SYSASSERT",
2366 "FATAL_ERROR",
2367 "BAD_COMMAND",
2368 "HW_ERROR_TUNE_LOCK",
2369 "HW_ERROR_TEMPERATURE",
2370 "ILLEGAL_CHAN_FREQ",
2371 "VCC_NOT_STABLE",
2372 "FH_ERROR",
2373 "NMI_INTERRUPT_HOST",
2374 "NMI_INTERRUPT_ACTION_PT",
2375 "NMI_INTERRUPT_UNKNOWN",
2376 "UCODE_VERSION_MISMATCH",
2377 "HW_ERROR_ABS_LOCK",
2378 "HW_ERROR_CAL_LOCK_FAIL",
2379 "NMI_INTERRUPT_INST_ACTION_PT",
2380 "NMI_INTERRUPT_DATA_ACTION_PT",
2381 "NMI_TRM_HW_ER",
2382 "NMI_INTERRUPT_TRM",
2383 "NMI_INTERRUPT_BREAK_POINT"
2384 "DEBUG_0",
2385 "DEBUG_1",
2386 "DEBUG_2",
2387 "DEBUG_3",
b7a79404
RC		 2388};
2389
4b58645c
JS		 2390static struct { char *name; u8 num; } advanced_lookup[] = {
2391 { "NMI_INTERRUPT_WDG", 0x34 },
2392 { "SYSASSERT", 0x35 },
2393 { "UCODE_VERSION_MISMATCH", 0x37 },
2394 { "BAD_COMMAND", 0x38 },
2395 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2396 { "FATAL_ERROR", 0x3D },
2397 { "NMI_TRM_HW_ERR", 0x46 },
2398 { "NMI_INTERRUPT_TRM", 0x4C },
2399 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2400 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2401 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2402 { "NMI_INTERRUPT_HOST", 0x66 },
2403 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2404 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2405 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2406 { "ADVANCED_SYSASSERT", 0 },
2407};
2408
2409static const char *desc_lookup(u32 num)
b7a79404 2410{
4b58645c
JS		 2411 int i;
2412 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2413
4b58645c
JS		 2414 if (num < max)
2415 return desc_lookup_text[num];
b7a79404 2416
4b58645c
JS		 2417 max = ARRAY_SIZE(advanced_lookup) - 1;
2418 for (i = 0; i < max; i++) {
2419 if (advanced_lookup[i].num == num)
2420 break;;
2421 }
2422 return advanced_lookup[i].name;
b7a79404
RC		 2423}
2424
2425#define ERROR_START_OFFSET (1 * sizeof(u32))
2426#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2427
2428void iwl_dump_nic_error_log(struct iwl_priv *priv)
2429{
2430 u32 data2, line;
2431 u32 desc, time, count, base, data1;
2432 u32 blink1, blink2, ilink1, ilink2;
461ef382 2433 u32 pc, hcmd;
b7a79404 2434
b2e640d4 2435 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2436 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2437 if (!base)
2438 base = priv->_agn.init_errlog_ptr;
2439 } else {
b7a79404 2440 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2441 if (!base)
2442 base = priv->_agn.inst_errlog_ptr;
2443 }
b7a79404
RC		 2444
2445 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2446 IWL_ERR(priv,
2447 "Not valid error log pointer 0x%08X for %s uCode\n",
2448 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2449 return;
2450 }
2451
2452 count = iwl_read_targ_mem(priv, base);
2453
2454 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2455 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2456 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2457 priv->status, count);
2458 }
2459
2460 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
6e6ebf4b 2461 priv->isr_stats.err_code = desc;
461ef382 2462 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2463 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2464 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2465 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2466 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2467 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2468 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2469 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2470 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2471 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2472
be1a71a1
JB		 2473 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2474 blink1, blink2, ilink1, ilink2);
2475
87563715 2476 IWL_ERR(priv, "Desc Time "
b7a79404 2477 "data1 data2 line\n");
87563715 2478 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2479 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2480 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2481 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2482 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2483}
2484
2485#define EVENT_START_OFFSET (4 * sizeof(u32))
2486
2487/**
2488 * iwl_print_event_log - Dump error event log to syslog
2489 *
2490 */
b03d7d0f
WYG		 2491static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2492 u32 num_events, u32 mode,
2493 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2494{
2495 u32 i;
2496 u32 base; /* SRAM byte address of event log header */
2497 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2498 u32 ptr; /* SRAM byte address of log data */
2499 u32 ev, time, data; /* event log data */
e5854471 2500 unsigned long reg_flags;
b7a79404
RC		 2501
2502 if (num_events == 0)
b03d7d0f 2503 return pos;
b2e640d4
JB		 2504
2505 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2506 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2507 if (!base)
2508 base = priv->_agn.init_evtlog_ptr;
2509 } else {
b7a79404 2510 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2511 if (!base)
2512 base = priv->_agn.inst_evtlog_ptr;
2513 }
b7a79404
RC		 2514
2515 if (mode == 0)
2516 event_size = 2 * sizeof(u32);
2517 else
2518 event_size = 3 * sizeof(u32);
2519
2520 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2521
e5854471
BC		 2522 /* Make sure device is powered up for SRAM reads */
2523 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2524 iwl_grab_nic_access(priv);
2525
2526 /* Set starting address; reads will auto-increment */
2527 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2528 rmb();
2529
b7a79404
RC		 2530 /* "time" is actually "data" for mode 0 (no timestamp).
2531 * place event id # at far right for easier visual parsing. */
2532 for (i = 0; i < num_events; i++) {
e5854471
BC		 2533 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2534 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2535 if (mode == 0) {
2536 /* data, ev */
b03d7d0f
WYG		 2537 if (bufsz) {
2538 pos += scnprintf(*buf + pos, bufsz - pos,
2539 "EVT_LOG:0x%08x:%04u\n",
2540 time, ev);
2541 } else {
2542 trace_iwlwifi_dev_ucode_event(priv, 0,
2543 time, ev);
2544 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2545 time, ev);
2546 }
b7a79404 2547 } else {
e5854471 2548 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2549 if (bufsz) {
2550 pos += scnprintf(*buf + pos, bufsz - pos,
2551 "EVT_LOGT:%010u:0x%08x:%04u\n",
2552 time, data, ev);
2553 } else {
2554 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2555 time, data, ev);
b03d7d0f
WYG		 2556 trace_iwlwifi_dev_ucode_event(priv, time,
2557 data, ev);
2558 }
b7a79404
RC		 2559 }
2560 }
e5854471
BC		 2561
2562 /* Allow device to power down */
2563 iwl_release_nic_access(priv);
2564 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2565 return pos;
b7a79404
RC		 2566}
2567
c341ddb2
WYG		 2568/**
2569 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2570 */
b03d7d0f
WYG		 2571static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2572 u32 num_wraps, u32 next_entry,
2573 u32 size, u32 mode,
2574 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2575{
2576 /*
2577 * display the newest DEFAULT_LOG_ENTRIES entries
2578 * i.e the entries just before the next ont that uCode would fill.
2579 */
2580 if (num_wraps) {
2581 if (next_entry < size) {
b03d7d0f
WYG		 2582 pos = iwl_print_event_log(priv,
2583 capacity - (size - next_entry),
2584 size - next_entry, mode,
2585 pos, buf, bufsz);
2586 pos = iwl_print_event_log(priv, 0,
2587 next_entry, mode,
2588 pos, buf, bufsz);
c341ddb2 2589 } else
b03d7d0f
WYG		 2590 pos = iwl_print_event_log(priv, next_entry - size,
2591 size, mode, pos, buf, bufsz);
c341ddb2 2592 } else {
b03d7d0f
WYG		 2593 if (next_entry < size) {
2594 pos = iwl_print_event_log(priv, 0, next_entry,
2595 mode, pos, buf, bufsz);
2596 } else {
2597 pos = iwl_print_event_log(priv, next_entry - size,
2598 size, mode, pos, buf, bufsz);
2599 }
c341ddb2 2600 }
b03d7d0f 2601 return pos;
c341ddb2
WYG		 2602}
2603
c341ddb2
WYG		 2604#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2605
b03d7d0f
WYG		 2606int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2607 char **buf, bool display)
b7a79404
RC		 2608{
2609 u32 base; /* SRAM byte address of event log header */
2610 u32 capacity; /* event log capacity in # entries */
2611 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2612 u32 num_wraps; /* # times uCode wrapped to top of log */
2613 u32 next_entry; /* index of next entry to be written by uCode */
2614 u32 size; /* # entries that we'll print */
b2e640d4 2615 u32 logsize;
b03d7d0f
WYG		 2616 int pos = 0;
2617 size_t bufsz = 0;
b7a79404 2618
b2e640d4 2619 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2620 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2621 logsize = priv->_agn.init_evtlog_size;
2622 if (!base)
2623 base = priv->_agn.init_evtlog_ptr;
2624 } else {
b7a79404 2625 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2626 logsize = priv->_agn.inst_evtlog_size;
2627 if (!base)
2628 base = priv->_agn.inst_evtlog_ptr;
2629 }
b7a79404
RC		 2630
2631 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2632 IWL_ERR(priv,
2633 "Invalid event log pointer 0x%08X for %s uCode\n",
2634 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2635 return -EINVAL;
b7a79404
RC		 2636 }
2637
2638 /* event log header */
2639 capacity = iwl_read_targ_mem(priv, base);
2640 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2641 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2642 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2643
b2e640d4 2644 if (capacity > logsize) {
84c40692 2645 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2646 capacity, logsize);
2647 capacity = logsize;
84c40692
BC		 2648 }
2649
b2e640d4 2650 if (next_entry > logsize) {
84c40692 2651 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2652 next_entry, logsize);
2653 next_entry = logsize;
84c40692
BC		 2654 }
2655
b7a79404
RC		 2656 size = num_wraps ? capacity : next_entry;
2657
2658 /* bail out if nothing in log */
2659 if (size == 0) {
2660 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2661 return pos;
b7a79404
RC		 2662 }
2663
f37837c9
WYG		 2664 /* enable/disable bt channel announcement */
2665 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2666
c341ddb2 2667#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2668 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2669 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2670 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2671#else
2672 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2673 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2674#endif
2675 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2676 size);
b7a79404 2677
c341ddb2 2678#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2679 if (display) {
2680 if (full_log)
2681 bufsz = capacity * 48;
2682 else
2683 bufsz = size * 48;
2684 *buf = kmalloc(bufsz, GFP_KERNEL);
2685 if (!*buf)
937c397e 2686 return -ENOMEM;
b03d7d0f 2687 }
c341ddb2
WYG		 2688 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2689 /*
2690 * if uCode has wrapped back to top of log,
2691 * start at the oldest entry,
2692 * i.e the next one that uCode would fill.
2693 */
2694 if (num_wraps)
b03d7d0f
WYG		 2695 pos = iwl_print_event_log(priv, next_entry,
2696 capacity - next_entry, mode,
2697 pos, buf, bufsz);
c341ddb2 2698 /* (then/else) start at top of log */
b03d7d0f
WYG		 2699 pos = iwl_print_event_log(priv, 0,
2700 next_entry, mode, pos, buf, bufsz);
c341ddb2 2701 } else
b03d7d0f
WYG		 2702 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2703 next_entry, size, mode,
2704 pos, buf, bufsz);
c341ddb2 2705#else
b03d7d0f
WYG		 2706 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2707 next_entry, size, mode,
2708 pos, buf, bufsz);
b7a79404 2709#endif
b03d7d0f 2710 return pos;
c341ddb2 2711}
b7a79404 2712
0975cc8f
WYG		 2713static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2714{
2715 struct iwl_ct_kill_config cmd;
2716 struct iwl_ct_kill_throttling_config adv_cmd;
2717 unsigned long flags;
2718 int ret = 0;
2719
2720 spin_lock_irqsave(&priv->lock, flags);
2721 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2722 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2723 spin_unlock_irqrestore(&priv->lock, flags);
2724 priv->thermal_throttle.ct_kill_toggle = false;
2725
7cb1b088 2726 if (priv->cfg->base_params->support_ct_kill_exit) {
0975cc8f
WYG		 2727 adv_cmd.critical_temperature_enter =
2728 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2729 adv_cmd.critical_temperature_exit =
2730 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2731
2732 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2733 sizeof(adv_cmd), &adv_cmd);
2734 if (ret)
2735 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2736 else
2737 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2738 "succeeded, "
2739 "critical temperature enter is %d,"
2740 "exit is %d\n",
2741 priv->hw_params.ct_kill_threshold,
2742 priv->hw_params.ct_kill_exit_threshold);
2743 } else {
2744 cmd.critical_temperature_R =
2745 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2746
2747 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2748 sizeof(cmd), &cmd);
2749 if (ret)
2750 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2751 else
2752 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2753 "succeeded, "
2754 "critical temperature is %d\n",
2755 priv->hw_params.ct_kill_threshold);
2756 }
2757}
2758
6d6a1afd
SZ		 2759static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2760{
2761 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2762 struct iwl_host_cmd cmd = {
2763 .id = CALIBRATION_CFG_CMD,
2764 .len = sizeof(struct iwl_calib_cfg_cmd),
2765 .data = &calib_cfg_cmd,
2766 };
2767
2768 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2769 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
7cb1b088 2770 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
6d6a1afd
SZ		 2771
2772 return iwl_send_cmd(priv, &cmd);
2773}
2774
2775
b481de9c 2776/**
4a4a9e81 2777 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2778 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2779 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2780 */
4a4a9e81 2781static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2782{
57aab75a 2783 int ret = 0;
246ed355 2784 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2785
e1623446 2786 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2787
2788 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2789 /* We had an error bringing up the hardware, so take it
2790 * all the way back down so we can try again */
e1623446 2791 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2792 goto restart;
2793 }
2794
2795 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2796 * This is a paranoid check, because we would not have gotten the
2797 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2798 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2799 /* Runtime instruction load was bad;
2800 * take it all the way back down so we can try again */
e1623446 2801 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2802 goto restart;
2803 }
2804
57aab75a
TW		 2805 ret = priv->cfg->ops->lib->alive_notify(priv);
2806 if (ret) {
39aadf8c
WT		 2807 IWL_WARN(priv,
2808 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2809 goto restart;
2810 }
2811
6d6a1afd 2812
5b9f8cd3 2813 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2814 set_bit(STATUS_ALIVE, &priv->status);
2815
b74e31a9
WYG		 2816 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2817 /* Enable timer to monitor the driver queues */
2818 mod_timer(&priv->monitor_recover,
2819 jiffies +
7cb1b088
WYG		 2820 msecs_to_jiffies(
2821 priv->cfg->base_params->monitor_recover_period));
b74e31a9
WYG		 2822 }
2823
fee1247a 2824 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2825 return;
2826
bc795df1 2827 /* download priority table before any calibration request */
7cb1b088
WYG		 2828 if (priv->cfg->bt_params &&
2829 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f
WYG		 2830 /* Configure Bluetooth device coexistence support */
2831 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2832 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2833 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2834 priv->cfg->ops->hcmd->send_bt_config(priv);
2835 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
a5901cbb 2836 iwlagn_send_prio_tbl(priv);
f7322f8f
WYG		 2837
2838 /* FIXME: w/a to force change uCode BT state machine */
2839 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2840 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2841 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2842 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2843 }
bc795df1
WYG		 2844 if (priv->hw_params.calib_rt_cfg)
2845 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2846
36d6825b 2847 ieee80211_wake_queues(priv->hw);
b481de9c 2848
470ab2dd 2849 priv->active_rate = IWL_RATES_MASK;
b481de9c 2850
2f748dec
WYG		 2851 /* Configure Tx antenna selection based on H/W config */
2852 if (priv->cfg->ops->hcmd->set_tx_ant)
2853 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2854
246ed355 2855 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2856 struct iwl_rxon_cmd *active_rxon =
246ed355 2857 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2858 /* apply any changes in staging */
246ed355 2859 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2860 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2861 } else {
d0fe478c 2862 struct iwl_rxon_context *tmp;
b481de9c 2863 /* Initialize our rx_config data */
d0fe478c
JB		 2864 for_each_context(priv, tmp)
2865 iwl_connection_init_rx_config(priv, tmp);
45823531
AK		 2866
2867 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 2868 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c
ZY		 2869 }
2870
7cb1b088
WYG		 2871 if (priv->cfg->bt_params &&
2872 !priv->cfg->bt_params->advanced_bt_coexist) {
aeb4a2ee
WYG		 2873 /* Configure Bluetooth device coexistence support */
2874 priv->cfg->ops->hcmd->send_bt_config(priv);
2875 }
b481de9c 2876
4a4a9e81
TW		 2877 iwl_reset_run_time_calib(priv);
2878
b481de9c 2879 /* Configure the adapter for unassociated operation */
246ed355 2880 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 2881
2882 /* At this point, the NIC is initialized and operational */
47f4a587 2883 iwl_rf_kill_ct_config(priv);
5a66926a 2884
e932a609 2885 iwl_leds_init(priv);
fe00b5a5 2886
e1623446 2887 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2888 set_bit(STATUS_READY, &priv->status);
5a66926a 2889 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2890
e312c24c 2891 iwl_power_update_mode(priv, true);
7e246191
RC		 2892 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2893
c46fbefa 2894
b481de9c
ZY		 2895 return;
2896
2897 restart:
2898 queue_work(priv->workqueue, &priv->restart);
2899}
2900
4e39317d 2901static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2902
5b9f8cd3 2903static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2904{
2905 unsigned long flags;
2906 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2907
e1623446 2908 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2909
d745d472
SG		 2910 iwl_scan_cancel_timeout(priv, 200);
2911
2912 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2913
b62177a0
SG		 2914 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2915 * to prevent rearm timer */
2916 if (priv->cfg->ops->lib->recover_from_tx_stall)
2917 del_timer_sync(&priv->monitor_recover);
2918
dcef732c 2919 iwl_clear_ucode_stations(priv, NULL);
a194e324 2920 iwl_dealloc_bcast_stations(priv);
db125c78 2921 iwl_clear_driver_stations(priv);
b481de9c 2922
a1174138 2923 /* reset BT coex data */
da5dbb97 2924 priv->bt_status = 0;
7cb1b088
WYG		 2925 if (priv->cfg->bt_params)
2926 priv->bt_traffic_load =
2927 priv->cfg->bt_params->bt_init_traffic_load;
2928 else
2929 priv->bt_traffic_load = 0;
a1174138 2930 priv->bt_sco_active = false;
bee008b7
WYG		 2931 priv->bt_full_concurrent = false;
2932 priv->bt_ci_compliance = 0;
a1174138 2933
b481de9c
ZY		 2934 /* Unblock any waiting calls */
2935 wake_up_interruptible_all(&priv->wait_command_queue);
2936
b481de9c
ZY		 2937 /* Wipe out the EXIT_PENDING status bit if we are not actually
2938 * exiting the module */
2939 if (!exit_pending)
2940 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2941
2942 /* stop and reset the on-board processor */
3395f6e9 2943 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2944
2945 /* tell the device to stop sending interrupts */
0359facc 2946 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2947 iwl_disable_interrupts(priv);
0359facc
MA		 2948 spin_unlock_irqrestore(&priv->lock, flags);
2949 iwl_synchronize_irq(priv);
b481de9c
ZY		 2950
2951 if (priv->mac80211_registered)
2952 ieee80211_stop_queues(priv->hw);
2953
5b9f8cd3 2954 /* If we have not previously called iwl_init() then
a60e77e5 2955 * clear all bits but the RF Kill bit and return */
fee1247a 2956 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2957 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2958 STATUS_RF_KILL_HW |
9788864e
RC		 2959 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2960 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2961 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2962 STATUS_EXIT_PENDING;
b481de9c
ZY		 2963 goto exit;
2964 }
2965
6da3a13e 2966 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2967 * bit and continue taking the NIC down. */
b481de9c
ZY		 2968 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2969 STATUS_RF_KILL_HW |
9788864e
RC		 2970 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2971 STATUS_GEO_CONFIGURED |
b481de9c 2972 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2973 STATUS_FW_ERROR |
2974 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2975 STATUS_EXIT_PENDING;
b481de9c 2976
ef850d7c
MA		 2977 /* device going down, Stop using ICT table */
2978 iwl_disable_ict(priv);
b481de9c 2979
74bcdb33 2980 iwlagn_txq_ctx_stop(priv);
54b81550 2981 iwlagn_rxq_stop(priv);
b481de9c 2982
309e731a
BC		 2983 /* Power-down device's busmaster DMA clocks */
2984 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2985 udelay(5);
2986
309e731a
BC		 2987 /* Make sure (redundant) we've released our request to stay awake */
2988 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2989
4d2ccdb9 2990 /* Stop the device, and put it in low power state */
14e8e4af 2991 iwl_apm_stop(priv);
4d2ccdb9 2992
b481de9c 2993 exit:
885ba202 2994 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c 2995
77834543 2996 dev_kfree_skb(priv->beacon_skb);
12e934dc 2997 priv->beacon_skb = NULL;
b481de9c
ZY		 2998
2999 /* clear out any free frames */
fcab423d 3000 iwl_clear_free_frames(priv);
b481de9c
ZY		 3001}
3002
5b9f8cd3 3003static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 3004{
3005 mutex_lock(&priv->mutex);
5b9f8cd3 3006 __iwl_down(priv);
b481de9c 3007 mutex_unlock(&priv->mutex);
b24d22b1 3008
4e39317d 3009 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 3010}
3011
086ed117
MA		 3012#define HW_READY_TIMEOUT (50)
3013
3014static int iwl_set_hw_ready(struct iwl_priv *priv)
3015{
3016 int ret = 0;
3017
3018 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3019 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
3020
3021 /* See if we got it */
3022 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3023 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3024 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3025 HW_READY_TIMEOUT);
3026 if (ret != -ETIMEDOUT)
3027 priv->hw_ready = true;
3028 else
3029 priv->hw_ready = false;
3030
3031 IWL_DEBUG_INFO(priv, "hardware %s\n",
3032 (priv->hw_ready == 1) ? "ready" : "not ready");
3033 return ret;
3034}
3035
3036static int iwl_prepare_card_hw(struct iwl_priv *priv)
3037{
3038 int ret = 0;
3039
91dd6c27 3040 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 3041
3354a0f6
MA		 3042 ret = iwl_set_hw_ready(priv);
3043 if (priv->hw_ready)
3044 return ret;
3045
3046 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 3047 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3048 CSR_HW_IF_CONFIG_REG_PREPARE);
3049
3050 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3051 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3052 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3053
3354a0f6 3054 /* HW should be ready by now, check again. */
086ed117
MA		 3055 if (ret != -ETIMEDOUT)
3056 iwl_set_hw_ready(priv);
3057
3058 return ret;
3059}
3060
b481de9c
ZY		 3061#define MAX_HW_RESTARTS 5
3062
5b9f8cd3 3063static int __iwl_up(struct iwl_priv *priv)
b481de9c 3064{
a194e324 3065 struct iwl_rxon_context *ctx;
57aab75a
TW		 3066 int i;
3067 int ret;
b481de9c
ZY		 3068
3069 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 3070 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 3071 return -EIO;
3072 }
3073
e903fbd4 3074 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 3075 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 3076 return -EIO;
3077 }
3078
a194e324 3079 for_each_context(priv, ctx) {
a30e3112 3080 ret = iwlagn_alloc_bcast_station(priv, ctx);
a194e324
JB		 3081 if (ret) {
3082 iwl_dealloc_bcast_stations(priv);
3083 return ret;
3084 }
3085 }
2c810ccd 3086
086ed117
MA		 3087 iwl_prepare_card_hw(priv);
3088
3089 if (!priv->hw_ready) {
3090 IWL_WARN(priv, "Exit HW not ready\n");
3091 return -EIO;
3092 }
3093
e655b9f0 3094 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 3095 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 3096 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3097 else
e655b9f0 3098 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3099
c1842d61 3100 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 3101 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3102
5b9f8cd3 3103 iwl_enable_interrupts(priv);
a60e77e5 3104 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 3105 return 0;
b481de9c
ZY		 3106 }
3107
3395f6e9 3108 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 3109
13bb9483 3110 /* must be initialised before iwl_hw_nic_init */
751ca305
JB		 3111 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3112 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3113 else
3114 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
13bb9483 3115
74bcdb33 3116 ret = iwlagn_hw_nic_init(priv);
57aab75a 3117 if (ret) {
15b1687c 3118 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 3119 return ret;
b481de9c
ZY		 3120 }
3121
3122 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3123 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3124 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 3125 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3126
3127 /* clear (again), then enable host interrupts */
3395f6e9 3128 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 3129 iwl_enable_interrupts(priv);
b481de9c
ZY		 3130
3131 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3132 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3133 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3134
3135 /* Copy original ucode data image from disk into backup cache.
3136 * This will be used to initialize the on-board processor's
3137 * data SRAM for a clean start when the runtime program first loads. */
3138 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 3139 priv->ucode_data.len);
b481de9c 3140
b481de9c
ZY		 3141 for (i = 0; i < MAX_HW_RESTARTS; i++) {
3142
b481de9c
ZY		 3143 /* load bootstrap state machine,
3144 * load bootstrap program into processor's memory,
3145 * prepare to load the "initialize" uCode */
57aab75a 3146 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 3147
57aab75a 3148 if (ret) {
15b1687c
WT		 3149 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3150 ret);
b481de9c
ZY		 3151 continue;
3152 }
3153
3154 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 3155 iwl_nic_start(priv);
b481de9c 3156
e1623446 3157 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 3158
3159 return 0;
3160 }
3161
3162 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 3163 __iwl_down(priv);
64e72c3e 3164 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 3165
3166 /* tried to restart and config the device for as long as our
3167 * patience could withstand */
15b1687c 3168 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 3169 return -EIO;
3170}
3171
3172
3173/*****************************************************************************
3174 *
3175 * Workqueue callbacks
3176 *
3177 *****************************************************************************/
3178
4a4a9e81 3179static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 3180{
c79dd5b5
TW		 3181 struct iwl_priv *priv =
3182 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 3183
3184 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3185 return;
3186
3187 mutex_lock(&priv->mutex);
f3ccc08c 3188 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 3189 mutex_unlock(&priv->mutex);
3190}
3191
4a4a9e81 3192static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 3193{
c79dd5b5
TW		 3194 struct iwl_priv *priv =
3195 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3196
3197 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3198 return;
3199
258c44a0
MA		 3200 /* enable dram interrupt */
3201 iwl_reset_ict(priv);
3202
b481de9c 3203 mutex_lock(&priv->mutex);
4a4a9e81 3204 iwl_alive_start(priv);
b481de9c
ZY		 3205 mutex_unlock(&priv->mutex);
3206}
3207
16e727e8
EG		 3208static void iwl_bg_run_time_calib_work(struct work_struct *work)
3209{
3210 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3211 run_time_calib_work);
3212
3213 mutex_lock(&priv->mutex);
3214
3215 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3216 test_bit(STATUS_SCANNING, &priv->status)) {
3217 mutex_unlock(&priv->mutex);
3218 return;
3219 }
3220
3221 if (priv->start_calib) {
7cb1b088
WYG		 3222 if (priv->cfg->bt_params &&
3223 priv->cfg->bt_params->bt_statistics) {
7980fba5
WYG		 3224 iwl_chain_noise_calibration(priv,
3225 (void *)&priv->_agn.statistics_bt);
3226 iwl_sensitivity_calibration(priv,
3227 (void *)&priv->_agn.statistics_bt);
3228 } else {
3229 iwl_chain_noise_calibration(priv,
3230 (void *)&priv->_agn.statistics);
3231 iwl_sensitivity_calibration(priv,
3232 (void *)&priv->_agn.statistics);
3233 }
16e727e8
EG		 3234 }
3235
3236 mutex_unlock(&priv->mutex);
16e727e8
EG		 3237}
3238
5b9f8cd3 3239static void iwl_bg_restart(struct work_struct *data)
b481de9c 3240{
c79dd5b5 3241 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3242
3243 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3244 return;
3245
19cc1087 3246 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
8bd413e6 3247 struct iwl_rxon_context *ctx;
bee008b7
WYG		 3248 bool bt_sco, bt_full_concurrent;
3249 u8 bt_ci_compliance;
511b082d 3250 u8 bt_load;
da5dbb97 3251 u8 bt_status;
511b082d 3252
19cc1087 3253 mutex_lock(&priv->mutex);
8bd413e6
JB		 3254 for_each_context(priv, ctx)
3255 ctx->vif = NULL;
19cc1087 3256 priv->is_open = 0;
511b082d
JB		 3257
3258 /*
3259 * __iwl_down() will clear the BT status variables,
3260 * which is correct, but when we restart we really
3261 * want to keep them so restore them afterwards.
3262 *
3263 * The restart process will later pick them up and
3264 * re-configure the hw when we reconfigure the BT
3265 * command.
3266 */
3267 bt_sco = priv->bt_sco_active;
bee008b7
WYG		 3268 bt_full_concurrent = priv->bt_full_concurrent;
3269 bt_ci_compliance = priv->bt_ci_compliance;
511b082d 3270 bt_load = priv->bt_traffic_load;
da5dbb97 3271 bt_status = priv->bt_status;
511b082d 3272
a1174138 3273 __iwl_down(priv);
511b082d
JB		 3274
3275 priv->bt_sco_active = bt_sco;
bee008b7
WYG		 3276 priv->bt_full_concurrent = bt_full_concurrent;
3277 priv->bt_ci_compliance = bt_ci_compliance;
511b082d 3278 priv->bt_traffic_load = bt_load;
da5dbb97 3279 priv->bt_status = bt_status;
511b082d 3280
19cc1087 3281 mutex_unlock(&priv->mutex);
a1174138 3282 iwl_cancel_deferred_work(priv);
19cc1087
JB		 3283 ieee80211_restart_hw(priv->hw);
3284 } else {
3285 iwl_down(priv);
80676518
JB		 3286
3287 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3288 return;
3289
3290 mutex_lock(&priv->mutex);
3291 __iwl_up(priv);
3292 mutex_unlock(&priv->mutex);
19cc1087 3293 }
b481de9c
ZY		 3294}
3295
5b9f8cd3 3296static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3297{
c79dd5b5
TW		 3298 struct iwl_priv *priv =
3299 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3300
3301 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3302 return;
3303
3304 mutex_lock(&priv->mutex);
54b81550 3305 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3306 mutex_unlock(&priv->mutex);
3307}
3308
7878a5a4
MA		 3309#define IWL_DELAY_NEXT_SCAN (HZ*2)
3310
1dda6d28 3311void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3312{
246ed355 3313 struct iwl_rxon_context *ctx;
b481de9c 3314 struct ieee80211_conf *conf = NULL;
857485c0 3315 int ret = 0;
b481de9c 3316
1dda6d28
JB		 3317 if (!vif || !priv->is_open)
3318 return;
3319
246ed355
JB		 3320 ctx = iwl_rxon_ctx_from_vif(vif);
3321
1dda6d28 3322 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3323 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 3324 return;
3325 }
3326
b481de9c
ZY		 3327 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3328 return;
3329
2a421b91 3330 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3331
b481de9c
ZY		 3332 conf = ieee80211_get_hw_conf(priv->hw);
3333
246ed355
JB		 3334 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3335 iwlcore_commit_rxon(priv, ctx);
b481de9c 3336
47313e34 3337 ret = iwl_send_rxon_timing(priv, ctx);
857485c0 3338 if (ret)
8f2d3d2a 3339 IWL_WARN(priv, "RXON timing - "
b481de9c
ZY		 3340 "Attempting to continue.\n");
3341
246ed355 3342 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3343
42eb7c64 3344 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3345
45823531 3346 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3347 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
45823531 3348
246ed355 3349 ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3350
e1623446 3351 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3352 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3353
c213d745 3354 if (vif->bss_conf.use_short_preamble)
246ed355 3355 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3356 else
246ed355 3357 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3358
246ed355 3359 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3360 if (vif->bss_conf.use_short_slot)
246ed355 3361 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3362 else
246ed355 3363 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3364 }
3365
246ed355 3366 iwlcore_commit_rxon(priv, ctx);
b481de9c 3367
fe6b23dd 3368 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
246ed355 3369 vif->bss_conf.aid, ctx->active.bssid_addr);
fe6b23dd 3370
1dda6d28 3371 switch (vif->type) {
05c914fe 3372 case NL80211_IFTYPE_STATION:
b481de9c 3373 break;
05c914fe 3374 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3375 iwl_send_beacon_cmd(priv);
b481de9c 3376 break;
b481de9c 3377 default:
15b1687c 3378 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3379 __func__, vif->type);
b481de9c
ZY		 3380 break;
3381 }
3382
04816448
GE		 3383 /* the chain noise calibration will enabled PM upon completion
3384 * If chain noise has already been run, then we need to enable
3385 * power management here */
3386 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3387 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3388
3389 /* Enable Rx differential gain and sensitivity calibrations */
3390 iwl_chain_noise_reset(priv);
3391 priv->start_calib = 1;
3392
508e32e1
RC		 3393}
3394
b481de9c
ZY		 3395/*****************************************************************************
3396 *
3397 * mac80211 entry point functions
3398 *
3399 *****************************************************************************/
3400
154b25ce 3401#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3402
f0b6e2e8
RC		 3403/*
3404 * Not a mac80211 entry point function, but it fits in with all the
3405 * other mac80211 functions grouped here.
3406 */
dd7a2509
JB		 3407static int iwl_mac_setup_register(struct iwl_priv *priv,
3408 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3409{
3410 int ret;
3411 struct ieee80211_hw *hw = priv->hw;
d0fe478c
JB		 3412 struct iwl_rxon_context *ctx;
3413
f0b6e2e8
RC		 3414 hw->rate_control_algorithm = "iwl-agn-rs";
3415
3416 /* Tell mac80211 our characteristics */
3417 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8 3418 IEEE80211_HW_AMPDU_AGGREGATION |
2491fa42 3419 IEEE80211_HW_NEED_DTIM_PERIOD |
f0b6e2e8
RC		 3420 IEEE80211_HW_SPECTRUM_MGMT;
3421
7cb1b088 3422 if (!priv->cfg->base_params->broken_powersave)
f0b6e2e8
RC		 3423 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3424 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3425
ba37a3d0
JB		 3426 if (priv->cfg->sku & IWL_SKU_N)
3427 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3428 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3429
8d9698b3 3430 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3431 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3432
d0fe478c
JB		 3433 for_each_context(priv, ctx) {
3434 hw->wiphy->interface_modes |= ctx->interface_modes;
3435 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3436 }
f0b6e2e8 3437
f6c8f152 3438 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3439 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3440
3441 /*
3442 * For now, disable PS by default because it affects
3443 * RX performance significantly.
3444 */
5be83de5 3445 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3446
1382c71c 3447 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3448 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3449 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3450
3451 /* Default value; 4 EDCA QOS priorities */
3452 hw->queues = 4;
3453
3454 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3455
3456 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3457 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3458 &priv->bands[IEEE80211_BAND_2GHZ];
3459 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3460 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3461 &priv->bands[IEEE80211_BAND_5GHZ];
3462
3463 ret = ieee80211_register_hw(priv->hw);
3464 if (ret) {
3465 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3466 return ret;
3467 }
3468 priv->mac80211_registered = 1;
3469
3470 return 0;
3471}
3472
3473
5b9f8cd3 3474static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3475{
c79dd5b5 3476 struct iwl_priv *priv = hw->priv;
5a66926a 3477 int ret;
b481de9c 3478
e1623446 3479 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3480
3481 /* we should be verifying the device is ready to be opened */
3482 mutex_lock(&priv->mutex);
5b9f8cd3 3483 ret = __iwl_up(priv);
b481de9c 3484 mutex_unlock(&priv->mutex);
5a66926a 3485
e655b9f0 3486 if (ret)
6cd0b1cb 3487 return ret;
e655b9f0 3488
c1842d61
TW		 3489 if (iwl_is_rfkill(priv))
3490 goto out;
3491
e1623446 3492 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3493
fe9b6b72 3494 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3495 * mac80211 will not be run successfully. */
154b25ce
EG		 3496 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3497 test_bit(STATUS_READY, &priv->status),
3498 UCODE_READY_TIMEOUT);
3499 if (!ret) {
3500 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3501 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3502 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3503 return -ETIMEDOUT;
5a66926a 3504 }
fe9b6b72 3505 }
0a078ffa 3506
e932a609
JB		 3507 iwl_led_start(priv);
3508
c1842d61 3509out:
0a078ffa 3510 priv->is_open = 1;
e1623446 3511 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3512 return 0;
3513}
3514
5b9f8cd3 3515static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3516{
c79dd5b5 3517 struct iwl_priv *priv = hw->priv;
b481de9c 3518
e1623446 3519 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3520
19cc1087 3521 if (!priv->is_open)
e655b9f0 3522 return;
e655b9f0 3523
b481de9c 3524 priv->is_open = 0;
5a66926a 3525
5b9f8cd3 3526 iwl_down(priv);
5a66926a
ZY		 3527
3528 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3529
3530 /* enable interrupts again in order to receive rfkill changes */
3531 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3532 iwl_enable_interrupts(priv);
948c171c 3533
e1623446 3534 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3535}
3536
5b9f8cd3 3537static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3538{
c79dd5b5 3539 struct iwl_priv *priv = hw->priv;
b481de9c 3540
e1623446 3541 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3542
e1623446 3543 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3544 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3545
74bcdb33 3546 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3547 dev_kfree_skb_any(skb);
3548
e1623446 3549 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3550 return NETDEV_TX_OK;
b481de9c
ZY		 3551}
3552
1dda6d28 3553void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3554{
246ed355 3555 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
857485c0 3556 int ret = 0;
b481de9c 3557
76d04815
JB		 3558 lockdep_assert_held(&priv->mutex);
3559
d986bcd1 3560 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3561 return;
3562
3563 /* The following should be done only at AP bring up */
246ed355 3564 if (!iwl_is_associated_ctx(ctx)) {
b481de9c
ZY		 3565
3566 /* RXON - unassoc (to set timing command) */
246ed355
JB		 3567 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3568 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 3569
3570 /* RXON Timing */
47313e34 3571 ret = iwl_send_rxon_timing(priv, ctx);
857485c0 3572 if (ret)
8f2d3d2a 3573 IWL_WARN(priv, "RXON timing failed - "
b481de9c
ZY		 3574 "Attempting to continue.\n");
3575
f513dfff
DH		 3576 /* AP has all antennas */
3577 priv->chain_noise_data.active_chains =
3578 priv->hw_params.valid_rx_ant;
3579 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531 3580 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3581 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c 3582
246ed355 3583 ctx->staging.assoc_id = 0;
1dda6d28 3584
c213d745 3585 if (vif->bss_conf.use_short_preamble)
246ed355 3586 ctx->staging.flags |=
b481de9c
ZY		 3587 RXON_FLG_SHORT_PREAMBLE_MSK;
3588 else
246ed355 3589 ctx->staging.flags &=
b481de9c
ZY		 3590 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3591
246ed355 3592 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3593 if (vif->bss_conf.use_short_slot)
246ed355 3594 ctx->staging.flags |=
b481de9c
ZY		 3595 RXON_FLG_SHORT_SLOT_MSK;
3596 else
246ed355 3597 ctx->staging.flags &=
b481de9c 3598 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3599 }
08abc53c
JB		 3600 /* need to send beacon cmd before committing assoc RXON! */
3601 iwl_send_beacon_cmd(priv);
b481de9c 3602 /* restore RXON assoc */
246ed355
JB		 3603 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3604 iwlcore_commit_rxon(priv, ctx);
e1493deb 3605 }
5b9f8cd3 3606 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3607
3608 /* FIXME - we need to add code here to detect a totally new
3609 * configuration, reset the AP, unassoc, rxon timing, assoc,
3610 * clear sta table, add BCAST sta... */
3611}
3612
5b9f8cd3 3613static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3614 struct ieee80211_vif *vif,
3615 struct ieee80211_key_conf *keyconf,
3616 struct ieee80211_sta *sta,
3617 u32 iv32, u16 *phase1key)
ab885f8c 3618{
ab885f8c 3619
9f58671e 3620 struct iwl_priv *priv = hw->priv;
a194e324
JB		 3621 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3622
e1623446 3623 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3624
a194e324 3625 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 3626 iv32, phase1key);
ab885f8c 3627
e1623446 3628 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3629}
3630
5b9f8cd3 3631static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3632 struct ieee80211_vif *vif,
3633 struct ieee80211_sta *sta,
b481de9c
ZY		 3634 struct ieee80211_key_conf *key)
3635{
c79dd5b5 3636 struct iwl_priv *priv = hw->priv;
a194e324 3637 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
c10afb6e 3638 struct iwl_rxon_context *ctx = vif_priv->ctx;
42986796
WT		 3639 int ret;
3640 u8 sta_id;
3641 bool is_default_wep_key = false;
b481de9c 3642
e1623446 3643 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3644
90e8e424 3645 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3646 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3647 return -EOPNOTSUPP;
3648 }
b481de9c 3649
a194e324 3650 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB		 3651 if (sta_id == IWL_INVALID_STATION)
3652 return -EINVAL;
b481de9c 3653
6974e363 3654 mutex_lock(&priv->mutex);
2a421b91 3655 iwl_scan_cancel_timeout(priv, 100);
6974e363 3656
a90178fa
JB		 3657 /*
3658 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3659 * so far, we are in legacy wep mode (group key only), otherwise we are
3660 * in 1X mode.
a90178fa
JB		 3661 * In legacy wep mode, we use another host command to the uCode.
3662 */
97359d12
JB		 3663 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3664 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 3665 !sta) {
6974e363 3666 if (cmd == SET_KEY)
c10afb6e 3667 is_default_wep_key = !ctx->key_mapping_keys;
6974e363 3668 else
ccc038ab
EG		 3669 is_default_wep_key =
3670 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3671 }
052c4b9f 3672
b481de9c 3673 switch (cmd) {
deb09c43 3674 case SET_KEY:
6974e363 3675 if (is_default_wep_key)
2995bafa 3676 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 3677 else
a194e324
JB		 3678 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3679 key, sta_id);
deb09c43 3680
e1623446 3681 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3682 break;
3683 case DISABLE_KEY:
6974e363 3684 if (is_default_wep_key)
c10afb6e 3685 ret = iwl_remove_default_wep_key(priv, ctx, key);
deb09c43 3686 else
c10afb6e 3687 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
deb09c43 3688
e1623446 3689 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3690 break;
3691 default:
deb09c43 3692 ret = -EINVAL;
b481de9c
ZY		 3693 }
3694
72e15d71 3695 mutex_unlock(&priv->mutex);
e1623446 3696 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3697
deb09c43 3698 return ret;
b481de9c
ZY		 3699}
3700
5b9f8cd3 3701static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3702 struct ieee80211_vif *vif,
832f47e3
JB		 3703 enum ieee80211_ampdu_mlme_action action,
3704 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3705{
3706 struct iwl_priv *priv = hw->priv;
4620fefa 3707 int ret = -EINVAL;
d783b061 3708
e1623446 3709 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3710 sta->addr, tid);
d783b061
TW		 3711
3712 if (!(priv->cfg->sku & IWL_SKU_N))
3713 return -EACCES;
3714
4620fefa
JB		 3715 mutex_lock(&priv->mutex);
3716
d783b061
TW		 3717 switch (action) {
3718 case IEEE80211_AMPDU_RX_START:
e1623446 3719 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3720 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3721 break;
d783b061 3722 case IEEE80211_AMPDU_RX_STOP:
e1623446 3723 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3724 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3725 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3726 ret = 0;
3727 break;
d783b061 3728 case IEEE80211_AMPDU_TX_START:
e1623446 3729 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3730 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3731 if (ret == 0) {
3732 priv->_agn.agg_tids_count++;
3733 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3734 priv->_agn.agg_tids_count);
3735 }
4620fefa 3736 break;
d783b061 3737 case IEEE80211_AMPDU_TX_STOP:
e1623446 3738 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3739 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3740 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3741 priv->_agn.agg_tids_count--;
3742 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3743 priv->_agn.agg_tids_count);
3744 }
5c2207c6 3745 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 3746 ret = 0;
7cb1b088
WYG		 3747 if (priv->cfg->ht_params &&
3748 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3749 struct iwl_station_priv *sta_priv =
3750 (void *) sta->drv_priv;
3751 /*
3752 * switch off RTS/CTS if it was previously enabled
3753 */
3754
3755 sta_priv->lq_sta.lq.general_params.flags &=
3756 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3757 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3758 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
94597ab2 3759 }
4620fefa 3760 break;
f0527971 3761 case IEEE80211_AMPDU_TX_OPERATIONAL:
7cb1b088
WYG		 3762 if (priv->cfg->ht_params &&
3763 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3764 struct iwl_station_priv *sta_priv =
3765 (void *) sta->drv_priv;
3766
cfecc6b4
WYG		 3767 /*
3768 * switch to RTS/CTS if it is the prefer protection
3769 * method for HT traffic
3770 */
94597ab2
JB		 3771
3772 sta_priv->lq_sta.lq.general_params.flags |=
3773 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3774 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3775 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
cfecc6b4
WYG		 3776 }
3777 ret = 0;
d783b061
TW		 3778 break;
3779 }
4620fefa
JB		 3780 mutex_unlock(&priv->mutex);
3781
3782 return ret;
d783b061 3783}
9f58671e 3784
6ab10ff8
JB		 3785static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3786 struct ieee80211_vif *vif,
3787 enum sta_notify_cmd cmd,
3788 struct ieee80211_sta *sta)
3789{
3790 struct iwl_priv *priv = hw->priv;
3791 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3792 int sta_id;
3793
6ab10ff8 3794 switch (cmd) {
6ab10ff8
JB		 3795 case STA_NOTIFY_SLEEP:
3796 WARN_ON(!sta_priv->client);
3797 sta_priv->asleep = true;
3798 if (atomic_read(&sta_priv->pending_frames) > 0)
3799 ieee80211_sta_block_awake(hw, sta, true);
3800 break;
3801 case STA_NOTIFY_AWAKE:
3802 WARN_ON(!sta_priv->client);
49dcc819
DH		 3803 if (!sta_priv->asleep)
3804 break;
6ab10ff8 3805 sta_priv->asleep = false;
2a87c26b 3806 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3807 if (sta_id != IWL_INVALID_STATION)
3808 iwl_sta_modify_ps_wake(priv, sta_id);
3809 break;
3810 default:
3811 break;
3812 }
3813}
3814
fe6b23dd
RC		 3815static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3816 struct ieee80211_vif *vif,
3817 struct ieee80211_sta *sta)
3818{
3819 struct iwl_priv *priv = hw->priv;
3820 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 3821 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 3822 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3823 int ret;
3824 u8 sta_id;
3825
3826 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3827 sta->addr);
da5ae1cf
RC		 3828 mutex_lock(&priv->mutex);
3829 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3830 sta->addr);
3831 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3832
3833 atomic_set(&sta_priv->pending_frames, 0);
3834 if (vif->type == NL80211_IFTYPE_AP)
3835 sta_priv->client = true;
3836
a194e324 3837 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
238d781d 3838 is_ap, sta, &sta_id);
fe6b23dd
RC		 3839 if (ret) {
3840 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3841 sta->addr, ret);
3842 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3843 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3844 return ret;
3845 }
3846
fd1af15d
JB		 3847 sta_priv->common.sta_id = sta_id;
3848
fe6b23dd 3849 /* Initialize rate scaling */
91dd6c27 3850 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3851 sta->addr);
3852 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3853 mutex_unlock(&priv->mutex);
fe6b23dd 3854
fd1af15d 3855 return 0;
fe6b23dd
RC		 3856}
3857
79d07325
WYG		 3858static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3859 struct ieee80211_channel_switch *ch_switch)
3860{
3861 struct iwl_priv *priv = hw->priv;
3862 const struct iwl_channel_info *ch_info;
3863 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 3864 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 3865 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB		 3866 /*
3867 * MULTI-FIXME
3868 * When we add support for multiple interfaces, we need to
3869 * revisit this. The channel switch command in the device
3870 * only affects the BSS context, but what does that really
3871 * mean? And what if we get a CSA on the second interface?
3872 * This needs a lot of work.
3873 */
3874 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325
WYG		 3875 u16 ch;
3876 unsigned long flags = 0;
3877
3878 IWL_DEBUG_MAC80211(priv, "enter\n");
3879
3880 if (iwl_is_rfkill(priv))
3881 goto out_exit;
3882
3883 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3884 test_bit(STATUS_SCANNING, &priv->status))
3885 goto out_exit;
3886
246ed355 3887 if (!iwl_is_associated_ctx(ctx))
79d07325
WYG		 3888 goto out_exit;
3889
3890 /* channel switch in progress */
3891 if (priv->switch_rxon.switch_in_progress == true)
3892 goto out_exit;
3893
3894 mutex_lock(&priv->mutex);
3895 if (priv->cfg->ops->lib->set_channel_switch) {
3896
aa2dc6b5 3897 ch = channel->hw_value;
246ed355 3898 if (le16_to_cpu(ctx->active.channel) != ch) {
79d07325 3899 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 3900 channel->band,
79d07325
WYG		 3901 ch);
3902 if (!is_channel_valid(ch_info)) {
3903 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3904 goto out;
3905 }
3906 spin_lock_irqsave(&priv->lock, flags);
3907
3908 priv->current_ht_config.smps = conf->smps_mode;
3909
3910 /* Configure HT40 channels */
7e6a5886
JB		 3911 ctx->ht.enabled = conf_is_ht(conf);
3912 if (ctx->ht.enabled) {
79d07325 3913 if (conf_is_ht40_minus(conf)) {
7e6a5886 3914 ctx->ht.extension_chan_offset =
79d07325 3915 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
7e6a5886 3916 ctx->ht.is_40mhz = true;
79d07325 3917 } else if (conf_is_ht40_plus(conf)) {
7e6a5886 3918 ctx->ht.extension_chan_offset =
79d07325 3919 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
7e6a5886 3920 ctx->ht.is_40mhz = true;
79d07325 3921 } else {
7e6a5886 3922 ctx->ht.extension_chan_offset =
79d07325 3923 IEEE80211_HT_PARAM_CHA_SEC_NONE;
7e6a5886 3924 ctx->ht.is_40mhz = false;
79d07325
WYG		 3925 }
3926 } else
7e6a5886 3927 ctx->ht.is_40mhz = false;
79d07325 3928
246ed355
JB		 3929 if ((le16_to_cpu(ctx->staging.channel) != ch))
3930 ctx->staging.flags = 0;
79d07325 3931
246ed355 3932 iwl_set_rxon_channel(priv, channel, ctx);
79d07325 3933 iwl_set_rxon_ht(priv, ht_conf);
246ed355 3934 iwl_set_flags_for_band(priv, ctx, channel->band,
8bd413e6 3935 ctx->vif);
79d07325
WYG		 3936 spin_unlock_irqrestore(&priv->lock, flags);
3937
3938 iwl_set_rate(priv);
3939 /*
3940 * at this point, staging_rxon has the
3941 * configuration for channel switch
3942 */
3943 if (priv->cfg->ops->lib->set_channel_switch(priv,
3944 ch_switch))
3945 priv->switch_rxon.switch_in_progress = false;
3946 }
3947 }
3948out:
3949 mutex_unlock(&priv->mutex);
3950out_exit:
3951 if (!priv->switch_rxon.switch_in_progress)
8bd413e6 3952 ieee80211_chswitch_done(ctx->vif, false);
79d07325
WYG		 3953 IWL_DEBUG_MAC80211(priv, "leave\n");
3954}
3955
8b8ab9d5
JB		 3956static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3957 unsigned int changed_flags,
3958 unsigned int *total_flags,
3959 u64 multicast)
3960{
3961 struct iwl_priv *priv = hw->priv;
3962 __le32 filter_or = 0, filter_nand = 0;
246ed355 3963 struct iwl_rxon_context *ctx;
8b8ab9d5
JB		 3964
3965#define CHK(test, flag) do { \
3966 if (*total_flags & (test)) \
3967 filter_or |= (flag); \
3968 else \
3969 filter_nand |= (flag); \
3970 } while (0)
3971
3972 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3973 changed_flags, *total_flags);
3974
3975 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3976 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3977 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3978
3979#undef CHK
3980
3981 mutex_lock(&priv->mutex);
3982
246ed355
JB		 3983 for_each_context(priv, ctx) {
3984 ctx->staging.filter_flags &= ~filter_nand;
3985 ctx->staging.filter_flags |= filter_or;
749ff4ef
SG		 3986
3987 /*
3988 * Not committing directly because hardware can perform a scan,
3989 * but we'll eventually commit the filter flags change anyway.
3990 */
246ed355 3991 }
8b8ab9d5
JB		 3992
3993 mutex_unlock(&priv->mutex);
3994
3995 /*
3996 * Receiving all multicast frames is always enabled by the
3997 * default flags setup in iwl_connection_init_rx_config()
3998 * since we currently do not support programming multicast
3999 * filters into the device.
4000 */
4001 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
4002 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4003}
4004
716c74b0
WYG		 4005static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
4006{
4007 struct iwl_priv *priv = hw->priv;
4008
4009 mutex_lock(&priv->mutex);
4010 IWL_DEBUG_MAC80211(priv, "enter\n");
4011
4012 /* do not support "flush" */
4013 if (!priv->cfg->ops->lib->txfifo_flush)
4014 goto done;
4015
4016 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4017 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
4018 goto done;
4019 }
4020 if (iwl_is_rfkill(priv)) {
4021 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
4022 goto done;
4023 }
4024
4025 /*
4026 * mac80211 will not push any more frames for transmit
4027 * until the flush is completed
4028 */
4029 if (drop) {
4030 IWL_DEBUG_MAC80211(priv, "send flush command\n");
4031 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
4032 IWL_ERR(priv, "flush request fail\n");
4033 goto done;
4034 }
4035 }
4036 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
4037 iwlagn_wait_tx_queue_empty(priv);
4038done:
4039 mutex_unlock(&priv->mutex);
4040 IWL_DEBUG_MAC80211(priv, "leave\n");
4041}
4042
b481de9c
ZY		 4043/*****************************************************************************
4044 *
4045 * driver setup and teardown
4046 *
4047 *****************************************************************************/
4048
4e39317d 4049static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 4050{
d21050c7 4051 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 4052
4053 init_waitqueue_head(&priv->wait_command_queue);
4054
5b9f8cd3
EG		 4055 INIT_WORK(&priv->restart, iwl_bg_restart);
4056 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 4057 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 4058 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 4059 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 4060 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 4061 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4a4a9e81
TW		 4062 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4063 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 4064
2a421b91 4065 iwl_setup_scan_deferred_work(priv);
bb8c093b 4066
4e39317d
EG		 4067 if (priv->cfg->ops->lib->setup_deferred_work)
4068 priv->cfg->ops->lib->setup_deferred_work(priv);
4069
4070 init_timer(&priv->statistics_periodic);
4071 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 4072 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 4073
a9e1cb6a
WYG		 4074 init_timer(&priv->ucode_trace);
4075 priv->ucode_trace.data = (unsigned long)priv;
4076 priv->ucode_trace.function = iwl_bg_ucode_trace;
4077
b74e31a9
WYG		 4078 if (priv->cfg->ops->lib->recover_from_tx_stall) {
4079 init_timer(&priv->monitor_recover);
4080 priv->monitor_recover.data = (unsigned long)priv;
4081 priv->monitor_recover.function =
4082 priv->cfg->ops->lib->recover_from_tx_stall;
4083 }
4084
7cb1b088 4085 if (!priv->cfg->base_params->use_isr_legacy)
ef850d7c
MA		 4086 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4087 iwl_irq_tasklet, (unsigned long)priv);
4088 else
4089 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4090 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 4091}
4092
4e39317d 4093static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 4094{
4e39317d
EG		 4095 if (priv->cfg->ops->lib->cancel_deferred_work)
4096 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 4097
3ae6a054 4098 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 4099 cancel_delayed_work(&priv->alive_start);
815e629b 4100 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 4101 cancel_work_sync(&priv->beacon_update);
e7e16b90
SG		 4102
4103 iwl_cancel_scan_deferred_work(priv);
4104
bee008b7 4105 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 4106 cancel_work_sync(&priv->bt_runtime_config);
e7e16b90 4107
4e39317d 4108 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 4109 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 4110}
4111
89f186a8
RC		 4112static void iwl_init_hw_rates(struct iwl_priv *priv,
4113 struct ieee80211_rate *rates)
4114{
4115 int i;
4116
4117 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4118 rates[i].bitrate = iwl_rates[i].ieee * 5;
4119 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4120 rates[i].hw_value_short = i;
4121 rates[i].flags = 0;
4122 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4123 /*
4124 * If CCK != 1M then set short preamble rate flag.
4125 */
4126 rates[i].flags |=
4127 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4128 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4129 }
4130 }
4131}
4132
4133static int iwl_init_drv(struct iwl_priv *priv)
4134{
4135 int ret;
4136
89f186a8
RC		 4137 spin_lock_init(&priv->sta_lock);
4138 spin_lock_init(&priv->hcmd_lock);
4139
4140 INIT_LIST_HEAD(&priv->free_frames);
4141
4142 mutex_init(&priv->mutex);
d2dfe6df 4143 mutex_init(&priv->sync_cmd_mutex);
89f186a8 4144
89f186a8
RC		 4145 priv->ieee_channels = NULL;
4146 priv->ieee_rates = NULL;
4147 priv->band = IEEE80211_BAND_2GHZ;
4148
4149 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 4150 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 4151 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 4152 priv->_agn.agg_tids_count = 0;
89f186a8 4153
8a472da4
WYG		 4154 /* initialize force reset */
4155 priv->force_reset[IWL_RF_RESET].reset_duration =
4156 IWL_DELAY_NEXT_FORCE_RF_RESET;
4157 priv->force_reset[IWL_FW_RESET].reset_duration =
4158 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 4159
4160 /* Choose which receivers/antennas to use */
4161 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355
JB		 4162 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4163 &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC		 4164
4165 iwl_init_scan_params(priv);
4166
22bf59a0 4167 /* init bt coex */
7cb1b088
WYG		 4168 if (priv->cfg->bt_params &&
4169 priv->cfg->bt_params->advanced_bt_coexist) {
b6e116e8
WYG		 4170 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4171 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4172 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 4173 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4174 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4175 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4176 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4177 }
4178
89f186a8
RC		 4179 /* Set the tx_power_user_lmt to the lowest power level
4180 * this value will get overwritten by channel max power avg
4181 * from eeprom */
b744cb79 4182 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
a25a66ac 4183 priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 4184
4185 ret = iwl_init_channel_map(priv);
4186 if (ret) {
4187 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4188 goto err;
4189 }
4190
4191 ret = iwlcore_init_geos(priv);
4192 if (ret) {
4193 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4194 goto err_free_channel_map;
4195 }
4196 iwl_init_hw_rates(priv, priv->ieee_rates);
4197
4198 return 0;
4199
4200err_free_channel_map:
4201 iwl_free_channel_map(priv);
4202err:
4203 return ret;
4204}
4205
4206static void iwl_uninit_drv(struct iwl_priv *priv)
4207{
4208 iwl_calib_free_results(priv);
4209 iwlcore_free_geos(priv);
4210 iwl_free_channel_map(priv);
811ecc99 4211 kfree(priv->scan_cmd);
89f186a8
RC		 4212}
4213
5b9f8cd3
EG		 4214static struct ieee80211_ops iwl_hw_ops = {
4215 .tx = iwl_mac_tx,
4216 .start = iwl_mac_start,
4217 .stop = iwl_mac_stop,
4218 .add_interface = iwl_mac_add_interface,
4219 .remove_interface = iwl_mac_remove_interface,
4220 .config = iwl_mac_config,
8b8ab9d5 4221 .configure_filter = iwlagn_configure_filter,
5b9f8cd3
EG		 4222 .set_key = iwl_mac_set_key,
4223 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 4224 .conf_tx = iwl_mac_conf_tx,
4225 .reset_tsf = iwl_mac_reset_tsf,
4226 .bss_info_changed = iwl_bss_info_changed,
4227 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 4228 .hw_scan = iwl_mac_hw_scan,
4229 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 4230 .sta_add = iwlagn_mac_sta_add,
4231 .sta_remove = iwl_mac_sta_remove,
79d07325 4232 .channel_switch = iwl_mac_channel_switch,
716c74b0 4233 .flush = iwl_mac_flush,
a85d7cca 4234 .tx_last_beacon = iwl_mac_tx_last_beacon,
b481de9c
ZY		 4235};
4236
3867fe04
WYG		 4237static void iwl_hw_detect(struct iwl_priv *priv)
4238{
4239 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4240 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4241 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
49ded76b 4242 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3867fe04
WYG		 4243}
4244
07d4f1ad
WYG		 4245static int iwl_set_hw_params(struct iwl_priv *priv)
4246{
4247 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4248 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4249 if (priv->cfg->mod_params->amsdu_size_8K)
4250 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4251 else
4252 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4253
4254 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4255
4256 if (priv->cfg->mod_params->disable_11n)
4257 priv->cfg->sku &= ~IWL_SKU_N;
4258
4259 /* Device-specific setup */
4260 return priv->cfg->ops->lib->set_hw_params(priv);
4261}
4262
e72f368b
JB		 4263static const u8 iwlagn_bss_ac_to_fifo[] = {
4264 IWL_TX_FIFO_VO,
4265 IWL_TX_FIFO_VI,
4266 IWL_TX_FIFO_BE,
4267 IWL_TX_FIFO_BK,
4268};
4269
4270static const u8 iwlagn_bss_ac_to_queue[] = {
4271 0, 1, 2, 3,
4272};
4273
4274static const u8 iwlagn_pan_ac_to_fifo[] = {
4275 IWL_TX_FIFO_VO_IPAN,
4276 IWL_TX_FIFO_VI_IPAN,
4277 IWL_TX_FIFO_BE_IPAN,
4278 IWL_TX_FIFO_BK_IPAN,
4279};
4280
4281static const u8 iwlagn_pan_ac_to_queue[] = {
4282 7, 6, 5, 4,
4283};
4284
5b9f8cd3 4285static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 4286{
246ed355 4287 int err = 0, i;
c79dd5b5 4288 struct iwl_priv *priv;
b481de9c 4289 struct ieee80211_hw *hw;
82b9a121 4290 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 4291 unsigned long flags;
c6fa17ed 4292 u16 pci_cmd, num_mac;
b481de9c 4293
316c30d9
AK		 4294 /************************
4295 * 1. Allocating HW data
4296 ************************/
4297
6440adb5
BC		 4298 /* Disabling hardware scan means that mac80211 will perform scans
4299 * "the hard way", rather than using device's scan. */
1ea87396 4300 if (cfg->mod_params->disable_hw_scan) {
72645eff
WYG		 4301 dev_printk(KERN_DEBUG, &(pdev->dev),
4302 "sw scan support is deprecated\n");
5b9f8cd3 4303 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 4304 }
4305
5b9f8cd3 4306 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 4307 if (!hw) {
b481de9c
ZY		 4308 err = -ENOMEM;
4309 goto out;
4310 }
1d0a082d
AK		 4311 priv = hw->priv;
4312 /* At this point both hw and priv are allocated. */
4313
246ed355
JB		 4314 /*
4315 * The default context is always valid,
4316 * more may be discovered when firmware
4317 * is loaded.
4318 */
4319 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4320
4321 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4322 priv->contexts[i].ctxid = i;
4323
763cc3bf
JB		 4324 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4325 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
8f2d3d2a
JB		 4326 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4327 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4328 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 4329 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 4330 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 4331 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
e72f368b
JB		 4332 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4333 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
d0fe478c
JB		 4334 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4335 BIT(NL80211_IFTYPE_ADHOC);
4336 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4337 BIT(NL80211_IFTYPE_STATION);
4338 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4339 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4340 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
ece9c4ee
JB		 4341
4342 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4343 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4344 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4345 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4346 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4347 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4348 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4349 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
e72f368b
JB		 4350 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4351 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4352 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
d0fe478c
JB		 4353 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4354 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4355 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4356 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4357 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
ece9c4ee
JB		 4358
4359 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
8f2d3d2a 4360
b481de9c
ZY		 4361 SET_IEEE80211_DEV(hw, &pdev->dev);
4362
e1623446 4363 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 4364 priv->cfg = cfg;
b481de9c 4365 priv->pci_dev = pdev;
40cefda9 4366 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 4367
bee008b7
WYG		 4368 /* is antenna coupling more than 35dB ? */
4369 priv->bt_ant_couple_ok =
4370 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4371 true : false;
4372
f37837c9
WYG		 4373 /* enable/disable bt channel announcement */
4374 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4375
20594eb0
WYG		 4376 if (iwl_alloc_traffic_mem(priv))
4377 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4378
316c30d9
AK		 4379 /**************************
4380 * 2. Initializing PCI bus
4381 **************************/
1a7123cd
JL		 4382 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4383 PCIE_LINK_STATE_CLKPM);
4384
316c30d9
AK		 4385 if (pci_enable_device(pdev)) {
4386 err = -ENODEV;
4387 goto out_ieee80211_free_hw;
4388 }
4389
4390 pci_set_master(pdev);
4391
093d874c 4392 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 4393 if (!err)
093d874c 4394 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 4395 if (err) {
093d874c 4396 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4397 if (!err)
093d874c 4398 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4399 /* both attempts failed: */
316c30d9 4400 if (err) {
978785a3 4401 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 4402 goto out_pci_disable_device;
cc2a8ea8 4403 }
316c30d9
AK		 4404 }
4405
4406 err = pci_request_regions(pdev, DRV_NAME);
4407 if (err)
4408 goto out_pci_disable_device;
4409
4410 pci_set_drvdata(pdev, priv);
4411
316c30d9
AK		 4412
4413 /***********************
4414 * 3. Read REV register
4415 ***********************/
4416 priv->hw_base = pci_iomap(pdev, 0, 0);
4417 if (!priv->hw_base) {
4418 err = -ENODEV;
4419 goto out_pci_release_regions;
4420 }
4421
e1623446 4422 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4423 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4424 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4425
731a29b7 4426 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4427 * we should init now
4428 */
4429 spin_lock_init(&priv->reg_lock);
731a29b7 4430 spin_lock_init(&priv->lock);
4843b5a7
RC		 4431
4432 /*
4433 * stop and reset the on-board processor just in case it is in a
4434 * strange state ... like being left stranded by a primary kernel
4435 * and this is now the kdump kernel trying to start up
4436 */
4437 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4438
b661c819 4439 iwl_hw_detect(priv);
c11362c0 4440 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4441 priv->cfg->name, priv->hw_rev);
316c30d9 4442
e7b63581
TW		 4443 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4444 * PCI Tx retries from interfering with C3 CPU state */
4445 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4446
086ed117
MA		 4447 iwl_prepare_card_hw(priv);
4448 if (!priv->hw_ready) {
4449 IWL_WARN(priv, "Failed, HW not ready\n");
4450 goto out_iounmap;
4451 }
4452
91238714
TW		 4453 /*****************
4454 * 4. Read EEPROM
4455 *****************/
316c30d9
AK		 4456 /* Read the EEPROM */
4457 err = iwl_eeprom_init(priv);
4458 if (err) {
15b1687c 4459 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4460 goto out_iounmap;
4461 }
8614f360
TW		 4462 err = iwl_eeprom_check_version(priv);
4463 if (err)
c8f16138 4464 goto out_free_eeprom;
8614f360 4465
02883017 4466 /* extract MAC Address */
c6fa17ed
WYG		 4467 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4468 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4469 priv->hw->wiphy->addresses = priv->addresses;
4470 priv->hw->wiphy->n_addresses = 1;
4471 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4472 if (num_mac > 1) {
4473 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4474 ETH_ALEN);
4475 priv->addresses[1].addr[5]++;
4476 priv->hw->wiphy->n_addresses++;
4477 }
316c30d9
AK		 4478
4479 /************************
4480 * 5. Setup HW constants
4481 ************************/
da154e30 4482 if (iwl_set_hw_params(priv)) {
15b1687c 4483 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4484 goto out_free_eeprom;
316c30d9
AK		 4485 }
4486
4487 /*******************
6ba87956 4488 * 6. Setup priv
316c30d9 4489 *******************/
b481de9c 4490
6ba87956 4491 err = iwl_init_drv(priv);
bf85ea4f 4492 if (err)
399f4900 4493 goto out_free_eeprom;
bf85ea4f 4494 /* At this point both hw and priv are initialized. */
316c30d9 4495
316c30d9 4496 /********************
09f9bf79 4497 * 7. Setup services
316c30d9 4498 ********************/
0359facc 4499 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4500 iwl_disable_interrupts(priv);
0359facc 4501 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4502
6cd0b1cb
HS		 4503 pci_enable_msi(priv->pci_dev);
4504
ef850d7c
MA		 4505 iwl_alloc_isr_ict(priv);
4506 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4507 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4508 if (err) {
4509 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4510 goto out_disable_msi;
4511 }
316c30d9 4512
4e39317d 4513 iwl_setup_deferred_work(priv);
653fa4a0 4514 iwl_setup_rx_handlers(priv);
316c30d9 4515
158bea07
JB		 4516 /*********************************************
4517 * 8. Enable interrupts and read RFKILL state
4518 *********************************************/
6ba87956 4519
6cd0b1cb
HS		 4520 /* enable interrupts if needed: hw bug w/a */
4521 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4522 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4523 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4524 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4525 }
4526
4527 iwl_enable_interrupts(priv);
4528
6cd0b1cb
HS		 4529 /* If platform's RF_KILL switch is NOT set to KILL */
4530 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4531 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4532 else
4533 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4534
a60e77e5
JB		 4535 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4536 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4537
58d0f361 4538 iwl_power_initialize(priv);
39b73fb1 4539 iwl_tt_initialize(priv);
158bea07 4540
a15707d8 4541 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4542
b08dfd04 4543 err = iwl_request_firmware(priv, true);
158bea07 4544 if (err)
7d47618a 4545 goto out_destroy_workqueue;
158bea07 4546
b481de9c
ZY		 4547 return 0;
4548
7d47618a 4549 out_destroy_workqueue:
c8f16138
RC		 4550 destroy_workqueue(priv->workqueue);
4551 priv->workqueue = NULL;
795cc0ad 4552 free_irq(priv->pci_dev->irq, priv);
ef850d7c 4553 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 4554 out_disable_msi:
4555 pci_disable_msi(priv->pci_dev);
6ba87956 4556 iwl_uninit_drv(priv);
073d3f5f
TW		 4557 out_free_eeprom:
4558 iwl_eeprom_free(priv);
b481de9c
ZY		 4559 out_iounmap:
4560 pci_iounmap(pdev, priv->hw_base);
4561 out_pci_release_regions:
316c30d9 4562 pci_set_drvdata(pdev, NULL);
623d563e 4563 pci_release_regions(pdev);
b481de9c
ZY		 4564 out_pci_disable_device:
4565 pci_disable_device(pdev);
b481de9c 4566 out_ieee80211_free_hw:
20594eb0 4567 iwl_free_traffic_mem(priv);
d7c76f4c 4568 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4569 out:
4570 return err;
4571}
4572
5b9f8cd3 4573static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4574{
c79dd5b5 4575 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4576 unsigned long flags;
b481de9c
ZY		 4577
4578 if (!priv)
4579 return;
4580
a15707d8 4581 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4582
e1623446 4583 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4584
67249625 4585 iwl_dbgfs_unregister(priv);
5b9f8cd3 4586 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4587
5b9f8cd3
EG		 4588 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4589 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4590 * we need to set STATUS_EXIT_PENDING bit.
4591 */
4592 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4593 if (priv->mac80211_registered) {
4594 ieee80211_unregister_hw(priv->hw);
4595 priv->mac80211_registered = 0;
0b124c31 4596 } else {
5b9f8cd3 4597 iwl_down(priv);
c4f55232
RR		 4598 }
4599
c166b25a
BC		 4600 /*
4601 * Make sure device is reset to low power before unloading driver.
4602 * This may be redundant with iwl_down(), but there are paths to
4603 * run iwl_down() without calling apm_ops.stop(), and there are
4604 * paths to avoid running iwl_down() at all before leaving driver.
4605 * This (inexpensive) call *makes sure* device is reset.
4606 */
14e8e4af 4607 iwl_apm_stop(priv);
c166b25a 4608
39b73fb1
WYG		 4609 iwl_tt_exit(priv);
4610
0359facc
MA		 4611 /* make sure we flush any pending irq or
4612 * tasklet for the driver
4613 */
4614 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4615 iwl_disable_interrupts(priv);
0359facc
MA		 4616 spin_unlock_irqrestore(&priv->lock, flags);
4617
4618 iwl_synchronize_irq(priv);
4619
5b9f8cd3 4620 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4621
4622 if (priv->rxq.bd)
54b81550 4623 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4624 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4625
073d3f5f 4626 iwl_eeprom_free(priv);
b481de9c 4627
b481de9c 4628
948c171c
MA		 4629 /*netif_stop_queue(dev); */
4630 flush_workqueue(priv->workqueue);
4631
5b9f8cd3 4632 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4633 * priv->workqueue... so we can't take down the workqueue
4634 * until now... */
4635 destroy_workqueue(priv->workqueue);
4636 priv->workqueue = NULL;
20594eb0 4637 iwl_free_traffic_mem(priv);
b481de9c 4638
6cd0b1cb
HS		 4639 free_irq(priv->pci_dev->irq, priv);
4640 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4641 pci_iounmap(pdev, priv->hw_base);
4642 pci_release_regions(pdev);
4643 pci_disable_device(pdev);
4644 pci_set_drvdata(pdev, NULL);
4645
6ba87956 4646 iwl_uninit_drv(priv);
b481de9c 4647
ef850d7c
MA		 4648 iwl_free_isr_ict(priv);
4649
77834543 4650 dev_kfree_skb(priv->beacon_skb);
b481de9c
ZY		 4651
4652 ieee80211_free_hw(priv->hw);
4653}
4654
b481de9c
ZY		 4655
4656/*****************************************************************************
4657 *
4658 * driver and module entry point
4659 *
4660 *****************************************************************************/
4661
fed9017e 4662/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4663static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4664#ifdef CONFIG_IWL4965
fed9017e
RR		 4665 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4666 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4667#endif /* CONFIG_IWL4965 */
5a6a256e 4668#ifdef CONFIG_IWL5000
ac592574
WYG		 4669/* 5100 Series WiFi */
4670 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4671 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4672 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4673 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4674 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4675 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4676 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4677 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4678 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4679 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4680 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4681 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4682 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4683 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4684 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4685 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4686 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4687 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4688 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4689 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4690 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4691 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4692 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4693 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4694
4695/* 5300 Series WiFi */
4696 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4697 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4698 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4699 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4700 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4701 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4702 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4703 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4704 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4705 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4706 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4707 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4708
4709/* 5350 Series WiFi/WiMax */
4710 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4711 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4712 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4713
4714/* 5150 Series Wifi/WiMax */
4715 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4716 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4717 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4718 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4719 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4720 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4721
4722 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4723 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4724 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4725 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4726
4727/* 6x00 Series */
5953a62e
WYG		 4728 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4729 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4730 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4731 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4732 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4733 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4734 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4735 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4736 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4737 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4738
95b13014
SZ		 4739/* 6x00 Series Gen2a */
4740 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4741 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4742 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4743 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4744 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4745 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4746 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4747 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4748 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4749 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4750 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4751 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4752 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4753 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4754
4755/* 6x00 Series Gen2b */
4756 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4757 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4758 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4759 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4760 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4761 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4762 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4763 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4764 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4765 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4766 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4767 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4768 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4769 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4770 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4771 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4772 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4773 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4774 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4775 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4776 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4777 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4778 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4779 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4780 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4781 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4782 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4783 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4784
4785/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4786 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4787 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4788 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4789 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4790 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4791 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4792
03264339
SZ		 4793/* 6x50 WiFi/WiMax Series Gen2 */
4794 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4795 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4796 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4797 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4798 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4799 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4800
77dcb6a9 4801/* 1000 Series WiFi */
4bd0914f
WYG		 4802 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4803 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4804 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4805 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4806 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4807 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4808 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4809 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4810 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4811 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4812 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4813 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
1de19ecc 4814
58a39090 4815/* 100 Series WiFi */
1de19ecc
JS		 4816 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4817 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4818 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4819 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4820 {IWL_PCI_DEVICE(0x08AE, 0x1017, iwl100_bg_cfg)},
58a39090
WYG		 4821
4822/* 130 Series WiFi */
4823 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4824 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4825 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4826 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4827 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4828 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4829
5a6a256e 4830#endif /* CONFIG_IWL5000 */
7100e924 4831
fed9017e
RR		 4832 {0}
4833};
4834MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4835
4836static struct pci_driver iwl_driver = {
b481de9c 4837 .name = DRV_NAME,
fed9017e 4838 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4839 .probe = iwl_pci_probe,
4840 .remove = __devexit_p(iwl_pci_remove),
f60dc013 4841 .driver.pm = IWL_PM_OPS,
b481de9c
ZY		 4842};
4843
5b9f8cd3 4844static int __init iwl_init(void)
b481de9c
ZY		 4845{
4846
4847 int ret;
c96c31e4
JP		 4848 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4849 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4850
e227ceac 4851 ret = iwlagn_rate_control_register();
897e1cf2 4852 if (ret) {
c96c31e4 4853 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4854 return ret;
4855 }
4856
fed9017e 4857 ret = pci_register_driver(&iwl_driver);
b481de9c 4858 if (ret) {
c96c31e4 4859 pr_err("Unable to initialize PCI module\n");
897e1cf2 4860 goto error_register;
b481de9c 4861 }
b481de9c
ZY		 4862
4863 return ret;
897e1cf2 4864
897e1cf2 4865error_register:
e227ceac 4866 iwlagn_rate_control_unregister();
897e1cf2 4867 return ret;
b481de9c
ZY		 4868}
4869
5b9f8cd3 4870static void __exit iwl_exit(void)
b481de9c 4871{
fed9017e 4872 pci_unregister_driver(&iwl_driver);
e227ceac 4873 iwlagn_rate_control_unregister();
b481de9c
ZY		 4874}
4875
5b9f8cd3
EG		 4876module_exit(iwl_exit);
4877module_init(iwl_init);
a562a9dd
RC		 4878
4879#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4880module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4881MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4882module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4883MODULE_PARM_DESC(debug, "debug output mask");
4884#endif
4885
2b068618
WYG		 4886module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4887MODULE_PARM_DESC(swcrypto50,
4888 "using crypto in software (default 0 [hardware]) (deprecated)");
4889module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4890MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4891module_param_named(queues_num50,
4892 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4893MODULE_PARM_DESC(queues_num50,
4894 "number of hw queues in 50xx series (deprecated)");
4895module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4896MODULE_PARM_DESC(queues_num, "number of hw queues.");
4897module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4898MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4899module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4900MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4901module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4902 int, S_IRUGO);
4903MODULE_PARM_DESC(amsdu_size_8K50,
4904 "enable 8K amsdu size in 50XX series (deprecated)");
4905module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4906 int, S_IRUGO);
4907MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4908module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4909MODULE_PARM_DESC(fw_restart50,
4910 "restart firmware in case of error (deprecated)");
4911module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4912MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4913module_param_named(
4914 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
72645eff
WYG		 4915MODULE_PARM_DESC(disable_hw_scan,
4916 "disable hardware scanning (default 0) (deprecated)");
dd7a2509
JB		 4917
4918module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4919 S_IRUGO);
4920MODULE_PARM_DESC(ucode_alternative,
4921 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 4922
4923module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4924MODULE_PARM_DESC(antenna_coupling,
4925 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9
WYG		 4926
4927module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4928MODULE_PARM_DESC(bt_ch_announce,
4929 "Enable BT channel announcement mode (default: enable)");
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