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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
b481de9c ZY |
35 | #include <linux/dma-mapping.h> |
36 | #include <linux/delay.h> | |
d43c36dc | 37 | #include <linux/sched.h> |
b481de9c ZY |
38 | #include <linux/skbuff.h> |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/wireless.h> | |
41 | #include <linux/firmware.h> | |
b481de9c ZY |
42 | #include <linux/etherdevice.h> |
43 | #include <linux/if_arp.h> | |
44 | ||
b481de9c ZY |
45 | #include <net/mac80211.h> |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
a3139c59 SO |
49 | #define DRV_NAME "iwlagn" |
50 | ||
6bc913bd | 51 | #include "iwl-eeprom.h" |
3e0d4cb1 | 52 | #include "iwl-dev.h" |
fee1247a | 53 | #include "iwl-core.h" |
3395f6e9 | 54 | #include "iwl-io.h" |
b481de9c | 55 | #include "iwl-helpers.h" |
6974e363 | 56 | #include "iwl-sta.h" |
f0832f13 | 57 | #include "iwl-calib.h" |
a1175124 | 58 | #include "iwl-agn.h" |
b481de9c | 59 | |
416e1438 | 60 | |
b481de9c ZY |
61 | /****************************************************************************** |
62 | * | |
63 | * module boiler plate | |
64 | * | |
65 | ******************************************************************************/ | |
66 | ||
b481de9c ZY |
67 | /* |
68 | * module name, copyright, version, etc. | |
b481de9c | 69 | */ |
d783b061 | 70 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 71 | |
0a6857e7 | 72 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
73 | #define VD "d" |
74 | #else | |
75 | #define VD | |
76 | #endif | |
77 | ||
81963d68 | 78 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 79 | |
b481de9c ZY |
80 | |
81 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
82 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 83 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 84 | MODULE_LICENSE("GPL"); |
4fc22b21 | 85 | MODULE_ALIAS("iwl4965"); |
b481de9c | 86 | |
b481de9c | 87 | /** |
5b9f8cd3 | 88 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 89 | * |
01ebd063 | 90 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
91 | * the active_rxon structure is updated with the new data. This |
92 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
93 | * a HW tune is required based on the RXON structure changes. | |
94 | */ | |
e0158e61 | 95 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
96 | { |
97 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 98 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
99 | int ret; |
100 | bool new_assoc = | |
101 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 102 | |
fee1247a | 103 | if (!iwl_is_alive(priv)) |
43d59b32 | 104 | return -EBUSY; |
b481de9c ZY |
105 | |
106 | /* always get timestamp with Rx frame */ | |
107 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
108 | ||
8ccde88a | 109 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 110 | if (ret) { |
15b1687c | 111 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
112 | return -EINVAL; |
113 | } | |
114 | ||
0924e519 WYG |
115 | /* |
116 | * receive commit_rxon request | |
117 | * abort any previous channel switch if still in process | |
118 | */ | |
119 | if (priv->switch_rxon.switch_in_progress && | |
120 | (priv->switch_rxon.channel != priv->staging_rxon.channel)) { | |
121 | IWL_DEBUG_11H(priv, "abort channel switch on %d\n", | |
122 | le16_to_cpu(priv->switch_rxon.channel)); | |
79d07325 | 123 | iwl_chswitch_done(priv, false); |
0924e519 WYG |
124 | } |
125 | ||
b481de9c | 126 | /* If we don't need to send a full RXON, we can use |
5b9f8cd3 | 127 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 128 | * and other flags for the current radio configuration. */ |
54559703 | 129 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
130 | ret = iwl_send_rxon_assoc(priv); |
131 | if (ret) { | |
15b1687c | 132 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 133 | return ret; |
b481de9c ZY |
134 | } |
135 | ||
136 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
a643565e | 137 | iwl_print_rx_config_cmd(priv); |
b481de9c ZY |
138 | return 0; |
139 | } | |
140 | ||
b481de9c ZY |
141 | /* If we are currently associated and the new config requires |
142 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
143 | * we must clear the associated from the active configuration | |
144 | * before we apply the new config */ | |
43d59b32 | 145 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 146 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
147 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
148 | ||
43d59b32 | 149 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 150 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
151 | &priv->active_rxon); |
152 | ||
153 | /* If the mask clearing failed then we set | |
154 | * active_rxon back to what it was previously */ | |
43d59b32 | 155 | if (ret) { |
b481de9c | 156 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 157 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 158 | return ret; |
b481de9c | 159 | } |
2c810ccd | 160 | iwl_clear_ucode_stations(priv); |
7e246191 | 161 | iwl_restore_stations(priv); |
335348b1 JB |
162 | ret = iwl_restore_default_wep_keys(priv); |
163 | if (ret) { | |
164 | IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret); | |
165 | return ret; | |
166 | } | |
b481de9c ZY |
167 | } |
168 | ||
e1623446 | 169 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
170 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
171 | "* channel = %d\n" | |
e174961c | 172 | "* bssid = %pM\n", |
43d59b32 | 173 | (new_assoc ? "" : "out"), |
b481de9c | 174 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 175 | priv->staging_rxon.bssid_addr); |
b481de9c | 176 | |
90e8e424 | 177 | iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto); |
43d59b32 EG |
178 | |
179 | /* Apply the new configuration | |
7e246191 RC |
180 | * RXON unassoc clears the station table in uCode so restoration of |
181 | * stations is needed after it (the RXON command) completes | |
43d59b32 EG |
182 | */ |
183 | if (!new_assoc) { | |
184 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 185 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 186 | if (ret) { |
15b1687c | 187 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
188 | return ret; |
189 | } | |
91dd6c27 | 190 | IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n"); |
43d59b32 | 191 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); |
2c810ccd | 192 | iwl_clear_ucode_stations(priv); |
7e246191 | 193 | iwl_restore_stations(priv); |
335348b1 JB |
194 | ret = iwl_restore_default_wep_keys(priv); |
195 | if (ret) { | |
196 | IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret); | |
197 | return ret; | |
198 | } | |
b481de9c ZY |
199 | } |
200 | ||
19cc1087 | 201 | priv->start_calib = 0; |
9185159d | 202 | if (new_assoc) { |
47eef9bd WYG |
203 | /* |
204 | * allow CTS-to-self if possible for new association. | |
205 | * this is relevant only for 5000 series and up, | |
206 | * but will not damage 4965 | |
207 | */ | |
208 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
209 | ||
43d59b32 EG |
210 | /* Apply the new configuration |
211 | * RXON assoc doesn't clear the station table in uCode, | |
212 | */ | |
213 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
214 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
215 | if (ret) { | |
15b1687c | 216 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
217 | return ret; |
218 | } | |
219 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c | 220 | } |
a643565e | 221 | iwl_print_rx_config_cmd(priv); |
b481de9c | 222 | |
36da7d70 ZY |
223 | iwl_init_sensitivity(priv); |
224 | ||
225 | /* If we issue a new RXON command which required a tune then we must | |
226 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
227 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
228 | if (ret) { | |
15b1687c | 229 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
230 | return ret; |
231 | } | |
232 | ||
b481de9c ZY |
233 | return 0; |
234 | } | |
235 | ||
5b9f8cd3 | 236 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
237 | { |
238 | ||
45823531 AK |
239 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
240 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 241 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
242 | } |
243 | ||
fcab423d | 244 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
245 | { |
246 | struct list_head *element; | |
247 | ||
e1623446 | 248 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
249 | priv->frames_count); |
250 | ||
251 | while (!list_empty(&priv->free_frames)) { | |
252 | element = priv->free_frames.next; | |
253 | list_del(element); | |
fcab423d | 254 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
255 | priv->frames_count--; |
256 | } | |
257 | ||
258 | if (priv->frames_count) { | |
39aadf8c | 259 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
260 | priv->frames_count); |
261 | priv->frames_count = 0; | |
262 | } | |
263 | } | |
264 | ||
fcab423d | 265 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 266 | { |
fcab423d | 267 | struct iwl_frame *frame; |
b481de9c ZY |
268 | struct list_head *element; |
269 | if (list_empty(&priv->free_frames)) { | |
270 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
271 | if (!frame) { | |
15b1687c | 272 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
273 | return NULL; |
274 | } | |
275 | ||
276 | priv->frames_count++; | |
277 | return frame; | |
278 | } | |
279 | ||
280 | element = priv->free_frames.next; | |
281 | list_del(element); | |
fcab423d | 282 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
283 | } |
284 | ||
fcab423d | 285 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
286 | { |
287 | memset(frame, 0, sizeof(*frame)); | |
288 | list_add(&frame->list, &priv->free_frames); | |
289 | } | |
290 | ||
47ff65c4 | 291 | static u32 iwl_fill_beacon_frame(struct iwl_priv *priv, |
4bf64efd | 292 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 293 | int left) |
b481de9c | 294 | { |
3109ece1 | 295 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
296 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
297 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
298 | return 0; |
299 | ||
300 | if (priv->ibss_beacon->len > left) | |
301 | return 0; | |
302 | ||
303 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
304 | ||
305 | return priv->ibss_beacon->len; | |
306 | } | |
307 | ||
47ff65c4 DH |
308 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
309 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
310 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, | |
311 | u8 *beacon, u32 frame_size) | |
312 | { | |
313 | u16 tim_idx; | |
314 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
315 | ||
316 | /* | |
317 | * The index is relative to frame start but we start looking at the | |
318 | * variable-length part of the beacon. | |
319 | */ | |
320 | tim_idx = mgmt->u.beacon.variable - beacon; | |
321 | ||
322 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
323 | while ((tim_idx < (frame_size - 2)) && | |
324 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
325 | tim_idx += beacon[tim_idx+1] + 2; | |
326 | ||
327 | /* If TIM field was found, set variables */ | |
328 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
329 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
330 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
331 | } else | |
332 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
333 | } | |
334 | ||
5b9f8cd3 | 335 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
47ff65c4 | 336 | struct iwl_frame *frame) |
4bf64efd TW |
337 | { |
338 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
47ff65c4 DH |
339 | u32 frame_size; |
340 | u32 rate_flags; | |
341 | u32 rate; | |
342 | /* | |
343 | * We have to set up the TX command, the TX Beacon command, and the | |
344 | * beacon contents. | |
345 | */ | |
4bf64efd | 346 | |
47ff65c4 | 347 | /* Initialize memory */ |
4bf64efd TW |
348 | tx_beacon_cmd = &frame->u.beacon; |
349 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
350 | ||
47ff65c4 | 351 | /* Set up TX beacon contents */ |
4bf64efd | 352 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, |
4bf64efd | 353 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
47ff65c4 DH |
354 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
355 | return 0; | |
4bf64efd | 356 | |
47ff65c4 | 357 | /* Set up TX command fields */ |
4bf64efd | 358 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
47ff65c4 DH |
359 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; |
360 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
361 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
362 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 363 | |
47ff65c4 DH |
364 | /* Set up TX beacon command fields */ |
365 | iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, | |
366 | frame_size); | |
4bf64efd | 367 | |
47ff65c4 DH |
368 | /* Set up packet rate and flags */ |
369 | rate = iwl_rate_get_lowest_plcp(priv); | |
0e1654fa JB |
370 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, |
371 | priv->hw_params.valid_tx_ant); | |
47ff65c4 DH |
372 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); |
373 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
374 | rate_flags |= RATE_MCS_CCK_MSK; | |
375 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
376 | rate_flags); | |
4bf64efd TW |
377 | |
378 | return sizeof(*tx_beacon_cmd) + frame_size; | |
379 | } | |
5b9f8cd3 | 380 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 381 | { |
fcab423d | 382 | struct iwl_frame *frame; |
b481de9c ZY |
383 | unsigned int frame_size; |
384 | int rc; | |
b481de9c | 385 | |
fcab423d | 386 | frame = iwl_get_free_frame(priv); |
b481de9c | 387 | if (!frame) { |
15b1687c | 388 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
389 | "command.\n"); |
390 | return -ENOMEM; | |
391 | } | |
392 | ||
47ff65c4 DH |
393 | frame_size = iwl_hw_get_beacon_cmd(priv, frame); |
394 | if (!frame_size) { | |
395 | IWL_ERR(priv, "Error configuring the beacon command\n"); | |
396 | iwl_free_frame(priv, frame); | |
397 | return -EINVAL; | |
398 | } | |
b481de9c | 399 | |
857485c0 | 400 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
401 | &frame->u.cmd[0]); |
402 | ||
fcab423d | 403 | iwl_free_frame(priv, frame); |
b481de9c ZY |
404 | |
405 | return rc; | |
406 | } | |
407 | ||
7aaa1d79 SO |
408 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
409 | { | |
410 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
411 | ||
412 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
413 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
414 | addr |= | |
415 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
416 | ||
417 | return addr; | |
418 | } | |
419 | ||
420 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
421 | { | |
422 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
423 | ||
424 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
425 | } | |
426 | ||
427 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
428 | dma_addr_t addr, u16 len) | |
429 | { | |
430 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
431 | u16 hi_n_len = len << 4; | |
432 | ||
433 | put_unaligned_le32(addr, &tb->lo); | |
434 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
435 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
436 | ||
437 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
438 | ||
439 | tfd->num_tbs = idx + 1; | |
440 | } | |
441 | ||
442 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
443 | { | |
444 | return tfd->num_tbs & 0x1f; | |
445 | } | |
446 | ||
447 | /** | |
448 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
449 | * @priv - driver private data | |
450 | * @txq - tx queue | |
451 | * | |
452 | * Does NOT advance any TFD circular buffer read/write indexes | |
453 | * Does NOT free the TFD itself (which is within circular buffer) | |
454 | */ | |
455 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
456 | { | |
59606ffa | 457 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
458 | struct iwl_tfd *tfd; |
459 | struct pci_dev *dev = priv->pci_dev; | |
460 | int index = txq->q.read_ptr; | |
461 | int i; | |
462 | int num_tbs; | |
463 | ||
464 | tfd = &tfd_tmp[index]; | |
465 | ||
466 | /* Sanity check on number of chunks */ | |
467 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
468 | ||
469 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
470 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
471 | /* @todo issue fatal error, it is quite serious situation */ | |
472 | return; | |
473 | } | |
474 | ||
475 | /* Unmap tx_cmd */ | |
476 | if (num_tbs) | |
477 | pci_unmap_single(dev, | |
2e724443 FT |
478 | dma_unmap_addr(&txq->meta[index], mapping), |
479 | dma_unmap_len(&txq->meta[index], len), | |
96891cee | 480 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
481 | |
482 | /* Unmap chunks, if any. */ | |
ff0d91c3 | 483 | for (i = 1; i < num_tbs; i++) |
7aaa1d79 SO |
484 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), |
485 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
486 | ||
ff0d91c3 JB |
487 | /* free SKB */ |
488 | if (txq->txb) { | |
489 | struct sk_buff *skb; | |
6f80240e | 490 | |
ff0d91c3 | 491 | skb = txq->txb[txq->q.read_ptr].skb; |
6f80240e | 492 | |
ff0d91c3 JB |
493 | /* can be called from irqs-disabled context */ |
494 | if (skb) { | |
495 | dev_kfree_skb_any(skb); | |
496 | txq->txb[txq->q.read_ptr].skb = NULL; | |
7aaa1d79 SO |
497 | } |
498 | } | |
499 | } | |
500 | ||
501 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
502 | struct iwl_tx_queue *txq, | |
503 | dma_addr_t addr, u16 len, | |
504 | u8 reset, u8 pad) | |
505 | { | |
506 | struct iwl_queue *q; | |
59606ffa | 507 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
508 | u32 num_tbs; |
509 | ||
510 | q = &txq->q; | |
59606ffa SO |
511 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
512 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
513 | |
514 | if (reset) | |
515 | memset(tfd, 0, sizeof(*tfd)); | |
516 | ||
517 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
518 | ||
519 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
520 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
521 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
522 | IWL_NUM_OF_TBS); | |
523 | return -EINVAL; | |
524 | } | |
525 | ||
526 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
527 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
528 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
529 | (unsigned long long)addr); | |
530 | ||
531 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
a8e74e27 SO |
536 | /* |
537 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
538 | * given Tx queue, and enable the DMA channel used for that queue. | |
539 | * | |
540 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
541 | * channels supported in hardware. | |
542 | */ | |
543 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
544 | struct iwl_tx_queue *txq) | |
545 | { | |
a8e74e27 SO |
546 | int txq_id = txq->q.id; |
547 | ||
a8e74e27 SO |
548 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
549 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
550 | txq->q.dma_addr >> 8); | |
551 | ||
a8e74e27 SO |
552 | return 0; |
553 | } | |
554 | ||
b481de9c ZY |
555 | /****************************************************************************** |
556 | * | |
557 | * Generic RX handler implementations | |
558 | * | |
559 | ******************************************************************************/ | |
885ba202 TW |
560 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
561 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 562 | { |
2f301227 | 563 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
885ba202 | 564 | struct iwl_alive_resp *palive; |
b481de9c ZY |
565 | struct delayed_work *pwork; |
566 | ||
567 | palive = &pkt->u.alive_frame; | |
568 | ||
e1623446 | 569 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
570 | "0x%01X 0x%01X\n", |
571 | palive->is_valid, palive->ver_type, | |
572 | palive->ver_subtype); | |
573 | ||
574 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 575 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
576 | memcpy(&priv->card_alive_init, |
577 | &pkt->u.alive_frame, | |
885ba202 | 578 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
579 | pwork = &priv->init_alive_start; |
580 | } else { | |
e1623446 | 581 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 582 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 583 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
584 | pwork = &priv->alive_start; |
585 | } | |
586 | ||
587 | /* We delay the ALIVE response by 5ms to | |
588 | * give the HW RF Kill time to activate... */ | |
589 | if (palive->is_valid == UCODE_VALID_OK) | |
590 | queue_delayed_work(priv->workqueue, pwork, | |
591 | msecs_to_jiffies(5)); | |
592 | else | |
39aadf8c | 593 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
594 | } |
595 | ||
5b9f8cd3 | 596 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 597 | { |
c79dd5b5 TW |
598 | struct iwl_priv *priv = |
599 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
600 | struct sk_buff *beacon; |
601 | ||
602 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 603 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
604 | |
605 | if (!beacon) { | |
15b1687c | 606 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
607 | return; |
608 | } | |
609 | ||
610 | mutex_lock(&priv->mutex); | |
611 | /* new beacon skb is allocated every time; dispose previous.*/ | |
612 | if (priv->ibss_beacon) | |
613 | dev_kfree_skb(priv->ibss_beacon); | |
614 | ||
615 | priv->ibss_beacon = beacon; | |
616 | mutex_unlock(&priv->mutex); | |
617 | ||
5b9f8cd3 | 618 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
619 | } |
620 | ||
4e39317d | 621 | /** |
5b9f8cd3 | 622 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
623 | * |
624 | * This callback is provided in order to send a statistics request. | |
625 | * | |
626 | * This timer function is continually reset to execute within | |
627 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
628 | * was received. We need to ensure we receive the statistics in order | |
629 | * to update the temperature used for calibrating the TXPOWER. | |
630 | */ | |
5b9f8cd3 | 631 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
632 | { |
633 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
634 | ||
635 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
636 | return; | |
637 | ||
61780ee3 MA |
638 | /* dont send host command if rf-kill is on */ |
639 | if (!iwl_is_ready_rf(priv)) | |
640 | return; | |
641 | ||
ef8d5529 | 642 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
643 | } |
644 | ||
a9e1cb6a WYG |
645 | |
646 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
647 | u32 start_idx, u32 num_events, | |
648 | u32 mode) | |
649 | { | |
650 | u32 i; | |
651 | u32 ptr; /* SRAM byte address of log data */ | |
652 | u32 ev, time, data; /* event log data */ | |
653 | unsigned long reg_flags; | |
654 | ||
655 | if (mode == 0) | |
656 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
657 | else | |
658 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
659 | ||
660 | /* Make sure device is powered up for SRAM reads */ | |
661 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
662 | if (iwl_grab_nic_access(priv)) { | |
663 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
664 | return; | |
665 | } | |
666 | ||
667 | /* Set starting address; reads will auto-increment */ | |
668 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
669 | rmb(); | |
670 | ||
671 | /* | |
672 | * "time" is actually "data" for mode 0 (no timestamp). | |
673 | * place event id # at far right for easier visual parsing. | |
674 | */ | |
675 | for (i = 0; i < num_events; i++) { | |
676 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
677 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
678 | if (mode == 0) { | |
679 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
680 | 0, time, ev); | |
681 | } else { | |
682 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
683 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
684 | time, data, ev); | |
685 | } | |
686 | } | |
687 | /* Allow device to power down */ | |
688 | iwl_release_nic_access(priv); | |
689 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
690 | } | |
691 | ||
875295f1 | 692 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
693 | { |
694 | u32 capacity; /* event log capacity in # entries */ | |
695 | u32 base; /* SRAM byte address of event log header */ | |
696 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
697 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
698 | u32 next_entry; /* index of next entry to be written by uCode */ | |
699 | ||
700 | if (priv->ucode_type == UCODE_INIT) | |
701 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
702 | else | |
703 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
704 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
705 | capacity = iwl_read_targ_mem(priv, base); | |
706 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
707 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
708 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
709 | } else | |
710 | return; | |
711 | ||
712 | if (num_wraps == priv->event_log.num_wraps) { | |
713 | iwl_print_cont_event_trace(priv, | |
714 | base, priv->event_log.next_entry, | |
715 | next_entry - priv->event_log.next_entry, | |
716 | mode); | |
717 | priv->event_log.non_wraps_count++; | |
718 | } else { | |
719 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
720 | priv->event_log.wraps_more_count++; | |
721 | else | |
722 | priv->event_log.wraps_once_count++; | |
723 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
724 | num_wraps - priv->event_log.num_wraps, | |
725 | next_entry, priv->event_log.next_entry); | |
726 | if (next_entry < priv->event_log.next_entry) { | |
727 | iwl_print_cont_event_trace(priv, base, | |
728 | priv->event_log.next_entry, | |
729 | capacity - priv->event_log.next_entry, | |
730 | mode); | |
731 | ||
732 | iwl_print_cont_event_trace(priv, base, 0, | |
733 | next_entry, mode); | |
734 | } else { | |
735 | iwl_print_cont_event_trace(priv, base, | |
736 | next_entry, capacity - next_entry, | |
737 | mode); | |
738 | ||
739 | iwl_print_cont_event_trace(priv, base, 0, | |
740 | next_entry, mode); | |
741 | } | |
742 | } | |
743 | priv->event_log.num_wraps = num_wraps; | |
744 | priv->event_log.next_entry = next_entry; | |
745 | } | |
746 | ||
747 | /** | |
748 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
749 | * | |
750 | * The timer is continually set to execute every | |
751 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
752 | * this function is to perform continuous uCode event logging operation | |
753 | * if enabled | |
754 | */ | |
755 | static void iwl_bg_ucode_trace(unsigned long data) | |
756 | { | |
757 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
758 | ||
759 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
760 | return; | |
761 | ||
762 | if (priv->event_log.ucode_trace) { | |
763 | iwl_continuous_event_trace(priv); | |
764 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
765 | mod_timer(&priv->ucode_trace, | |
766 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
767 | } | |
768 | } | |
769 | ||
5b9f8cd3 | 770 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 771 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 772 | { |
0a6857e7 | 773 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 774 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
2aa6ab86 TW |
775 | struct iwl4965_beacon_notif *beacon = |
776 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 777 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 778 | |
e1623446 | 779 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 780 | "tsf %d %d rate %d\n", |
25a6572c | 781 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
782 | beacon->beacon_notify_hdr.failure_frame, |
783 | le32_to_cpu(beacon->ibss_mgr_status), | |
784 | le32_to_cpu(beacon->high_tsf), | |
785 | le32_to_cpu(beacon->low_tsf), rate); | |
786 | #endif | |
787 | ||
05c914fe | 788 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
789 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
790 | queue_work(priv->workqueue, &priv->beacon_update); | |
791 | } | |
792 | ||
b481de9c ZY |
793 | /* Handle notification from uCode that card's power state is changing |
794 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 795 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 796 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 797 | { |
2f301227 | 798 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
799 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
800 | unsigned long status = priv->status; | |
801 | ||
3a41bbd5 | 802 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n", |
b481de9c | 803 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
3a41bbd5 WYG |
804 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", |
805 | (flags & CT_CARD_DISABLED) ? | |
806 | "Reached" : "Not reached"); | |
b481de9c ZY |
807 | |
808 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3a41bbd5 | 809 | CT_CARD_DISABLED)) { |
b481de9c | 810 | |
3395f6e9 | 811 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
812 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
813 | ||
a8b50a0a MA |
814 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
815 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
816 | |
817 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 818 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 819 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 820 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 821 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 822 | } |
3a41bbd5 | 823 | if (flags & CT_CARD_DISABLED) |
39b73fb1 | 824 | iwl_tt_enter_ct_kill(priv); |
b481de9c | 825 | } |
3a41bbd5 | 826 | if (!(flags & CT_CARD_DISABLED)) |
39b73fb1 | 827 | iwl_tt_exit_ct_kill(priv); |
b481de9c ZY |
828 | |
829 | if (flags & HW_CARD_DISABLED) | |
830 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
831 | else | |
832 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
833 | ||
834 | ||
b481de9c | 835 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 836 | iwl_scan_cancel(priv); |
b481de9c ZY |
837 | |
838 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
839 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
840 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
841 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
842 | else |
843 | wake_up_interruptible(&priv->wait_command_queue); | |
844 | } | |
845 | ||
5b9f8cd3 | 846 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 847 | { |
e2e3c57b | 848 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 849 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
850 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
851 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
852 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
853 | } else { | |
854 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
855 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
856 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
857 | } | |
858 | ||
a8b50a0a | 859 | return 0; |
e2e3c57b TW |
860 | } |
861 | ||
65550636 WYG |
862 | static void iwl_bg_tx_flush(struct work_struct *work) |
863 | { | |
864 | struct iwl_priv *priv = | |
865 | container_of(work, struct iwl_priv, tx_flush); | |
866 | ||
867 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
868 | return; | |
869 | ||
870 | /* do nothing if rf-kill is on */ | |
871 | if (!iwl_is_ready_rf(priv)) | |
872 | return; | |
873 | ||
874 | if (priv->cfg->ops->lib->txfifo_flush) { | |
875 | IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n"); | |
876 | iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL); | |
877 | } | |
878 | } | |
879 | ||
b481de9c | 880 | /** |
5b9f8cd3 | 881 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
882 | * |
883 | * Setup the RX handlers for each of the reply types sent from the uCode | |
884 | * to the host. | |
885 | * | |
886 | * This function chains into the hardware specific files for them to setup | |
887 | * any hardware specific handlers as well. | |
888 | */ | |
653fa4a0 | 889 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 890 | { |
885ba202 | 891 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
892 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
893 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
81963d68 RC |
894 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
895 | iwl_rx_spectrum_measure_notif; | |
5b9f8cd3 | 896 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 897 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
898 | iwl_rx_pm_debug_statistics_notif; |
899 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 900 | |
9fbab516 BC |
901 | /* |
902 | * The same handler is used for both the REPLY to a discrete | |
903 | * statistics request from the host as well as for the periodic | |
904 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 905 | */ |
ef8d5529 | 906 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics; |
8f91aecb | 907 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; |
2a421b91 TW |
908 | |
909 | iwl_setup_rx_scan_handlers(priv); | |
910 | ||
37a44211 | 911 | /* status change handler */ |
5b9f8cd3 | 912 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 913 | |
c1354754 TW |
914 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
915 | iwl_rx_missed_beacon_notif; | |
37a44211 | 916 | /* Rx handlers */ |
8d801080 WYG |
917 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy; |
918 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx; | |
653fa4a0 | 919 | /* block ack */ |
74bcdb33 | 920 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba; |
9fbab516 | 921 | /* Set up hardware specific Rx handlers */ |
d4789efe | 922 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
923 | } |
924 | ||
b481de9c | 925 | /** |
a55360e4 | 926 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
927 | * |
928 | * Uses the priv->rx_handlers callback function array to invoke | |
929 | * the appropriate handlers, including command responses, | |
930 | * frame-received notifications, and other notifications. | |
931 | */ | |
a55360e4 | 932 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 933 | { |
a55360e4 | 934 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 935 | struct iwl_rx_packet *pkt; |
a55360e4 | 936 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
937 | u32 r, i; |
938 | int reclaim; | |
939 | unsigned long flags; | |
5c0eef96 | 940 | u8 fill_rx = 0; |
d68ab680 | 941 | u32 count = 8; |
4752c93c | 942 | int total_empty; |
b481de9c | 943 | |
6440adb5 BC |
944 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
945 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 946 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
947 | i = rxq->read; |
948 | ||
949 | /* Rx interrupt, but nothing sent from uCode */ | |
950 | if (i == r) | |
e1623446 | 951 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 952 | |
4752c93c | 953 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 954 | total_empty = r - rxq->write_actual; |
4752c93c MA |
955 | if (total_empty < 0) |
956 | total_empty += RX_QUEUE_SIZE; | |
957 | ||
958 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
959 | fill_rx = 1; |
960 | ||
b481de9c | 961 | while (i != r) { |
f4989d9b JB |
962 | int len; |
963 | ||
b481de9c ZY |
964 | rxb = rxq->queue[i]; |
965 | ||
9fbab516 | 966 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
967 | * then a bug has been introduced in the queue refilling |
968 | * routines -- catch it here */ | |
969 | BUG_ON(rxb == NULL); | |
970 | ||
971 | rxq->queue[i] = NULL; | |
972 | ||
2f301227 ZY |
973 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
974 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
975 | PCI_DMA_FROMDEVICE); | |
976 | pkt = rxb_addr(rxb); | |
b481de9c | 977 | |
f4989d9b JB |
978 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
979 | len += sizeof(u32); /* account for status word */ | |
980 | trace_iwlwifi_dev_rx(priv, pkt, len); | |
be1a71a1 | 981 | |
b481de9c ZY |
982 | /* Reclaim a command buffer only if this packet is a response |
983 | * to a (driver-originated) command. | |
984 | * If the packet (e.g. Rx frame) originated from uCode, | |
985 | * there is no command buffer to reclaim. | |
986 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
987 | * but apparently a few don't get set; catch them here. */ | |
988 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
989 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 990 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 991 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 992 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
993 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
994 | (pkt->hdr.cmd != REPLY_TX); | |
995 | ||
996 | /* Based on type of command response or notification, | |
997 | * handle those that need handling via function in | |
5b9f8cd3 | 998 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 999 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 1000 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 1001 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 1002 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 1003 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
1004 | } else { |
1005 | /* No handling needed */ | |
e1623446 | 1006 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
1007 | "r %d i %d No handler needed for %s, 0x%02x\n", |
1008 | r, i, get_cmd_string(pkt->hdr.cmd), | |
1009 | pkt->hdr.cmd); | |
1010 | } | |
1011 | ||
29b1b268 ZY |
1012 | /* |
1013 | * XXX: After here, we should always check rxb->page | |
1014 | * against NULL before touching it or its virtual | |
1015 | * memory (pkt). Because some rx_handler might have | |
1016 | * already taken or freed the pages. | |
1017 | */ | |
1018 | ||
b481de9c | 1019 | if (reclaim) { |
2f301227 ZY |
1020 | /* Invoke any callbacks, transfer the buffer to caller, |
1021 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 1022 | * as we reclaim the driver command queue */ |
29b1b268 | 1023 | if (rxb->page) |
17b88929 | 1024 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1025 | else |
39aadf8c | 1026 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1027 | } |
1028 | ||
7300515d ZY |
1029 | /* Reuse the page if possible. For notification packets and |
1030 | * SKBs that fail to Rx correctly, add them back into the | |
1031 | * rx_free list for reuse later. */ | |
1032 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1033 | if (rxb->page != NULL) { |
7300515d ZY |
1034 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
1035 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
1036 | PCI_DMA_FROMDEVICE); | |
1037 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1038 | rxq->free_count++; | |
1039 | } else | |
1040 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 1041 | |
b481de9c | 1042 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 1043 | |
b481de9c | 1044 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
1045 | /* If there are a lot of unused frames, |
1046 | * restock the Rx queue so ucode wont assert. */ | |
1047 | if (fill_rx) { | |
1048 | count++; | |
1049 | if (count >= 8) { | |
7300515d | 1050 | rxq->read = i; |
54b81550 | 1051 | iwlagn_rx_replenish_now(priv); |
5c0eef96 MA |
1052 | count = 0; |
1053 | } | |
1054 | } | |
b481de9c ZY |
1055 | } |
1056 | ||
1057 | /* Backtrack one entry */ | |
7300515d | 1058 | rxq->read = i; |
4752c93c | 1059 | if (fill_rx) |
54b81550 | 1060 | iwlagn_rx_replenish_now(priv); |
4752c93c | 1061 | else |
54b81550 | 1062 | iwlagn_rx_queue_restock(priv); |
a55360e4 | 1063 | } |
a55360e4 | 1064 | |
0359facc MA |
1065 | /* call this function to flush any scheduled tasklet */ |
1066 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
1067 | { | |
a96a27f9 | 1068 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1069 | synchronize_irq(priv->pci_dev->irq); |
1070 | tasklet_kill(&priv->irq_tasklet); | |
1071 | } | |
1072 | ||
ef850d7c | 1073 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
1074 | { |
1075 | u32 inta, handled = 0; | |
1076 | u32 inta_fh; | |
1077 | unsigned long flags; | |
c2e61da2 | 1078 | u32 i; |
0a6857e7 | 1079 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1080 | u32 inta_mask; |
1081 | #endif | |
1082 | ||
1083 | spin_lock_irqsave(&priv->lock, flags); | |
1084 | ||
1085 | /* Ack/clear/reset pending uCode interrupts. | |
1086 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1087 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
1088 | inta = iwl_read32(priv, CSR_INT); |
1089 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1090 | |
1091 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1092 | * Any new interrupts that happen after this, either while we're | |
1093 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
1094 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1095 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1096 | |
0a6857e7 | 1097 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1098 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1099 | /* just for debug */ |
3395f6e9 | 1100 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1101 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1102 | inta, inta_mask, inta_fh); |
1103 | } | |
1104 | #endif | |
1105 | ||
2f301227 ZY |
1106 | spin_unlock_irqrestore(&priv->lock, flags); |
1107 | ||
b481de9c ZY |
1108 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1109 | * atomic, make sure that inta covers all the interrupts that | |
1110 | * we've discovered, even if FH interrupt came in just after | |
1111 | * reading CSR_INT. */ | |
6f83eaa1 | 1112 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 1113 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1114 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
1115 | inta |= CSR_INT_BIT_FH_TX; |
1116 | ||
1117 | /* Now service all interrupt bits discovered above. */ | |
1118 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1119 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1120 | |
1121 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 1122 | iwl_disable_interrupts(priv); |
b481de9c | 1123 | |
a83b9141 | 1124 | priv->isr_stats.hw++; |
5b9f8cd3 | 1125 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1126 | |
1127 | handled |= CSR_INT_BIT_HW_ERR; | |
1128 | ||
b481de9c ZY |
1129 | return; |
1130 | } | |
1131 | ||
0a6857e7 | 1132 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1133 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1134 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 1135 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1136 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1137 | "the frame/frames.\n"); |
a83b9141 WYG |
1138 | priv->isr_stats.sch++; |
1139 | } | |
b481de9c ZY |
1140 | |
1141 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 1142 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1143 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
1144 | priv->isr_stats.alive++; |
1145 | } | |
b481de9c ZY |
1146 | } |
1147 | #endif | |
1148 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1149 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1150 | |
9fbab516 | 1151 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1152 | if (inta & CSR_INT_BIT_RF_KILL) { |
1153 | int hw_rf_kill = 0; | |
3395f6e9 | 1154 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1155 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1156 | hw_rf_kill = 1; | |
1157 | ||
4c423a2b | 1158 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1159 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1160 | |
a83b9141 WYG |
1161 | priv->isr_stats.rfkill++; |
1162 | ||
a9efa652 | 1163 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1164 | * the driver allows loading the ucode even if the radio |
1165 | * is killed. Hence update the killswitch state here. The | |
1166 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1167 | */ |
6cd0b1cb HS |
1168 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1169 | if (hw_rf_kill) | |
1170 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1171 | else | |
1172 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1173 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 1174 | } |
b481de9c ZY |
1175 | |
1176 | handled |= CSR_INT_BIT_RF_KILL; | |
1177 | } | |
1178 | ||
9fbab516 | 1179 | /* Chip got too hot and stopped itself */ |
b481de9c | 1180 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1181 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 1182 | priv->isr_stats.ctkill++; |
b481de9c ZY |
1183 | handled |= CSR_INT_BIT_CT_KILL; |
1184 | } | |
1185 | ||
1186 | /* Error detected by uCode */ | |
1187 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1188 | IWL_ERR(priv, "Microcode SW error detected. " |
1189 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
1190 | priv->isr_stats.sw++; |
1191 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 1192 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1193 | handled |= CSR_INT_BIT_SW_ERR; |
1194 | } | |
1195 | ||
c2e61da2 BC |
1196 | /* |
1197 | * uCode wakes up after power-down sleep. | |
1198 | * Tell device about any new tx or host commands enqueued, | |
1199 | * and about any Rx buffers made available while asleep. | |
1200 | */ | |
b481de9c | 1201 | if (inta & CSR_INT_BIT_WAKEUP) { |
e1623446 | 1202 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1203 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
c2e61da2 BC |
1204 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1205 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
a83b9141 | 1206 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1207 | handled |= CSR_INT_BIT_WAKEUP; |
1208 | } | |
1209 | ||
1210 | /* All uCode command responses, including Tx command responses, | |
1211 | * Rx "responses" (frame-received notification), and other | |
1212 | * notifications from uCode come through here*/ | |
1213 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1214 | iwl_rx_handle(priv); |
a83b9141 | 1215 | priv->isr_stats.rx++; |
b481de9c ZY |
1216 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1217 | } | |
1218 | ||
c72cd19f | 1219 | /* This "Tx" DMA channel is used only for loading uCode */ |
b481de9c | 1220 | if (inta & CSR_INT_BIT_FH_TX) { |
c72cd19f | 1221 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
a83b9141 | 1222 | priv->isr_stats.tx++; |
b481de9c | 1223 | handled |= CSR_INT_BIT_FH_TX; |
c72cd19f | 1224 | /* Wake up uCode load routine, now that load is complete */ |
dbb983b7 RR |
1225 | priv->ucode_write_complete = 1; |
1226 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1227 | } |
1228 | ||
a83b9141 | 1229 | if (inta & ~handled) { |
15b1687c | 1230 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1231 | priv->isr_stats.unhandled++; |
1232 | } | |
b481de9c | 1233 | |
40cefda9 | 1234 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1235 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1236 | inta & ~priv->inta_mask); |
39aadf8c | 1237 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1238 | } |
1239 | ||
1240 | /* Re-enable all interrupts */ | |
0359facc MA |
1241 | /* only Re-enable if diabled by irq */ |
1242 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1243 | iwl_enable_interrupts(priv); |
b481de9c | 1244 | |
0a6857e7 | 1245 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1246 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1247 | inta = iwl_read32(priv, CSR_INT); |
1248 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1249 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1250 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1251 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1252 | } | |
1253 | #endif | |
b481de9c ZY |
1254 | } |
1255 | ||
ef850d7c MA |
1256 | /* tasklet for iwlagn interrupt */ |
1257 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1258 | { | |
1259 | u32 inta = 0; | |
1260 | u32 handled = 0; | |
1261 | unsigned long flags; | |
8756990f | 1262 | u32 i; |
ef850d7c MA |
1263 | #ifdef CONFIG_IWLWIFI_DEBUG |
1264 | u32 inta_mask; | |
1265 | #endif | |
1266 | ||
1267 | spin_lock_irqsave(&priv->lock, flags); | |
1268 | ||
1269 | /* Ack/clear/reset pending uCode interrupts. | |
1270 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1271 | */ | |
48a6be6a SZ |
1272 | /* There is a hardware bug in the interrupt mask function that some |
1273 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
1274 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
1275 | * ICT interrupt handling mechanism has another bug that might cause | |
1276 | * these unmasked interrupts fail to be detected. We workaround the | |
1277 | * hardware bugs here by ACKing all the possible interrupts so that | |
1278 | * interrupt coalescing can still be achieved. | |
1279 | */ | |
4a35ecf8 | 1280 | iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask); |
ef850d7c | 1281 | |
a4c8b2a6 | 1282 | inta = priv->_agn.inta; |
ef850d7c MA |
1283 | |
1284 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1285 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1286 | /* just for debug */ |
1287 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1288 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1289 | inta, inta_mask); | |
1290 | } | |
1291 | #endif | |
2f301227 ZY |
1292 | |
1293 | spin_unlock_irqrestore(&priv->lock, flags); | |
1294 | ||
a4c8b2a6 JB |
1295 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ |
1296 | priv->_agn.inta = 0; | |
ef850d7c MA |
1297 | |
1298 | /* Now service all interrupt bits discovered above. */ | |
1299 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1300 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1301 | |
1302 | /* Tell the device to stop sending interrupts */ | |
1303 | iwl_disable_interrupts(priv); | |
1304 | ||
1305 | priv->isr_stats.hw++; | |
1306 | iwl_irq_handle_error(priv); | |
1307 | ||
1308 | handled |= CSR_INT_BIT_HW_ERR; | |
1309 | ||
ef850d7c MA |
1310 | return; |
1311 | } | |
1312 | ||
1313 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1314 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1315 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1316 | if (inta & CSR_INT_BIT_SCD) { | |
1317 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1318 | "the frame/frames.\n"); | |
1319 | priv->isr_stats.sch++; | |
1320 | } | |
1321 | ||
1322 | /* Alive notification via Rx interrupt will do the real work */ | |
1323 | if (inta & CSR_INT_BIT_ALIVE) { | |
1324 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1325 | priv->isr_stats.alive++; | |
1326 | } | |
1327 | } | |
1328 | #endif | |
1329 | /* Safely ignore these bits for debug checks below */ | |
1330 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1331 | ||
1332 | /* HW RF KILL switch toggled */ | |
1333 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1334 | int hw_rf_kill = 0; | |
1335 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1336 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1337 | hw_rf_kill = 1; | |
1338 | ||
4c423a2b | 1339 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1340 | hw_rf_kill ? "disable radio" : "enable radio"); |
1341 | ||
1342 | priv->isr_stats.rfkill++; | |
1343 | ||
1344 | /* driver only loads ucode once setting the interface up. | |
1345 | * the driver allows loading the ucode even if the radio | |
1346 | * is killed. Hence update the killswitch state here. The | |
1347 | * rfkill handler will care about restarting if needed. | |
1348 | */ | |
1349 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1350 | if (hw_rf_kill) | |
1351 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1352 | else | |
1353 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1354 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1355 | } |
1356 | ||
1357 | handled |= CSR_INT_BIT_RF_KILL; | |
1358 | } | |
1359 | ||
1360 | /* Chip got too hot and stopped itself */ | |
1361 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1362 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1363 | priv->isr_stats.ctkill++; | |
1364 | handled |= CSR_INT_BIT_CT_KILL; | |
1365 | } | |
1366 | ||
1367 | /* Error detected by uCode */ | |
1368 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1369 | IWL_ERR(priv, "Microcode SW error detected. " | |
1370 | " Restarting 0x%X.\n", inta); | |
1371 | priv->isr_stats.sw++; | |
1372 | priv->isr_stats.sw_err = inta; | |
1373 | iwl_irq_handle_error(priv); | |
1374 | handled |= CSR_INT_BIT_SW_ERR; | |
1375 | } | |
1376 | ||
1377 | /* uCode wakes up after power-down sleep */ | |
1378 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1379 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1380 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
1381 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1382 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
1383 | |
1384 | priv->isr_stats.wakeup++; | |
1385 | ||
1386 | handled |= CSR_INT_BIT_WAKEUP; | |
1387 | } | |
1388 | ||
1389 | /* All uCode command responses, including Tx command responses, | |
1390 | * Rx "responses" (frame-received notification), and other | |
1391 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1392 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1393 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1394 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1395 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1396 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1397 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1398 | CSR49_FH_INT_RX_MASK); | |
1399 | } | |
1400 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1401 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1402 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1403 | } | |
1404 | /* Sending RX interrupt require many steps to be done in the | |
1405 | * the device: | |
1406 | * 1- write interrupt to current index in ICT table. | |
1407 | * 2- dma RX frame. | |
1408 | * 3- update RX shared data to indicate last write index. | |
1409 | * 4- send interrupt. | |
1410 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
1411 | * but the shared data changes does not reflect this; |
1412 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 1413 | */ |
74ba67ed BC |
1414 | |
1415 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1416 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 1417 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 1418 | iwl_rx_handle(priv); |
74ba67ed BC |
1419 | |
1420 | /* | |
1421 | * Enable periodic interrupt in 8 msec only if we received | |
1422 | * real RX interrupt (instead of just periodic int), to catch | |
1423 | * any dangling Rx interrupt. If it was just the periodic | |
1424 | * interrupt, there was no dangling Rx activity, and no need | |
1425 | * to extend the periodic interrupt; one-shot is enough. | |
1426 | */ | |
40cefda9 | 1427 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 1428 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
1429 | CSR_INT_PERIODIC_ENA); |
1430 | ||
ef850d7c | 1431 | priv->isr_stats.rx++; |
ef850d7c MA |
1432 | } |
1433 | ||
c72cd19f | 1434 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c MA |
1435 | if (inta & CSR_INT_BIT_FH_TX) { |
1436 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
c72cd19f | 1437 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
1438 | priv->isr_stats.tx++; |
1439 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 1440 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
1441 | priv->ucode_write_complete = 1; |
1442 | wake_up_interruptible(&priv->wait_command_queue); | |
1443 | } | |
1444 | ||
1445 | if (inta & ~handled) { | |
1446 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1447 | priv->isr_stats.unhandled++; | |
1448 | } | |
1449 | ||
40cefda9 | 1450 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1451 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1452 | inta & ~priv->inta_mask); |
ef850d7c MA |
1453 | } |
1454 | ||
ef850d7c MA |
1455 | /* Re-enable all interrupts */ |
1456 | /* only Re-enable if diabled by irq */ | |
1457 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1458 | iwl_enable_interrupts(priv); | |
ef850d7c MA |
1459 | } |
1460 | ||
872c8ddc WYG |
1461 | /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */ |
1462 | #define ACK_CNT_RATIO (50) | |
1463 | #define BA_TIMEOUT_CNT (5) | |
1464 | #define BA_TIMEOUT_MAX (16) | |
1465 | ||
1466 | /** | |
1467 | * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries. | |
1468 | * | |
1469 | * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding | |
1470 | * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal | |
1471 | * operation state. | |
1472 | */ | |
1473 | bool iwl_good_ack_health(struct iwl_priv *priv, | |
1474 | struct iwl_rx_packet *pkt) | |
1475 | { | |
1476 | bool rc = true; | |
1477 | int actual_ack_cnt_delta, expected_ack_cnt_delta; | |
1478 | int ba_timeout_delta; | |
1479 | ||
1480 | actual_ack_cnt_delta = | |
1481 | le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) - | |
f3aebeee | 1482 | le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt); |
872c8ddc WYG |
1483 | expected_ack_cnt_delta = |
1484 | le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) - | |
f3aebeee | 1485 | le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt); |
872c8ddc WYG |
1486 | ba_timeout_delta = |
1487 | le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) - | |
f3aebeee | 1488 | le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout); |
872c8ddc WYG |
1489 | if ((priv->_agn.agg_tids_count > 0) && |
1490 | (expected_ack_cnt_delta > 0) && | |
1491 | (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta) | |
1492 | < ACK_CNT_RATIO) && | |
1493 | (ba_timeout_delta > BA_TIMEOUT_CNT)) { | |
1494 | IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d," | |
1495 | " expected_ack_cnt = %d\n", | |
1496 | actual_ack_cnt_delta, expected_ack_cnt_delta); | |
1497 | ||
d73e4923 JB |
1498 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1499 | /* | |
1500 | * This is ifdef'ed on DEBUGFS because otherwise the | |
1501 | * statistics aren't available. If DEBUGFS is set but | |
1502 | * DEBUG is not, these will just compile out. | |
1503 | */ | |
872c8ddc | 1504 | IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n", |
f3aebeee | 1505 | priv->_agn.delta_statistics.tx.rx_detected_cnt); |
872c8ddc WYG |
1506 | IWL_DEBUG_RADIO(priv, |
1507 | "ack_or_ba_timeout_collision delta = %d\n", | |
f3aebeee | 1508 | priv->_agn.delta_statistics.tx. |
872c8ddc WYG |
1509 | ack_or_ba_timeout_collision); |
1510 | #endif | |
1511 | IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n", | |
1512 | ba_timeout_delta); | |
1513 | if (!actual_ack_cnt_delta && | |
1514 | (ba_timeout_delta >= BA_TIMEOUT_MAX)) | |
1515 | rc = false; | |
1516 | } | |
1517 | return rc; | |
1518 | } | |
1519 | ||
a83b9141 | 1520 | |
7d47618a EG |
1521 | /***************************************************************************** |
1522 | * | |
1523 | * sysfs attributes | |
1524 | * | |
1525 | *****************************************************************************/ | |
1526 | ||
1527 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1528 | ||
1529 | /* | |
1530 | * The following adds a new attribute to the sysfs representation | |
1531 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) | |
1532 | * used for controlling the debug level. | |
1533 | * | |
1534 | * See the level definitions in iwl for details. | |
1535 | * | |
1536 | * The debug_level being managed using sysfs below is a per device debug | |
1537 | * level that is used instead of the global debug level if it (the per | |
1538 | * device debug level) is set. | |
1539 | */ | |
1540 | static ssize_t show_debug_level(struct device *d, | |
1541 | struct device_attribute *attr, char *buf) | |
1542 | { | |
1543 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1544 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
1545 | } | |
1546 | static ssize_t store_debug_level(struct device *d, | |
1547 | struct device_attribute *attr, | |
1548 | const char *buf, size_t count) | |
1549 | { | |
1550 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1551 | unsigned long val; | |
1552 | int ret; | |
1553 | ||
1554 | ret = strict_strtoul(buf, 0, &val); | |
1555 | if (ret) | |
1556 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); | |
1557 | else { | |
1558 | priv->debug_level = val; | |
1559 | if (iwl_alloc_traffic_mem(priv)) | |
1560 | IWL_ERR(priv, | |
1561 | "Not enough memory to generate traffic log\n"); | |
1562 | } | |
1563 | return strnlen(buf, count); | |
1564 | } | |
1565 | ||
1566 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
1567 | show_debug_level, store_debug_level); | |
1568 | ||
1569 | ||
1570 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
1571 | ||
1572 | ||
1573 | static ssize_t show_temperature(struct device *d, | |
1574 | struct device_attribute *attr, char *buf) | |
1575 | { | |
1576 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1577 | ||
1578 | if (!iwl_is_alive(priv)) | |
1579 | return -EAGAIN; | |
1580 | ||
1581 | return sprintf(buf, "%d\n", priv->temperature); | |
1582 | } | |
1583 | ||
1584 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
1585 | ||
1586 | static ssize_t show_tx_power(struct device *d, | |
1587 | struct device_attribute *attr, char *buf) | |
1588 | { | |
1589 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1590 | ||
1591 | if (!iwl_is_ready_rf(priv)) | |
1592 | return sprintf(buf, "off\n"); | |
1593 | else | |
1594 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
1595 | } | |
1596 | ||
1597 | static ssize_t store_tx_power(struct device *d, | |
1598 | struct device_attribute *attr, | |
1599 | const char *buf, size_t count) | |
1600 | { | |
1601 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1602 | unsigned long val; | |
1603 | int ret; | |
1604 | ||
1605 | ret = strict_strtoul(buf, 10, &val); | |
1606 | if (ret) | |
1607 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); | |
1608 | else { | |
1609 | ret = iwl_set_tx_power(priv, val, false); | |
1610 | if (ret) | |
1611 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
1612 | ret); | |
1613 | else | |
1614 | ret = count; | |
1615 | } | |
1616 | return ret; | |
1617 | } | |
1618 | ||
1619 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
1620 | ||
1621 | static ssize_t show_rts_ht_protection(struct device *d, | |
1622 | struct device_attribute *attr, char *buf) | |
1623 | { | |
1624 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1625 | ||
1626 | return sprintf(buf, "%s\n", | |
1627 | priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self"); | |
1628 | } | |
1629 | ||
1630 | static ssize_t store_rts_ht_protection(struct device *d, | |
1631 | struct device_attribute *attr, | |
1632 | const char *buf, size_t count) | |
1633 | { | |
1634 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1635 | unsigned long val; | |
1636 | int ret; | |
1637 | ||
1638 | ret = strict_strtoul(buf, 10, &val); | |
1639 | if (ret) | |
1640 | IWL_INFO(priv, "Input is not in decimal form.\n"); | |
1641 | else { | |
1642 | if (!iwl_is_associated(priv)) | |
1643 | priv->cfg->use_rts_for_ht = val ? true : false; | |
1644 | else | |
1645 | IWL_ERR(priv, "Sta associated with AP - " | |
1646 | "Change protection mechanism is not allowed\n"); | |
1647 | ret = count; | |
1648 | } | |
1649 | return ret; | |
1650 | } | |
1651 | ||
1652 | static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO, | |
1653 | show_rts_ht_protection, store_rts_ht_protection); | |
1654 | ||
1655 | ||
1656 | static struct attribute *iwl_sysfs_entries[] = { | |
1657 | &dev_attr_temperature.attr, | |
1658 | &dev_attr_tx_power.attr, | |
1659 | &dev_attr_rts_ht_protection.attr, | |
1660 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1661 | &dev_attr_debug_level.attr, | |
1662 | #endif | |
1663 | NULL | |
1664 | }; | |
1665 | ||
1666 | static struct attribute_group iwl_attribute_group = { | |
1667 | .name = NULL, /* put in device directory */ | |
1668 | .attrs = iwl_sysfs_entries, | |
1669 | }; | |
1670 | ||
b481de9c ZY |
1671 | /****************************************************************************** |
1672 | * | |
1673 | * uCode download functions | |
1674 | * | |
1675 | ******************************************************************************/ | |
1676 | ||
5b9f8cd3 | 1677 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1678 | { |
98c92211 TW |
1679 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1680 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1681 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1682 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1683 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1684 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1685 | } |
1686 | ||
5b9f8cd3 | 1687 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1688 | { |
1689 | /* Remove all resets to allow NIC to operate */ | |
1690 | iwl_write32(priv, CSR_RESET, 0); | |
1691 | } | |
1692 | ||
dd7a2509 JB |
1693 | struct iwlagn_ucode_capabilities { |
1694 | u32 max_probe_length; | |
1695 | }; | |
edcdf8b2 | 1696 | |
b08dfd04 | 1697 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
dd7a2509 JB |
1698 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
1699 | struct iwlagn_ucode_capabilities *capa); | |
b08dfd04 JB |
1700 | |
1701 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) | |
1702 | { | |
1703 | const char *name_pre = priv->cfg->fw_name_pre; | |
1704 | ||
1705 | if (first) | |
1706 | priv->fw_index = priv->cfg->ucode_api_max; | |
1707 | else | |
1708 | priv->fw_index--; | |
1709 | ||
1710 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1711 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1712 | return -ENOENT; | |
1713 | } | |
1714 | ||
1715 | sprintf(priv->firmware_name, "%s%d%s", | |
1716 | name_pre, priv->fw_index, ".ucode"); | |
1717 | ||
1718 | IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n", | |
1719 | priv->firmware_name); | |
1720 | ||
1721 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
1722 | &priv->pci_dev->dev, GFP_KERNEL, priv, | |
1723 | iwl_ucode_callback); | |
1724 | } | |
1725 | ||
0e9a44dc JB |
1726 | struct iwlagn_firmware_pieces { |
1727 | const void *inst, *data, *init, *init_data, *boot; | |
1728 | size_t inst_size, data_size, init_size, init_data_size, boot_size; | |
1729 | ||
1730 | u32 build; | |
b2e640d4 JB |
1731 | |
1732 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1733 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
0e9a44dc JB |
1734 | }; |
1735 | ||
1736 | static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |
1737 | const struct firmware *ucode_raw, | |
1738 | struct iwlagn_firmware_pieces *pieces) | |
1739 | { | |
1740 | struct iwl_ucode_header *ucode = (void *)ucode_raw->data; | |
1741 | u32 api_ver, hdr_size; | |
1742 | const u8 *src; | |
1743 | ||
1744 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1745 | api_ver = IWL_UCODE_API(priv->ucode_ver); | |
1746 | ||
1747 | switch (api_ver) { | |
1748 | default: | |
1749 | /* | |
1750 | * 4965 doesn't revision the firmware file format | |
1751 | * along with the API version, it always uses v1 | |
1752 | * file format. | |
1753 | */ | |
1754 | if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) != | |
1755 | CSR_HW_REV_TYPE_4965) { | |
1756 | hdr_size = 28; | |
1757 | if (ucode_raw->size < hdr_size) { | |
1758 | IWL_ERR(priv, "File size too small!\n"); | |
1759 | return -EINVAL; | |
1760 | } | |
1761 | pieces->build = le32_to_cpu(ucode->u.v2.build); | |
1762 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | |
1763 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | |
1764 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | |
1765 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | |
1766 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | |
1767 | src = ucode->u.v2.data; | |
1768 | break; | |
1769 | } | |
1770 | /* fall through for 4965 */ | |
1771 | case 0: | |
1772 | case 1: | |
1773 | case 2: | |
1774 | hdr_size = 24; | |
1775 | if (ucode_raw->size < hdr_size) { | |
1776 | IWL_ERR(priv, "File size too small!\n"); | |
1777 | return -EINVAL; | |
1778 | } | |
1779 | pieces->build = 0; | |
1780 | pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size); | |
1781 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); | |
1782 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); | |
1783 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); | |
1784 | pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size); | |
1785 | src = ucode->u.v1.data; | |
1786 | break; | |
1787 | } | |
1788 | ||
1789 | /* Verify size of file vs. image size info in file's header */ | |
1790 | if (ucode_raw->size != hdr_size + pieces->inst_size + | |
1791 | pieces->data_size + pieces->init_size + | |
1792 | pieces->init_data_size + pieces->boot_size) { | |
1793 | ||
1794 | IWL_ERR(priv, | |
1795 | "uCode file size %d does not match expected size\n", | |
1796 | (int)ucode_raw->size); | |
1797 | return -EINVAL; | |
1798 | } | |
1799 | ||
1800 | pieces->inst = src; | |
1801 | src += pieces->inst_size; | |
1802 | pieces->data = src; | |
1803 | src += pieces->data_size; | |
1804 | pieces->init = src; | |
1805 | src += pieces->init_size; | |
1806 | pieces->init_data = src; | |
1807 | src += pieces->init_data_size; | |
1808 | pieces->boot = src; | |
1809 | src += pieces->boot_size; | |
1810 | ||
1811 | return 0; | |
1812 | } | |
1813 | ||
dd7a2509 JB |
1814 | static int iwlagn_wanted_ucode_alternative = 1; |
1815 | ||
1816 | static int iwlagn_load_firmware(struct iwl_priv *priv, | |
1817 | const struct firmware *ucode_raw, | |
1818 | struct iwlagn_firmware_pieces *pieces, | |
1819 | struct iwlagn_ucode_capabilities *capa) | |
1820 | { | |
1821 | struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data; | |
1822 | struct iwl_ucode_tlv *tlv; | |
1823 | size_t len = ucode_raw->size; | |
1824 | const u8 *data; | |
1825 | int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp; | |
1826 | u64 alternatives; | |
ad8d8333 WYG |
1827 | u32 tlv_len; |
1828 | enum iwl_ucode_tlv_type tlv_type; | |
1829 | const u8 *tlv_data; | |
1830 | int ret = 0; | |
dd7a2509 | 1831 | |
ad8d8333 WYG |
1832 | if (len < sizeof(*ucode)) { |
1833 | IWL_ERR(priv, "uCode has invalid length: %zd\n", len); | |
dd7a2509 | 1834 | return -EINVAL; |
ad8d8333 | 1835 | } |
dd7a2509 | 1836 | |
ad8d8333 WYG |
1837 | if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) { |
1838 | IWL_ERR(priv, "invalid uCode magic: 0X%x\n", | |
1839 | le32_to_cpu(ucode->magic)); | |
dd7a2509 | 1840 | return -EINVAL; |
ad8d8333 | 1841 | } |
dd7a2509 JB |
1842 | |
1843 | /* | |
1844 | * Check which alternatives are present, and "downgrade" | |
1845 | * when the chosen alternative is not present, warning | |
1846 | * the user when that happens. Some files may not have | |
1847 | * any alternatives, so don't warn in that case. | |
1848 | */ | |
1849 | alternatives = le64_to_cpu(ucode->alternatives); | |
1850 | tmp = wanted_alternative; | |
1851 | if (wanted_alternative > 63) | |
1852 | wanted_alternative = 63; | |
1853 | while (wanted_alternative && !(alternatives & BIT(wanted_alternative))) | |
1854 | wanted_alternative--; | |
1855 | if (wanted_alternative && wanted_alternative != tmp) | |
1856 | IWL_WARN(priv, | |
1857 | "uCode alternative %d not available, choosing %d\n", | |
1858 | tmp, wanted_alternative); | |
1859 | ||
1860 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1861 | pieces->build = le32_to_cpu(ucode->build); | |
1862 | data = ucode->data; | |
1863 | ||
1864 | len -= sizeof(*ucode); | |
1865 | ||
ad8d8333 | 1866 | while (len >= sizeof(*tlv) && !ret) { |
dd7a2509 | 1867 | u16 tlv_alt; |
ad8d8333 | 1868 | u32 fixed_tlv_size = 4; |
dd7a2509 JB |
1869 | |
1870 | len -= sizeof(*tlv); | |
1871 | tlv = (void *)data; | |
1872 | ||
1873 | tlv_len = le32_to_cpu(tlv->length); | |
1874 | tlv_type = le16_to_cpu(tlv->type); | |
1875 | tlv_alt = le16_to_cpu(tlv->alternative); | |
1876 | tlv_data = tlv->data; | |
1877 | ||
ad8d8333 WYG |
1878 | if (len < tlv_len) { |
1879 | IWL_ERR(priv, "invalid TLV len: %zd/%u\n", | |
1880 | len, tlv_len); | |
dd7a2509 | 1881 | return -EINVAL; |
ad8d8333 | 1882 | } |
dd7a2509 JB |
1883 | len -= ALIGN(tlv_len, 4); |
1884 | data += sizeof(*tlv) + ALIGN(tlv_len, 4); | |
1885 | ||
1886 | /* | |
1887 | * Alternative 0 is always valid. | |
1888 | * | |
1889 | * Skip alternative TLVs that are not selected. | |
1890 | */ | |
1891 | if (tlv_alt != 0 && tlv_alt != wanted_alternative) | |
1892 | continue; | |
1893 | ||
1894 | switch (tlv_type) { | |
1895 | case IWL_UCODE_TLV_INST: | |
1896 | pieces->inst = tlv_data; | |
1897 | pieces->inst_size = tlv_len; | |
1898 | break; | |
1899 | case IWL_UCODE_TLV_DATA: | |
1900 | pieces->data = tlv_data; | |
1901 | pieces->data_size = tlv_len; | |
1902 | break; | |
1903 | case IWL_UCODE_TLV_INIT: | |
1904 | pieces->init = tlv_data; | |
1905 | pieces->init_size = tlv_len; | |
1906 | break; | |
1907 | case IWL_UCODE_TLV_INIT_DATA: | |
1908 | pieces->init_data = tlv_data; | |
1909 | pieces->init_data_size = tlv_len; | |
1910 | break; | |
1911 | case IWL_UCODE_TLV_BOOT: | |
1912 | pieces->boot = tlv_data; | |
1913 | pieces->boot_size = tlv_len; | |
1914 | break; | |
1915 | case IWL_UCODE_TLV_PROBE_MAX_LEN: | |
ad8d8333 WYG |
1916 | if (tlv_len != fixed_tlv_size) |
1917 | ret = -EINVAL; | |
1918 | else | |
1919 | capa->max_probe_length = | |
1920 | le32_to_cpup((__le32 *)tlv_data); | |
dd7a2509 | 1921 | break; |
b2e640d4 | 1922 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: |
ad8d8333 WYG |
1923 | if (tlv_len != fixed_tlv_size) |
1924 | ret = -EINVAL; | |
1925 | else | |
1926 | pieces->init_evtlog_ptr = | |
1927 | le32_to_cpup((__le32 *)tlv_data); | |
b2e640d4 JB |
1928 | break; |
1929 | case IWL_UCODE_TLV_INIT_EVTLOG_SIZE: | |
ad8d8333 WYG |
1930 | if (tlv_len != fixed_tlv_size) |
1931 | ret = -EINVAL; | |
1932 | else | |
1933 | pieces->init_evtlog_size = | |
1934 | le32_to_cpup((__le32 *)tlv_data); | |
b2e640d4 JB |
1935 | break; |
1936 | case IWL_UCODE_TLV_INIT_ERRLOG_PTR: | |
ad8d8333 WYG |
1937 | if (tlv_len != fixed_tlv_size) |
1938 | ret = -EINVAL; | |
1939 | else | |
1940 | pieces->init_errlog_ptr = | |
1941 | le32_to_cpup((__le32 *)tlv_data); | |
b2e640d4 JB |
1942 | break; |
1943 | case IWL_UCODE_TLV_RUNT_EVTLOG_PTR: | |
ad8d8333 WYG |
1944 | if (tlv_len != fixed_tlv_size) |
1945 | ret = -EINVAL; | |
1946 | else | |
1947 | pieces->inst_evtlog_ptr = | |
1948 | le32_to_cpup((__le32 *)tlv_data); | |
b2e640d4 JB |
1949 | break; |
1950 | case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE: | |
ad8d8333 WYG |
1951 | if (tlv_len != fixed_tlv_size) |
1952 | ret = -EINVAL; | |
1953 | else | |
1954 | pieces->inst_evtlog_size = | |
1955 | le32_to_cpup((__le32 *)tlv_data); | |
b2e640d4 JB |
1956 | break; |
1957 | case IWL_UCODE_TLV_RUNT_ERRLOG_PTR: | |
ad8d8333 WYG |
1958 | if (tlv_len != fixed_tlv_size) |
1959 | ret = -EINVAL; | |
1960 | else | |
1961 | pieces->inst_errlog_ptr = | |
1962 | le32_to_cpup((__le32 *)tlv_data); | |
b2e640d4 | 1963 | break; |
c8312fac WYG |
1964 | case IWL_UCODE_TLV_ENHANCE_SENS_TBL: |
1965 | if (tlv_len) | |
1966 | ret = -EINVAL; | |
1967 | else | |
1968 | priv->enhance_sensitivity_table = true; | |
1969 | break; | |
dd7a2509 | 1970 | default: |
ad8d8333 | 1971 | IWL_WARN(priv, "unknown TLV: %d\n", tlv_type); |
dd7a2509 JB |
1972 | break; |
1973 | } | |
1974 | } | |
1975 | ||
ad8d8333 WYG |
1976 | if (len) { |
1977 | IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len); | |
1978 | iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len); | |
1979 | ret = -EINVAL; | |
1980 | } else if (ret) { | |
1981 | IWL_ERR(priv, "TLV %d has invalid size: %u\n", | |
1982 | tlv_type, tlv_len); | |
1983 | iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)tlv_data, tlv_len); | |
1984 | } | |
dd7a2509 | 1985 | |
ad8d8333 | 1986 | return ret; |
dd7a2509 JB |
1987 | } |
1988 | ||
b481de9c | 1989 | /** |
b08dfd04 | 1990 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 1991 | * |
b08dfd04 JB |
1992 | * If loaded successfully, copies the firmware into buffers |
1993 | * for the card to fetch (via DMA). | |
b481de9c | 1994 | */ |
b08dfd04 | 1995 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 1996 | { |
b08dfd04 | 1997 | struct iwl_priv *priv = context; |
cc0f555d | 1998 | struct iwl_ucode_header *ucode; |
0e9a44dc JB |
1999 | int err; |
2000 | struct iwlagn_firmware_pieces pieces; | |
a0987a8d RC |
2001 | const unsigned int api_max = priv->cfg->ucode_api_max; |
2002 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
0e9a44dc | 2003 | u32 api_ver; |
3e4de761 | 2004 | char buildstr[25]; |
0e9a44dc | 2005 | u32 build; |
dd7a2509 JB |
2006 | struct iwlagn_ucode_capabilities ucode_capa = { |
2007 | .max_probe_length = 200, | |
2008 | }; | |
0e9a44dc JB |
2009 | |
2010 | memset(&pieces, 0, sizeof(pieces)); | |
b481de9c | 2011 | |
b08dfd04 JB |
2012 | if (!ucode_raw) { |
2013 | IWL_ERR(priv, "request for firmware file '%s' failed.\n", | |
2014 | priv->firmware_name); | |
2015 | goto try_again; | |
b481de9c ZY |
2016 | } |
2017 | ||
b08dfd04 JB |
2018 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
2019 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 2020 | |
22adba2a JB |
2021 | /* Make sure that we got at least the API version number */ |
2022 | if (ucode_raw->size < 4) { | |
15b1687c | 2023 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 2024 | goto try_again; |
b481de9c ZY |
2025 | } |
2026 | ||
2027 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 2028 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 2029 | |
0e9a44dc JB |
2030 | if (ucode->ver) |
2031 | err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces); | |
2032 | else | |
dd7a2509 JB |
2033 | err = iwlagn_load_firmware(priv, ucode_raw, &pieces, |
2034 | &ucode_capa); | |
22adba2a | 2035 | |
0e9a44dc JB |
2036 | if (err) |
2037 | goto try_again; | |
b481de9c | 2038 | |
a0987a8d | 2039 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
0e9a44dc | 2040 | build = pieces.build; |
a0987a8d | 2041 | |
0e9a44dc JB |
2042 | /* |
2043 | * api_ver should match the api version forming part of the | |
2044 | * firmware filename ... but we don't check for that and only rely | |
2045 | * on the API version read from firmware header from here on forward | |
2046 | */ | |
a0987a8d | 2047 | if (api_ver < api_min || api_ver > api_max) { |
15b1687c | 2048 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
2049 | "Driver supports v%u, firmware is v%u.\n", |
2050 | api_max, api_ver); | |
b08dfd04 | 2051 | goto try_again; |
a0987a8d | 2052 | } |
b08dfd04 | 2053 | |
a0987a8d | 2054 | if (api_ver != api_max) |
978785a3 | 2055 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
2056 | "got v%u. New firmware can be obtained " |
2057 | "from http://www.intellinuxwireless.org.\n", | |
2058 | api_max, api_ver); | |
2059 | ||
3e4de761 JB |
2060 | if (build) |
2061 | sprintf(buildstr, " build %u", build); | |
2062 | else | |
2063 | buildstr[0] = '\0'; | |
2064 | ||
2065 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n", | |
2066 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2067 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2068 | IWL_UCODE_API(priv->ucode_ver), | |
2069 | IWL_UCODE_SERIAL(priv->ucode_ver), | |
2070 | buildstr); | |
a0987a8d | 2071 | |
5ebeb5a6 RC |
2072 | snprintf(priv->hw->wiphy->fw_version, |
2073 | sizeof(priv->hw->wiphy->fw_version), | |
3e4de761 | 2074 | "%u.%u.%u.%u%s", |
5ebeb5a6 RC |
2075 | IWL_UCODE_MAJOR(priv->ucode_ver), |
2076 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2077 | IWL_UCODE_API(priv->ucode_ver), | |
3e4de761 JB |
2078 | IWL_UCODE_SERIAL(priv->ucode_ver), |
2079 | buildstr); | |
b481de9c | 2080 | |
b08dfd04 JB |
2081 | /* |
2082 | * For any of the failures below (before allocating pci memory) | |
2083 | * we will try to load a version with a smaller API -- maybe the | |
2084 | * user just got a corrupted version of the latest API. | |
2085 | */ | |
2086 | ||
0e9a44dc JB |
2087 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
2088 | priv->ucode_ver); | |
2089 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n", | |
2090 | pieces.inst_size); | |
2091 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n", | |
2092 | pieces.data_size); | |
2093 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n", | |
2094 | pieces.init_size); | |
2095 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", | |
2096 | pieces.init_data_size); | |
2097 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n", | |
2098 | pieces.boot_size); | |
b481de9c ZY |
2099 | |
2100 | /* Verify that uCode images will fit in card's SRAM */ | |
0e9a44dc JB |
2101 | if (pieces.inst_size > priv->hw_params.max_inst_size) { |
2102 | IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n", | |
2103 | pieces.inst_size); | |
b08dfd04 | 2104 | goto try_again; |
b481de9c ZY |
2105 | } |
2106 | ||
0e9a44dc JB |
2107 | if (pieces.data_size > priv->hw_params.max_data_size) { |
2108 | IWL_ERR(priv, "uCode data len %Zd too large to fit in\n", | |
2109 | pieces.data_size); | |
b08dfd04 | 2110 | goto try_again; |
b481de9c | 2111 | } |
0e9a44dc JB |
2112 | |
2113 | if (pieces.init_size > priv->hw_params.max_inst_size) { | |
2114 | IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n", | |
2115 | pieces.init_size); | |
b08dfd04 | 2116 | goto try_again; |
b481de9c | 2117 | } |
0e9a44dc JB |
2118 | |
2119 | if (pieces.init_data_size > priv->hw_params.max_data_size) { | |
2120 | IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n", | |
2121 | pieces.init_data_size); | |
b08dfd04 | 2122 | goto try_again; |
b481de9c | 2123 | } |
0e9a44dc JB |
2124 | |
2125 | if (pieces.boot_size > priv->hw_params.max_bsm_size) { | |
2126 | IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n", | |
2127 | pieces.boot_size); | |
b08dfd04 | 2128 | goto try_again; |
b481de9c ZY |
2129 | } |
2130 | ||
2131 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2132 | ||
2133 | /* Runtime instructions and 2 copies of data: | |
2134 | * 1) unmodified from disk | |
2135 | * 2) backup cache for save/restore during power-downs */ | |
0e9a44dc | 2136 | priv->ucode_code.len = pieces.inst_size; |
98c92211 | 2137 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c | 2138 | |
0e9a44dc | 2139 | priv->ucode_data.len = pieces.data_size; |
98c92211 | 2140 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c | 2141 | |
0e9a44dc | 2142 | priv->ucode_data_backup.len = pieces.data_size; |
98c92211 | 2143 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2144 | |
1f304e4e ZY |
2145 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2146 | !priv->ucode_data_backup.v_addr) | |
2147 | goto err_pci_alloc; | |
2148 | ||
b481de9c | 2149 | /* Initialization instructions and data */ |
0e9a44dc JB |
2150 | if (pieces.init_size && pieces.init_data_size) { |
2151 | priv->ucode_init.len = pieces.init_size; | |
98c92211 | 2152 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 | 2153 | |
0e9a44dc | 2154 | priv->ucode_init_data.len = pieces.init_data_size; |
98c92211 | 2155 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2156 | |
2157 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2158 | goto err_pci_alloc; | |
2159 | } | |
b481de9c ZY |
2160 | |
2161 | /* Bootstrap (instructions only, no data) */ | |
0e9a44dc JB |
2162 | if (pieces.boot_size) { |
2163 | priv->ucode_boot.len = pieces.boot_size; | |
98c92211 | 2164 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2165 | |
90e759d1 TW |
2166 | if (!priv->ucode_boot.v_addr) |
2167 | goto err_pci_alloc; | |
2168 | } | |
b481de9c | 2169 | |
b2e640d4 JB |
2170 | /* Now that we can no longer fail, copy information */ |
2171 | ||
2172 | /* | |
2173 | * The (size - 16) / 12 formula is based on the information recorded | |
2174 | * for each event, which is of mode 1 (including timestamp) for all | |
2175 | * new microcodes that include this information. | |
2176 | */ | |
2177 | priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr; | |
2178 | if (pieces.init_evtlog_size) | |
2179 | priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12; | |
2180 | else | |
2181 | priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size; | |
2182 | priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr; | |
2183 | priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr; | |
2184 | if (pieces.inst_evtlog_size) | |
2185 | priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12; | |
2186 | else | |
2187 | priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size; | |
2188 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; | |
2189 | ||
b481de9c ZY |
2190 | /* Copy images into buffers for card's bus-master reads ... */ |
2191 | ||
2192 | /* Runtime instructions (first block of data in file) */ | |
0e9a44dc JB |
2193 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", |
2194 | pieces.inst_size); | |
2195 | memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size); | |
cc0f555d | 2196 | |
e1623446 | 2197 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2198 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2199 | ||
0e9a44dc JB |
2200 | /* |
2201 | * Runtime data | |
2202 | * NOTE: Copy into backup buffer will be done in iwl_up() | |
2203 | */ | |
2204 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", | |
2205 | pieces.data_size); | |
2206 | memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size); | |
2207 | memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size); | |
2208 | ||
2209 | /* Initialization instructions */ | |
2210 | if (pieces.init_size) { | |
e1623446 | 2211 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
0e9a44dc JB |
2212 | pieces.init_size); |
2213 | memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size); | |
b481de9c ZY |
2214 | } |
2215 | ||
0e9a44dc JB |
2216 | /* Initialization data */ |
2217 | if (pieces.init_data_size) { | |
e1623446 | 2218 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
0e9a44dc JB |
2219 | pieces.init_data_size); |
2220 | memcpy(priv->ucode_init_data.v_addr, pieces.init_data, | |
2221 | pieces.init_data_size); | |
b481de9c ZY |
2222 | } |
2223 | ||
0e9a44dc JB |
2224 | /* Bootstrap instructions */ |
2225 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", | |
2226 | pieces.boot_size); | |
2227 | memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size); | |
b481de9c | 2228 | |
b08dfd04 JB |
2229 | /************************************************** |
2230 | * This is still part of probe() in a sense... | |
2231 | * | |
2232 | * 9. Setup and register with mac80211 and debugfs | |
2233 | **************************************************/ | |
dd7a2509 | 2234 | err = iwl_mac_setup_register(priv, &ucode_capa); |
b08dfd04 JB |
2235 | if (err) |
2236 | goto out_unbind; | |
2237 | ||
2238 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
2239 | if (err) | |
2240 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
2241 | ||
7d47618a EG |
2242 | err = sysfs_create_group(&priv->pci_dev->dev.kobj, |
2243 | &iwl_attribute_group); | |
2244 | if (err) { | |
2245 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); | |
2246 | goto out_unbind; | |
2247 | } | |
2248 | ||
b481de9c ZY |
2249 | /* We have our copies now, allow OS release its copies */ |
2250 | release_firmware(ucode_raw); | |
a15707d8 | 2251 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 JB |
2252 | return; |
2253 | ||
2254 | try_again: | |
2255 | /* try next, if any */ | |
2256 | if (iwl_request_firmware(priv, false)) | |
2257 | goto out_unbind; | |
2258 | release_firmware(ucode_raw); | |
2259 | return; | |
b481de9c ZY |
2260 | |
2261 | err_pci_alloc: | |
15b1687c | 2262 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
5b9f8cd3 | 2263 | iwl_dealloc_ucode_pci(priv); |
b08dfd04 | 2264 | out_unbind: |
a15707d8 | 2265 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 | 2266 | device_release_driver(&priv->pci_dev->dev); |
b481de9c | 2267 | release_firmware(ucode_raw); |
b481de9c ZY |
2268 | } |
2269 | ||
b7a79404 RC |
2270 | static const char *desc_lookup_text[] = { |
2271 | "OK", | |
2272 | "FAIL", | |
2273 | "BAD_PARAM", | |
2274 | "BAD_CHECKSUM", | |
2275 | "NMI_INTERRUPT_WDG", | |
2276 | "SYSASSERT", | |
2277 | "FATAL_ERROR", | |
2278 | "BAD_COMMAND", | |
2279 | "HW_ERROR_TUNE_LOCK", | |
2280 | "HW_ERROR_TEMPERATURE", | |
2281 | "ILLEGAL_CHAN_FREQ", | |
2282 | "VCC_NOT_STABLE", | |
2283 | "FH_ERROR", | |
2284 | "NMI_INTERRUPT_HOST", | |
2285 | "NMI_INTERRUPT_ACTION_PT", | |
2286 | "NMI_INTERRUPT_UNKNOWN", | |
2287 | "UCODE_VERSION_MISMATCH", | |
2288 | "HW_ERROR_ABS_LOCK", | |
2289 | "HW_ERROR_CAL_LOCK_FAIL", | |
2290 | "NMI_INTERRUPT_INST_ACTION_PT", | |
2291 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
2292 | "NMI_TRM_HW_ER", | |
2293 | "NMI_INTERRUPT_TRM", | |
2294 | "NMI_INTERRUPT_BREAK_POINT" | |
2295 | "DEBUG_0", | |
2296 | "DEBUG_1", | |
2297 | "DEBUG_2", | |
2298 | "DEBUG_3", | |
b7a79404 RC |
2299 | }; |
2300 | ||
4b58645c JS |
2301 | static struct { char *name; u8 num; } advanced_lookup[] = { |
2302 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
2303 | { "SYSASSERT", 0x35 }, | |
2304 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
2305 | { "BAD_COMMAND", 0x38 }, | |
2306 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
2307 | { "FATAL_ERROR", 0x3D }, | |
2308 | { "NMI_TRM_HW_ERR", 0x46 }, | |
2309 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
2310 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
2311 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
2312 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
2313 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
2314 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
2315 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
2316 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
2317 | { "ADVANCED_SYSASSERT", 0 }, | |
2318 | }; | |
2319 | ||
2320 | static const char *desc_lookup(u32 num) | |
b7a79404 | 2321 | { |
4b58645c JS |
2322 | int i; |
2323 | int max = ARRAY_SIZE(desc_lookup_text); | |
b7a79404 | 2324 | |
4b58645c JS |
2325 | if (num < max) |
2326 | return desc_lookup_text[num]; | |
b7a79404 | 2327 | |
4b58645c JS |
2328 | max = ARRAY_SIZE(advanced_lookup) - 1; |
2329 | for (i = 0; i < max; i++) { | |
2330 | if (advanced_lookup[i].num == num) | |
2331 | break;; | |
2332 | } | |
2333 | return advanced_lookup[i].name; | |
b7a79404 RC |
2334 | } |
2335 | ||
2336 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
2337 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
2338 | ||
2339 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
2340 | { | |
2341 | u32 data2, line; | |
2342 | u32 desc, time, count, base, data1; | |
2343 | u32 blink1, blink2, ilink1, ilink2; | |
461ef382 | 2344 | u32 pc, hcmd; |
b7a79404 | 2345 | |
b2e640d4 | 2346 | if (priv->ucode_type == UCODE_INIT) { |
b7a79404 | 2347 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); |
b2e640d4 JB |
2348 | if (!base) |
2349 | base = priv->_agn.init_errlog_ptr; | |
2350 | } else { | |
b7a79404 | 2351 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); |
b2e640d4 JB |
2352 | if (!base) |
2353 | base = priv->_agn.inst_errlog_ptr; | |
2354 | } | |
b7a79404 RC |
2355 | |
2356 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2357 | IWL_ERR(priv, |
2358 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
2359 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
b7a79404 RC |
2360 | return; |
2361 | } | |
2362 | ||
2363 | count = iwl_read_targ_mem(priv, base); | |
2364 | ||
2365 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
2366 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
2367 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
2368 | priv->status, count); | |
2369 | } | |
2370 | ||
2371 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
461ef382 | 2372 | pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32)); |
b7a79404 RC |
2373 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); |
2374 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
2375 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
2376 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
2377 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
2378 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
2379 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
2380 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
461ef382 | 2381 | hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32)); |
b7a79404 | 2382 | |
be1a71a1 JB |
2383 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
2384 | blink1, blink2, ilink1, ilink2); | |
2385 | ||
87563715 | 2386 | IWL_ERR(priv, "Desc Time " |
b7a79404 | 2387 | "data1 data2 line\n"); |
87563715 | 2388 | IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", |
b7a79404 | 2389 | desc_lookup(desc), desc, time, data1, data2, line); |
461ef382 WYG |
2390 | IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n"); |
2391 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", | |
2392 | pc, blink1, blink2, ilink1, ilink2, hcmd); | |
b7a79404 RC |
2393 | } |
2394 | ||
2395 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
2396 | ||
2397 | /** | |
2398 | * iwl_print_event_log - Dump error event log to syslog | |
2399 | * | |
2400 | */ | |
b03d7d0f WYG |
2401 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
2402 | u32 num_events, u32 mode, | |
2403 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
2404 | { |
2405 | u32 i; | |
2406 | u32 base; /* SRAM byte address of event log header */ | |
2407 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
2408 | u32 ptr; /* SRAM byte address of log data */ | |
2409 | u32 ev, time, data; /* event log data */ | |
e5854471 | 2410 | unsigned long reg_flags; |
b7a79404 RC |
2411 | |
2412 | if (num_events == 0) | |
b03d7d0f | 2413 | return pos; |
b2e640d4 JB |
2414 | |
2415 | if (priv->ucode_type == UCODE_INIT) { | |
b7a79404 | 2416 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
b2e640d4 JB |
2417 | if (!base) |
2418 | base = priv->_agn.init_evtlog_ptr; | |
2419 | } else { | |
b7a79404 | 2420 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
b2e640d4 JB |
2421 | if (!base) |
2422 | base = priv->_agn.inst_evtlog_ptr; | |
2423 | } | |
b7a79404 RC |
2424 | |
2425 | if (mode == 0) | |
2426 | event_size = 2 * sizeof(u32); | |
2427 | else | |
2428 | event_size = 3 * sizeof(u32); | |
2429 | ||
2430 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
2431 | ||
e5854471 BC |
2432 | /* Make sure device is powered up for SRAM reads */ |
2433 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
2434 | iwl_grab_nic_access(priv); | |
2435 | ||
2436 | /* Set starting address; reads will auto-increment */ | |
2437 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
2438 | rmb(); | |
2439 | ||
b7a79404 RC |
2440 | /* "time" is actually "data" for mode 0 (no timestamp). |
2441 | * place event id # at far right for easier visual parsing. */ | |
2442 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
2443 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
2444 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
2445 | if (mode == 0) { |
2446 | /* data, ev */ | |
b03d7d0f WYG |
2447 | if (bufsz) { |
2448 | pos += scnprintf(*buf + pos, bufsz - pos, | |
2449 | "EVT_LOG:0x%08x:%04u\n", | |
2450 | time, ev); | |
2451 | } else { | |
2452 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
2453 | time, ev); | |
2454 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
2455 | time, ev); | |
2456 | } | |
b7a79404 | 2457 | } else { |
e5854471 | 2458 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
2459 | if (bufsz) { |
2460 | pos += scnprintf(*buf + pos, bufsz - pos, | |
2461 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
2462 | time, data, ev); | |
2463 | } else { | |
2464 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 2465 | time, data, ev); |
b03d7d0f WYG |
2466 | trace_iwlwifi_dev_ucode_event(priv, time, |
2467 | data, ev); | |
2468 | } | |
b7a79404 RC |
2469 | } |
2470 | } | |
e5854471 BC |
2471 | |
2472 | /* Allow device to power down */ | |
2473 | iwl_release_nic_access(priv); | |
2474 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 2475 | return pos; |
b7a79404 RC |
2476 | } |
2477 | ||
c341ddb2 WYG |
2478 | /** |
2479 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
2480 | */ | |
b03d7d0f WYG |
2481 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
2482 | u32 num_wraps, u32 next_entry, | |
2483 | u32 size, u32 mode, | |
2484 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
2485 | { |
2486 | /* | |
2487 | * display the newest DEFAULT_LOG_ENTRIES entries | |
2488 | * i.e the entries just before the next ont that uCode would fill. | |
2489 | */ | |
2490 | if (num_wraps) { | |
2491 | if (next_entry < size) { | |
b03d7d0f WYG |
2492 | pos = iwl_print_event_log(priv, |
2493 | capacity - (size - next_entry), | |
2494 | size - next_entry, mode, | |
2495 | pos, buf, bufsz); | |
2496 | pos = iwl_print_event_log(priv, 0, | |
2497 | next_entry, mode, | |
2498 | pos, buf, bufsz); | |
c341ddb2 | 2499 | } else |
b03d7d0f WYG |
2500 | pos = iwl_print_event_log(priv, next_entry - size, |
2501 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 2502 | } else { |
b03d7d0f WYG |
2503 | if (next_entry < size) { |
2504 | pos = iwl_print_event_log(priv, 0, next_entry, | |
2505 | mode, pos, buf, bufsz); | |
2506 | } else { | |
2507 | pos = iwl_print_event_log(priv, next_entry - size, | |
2508 | size, mode, pos, buf, bufsz); | |
2509 | } | |
c341ddb2 | 2510 | } |
b03d7d0f | 2511 | return pos; |
c341ddb2 WYG |
2512 | } |
2513 | ||
c341ddb2 WYG |
2514 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
2515 | ||
b03d7d0f WYG |
2516 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
2517 | char **buf, bool display) | |
b7a79404 RC |
2518 | { |
2519 | u32 base; /* SRAM byte address of event log header */ | |
2520 | u32 capacity; /* event log capacity in # entries */ | |
2521 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
2522 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
2523 | u32 next_entry; /* index of next entry to be written by uCode */ | |
2524 | u32 size; /* # entries that we'll print */ | |
b2e640d4 | 2525 | u32 logsize; |
b03d7d0f WYG |
2526 | int pos = 0; |
2527 | size_t bufsz = 0; | |
b7a79404 | 2528 | |
b2e640d4 | 2529 | if (priv->ucode_type == UCODE_INIT) { |
b7a79404 | 2530 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
b2e640d4 JB |
2531 | logsize = priv->_agn.init_evtlog_size; |
2532 | if (!base) | |
2533 | base = priv->_agn.init_evtlog_ptr; | |
2534 | } else { | |
b7a79404 | 2535 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
b2e640d4 JB |
2536 | logsize = priv->_agn.inst_evtlog_size; |
2537 | if (!base) | |
2538 | base = priv->_agn.inst_evtlog_ptr; | |
2539 | } | |
b7a79404 RC |
2540 | |
2541 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2542 | IWL_ERR(priv, |
2543 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
2544 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
937c397e | 2545 | return -EINVAL; |
b7a79404 RC |
2546 | } |
2547 | ||
2548 | /* event log header */ | |
2549 | capacity = iwl_read_targ_mem(priv, base); | |
2550 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
2551 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
2552 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
2553 | ||
b2e640d4 | 2554 | if (capacity > logsize) { |
84c40692 | 2555 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
b2e640d4 JB |
2556 | capacity, logsize); |
2557 | capacity = logsize; | |
84c40692 BC |
2558 | } |
2559 | ||
b2e640d4 | 2560 | if (next_entry > logsize) { |
84c40692 | 2561 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
b2e640d4 JB |
2562 | next_entry, logsize); |
2563 | next_entry = logsize; | |
84c40692 BC |
2564 | } |
2565 | ||
b7a79404 RC |
2566 | size = num_wraps ? capacity : next_entry; |
2567 | ||
2568 | /* bail out if nothing in log */ | |
2569 | if (size == 0) { | |
2570 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 2571 | return pos; |
b7a79404 RC |
2572 | } |
2573 | ||
c341ddb2 | 2574 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 2575 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
2576 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
2577 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2578 | #else | |
2579 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
2580 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2581 | #endif | |
2582 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
2583 | size); | |
b7a79404 | 2584 | |
c341ddb2 | 2585 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
2586 | if (display) { |
2587 | if (full_log) | |
2588 | bufsz = capacity * 48; | |
2589 | else | |
2590 | bufsz = size * 48; | |
2591 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
2592 | if (!*buf) | |
937c397e | 2593 | return -ENOMEM; |
b03d7d0f | 2594 | } |
c341ddb2 WYG |
2595 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
2596 | /* | |
2597 | * if uCode has wrapped back to top of log, | |
2598 | * start at the oldest entry, | |
2599 | * i.e the next one that uCode would fill. | |
2600 | */ | |
2601 | if (num_wraps) | |
b03d7d0f WYG |
2602 | pos = iwl_print_event_log(priv, next_entry, |
2603 | capacity - next_entry, mode, | |
2604 | pos, buf, bufsz); | |
c341ddb2 | 2605 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
2606 | pos = iwl_print_event_log(priv, 0, |
2607 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 2608 | } else |
b03d7d0f WYG |
2609 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2610 | next_entry, size, mode, | |
2611 | pos, buf, bufsz); | |
c341ddb2 | 2612 | #else |
b03d7d0f WYG |
2613 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2614 | next_entry, size, mode, | |
2615 | pos, buf, bufsz); | |
b7a79404 | 2616 | #endif |
b03d7d0f | 2617 | return pos; |
c341ddb2 | 2618 | } |
b7a79404 | 2619 | |
b481de9c | 2620 | /** |
4a4a9e81 | 2621 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2622 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 2623 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 2624 | */ |
4a4a9e81 | 2625 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 2626 | { |
57aab75a | 2627 | int ret = 0; |
b481de9c | 2628 | |
e1623446 | 2629 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2630 | |
2631 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2632 | /* We had an error bringing up the hardware, so take it | |
2633 | * all the way back down so we can try again */ | |
e1623446 | 2634 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2635 | goto restart; |
2636 | } | |
2637 | ||
2638 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2639 | * This is a paranoid check, because we would not have gotten the | |
2640 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 2641 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
2642 | /* Runtime instruction load was bad; |
2643 | * take it all the way back down so we can try again */ | |
e1623446 | 2644 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2645 | goto restart; |
2646 | } | |
2647 | ||
57aab75a TW |
2648 | ret = priv->cfg->ops->lib->alive_notify(priv); |
2649 | if (ret) { | |
39aadf8c WT |
2650 | IWL_WARN(priv, |
2651 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
2652 | goto restart; |
2653 | } | |
2654 | ||
5b9f8cd3 | 2655 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
2656 | set_bit(STATUS_ALIVE, &priv->status); |
2657 | ||
b74e31a9 WYG |
2658 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
2659 | /* Enable timer to monitor the driver queues */ | |
2660 | mod_timer(&priv->monitor_recover, | |
2661 | jiffies + | |
2662 | msecs_to_jiffies(priv->cfg->monitor_recover_period)); | |
2663 | } | |
2664 | ||
fee1247a | 2665 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2666 | return; |
2667 | ||
36d6825b | 2668 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2669 | |
470ab2dd | 2670 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2671 | |
2f748dec WYG |
2672 | /* Configure Tx antenna selection based on H/W config */ |
2673 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2674 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2675 | ||
3109ece1 | 2676 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
2677 | struct iwl_rxon_cmd *active_rxon = |
2678 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
2679 | /* apply any changes in staging */ |
2680 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
2681 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2682 | } else { | |
2683 | /* Initialize our rx_config data */ | |
1dda6d28 | 2684 | iwl_connection_init_rx_config(priv, NULL); |
45823531 AK |
2685 | |
2686 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2687 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c ZY |
2688 | } |
2689 | ||
9fbab516 | 2690 | /* Configure Bluetooth device coexistence support */ |
65b52bde | 2691 | priv->cfg->ops->hcmd->send_bt_config(priv); |
b481de9c | 2692 | |
4a4a9e81 TW |
2693 | iwl_reset_run_time_calib(priv); |
2694 | ||
b481de9c | 2695 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 2696 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2697 | |
2698 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2699 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2700 | |
e932a609 | 2701 | iwl_leds_init(priv); |
fe00b5a5 | 2702 | |
e1623446 | 2703 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2704 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2705 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2706 | |
e312c24c | 2707 | iwl_power_update_mode(priv, true); |
7e246191 RC |
2708 | IWL_DEBUG_INFO(priv, "Updated power mode\n"); |
2709 | ||
c46fbefa | 2710 | |
b481de9c ZY |
2711 | return; |
2712 | ||
2713 | restart: | |
2714 | queue_work(priv->workqueue, &priv->restart); | |
2715 | } | |
2716 | ||
4e39317d | 2717 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2718 | |
5b9f8cd3 | 2719 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2720 | { |
2721 | unsigned long flags; | |
2722 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2723 | |
e1623446 | 2724 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2725 | |
b481de9c ZY |
2726 | if (!exit_pending) |
2727 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2728 | ||
2c810ccd JB |
2729 | iwl_clear_ucode_stations(priv); |
2730 | iwl_dealloc_bcast_station(priv); | |
db125c78 | 2731 | iwl_clear_driver_stations(priv); |
b481de9c ZY |
2732 | |
2733 | /* Unblock any waiting calls */ | |
2734 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2735 | ||
b481de9c ZY |
2736 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2737 | * exiting the module */ | |
2738 | if (!exit_pending) | |
2739 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2740 | ||
2741 | /* stop and reset the on-board processor */ | |
3395f6e9 | 2742 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2743 | |
2744 | /* tell the device to stop sending interrupts */ | |
0359facc | 2745 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2746 | iwl_disable_interrupts(priv); |
0359facc MA |
2747 | spin_unlock_irqrestore(&priv->lock, flags); |
2748 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2749 | |
2750 | if (priv->mac80211_registered) | |
2751 | ieee80211_stop_queues(priv->hw); | |
2752 | ||
5b9f8cd3 | 2753 | /* If we have not previously called iwl_init() then |
a60e77e5 | 2754 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 2755 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2756 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2757 | STATUS_RF_KILL_HW | | |
9788864e RC |
2758 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2759 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
2760 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2761 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2762 | goto exit; |
2763 | } | |
2764 | ||
6da3a13e | 2765 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2766 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2767 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2768 | STATUS_RF_KILL_HW | | |
9788864e RC |
2769 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2770 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2771 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2772 | STATUS_FW_ERROR | |
2773 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2774 | STATUS_EXIT_PENDING; | |
b481de9c | 2775 | |
ef850d7c MA |
2776 | /* device going down, Stop using ICT table */ |
2777 | iwl_disable_ict(priv); | |
b481de9c | 2778 | |
74bcdb33 | 2779 | iwlagn_txq_ctx_stop(priv); |
54b81550 | 2780 | iwlagn_rxq_stop(priv); |
b481de9c | 2781 | |
309e731a BC |
2782 | /* Power-down device's busmaster DMA clocks */ |
2783 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2784 | udelay(5); |
2785 | ||
309e731a BC |
2786 | /* Make sure (redundant) we've released our request to stay awake */ |
2787 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
2788 | ||
4d2ccdb9 BC |
2789 | /* Stop the device, and put it in low power state */ |
2790 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
2791 | ||
b481de9c | 2792 | exit: |
885ba202 | 2793 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2794 | |
2795 | if (priv->ibss_beacon) | |
2796 | dev_kfree_skb(priv->ibss_beacon); | |
2797 | priv->ibss_beacon = NULL; | |
2798 | ||
2799 | /* clear out any free frames */ | |
fcab423d | 2800 | iwl_clear_free_frames(priv); |
b481de9c ZY |
2801 | } |
2802 | ||
5b9f8cd3 | 2803 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2804 | { |
2805 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2806 | __iwl_down(priv); |
b481de9c | 2807 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2808 | |
4e39317d | 2809 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2810 | } |
2811 | ||
086ed117 MA |
2812 | #define HW_READY_TIMEOUT (50) |
2813 | ||
2814 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
2815 | { | |
2816 | int ret = 0; | |
2817 | ||
2818 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2819 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2820 | ||
2821 | /* See if we got it */ | |
2822 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2823 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2824 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2825 | HW_READY_TIMEOUT); | |
2826 | if (ret != -ETIMEDOUT) | |
2827 | priv->hw_ready = true; | |
2828 | else | |
2829 | priv->hw_ready = false; | |
2830 | ||
2831 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
2832 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
2833 | return ret; | |
2834 | } | |
2835 | ||
2836 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
2837 | { | |
2838 | int ret = 0; | |
2839 | ||
91dd6c27 | 2840 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n"); |
086ed117 | 2841 | |
3354a0f6 MA |
2842 | ret = iwl_set_hw_ready(priv); |
2843 | if (priv->hw_ready) | |
2844 | return ret; | |
2845 | ||
2846 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2847 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2848 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2849 | ||
2850 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2851 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2852 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2853 | ||
3354a0f6 | 2854 | /* HW should be ready by now, check again. */ |
086ed117 MA |
2855 | if (ret != -ETIMEDOUT) |
2856 | iwl_set_hw_ready(priv); | |
2857 | ||
2858 | return ret; | |
2859 | } | |
2860 | ||
b481de9c ZY |
2861 | #define MAX_HW_RESTARTS 5 |
2862 | ||
5b9f8cd3 | 2863 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2864 | { |
57aab75a TW |
2865 | int i; |
2866 | int ret; | |
b481de9c ZY |
2867 | |
2868 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2869 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2870 | return -EIO; |
2871 | } | |
2872 | ||
e903fbd4 | 2873 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2874 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
2875 | return -EIO; |
2876 | } | |
2877 | ||
2c810ccd JB |
2878 | ret = iwl_alloc_bcast_station(priv, true); |
2879 | if (ret) | |
2880 | return ret; | |
2881 | ||
086ed117 MA |
2882 | iwl_prepare_card_hw(priv); |
2883 | ||
2884 | if (!priv->hw_ready) { | |
2885 | IWL_WARN(priv, "Exit HW not ready\n"); | |
2886 | return -EIO; | |
2887 | } | |
2888 | ||
e655b9f0 | 2889 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 2890 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 2891 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2892 | else |
e655b9f0 | 2893 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2894 | |
c1842d61 | 2895 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
2896 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
2897 | ||
5b9f8cd3 | 2898 | iwl_enable_interrupts(priv); |
a60e77e5 | 2899 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 2900 | return 0; |
b481de9c ZY |
2901 | } |
2902 | ||
3395f6e9 | 2903 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2904 | |
74bcdb33 | 2905 | ret = iwlagn_hw_nic_init(priv); |
57aab75a | 2906 | if (ret) { |
15b1687c | 2907 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 2908 | return ret; |
b481de9c ZY |
2909 | } |
2910 | ||
2911 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2912 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2913 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2914 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2915 | ||
2916 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 2917 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 2918 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2919 | |
2920 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2921 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2922 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2923 | |
2924 | /* Copy original ucode data image from disk into backup cache. | |
2925 | * This will be used to initialize the on-board processor's | |
2926 | * data SRAM for a clean start when the runtime program first loads. */ | |
2927 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2928 | priv->ucode_data.len); |
b481de9c | 2929 | |
b481de9c ZY |
2930 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2931 | ||
b481de9c ZY |
2932 | /* load bootstrap state machine, |
2933 | * load bootstrap program into processor's memory, | |
2934 | * prepare to load the "initialize" uCode */ | |
57aab75a | 2935 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 2936 | |
57aab75a | 2937 | if (ret) { |
15b1687c WT |
2938 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
2939 | ret); | |
b481de9c ZY |
2940 | continue; |
2941 | } | |
2942 | ||
2943 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 2944 | iwl_nic_start(priv); |
b481de9c | 2945 | |
e1623446 | 2946 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2947 | |
2948 | return 0; | |
2949 | } | |
2950 | ||
2951 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 2952 | __iwl_down(priv); |
64e72c3e | 2953 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2954 | |
2955 | /* tried to restart and config the device for as long as our | |
2956 | * patience could withstand */ | |
15b1687c | 2957 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2958 | return -EIO; |
2959 | } | |
2960 | ||
2961 | ||
2962 | /***************************************************************************** | |
2963 | * | |
2964 | * Workqueue callbacks | |
2965 | * | |
2966 | *****************************************************************************/ | |
2967 | ||
4a4a9e81 | 2968 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2969 | { |
c79dd5b5 TW |
2970 | struct iwl_priv *priv = |
2971 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2972 | |
2973 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2974 | return; | |
2975 | ||
2976 | mutex_lock(&priv->mutex); | |
f3ccc08c | 2977 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
2978 | mutex_unlock(&priv->mutex); |
2979 | } | |
2980 | ||
4a4a9e81 | 2981 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 2982 | { |
c79dd5b5 TW |
2983 | struct iwl_priv *priv = |
2984 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2985 | |
2986 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2987 | return; | |
2988 | ||
258c44a0 MA |
2989 | /* enable dram interrupt */ |
2990 | iwl_reset_ict(priv); | |
2991 | ||
b481de9c | 2992 | mutex_lock(&priv->mutex); |
4a4a9e81 | 2993 | iwl_alive_start(priv); |
b481de9c ZY |
2994 | mutex_unlock(&priv->mutex); |
2995 | } | |
2996 | ||
16e727e8 EG |
2997 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2998 | { | |
2999 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
3000 | run_time_calib_work); | |
3001 | ||
3002 | mutex_lock(&priv->mutex); | |
3003 | ||
3004 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
3005 | test_bit(STATUS_SCANNING, &priv->status)) { | |
3006 | mutex_unlock(&priv->mutex); | |
3007 | return; | |
3008 | } | |
3009 | ||
3010 | if (priv->start_calib) { | |
7980fba5 WYG |
3011 | if (priv->cfg->bt_statistics) { |
3012 | iwl_chain_noise_calibration(priv, | |
3013 | (void *)&priv->_agn.statistics_bt); | |
3014 | iwl_sensitivity_calibration(priv, | |
3015 | (void *)&priv->_agn.statistics_bt); | |
3016 | } else { | |
3017 | iwl_chain_noise_calibration(priv, | |
3018 | (void *)&priv->_agn.statistics); | |
3019 | iwl_sensitivity_calibration(priv, | |
3020 | (void *)&priv->_agn.statistics); | |
3021 | } | |
16e727e8 EG |
3022 | } |
3023 | ||
3024 | mutex_unlock(&priv->mutex); | |
16e727e8 EG |
3025 | } |
3026 | ||
5b9f8cd3 | 3027 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 3028 | { |
c79dd5b5 | 3029 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
3030 | |
3031 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3032 | return; | |
3033 | ||
19cc1087 JB |
3034 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
3035 | mutex_lock(&priv->mutex); | |
3036 | priv->vif = NULL; | |
3037 | priv->is_open = 0; | |
3038 | mutex_unlock(&priv->mutex); | |
3039 | iwl_down(priv); | |
3040 | ieee80211_restart_hw(priv->hw); | |
3041 | } else { | |
3042 | iwl_down(priv); | |
80676518 JB |
3043 | |
3044 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3045 | return; | |
3046 | ||
3047 | mutex_lock(&priv->mutex); | |
3048 | __iwl_up(priv); | |
3049 | mutex_unlock(&priv->mutex); | |
19cc1087 | 3050 | } |
b481de9c ZY |
3051 | } |
3052 | ||
5b9f8cd3 | 3053 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 3054 | { |
c79dd5b5 TW |
3055 | struct iwl_priv *priv = |
3056 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
3057 | |
3058 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3059 | return; | |
3060 | ||
3061 | mutex_lock(&priv->mutex); | |
54b81550 | 3062 | iwlagn_rx_replenish(priv); |
b481de9c ZY |
3063 | mutex_unlock(&priv->mutex); |
3064 | } | |
3065 | ||
7878a5a4 MA |
3066 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
3067 | ||
1dda6d28 | 3068 | void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 3069 | { |
b481de9c | 3070 | struct ieee80211_conf *conf = NULL; |
857485c0 | 3071 | int ret = 0; |
b481de9c | 3072 | |
1dda6d28 JB |
3073 | if (!vif || !priv->is_open) |
3074 | return; | |
3075 | ||
3076 | if (vif->type == NL80211_IFTYPE_AP) { | |
15b1687c | 3077 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
3078 | return; |
3079 | } | |
3080 | ||
b481de9c ZY |
3081 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
3082 | return; | |
3083 | ||
2a421b91 | 3084 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 3085 | |
b481de9c ZY |
3086 | conf = ieee80211_get_hw_conf(priv->hw); |
3087 | ||
3088 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 3089 | iwlcore_commit_rxon(priv); |
b481de9c | 3090 | |
1dda6d28 | 3091 | iwl_setup_rxon_timing(priv, vif); |
857485c0 | 3092 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 3093 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 3094 | if (ret) |
39aadf8c | 3095 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3096 | "Attempting to continue.\n"); |
3097 | ||
3098 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
3099 | ||
42eb7c64 | 3100 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 3101 | |
45823531 AK |
3102 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
3103 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
3104 | ||
1dda6d28 | 3105 | priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid); |
b481de9c | 3106 | |
e1623446 | 3107 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
1dda6d28 | 3108 | vif->bss_conf.aid, vif->bss_conf.beacon_int); |
b481de9c | 3109 | |
c213d745 | 3110 | if (vif->bss_conf.use_short_preamble) |
b481de9c ZY |
3111 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
3112 | else | |
3113 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
3114 | ||
3115 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
c213d745 | 3116 | if (vif->bss_conf.use_short_slot) |
b481de9c ZY |
3117 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
3118 | else | |
3119 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
b481de9c ZY |
3120 | } |
3121 | ||
e0158e61 | 3122 | iwlcore_commit_rxon(priv); |
b481de9c | 3123 | |
fe6b23dd | 3124 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
1dda6d28 | 3125 | vif->bss_conf.aid, priv->active_rxon.bssid_addr); |
fe6b23dd | 3126 | |
1dda6d28 | 3127 | switch (vif->type) { |
05c914fe | 3128 | case NL80211_IFTYPE_STATION: |
b481de9c | 3129 | break; |
05c914fe | 3130 | case NL80211_IFTYPE_ADHOC: |
5b9f8cd3 | 3131 | iwl_send_beacon_cmd(priv); |
b481de9c | 3132 | break; |
b481de9c | 3133 | default: |
15b1687c | 3134 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
1dda6d28 | 3135 | __func__, vif->type); |
b481de9c ZY |
3136 | break; |
3137 | } | |
3138 | ||
04816448 GE |
3139 | /* the chain noise calibration will enabled PM upon completion |
3140 | * If chain noise has already been run, then we need to enable | |
3141 | * power management here */ | |
3142 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
e312c24c | 3143 | iwl_power_update_mode(priv, false); |
c90a74ba EG |
3144 | |
3145 | /* Enable Rx differential gain and sensitivity calibrations */ | |
3146 | iwl_chain_noise_reset(priv); | |
3147 | priv->start_calib = 1; | |
3148 | ||
508e32e1 RC |
3149 | } |
3150 | ||
b481de9c ZY |
3151 | /***************************************************************************** |
3152 | * | |
3153 | * mac80211 entry point functions | |
3154 | * | |
3155 | *****************************************************************************/ | |
3156 | ||
154b25ce | 3157 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 3158 | |
f0b6e2e8 RC |
3159 | /* |
3160 | * Not a mac80211 entry point function, but it fits in with all the | |
3161 | * other mac80211 functions grouped here. | |
3162 | */ | |
dd7a2509 JB |
3163 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
3164 | struct iwlagn_ucode_capabilities *capa) | |
f0b6e2e8 RC |
3165 | { |
3166 | int ret; | |
3167 | struct ieee80211_hw *hw = priv->hw; | |
3168 | hw->rate_control_algorithm = "iwl-agn-rs"; | |
3169 | ||
3170 | /* Tell mac80211 our characteristics */ | |
3171 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
f0b6e2e8 RC |
3172 | IEEE80211_HW_AMPDU_AGGREGATION | |
3173 | IEEE80211_HW_SPECTRUM_MGMT; | |
3174 | ||
3175 | if (!priv->cfg->broken_powersave) | |
3176 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | |
3177 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
3178 | ||
ba37a3d0 JB |
3179 | if (priv->cfg->sku & IWL_SKU_N) |
3180 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
3181 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
3182 | ||
8d9698b3 | 3183 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
fd1af15d JB |
3184 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
3185 | ||
f0b6e2e8 RC |
3186 | hw->wiphy->interface_modes = |
3187 | BIT(NL80211_IFTYPE_STATION) | | |
3188 | BIT(NL80211_IFTYPE_ADHOC); | |
3189 | ||
f6c8f152 | 3190 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
5be83de5 | 3191 | WIPHY_FLAG_DISABLE_BEACON_HINTS; |
f0b6e2e8 RC |
3192 | |
3193 | /* | |
3194 | * For now, disable PS by default because it affects | |
3195 | * RX performance significantly. | |
3196 | */ | |
5be83de5 | 3197 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
f0b6e2e8 | 3198 | |
1382c71c | 3199 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
f0b6e2e8 | 3200 | /* we create the 802.11 header and a zero-length SSID element */ |
dd7a2509 | 3201 | hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2; |
f0b6e2e8 RC |
3202 | |
3203 | /* Default value; 4 EDCA QOS priorities */ | |
3204 | hw->queues = 4; | |
3205 | ||
3206 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
3207 | ||
3208 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
3209 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3210 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
3211 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
3212 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3213 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
3214 | ||
3215 | ret = ieee80211_register_hw(priv->hw); | |
3216 | if (ret) { | |
3217 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
3218 | return ret; | |
3219 | } | |
3220 | priv->mac80211_registered = 1; | |
3221 | ||
3222 | return 0; | |
3223 | } | |
3224 | ||
3225 | ||
5b9f8cd3 | 3226 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3227 | { |
c79dd5b5 | 3228 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3229 | int ret; |
b481de9c | 3230 | |
e1623446 | 3231 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3232 | |
3233 | /* we should be verifying the device is ready to be opened */ | |
3234 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 3235 | ret = __iwl_up(priv); |
b481de9c | 3236 | mutex_unlock(&priv->mutex); |
5a66926a | 3237 | |
e655b9f0 | 3238 | if (ret) |
6cd0b1cb | 3239 | return ret; |
e655b9f0 | 3240 | |
c1842d61 TW |
3241 | if (iwl_is_rfkill(priv)) |
3242 | goto out; | |
3243 | ||
e1623446 | 3244 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 3245 | |
fe9b6b72 | 3246 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 3247 | * mac80211 will not be run successfully. */ |
154b25ce EG |
3248 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
3249 | test_bit(STATUS_READY, &priv->status), | |
3250 | UCODE_READY_TIMEOUT); | |
3251 | if (!ret) { | |
3252 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 3253 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 3254 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 3255 | return -ETIMEDOUT; |
5a66926a | 3256 | } |
fe9b6b72 | 3257 | } |
0a078ffa | 3258 | |
e932a609 JB |
3259 | iwl_led_start(priv); |
3260 | ||
c1842d61 | 3261 | out: |
0a078ffa | 3262 | priv->is_open = 1; |
e1623446 | 3263 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3264 | return 0; |
3265 | } | |
3266 | ||
5b9f8cd3 | 3267 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3268 | { |
c79dd5b5 | 3269 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3270 | |
e1623446 | 3271 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 3272 | |
19cc1087 | 3273 | if (!priv->is_open) |
e655b9f0 | 3274 | return; |
e655b9f0 | 3275 | |
b481de9c | 3276 | priv->is_open = 0; |
5a66926a | 3277 | |
5bddf549 | 3278 | if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) { |
e655b9f0 ZY |
3279 | /* stop mac, cancel any scan request and clear |
3280 | * RXON_FILTER_ASSOC_MSK BIT | |
3281 | */ | |
5a66926a | 3282 | mutex_lock(&priv->mutex); |
2a421b91 | 3283 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 3284 | mutex_unlock(&priv->mutex); |
fde3571f MA |
3285 | } |
3286 | ||
5b9f8cd3 | 3287 | iwl_down(priv); |
5a66926a ZY |
3288 | |
3289 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
3290 | |
3291 | /* enable interrupts again in order to receive rfkill changes */ | |
3292 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
3293 | iwl_enable_interrupts(priv); | |
948c171c | 3294 | |
e1623446 | 3295 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3296 | } |
3297 | ||
5b9f8cd3 | 3298 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3299 | { |
c79dd5b5 | 3300 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3301 | |
e1623446 | 3302 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 3303 | |
e1623446 | 3304 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3305 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3306 | |
74bcdb33 | 3307 | if (iwlagn_tx_skb(priv, skb)) |
b481de9c ZY |
3308 | dev_kfree_skb_any(skb); |
3309 | ||
e1623446 | 3310 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 3311 | return NETDEV_TX_OK; |
b481de9c ZY |
3312 | } |
3313 | ||
1dda6d28 | 3314 | void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 3315 | { |
857485c0 | 3316 | int ret = 0; |
b481de9c | 3317 | |
d986bcd1 | 3318 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3319 | return; |
3320 | ||
3321 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 3322 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
3323 | |
3324 | /* RXON - unassoc (to set timing command) */ | |
3325 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 3326 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3327 | |
3328 | /* RXON Timing */ | |
1dda6d28 | 3329 | iwl_setup_rxon_timing(priv, vif); |
857485c0 | 3330 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 3331 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 3332 | if (ret) |
39aadf8c | 3333 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3334 | "Attempting to continue.\n"); |
3335 | ||
f513dfff DH |
3336 | /* AP has all antennas */ |
3337 | priv->chain_noise_data.active_chains = | |
3338 | priv->hw_params.valid_rx_ant; | |
3339 | iwl_set_rxon_ht(priv, &priv->current_ht_config); | |
45823531 AK |
3340 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
3341 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c | 3342 | |
1dda6d28 JB |
3343 | priv->staging_rxon.assoc_id = 0; |
3344 | ||
c213d745 | 3345 | if (vif->bss_conf.use_short_preamble) |
b481de9c ZY |
3346 | priv->staging_rxon.flags |= |
3347 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
3348 | else | |
3349 | priv->staging_rxon.flags &= | |
3350 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
3351 | ||
3352 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
c213d745 | 3353 | if (vif->bss_conf.use_short_slot) |
b481de9c ZY |
3354 | priv->staging_rxon.flags |= |
3355 | RXON_FLG_SHORT_SLOT_MSK; | |
3356 | else | |
3357 | priv->staging_rxon.flags &= | |
3358 | ~RXON_FLG_SHORT_SLOT_MSK; | |
b481de9c ZY |
3359 | } |
3360 | /* restore RXON assoc */ | |
3361 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 3362 | iwlcore_commit_rxon(priv); |
e1493deb | 3363 | } |
5b9f8cd3 | 3364 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
3365 | |
3366 | /* FIXME - we need to add code here to detect a totally new | |
3367 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3368 | * clear sta table, add BCAST sta... */ | |
3369 | } | |
3370 | ||
5b9f8cd3 | 3371 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
b3fbdcf4 JB |
3372 | struct ieee80211_vif *vif, |
3373 | struct ieee80211_key_conf *keyconf, | |
3374 | struct ieee80211_sta *sta, | |
3375 | u32 iv32, u16 *phase1key) | |
ab885f8c | 3376 | { |
ab885f8c | 3377 | |
9f58671e | 3378 | struct iwl_priv *priv = hw->priv; |
e1623446 | 3379 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 3380 | |
bdbb612f | 3381 | iwl_update_tkip_key(priv, keyconf, sta, |
b3fbdcf4 | 3382 | iv32, phase1key); |
ab885f8c | 3383 | |
e1623446 | 3384 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
3385 | } |
3386 | ||
5b9f8cd3 | 3387 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3388 | struct ieee80211_vif *vif, |
3389 | struct ieee80211_sta *sta, | |
b481de9c ZY |
3390 | struct ieee80211_key_conf *key) |
3391 | { | |
c79dd5b5 | 3392 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
3393 | int ret; |
3394 | u8 sta_id; | |
3395 | bool is_default_wep_key = false; | |
b481de9c | 3396 | |
e1623446 | 3397 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3398 | |
90e8e424 | 3399 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 3400 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3401 | return -EOPNOTSUPP; |
3402 | } | |
b481de9c | 3403 | |
0af8bcae JB |
3404 | sta_id = iwl_sta_id_or_broadcast(priv, sta); |
3405 | if (sta_id == IWL_INVALID_STATION) | |
3406 | return -EINVAL; | |
b481de9c | 3407 | |
6974e363 | 3408 | mutex_lock(&priv->mutex); |
2a421b91 | 3409 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 | 3410 | |
a90178fa JB |
3411 | /* |
3412 | * If we are getting WEP group key and we didn't receive any key mapping | |
6974e363 EG |
3413 | * so far, we are in legacy wep mode (group key only), otherwise we are |
3414 | * in 1X mode. | |
a90178fa JB |
3415 | * In legacy wep mode, we use another host command to the uCode. |
3416 | */ | |
3417 | if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) { | |
6974e363 EG |
3418 | if (cmd == SET_KEY) |
3419 | is_default_wep_key = !priv->key_mapping_key; | |
3420 | else | |
ccc038ab EG |
3421 | is_default_wep_key = |
3422 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 3423 | } |
052c4b9f | 3424 | |
b481de9c | 3425 | switch (cmd) { |
deb09c43 | 3426 | case SET_KEY: |
6974e363 EG |
3427 | if (is_default_wep_key) |
3428 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 3429 | else |
7480513f | 3430 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 3431 | |
e1623446 | 3432 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
3433 | break; |
3434 | case DISABLE_KEY: | |
6974e363 EG |
3435 | if (is_default_wep_key) |
3436 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 3437 | else |
3ec47732 | 3438 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 3439 | |
e1623446 | 3440 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
3441 | break; |
3442 | default: | |
deb09c43 | 3443 | ret = -EINVAL; |
b481de9c ZY |
3444 | } |
3445 | ||
72e15d71 | 3446 | mutex_unlock(&priv->mutex); |
e1623446 | 3447 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3448 | |
deb09c43 | 3449 | return ret; |
b481de9c ZY |
3450 | } |
3451 | ||
cfecc6b4 WYG |
3452 | /* |
3453 | * switch to RTS/CTS for TX | |
3454 | */ | |
3455 | static void iwl_enable_rts_cts(struct iwl_priv *priv) | |
3456 | { | |
3457 | ||
3458 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3459 | return; | |
3460 | ||
3461 | priv->staging_rxon.flags &= ~RXON_FLG_SELF_CTS_EN; | |
3462 | if (!test_bit(STATUS_SCANNING, &priv->status)) { | |
3463 | IWL_DEBUG_INFO(priv, "use RTS/CTS protection\n"); | |
3464 | iwlcore_commit_rxon(priv); | |
3465 | } else { | |
3466 | /* scanning, defer the request until scan completed */ | |
3467 | IWL_DEBUG_INFO(priv, "defer setting RTS/CTS protection\n"); | |
3468 | } | |
3469 | } | |
3470 | ||
5b9f8cd3 | 3471 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 3472 | struct ieee80211_vif *vif, |
832f47e3 JB |
3473 | enum ieee80211_ampdu_mlme_action action, |
3474 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) | |
d783b061 TW |
3475 | { |
3476 | struct iwl_priv *priv = hw->priv; | |
4620fefa | 3477 | int ret = -EINVAL; |
d783b061 | 3478 | |
e1623446 | 3479 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 3480 | sta->addr, tid); |
d783b061 TW |
3481 | |
3482 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
3483 | return -EACCES; | |
3484 | ||
4620fefa JB |
3485 | mutex_lock(&priv->mutex); |
3486 | ||
d783b061 TW |
3487 | switch (action) { |
3488 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 3489 | IWL_DEBUG_HT(priv, "start Rx\n"); |
4620fefa JB |
3490 | ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn); |
3491 | break; | |
d783b061 | 3492 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 3493 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
619753ff | 3494 | ret = iwl_sta_rx_agg_stop(priv, sta, tid); |
5c2207c6 | 3495 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa JB |
3496 | ret = 0; |
3497 | break; | |
d783b061 | 3498 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 3499 | IWL_DEBUG_HT(priv, "start Tx\n"); |
619753ff | 3500 | ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn); |
d5a0ffa3 WYG |
3501 | if (ret == 0) { |
3502 | priv->_agn.agg_tids_count++; | |
3503 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3504 | priv->_agn.agg_tids_count); | |
3505 | } | |
4620fefa | 3506 | break; |
d783b061 | 3507 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 3508 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
619753ff | 3509 | ret = iwlagn_tx_agg_stop(priv, vif, sta, tid); |
d5a0ffa3 WYG |
3510 | if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { |
3511 | priv->_agn.agg_tids_count--; | |
3512 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3513 | priv->_agn.agg_tids_count); | |
3514 | } | |
5c2207c6 | 3515 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa JB |
3516 | ret = 0; |
3517 | break; | |
f0527971 | 3518 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
cfecc6b4 WYG |
3519 | if (priv->cfg->use_rts_for_ht) { |
3520 | /* | |
3521 | * switch to RTS/CTS if it is the prefer protection | |
3522 | * method for HT traffic | |
3523 | */ | |
3524 | iwl_enable_rts_cts(priv); | |
3525 | } | |
3526 | ret = 0; | |
d783b061 TW |
3527 | break; |
3528 | } | |
4620fefa JB |
3529 | mutex_unlock(&priv->mutex); |
3530 | ||
3531 | return ret; | |
d783b061 | 3532 | } |
9f58671e | 3533 | |
6ab10ff8 JB |
3534 | static void iwl_mac_sta_notify(struct ieee80211_hw *hw, |
3535 | struct ieee80211_vif *vif, | |
3536 | enum sta_notify_cmd cmd, | |
3537 | struct ieee80211_sta *sta) | |
3538 | { | |
3539 | struct iwl_priv *priv = hw->priv; | |
3540 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
3541 | int sta_id; | |
3542 | ||
6ab10ff8 | 3543 | switch (cmd) { |
6ab10ff8 JB |
3544 | case STA_NOTIFY_SLEEP: |
3545 | WARN_ON(!sta_priv->client); | |
3546 | sta_priv->asleep = true; | |
3547 | if (atomic_read(&sta_priv->pending_frames) > 0) | |
3548 | ieee80211_sta_block_awake(hw, sta, true); | |
3549 | break; | |
3550 | case STA_NOTIFY_AWAKE: | |
3551 | WARN_ON(!sta_priv->client); | |
49dcc819 DH |
3552 | if (!sta_priv->asleep) |
3553 | break; | |
6ab10ff8 | 3554 | sta_priv->asleep = false; |
2a87c26b | 3555 | sta_id = iwl_sta_id(sta); |
6ab10ff8 JB |
3556 | if (sta_id != IWL_INVALID_STATION) |
3557 | iwl_sta_modify_ps_wake(priv, sta_id); | |
3558 | break; | |
3559 | default: | |
3560 | break; | |
3561 | } | |
3562 | } | |
3563 | ||
fe6b23dd RC |
3564 | static int iwlagn_mac_sta_add(struct ieee80211_hw *hw, |
3565 | struct ieee80211_vif *vif, | |
3566 | struct ieee80211_sta *sta) | |
3567 | { | |
3568 | struct iwl_priv *priv = hw->priv; | |
3569 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
eafdfbd3 | 3570 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
3571 | int ret; |
3572 | u8 sta_id; | |
3573 | ||
3574 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
3575 | sta->addr); | |
da5ae1cf RC |
3576 | mutex_lock(&priv->mutex); |
3577 | IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n", | |
3578 | sta->addr); | |
3579 | sta_priv->common.sta_id = IWL_INVALID_STATION; | |
fe6b23dd RC |
3580 | |
3581 | atomic_set(&sta_priv->pending_frames, 0); | |
3582 | if (vif->type == NL80211_IFTYPE_AP) | |
3583 | sta_priv->client = true; | |
3584 | ||
3585 | ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap, | |
3586 | &sta_id); | |
3587 | if (ret) { | |
3588 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3589 | sta->addr, ret); | |
3590 | /* Should we return success if return code is EEXIST ? */ | |
da5ae1cf | 3591 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3592 | return ret; |
3593 | } | |
3594 | ||
fd1af15d JB |
3595 | sta_priv->common.sta_id = sta_id; |
3596 | ||
fe6b23dd | 3597 | /* Initialize rate scaling */ |
91dd6c27 | 3598 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
3599 | sta->addr); |
3600 | iwl_rs_rate_init(priv, sta, sta_id); | |
da5ae1cf | 3601 | mutex_unlock(&priv->mutex); |
fe6b23dd | 3602 | |
fd1af15d | 3603 | return 0; |
fe6b23dd RC |
3604 | } |
3605 | ||
79d07325 WYG |
3606 | static void iwl_mac_channel_switch(struct ieee80211_hw *hw, |
3607 | struct ieee80211_channel_switch *ch_switch) | |
3608 | { | |
3609 | struct iwl_priv *priv = hw->priv; | |
3610 | const struct iwl_channel_info *ch_info; | |
3611 | struct ieee80211_conf *conf = &hw->conf; | |
3612 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; | |
3613 | u16 ch; | |
3614 | unsigned long flags = 0; | |
3615 | ||
3616 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3617 | ||
3618 | if (iwl_is_rfkill(priv)) | |
3619 | goto out_exit; | |
3620 | ||
3621 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
3622 | test_bit(STATUS_SCANNING, &priv->status)) | |
3623 | goto out_exit; | |
3624 | ||
3625 | if (!iwl_is_associated(priv)) | |
3626 | goto out_exit; | |
3627 | ||
3628 | /* channel switch in progress */ | |
3629 | if (priv->switch_rxon.switch_in_progress == true) | |
3630 | goto out_exit; | |
3631 | ||
3632 | mutex_lock(&priv->mutex); | |
3633 | if (priv->cfg->ops->lib->set_channel_switch) { | |
3634 | ||
3635 | ch = ieee80211_frequency_to_channel( | |
3636 | ch_switch->channel->center_freq); | |
3637 | if (le16_to_cpu(priv->active_rxon.channel) != ch) { | |
3638 | ch_info = iwl_get_channel_info(priv, | |
3639 | conf->channel->band, | |
3640 | ch); | |
3641 | if (!is_channel_valid(ch_info)) { | |
3642 | IWL_DEBUG_MAC80211(priv, "invalid channel\n"); | |
3643 | goto out; | |
3644 | } | |
3645 | spin_lock_irqsave(&priv->lock, flags); | |
3646 | ||
3647 | priv->current_ht_config.smps = conf->smps_mode; | |
3648 | ||
3649 | /* Configure HT40 channels */ | |
3650 | ht_conf->is_ht = conf_is_ht(conf); | |
3651 | if (ht_conf->is_ht) { | |
3652 | if (conf_is_ht40_minus(conf)) { | |
3653 | ht_conf->extension_chan_offset = | |
3654 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; | |
3655 | ht_conf->is_40mhz = true; | |
3656 | } else if (conf_is_ht40_plus(conf)) { | |
3657 | ht_conf->extension_chan_offset = | |
3658 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; | |
3659 | ht_conf->is_40mhz = true; | |
3660 | } else { | |
3661 | ht_conf->extension_chan_offset = | |
3662 | IEEE80211_HT_PARAM_CHA_SEC_NONE; | |
3663 | ht_conf->is_40mhz = false; | |
3664 | } | |
3665 | } else | |
3666 | ht_conf->is_40mhz = false; | |
3667 | ||
3668 | /* if we are switching from ht to 2.4 clear flags | |
3669 | * from any ht related info since 2.4 does not | |
3670 | * support ht */ | |
3671 | if ((le16_to_cpu(priv->staging_rxon.channel) != ch)) | |
3672 | priv->staging_rxon.flags = 0; | |
3673 | ||
3674 | iwl_set_rxon_channel(priv, conf->channel); | |
3675 | iwl_set_rxon_ht(priv, ht_conf); | |
3676 | iwl_set_flags_for_band(priv, conf->channel->band, | |
3677 | priv->vif); | |
3678 | spin_unlock_irqrestore(&priv->lock, flags); | |
3679 | ||
3680 | iwl_set_rate(priv); | |
3681 | /* | |
3682 | * at this point, staging_rxon has the | |
3683 | * configuration for channel switch | |
3684 | */ | |
3685 | if (priv->cfg->ops->lib->set_channel_switch(priv, | |
3686 | ch_switch)) | |
3687 | priv->switch_rxon.switch_in_progress = false; | |
3688 | } | |
3689 | } | |
3690 | out: | |
3691 | mutex_unlock(&priv->mutex); | |
3692 | out_exit: | |
3693 | if (!priv->switch_rxon.switch_in_progress) | |
3694 | ieee80211_chswitch_done(priv->vif, false); | |
3695 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
3696 | } | |
3697 | ||
716c74b0 WYG |
3698 | static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop) |
3699 | { | |
3700 | struct iwl_priv *priv = hw->priv; | |
3701 | ||
3702 | mutex_lock(&priv->mutex); | |
3703 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3704 | ||
3705 | /* do not support "flush" */ | |
3706 | if (!priv->cfg->ops->lib->txfifo_flush) | |
3707 | goto done; | |
3708 | ||
3709 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
3710 | IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n"); | |
3711 | goto done; | |
3712 | } | |
3713 | if (iwl_is_rfkill(priv)) { | |
3714 | IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n"); | |
3715 | goto done; | |
3716 | } | |
3717 | ||
3718 | /* | |
3719 | * mac80211 will not push any more frames for transmit | |
3720 | * until the flush is completed | |
3721 | */ | |
3722 | if (drop) { | |
3723 | IWL_DEBUG_MAC80211(priv, "send flush command\n"); | |
3724 | if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) { | |
3725 | IWL_ERR(priv, "flush request fail\n"); | |
3726 | goto done; | |
3727 | } | |
3728 | } | |
3729 | IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n"); | |
3730 | iwlagn_wait_tx_queue_empty(priv); | |
3731 | done: | |
3732 | mutex_unlock(&priv->mutex); | |
3733 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
3734 | } | |
3735 | ||
b481de9c ZY |
3736 | /***************************************************************************** |
3737 | * | |
3738 | * driver setup and teardown | |
3739 | * | |
3740 | *****************************************************************************/ | |
3741 | ||
4e39317d | 3742 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3743 | { |
d21050c7 | 3744 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3745 | |
3746 | init_waitqueue_head(&priv->wait_command_queue); | |
3747 | ||
5b9f8cd3 EG |
3748 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3749 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3750 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3751 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
65550636 | 3752 | INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush); |
4a4a9e81 TW |
3753 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
3754 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 3755 | |
2a421b91 | 3756 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3757 | |
4e39317d EG |
3758 | if (priv->cfg->ops->lib->setup_deferred_work) |
3759 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3760 | ||
3761 | init_timer(&priv->statistics_periodic); | |
3762 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3763 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3764 | |
a9e1cb6a WYG |
3765 | init_timer(&priv->ucode_trace); |
3766 | priv->ucode_trace.data = (unsigned long)priv; | |
3767 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3768 | ||
b74e31a9 WYG |
3769 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
3770 | init_timer(&priv->monitor_recover); | |
3771 | priv->monitor_recover.data = (unsigned long)priv; | |
3772 | priv->monitor_recover.function = | |
3773 | priv->cfg->ops->lib->recover_from_tx_stall; | |
3774 | } | |
3775 | ||
ef850d7c MA |
3776 | if (!priv->cfg->use_isr_legacy) |
3777 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3778 | iwl_irq_tasklet, (unsigned long)priv); | |
3779 | else | |
3780 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3781 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
3782 | } |
3783 | ||
4e39317d | 3784 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3785 | { |
4e39317d EG |
3786 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3787 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3788 | |
3ae6a054 | 3789 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c | 3790 | cancel_delayed_work(&priv->scan_check); |
88be0264 | 3791 | cancel_work_sync(&priv->start_internal_scan); |
b481de9c | 3792 | cancel_delayed_work(&priv->alive_start); |
815e629b | 3793 | cancel_work_sync(&priv->run_time_calib_work); |
b481de9c | 3794 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 3795 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 3796 | del_timer_sync(&priv->ucode_trace); |
b74e31a9 WYG |
3797 | if (priv->cfg->ops->lib->recover_from_tx_stall) |
3798 | del_timer_sync(&priv->monitor_recover); | |
b481de9c ZY |
3799 | } |
3800 | ||
89f186a8 RC |
3801 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
3802 | struct ieee80211_rate *rates) | |
3803 | { | |
3804 | int i; | |
3805 | ||
3806 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
3807 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
3808 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
3809 | rates[i].hw_value_short = i; | |
3810 | rates[i].flags = 0; | |
3811 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
3812 | /* | |
3813 | * If CCK != 1M then set short preamble rate flag. | |
3814 | */ | |
3815 | rates[i].flags |= | |
3816 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
3817 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
3818 | } | |
3819 | } | |
3820 | } | |
3821 | ||
3822 | static int iwl_init_drv(struct iwl_priv *priv) | |
3823 | { | |
3824 | int ret; | |
3825 | ||
3826 | priv->ibss_beacon = NULL; | |
3827 | ||
89f186a8 RC |
3828 | spin_lock_init(&priv->sta_lock); |
3829 | spin_lock_init(&priv->hcmd_lock); | |
3830 | ||
3831 | INIT_LIST_HEAD(&priv->free_frames); | |
3832 | ||
3833 | mutex_init(&priv->mutex); | |
d2dfe6df | 3834 | mutex_init(&priv->sync_cmd_mutex); |
89f186a8 | 3835 | |
89f186a8 RC |
3836 | priv->ieee_channels = NULL; |
3837 | priv->ieee_rates = NULL; | |
3838 | priv->band = IEEE80211_BAND_2GHZ; | |
3839 | ||
3840 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 3841 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 3842 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
d5a0ffa3 | 3843 | priv->_agn.agg_tids_count = 0; |
89f186a8 | 3844 | |
8a472da4 WYG |
3845 | /* initialize force reset */ |
3846 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
3847 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
3848 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
3849 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 RC |
3850 | |
3851 | /* Choose which receivers/antennas to use */ | |
3852 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
3853 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
3854 | ||
3855 | iwl_init_scan_params(priv); | |
3856 | ||
89f186a8 RC |
3857 | /* Set the tx_power_user_lmt to the lowest power level |
3858 | * this value will get overwritten by channel max power avg | |
3859 | * from eeprom */ | |
b744cb79 | 3860 | priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
89f186a8 RC |
3861 | |
3862 | ret = iwl_init_channel_map(priv); | |
3863 | if (ret) { | |
3864 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3865 | goto err; | |
3866 | } | |
3867 | ||
3868 | ret = iwlcore_init_geos(priv); | |
3869 | if (ret) { | |
3870 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3871 | goto err_free_channel_map; | |
3872 | } | |
3873 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
3874 | ||
3875 | return 0; | |
3876 | ||
3877 | err_free_channel_map: | |
3878 | iwl_free_channel_map(priv); | |
3879 | err: | |
3880 | return ret; | |
3881 | } | |
3882 | ||
3883 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
3884 | { | |
3885 | iwl_calib_free_results(priv); | |
3886 | iwlcore_free_geos(priv); | |
3887 | iwl_free_channel_map(priv); | |
811ecc99 | 3888 | kfree(priv->scan_cmd); |
89f186a8 RC |
3889 | } |
3890 | ||
5b9f8cd3 EG |
3891 | static struct ieee80211_ops iwl_hw_ops = { |
3892 | .tx = iwl_mac_tx, | |
3893 | .start = iwl_mac_start, | |
3894 | .stop = iwl_mac_stop, | |
3895 | .add_interface = iwl_mac_add_interface, | |
3896 | .remove_interface = iwl_mac_remove_interface, | |
3897 | .config = iwl_mac_config, | |
5b9f8cd3 EG |
3898 | .configure_filter = iwl_configure_filter, |
3899 | .set_key = iwl_mac_set_key, | |
3900 | .update_tkip_key = iwl_mac_update_tkip_key, | |
5b9f8cd3 EG |
3901 | .conf_tx = iwl_mac_conf_tx, |
3902 | .reset_tsf = iwl_mac_reset_tsf, | |
3903 | .bss_info_changed = iwl_bss_info_changed, | |
3904 | .ampdu_action = iwl_mac_ampdu_action, | |
6ab10ff8 JB |
3905 | .hw_scan = iwl_mac_hw_scan, |
3906 | .sta_notify = iwl_mac_sta_notify, | |
fe6b23dd RC |
3907 | .sta_add = iwlagn_mac_sta_add, |
3908 | .sta_remove = iwl_mac_sta_remove, | |
79d07325 | 3909 | .channel_switch = iwl_mac_channel_switch, |
716c74b0 | 3910 | .flush = iwl_mac_flush, |
b481de9c ZY |
3911 | }; |
3912 | ||
5b9f8cd3 | 3913 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3914 | { |
3915 | int err = 0; | |
c79dd5b5 | 3916 | struct iwl_priv *priv; |
b481de9c | 3917 | struct ieee80211_hw *hw; |
82b9a121 | 3918 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 3919 | unsigned long flags; |
6cd0b1cb | 3920 | u16 pci_cmd; |
30eabc17 | 3921 | u8 perm_addr[ETH_ALEN]; |
b481de9c | 3922 | |
316c30d9 AK |
3923 | /************************ |
3924 | * 1. Allocating HW data | |
3925 | ************************/ | |
3926 | ||
6440adb5 BC |
3927 | /* Disabling hardware scan means that mac80211 will perform scans |
3928 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 3929 | if (cfg->mod_params->disable_hw_scan) { |
a562a9dd | 3930 | if (iwl_debug_level & IWL_DL_INFO) |
bf403db8 EK |
3931 | dev_printk(KERN_DEBUG, &(pdev->dev), |
3932 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 3933 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
3934 | } |
3935 | ||
5b9f8cd3 | 3936 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 3937 | if (!hw) { |
b481de9c ZY |
3938 | err = -ENOMEM; |
3939 | goto out; | |
3940 | } | |
1d0a082d AK |
3941 | priv = hw->priv; |
3942 | /* At this point both hw and priv are allocated. */ | |
3943 | ||
b481de9c ZY |
3944 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3945 | ||
e1623446 | 3946 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 3947 | priv->cfg = cfg; |
b481de9c | 3948 | priv->pci_dev = pdev; |
40cefda9 | 3949 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 3950 | |
20594eb0 WYG |
3951 | if (iwl_alloc_traffic_mem(priv)) |
3952 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3953 | |
316c30d9 AK |
3954 | /************************** |
3955 | * 2. Initializing PCI bus | |
3956 | **************************/ | |
3957 | if (pci_enable_device(pdev)) { | |
3958 | err = -ENODEV; | |
3959 | goto out_ieee80211_free_hw; | |
3960 | } | |
3961 | ||
3962 | pci_set_master(pdev); | |
3963 | ||
093d874c | 3964 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 3965 | if (!err) |
093d874c | 3966 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 3967 | if (err) { |
093d874c | 3968 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3969 | if (!err) |
093d874c | 3970 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3971 | /* both attempts failed: */ |
316c30d9 | 3972 | if (err) { |
978785a3 | 3973 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 3974 | goto out_pci_disable_device; |
cc2a8ea8 | 3975 | } |
316c30d9 AK |
3976 | } |
3977 | ||
3978 | err = pci_request_regions(pdev, DRV_NAME); | |
3979 | if (err) | |
3980 | goto out_pci_disable_device; | |
3981 | ||
3982 | pci_set_drvdata(pdev, priv); | |
3983 | ||
316c30d9 AK |
3984 | |
3985 | /*********************** | |
3986 | * 3. Read REV register | |
3987 | ***********************/ | |
3988 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3989 | if (!priv->hw_base) { | |
3990 | err = -ENODEV; | |
3991 | goto out_pci_release_regions; | |
3992 | } | |
3993 | ||
e1623446 | 3994 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 3995 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3996 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 3997 | |
731a29b7 | 3998 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
3999 | * we should init now |
4000 | */ | |
4001 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 4002 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
4003 | |
4004 | /* | |
4005 | * stop and reset the on-board processor just in case it is in a | |
4006 | * strange state ... like being left stranded by a primary kernel | |
4007 | * and this is now the kdump kernel trying to start up | |
4008 | */ | |
4009 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
4010 | ||
b661c819 | 4011 | iwl_hw_detect(priv); |
c11362c0 | 4012 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
b661c819 | 4013 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 4014 | |
e7b63581 TW |
4015 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4016 | * PCI Tx retries from interfering with C3 CPU state */ | |
4017 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
4018 | ||
086ed117 MA |
4019 | iwl_prepare_card_hw(priv); |
4020 | if (!priv->hw_ready) { | |
4021 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
4022 | goto out_iounmap; | |
4023 | } | |
4024 | ||
91238714 TW |
4025 | /***************** |
4026 | * 4. Read EEPROM | |
4027 | *****************/ | |
316c30d9 AK |
4028 | /* Read the EEPROM */ |
4029 | err = iwl_eeprom_init(priv); | |
4030 | if (err) { | |
15b1687c | 4031 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
4032 | goto out_iounmap; |
4033 | } | |
8614f360 TW |
4034 | err = iwl_eeprom_check_version(priv); |
4035 | if (err) | |
c8f16138 | 4036 | goto out_free_eeprom; |
8614f360 | 4037 | |
02883017 | 4038 | /* extract MAC Address */ |
30eabc17 JB |
4039 | iwl_eeprom_get_mac(priv, perm_addr); |
4040 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", perm_addr); | |
4041 | SET_IEEE80211_PERM_ADDR(priv->hw, perm_addr); | |
316c30d9 AK |
4042 | |
4043 | /************************ | |
4044 | * 5. Setup HW constants | |
4045 | ************************/ | |
da154e30 | 4046 | if (iwl_set_hw_params(priv)) { |
15b1687c | 4047 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 4048 | goto out_free_eeprom; |
316c30d9 AK |
4049 | } |
4050 | ||
4051 | /******************* | |
6ba87956 | 4052 | * 6. Setup priv |
316c30d9 | 4053 | *******************/ |
b481de9c | 4054 | |
6ba87956 | 4055 | err = iwl_init_drv(priv); |
bf85ea4f | 4056 | if (err) |
399f4900 | 4057 | goto out_free_eeprom; |
bf85ea4f | 4058 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 4059 | |
316c30d9 | 4060 | /******************** |
09f9bf79 | 4061 | * 7. Setup services |
316c30d9 | 4062 | ********************/ |
0359facc | 4063 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 4064 | iwl_disable_interrupts(priv); |
0359facc | 4065 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 4066 | |
6cd0b1cb HS |
4067 | pci_enable_msi(priv->pci_dev); |
4068 | ||
ef850d7c MA |
4069 | iwl_alloc_isr_ict(priv); |
4070 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
4071 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
4072 | if (err) { |
4073 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4074 | goto out_disable_msi; | |
4075 | } | |
316c30d9 | 4076 | |
4e39317d | 4077 | iwl_setup_deferred_work(priv); |
653fa4a0 | 4078 | iwl_setup_rx_handlers(priv); |
316c30d9 | 4079 | |
158bea07 JB |
4080 | /********************************************* |
4081 | * 8. Enable interrupts and read RFKILL state | |
4082 | *********************************************/ | |
6ba87956 | 4083 | |
6cd0b1cb HS |
4084 | /* enable interrupts if needed: hw bug w/a */ |
4085 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
4086 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
4087 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
4088 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
4089 | } | |
4090 | ||
4091 | iwl_enable_interrupts(priv); | |
4092 | ||
6cd0b1cb HS |
4093 | /* If platform's RF_KILL switch is NOT set to KILL */ |
4094 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
4095 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
4096 | else | |
4097 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 4098 | |
a60e77e5 JB |
4099 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
4100 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 4101 | |
58d0f361 | 4102 | iwl_power_initialize(priv); |
39b73fb1 | 4103 | iwl_tt_initialize(priv); |
158bea07 | 4104 | |
a15707d8 | 4105 | init_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 4106 | |
b08dfd04 | 4107 | err = iwl_request_firmware(priv, true); |
158bea07 | 4108 | if (err) |
7d47618a | 4109 | goto out_destroy_workqueue; |
158bea07 | 4110 | |
b481de9c ZY |
4111 | return 0; |
4112 | ||
7d47618a | 4113 | out_destroy_workqueue: |
c8f16138 RC |
4114 | destroy_workqueue(priv->workqueue); |
4115 | priv->workqueue = NULL; | |
795cc0ad | 4116 | free_irq(priv->pci_dev->irq, priv); |
ef850d7c | 4117 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
4118 | out_disable_msi: |
4119 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 4120 | iwl_uninit_drv(priv); |
073d3f5f TW |
4121 | out_free_eeprom: |
4122 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4123 | out_iounmap: |
4124 | pci_iounmap(pdev, priv->hw_base); | |
4125 | out_pci_release_regions: | |
316c30d9 | 4126 | pci_set_drvdata(pdev, NULL); |
623d563e | 4127 | pci_release_regions(pdev); |
b481de9c ZY |
4128 | out_pci_disable_device: |
4129 | pci_disable_device(pdev); | |
b481de9c | 4130 | out_ieee80211_free_hw: |
20594eb0 | 4131 | iwl_free_traffic_mem(priv); |
d7c76f4c | 4132 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
4133 | out: |
4134 | return err; | |
4135 | } | |
4136 | ||
5b9f8cd3 | 4137 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 4138 | { |
c79dd5b5 | 4139 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4140 | unsigned long flags; |
b481de9c ZY |
4141 | |
4142 | if (!priv) | |
4143 | return; | |
4144 | ||
a15707d8 | 4145 | wait_for_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 4146 | |
e1623446 | 4147 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4148 | |
67249625 | 4149 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 4150 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 4151 | |
5b9f8cd3 EG |
4152 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
4153 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
4154 | * we need to set STATUS_EXIT_PENDING bit. |
4155 | */ | |
4156 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
4157 | if (priv->mac80211_registered) { |
4158 | ieee80211_unregister_hw(priv->hw); | |
4159 | priv->mac80211_registered = 0; | |
0b124c31 | 4160 | } else { |
5b9f8cd3 | 4161 | iwl_down(priv); |
c4f55232 RR |
4162 | } |
4163 | ||
c166b25a BC |
4164 | /* |
4165 | * Make sure device is reset to low power before unloading driver. | |
4166 | * This may be redundant with iwl_down(), but there are paths to | |
4167 | * run iwl_down() without calling apm_ops.stop(), and there are | |
4168 | * paths to avoid running iwl_down() at all before leaving driver. | |
4169 | * This (inexpensive) call *makes sure* device is reset. | |
4170 | */ | |
4171 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
4172 | ||
39b73fb1 WYG |
4173 | iwl_tt_exit(priv); |
4174 | ||
0359facc MA |
4175 | /* make sure we flush any pending irq or |
4176 | * tasklet for the driver | |
4177 | */ | |
4178 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 4179 | iwl_disable_interrupts(priv); |
0359facc MA |
4180 | spin_unlock_irqrestore(&priv->lock, flags); |
4181 | ||
4182 | iwl_synchronize_irq(priv); | |
4183 | ||
5b9f8cd3 | 4184 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
4185 | |
4186 | if (priv->rxq.bd) | |
54b81550 | 4187 | iwlagn_rx_queue_free(priv, &priv->rxq); |
74bcdb33 | 4188 | iwlagn_hw_txq_ctx_free(priv); |
b481de9c | 4189 | |
073d3f5f | 4190 | iwl_eeprom_free(priv); |
b481de9c | 4191 | |
b481de9c | 4192 | |
948c171c MA |
4193 | /*netif_stop_queue(dev); */ |
4194 | flush_workqueue(priv->workqueue); | |
4195 | ||
5b9f8cd3 | 4196 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
4197 | * priv->workqueue... so we can't take down the workqueue |
4198 | * until now... */ | |
4199 | destroy_workqueue(priv->workqueue); | |
4200 | priv->workqueue = NULL; | |
20594eb0 | 4201 | iwl_free_traffic_mem(priv); |
b481de9c | 4202 | |
6cd0b1cb HS |
4203 | free_irq(priv->pci_dev->irq, priv); |
4204 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
4205 | pci_iounmap(pdev, priv->hw_base); |
4206 | pci_release_regions(pdev); | |
4207 | pci_disable_device(pdev); | |
4208 | pci_set_drvdata(pdev, NULL); | |
4209 | ||
6ba87956 | 4210 | iwl_uninit_drv(priv); |
b481de9c | 4211 | |
ef850d7c MA |
4212 | iwl_free_isr_ict(priv); |
4213 | ||
b481de9c ZY |
4214 | if (priv->ibss_beacon) |
4215 | dev_kfree_skb(priv->ibss_beacon); | |
4216 | ||
4217 | ieee80211_free_hw(priv->hw); | |
4218 | } | |
4219 | ||
b481de9c ZY |
4220 | |
4221 | /***************************************************************************** | |
4222 | * | |
4223 | * driver and module entry point | |
4224 | * | |
4225 | *****************************************************************************/ | |
4226 | ||
fed9017e | 4227 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
a3aa1884 | 4228 | static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = { |
4fc22b21 | 4229 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
4230 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
4231 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 4232 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 4233 | #ifdef CONFIG_IWL5000 |
ac592574 WYG |
4234 | /* 5100 Series WiFi */ |
4235 | {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ | |
4236 | {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4237 | {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ | |
4238 | {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4239 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4240 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4241 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ | |
4242 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4243 | {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */ | |
4244 | {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4245 | {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */ | |
4246 | {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4247 | {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4248 | {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4249 | {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */ | |
4250 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4251 | {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */ | |
4252 | {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4253 | {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */ | |
4254 | {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4255 | {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4256 | {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4257 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */ | |
4258 | {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4259 | ||
4260 | /* 5300 Series WiFi */ | |
4261 | {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */ | |
4262 | {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4263 | {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */ | |
4264 | {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4265 | {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */ | |
4266 | {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4267 | {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */ | |
4268 | {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4269 | {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */ | |
4270 | {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4271 | {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */ | |
4272 | {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4273 | ||
4274 | /* 5350 Series WiFi/WiMax */ | |
4275 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */ | |
4276 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */ | |
4277 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */ | |
4278 | ||
4279 | /* 5150 Series Wifi/WiMax */ | |
4280 | {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */ | |
4281 | {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4282 | {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */ | |
4283 | {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
4284 | {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */ | |
4285 | {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4286 | ||
4287 | {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */ | |
4288 | {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4289 | {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */ | |
4290 | {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
5953a62e WYG |
4291 | |
4292 | /* 6x00 Series */ | |
5953a62e WYG |
4293 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, |
4294 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
4295 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
4296 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
4297 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
4298 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
4299 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
4300 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
4301 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
4302 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
4b3e8062 | 4303 | |
95b13014 SZ |
4304 | /* 6x00 Series Gen2a */ |
4305 | {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)}, | |
4306 | {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)}, | |
4307 | {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)}, | |
1808972f SZ |
4308 | {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)}, |
4309 | {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)}, | |
4310 | {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)}, | |
4311 | {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)}, | |
9f6e1baf SZ |
4312 | {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)}, |
4313 | {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)}, | |
4314 | {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)}, | |
4315 | {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)}, | |
4316 | {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)}, | |
4317 | {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)}, | |
4318 | {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)}, | |
1808972f SZ |
4319 | |
4320 | /* 6x00 Series Gen2b */ | |
4321 | {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)}, | |
4322 | {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)}, | |
4323 | {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)}, | |
4324 | {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)}, | |
4325 | {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)}, | |
4326 | {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)}, | |
4327 | {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)}, | |
4328 | {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)}, | |
4329 | {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)}, | |
4330 | {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)}, | |
4331 | {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)}, | |
9f6e1baf SZ |
4332 | {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)}, |
4333 | {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)}, | |
4334 | {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)}, | |
4335 | {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)}, | |
4336 | {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)}, | |
4337 | {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)}, | |
4338 | {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)}, | |
4339 | {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)}, | |
4340 | {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)}, | |
4341 | {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)}, | |
4342 | {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)}, | |
4343 | {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)}, | |
4344 | {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)}, | |
4345 | {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)}, | |
4346 | {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)}, | |
4347 | {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)}, | |
4348 | {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)}, | |
5953a62e WYG |
4349 | |
4350 | /* 6x50 WiFi/WiMax Series */ | |
5953a62e WYG |
4351 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, |
4352 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
4353 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
4354 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
5953a62e WYG |
4355 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, |
4356 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
4357 | ||
03264339 SZ |
4358 | /* 6x50 WiFi/WiMax Series Gen2 */ |
4359 | {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)}, | |
4360 | {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)}, | |
4361 | {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)}, | |
4362 | {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)}, | |
4363 | {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)}, | |
4364 | {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)}, | |
4365 | ||
77dcb6a9 | 4366 | /* 1000 Series WiFi */ |
4bd0914f WYG |
4367 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
4368 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
4369 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
4370 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
4371 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
4372 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
4373 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
4374 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
4375 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
4376 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
4377 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
4378 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
5a6a256e | 4379 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 4380 | |
fed9017e RR |
4381 | {0} |
4382 | }; | |
4383 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
4384 | ||
4385 | static struct pci_driver iwl_driver = { | |
b481de9c | 4386 | .name = DRV_NAME, |
fed9017e | 4387 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
4388 | .probe = iwl_pci_probe, |
4389 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 4390 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
4391 | .suspend = iwl_pci_suspend, |
4392 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4393 | #endif |
4394 | }; | |
4395 | ||
5b9f8cd3 | 4396 | static int __init iwl_init(void) |
b481de9c ZY |
4397 | { |
4398 | ||
4399 | int ret; | |
4400 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
4401 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 4402 | |
e227ceac | 4403 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 4404 | if (ret) { |
a3139c59 SO |
4405 | printk(KERN_ERR DRV_NAME |
4406 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
4407 | return ret; |
4408 | } | |
4409 | ||
fed9017e | 4410 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 4411 | if (ret) { |
a3139c59 | 4412 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 4413 | goto error_register; |
b481de9c | 4414 | } |
b481de9c ZY |
4415 | |
4416 | return ret; | |
897e1cf2 | 4417 | |
897e1cf2 | 4418 | error_register: |
e227ceac | 4419 | iwlagn_rate_control_unregister(); |
897e1cf2 | 4420 | return ret; |
b481de9c ZY |
4421 | } |
4422 | ||
5b9f8cd3 | 4423 | static void __exit iwl_exit(void) |
b481de9c | 4424 | { |
fed9017e | 4425 | pci_unregister_driver(&iwl_driver); |
e227ceac | 4426 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
4427 | } |
4428 | ||
5b9f8cd3 EG |
4429 | module_exit(iwl_exit); |
4430 | module_init(iwl_init); | |
a562a9dd RC |
4431 | |
4432 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 4433 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); |
a562a9dd | 4434 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); |
4e30cb69 | 4435 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
4436 | MODULE_PARM_DESC(debug, "debug output mask"); |
4437 | #endif | |
4438 | ||
2b068618 WYG |
4439 | module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO); |
4440 | MODULE_PARM_DESC(swcrypto50, | |
4441 | "using crypto in software (default 0 [hardware]) (deprecated)"); | |
4442 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); | |
4443 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | |
4444 | module_param_named(queues_num50, | |
4445 | iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
4446 | MODULE_PARM_DESC(queues_num50, | |
4447 | "number of hw queues in 50xx series (deprecated)"); | |
4448 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
4449 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
4450 | module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
4451 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)"); | |
4452 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
4453 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
4454 | module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K, | |
4455 | int, S_IRUGO); | |
4456 | MODULE_PARM_DESC(amsdu_size_8K50, | |
4457 | "enable 8K amsdu size in 50XX series (deprecated)"); | |
4458 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, | |
4459 | int, S_IRUGO); | |
4460 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
4461 | module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
4462 | MODULE_PARM_DESC(fw_restart50, | |
4463 | "restart firmware in case of error (deprecated)"); | |
4464 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
4465 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | |
4466 | module_param_named( | |
4467 | disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO); | |
4468 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); | |
dd7a2509 JB |
4469 | |
4470 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | |
4471 | S_IRUGO); | |
4472 | MODULE_PARM_DESC(ucode_alternative, | |
4473 | "specify ucode alternative to use from ucode file"); |