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mac80211: use hardware flags for signal/noise units
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df48c323 1/******************************************************************************
df48c323
TW
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/version.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
712b6cf5 34struct iwl_priv; /* FIXME: remove */
0a6857e7 35#include "iwl-debug.h"
6bc913bd 36#include "iwl-eeprom.h"
3e0d4cb1 37#include "iwl-dev.h" /* FIXME: remove */
df48c323 38#include "iwl-core.h"
b661c819 39#include "iwl-io.h"
ad97edd2 40#include "iwl-rfkill.h"
5da4b55f 41#include "iwl-power.h"
df48c323 42
1d0a082d 43
df48c323
TW
44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
46MODULE_AUTHOR(DRV_COPYRIGHT);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR
49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
62/*
63 * Parameter order:
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 *
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
68 *
69 */
70const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
71 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
85};
86EXPORT_SYMBOL(iwl4965_rates);
87
1d0a082d
AK
88/* This function both allocates and initializes hw and priv. */
89struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
90 struct ieee80211_ops *hw_ops)
91{
92 struct iwl_priv *priv;
93
94 /* mac80211 allocates memory for this device instance, including
95 * space for this driver's private structure */
96 struct ieee80211_hw *hw =
97 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
98 if (hw == NULL) {
99 IWL_ERROR("Can not allocate network device\n");
100 goto out;
101 }
102
103 priv = hw->priv;
104 priv->hw = hw;
105
106out:
107 return hw;
108}
109EXPORT_SYMBOL(iwl_alloc_all);
110
b661c819
TW
111void iwl_hw_detect(struct iwl_priv *priv)
112{
113 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
114 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
115 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
116}
117EXPORT_SYMBOL(iwl_hw_detect);
118
1053d35f
RR
119/* Tell nic where to find the "keep warm" buffer */
120int iwl_kw_init(struct iwl_priv *priv)
121{
122 unsigned long flags;
123 int ret;
124
125 spin_lock_irqsave(&priv->lock, flags);
126 ret = iwl_grab_nic_access(priv);
127 if (ret)
128 goto out;
129
130 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
131 priv->kw.dma_addr >> 4);
132 iwl_release_nic_access(priv);
133out:
134 spin_unlock_irqrestore(&priv->lock, flags);
135 return ret;
136}
137
138int iwl_kw_alloc(struct iwl_priv *priv)
139{
140 struct pci_dev *dev = priv->pci_dev;
16466903 141 struct iwl_kw *kw = &priv->kw;
1053d35f 142
16466903 143 kw->size = IWL_KW_SIZE;
1053d35f
RR
144 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
145 if (!kw->v_addr)
146 return -ENOMEM;
147
148 return 0;
149}
150
151/**
152 * iwl_kw_free - Free the "keep warm" buffer
153 */
154void iwl_kw_free(struct iwl_priv *priv)
155{
156 struct pci_dev *dev = priv->pci_dev;
16466903 157 struct iwl_kw *kw = &priv->kw;
1053d35f
RR
158
159 if (kw->v_addr) {
160 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
161 memset(kw, 0, sizeof(*kw));
162 }
163}
164
165int iwl_hw_nic_init(struct iwl_priv *priv)
166{
167 unsigned long flags;
168 struct iwl_rx_queue *rxq = &priv->rxq;
169 int ret;
170
171 /* nic_init */
1053d35f 172 spin_lock_irqsave(&priv->lock, flags);
1b73af82 173 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR
174 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
175 spin_unlock_irqrestore(&priv->lock, flags);
176
177 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
178
179 priv->cfg->ops->lib->apm_ops.config(priv);
180
181 /* Allocate the RX queue, or reset if it is already allocated */
182 if (!rxq->bd) {
183 ret = iwl_rx_queue_alloc(priv);
184 if (ret) {
185 IWL_ERROR("Unable to initialize Rx queue\n");
186 return -ENOMEM;
187 }
188 } else
189 iwl_rx_queue_reset(priv, rxq);
190
191 iwl_rx_replenish(priv);
192
193 iwl_rx_init(priv, rxq);
194
195 spin_lock_irqsave(&priv->lock, flags);
196
197 rxq->need_update = 1;
198 iwl_rx_queue_update_write_ptr(priv, rxq);
199
200 spin_unlock_irqrestore(&priv->lock, flags);
201
202 /* Allocate and init all Tx and Command queues */
203 ret = iwl_txq_ctx_reset(priv);
204 if (ret)
205 return ret;
206
207 set_bit(STATUS_INIT, &priv->status);
208
209 return 0;
210}
211EXPORT_SYMBOL(iwl_hw_nic_init);
212
bf85ea4f
AK
213/**
214 * iwlcore_clear_stations_table - Clear the driver's station table
215 *
216 * NOTE: This does not clear or otherwise alter the device's station table.
217 */
218void iwlcore_clear_stations_table(struct iwl_priv *priv)
219{
220 unsigned long flags;
221
222 spin_lock_irqsave(&priv->sta_lock, flags);
223
224 priv->num_stations = 0;
225 memset(priv->stations, 0, sizeof(priv->stations));
226
227 spin_unlock_irqrestore(&priv->sta_lock, flags);
228}
229EXPORT_SYMBOL(iwlcore_clear_stations_table);
230
c7de35cd 231void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK
232{
233 u16 cw_min = 15;
234 u16 cw_max = 1023;
235 u8 aifs = 2;
236 u8 is_legacy = 0;
237 unsigned long flags;
238 int i;
239
240 spin_lock_irqsave(&priv->lock, flags);
241 priv->qos_data.qos_active = 0;
242
243 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
244 if (priv->qos_data.qos_enable)
245 priv->qos_data.qos_active = 1;
246 if (!(priv->active_rate & 0xfff0)) {
247 cw_min = 31;
248 is_legacy = 1;
249 }
250 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
251 if (priv->qos_data.qos_enable)
252 priv->qos_data.qos_active = 1;
253 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
254 cw_min = 31;
255 is_legacy = 1;
256 }
257
258 if (priv->qos_data.qos_active)
259 aifs = 3;
260
261 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
262 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
263 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
264 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
265 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
266
267 if (priv->qos_data.qos_active) {
268 i = 1;
269 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
270 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
271 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
272 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
273 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
274
275 i = 2;
276 priv->qos_data.def_qos_parm.ac[i].cw_min =
277 cpu_to_le16((cw_min + 1) / 2 - 1);
278 priv->qos_data.def_qos_parm.ac[i].cw_max =
279 cpu_to_le16(cw_max);
280 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
281 if (is_legacy)
282 priv->qos_data.def_qos_parm.ac[i].edca_txop =
283 cpu_to_le16(6016);
284 else
285 priv->qos_data.def_qos_parm.ac[i].edca_txop =
286 cpu_to_le16(3008);
287 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
288
289 i = 3;
290 priv->qos_data.def_qos_parm.ac[i].cw_min =
291 cpu_to_le16((cw_min + 1) / 4 - 1);
292 priv->qos_data.def_qos_parm.ac[i].cw_max =
293 cpu_to_le16((cw_max + 1) / 2 - 1);
294 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
295 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
296 if (is_legacy)
297 priv->qos_data.def_qos_parm.ac[i].edca_txop =
298 cpu_to_le16(3264);
299 else
300 priv->qos_data.def_qos_parm.ac[i].edca_txop =
301 cpu_to_le16(1504);
302 } else {
303 for (i = 1; i < 4; i++) {
304 priv->qos_data.def_qos_parm.ac[i].cw_min =
305 cpu_to_le16(cw_min);
306 priv->qos_data.def_qos_parm.ac[i].cw_max =
307 cpu_to_le16(cw_max);
308 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
309 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
310 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
311 }
312 }
313 IWL_DEBUG_QOS("set QoS to default \n");
314
315 spin_unlock_irqrestore(&priv->lock, flags);
316}
c7de35cd
RR
317EXPORT_SYMBOL(iwl_reset_qos);
318
319#ifdef CONFIG_IWL4965_HT
320static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
321 struct ieee80211_ht_info *ht_info,
322 enum ieee80211_band band)
323{
324 ht_info->cap = 0;
325 memset(ht_info->supp_mcs_set, 0, 16);
326
327 ht_info->ht_supported = 1;
328
329 if (priv->hw_params.fat_channel & BIT(band)) {
330 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
331 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
332 ht_info->supp_mcs_set[4] = 0x01;
333 }
334 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
335 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
336 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
337 (IWL_MIMO_PS_NONE << 2));
338
339 if (priv->cfg->mod_params->amsdu_size_8K)
340 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
341
342 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
343 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
344
345 ht_info->supp_mcs_set[0] = 0xFF;
346 if (priv->hw_params.tx_chains_num >= 2)
347 ht_info->supp_mcs_set[1] = 0xFF;
348 if (priv->hw_params.tx_chains_num >= 3)
349 ht_info->supp_mcs_set[2] = 0xFF;
350}
88787d28
AM
351#else
352static inline void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
353 struct ieee80211_ht_info *ht_info,
354 enum ieee80211_band band)
355{
356}
c7de35cd
RR
357#endif /* CONFIG_IWL4965_HT */
358
359static void iwlcore_init_hw_rates(struct iwl_priv *priv,
360 struct ieee80211_rate *rates)
361{
362 int i;
363
364 for (i = 0; i < IWL_RATE_COUNT; i++) {
365 rates[i].bitrate = iwl4965_rates[i].ieee * 5;
366 rates[i].hw_value = i; /* Rate scaling will work on indexes */
367 rates[i].hw_value_short = i;
368 rates[i].flags = 0;
369 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
370 /*
371 * If CCK != 1M then set short preamble rate flag.
372 */
373 rates[i].flags |=
374 (iwl4965_rates[i].plcp == IWL_RATE_1M_PLCP) ?
375 0 : IEEE80211_RATE_SHORT_PREAMBLE;
376 }
377 }
378}
379
380/**
381 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
382 */
383static int iwlcore_init_geos(struct iwl_priv *priv)
384{
385 struct iwl_channel_info *ch;
386 struct ieee80211_supported_band *sband;
387 struct ieee80211_channel *channels;
388 struct ieee80211_channel *geo_ch;
389 struct ieee80211_rate *rates;
390 int i = 0;
391
392 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
393 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
394 IWL_DEBUG_INFO("Geography modes already initialized.\n");
395 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
396 return 0;
397 }
398
399 channels = kzalloc(sizeof(struct ieee80211_channel) *
400 priv->channel_count, GFP_KERNEL);
401 if (!channels)
402 return -ENOMEM;
403
404 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
405 GFP_KERNEL);
406 if (!rates) {
407 kfree(channels);
408 return -ENOMEM;
409 }
410
411 /* 5.2GHz channels start after the 2.4GHz channels */
412 sband = &priv->bands[IEEE80211_BAND_5GHZ];
413 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
414 /* just OFDM */
415 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
416 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
417
418 iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
419
420 sband = &priv->bands[IEEE80211_BAND_2GHZ];
421 sband->channels = channels;
422 /* OFDM & CCK */
423 sband->bitrates = rates;
424 sband->n_bitrates = IWL_RATE_COUNT;
425
426 iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
427
428 priv->ieee_channels = channels;
429 priv->ieee_rates = rates;
430
431 iwlcore_init_hw_rates(priv, rates);
432
433 for (i = 0; i < priv->channel_count; i++) {
434 ch = &priv->channel_info[i];
435
436 /* FIXME: might be removed if scan is OK */
437 if (!is_channel_valid(ch))
438 continue;
439
440 if (is_channel_a_band(ch))
441 sband = &priv->bands[IEEE80211_BAND_5GHZ];
442 else
443 sband = &priv->bands[IEEE80211_BAND_2GHZ];
444
445 geo_ch = &sband->channels[sband->n_channels++];
446
447 geo_ch->center_freq =
448 ieee80211_channel_to_frequency(ch->channel);
449 geo_ch->max_power = ch->max_power_avg;
450 geo_ch->max_antenna_gain = 0xff;
451 geo_ch->hw_value = ch->channel;
452
453 if (is_channel_valid(ch)) {
454 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
455 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
456
457 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
458 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
459
460 if (ch->flags & EEPROM_CHANNEL_RADAR)
461 geo_ch->flags |= IEEE80211_CHAN_RADAR;
462
463 if (ch->max_power_avg > priv->max_channel_txpower_limit)
464 priv->max_channel_txpower_limit =
465 ch->max_power_avg;
466 } else {
467 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
468 }
469
470 /* Save flags for reg domain usage */
471 geo_ch->orig_flags = geo_ch->flags;
472
473 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
474 ch->channel, geo_ch->center_freq,
475 is_channel_a_band(ch) ? "5.2" : "2.4",
476 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
477 "restricted" : "valid",
478 geo_ch->flags);
479 }
480
481 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
482 priv->cfg->sku & IWL_SKU_A) {
483 printk(KERN_INFO DRV_NAME
484 ": Incorrectly detected BG card as ABG. Please send "
485 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
486 priv->pci_dev->device, priv->pci_dev->subsystem_device);
487 priv->cfg->sku &= ~IWL_SKU_A;
488 }
489
490 printk(KERN_INFO DRV_NAME
491 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
492 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
493 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
494
495 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
496 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
497 &priv->bands[IEEE80211_BAND_2GHZ];
498 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
499 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
500 &priv->bands[IEEE80211_BAND_5GHZ];
501
502 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
503
504 return 0;
505}
506
507/*
508 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
509 */
510void iwlcore_free_geos(struct iwl_priv *priv)
511{
512 kfree(priv->ieee_channels);
513 kfree(priv->ieee_rates);
514 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
515}
516EXPORT_SYMBOL(iwlcore_free_geos);
517
518#ifdef CONFIG_IWL4965_HT
519static u8 is_single_rx_stream(struct iwl_priv *priv)
520{
521 return !priv->current_ht_config.is_ht ||
522 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
523 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
524 priv->ps_mode == IWL_MIMO_PS_STATIC;
525}
47c5196e
TW
526static u8 iwl_is_channel_extension(struct iwl_priv *priv,
527 enum ieee80211_band band,
528 u16 channel, u8 extension_chan_offset)
529{
530 const struct iwl_channel_info *ch_info;
531
532 ch_info = iwl_get_channel_info(priv, band, channel);
533 if (!is_channel_valid(ch_info))
534 return 0;
535
536 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
537 return 0;
538
539 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
540 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
541 return 1;
542
543 return 0;
544}
545
546u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
547 struct ieee80211_ht_info *sta_ht_inf)
548{
549 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
550
551 if ((!iwl_ht_conf->is_ht) ||
552 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
553 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
554 return 0;
555
556 if (sta_ht_inf) {
557 if ((!sta_ht_inf->ht_supported) ||
558 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
559 return 0;
560 }
561
562 return iwl_is_channel_extension(priv, priv->band,
563 iwl_ht_conf->control_channel,
564 iwl_ht_conf->extension_chan_offset);
565}
566EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
567
568void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
569{
570 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
571 u32 val;
572
573 if (!ht_info->is_ht)
574 return;
575
576 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
577 if (iwl_is_fat_tx_allowed(priv, NULL))
578 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
579 else
580 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
581 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
582
583 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
584 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
585 le16_to_cpu(rxon->channel),
586 ht_info->control_channel);
587 rxon->channel = cpu_to_le16(ht_info->control_channel);
588 return;
589 }
590
591 /* Note: control channel is opposite of extension channel */
592 switch (ht_info->extension_chan_offset) {
593 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
594 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
595 break;
596 case IWL_EXT_CHANNEL_OFFSET_BELOW:
597 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
598 break;
599 case IWL_EXT_CHANNEL_OFFSET_NONE:
600 default:
601 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
602 break;
603 }
604
605 val = ht_info->ht_protection;
606
607 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
608
609 iwl_set_rxon_chain(priv);
610
611 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
612 "rxon flags 0x%X operation mode :0x%X "
613 "extension channel offset 0x%x "
614 "control chan %d\n",
615 ht_info->supp_mcs_set[0],
616 ht_info->supp_mcs_set[1],
617 ht_info->supp_mcs_set[2],
618 le32_to_cpu(rxon->flags), ht_info->ht_protection,
619 ht_info->extension_chan_offset,
620 ht_info->control_channel);
621 return;
622}
623EXPORT_SYMBOL(iwl_set_rxon_ht);
624
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625#else
626static inline u8 is_single_rx_stream(struct iwl_priv *priv)
627{
628 return 1;
629}
630#endif /*CONFIG_IWL4965_HT */
631
632/*
633 * Determine how many receiver/antenna chains to use.
634 * More provides better reception via diversity. Fewer saves power.
635 * MIMO (dual stream) requires at least 2, but works better with 3.
636 * This does not determine *which* chains to use, just how many.
637 */
638static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
639 u8 *idle_state, u8 *rx_state)
640{
641 u8 is_single = is_single_rx_stream(priv);
642 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
643
644 /* # of Rx chains to use when expecting MIMO. */
645 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
646 *rx_state = 2;
647 else
648 *rx_state = 3;
649
650 /* # Rx chains when idling and maybe trying to save power */
651 switch (priv->ps_mode) {
652 case IWL_MIMO_PS_STATIC:
653 case IWL_MIMO_PS_DYNAMIC:
654 *idle_state = (is_cam) ? 2 : 1;
655 break;
656 case IWL_MIMO_PS_NONE:
657 *idle_state = (is_cam) ? *rx_state : 1;
658 break;
659 default:
660 *idle_state = 1;
661 break;
662 }
663
664 return 0;
665}
666
667/**
668 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
669 *
670 * Selects how many and which Rx receivers/antennas/chains to use.
671 * This should not be used for scan command ... it puts data in wrong place.
672 */
673void iwl_set_rxon_chain(struct iwl_priv *priv)
674{
675 u8 is_single = is_single_rx_stream(priv);
676 u8 idle_state, rx_state;
677
678 priv->staging_rxon.rx_chain = 0;
679 rx_state = idle_state = 3;
680
681 /* Tell uCode which antennas are actually connected.
682 * Before first association, we assume all antennas are connected.
683 * Just after first association, iwl_chain_noise_calibration()
684 * checks which antennas actually *are* connected. */
685 priv->staging_rxon.rx_chain |=
686 cpu_to_le16(priv->hw_params.valid_rx_ant <<
687 RXON_RX_CHAIN_VALID_POS);
688
689 /* How many receivers should we use? */
690 iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
691 priv->staging_rxon.rx_chain |=
692 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
693 priv->staging_rxon.rx_chain |=
694 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
695
696 if (!is_single && (rx_state >= 2) &&
697 !test_bit(STATUS_POWER_PMI, &priv->status))
698 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
699 else
700 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
701
702 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
703}
704EXPORT_SYMBOL(iwl_set_rxon_chain);
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705
706/**
707 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
708 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
709 * @channel: Any channel valid for the requested phymode
710
711 * In addition to setting the staging RXON, priv->phymode is also set.
712 *
713 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
714 * in the staging RXON flag structure based on the phymode
715 */
c7de35cd 716int iwl_set_rxon_channel(struct iwl_priv *priv,
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717 enum ieee80211_band band,
718 u16 channel)
719{
8622e705 720 if (!iwl_get_channel_info(priv, band, channel)) {
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721 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
722 channel, band);
723 return -EINVAL;
724 }
725
726 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
727 (priv->band == band))
728 return 0;
729
730 priv->staging_rxon.channel = cpu_to_le16(channel);
731 if (band == IEEE80211_BAND_5GHZ)
732 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
733 else
734 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
735
736 priv->band = band;
737
738 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
739
740 return 0;
741}
c7de35cd 742EXPORT_SYMBOL(iwl_set_rxon_channel);
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743
744static void iwlcore_init_hw(struct iwl_priv *priv)
745{
746 struct ieee80211_hw *hw = priv->hw;
747 hw->rate_control_algorithm = "iwl-4965-rs";
748
566bfe5a
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749 /* Tell mac80211 our characteristics */
750 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
751 IEEE80211_HW_SIGNAL_DBM |
752 IEEE80211_HW_NOISE_DBM;
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753 /* Default value; 4 EDCA QOS priorities */
754 hw->queues = 4;
755#ifdef CONFIG_IWL4965_HT
756 /* Enhanced value; more queues, to support 11n aggregation */
e100bb64 757 hw->ampdu_queues = 12;
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758#endif /* CONFIG_IWL4965_HT */
759}
760
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761static int iwlcore_init_drv(struct iwl_priv *priv)
762{
763 int ret;
764 int i;
765
766 priv->retry_rate = 1;
767 priv->ibss_beacon = NULL;
768
769 spin_lock_init(&priv->lock);
770 spin_lock_init(&priv->power_data.lock);
771 spin_lock_init(&priv->sta_lock);
772 spin_lock_init(&priv->hcmd_lock);
773 spin_lock_init(&priv->lq_mngr.lock);
774
775 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
776 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
777
778 INIT_LIST_HEAD(&priv->free_frames);
779
780 mutex_init(&priv->mutex);
781
782 /* Clear the driver's (not device's) station table */
783 iwlcore_clear_stations_table(priv);
784
785 priv->data_retry_limit = -1;
786 priv->ieee_channels = NULL;
787 priv->ieee_rates = NULL;
788 priv->band = IEEE80211_BAND_2GHZ;
789
790 priv->iw_mode = IEEE80211_IF_TYPE_STA;
791
792 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
793 priv->ps_mode = IWL_MIMO_PS_NONE;
794
795 /* Choose which receivers/antennas to use */
796 iwl_set_rxon_chain(priv);
797
798 iwl_reset_qos(priv);
799
800 priv->qos_data.qos_active = 0;
801 priv->qos_data.qos_cap.val = 0;
802
803 iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
804
805 priv->rates_mask = IWL_RATES_MASK;
806 /* If power management is turned on, default to AC mode */
807 priv->power_mode = IWL_POWER_AC;
808 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
809
810 ret = iwl_init_channel_map(priv);
811 if (ret) {
812 IWL_ERROR("initializing regulatory failed: %d\n", ret);
813 goto err;
814 }
815
816 ret = iwlcore_init_geos(priv);
817 if (ret) {
818 IWL_ERROR("initializing geos failed: %d\n", ret);
819 goto err_free_channel_map;
820 }
821
822 ret = ieee80211_register_hw(priv->hw);
823 if (ret) {
824 IWL_ERROR("Failed to register network device (error %d)\n",
825 ret);
826 goto err_free_geos;
827 }
828
829 priv->hw->conf.beacon_int = 100;
830 priv->mac80211_registered = 1;
831
832 return 0;
833
834err_free_geos:
835 iwlcore_free_geos(priv);
836err_free_channel_map:
837 iwl_free_channel_map(priv);
838err:
839 return ret;
840}
841
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842int iwl_setup(struct iwl_priv *priv)
843{
844 int ret = 0;
845 iwlcore_init_hw(priv);
c7de35cd 846 ret = iwlcore_init_drv(priv);
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847 return ret;
848}
849EXPORT_SYMBOL(iwl_setup);
850
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851/* Low level driver call this function to update iwlcore with
852 * driver status.
853 */
854int iwlcore_low_level_notify(struct iwl_priv *priv,
855 enum iwlcore_card_notify notify)
856{
03d29c68 857 int ret;
c8381fdc
MA
858 switch (notify) {
859 case IWLCORE_INIT_EVT:
03d29c68
MA
860 ret = iwl_rfkill_init(priv);
861 if (ret)
862 IWL_ERROR("Unable to initialize RFKILL system. "
863 "Ignoring error: %d\n", ret);
5da4b55f 864 iwl_power_initialize(priv);
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865 break;
866 case IWLCORE_START_EVT:
5da4b55f 867 iwl_power_update_mode(priv, 1);
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868 break;
869 case IWLCORE_STOP_EVT:
870 break;
871 case IWLCORE_REMOVE_EVT:
ad97edd2 872 iwl_rfkill_unregister(priv);
c8381fdc
MA
873 break;
874 }
875
876 return 0;
877}
878EXPORT_SYMBOL(iwlcore_low_level_notify);
879
49ea8596
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880int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
881{
882 u32 stat_flags = 0;
883 struct iwl_host_cmd cmd = {
884 .id = REPLY_STATISTICS_CMD,
885 .meta.flags = flags,
886 .len = sizeof(stat_flags),
887 .data = (u8 *) &stat_flags,
888 };
889 return iwl_send_cmd(priv, &cmd);
890}
891EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 892
b0692f2f
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893/**
894 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
895 * using sample data 100 bytes apart. If these sample points are good,
896 * it's a pretty good bet that everything between them is good, too.
897 */
898static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
899{
900 u32 val;
901 int ret = 0;
902 u32 errcnt = 0;
903 u32 i;
904
905 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
906
907 ret = iwl_grab_nic_access(priv);
908 if (ret)
909 return ret;
910
911 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
912 /* read data comes through single port, auto-incr addr */
913 /* NOTE: Use the debugless read so we don't flood kernel log
914 * if IWL_DL_IO is set */
915 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
916 i + RTC_INST_LOWER_BOUND);
917 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
918 if (val != le32_to_cpu(*image)) {
919 ret = -EIO;
920 errcnt++;
921 if (errcnt >= 3)
922 break;
923 }
924 }
925
926 iwl_release_nic_access(priv);
927
928 return ret;
929}
930
931/**
932 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
933 * looking at all data.
934 */
935static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
936 u32 len)
937{
938 u32 val;
939 u32 save_len = len;
940 int ret = 0;
941 u32 errcnt;
942
943 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
944
945 ret = iwl_grab_nic_access(priv);
946 if (ret)
947 return ret;
948
949 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
950
951 errcnt = 0;
952 for (; len > 0; len -= sizeof(u32), image++) {
953 /* read data comes through single port, auto-incr addr */
954 /* NOTE: Use the debugless read so we don't flood kernel log
955 * if IWL_DL_IO is set */
956 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
957 if (val != le32_to_cpu(*image)) {
958 IWL_ERROR("uCode INST section is invalid at "
959 "offset 0x%x, is 0x%x, s/b 0x%x\n",
960 save_len - len, val, le32_to_cpu(*image));
961 ret = -EIO;
962 errcnt++;
963 if (errcnt >= 20)
964 break;
965 }
966 }
967
968 iwl_release_nic_access(priv);
969
970 if (!errcnt)
971 IWL_DEBUG_INFO
972 ("ucode image in INSTRUCTION memory is good\n");
973
974 return ret;
975}
976
977/**
978 * iwl_verify_ucode - determine which instruction image is in SRAM,
979 * and verify its contents
980 */
981int iwl_verify_ucode(struct iwl_priv *priv)
982{
983 __le32 *image;
984 u32 len;
985 int ret;
986
987 /* Try bootstrap */
988 image = (__le32 *)priv->ucode_boot.v_addr;
989 len = priv->ucode_boot.len;
990 ret = iwlcore_verify_inst_sparse(priv, image, len);
991 if (!ret) {
992 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
993 return 0;
994 }
995
996 /* Try initialize */
997 image = (__le32 *)priv->ucode_init.v_addr;
998 len = priv->ucode_init.len;
999 ret = iwlcore_verify_inst_sparse(priv, image, len);
1000 if (!ret) {
1001 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1002 return 0;
1003 }
1004
1005 /* Try runtime/protocol */
1006 image = (__le32 *)priv->ucode_code.v_addr;
1007 len = priv->ucode_code.len;
1008 ret = iwlcore_verify_inst_sparse(priv, image, len);
1009 if (!ret) {
1010 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1011 return 0;
1012 }
1013
1014 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1015
1016 /* Since nothing seems to match, show first several data entries in
1017 * instruction SRAM, so maybe visual inspection will give a clue.
1018 * Selection of bootstrap image (vs. other images) is arbitrary. */
1019 image = (__le32 *)priv->ucode_boot.v_addr;
1020 len = priv->ucode_boot.len;
1021 ret = iwl_verify_inst_full(priv, image, len);
1022
1023 return ret;
1024}
1025EXPORT_SYMBOL(iwl_verify_ucode);
1026