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iwlwifi: separate thermal throttling function
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CommitLineData
b481de9c
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-4965-hw.h"
45#include "iwl-3945-hw.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
0975cc8f 50#include "iwl-agn-tt.h"
5d08cd1d 51
672639de
WYG
52struct iwl_tx_queue;
53
099b40b7 54/* CT-KILL constants */
672639de
WYG
55#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
56#define CT_KILL_THRESHOLD 114 /* in Celsius */
57#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 58
5d08cd1d
CH
59/* Default noise level to report when noise measurement is not available.
60 * This may be because we're:
61 * 1) Not associated (4965, no beacon statistics being sent to driver)
62 * 2) Scanning (noise measurement does not apply to associated channel)
63 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
64 * Use default noise value of -127 ... this is below the range of measurable
65 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
66 * Also, -127 works better than 0 when averaging frames with/without
67 * noise info (e.g. averaging might be done in app); measured dBm values are
68 * always negative ... using a negative value as the default keeps all
69 * averages within an s8's (used in some apps) range of negative values. */
70#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
71
5d08cd1d
CH
72/*
73 * RTS threshold here is total size [2347] minus 4 FCS bytes
74 * Per spec:
75 * a value of 0 means RTS on all data/management packets
76 * a value > max MSDU size means no RTS
77 * else RTS for data/management frames where MPDU is larger
78 * than RTS value.
79 */
80#define DEFAULT_RTS_THRESHOLD 2347U
81#define MIN_RTS_THRESHOLD 0U
82#define MAX_RTS_THRESHOLD 2347U
83#define MAX_MSDU_SIZE 2304U
84#define MAX_MPDU_SIZE 2346U
85#define DEFAULT_BEACON_INTERVAL 100U
86#define DEFAULT_SHORT_RETRY_LIMIT 7U
87#define DEFAULT_LONG_RETRY_LIMIT 4U
88
a55360e4 89struct iwl_rx_mem_buffer {
2f301227
ZY
90 dma_addr_t page_dma;
91 struct page *page;
5d08cd1d
CH
92 struct list_head list;
93};
94
2f301227
ZY
95#define rxb_addr(r) page_address(r->page)
96
c2acea8e
JB
97/* defined below */
98struct iwl_device_cmd;
99
100struct iwl_cmd_meta {
101 /* only for SYNC commands, iff the reply skb is wanted */
102 struct iwl_host_cmd *source;
103 /*
104 * only for ASYNC commands
105 * (which is somewhat stupid -- look at iwl-sta.c for instance
106 * which duplicates a bunch of code because the callback isn't
107 * invoked for SYNC commands, if it were and its result passed
108 * through it would be simpler...)
109 */
5696aea6
JB
110 void (*callback)(struct iwl_priv *priv,
111 struct iwl_device_cmd *cmd,
2f301227 112 struct iwl_rx_packet *pkt);
c2acea8e
JB
113
114 /* The CMD_SIZE_HUGE flag bit indicates that the command
115 * structure is stored at the end of the shared queue memory. */
116 u32 flags;
117
2e724443
FT
118 DEFINE_DMA_UNMAP_ADDR(mapping);
119 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
120};
121
5d08cd1d
CH
122/*
123 * Generic queue structure
124 *
125 * Contains common data for Rx and Tx queues
126 */
443cfd45 127struct iwl_queue {
5d08cd1d
CH
128 int n_bd; /* number of BDs in this queue */
129 int write_ptr; /* 1-st empty entry (index) host_w*/
130 int read_ptr; /* last used entry (index) host_r*/
b74e31a9
WYG
131 /* use for monitoring and recovering the stuck queue */
132 int last_read_ptr; /* storing the last read_ptr */
133 /* number of time read_ptr and last_read_ptr are the same */
134 u8 repeat_same_read_ptr;
5d08cd1d
CH
135 dma_addr_t dma_addr; /* physical addr for BD's */
136 int n_window; /* safe queue window */
137 u32 id;
138 int low_mark; /* low watermark, resume queue if free
139 * space more than this */
140 int high_mark; /* high watermark, stop queue if free
141 * space less than this */
ba2d3587 142} __packed;
5d08cd1d 143
bc47279f 144/* One for each TFD */
8567c63e 145struct iwl_tx_info {
ff0d91c3 146 struct sk_buff *skb;
5d08cd1d
CH
147};
148
149/**
16466903 150 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
151 * @q: generic Rx/Tx queue descriptor
152 * @bd: base of circular buffer of TFDs
c2acea8e
JB
153 * @cmd: array of command/TX buffer pointers
154 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
155 * @dma_addr_cmd: physical address of cmd/tx buffer array
156 * @txb: array of per-TFD driver data
157 * @need_update: indicates need to update read/write index
158 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 159 *
bc47279f
BC
160 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
161 * descriptors) and required locking structures.
5d08cd1d 162 */
188cf6c7
SO
163#define TFD_TX_CMD_SLOTS 256
164#define TFD_CMD_SLOTS 32
165
16466903 166struct iwl_tx_queue {
443cfd45 167 struct iwl_queue q;
59606ffa 168 void *tfds;
c2acea8e
JB
169 struct iwl_device_cmd **cmd;
170 struct iwl_cmd_meta *meta;
8567c63e 171 struct iwl_tx_info *txb;
3fd07a1e
TW
172 u8 need_update;
173 u8 sched_retry;
174 u8 active;
175 u8 swq_id;
5d08cd1d
CH
176};
177
178#define IWL_NUM_SCAN_RATES (2)
179
bb8c093b 180struct iwl4965_channel_tgd_info {
5d08cd1d
CH
181 u8 type;
182 s8 max_power;
183};
184
bb8c093b 185struct iwl4965_channel_tgh_info {
5d08cd1d
CH
186 s64 last_radar_time;
187};
188
d20b3c65
SO
189#define IWL4965_MAX_RATE (33)
190
85d41495
KA
191struct iwl3945_clip_group {
192 /* maximum power level to prevent clipping for each rate, derived by
193 * us from this band's saturation power in EEPROM */
194 const s8 clip_powers[IWL_MAX_RATES];
195};
196
d20b3c65
SO
197/* current Tx power values to use, one for each rate for each channel.
198 * requested power is limited by:
199 * -- regulatory EEPROM limits for this channel
200 * -- hardware capabilities (clip-powers)
201 * -- spectrum management
202 * -- user preference (e.g. iwconfig)
203 * when requested power is set, base power index must also be set. */
204struct iwl3945_channel_power_info {
205 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
206 s8 power_table_index; /* actual (compenst'd) index into gain table */
207 s8 base_power_index; /* gain index for power at factory temp. */
208 s8 requested_power; /* power (dBm) requested for this chnl/rate */
209};
210
211/* current scan Tx power values to use, one for each scan rate for each
212 * channel. */
213struct iwl3945_scan_power_info {
214 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
215 s8 power_table_index; /* actual (compenst'd) index into gain table */
216 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
217};
218
5d08cd1d
CH
219/*
220 * One for each channel, holds all channel setup data
221 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
222 * with one another!
223 */
bf85ea4f 224struct iwl_channel_info {
bb8c093b
CH
225 struct iwl4965_channel_tgd_info tgd;
226 struct iwl4965_channel_tgh_info tgh;
073d3f5f 227 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
228 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
229 * HT40 channel */
5d08cd1d
CH
230
231 u8 channel; /* channel number */
232 u8 flags; /* flags copied from EEPROM */
233 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 234 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
235 s8 min_power; /* always 0 */
236 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
237
238 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
239 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 240 enum ieee80211_band band;
5d08cd1d 241
7aafef1c
WYG
242 /* HT40 channel info */
243 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
244 u8 ht40_flags; /* flags copied from EEPROM */
245 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
246
247 /* Radio/DSP gain settings for each "normal" data Tx rate.
248 * These include, in addition to RF and DSP gain, a few fields for
249 * remembering/modifying gain settings (indexes). */
250 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
251
252 /* Radio/DSP gain settings for each scan rate, for directed scans. */
253 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
254};
255
edc1a3a0
JB
256#define IWL_TX_FIFO_BK 0
257#define IWL_TX_FIFO_BE 1
258#define IWL_TX_FIFO_VI 2
259#define IWL_TX_FIFO_VO 3
260#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 261
01a7e084
RC
262/* Minimum number of queues. MAX_NUM is defined in hw specific files.
263 * Set the minimum to accommodate the 4 standard TX queues, 1 command
264 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
265#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 266
bd35f150 267/*
1a716557
JB
268 * Queue #4 is the command queue for 3945/4965/5x00/1000/6x00,
269 * the driver maps it into the appropriate device FIFO for the
270 * uCode.
bd35f150
WYG
271 */
272#define IWL_CMD_QUEUE_NUM 4
273
5d08cd1d
CH
274/* Power management (not Tx power) structures */
275
6f4083aa
TW
276enum iwl_pwr_src {
277 IWL_PWR_SRC_VMAIN,
278 IWL_PWR_SRC_VAUX,
279};
280
5d08cd1d
CH
281#define IEEE80211_DATA_LEN 2304
282#define IEEE80211_4ADDR_LEN 30
283#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
284#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
285
fcab423d 286struct iwl_frame {
5d08cd1d
CH
287 union {
288 struct ieee80211_hdr frame;
4bf64efd 289 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
290 u8 raw[IEEE80211_FRAME_LEN];
291 u8 cmd[360];
292 } u;
293 struct list_head list;
294};
295
5d08cd1d
CH
296#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
297#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
298#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
299
300enum {
c587de0b
TW
301 CMD_SYNC = 0,
302 CMD_SIZE_NORMAL = 0,
303 CMD_NO_SKB = 0,
5d08cd1d 304 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 305 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
306 CMD_WANT_SKB = (1 << 2),
307};
308
c8c24872 309#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 310
bc47279f 311/**
c2acea8e 312 * struct iwl_device_cmd
bc47279f
BC
313 *
314 * For allocation of the command and tx queues, this establishes the overall
315 * size of the largest command we send to uCode, except for a scan command
316 * (which is relatively huge; space is allocated separately).
317 */
c2acea8e 318struct iwl_device_cmd {
857485c0 319 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 320 union {
5d08cd1d
CH
321 u32 flags;
322 u8 val8;
323 u16 val16;
324 u32 val32;
83d527d9 325 struct iwl_tx_cmd tx;
c8c24872
WYG
326 struct iwl6000_channel_switch_cmd chswitch;
327 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
328 } __packed cmd;
329} __packed;
5d08cd1d 330
c2acea8e
JB
331#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
332
3257e5d4 333
857485c0 334struct iwl_host_cmd {
5d08cd1d 335 const void *data;
2f301227 336 unsigned long reply_page;
5696aea6
JB
337 void (*callback)(struct iwl_priv *priv,
338 struct iwl_device_cmd *cmd,
2f301227 339 struct iwl_rx_packet *pkt);
c2acea8e
JB
340 u32 flags;
341 u16 len;
342 u8 id;
5d08cd1d
CH
343};
344
5d08cd1d
CH
345#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
346#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
347#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
348
349/**
a55360e4 350 * struct iwl_rx_queue - Rx queue
df833b1d 351 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 352 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
353 * @read: Shared index to newest available Rx buffer
354 * @write: Shared index to oldest written Rx packet
355 * @free_count: Number of pre-allocated buffers in rx_free
356 * @rx_free: list of free SKBs for use
357 * @rx_used: List of Rx buffers with no SKB
358 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
359 * @rb_stts: driver's pointer to receive buffer status
360 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 361 *
a55360e4 362 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 363 */
a55360e4 364struct iwl_rx_queue {
5d08cd1d 365 __le32 *bd;
d5b25c90 366 dma_addr_t bd_dma;
a55360e4
TW
367 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
368 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
369 u32 read;
370 u32 write;
371 u32 free_count;
4752c93c 372 u32 write_actual;
5d08cd1d
CH
373 struct list_head rx_free;
374 struct list_head rx_used;
375 int need_update;
8d86422a
WT
376 struct iwl_rb_status *rb_stts;
377 dma_addr_t rb_stts_dma;
5d08cd1d
CH
378 spinlock_t lock;
379};
380
381#define IWL_SUPPORTED_RATES_IE_LEN 8
382
5d08cd1d
CH
383#define MAX_TID_COUNT 9
384
385#define IWL_INVALID_RATE 0xFF
386#define IWL_INVALID_VALUE -1
387
bc47279f 388/**
6def9761 389 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
390 * @txq_id: Tx queue used for Tx attempt
391 * @frame_count: # frames attempted by Tx command
392 * @wait_for_ba: Expect block-ack before next Tx reply
393 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
394 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
395 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
396 * @rate_n_flags: Rate at which Tx was attempted
397 *
398 * If REPLY_TX indicates that aggregation was attempted, driver must wait
399 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
400 * until block ack arrives.
401 */
6def9761 402struct iwl_ht_agg {
5d08cd1d
CH
403 u16 txq_id;
404 u16 frame_count;
405 u16 wait_for_ba;
406 u16 start_idx;
fe01b477 407 u64 bitmap;
5d08cd1d 408 u32 rate_n_flags;
fe01b477
RR
409#define IWL_AGG_OFF 0
410#define IWL_AGG_ON 1
411#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
412#define IWL_EMPTYING_HW_QUEUE_DELBA 3
413 u8 state;
5d08cd1d 414};
fe01b477 415
5d08cd1d 416
6def9761 417struct iwl_tid_data {
f862a236 418 u16 seq_number; /* agn only */
fe01b477 419 u16 tfds_in_queue;
6def9761 420 struct iwl_ht_agg agg;
5d08cd1d
CH
421};
422
6def9761 423struct iwl_hw_key {
97359d12 424 u32 cipher;
5d08cd1d 425 int keylen;
0211ddda 426 u8 keyidx;
5d08cd1d
CH
427 u8 key[32];
428};
429
a78fe754 430union iwl_ht_rate_supp {
5d08cd1d
CH
431 u16 rates;
432 struct {
433 u8 siso_rate;
434 u8 mimo_rate;
435 };
436};
437
5d08cd1d 438#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
bcc693a1
WYG
439
440/*
441 * Maximal MPDU density for TX aggregation
442 * 4 - 2us density
443 * 5 - 4us density
444 * 6 - 8us density
445 * 7 - 16us density
446 */
447#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
448#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
5d08cd1d 449
fad95bf5 450struct iwl_ht_config {
9e0cc6de 451 /* self configuration data */
c812ee24
JB
452 bool is_ht;
453 bool is_40mhz;
02bb1bea 454 bool single_chain_sufficient;
ba37a3d0 455 enum ieee80211_smps_mode smps; /* current smps mode */
9e0cc6de 456 /* BSS related data */
5d08cd1d 457 u8 extension_chan_offset;
9e0cc6de
RR
458 u8 ht_protection;
459 u8 non_GF_STA_present;
5d08cd1d 460};
5d08cd1d 461
5d08cd1d 462/* QoS structures */
1ff50bda 463struct iwl_qos_info {
5d08cd1d 464 int qos_active;
1ff50bda 465 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 466};
5d08cd1d 467
fe6b23dd
RC
468/*
469 * Structure should be accessed with sta_lock held. When station addition
470 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
471 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
472 * held.
473 */
6def9761 474struct iwl_station_entry {
133636de 475 struct iwl_addsta_cmd sta;
6def9761 476 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d 477 u8 used;
6def9761 478 struct iwl_hw_key keyinfo;
fe6b23dd 479 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
480};
481
fd1af15d
JB
482struct iwl_station_priv_common {
483 u8 sta_id;
484};
485
8d9698b3
RC
486/*
487 * iwl_station_priv: Driver's private station information
488 *
489 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
490 * in the structure for use by driver. This structure is places in that
491 * space.
fd1af15d
JB
492 *
493 * The common struct MUST be first because it is shared between
494 * 3945 and agn!
8d9698b3
RC
495 */
496struct iwl_station_priv {
fd1af15d 497 struct iwl_station_priv_common common;
8d9698b3 498 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
499 atomic_t pending_frames;
500 bool client;
501 bool asleep;
8d9698b3
RC
502};
503
fd1af15d
JB
504/**
505 * struct iwl_vif_priv - driver's private per-interface information
506 *
507 * When mac80211 allocates a virtual interface, it can allocate
508 * space for us to put data into.
509 */
510struct iwl_vif_priv {
511 u8 ibss_bssid_sta_id;
512};
513
5d08cd1d
CH
514/* one for each uCode image (inst/data, boot/init/runtime) */
515struct fw_desc {
516 void *v_addr; /* access by driver */
517 dma_addr_t p_addr; /* access by card's busmaster DMA */
518 u32 len; /* bytes */
519};
520
dd7a2509 521/* v1/v2 uCode file layout */
cc0f555d
JS
522struct iwl_ucode_header {
523 __le32 ver; /* major/minor/API/serial */
524 union {
525 struct {
526 __le32 inst_size; /* bytes of runtime code */
527 __le32 data_size; /* bytes of runtime data */
528 __le32 init_size; /* bytes of init code */
529 __le32 init_data_size; /* bytes of init data */
530 __le32 boot_size; /* bytes of bootstrap code */
531 u8 data[0]; /* in same order as sizes */
532 } v1;
533 struct {
534 __le32 build; /* build number */
535 __le32 inst_size; /* bytes of runtime code */
536 __le32 data_size; /* bytes of runtime data */
537 __le32 init_size; /* bytes of init code */
538 __le32 init_data_size; /* bytes of init data */
539 __le32 boot_size; /* bytes of bootstrap code */
540 u8 data[0]; /* in same order as sizes */
541 } v2;
542 } u;
5d08cd1d
CH
543};
544
dd7a2509
JB
545/*
546 * new TLV uCode file layout
547 *
548 * The new TLV file format contains TLVs, that each specify
549 * some piece of data. To facilitate "groups", for example
550 * different instruction image with different capabilities,
551 * bundled with the same init image, an alternative mechanism
552 * is provided:
553 * When the alternative field is 0, that means that the item
554 * is always valid. When it is non-zero, then it is only
555 * valid in conjunction with items of the same alternative,
556 * in which case the driver (user) selects one alternative
557 * to use.
558 */
559
560enum iwl_ucode_tlv_type {
561 IWL_UCODE_TLV_INVALID = 0, /* unused */
562 IWL_UCODE_TLV_INST = 1,
563 IWL_UCODE_TLV_DATA = 2,
564 IWL_UCODE_TLV_INIT = 3,
565 IWL_UCODE_TLV_INIT_DATA = 4,
566 IWL_UCODE_TLV_BOOT = 5,
567 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
b2e640d4
JB
568 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
569 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
570 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
571 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
572 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
573 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 574 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 575 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
dd7a2509
JB
576};
577
578struct iwl_ucode_tlv {
579 __le16 type; /* see above */
580 __le16 alternative; /* see comment */
581 __le32 length; /* not including type/length fields */
582 u8 data[0];
ba2d3587 583} __packed;
dd7a2509
JB
584
585#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
586
587struct iwl_tlv_ucode_header {
588 /*
589 * The TLV style ucode header is distinguished from
590 * the v1/v2 style header by first four bytes being
591 * zero, as such is an invalid combination of
592 * major/minor/API/serial versions.
593 */
594 __le32 zero;
595 __le32 magic;
596 u8 human_readable[64];
597 __le32 ver; /* major/minor/API/serial */
598 __le32 build;
599 __le64 alternatives; /* bitmask of valid alternatives */
600 /*
601 * The data contained herein has a TLV layout,
602 * see above for the TLV header and types.
603 * Note that each TLV is padded to a length
604 * that is a multiple of 4 for alignment.
605 */
606 u8 data[0];
607};
608
bb8c093b 609struct iwl4965_ibss_seq {
5d08cd1d
CH
610 u8 mac[ETH_ALEN];
611 u16 seq_num;
612 u16 frag_num;
613 unsigned long packet_time;
614 struct list_head list;
615};
616
f0832f13
EG
617struct iwl_sensitivity_ranges {
618 u16 min_nrg_cck;
619 u16 max_nrg_cck;
620
621 u16 nrg_th_cck;
622 u16 nrg_th_ofdm;
623
624 u16 auto_corr_min_ofdm;
625 u16 auto_corr_min_ofdm_mrc;
626 u16 auto_corr_min_ofdm_x1;
627 u16 auto_corr_min_ofdm_mrc_x1;
628
629 u16 auto_corr_max_ofdm;
630 u16 auto_corr_max_ofdm_mrc;
631 u16 auto_corr_max_ofdm_x1;
632 u16 auto_corr_max_ofdm_mrc_x1;
633
634 u16 auto_corr_max_cck;
635 u16 auto_corr_max_cck_mrc;
636 u16 auto_corr_min_cck;
637 u16 auto_corr_min_cck_mrc;
55036d66
WYG
638
639 u16 barker_corr_th_min;
640 u16 barker_corr_th_min_mrc;
641 u16 nrg_th_cca;
f0832f13
EG
642};
643
099b40b7 644
b5047f78
TW
645#define KELVIN_TO_CELSIUS(x) ((x)-273)
646#define CELSIUS_TO_KELVIN(x) ((x)+273)
647
648
bc47279f 649/**
5425e490 650 * struct iwl_hw_params
bc47279f 651 * @max_txq_num: Max # Tx queues supported
f3f911d1 652 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 653 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 654 * @tfd_size: TFD size
099b40b7
RR
655 * @tx/rx_chains_num: Number of TX/RX chains
656 * @valid_tx/rx_ant: usable antennas
bc47279f 657 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 658 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 659 * @rx_page_order: Rx buffer page order
141c43a3 660 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f
BC
661 * @max_stations:
662 * @bcast_sta_id:
7aafef1c 663 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
664 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
665 * @sw_crypto: 0 for hw, 1 for sw
666 * @max_xxx_size: for ucode uses
667 * @ct_kill_threshold: temperature threshold
a0ee74cf 668 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 669 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 670 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 671 */
5425e490 672struct iwl_hw_params {
f3f911d1
ZY
673 u8 max_txq_num;
674 u8 dma_chnl_num;
4ddbb7d0 675 u16 scd_bc_tbls_size;
a8e74e27 676 u32 tfd_size;
ec35cf2a
TW
677 u8 tx_chains_num;
678 u8 rx_chains_num;
679 u8 valid_tx_ant;
680 u8 valid_rx_ant;
5d08cd1d 681 u16 max_rxq_size;
ec35cf2a 682 u16 max_rxq_log;
2f301227 683 u32 rx_page_order;
141c43a3 684 u32 rx_wrt_ptr_reg;
5d08cd1d
CH
685 u8 max_stations;
686 u8 bcast_sta_id;
7aafef1c 687 u8 ht40_channel;
2c2f3b33 688 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
689 u32 max_inst_size;
690 u32 max_data_size;
691 u32 max_bsm_size;
692 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
693 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
694 /* for 1000, 6000 series and up */
a0ee74cf 695 u16 beacon_time_tsf_bits;
be5d56ed 696 u32 calib_init_cfg;
f0832f13 697 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
698};
699
5d08cd1d 700
5d08cd1d
CH
701/******************************************************************************
702 *
a33c2f47
EG
703 * Functions implemented in core module which are forward declared here
704 * for use by iwl-[4-5].c
5d08cd1d 705 *
a33c2f47
EG
706 * NOTE: The implementation of these functions are not hardware specific
707 * which is why they are in the core module files.
5d08cd1d
CH
708 *
709 * Naming convention --
a33c2f47 710 * iwl_ <-- Is part of iwlwifi
5d08cd1d 711 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
712 * iwl4965_bg_ <-- Called from work queue context
713 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
714 *
715 ****************************************************************************/
5b9f8cd3
EG
716extern void iwl_update_chain_flags(struct iwl_priv *priv);
717extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 718extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 719extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 720extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 721extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
722static inline int iwl_queue_used(const struct iwl_queue *q, int i)
723{
c8106d76 724 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
725 (i >= q->read_ptr && i < q->write_ptr) :
726 !(i < q->read_ptr && i >= q->write_ptr);
727}
728
729
730static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
731{
c8c24872
WYG
732 /*
733 * This is for init calibration result and scan command which
734 * required buffer > TFD_MAX_PAYLOAD_SIZE,
735 * the big buffer at end of command array
736 */
fd4abac5
TW
737 if (is_huge)
738 return q->n_window; /* must be power of 2 */
739
740 /* Otherwise, use normal size buffers */
741 return index & (q->n_window - 1);
742}
743
744
4ddbb7d0
TW
745struct iwl_dma_ptr {
746 dma_addr_t dma;
747 void *addr;
b481de9c
ZY
748 size_t size;
749};
750
b481de9c
ZY
751#define IWL_OPERATION_MODE_AUTO 0
752#define IWL_OPERATION_MODE_HT_ONLY 1
753#define IWL_OPERATION_MODE_MIXED 2
754#define IWL_OPERATION_MODE_20MHZ 3
755
3195cdb7
TW
756#define IWL_TX_CRC_SIZE 4
757#define IWL_TX_DELIMITER_SIZE 4
b481de9c 758
b481de9c 759#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 760
b481de9c 761/* Sensitivity and chain noise calibration */
b481de9c 762#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
763#define IWL4965_CAL_NUM_BEACONS 20
764#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
765#define MAXIMUM_ALLOWED_PATHLOSS 15
766
b481de9c
ZY
767#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
768
769#define MAX_FA_OFDM 50
770#define MIN_FA_OFDM 5
771#define MAX_FA_CCK 50
772#define MIN_FA_CCK 5
773
b481de9c
ZY
774#define AUTO_CORR_STEP_OFDM 1
775
b481de9c
ZY
776#define AUTO_CORR_STEP_CCK 3
777#define AUTO_CORR_MAX_TH_CCK 160
778
b481de9c
ZY
779#define NRG_DIFF 2
780#define NRG_STEP_CCK 2
781#define NRG_MARGIN 8
782#define MAX_NUMBER_CCK_NO_FA 100
783
784#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
785
786#define CHAIN_A 0
787#define CHAIN_B 1
788#define CHAIN_C 2
789#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
790#define ALL_BAND_FILTER 0xFF00
791#define IN_BAND_FILTER 0xFF
792#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
793
3195cdb7
TW
794#define NRG_NUM_PREV_STAT_L 20
795#define NUM_RX_CHAINS 3
796
bb8c093b 797enum iwl4965_false_alarm_state {
b481de9c
ZY
798 IWL_FA_TOO_MANY = 0,
799 IWL_FA_TOO_FEW = 1,
800 IWL_FA_GOOD_RANGE = 2,
801};
802
bb8c093b 803enum iwl4965_chain_noise_state {
b481de9c 804 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
805 IWL_CHAIN_NOISE_ACCUMULATE,
806 IWL_CHAIN_NOISE_CALIBRATED,
807 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
808};
809
bb8c093b 810enum iwl4965_calib_enabled_state {
b481de9c
ZY
811 IWL_CALIB_DISABLED = 0, /* must be 0 */
812 IWL_CALIB_ENABLED = 1,
813};
814
f69f42a6
TW
815
816/*
817 * enum iwl_calib
818 * defines the order in which results of initial calibrations
819 * should be sent to the runtime uCode
820 */
821enum iwl_calib {
822 IWL_CALIB_XTAL,
819500c5 823 IWL_CALIB_DC,
f69f42a6
TW
824 IWL_CALIB_LO,
825 IWL_CALIB_TX_IQ,
826 IWL_CALIB_TX_IQ_PERD,
201706ac 827 IWL_CALIB_BASE_BAND,
f69f42a6
TW
828 IWL_CALIB_MAX
829};
830
6e21f2c1
TW
831/* Opaque calibration results */
832struct iwl_calib_result {
833 void *buf;
834 size_t buf_len;
7c616cba
TW
835};
836
dbb983b7
RR
837enum ucode_type {
838 UCODE_NONE = 0,
839 UCODE_INIT,
840 UCODE_RT
841};
842
b481de9c 843/* Sensitivity calib data */
f0832f13 844struct iwl_sensitivity_data {
b481de9c
ZY
845 u32 auto_corr_ofdm;
846 u32 auto_corr_ofdm_mrc;
847 u32 auto_corr_ofdm_x1;
848 u32 auto_corr_ofdm_mrc_x1;
849 u32 auto_corr_cck;
850 u32 auto_corr_cck_mrc;
851
852 u32 last_bad_plcp_cnt_ofdm;
853 u32 last_fa_cnt_ofdm;
854 u32 last_bad_plcp_cnt_cck;
855 u32 last_fa_cnt_cck;
856
857 u32 nrg_curr_state;
858 u32 nrg_prev_state;
859 u32 nrg_value[10];
860 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
861 u32 nrg_silence_ref;
862 u32 nrg_energy_idx;
863 u32 nrg_silence_idx;
864 u32 nrg_th_cck;
865 s32 nrg_auto_corr_silence_diff;
866 u32 num_in_cck_no_fa;
867 u32 nrg_th_ofdm;
55036d66
WYG
868
869 u16 barker_corr_th_min;
870 u16 barker_corr_th_min_mrc;
871 u16 nrg_th_cca;
b481de9c
ZY
872};
873
874/* Chain noise (differential Rx gain) calib data */
f0832f13 875struct iwl_chain_noise_data {
04816448 876 u32 active_chains;
b481de9c
ZY
877 u32 chain_noise_a;
878 u32 chain_noise_b;
879 u32 chain_noise_c;
880 u32 chain_signal_a;
881 u32 chain_signal_b;
882 u32 chain_signal_c;
04816448 883 u16 beacon_count;
b481de9c
ZY
884 u8 disconn_array[NUM_RX_CHAINS];
885 u8 delta_gain_code[NUM_RX_CHAINS];
886 u8 radio_write;
04816448 887 u8 state;
b481de9c
ZY
888};
889
abceddb4
BC
890#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
891#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 892
20594eb0
WYG
893#define IWL_TRAFFIC_ENTRIES (256)
894#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 895
5d08cd1d
CH
896enum {
897 MEASUREMENT_READY = (1 << 0),
898 MEASUREMENT_ACTIVE = (1 << 1),
899};
900
0848e297
WYG
901enum iwl_nvm_type {
902 NVM_DEVICE_TYPE_EEPROM = 0,
903 NVM_DEVICE_TYPE_OTP,
904};
905
415e4993
WYG
906/*
907 * Two types of OTP memory access modes
908 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
909 * based on physical memory addressing
910 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
911 * based on logical memory addressing
912 */
913enum iwl_access_mode {
914 IWL_OTP_ACCESS_ABSOLUTE,
915 IWL_OTP_ACCESS_RELATIVE,
916};
65b7998a
WYG
917
918/**
919 * enum iwl_pa_type - Power Amplifier type
920 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
921 * @IWL_PA_INTERNAL: use Internal only
922 */
923enum iwl_pa_type {
924 IWL_PA_SYSTEM = 0,
740e7f51 925 IWL_PA_INTERNAL = 1,
65b7998a
WYG
926};
927
a83b9141
WYG
928/* interrupt statistics */
929struct isr_statistics {
930 u32 hw;
931 u32 sw;
932 u32 sw_err;
933 u32 sch;
934 u32 alive;
935 u32 rfkill;
936 u32 ctkill;
937 u32 wakeup;
938 u32 rx;
939 u32 rx_handlers[REPLY_MAX];
940 u32 tx;
941 u32 unhandled;
942};
5d08cd1d 943
22fdf3c9
WYG
944#ifdef CONFIG_IWLWIFI_DEBUGFS
945/* management statistics */
946enum iwl_mgmt_stats {
947 MANAGEMENT_ASSOC_REQ = 0,
948 MANAGEMENT_ASSOC_RESP,
949 MANAGEMENT_REASSOC_REQ,
950 MANAGEMENT_REASSOC_RESP,
951 MANAGEMENT_PROBE_REQ,
952 MANAGEMENT_PROBE_RESP,
953 MANAGEMENT_BEACON,
954 MANAGEMENT_ATIM,
955 MANAGEMENT_DISASSOC,
956 MANAGEMENT_AUTH,
957 MANAGEMENT_DEAUTH,
958 MANAGEMENT_ACTION,
959 MANAGEMENT_MAX,
960};
961/* control statistics */
962enum iwl_ctrl_stats {
963 CONTROL_BACK_REQ = 0,
964 CONTROL_BACK,
965 CONTROL_PSPOLL,
966 CONTROL_RTS,
967 CONTROL_CTS,
968 CONTROL_ACK,
969 CONTROL_CFEND,
970 CONTROL_CFENDACK,
971 CONTROL_MAX,
972};
973
974struct traffic_stats {
975 u32 mgmt[MANAGEMENT_MAX];
976 u32 ctrl[CONTROL_MAX];
977 u32 data_cnt;
978 u64 data_bytes;
979};
980#else
981struct traffic_stats {
982 u64 data_bytes;
983};
984#endif
985
0924e519
WYG
986/*
987 * iwl_switch_rxon: "channel switch" structure
988 *
989 * @ switch_in_progress: channel switch in progress
990 * @ channel: new channel
991 */
992struct iwl_switch_rxon {
993 bool switch_in_progress;
994 __le16 channel;
995};
996
a9e1cb6a
WYG
997/*
998 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
999 * to perform continuous uCode event logging operation if enabled
1000 */
1001#define UCODE_TRACE_PERIOD (100)
1002
1003/*
1004 * iwl_event_log: current uCode event log position
1005 *
1006 * @ucode_trace: enable/disable ucode continuous trace timer
1007 * @num_wraps: how many times the event buffer wraps
1008 * @next_entry: the entry just before the next one that uCode would fill
1009 * @non_wraps_count: counter for no wrap detected when dump ucode events
1010 * @wraps_once_count: counter for wrap once detected when dump ucode events
1011 * @wraps_more_count: counter for wrap more than once detected
1012 * when dump ucode events
1013 */
1014struct iwl_event_log {
1015 bool ucode_trace;
1016 u32 num_wraps;
1017 u32 next_entry;
1018 int non_wraps_count;
1019 int wraps_once_count;
1020 int wraps_more_count;
1021};
1022
2be76703
WYG
1023/*
1024 * host interrupt timeout value
1025 * used with setting interrupt coalescing timer
1026 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1027 *
1028 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1029 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1030 */
1031#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1032#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1033#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1034#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1035#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1036#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1037
3e4fb5fa
TAN
1038/*
1039 * This is the threshold value of plcp error rate per 100mSecs. It is
1040 * used to set and check for the validity of plcp_delta.
1041 */
680788ac 1042#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1043#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1044#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1045#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1046#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1047#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1048
8a472da4
WYG
1049#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1050#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1051
b74e31a9
WYG
1052/* timer constants use to monitor and recover stuck tx queues in mSecs */
1053#define IWL_MONITORING_PERIOD (1000)
1054#define IWL_ONE_HUNDRED_MSECS (100)
1055#define IWL_SIXTY_SECS (60000)
1056
a93e7973
WYG
1057enum iwl_reset {
1058 IWL_RF_RESET = 0,
1059 IWL_FW_RESET,
8a472da4
WYG
1060 IWL_MAX_FORCE_RESET,
1061};
1062
1063struct iwl_force_reset {
1064 int reset_request_count;
1065 int reset_success_count;
1066 int reset_reject_count;
1067 unsigned long reset_duration;
1068 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1069};
1070
a0ee74cf
WYG
1071/* extend beacon time format bit shifting */
1072/*
1073 * for _3945 devices
1074 * bits 31:24 - extended
1075 * bits 23:0 - interval
1076 */
1077#define IWL3945_EXT_BEACON_TIME_POS 24
1078/*
1079 * for _agn devices
1080 * bits 31:22 - extended
1081 * bits 21:0 - interval
1082 */
1083#define IWLAGN_EXT_BEACON_TIME_POS 22
1084
c79dd5b5 1085struct iwl_priv {
5d08cd1d
CH
1086
1087 /* ieee device used by generic ieee processing code */
1088 struct ieee80211_hw *hw;
1089 struct ieee80211_channel *ieee_channels;
1090 struct ieee80211_rate *ieee_rates;
82b9a121 1091 struct iwl_cfg *cfg;
5d08cd1d
CH
1092
1093 /* temporary frame storage list */
1094 struct list_head free_frames;
1095 int frames_count;
1096
8318d78a 1097 enum ieee80211_band band;
2f301227 1098 int alloc_rxb_page;
5d08cd1d 1099
c79dd5b5 1100 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1101 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1102
8318d78a 1103 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1104
5d08cd1d 1105 /* spectrum measurement report caching */
2aa6ab86 1106 struct iwl_spectrum_notification measure_report;
5d08cd1d 1107 u8 measurement_status;
81963d68 1108
5d08cd1d
CH
1109 /* ucode beacon time */
1110 u32 ucode_beacon_time;
a13d276f 1111 int missed_beacon_threshold;
5d08cd1d 1112
a85d7cca
JB
1113 /* track IBSS manager (last beacon) status */
1114 u32 ibss_manager;
1115
3e4fb5fa
TAN
1116 /* storing the jiffies when the plcp error rate is received */
1117 unsigned long plcp_jiffies;
1118
a93e7973 1119 /* force reset */
8a472da4 1120 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1121
5a2a780c 1122 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1123 * Access via channel # using indirect index array */
bf85ea4f 1124 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1125 u8 channel_count; /* # of channels */
1126
5d08cd1d
CH
1127 /* thermal calibration */
1128 s32 temperature; /* degrees Kelvin */
1129 s32 last_temperature;
1130
7c616cba 1131 /* init calibration results */
6e21f2c1 1132 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1133
5d08cd1d 1134 /* Scan related variables */
5d08cd1d 1135 unsigned long scan_start;
5d08cd1d 1136 unsigned long scan_start_tsf;
811ecc99 1137 void *scan_cmd;
00700ee0 1138 enum ieee80211_band scan_band;
1ecf9fc1 1139 struct cfg80211_scan_request *scan_request;
f84b29ec 1140 struct ieee80211_vif *scan_vif;
afbdd69a 1141 bool is_internal_short_scan;
76eff18b
TW
1142 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1143 u8 mgmt_tx_ant;
5d08cd1d
CH
1144
1145 /* spinlock */
1146 spinlock_t lock; /* protect general shared data */
1147 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1148 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1149 struct mutex mutex;
d2dfe6df 1150 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1151
1152 /* basic pci-network driver stuff */
1153 struct pci_dev *pci_dev;
1154
1155 /* pci hardware address support */
1156 void __iomem *hw_base;
b661c819
TW
1157 u32 hw_rev;
1158 u32 hw_wa_rev;
1159 u8 rev_id;
5d08cd1d 1160
c6fa17ed
WYG
1161 /* EEPROM MAC addresses */
1162 struct mac_address addresses[2];
1163
5d08cd1d 1164 /* uCode images, save to reload in case of failure */
b08dfd04 1165 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1166 u32 ucode_ver; /* version of ucode, copy of
1167 iwl_ucode.ver */
5d08cd1d
CH
1168 struct fw_desc ucode_code; /* runtime inst */
1169 struct fw_desc ucode_data; /* runtime data original */
1170 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1171 struct fw_desc ucode_init; /* initialization inst */
1172 struct fw_desc ucode_init_data; /* initialization data */
1173 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1174 enum ucode_type ucode_type;
1175 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1176 char firmware_name[25];
5d08cd1d
CH
1177
1178
3195c1f3 1179 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
1180
1181 /* We declare this const so it can only be
1182 * changed via explicit cast within the
1183 * routines that actually update the physical
1184 * hardware */
c1adf9fb
GG
1185 const struct iwl_rxon_cmd active_rxon;
1186 struct iwl_rxon_cmd staging_rxon;
5d08cd1d 1187
0924e519
WYG
1188 struct iwl_switch_rxon switch_rxon;
1189
5d08cd1d 1190 /* 1st responses from initialize and runtime uCode images.
5a2a780c 1191 * _agn's initialize alive response contains some calibration data. */
885ba202
TW
1192 struct iwl_init_alive_resp card_alive_init;
1193 struct iwl_alive_resp card_alive;
5d08cd1d 1194
ab53d8af
MA
1195 unsigned long last_blink_time;
1196 u8 last_blink_rate;
1197 u8 allow_blinking;
1198 u64 led_tpt;
e932a609 1199
5d08cd1d 1200 u16 active_rate;
5d08cd1d 1201
5d08cd1d 1202 u8 start_calib;
f0832f13
EG
1203 struct iwl_sensitivity_data sensitivity_data;
1204 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1205 bool enhance_sensitivity_table;
5d08cd1d 1206 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1207 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1208
fad95bf5 1209 struct iwl_ht_config current_ht_config;
5d08cd1d 1210
5d08cd1d 1211 /* Rate scaling data */
5d08cd1d
CH
1212 u8 retry_rate;
1213
1214 wait_queue_head_t wait_command_queue;
1215
1216 int activity_timer_active;
1217
1218 /* Rx and Tx DMA processing queues */
a55360e4 1219 struct iwl_rx_queue rxq;
88804e2b 1220 struct iwl_tx_queue *txq;
5d08cd1d 1221 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1222 struct iwl_dma_ptr kw; /* keep warm address */
1223 struct iwl_dma_ptr scd_bc_tbls;
1224
5d08cd1d
CH
1225 u32 scd_base_addr; /* scheduler sram base address */
1226
1227 unsigned long status;
5d08cd1d 1228
19758bef 1229 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1230 struct traffic_stats tx_stats;
1231 struct traffic_stats rx_stats;
19758bef 1232
a83b9141
WYG
1233 /* counts interrupts */
1234 struct isr_statistics isr_stats;
1235
5da4b55f 1236 struct iwl_power_mgr power_data;
3ad3b92a 1237 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1238
5d08cd1d 1239 /* context information */
59c02b41 1240 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
5d08cd1d 1241
9c5ac091
RC
1242 /* station table variables */
1243
1244 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1245 spinlock_t sta_lock;
1246 int num_stations;
6def9761 1247 struct iwl_station_entry stations[IWL_STATION_COUNT];
72e15d71 1248 struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; /* protected by mutex */
6974e363 1249 u8 key_mapping_key;
80fb47a1 1250 unsigned long ucode_key_table;
5d08cd1d 1251
e4e72fb4
JB
1252 /* queue refcounts */
1253#define IWL_MAX_HW_QUEUES 32
1254 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1255 /* for each AC */
1256 atomic_t queue_stop_count[4];
1257
5d08cd1d 1258 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1259 u8 is_open;
5d08cd1d
CH
1260
1261 u8 mac80211_registered;
5d08cd1d 1262
af6b8ee3 1263 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1264 u8 *eeprom;
0848e297 1265 int nvm_device_type;
073d3f5f 1266 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1267
05c914fe 1268 enum nl80211_iftype iw_mode;
5d08cd1d
CH
1269
1270 struct sk_buff *ibss_beacon;
1271
1272 /* Last Rx'd beacon timestamp */
3109ece1 1273 u64 timestamp;
32bfd35d 1274 struct ieee80211_vif *vif;
5d08cd1d 1275
ee525d13
JB
1276 union {
1277#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1278 struct {
1279 void *shared_virt;
1280 dma_addr_t shared_phys;
1281
1282 struct delayed_work thermal_periodic;
1283 struct delayed_work rfkill_poll;
1284
1285 struct iwl3945_notif_statistics statistics;
d73e4923 1286#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK
1287 struct iwl3945_notif_statistics accum_statistics;
1288 struct iwl3945_notif_statistics delta_statistics;
1289 struct iwl3945_notif_statistics max_delta;
1290#endif
ee525d13
JB
1291
1292 u32 sta_supp_rates;
e99f168c
JB
1293 int last_rx_rssi; /* From Rx packet statistics */
1294
1295 /* Rx'd packet timing information */
1296 u32 last_beacon_time;
1297 u64 last_tsf;
67d613ae
JB
1298
1299 /*
1300 * each calibration channel group in the
1301 * EEPROM has a derived clip setting for
1302 * each rate.
1303 */
1304 const struct iwl3945_clip_group clip_groups[5];
1305
ee525d13 1306 } _3945;
a4c8b2a6
JB
1307#endif
1308#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1309 struct {
1310 /* INT ICT Table */
1311 __le32 *ict_tbl;
1312 void *ict_tbl_vir;
1313 dma_addr_t ict_tbl_dma;
1314 dma_addr_t aligned_ict_tbl_dma;
1315 int ict_index;
1316 u32 inta;
1317 bool use_ict;
d5a0ffa3
WYG
1318 /*
1319 * reporting the number of tids has AGG on. 0 means
1320 * no AGGREGATION
1321 */
1322 u8 agg_tids_count;
05d57520
JB
1323
1324 struct iwl_rx_phy_res last_phy_res;
1325 bool last_phy_res_valid;
a15707d8
RC
1326
1327 struct completion firmware_loading_complete;
a2064b7a 1328
b2e640d4
JB
1329 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1330 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
f3aebeee 1331
6a822d06
WYG
1332 /*
1333 * chain noise reset and gain commands are the
1334 * two extra calibration commands follows the standard
1335 * phy calibration commands
1336 */
1337 u8 phy_calib_chain_noise_reset_cmd;
1338 u8 phy_calib_chain_noise_gain_cmd;
1339
f3aebeee 1340 struct iwl_notif_statistics statistics;
7980fba5 1341 struct iwl_bt_notif_statistics statistics_bt;
f3aebeee
WYG
1342#ifdef CONFIG_IWLWIFI_DEBUGFS
1343 struct iwl_notif_statistics accum_statistics;
1344 struct iwl_notif_statistics delta_statistics;
1345 struct iwl_notif_statistics max_delta;
7980fba5
WYG
1346 struct iwl_bt_notif_statistics accum_statistics_bt;
1347 struct iwl_bt_notif_statistics delta_statistics_bt;
1348 struct iwl_bt_notif_statistics max_delta_bt;
f3aebeee 1349#endif
a4c8b2a6 1350 } _agn;
ee525d13
JB
1351#endif
1352 };
1353
5425e490 1354 struct iwl_hw_params hw_params;
4ddbb7d0 1355
40cefda9 1356 u32 inta_mask;
5d08cd1d 1357
1ff50bda 1358 struct iwl_qos_info qos_data;
5d08cd1d
CH
1359
1360 struct workqueue_struct *workqueue;
1361
5d08cd1d 1362 struct work_struct restart;
5d08cd1d
CH
1363 struct work_struct scan_completed;
1364 struct work_struct rx_replenish;
5d08cd1d 1365 struct work_struct abort_scan;
5d08cd1d 1366 struct work_struct beacon_update;
a28027cd
WYG
1367 struct work_struct tt_work;
1368 struct work_struct ct_enter;
1369 struct work_struct ct_exit;
88be0264 1370 struct work_struct start_internal_scan;
65550636 1371 struct work_struct tx_flush;
5d08cd1d
CH
1372
1373 struct tasklet_struct irq_tasklet;
1374
1375 struct delayed_work init_alive_start;
1376 struct delayed_work alive_start;
5d08cd1d 1377 struct delayed_work scan_check;
4a8a4322 1378
630fe9b6
TW
1379 /* TX Power */
1380 s8 tx_power_user_lmt;
dc1b0973 1381 s8 tx_power_device_lmt;
ae16fc3c 1382 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
5d08cd1d 1383
5d08cd1d 1384
d08853a3 1385#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1386 /* debugging info */
3d816c77
RC
1387 u32 debug_level; /* per device debugging will override global
1388 iwl_debug_level if set */
d73e4923 1389#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1390#ifdef CONFIG_IWLWIFI_DEBUGFS
1391 /* debugfs */
20594eb0
WYG
1392 u16 tx_traffic_idx;
1393 u16 rx_traffic_idx;
1394 u8 *tx_traffic;
1395 u8 *rx_traffic;
4c84a8f1
JB
1396 struct dentry *debugfs_dir;
1397 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1398 bool disable_ht40;
712b6cf5 1399#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1400
1401 struct work_struct txpower_work;
445c2dff
TW
1402 u32 disable_sens_cal;
1403 u32 disable_chain_noise_cal;
203566f3 1404 u32 disable_tx_power_cal;
16e727e8 1405 struct work_struct run_time_calib_work;
5d08cd1d 1406 struct timer_list statistics_periodic;
a9e1cb6a 1407 struct timer_list ucode_trace;
b74e31a9 1408 struct timer_list monitor_recover;
086ed117 1409 bool hw_ready;
a9e1cb6a
WYG
1410
1411 struct iwl_event_log event_log;
c79dd5b5 1412}; /*iwl_priv */
5d08cd1d 1413
36470749
RR
1414static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1415{
1416 set_bit(txq_id, &priv->txq_ctx_active_msk);
1417}
1418
1419static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1420{
1421 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1422}
1423
994d31f7 1424#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6 1425const char *iwl_get_tx_fail_reason(u32 status);
3d816c77
RC
1426/*
1427 * iwl_get_debug_level: Return active debug level for device
1428 *
1429 * Using sysfs it is possible to set per device debug level. This debug
1430 * level will be used if set, otherwise the global debug level which can be
1431 * set via module parameter is used.
1432 */
1433static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1434{
1435 if (priv->debug_level)
1436 return priv->debug_level;
1437 else
1438 return iwl_debug_level;
1439}
a332f8d6
TW
1440#else
1441static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
3d816c77
RC
1442
1443static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1444{
1445 return iwl_debug_level;
1446}
a332f8d6
TW
1447#endif
1448
1449
a332f8d6
TW
1450static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1451 int txq_id, int idx)
1452{
ff0d91c3 1453 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1454 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1455 txb[idx].skb->data;
a332f8d6
TW
1456 return NULL;
1457}
a332f8d6
TW
1458
1459
3109ece1 1460static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1461{
1462 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1463}
1464
bf85ea4f 1465static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1466{
1467 if (ch_info == NULL)
1468 return 0;
1469 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1470}
1471
bf85ea4f 1472static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1473{
1474 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1475}
1476
bf85ea4f 1477static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1478{
8318d78a 1479 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1480}
1481
bf85ea4f 1482static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1483{
8318d78a 1484 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1485}
1486
bf85ea4f 1487static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1488{
1489 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1490}
1491
bf85ea4f 1492static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1493{
1494 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1495}
1496
64a76b50
ZY
1497static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1498{
1499 __free_pages(page, priv->hw_params.rx_page_order);
1500 priv->alloc_rxb_page--;
1501}
1502
1503static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1504{
1505 free_pages(page, priv->hw_params.rx_page_order);
1506 priv->alloc_rxb_page--;
1507}
be1f3ab6 1508#endif /* __iwl_dev_h__ */