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iwlagn: move sync_irq to transport layer
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CommitLineData
b481de9c
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1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 */
30
be1f3ab6
EG
31#ifndef __iwl_dev_h__
32#define __iwl_dev_h__
b481de9c 33
5d08cd1d
CH
34#include <linux/pci.h> /* for struct pci_device_id */
35#include <linux/kernel.h>
7194207c 36#include <linux/wait.h>
5ed540ae 37#include <linux/leds.h>
5d08cd1d
CH
38#include <net/ieee80211_radiotap.h>
39
6bc913bd 40#include "iwl-eeprom.h"
6f83eaa1 41#include "iwl-csr.h"
5d08cd1d 42#include "iwl-prph.h"
dbb6654c 43#include "iwl-fh.h"
0a6857e7 44#include "iwl-debug.h"
b744cb79 45#include "iwl-agn-hw.h"
ab53d8af 46#include "iwl-led.h"
5da4b55f 47#include "iwl-power.h"
e227ceac 48#include "iwl-agn-rs.h"
0975cc8f 49#include "iwl-agn-tt.h"
5d08cd1d 50
48d1a211
EG
51#define DRV_NAME "iwlagn"
52
672639de
WYG
53struct iwl_tx_queue;
54
099b40b7 55/* CT-KILL constants */
672639de
WYG
56#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
57#define CT_KILL_THRESHOLD 114 /* in Celsius */
58#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 59
5d08cd1d
CH
60/* Default noise level to report when noise measurement is not available.
61 * This may be because we're:
62 * 1) Not associated (4965, no beacon statistics being sent to driver)
63 * 2) Scanning (noise measurement does not apply to associated channel)
64 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
65 * Use default noise value of -127 ... this is below the range of measurable
66 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
67 * Also, -127 works better than 0 when averaging frames with/without
68 * noise info (e.g. averaging might be done in app); measured dBm values are
69 * always negative ... using a negative value as the default keeps all
70 * averages within an s8's (used in some apps) range of negative values. */
71#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
72
5d08cd1d
CH
73/*
74 * RTS threshold here is total size [2347] minus 4 FCS bytes
75 * Per spec:
76 * a value of 0 means RTS on all data/management packets
77 * a value > max MSDU size means no RTS
78 * else RTS for data/management frames where MPDU is larger
79 * than RTS value.
80 */
81#define DEFAULT_RTS_THRESHOLD 2347U
82#define MIN_RTS_THRESHOLD 0U
83#define MAX_RTS_THRESHOLD 2347U
84#define MAX_MSDU_SIZE 2304U
85#define MAX_MPDU_SIZE 2346U
51b7ef05 86#define DEFAULT_BEACON_INTERVAL 200U
5d08cd1d
CH
87#define DEFAULT_SHORT_RETRY_LIMIT 7U
88#define DEFAULT_LONG_RETRY_LIMIT 4U
89
a55360e4 90struct iwl_rx_mem_buffer {
2f301227
ZY
91 dma_addr_t page_dma;
92 struct page *page;
5d08cd1d
CH
93 struct list_head list;
94};
95
2f301227
ZY
96#define rxb_addr(r) page_address(r->page)
97
c2acea8e
JB
98/* defined below */
99struct iwl_device_cmd;
100
101struct iwl_cmd_meta {
102 /* only for SYNC commands, iff the reply skb is wanted */
103 struct iwl_host_cmd *source;
104 /*
105 * only for ASYNC commands
106 * (which is somewhat stupid -- look at iwl-sta.c for instance
107 * which duplicates a bunch of code because the callback isn't
108 * invoked for SYNC commands, if it were and its result passed
109 * through it would be simpler...)
110 */
5696aea6
JB
111 void (*callback)(struct iwl_priv *priv,
112 struct iwl_device_cmd *cmd,
2f301227 113 struct iwl_rx_packet *pkt);
c2acea8e 114
c2acea8e
JB
115 u32 flags;
116
2e724443
FT
117 DEFINE_DMA_UNMAP_ADDR(mapping);
118 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
119};
120
5d08cd1d
CH
121/*
122 * Generic queue structure
123 *
4ce7cc2b
JB
124 * Contains common data for Rx and Tx queues.
125 *
126 * Note the difference between n_bd and n_window: the hardware
127 * always assumes 256 descriptors, so n_bd is always 256 (unless
128 * there might be HW changes in the future). For the normal TX
129 * queues, n_window, which is the size of the software queue data
130 * is also 256; however, for the command queue, n_window is only
131 * 32 since we don't need so many commands pending. Since the HW
132 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
133 * the software buffers (in the variables @meta, @txb in struct
134 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
135 * in the same struct) have 256.
136 * This means that we end up with the following:
137 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
138 * SW entries: | 0 | ... | 31 |
139 * where N is a number between 0 and 7. This means that the SW
140 * data is a window overlayed over the HW queue.
5d08cd1d 141 */
443cfd45 142struct iwl_queue {
5d08cd1d
CH
143 int n_bd; /* number of BDs in this queue */
144 int write_ptr; /* 1-st empty entry (index) host_w*/
145 int read_ptr; /* last used entry (index) host_r*/
b74e31a9 146 /* use for monitoring and recovering the stuck queue */
5d08cd1d
CH
147 dma_addr_t dma_addr; /* physical addr for BD's */
148 int n_window; /* safe queue window */
149 u32 id;
150 int low_mark; /* low watermark, resume queue if free
151 * space more than this */
152 int high_mark; /* high watermark, stop queue if free
153 * space less than this */
a839cf69 154};
5d08cd1d 155
bc47279f 156/* One for each TFD */
8567c63e 157struct iwl_tx_info {
ff0d91c3 158 struct sk_buff *skb;
c90cbbbd 159 struct iwl_rxon_context *ctx;
5d08cd1d
CH
160};
161
162/**
16466903 163 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
164 * @q: generic Rx/Tx queue descriptor
165 * @bd: base of circular buffer of TFDs
c2acea8e
JB
166 * @cmd: array of command/TX buffer pointers
167 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
168 * @dma_addr_cmd: physical address of cmd/tx buffer array
169 * @txb: array of per-TFD driver data
22de94de 170 * @time_stamp: time (in jiffies) of last read_ptr change
bc47279f
BC
171 * @need_update: indicates need to update read/write index
172 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 173 *
bc47279f
BC
174 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
175 * descriptors) and required locking structures.
5d08cd1d 176 */
188cf6c7
SO
177#define TFD_TX_CMD_SLOTS 256
178#define TFD_CMD_SLOTS 32
179
16466903 180struct iwl_tx_queue {
443cfd45 181 struct iwl_queue q;
4ce7cc2b 182 struct iwl_tfd *tfds;
c2acea8e
JB
183 struct iwl_device_cmd **cmd;
184 struct iwl_cmd_meta *meta;
8567c63e 185 struct iwl_tx_info *txb;
22de94de 186 unsigned long time_stamp;
3fd07a1e
TW
187 u8 need_update;
188 u8 sched_retry;
189 u8 active;
190 u8 swq_id;
5d08cd1d
CH
191};
192
193#define IWL_NUM_SCAN_RATES (2)
194
5d08cd1d
CH
195/*
196 * One for each channel, holds all channel setup data
197 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
198 * with one another!
199 */
bf85ea4f 200struct iwl_channel_info {
073d3f5f 201 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
202 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
203 * HT40 channel */
5d08cd1d
CH
204
205 u8 channel; /* channel number */
206 u8 flags; /* flags copied from EEPROM */
207 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 208 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
209 s8 min_power; /* always 0 */
210 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
211
212 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
213 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 214 enum ieee80211_band band;
5d08cd1d 215
7aafef1c
WYG
216 /* HT40 channel info */
217 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
218 u8 ht40_flags; /* flags copied from EEPROM */
219 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
5d08cd1d
CH
220};
221
751ca305 222#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 223#define IWL_TX_FIFO_BE 1
751ca305 224#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 225#define IWL_TX_FIFO_VO 3
751ca305
JB
226#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
227#define IWL_TX_FIFO_BE_IPAN 4
228#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
229#define IWL_TX_FIFO_VO_IPAN 5
edc1a3a0 230#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 231
01a7e084
RC
232/* Minimum number of queues. MAX_NUM is defined in hw specific files.
233 * Set the minimum to accommodate the 4 standard TX queues, 1 command
234 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
235#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 236
bd35f150 237/*
13bb9483 238 * Command queue depends on iPAN support.
bd35f150 239 */
13bb9483
JB
240#define IWL_DEFAULT_CMD_QUEUE_NUM 4
241#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 242
751ca305
JB
243/*
244 * This queue number is required for proper operation
245 * because the ucode will stop/start the scheduler as
246 * required.
247 */
248#define IWL_IPAN_MCAST_QUEUE 8
249
5d08cd1d
CH
250#define IEEE80211_DATA_LEN 2304
251#define IEEE80211_4ADDR_LEN 30
252#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
253#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
254
5d08cd1d 255
5d08cd1d
CH
256#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
257#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
258#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
259
260enum {
c587de0b 261 CMD_SYNC = 0,
e419d62d
EG
262 CMD_ASYNC = BIT(0),
263 CMD_WANT_SKB = BIT(1),
c7c1115b 264 CMD_ON_DEMAND = BIT(2),
5d08cd1d
CH
265};
266
c8c24872 267#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 268
bc47279f 269/**
c2acea8e 270 * struct iwl_device_cmd
bc47279f
BC
271 *
272 * For allocation of the command and tx queues, this establishes the overall
4ce7cc2b
JB
273 * size of the largest command we send to uCode, except for commands that
274 * aren't fully copied and use other TFD space.
bc47279f 275 */
c2acea8e 276struct iwl_device_cmd {
857485c0 277 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 278 union {
5d08cd1d
CH
279 u32 flags;
280 u8 val8;
281 u16 val16;
282 u32 val32;
83d527d9 283 struct iwl_tx_cmd tx;
c8c24872
WYG
284 struct iwl6000_channel_switch_cmd chswitch;
285 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
286 } __packed cmd;
287} __packed;
5d08cd1d 288
c2acea8e
JB
289#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
290
4ce7cc2b
JB
291#define IWL_MAX_CMD_TFDS 2
292
293enum iwl_hcmd_dataflag {
294 IWL_HCMD_DFL_NOCOPY = BIT(0),
295};
3257e5d4 296
e419d62d
EG
297/**
298 * struct iwl_host_cmd - Host command to the uCode
299 * @data: array of chunks that composes the data of the host command
300 * @reply_page: pointer to the page that holds the response to the host command
301 * @callback:
302 * @flags: can be CMD_* note CMD_WANT_SKB is incompatible withe CMD_ASYNC
303 * @len: array of the lenths of the chunks in data
304 * @dataflags:
305 * @id: id of the host command
306 */
857485c0 307struct iwl_host_cmd {
3fa50738 308 const void *data[IWL_MAX_CMD_TFDS];
2f301227 309 unsigned long reply_page;
5696aea6
JB
310 void (*callback)(struct iwl_priv *priv,
311 struct iwl_device_cmd *cmd,
2f301227 312 struct iwl_rx_packet *pkt);
c2acea8e 313 u32 flags;
3fa50738 314 u16 len[IWL_MAX_CMD_TFDS];
4ce7cc2b 315 u8 dataflags[IWL_MAX_CMD_TFDS];
c2acea8e 316 u8 id;
5d08cd1d
CH
317};
318
5d08cd1d
CH
319#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
320#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
321#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
322
323/**
a55360e4 324 * struct iwl_rx_queue - Rx queue
df833b1d 325 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 326 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
327 * @read: Shared index to newest available Rx buffer
328 * @write: Shared index to oldest written Rx packet
329 * @free_count: Number of pre-allocated buffers in rx_free
330 * @rx_free: list of free SKBs for use
331 * @rx_used: List of Rx buffers with no SKB
332 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
333 * @rb_stts: driver's pointer to receive buffer status
334 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 335 *
a55360e4 336 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 337 */
a55360e4 338struct iwl_rx_queue {
5d08cd1d 339 __le32 *bd;
d5b25c90 340 dma_addr_t bd_dma;
a55360e4
TW
341 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
342 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
343 u32 read;
344 u32 write;
345 u32 free_count;
4752c93c 346 u32 write_actual;
5d08cd1d
CH
347 struct list_head rx_free;
348 struct list_head rx_used;
349 int need_update;
8d86422a
WT
350 struct iwl_rb_status *rb_stts;
351 dma_addr_t rb_stts_dma;
5d08cd1d
CH
352 spinlock_t lock;
353};
354
355#define IWL_SUPPORTED_RATES_IE_LEN 8
356
5d08cd1d
CH
357#define MAX_TID_COUNT 9
358
359#define IWL_INVALID_RATE 0xFF
360#define IWL_INVALID_VALUE -1
361
bc47279f 362/**
6def9761 363 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
364 * @txq_id: Tx queue used for Tx attempt
365 * @frame_count: # frames attempted by Tx command
366 * @wait_for_ba: Expect block-ack before next Tx reply
367 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
368 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
369 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
370 * @rate_n_flags: Rate at which Tx was attempted
371 *
372 * If REPLY_TX indicates that aggregation was attempted, driver must wait
373 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
374 * until block ack arrives.
375 */
6def9761 376struct iwl_ht_agg {
5d08cd1d
CH
377 u16 txq_id;
378 u16 frame_count;
379 u16 wait_for_ba;
380 u16 start_idx;
fe01b477 381 u64 bitmap;
5d08cd1d 382 u32 rate_n_flags;
fe01b477
RR
383#define IWL_AGG_OFF 0
384#define IWL_AGG_ON 1
385#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
386#define IWL_EMPTYING_HW_QUEUE_DELBA 3
387 u8 state;
c8823ec1 388 u8 tx_fifo;
5d08cd1d 389};
fe01b477 390
5d08cd1d 391
6def9761 392struct iwl_tid_data {
f862a236 393 u16 seq_number; /* agn only */
fe01b477 394 u16 tfds_in_queue;
6def9761 395 struct iwl_ht_agg agg;
5d08cd1d
CH
396};
397
6def9761 398struct iwl_hw_key {
97359d12 399 u32 cipher;
5d08cd1d 400 int keylen;
0211ddda 401 u8 keyidx;
5d08cd1d
CH
402 u8 key[32];
403};
404
a78fe754 405union iwl_ht_rate_supp {
5d08cd1d
CH
406 u16 rates;
407 struct {
408 u8 siso_rate;
409 u8 mimo_rate;
410 };
411};
412
172c1d11
WYG
413#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
414#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
415#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
416#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
417#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
418#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
419#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
420
421/*
422 * Maximal MPDU density for TX aggregation
423 * 4 - 2us density
424 * 5 - 4us density
425 * 6 - 8us density
426 * 7 - 16us density
427 */
172c1d11 428#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 429#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
430#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
431#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 432#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
433#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
434#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 435
fad95bf5 436struct iwl_ht_config {
02bb1bea 437 bool single_chain_sufficient;
ba37a3d0 438 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 439};
5d08cd1d 440
5d08cd1d 441/* QoS structures */
1ff50bda 442struct iwl_qos_info {
5d08cd1d 443 int qos_active;
1ff50bda 444 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 445};
5d08cd1d 446
fe6b23dd
RC
447/*
448 * Structure should be accessed with sta_lock held. When station addition
449 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
450 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
451 * held.
452 */
6def9761 453struct iwl_station_entry {
133636de 454 struct iwl_addsta_cmd sta;
6def9761 455 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 456 u8 used, ctxid;
6def9761 457 struct iwl_hw_key keyinfo;
fe6b23dd 458 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
459};
460
fd1af15d 461struct iwl_station_priv_common {
238d781d 462 struct iwl_rxon_context *ctx;
fd1af15d
JB
463 u8 sta_id;
464};
465
8d9698b3
RC
466/*
467 * iwl_station_priv: Driver's private station information
468 *
469 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
470 * in the structure for use by driver. This structure is places in that
471 * space.
8d9698b3
RC
472 */
473struct iwl_station_priv {
fd1af15d 474 struct iwl_station_priv_common common;
8d9698b3 475 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
476 atomic_t pending_frames;
477 bool client;
478 bool asleep;
7b090687 479 u8 max_agg_bufsize;
8d9698b3
RC
480};
481
fd1af15d
JB
482/**
483 * struct iwl_vif_priv - driver's private per-interface information
484 *
485 * When mac80211 allocates a virtual interface, it can allocate
486 * space for us to put data into.
487 */
488struct iwl_vif_priv {
246ed355 489 struct iwl_rxon_context *ctx;
fd1af15d
JB
490 u8 ibss_bssid_sta_id;
491};
492
5d08cd1d
CH
493/* one for each uCode image (inst/data, boot/init/runtime) */
494struct fw_desc {
495 void *v_addr; /* access by driver */
496 dma_addr_t p_addr; /* access by card's busmaster DMA */
497 u32 len; /* bytes */
498};
499
dbf28e21
JB
500struct fw_img {
501 struct fw_desc code, data;
502};
503
dd7a2509 504/* v1/v2 uCode file layout */
cc0f555d
JS
505struct iwl_ucode_header {
506 __le32 ver; /* major/minor/API/serial */
507 union {
508 struct {
509 __le32 inst_size; /* bytes of runtime code */
510 __le32 data_size; /* bytes of runtime data */
511 __le32 init_size; /* bytes of init code */
512 __le32 init_data_size; /* bytes of init data */
513 __le32 boot_size; /* bytes of bootstrap code */
514 u8 data[0]; /* in same order as sizes */
515 } v1;
516 struct {
517 __le32 build; /* build number */
518 __le32 inst_size; /* bytes of runtime code */
519 __le32 data_size; /* bytes of runtime data */
520 __le32 init_size; /* bytes of init code */
521 __le32 init_data_size; /* bytes of init data */
522 __le32 boot_size; /* bytes of bootstrap code */
523 u8 data[0]; /* in same order as sizes */
524 } v2;
525 } u;
5d08cd1d
CH
526};
527
dd7a2509
JB
528/*
529 * new TLV uCode file layout
530 *
531 * The new TLV file format contains TLVs, that each specify
532 * some piece of data. To facilitate "groups", for example
533 * different instruction image with different capabilities,
534 * bundled with the same init image, an alternative mechanism
535 * is provided:
536 * When the alternative field is 0, that means that the item
537 * is always valid. When it is non-zero, then it is only
538 * valid in conjunction with items of the same alternative,
539 * in which case the driver (user) selects one alternative
540 * to use.
541 */
542
543enum iwl_ucode_tlv_type {
544 IWL_UCODE_TLV_INVALID = 0, /* unused */
545 IWL_UCODE_TLV_INST = 1,
546 IWL_UCODE_TLV_DATA = 2,
547 IWL_UCODE_TLV_INIT = 3,
548 IWL_UCODE_TLV_INIT_DATA = 4,
549 IWL_UCODE_TLV_BOOT = 5,
550 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 551 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
552 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
553 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
554 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
555 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
556 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
557 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 558 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 559 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
3997ff39
JB
560 /* 16 and 17 reserved for future use */
561 IWL_UCODE_TLV_FLAGS = 18,
562};
563
564/**
565 * enum iwl_ucode_tlv_flag - ucode API flags
566 * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
567 * was a separate TLV but moved here to save space.
d2690c0d
JB
568 * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
569 * treats good CRC threshold as a boolean
3997ff39
JB
570 * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
571 */
572enum iwl_ucode_tlv_flag {
573 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
d2690c0d 574 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
3997ff39 575 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
dd7a2509
JB
576};
577
578struct iwl_ucode_tlv {
579 __le16 type; /* see above */
580 __le16 alternative; /* see comment */
581 __le32 length; /* not including type/length fields */
582 u8 data[0];
ba2d3587 583} __packed;
dd7a2509
JB
584
585#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
586
587struct iwl_tlv_ucode_header {
588 /*
589 * The TLV style ucode header is distinguished from
590 * the v1/v2 style header by first four bytes being
591 * zero, as such is an invalid combination of
592 * major/minor/API/serial versions.
593 */
594 __le32 zero;
595 __le32 magic;
596 u8 human_readable[64];
597 __le32 ver; /* major/minor/API/serial */
598 __le32 build;
599 __le64 alternatives; /* bitmask of valid alternatives */
600 /*
601 * The data contained herein has a TLV layout,
602 * see above for the TLV header and types.
603 * Note that each TLV is padded to a length
604 * that is a multiple of 4 for alignment.
605 */
606 u8 data[0];
607};
608
f0832f13
EG
609struct iwl_sensitivity_ranges {
610 u16 min_nrg_cck;
611 u16 max_nrg_cck;
612
613 u16 nrg_th_cck;
614 u16 nrg_th_ofdm;
615
616 u16 auto_corr_min_ofdm;
617 u16 auto_corr_min_ofdm_mrc;
618 u16 auto_corr_min_ofdm_x1;
619 u16 auto_corr_min_ofdm_mrc_x1;
620
621 u16 auto_corr_max_ofdm;
622 u16 auto_corr_max_ofdm_mrc;
623 u16 auto_corr_max_ofdm_x1;
624 u16 auto_corr_max_ofdm_mrc_x1;
625
626 u16 auto_corr_max_cck;
627 u16 auto_corr_max_cck_mrc;
628 u16 auto_corr_min_cck;
629 u16 auto_corr_min_cck_mrc;
55036d66
WYG
630
631 u16 barker_corr_th_min;
632 u16 barker_corr_th_min_mrc;
633 u16 nrg_th_cca;
f0832f13
EG
634};
635
099b40b7 636
b5047f78
TW
637#define KELVIN_TO_CELSIUS(x) ((x)-273)
638#define CELSIUS_TO_KELVIN(x) ((x)+273)
639
640
bc47279f 641/**
5425e490 642 * struct iwl_hw_params
bc47279f 643 * @max_txq_num: Max # Tx queues supported
4ddbb7d0 644 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 645 * @tfd_size: TFD size
099b40b7
RR
646 * @tx/rx_chains_num: Number of TX/RX chains
647 * @valid_tx/rx_ant: usable antennas
bc47279f 648 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 649 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 650 * @rx_page_order: Rx buffer page order
141c43a3 651 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 652 * @max_stations:
7aafef1c 653 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
654 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
655 * @sw_crypto: 0 for hw, 1 for sw
656 * @max_xxx_size: for ucode uses
657 * @ct_kill_threshold: temperature threshold
a0ee74cf 658 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 659 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 660 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 661 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 662 */
5425e490 663struct iwl_hw_params {
f3f911d1 664 u8 max_txq_num;
4ddbb7d0 665 u16 scd_bc_tbls_size;
a8e74e27 666 u32 tfd_size;
ec35cf2a
TW
667 u8 tx_chains_num;
668 u8 rx_chains_num;
669 u8 valid_tx_ant;
670 u8 valid_rx_ant;
5d08cd1d 671 u16 max_rxq_size;
ec35cf2a 672 u16 max_rxq_log;
2f301227 673 u32 rx_page_order;
5d08cd1d 674 u8 max_stations;
7aafef1c 675 u8 ht40_channel;
2c2f3b33 676 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
677 u32 max_inst_size;
678 u32 max_data_size;
099b40b7 679 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
680 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
681 /* for 1000, 6000 series and up */
a0ee74cf 682 u16 beacon_time_tsf_bits;
be5d56ed 683 u32 calib_init_cfg;
6d6a1afd 684 u32 calib_rt_cfg;
f0832f13 685 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
686};
687
5d08cd1d 688
5d08cd1d
CH
689/******************************************************************************
690 *
a33c2f47
EG
691 * Functions implemented in core module which are forward declared here
692 * for use by iwl-[4-5].c
5d08cd1d 693 *
a33c2f47
EG
694 * NOTE: The implementation of these functions are not hardware specific
695 * which is why they are in the core module files.
5d08cd1d
CH
696 *
697 * Naming convention --
a33c2f47 698 * iwl_ <-- Is part of iwlwifi
5d08cd1d 699 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
5d08cd1d
CH
700 *
701 ****************************************************************************/
5b9f8cd3 702extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 703extern const u8 iwl_bcast_addr[ETH_ALEN];
443cfd45 704extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
705static inline int iwl_queue_used(const struct iwl_queue *q, int i)
706{
c8106d76 707 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
708 (i >= q->read_ptr && i < q->write_ptr) :
709 !(i < q->read_ptr && i >= q->write_ptr);
710}
711
712
4ce7cc2b 713static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
fd4abac5 714{
fd4abac5
TW
715 return index & (q->n_window - 1);
716}
717
718
4ddbb7d0
TW
719struct iwl_dma_ptr {
720 dma_addr_t dma;
721 void *addr;
b481de9c
ZY
722 size_t size;
723};
724
b481de9c
ZY
725#define IWL_OPERATION_MODE_AUTO 0
726#define IWL_OPERATION_MODE_HT_ONLY 1
727#define IWL_OPERATION_MODE_MIXED 2
728#define IWL_OPERATION_MODE_20MHZ 3
729
3195cdb7
TW
730#define IWL_TX_CRC_SIZE 4
731#define IWL_TX_DELIMITER_SIZE 4
b481de9c 732
b481de9c 733#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 734
b481de9c 735/* Sensitivity and chain noise calibration */
b481de9c 736#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a 737#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
738#define MAXIMUM_ALLOWED_PATHLOSS 15
739
b481de9c
ZY
740#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
741
742#define MAX_FA_OFDM 50
743#define MIN_FA_OFDM 5
744#define MAX_FA_CCK 50
745#define MIN_FA_CCK 5
746
b481de9c
ZY
747#define AUTO_CORR_STEP_OFDM 1
748
b481de9c
ZY
749#define AUTO_CORR_STEP_CCK 3
750#define AUTO_CORR_MAX_TH_CCK 160
751
b481de9c
ZY
752#define NRG_DIFF 2
753#define NRG_STEP_CCK 2
754#define NRG_MARGIN 8
755#define MAX_NUMBER_CCK_NO_FA 100
756
757#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
758
759#define CHAIN_A 0
760#define CHAIN_B 1
761#define CHAIN_C 2
762#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
763#define ALL_BAND_FILTER 0xFF00
764#define IN_BAND_FILTER 0xFF
765#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
766
3195cdb7
TW
767#define NRG_NUM_PREV_STAT_L 20
768#define NUM_RX_CHAINS 3
769
3240cab3 770enum iwlagn_false_alarm_state {
b481de9c
ZY
771 IWL_FA_TOO_MANY = 0,
772 IWL_FA_TOO_FEW = 1,
773 IWL_FA_GOOD_RANGE = 2,
774};
775
3240cab3 776enum iwlagn_chain_noise_state {
b481de9c 777 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
778 IWL_CHAIN_NOISE_ACCUMULATE,
779 IWL_CHAIN_NOISE_CALIBRATED,
780 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
781};
782
f69f42a6
TW
783
784/*
785 * enum iwl_calib
786 * defines the order in which results of initial calibrations
787 * should be sent to the runtime uCode
788 */
789enum iwl_calib {
790 IWL_CALIB_XTAL,
819500c5 791 IWL_CALIB_DC,
f69f42a6
TW
792 IWL_CALIB_LO,
793 IWL_CALIB_TX_IQ,
794 IWL_CALIB_TX_IQ_PERD,
201706ac 795 IWL_CALIB_BASE_BAND,
bf53f939 796 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
797 IWL_CALIB_MAX
798};
799
6e21f2c1
TW
800/* Opaque calibration results */
801struct iwl_calib_result {
802 void *buf;
803 size_t buf_len;
7c616cba
TW
804};
805
b481de9c 806/* Sensitivity calib data */
f0832f13 807struct iwl_sensitivity_data {
b481de9c
ZY
808 u32 auto_corr_ofdm;
809 u32 auto_corr_ofdm_mrc;
810 u32 auto_corr_ofdm_x1;
811 u32 auto_corr_ofdm_mrc_x1;
812 u32 auto_corr_cck;
813 u32 auto_corr_cck_mrc;
814
815 u32 last_bad_plcp_cnt_ofdm;
816 u32 last_fa_cnt_ofdm;
817 u32 last_bad_plcp_cnt_cck;
818 u32 last_fa_cnt_cck;
819
820 u32 nrg_curr_state;
821 u32 nrg_prev_state;
822 u32 nrg_value[10];
823 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
824 u32 nrg_silence_ref;
825 u32 nrg_energy_idx;
826 u32 nrg_silence_idx;
827 u32 nrg_th_cck;
828 s32 nrg_auto_corr_silence_diff;
829 u32 num_in_cck_no_fa;
830 u32 nrg_th_ofdm;
55036d66
WYG
831
832 u16 barker_corr_th_min;
833 u16 barker_corr_th_min_mrc;
834 u16 nrg_th_cca;
b481de9c
ZY
835};
836
837/* Chain noise (differential Rx gain) calib data */
f0832f13 838struct iwl_chain_noise_data {
04816448 839 u32 active_chains;
b481de9c
ZY
840 u32 chain_noise_a;
841 u32 chain_noise_b;
842 u32 chain_noise_c;
843 u32 chain_signal_a;
844 u32 chain_signal_b;
845 u32 chain_signal_c;
04816448 846 u16 beacon_count;
b481de9c
ZY
847 u8 disconn_array[NUM_RX_CHAINS];
848 u8 delta_gain_code[NUM_RX_CHAINS];
849 u8 radio_write;
04816448 850 u8 state;
b481de9c
ZY
851};
852
abceddb4
BC
853#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
854#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 855
20594eb0
WYG
856#define IWL_TRAFFIC_ENTRIES (256)
857#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 858
5d08cd1d
CH
859enum {
860 MEASUREMENT_READY = (1 << 0),
861 MEASUREMENT_ACTIVE = (1 << 1),
862};
863
0848e297
WYG
864enum iwl_nvm_type {
865 NVM_DEVICE_TYPE_EEPROM = 0,
866 NVM_DEVICE_TYPE_OTP,
867};
868
415e4993
WYG
869/*
870 * Two types of OTP memory access modes
871 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
872 * based on physical memory addressing
873 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
874 * based on logical memory addressing
875 */
876enum iwl_access_mode {
877 IWL_OTP_ACCESS_ABSOLUTE,
878 IWL_OTP_ACCESS_RELATIVE,
879};
65b7998a
WYG
880
881/**
882 * enum iwl_pa_type - Power Amplifier type
883 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
884 * @IWL_PA_INTERNAL: use Internal only
885 */
886enum iwl_pa_type {
887 IWL_PA_SYSTEM = 0,
740e7f51 888 IWL_PA_INTERNAL = 1,
65b7998a
WYG
889};
890
a83b9141
WYG
891/* interrupt statistics */
892struct isr_statistics {
893 u32 hw;
894 u32 sw;
6e6ebf4b 895 u32 err_code;
a83b9141
WYG
896 u32 sch;
897 u32 alive;
898 u32 rfkill;
899 u32 ctkill;
900 u32 wakeup;
901 u32 rx;
902 u32 rx_handlers[REPLY_MAX];
903 u32 tx;
904 u32 unhandled;
905};
5d08cd1d 906
91835ba4
WYG
907/* reply_tx_statistics (for _agn devices) */
908struct reply_tx_error_statistics {
909 u32 pp_delay;
910 u32 pp_few_bytes;
911 u32 pp_bt_prio;
912 u32 pp_quiet_period;
913 u32 pp_calc_ttak;
914 u32 int_crossed_retry;
915 u32 short_limit;
916 u32 long_limit;
917 u32 fifo_underrun;
918 u32 drain_flow;
919 u32 rfkill_flush;
920 u32 life_expire;
921 u32 dest_ps;
922 u32 host_abort;
923 u32 bt_retry;
924 u32 sta_invalid;
925 u32 frag_drop;
926 u32 tid_disable;
927 u32 fifo_flush;
928 u32 insuff_cf_poll;
929 u32 fail_hw_drop;
930 u32 sta_color_mismatch;
931 u32 unknown;
932};
933
814665fe
WYG
934/* reply_agg_tx_statistics (for _agn devices) */
935struct reply_agg_tx_error_statistics {
936 u32 underrun;
937 u32 bt_prio;
938 u32 few_bytes;
939 u32 abort;
940 u32 last_sent_ttl;
941 u32 last_sent_try;
942 u32 last_sent_bt_kill;
943 u32 scd_query;
944 u32 bad_crc32;
945 u32 response;
946 u32 dump_tx;
947 u32 delay_tx;
948 u32 unknown;
949};
950
22fdf3c9
WYG
951/* management statistics */
952enum iwl_mgmt_stats {
953 MANAGEMENT_ASSOC_REQ = 0,
954 MANAGEMENT_ASSOC_RESP,
955 MANAGEMENT_REASSOC_REQ,
956 MANAGEMENT_REASSOC_RESP,
957 MANAGEMENT_PROBE_REQ,
958 MANAGEMENT_PROBE_RESP,
959 MANAGEMENT_BEACON,
960 MANAGEMENT_ATIM,
961 MANAGEMENT_DISASSOC,
962 MANAGEMENT_AUTH,
963 MANAGEMENT_DEAUTH,
964 MANAGEMENT_ACTION,
965 MANAGEMENT_MAX,
966};
967/* control statistics */
968enum iwl_ctrl_stats {
969 CONTROL_BACK_REQ = 0,
970 CONTROL_BACK,
971 CONTROL_PSPOLL,
972 CONTROL_RTS,
973 CONTROL_CTS,
974 CONTROL_ACK,
975 CONTROL_CFEND,
976 CONTROL_CFENDACK,
977 CONTROL_MAX,
978};
979
980struct traffic_stats {
5ed540ae 981#ifdef CONFIG_IWLWIFI_DEBUGFS
22fdf3c9
WYG
982 u32 mgmt[MANAGEMENT_MAX];
983 u32 ctrl[CONTROL_MAX];
984 u32 data_cnt;
985 u64 data_bytes;
22fdf3c9 986#endif
5ed540ae 987};
22fdf3c9 988
a9e1cb6a
WYG
989/*
990 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
991 * to perform continuous uCode event logging operation if enabled
992 */
993#define UCODE_TRACE_PERIOD (100)
994
995/*
996 * iwl_event_log: current uCode event log position
997 *
998 * @ucode_trace: enable/disable ucode continuous trace timer
999 * @num_wraps: how many times the event buffer wraps
1000 * @next_entry: the entry just before the next one that uCode would fill
1001 * @non_wraps_count: counter for no wrap detected when dump ucode events
1002 * @wraps_once_count: counter for wrap once detected when dump ucode events
1003 * @wraps_more_count: counter for wrap more than once detected
1004 * when dump ucode events
1005 */
1006struct iwl_event_log {
1007 bool ucode_trace;
1008 u32 num_wraps;
1009 u32 next_entry;
1010 int non_wraps_count;
1011 int wraps_once_count;
1012 int wraps_more_count;
1013};
1014
2be76703
WYG
1015/*
1016 * host interrupt timeout value
1017 * used with setting interrupt coalescing timer
1018 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1019 *
1020 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1021 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1022 */
1023#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1024#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1025#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1026#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1027#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1028#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1029
3e4fb5fa
TAN
1030/*
1031 * This is the threshold value of plcp error rate per 100mSecs. It is
1032 * used to set and check for the validity of plcp_delta.
1033 */
680788ac 1034#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1035#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1036#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1037#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1038#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1039#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1040
8a472da4
WYG
1041#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1042#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1043
22de94de
SG
1044/* TX queue watchdog timeouts in mSecs */
1045#define IWL_DEF_WD_TIMEOUT (2000)
1046#define IWL_LONG_WD_TIMEOUT (10000)
1047#define IWL_MAX_WD_TIMEOUT (120000)
b74e31a9 1048
bee008b7
WYG
1049/* BT Antenna Coupling Threshold (dB) */
1050#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1051
491bc292
WYG
1052/* Firmware reload counter and Timestamp */
1053#define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */
1054#define IWL_MAX_CONTINUE_RELOAD_CNT 4
1055
1056
a93e7973
WYG
1057enum iwl_reset {
1058 IWL_RF_RESET = 0,
1059 IWL_FW_RESET,
8a472da4
WYG
1060 IWL_MAX_FORCE_RESET,
1061};
1062
1063struct iwl_force_reset {
1064 int reset_request_count;
1065 int reset_success_count;
1066 int reset_reject_count;
1067 unsigned long reset_duration;
1068 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1069};
1070
a0ee74cf 1071/* extend beacon time format bit shifting */
a0ee74cf
WYG
1072/*
1073 * for _agn devices
1074 * bits 31:22 - extended
1075 * bits 21:0 - interval
1076 */
1077#define IWLAGN_EXT_BEACON_TIME_POS 22
1078
7194207c
JB
1079/**
1080 * struct iwl_notification_wait - notification wait entry
1081 * @list: list head for global list
1082 * @fn: function called with the notification
1083 * @cmd: command ID
1084 *
1085 * This structure is not used directly, to wait for a
1086 * notification declare it on the stack, and call
1087 * iwlagn_init_notification_wait() with appropriate
1088 * parameters. Then do whatever will cause the ucode
1089 * to notify the driver, and to wait for that then
1090 * call iwlagn_wait_notification().
1091 *
1092 * Each notification is one-shot. If at some point we
1093 * need to support multi-shot notifications (which
1094 * can't be allocated on the stack) we need to modify
1095 * the code for them.
1096 */
1097struct iwl_notification_wait {
1098 struct list_head list;
1099
09f18afe
JB
1100 void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt,
1101 void *data);
1102 void *fn_data;
7194207c
JB
1103
1104 u8 cmd;
e74fe233 1105 bool triggered, aborted;
7194207c
JB
1106};
1107
246ed355
JB
1108enum iwl_rxon_context_id {
1109 IWL_RXON_CTX_BSS,
ece9c4ee 1110 IWL_RXON_CTX_PAN,
246ed355
JB
1111
1112 NUM_IWL_RXON_CTX
1113};
1114
1115struct iwl_rxon_context {
8bd413e6 1116 struct ieee80211_vif *vif;
e72f368b
JB
1117
1118 const u8 *ac_to_fifo;
1119 const u8 *ac_to_queue;
1120 u8 mcast_queue;
1121
763cc3bf
JB
1122 /*
1123 * We could use the vif to indicate active, but we
1124 * also need it to be active during disabling when
1125 * we already removed the vif for type setting.
1126 */
1127 bool always_active, is_active;
1128
2295c66b
JB
1129 bool ht_need_multiple_chains;
1130
246ed355 1131 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1132
1133 u32 interface_modes, exclusive_interface_modes;
1134 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1135
246ed355
JB
1136 /*
1137 * We declare this const so it can only be
1138 * changed via explicit cast within the
1139 * routines that actually update the physical
1140 * hardware.
1141 */
1142 const struct iwl_rxon_cmd active;
1143 struct iwl_rxon_cmd staging;
1144
1145 struct iwl_rxon_time_cmd timing;
a194e324 1146
8dfdb9d5
JB
1147 struct iwl_qos_info qos_data;
1148
2995bafa 1149 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1150
1151 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1152 u8 qos_cmd;
c10afb6e
JB
1153 u8 wep_key_cmd;
1154
1155 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1156 u8 key_mapping_keys;
770e13bd
JB
1157
1158 __le32 station_flags;
7e6a5886
JB
1159
1160 struct {
1161 bool non_gf_sta_present;
1162 u8 protection;
1163 bool enabled, is_40mhz;
1164 u8 extension_chan_offset;
1165 } ht;
68b99311
GT
1166
1167 bool last_tx_rejected;
246ed355
JB
1168};
1169
266af4c7
JB
1170enum iwl_scan_type {
1171 IWL_SCAN_NORMAL,
1172 IWL_SCAN_RADIO_RESET,
1173 IWL_SCAN_OFFCH_TX,
1174};
1175
872907bb
JB
1176enum iwlagn_ucode_type {
1177 IWL_UCODE_NONE,
1178 IWL_UCODE_REGULAR,
1179 IWL_UCODE_INIT,
1180 IWL_UCODE_WOWLAN,
1181};
1182
7a4e5281
WYG
1183#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1184struct iwl_testmode_trace {
49b72100
WYG
1185 u32 buff_size;
1186 u32 total_size;
eb64dca0 1187 u32 num_chunks;
7a4e5281
WYG
1188 u8 *cpu_addr;
1189 u8 *trace_addr;
1190 dma_addr_t dma_addr;
1191 bool trace_enabled;
1192};
1193#endif
a48709c5
EG
1194
1195struct iwl_bus;
1196
1197/**
1198 * struct iwl_bus_ops - bus specific operations
d57fa99d
WYG
1199
1200 * @get_pm_support: must returns true if the bus can go to sleep
1201 * @apm_config: will be called during the config of the APM configuration
a48709c5 1202 * @set_drv_data: set the priv pointer to the bus layer
3599d39a 1203 * @get_dev: returns the device struct
08321c06 1204 * @get_irq: returns the irq number
19707bac 1205 * @get_hw_id: prints the hw_id in the provided buffer
084dd791
EG
1206 * @write8: write a byte to register at offset ofs
1207 * @write32: write a dword to register at offset ofs
1208 * @wread32: read a dword at register at offset ofs
a48709c5
EG
1209 */
1210struct iwl_bus_ops {
d57fa99d
WYG
1211 bool (*get_pm_support)(struct iwl_bus *bus);
1212 void (*apm_config)(struct iwl_bus *bus);
a48709c5 1213 void (*set_drv_data)(struct iwl_bus *bus, void *priv);
3599d39a 1214 struct device *(*get_dev)(const struct iwl_bus *bus);
08321c06 1215 unsigned int (*get_irq)(const struct iwl_bus *bus);
19707bac 1216 void (*get_hw_id)(struct iwl_bus *bus, char buf[], int buf_len);
084dd791
EG
1217 void (*write8)(struct iwl_bus *bus, u32 ofs, u8 val);
1218 void (*write32)(struct iwl_bus *bus, u32 ofs, u32 val);
1219 u32 (*read32)(struct iwl_bus *bus, u32 ofs);
a48709c5
EG
1220};
1221
1222struct iwl_bus {
1223 /* pointer to bus specific struct */
1224 void *bus_specific;
1225
1226 /* Common data to all buses */
1227 struct iwl_priv *priv; /* driver's context */
3599d39a 1228 struct device *dev;
a48709c5 1229 struct iwl_bus_ops *ops;
705cd451 1230 unsigned int irq;
a48709c5
EG
1231};
1232
c85eb619
EG
1233struct iwl_trans;
1234
1235/**
1236 * struct iwl_trans_ops - transport specific operations
1237
1238 * @rx_init: inits the rx memory, allocate it if needed
c2c52e8b 1239 * @rx_stop: stop the rx
02aca585
EG
1240 * @rx_free: frees the rx memory
1241 * @tx_init:inits the tx memory, allocate if needed
c170b867 1242 * @tx_stop: stop the tx
1359ca4f 1243 * @tx_free: frees the tx memory
e419d62d
EG
1244 * @send_cmd:send a host command
1245 * @send_cmd_pdu:send a host command: flags can be CMD_*
a27367d2
EG
1246 * @sync_irq: the upper layer will typically disable interrupt and call this
1247 * handler. After this handler returns, it is guaranteed that all
1248 * the ISR / tasklet etc... have finished running and the transport
1249 * layer shall not pass any Rx.
34c1b7ba
EG
1250 * @free: release all the ressource for the transport layer itself such as
1251 * irq, tasklet etc...
c85eb619
EG
1252 */
1253struct iwl_trans_ops {
1254 int (*rx_init)(struct iwl_priv *priv);
c2c52e8b 1255 int (*rx_stop)(struct iwl_priv *priv);
a0f6b0a2 1256 void (*rx_free)(struct iwl_priv *priv);
1359ca4f 1257
02aca585 1258 int (*tx_init)(struct iwl_priv *priv);
c170b867 1259 int (*tx_stop)(struct iwl_priv *priv);
1359ca4f 1260 void (*tx_free)(struct iwl_priv *priv);
e419d62d
EG
1261
1262 int (*send_cmd)(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
1263
1264 int (*send_cmd_pdu)(struct iwl_priv *priv, u8 id, u32 flags, u16 len,
1265 const void *data);
47c1b496
EG
1266 struct iwl_tx_cmd * (*get_tx_cmd)(struct iwl_priv *priv, int txq_id);
1267 int (*tx)(struct iwl_priv *priv, struct sk_buff *skb,
1268 struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
1269 struct iwl_rxon_context *ctx);
34c1b7ba 1270
a27367d2 1271 void (*sync_irq)(struct iwl_priv *priv);
34c1b7ba 1272 void (*free)(struct iwl_priv *priv);
c85eb619
EG
1273};
1274
1275struct iwl_trans {
1276 const struct iwl_trans_ops *ops;
1277};
1278
e98a1939
WYG
1279/* uCode ownership */
1280#define IWL_OWNERSHIP_DRIVER 0
1281#define IWL_OWNERSHIP_TM 1
1282
c79dd5b5 1283struct iwl_priv {
5d08cd1d
CH
1284
1285 /* ieee device used by generic ieee processing code */
1286 struct ieee80211_hw *hw;
1287 struct ieee80211_channel *ieee_channels;
1288 struct ieee80211_rate *ieee_rates;
82b9a121 1289 struct iwl_cfg *cfg;
5d08cd1d 1290
8318d78a 1291 enum ieee80211_band band;
5d08cd1d 1292
4613e72d
CK
1293 void (*pre_rx_handler)(struct iwl_priv *priv,
1294 struct iwl_rx_mem_buffer *rxb);
c79dd5b5 1295 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1296 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1297
8318d78a 1298 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1299
5d08cd1d 1300 /* spectrum measurement report caching */
2aa6ab86 1301 struct iwl_spectrum_notification measure_report;
5d08cd1d 1302 u8 measurement_status;
81963d68 1303
5d08cd1d
CH
1304 /* ucode beacon time */
1305 u32 ucode_beacon_time;
a13d276f 1306 int missed_beacon_threshold;
5d08cd1d 1307
a85d7cca
JB
1308 /* track IBSS manager (last beacon) status */
1309 u32 ibss_manager;
1310
410f2bb3
SG
1311 /* jiffies when last recovery from statistics was performed */
1312 unsigned long rx_statistics_jiffies;
3e4fb5fa 1313
a93e7973 1314 /* force reset */
8a472da4 1315 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1316
491bc292
WYG
1317 /* firmware reload counter and timestamp */
1318 unsigned long reload_jiffies;
1319 int reload_count;
1320
5a2a780c 1321 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1322 * Access via channel # using indirect index array */
bf85ea4f 1323 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1324 u8 channel_count; /* # of channels */
1325
5d08cd1d
CH
1326 /* thermal calibration */
1327 s32 temperature; /* degrees Kelvin */
1328 s32 last_temperature;
1329
7c616cba 1330 /* init calibration results */
6e21f2c1 1331 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1332
5d08cd1d 1333 /* Scan related variables */
5d08cd1d 1334 unsigned long scan_start;
5d08cd1d 1335 unsigned long scan_start_tsf;
811ecc99 1336 void *scan_cmd;
00700ee0 1337 enum ieee80211_band scan_band;
1ecf9fc1 1338 struct cfg80211_scan_request *scan_request;
f84b29ec 1339 struct ieee80211_vif *scan_vif;
266af4c7 1340 enum iwl_scan_type scan_type;
76eff18b
TW
1341 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1342 u8 mgmt_tx_ant;
5d08cd1d
CH
1343
1344 /* spinlock */
1345 spinlock_t lock; /* protect general shared data */
1346 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1347 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d
CH
1348 struct mutex mutex;
1349
a48709c5 1350 struct iwl_bus bus; /* bus specific data */
c85eb619 1351 struct iwl_trans trans;
a48709c5 1352
246ed355
JB
1353 /* microcode/device supports multiple contexts */
1354 u8 valid_contexts;
1355
13bb9483
JB
1356 /* command queue number */
1357 u8 cmd_queue;
1358
c10afb6e
JB
1359 /* max number of station keys */
1360 u8 sta_key_max_num;
1361
d2690c0d
JB
1362 bool new_scan_threshold_behaviour;
1363
c6fa17ed
WYG
1364 /* EEPROM MAC addresses */
1365 struct mac_address addresses[2];
1366
5d08cd1d 1367 /* uCode images, save to reload in case of failure */
b08dfd04 1368 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1369 u32 ucode_ver; /* version of ucode, copy of
1370 iwl_ucode.ver */
e98a1939
WYG
1371
1372 /* uCode owner: default: IWL_OWNERSHIP_DRIVER */
1373 u8 ucode_owner;
1374
dbf28e21
JB
1375 struct fw_img ucode_rt;
1376 struct fw_img ucode_init;
1377
872907bb 1378 enum iwlagn_ucode_type ucode_type;
dbb983b7 1379 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1380 char firmware_name[25];
5d08cd1d 1381
246ed355 1382 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1383
6f213ff1 1384 __le16 switch_channel;
0924e519 1385
d7d5783c
JB
1386 struct {
1387 u32 error_event_table;
1388 u32 log_event_table;
1389 } device_pointers;
5d08cd1d 1390
5d08cd1d 1391 u16 active_rate;
5d08cd1d 1392
5d08cd1d 1393 u8 start_calib;
f0832f13
EG
1394 struct iwl_sensitivity_data sensitivity_data;
1395 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1396 bool enhance_sensitivity_table;
5d08cd1d 1397 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1398 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1399
fad95bf5 1400 struct iwl_ht_config current_ht_config;
5d08cd1d 1401
5d08cd1d 1402 /* Rate scaling data */
5d08cd1d
CH
1403 u8 retry_rate;
1404
1405 wait_queue_head_t wait_command_queue;
1406
1407 int activity_timer_active;
1408
1409 /* Rx and Tx DMA processing queues */
a55360e4 1410 struct iwl_rx_queue rxq;
88804e2b 1411 struct iwl_tx_queue *txq;
5d08cd1d 1412 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1413 struct iwl_dma_ptr kw; /* keep warm address */
1414 struct iwl_dma_ptr scd_bc_tbls;
1415
5d08cd1d
CH
1416 u32 scd_base_addr; /* scheduler sram base address */
1417
1418 unsigned long status;
5d08cd1d 1419
19758bef 1420 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1421 struct traffic_stats tx_stats;
1422 struct traffic_stats rx_stats;
19758bef 1423
a83b9141
WYG
1424 /* counts interrupts */
1425 struct isr_statistics isr_stats;
1426
5da4b55f 1427 struct iwl_power_mgr power_data;
3ad3b92a 1428 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1429
9c5ac091
RC
1430 /* station table variables */
1431
1432 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1433 spinlock_t sta_lock;
1434 int num_stations;
3240cab3 1435 struct iwl_station_entry stations[IWLAGN_STATION_COUNT];
80fb47a1 1436 unsigned long ucode_key_table;
5d08cd1d 1437
e4e72fb4
JB
1438 /* queue refcounts */
1439#define IWL_MAX_HW_QUEUES 32
1440 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1441 /* for each AC */
1442 atomic_t queue_stop_count[4];
1443
5d08cd1d 1444 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1445 u8 is_open;
5d08cd1d
CH
1446
1447 u8 mac80211_registered;
5d08cd1d 1448
af6b8ee3 1449 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1450 u8 *eeprom;
0848e297 1451 int nvm_device_type;
073d3f5f 1452 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1453
05c914fe 1454 enum nl80211_iftype iw_mode;
5d08cd1d 1455
5d08cd1d 1456 /* Last Rx'd beacon timestamp */
3109ece1 1457 u64 timestamp;
5d08cd1d 1458
0da0e5bf
JB
1459 struct {
1460 __le32 flag;
1461 struct statistics_general_common common;
1462 struct statistics_rx_non_phy rx_non_phy;
1463 struct statistics_rx_phy rx_ofdm;
1464 struct statistics_rx_ht_phy rx_ofdm_ht;
1465 struct statistics_rx_phy rx_cck;
1466 struct statistics_tx tx;
1467#ifdef CONFIG_IWLWIFI_DEBUGFS
1468 struct statistics_bt_activity bt_activity;
1469 __le32 num_bt_kills, accum_num_bt_kills;
1470#endif
1471 } statistics;
1472#ifdef CONFIG_IWLWIFI_DEBUGFS
1473 struct {
1474 struct statistics_general_common common;
1475 struct statistics_rx_non_phy rx_non_phy;
1476 struct statistics_rx_phy rx_ofdm;
1477 struct statistics_rx_ht_phy rx_ofdm_ht;
1478 struct statistics_rx_phy rx_cck;
1479 struct statistics_tx tx;
1480 struct statistics_bt_activity bt_activity;
1481 } accum_stats, delta_stats, max_delta_stats;
1482#endif
1483
3240cab3
JB
1484 struct {
1485 /* INT ICT Table */
1486 __le32 *ict_tbl;
1487 void *ict_tbl_vir;
1488 dma_addr_t ict_tbl_dma;
1489 dma_addr_t aligned_ict_tbl_dma;
1490 int ict_index;
1491 u32 inta;
1492 bool use_ict;
1493 /*
1494 * reporting the number of tids has AGG on. 0 means
1495 * no AGGREGATION
1496 */
1497 u8 agg_tids_count;
1498
1499 struct iwl_rx_phy_res last_phy_res;
1500 bool last_phy_res_valid;
1501
1502 struct completion firmware_loading_complete;
1503
1504 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1505 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1506
1507 /*
1508 * chain noise reset and gain commands are the
1509 * two extra calibration commands follows the standard
1510 * phy calibration commands
1511 */
1512 u8 phy_calib_chain_noise_reset_cmd;
1513 u8 phy_calib_chain_noise_gain_cmd;
1514
3240cab3
JB
1515 /* counts reply_tx error */
1516 struct reply_tx_error_statistics reply_tx_stats;
1517 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
3240cab3
JB
1518 /* notification wait support */
1519 struct list_head notif_waits;
1520 spinlock_t notif_wait_lock;
1521 wait_queue_head_t notif_waitq;
1522
1523 /* remain-on-channel offload support */
1524 struct ieee80211_channel *hw_roc_channel;
1525 struct delayed_work hw_roc_work;
1526 enum nl80211_channel_type hw_roc_chantype;
1527 int hw_roc_duration;
1528 bool hw_roc_setup;
1529
1530 struct sk_buff *offchan_tx_skb;
1531 int offchan_tx_timeout;
1532 struct ieee80211_channel *offchan_tx_chan;
1533 } _agn;
ee525d13 1534
22bf59a0 1535 /* bt coex */
f21dd005 1536 u8 bt_enable_flag;
da5dbb97 1537 u8 bt_status;
66e863a5 1538 u8 bt_traffic_load, last_bt_traffic_load;
f37837c9 1539 bool bt_ch_announce;
bee008b7
WYG
1540 bool bt_full_concurrent;
1541 bool bt_ant_couple_ok;
fbba9410
WYG
1542 __le32 kill_ack_mask;
1543 __le32 kill_cts_mask;
1544 __le16 bt_valid;
22bf59a0
WYG
1545 u16 bt_on_thresh;
1546 u16 bt_duration;
1547 u16 dynamic_frag_thresh;
bee008b7 1548 u8 bt_ci_compliance;
9e4afc21 1549 struct work_struct bt_traffic_change_work;
207ecc5e
MV
1550 bool bt_enable_pspoll;
1551 struct iwl_rxon_context *cur_rssi_ctx;
1552 bool bt_is_sco;
9e4afc21 1553
5425e490 1554 struct iwl_hw_params hw_params;
4ddbb7d0 1555
40cefda9 1556 u32 inta_mask;
5d08cd1d 1557
5d08cd1d
CH
1558 struct workqueue_struct *workqueue;
1559
5d08cd1d 1560 struct work_struct restart;
5d08cd1d
CH
1561 struct work_struct scan_completed;
1562 struct work_struct rx_replenish;
5d08cd1d 1563 struct work_struct abort_scan;
12e934dc 1564
5d08cd1d 1565 struct work_struct beacon_update;
76d04815 1566 struct iwl_rxon_context *beacon_ctx;
12e934dc 1567 struct sk_buff *beacon_skb;
4ce7cc2b 1568 void *beacon_cmd;
76d04815 1569
a28027cd
WYG
1570 struct work_struct tt_work;
1571 struct work_struct ct_enter;
1572 struct work_struct ct_exit;
88be0264 1573 struct work_struct start_internal_scan;
65550636 1574 struct work_struct tx_flush;
bee008b7 1575 struct work_struct bt_full_concurrency;
fbba9410 1576 struct work_struct bt_runtime_config;
5d08cd1d
CH
1577
1578 struct tasklet_struct irq_tasklet;
1579
5d08cd1d 1580 struct delayed_work scan_check;
4a8a4322 1581
630fe9b6
TW
1582 /* TX Power */
1583 s8 tx_power_user_lmt;
dc1b0973 1584 s8 tx_power_device_lmt;
ae16fc3c 1585 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
a25a66ac 1586 s8 tx_power_next;
5d08cd1d 1587
5d08cd1d 1588
d08853a3 1589#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1590 /* debugging info */
3d816c77
RC
1591 u32 debug_level; /* per device debugging will override global
1592 iwl_debug_level if set */
d73e4923 1593#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1594#ifdef CONFIG_IWLWIFI_DEBUGFS
1595 /* debugfs */
20594eb0
WYG
1596 u16 tx_traffic_idx;
1597 u16 rx_traffic_idx;
1598 u8 *tx_traffic;
1599 u8 *rx_traffic;
4c84a8f1
JB
1600 struct dentry *debugfs_dir;
1601 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1602 bool disable_ht40;
712b6cf5 1603#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1604
1605 struct work_struct txpower_work;
445c2dff
TW
1606 u32 disable_sens_cal;
1607 u32 disable_chain_noise_cal;
16e727e8 1608 struct work_struct run_time_calib_work;
5d08cd1d 1609 struct timer_list statistics_periodic;
a9e1cb6a 1610 struct timer_list ucode_trace;
22de94de 1611 struct timer_list watchdog;
a9e1cb6a
WYG
1612
1613 struct iwl_event_log event_log;
5ed540ae
WYG
1614
1615 struct led_classdev led;
1616 unsigned long blink_on, blink_off;
1617 bool led_registered;
7a4e5281
WYG
1618#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1619 struct iwl_testmode_trace testmode_trace;
1620#endif
4e308119 1621 u32 tm_fixed_rate;
6489854b 1622
c79dd5b5 1623}; /*iwl_priv */
5d08cd1d 1624
36470749
RR
1625static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1626{
1627 set_bit(txq_id, &priv->txq_ctx_active_msk);
1628}
1629
1630static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1631{
1632 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1633}
1634
994d31f7 1635#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1636/*
1637 * iwl_get_debug_level: Return active debug level for device
1638 *
1639 * Using sysfs it is possible to set per device debug level. This debug
1640 * level will be used if set, otherwise the global debug level which can be
1641 * set via module parameter is used.
1642 */
1643static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1644{
1645 if (priv->debug_level)
1646 return priv->debug_level;
1647 else
1648 return iwl_debug_level;
1649}
a332f8d6 1650#else
3d816c77
RC
1651static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1652{
1653 return iwl_debug_level;
1654}
a332f8d6
TW
1655#endif
1656
1657
a332f8d6
TW
1658static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1659 int txq_id, int idx)
1660{
ff0d91c3 1661 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1662 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1663 txb[idx].skb->data;
a332f8d6
TW
1664 return NULL;
1665}
a332f8d6 1666
246ed355
JB
1667static inline struct iwl_rxon_context *
1668iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1669{
1670 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1671
1672 return vif_priv->ctx;
1673}
1674
1675#define for_each_context(priv, ctx) \
1676 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1677 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1678 if (priv->valid_contexts & BIT(ctx->ctxid))
1679
054ec924 1680static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
246ed355 1681{
054ec924 1682 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
246ed355
JB
1683}
1684
054ec924
JB
1685static inline int iwl_is_associated(struct iwl_priv *priv,
1686 enum iwl_rxon_context_id ctxid)
246ed355 1687{
054ec924 1688 return iwl_is_associated_ctx(&priv->contexts[ctxid]);
246ed355 1689}
a332f8d6 1690
054ec924 1691static inline int iwl_is_any_associated(struct iwl_priv *priv)
5d08cd1d 1692{
054ec924
JB
1693 struct iwl_rxon_context *ctx;
1694 for_each_context(priv, ctx)
1695 if (iwl_is_associated_ctx(ctx))
1696 return true;
1697 return false;
5d08cd1d
CH
1698}
1699
bf85ea4f 1700static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1701{
1702 if (ch_info == NULL)
1703 return 0;
1704 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1705}
1706
bf85ea4f 1707static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1708{
1709 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1710}
1711
bf85ea4f 1712static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1713{
8318d78a 1714 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1715}
1716
bf85ea4f 1717static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1718{
8318d78a 1719 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1720}
1721
bf85ea4f 1722static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1723{
1724 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1725}
1726
bf85ea4f 1727static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1728{
1729 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1730}
1731
64a76b50
ZY
1732static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1733{
1734 __free_pages(page, priv->hw_params.rx_page_order);
64a76b50
ZY
1735}
1736
1737static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1738{
1739 free_pages(page, priv->hw_params.rx_page_order);
64a76b50 1740}
be1f3ab6 1741#endif /* __iwl_dev_h__ */