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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
fcd427bb | 26 | /* |
3e0d4cb1 | 27 | * Please use this file (iwl-dev.h) for driver implementation definitions. |
5a36ba0e | 28 | * Please use iwl-commands.h for uCode API definitions. |
fcd427bb BC |
29 | * Please use iwl-4965-hw.h for hardware-related definitions. |
30 | */ | |
31 | ||
be1f3ab6 EG |
32 | #ifndef __iwl_dev_h__ |
33 | #define __iwl_dev_h__ | |
b481de9c | 34 | |
5d08cd1d CH |
35 | #include <linux/pci.h> /* for struct pci_device_id */ |
36 | #include <linux/kernel.h> | |
37 | #include <net/ieee80211_radiotap.h> | |
38 | ||
6bc913bd | 39 | #include "iwl-eeprom.h" |
6f83eaa1 | 40 | #include "iwl-csr.h" |
5d08cd1d | 41 | #include "iwl-prph.h" |
dbb6654c | 42 | #include "iwl-fh.h" |
0a6857e7 | 43 | #include "iwl-debug.h" |
dbb6654c WT |
44 | #include "iwl-4965-hw.h" |
45 | #include "iwl-3945-hw.h" | |
46 | #include "iwl-3945-led.h" | |
ab53d8af | 47 | #include "iwl-led.h" |
5da4b55f | 48 | #include "iwl-power.h" |
e227ceac | 49 | #include "iwl-agn-rs.h" |
5d08cd1d | 50 | |
fed9017e RR |
51 | /* configuration for the iwl4965 */ |
52 | extern struct iwl_cfg iwl4965_agn_cfg; | |
5a6a256e TW |
53 | extern struct iwl_cfg iwl5300_agn_cfg; |
54 | extern struct iwl_cfg iwl5100_agn_cfg; | |
55 | extern struct iwl_cfg iwl5350_agn_cfg; | |
47408639 EK |
56 | extern struct iwl_cfg iwl5100_bg_cfg; |
57 | extern struct iwl_cfg iwl5100_abg_cfg; | |
7100e924 | 58 | extern struct iwl_cfg iwl5150_agn_cfg; |
65b7998a WYG |
59 | extern struct iwl_cfg iwl6000h_2agn_cfg; |
60 | extern struct iwl_cfg iwl6000i_2agn_cfg; | |
e1228374 JS |
61 | extern struct iwl_cfg iwl6000_3agn_cfg; |
62 | extern struct iwl_cfg iwl6050_2agn_cfg; | |
63 | extern struct iwl_cfg iwl6050_3agn_cfg; | |
77dcb6a9 | 64 | extern struct iwl_cfg iwl1000_bgn_cfg; |
fed9017e | 65 | |
672639de WYG |
66 | struct iwl_tx_queue; |
67 | ||
cec2d3f3 JS |
68 | /* shared structures from iwl-5000.c */ |
69 | extern struct iwl_mod_params iwl50_mod_params; | |
70 | extern struct iwl_ops iwl5000_ops; | |
cc0f555d | 71 | extern struct iwl_ucode_ops iwl5000_ucode; |
e8c00dcb JS |
72 | extern struct iwl_lib_ops iwl5000_lib; |
73 | extern struct iwl_hcmd_ops iwl5000_hcmd; | |
74 | extern struct iwl_hcmd_utils_ops iwl5000_hcmd_utils; | |
75 | ||
76 | /* shared functions from iwl-5000.c */ | |
77 | extern u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len); | |
78 | extern u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, | |
79 | u8 *data); | |
80 | extern void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, | |
81 | __le32 *tx_flags); | |
82 | extern int iwl5000_calc_rssi(struct iwl_priv *priv, | |
83 | struct iwl_rx_phy_res *rx_resp); | |
672639de WYG |
84 | extern int iwl5000_apm_init(struct iwl_priv *priv); |
85 | extern void iwl5000_apm_stop(struct iwl_priv *priv); | |
86 | extern int iwl5000_apm_reset(struct iwl_priv *priv); | |
87 | extern void iwl5000_nic_config(struct iwl_priv *priv); | |
88 | extern u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv); | |
89 | extern const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, | |
90 | size_t offset); | |
91 | extern void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |
92 | struct iwl_tx_queue *txq, | |
93 | u16 byte_cnt); | |
94 | extern void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, | |
95 | struct iwl_tx_queue *txq); | |
96 | extern int iwl5000_load_ucode(struct iwl_priv *priv); | |
97 | extern void iwl5000_init_alive_start(struct iwl_priv *priv); | |
98 | extern int iwl5000_alive_notify(struct iwl_priv *priv); | |
99 | extern int iwl5000_hw_set_hw_params(struct iwl_priv *priv); | |
100 | extern int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |
101 | int tx_fifo, int sta_id, int tid, u16 ssn_idx); | |
102 | extern int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | |
103 | u16 ssn_idx, u8 tx_fifo); | |
104 | extern void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask); | |
105 | extern void iwl5000_setup_deferred_work(struct iwl_priv *priv); | |
106 | extern void iwl5000_rx_handler_setup(struct iwl_priv *priv); | |
107 | extern int iwl5000_hw_valid_rtc_data_addr(u32 addr); | |
108 | extern int iwl5000_send_tx_power(struct iwl_priv *priv); | |
109 | extern void iwl5000_temperature(struct iwl_priv *priv); | |
cec2d3f3 | 110 | |
099b40b7 | 111 | /* CT-KILL constants */ |
672639de WYG |
112 | #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */ |
113 | #define CT_KILL_THRESHOLD 114 /* in Celsius */ | |
114 | #define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ | |
4bf775cd | 115 | |
5d08cd1d CH |
116 | /* Default noise level to report when noise measurement is not available. |
117 | * This may be because we're: | |
118 | * 1) Not associated (4965, no beacon statistics being sent to driver) | |
119 | * 2) Scanning (noise measurement does not apply to associated channel) | |
120 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
121 | * Use default noise value of -127 ... this is below the range of measurable | |
122 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
123 | * Also, -127 works better than 0 when averaging frames with/without | |
124 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
125 | * always negative ... using a negative value as the default keeps all | |
126 | * averages within an s8's (used in some apps) range of negative values. */ | |
127 | #define IWL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
128 | ||
5d08cd1d CH |
129 | /* |
130 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
131 | * Per spec: | |
132 | * a value of 0 means RTS on all data/management packets | |
133 | * a value > max MSDU size means no RTS | |
134 | * else RTS for data/management frames where MPDU is larger | |
135 | * than RTS value. | |
136 | */ | |
137 | #define DEFAULT_RTS_THRESHOLD 2347U | |
138 | #define MIN_RTS_THRESHOLD 0U | |
139 | #define MAX_RTS_THRESHOLD 2347U | |
140 | #define MAX_MSDU_SIZE 2304U | |
141 | #define MAX_MPDU_SIZE 2346U | |
142 | #define DEFAULT_BEACON_INTERVAL 100U | |
143 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
144 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
145 | ||
a55360e4 | 146 | struct iwl_rx_mem_buffer { |
4018517a JB |
147 | dma_addr_t real_dma_addr; |
148 | dma_addr_t aligned_dma_addr; | |
5d08cd1d CH |
149 | struct sk_buff *skb; |
150 | struct list_head list; | |
151 | }; | |
152 | ||
c2acea8e JB |
153 | /* defined below */ |
154 | struct iwl_device_cmd; | |
155 | ||
156 | struct iwl_cmd_meta { | |
157 | /* only for SYNC commands, iff the reply skb is wanted */ | |
158 | struct iwl_host_cmd *source; | |
159 | /* | |
160 | * only for ASYNC commands | |
161 | * (which is somewhat stupid -- look at iwl-sta.c for instance | |
162 | * which duplicates a bunch of code because the callback isn't | |
163 | * invoked for SYNC commands, if it were and its result passed | |
164 | * through it would be simpler...) | |
165 | */ | |
5696aea6 JB |
166 | void (*callback)(struct iwl_priv *priv, |
167 | struct iwl_device_cmd *cmd, | |
168 | struct sk_buff *skb); | |
c2acea8e JB |
169 | |
170 | /* The CMD_SIZE_HUGE flag bit indicates that the command | |
171 | * structure is stored at the end of the shared queue memory. */ | |
172 | u32 flags; | |
173 | ||
174 | DECLARE_PCI_UNMAP_ADDR(mapping) | |
175 | DECLARE_PCI_UNMAP_LEN(len) | |
176 | }; | |
177 | ||
5d08cd1d CH |
178 | /* |
179 | * Generic queue structure | |
180 | * | |
181 | * Contains common data for Rx and Tx queues | |
182 | */ | |
443cfd45 | 183 | struct iwl_queue { |
5d08cd1d CH |
184 | int n_bd; /* number of BDs in this queue */ |
185 | int write_ptr; /* 1-st empty entry (index) host_w*/ | |
186 | int read_ptr; /* last used entry (index) host_r*/ | |
187 | dma_addr_t dma_addr; /* physical addr for BD's */ | |
188 | int n_window; /* safe queue window */ | |
189 | u32 id; | |
190 | int low_mark; /* low watermark, resume queue if free | |
191 | * space more than this */ | |
192 | int high_mark; /* high watermark, stop queue if free | |
193 | * space less than this */ | |
194 | } __attribute__ ((packed)); | |
195 | ||
bc47279f | 196 | /* One for each TFD */ |
8567c63e | 197 | struct iwl_tx_info { |
499b1883 | 198 | struct sk_buff *skb[IWL_NUM_OF_TBS - 1]; |
5d08cd1d CH |
199 | }; |
200 | ||
201 | /** | |
16466903 | 202 | * struct iwl_tx_queue - Tx Queue for DMA |
bc47279f BC |
203 | * @q: generic Rx/Tx queue descriptor |
204 | * @bd: base of circular buffer of TFDs | |
c2acea8e JB |
205 | * @cmd: array of command/TX buffer pointers |
206 | * @meta: array of meta data for each command/tx buffer | |
bc47279f BC |
207 | * @dma_addr_cmd: physical address of cmd/tx buffer array |
208 | * @txb: array of per-TFD driver data | |
209 | * @need_update: indicates need to update read/write index | |
210 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
5d08cd1d | 211 | * |
bc47279f BC |
212 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame |
213 | * descriptors) and required locking structures. | |
5d08cd1d | 214 | */ |
188cf6c7 SO |
215 | #define TFD_TX_CMD_SLOTS 256 |
216 | #define TFD_CMD_SLOTS 32 | |
217 | ||
16466903 | 218 | struct iwl_tx_queue { |
443cfd45 | 219 | struct iwl_queue q; |
59606ffa | 220 | void *tfds; |
c2acea8e JB |
221 | struct iwl_device_cmd **cmd; |
222 | struct iwl_cmd_meta *meta; | |
8567c63e | 223 | struct iwl_tx_info *txb; |
3fd07a1e TW |
224 | u8 need_update; |
225 | u8 sched_retry; | |
226 | u8 active; | |
227 | u8 swq_id; | |
5d08cd1d CH |
228 | }; |
229 | ||
230 | #define IWL_NUM_SCAN_RATES (2) | |
231 | ||
bb8c093b | 232 | struct iwl4965_channel_tgd_info { |
5d08cd1d CH |
233 | u8 type; |
234 | s8 max_power; | |
235 | }; | |
236 | ||
bb8c093b | 237 | struct iwl4965_channel_tgh_info { |
5d08cd1d CH |
238 | s64 last_radar_time; |
239 | }; | |
240 | ||
d20b3c65 SO |
241 | #define IWL4965_MAX_RATE (33) |
242 | ||
85d41495 KA |
243 | struct iwl3945_clip_group { |
244 | /* maximum power level to prevent clipping for each rate, derived by | |
245 | * us from this band's saturation power in EEPROM */ | |
246 | const s8 clip_powers[IWL_MAX_RATES]; | |
247 | }; | |
248 | ||
d20b3c65 SO |
249 | /* current Tx power values to use, one for each rate for each channel. |
250 | * requested power is limited by: | |
251 | * -- regulatory EEPROM limits for this channel | |
252 | * -- hardware capabilities (clip-powers) | |
253 | * -- spectrum management | |
254 | * -- user preference (e.g. iwconfig) | |
255 | * when requested power is set, base power index must also be set. */ | |
256 | struct iwl3945_channel_power_info { | |
257 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
258 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
259 | s8 base_power_index; /* gain index for power at factory temp. */ | |
260 | s8 requested_power; /* power (dBm) requested for this chnl/rate */ | |
261 | }; | |
262 | ||
263 | /* current scan Tx power values to use, one for each scan rate for each | |
264 | * channel. */ | |
265 | struct iwl3945_scan_power_info { | |
266 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
267 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
268 | s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */ | |
269 | }; | |
270 | ||
5d08cd1d CH |
271 | /* |
272 | * One for each channel, holds all channel setup data | |
273 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
274 | * with one another! | |
275 | */ | |
bf85ea4f | 276 | struct iwl_channel_info { |
bb8c093b CH |
277 | struct iwl4965_channel_tgd_info tgd; |
278 | struct iwl4965_channel_tgh_info tgh; | |
073d3f5f | 279 | struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */ |
7aafef1c WYG |
280 | struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for |
281 | * HT40 channel */ | |
5d08cd1d CH |
282 | |
283 | u8 channel; /* channel number */ | |
284 | u8 flags; /* flags copied from EEPROM */ | |
285 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
fcd427bb | 286 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ |
5d08cd1d CH |
287 | s8 min_power; /* always 0 */ |
288 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
289 | ||
290 | u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */ | |
291 | u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */ | |
8318d78a | 292 | enum ieee80211_band band; |
5d08cd1d | 293 | |
7aafef1c WYG |
294 | /* HT40 channel info */ |
295 | s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
296 | s8 ht40_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */ | |
297 | s8 ht40_min_power; /* always 0 */ | |
298 | s8 ht40_scan_power; /* (dBm) eeprom, direct scans, any rate */ | |
299 | u8 ht40_flags; /* flags copied from EEPROM */ | |
300 | u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ | |
d20b3c65 SO |
301 | |
302 | /* Radio/DSP gain settings for each "normal" data Tx rate. | |
303 | * These include, in addition to RF and DSP gain, a few fields for | |
304 | * remembering/modifying gain settings (indexes). */ | |
305 | struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE]; | |
306 | ||
307 | /* Radio/DSP gain settings for each scan rate, for directed scans. */ | |
308 | struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES]; | |
5d08cd1d CH |
309 | }; |
310 | ||
5d08cd1d CH |
311 | #define IWL_TX_FIFO_AC0 0 |
312 | #define IWL_TX_FIFO_AC1 1 | |
313 | #define IWL_TX_FIFO_AC2 2 | |
314 | #define IWL_TX_FIFO_AC3 3 | |
315 | #define IWL_TX_FIFO_HCCA_1 5 | |
316 | #define IWL_TX_FIFO_HCCA_2 6 | |
317 | #define IWL_TX_FIFO_NONE 7 | |
318 | ||
01a7e084 RC |
319 | /* Minimum number of queues. MAX_NUM is defined in hw specific files. |
320 | * Set the minimum to accommodate the 4 standard TX queues, 1 command | |
321 | * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */ | |
322 | #define IWL_MIN_NUM_QUEUES 10 | |
5d08cd1d CH |
323 | |
324 | /* Power management (not Tx power) structures */ | |
325 | ||
6f4083aa TW |
326 | enum iwl_pwr_src { |
327 | IWL_PWR_SRC_VMAIN, | |
328 | IWL_PWR_SRC_VAUX, | |
329 | }; | |
330 | ||
5d08cd1d CH |
331 | #define IEEE80211_DATA_LEN 2304 |
332 | #define IEEE80211_4ADDR_LEN 30 | |
333 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
334 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
335 | ||
fcab423d | 336 | struct iwl_frame { |
5d08cd1d CH |
337 | union { |
338 | struct ieee80211_hdr frame; | |
4bf64efd | 339 | struct iwl_tx_beacon_cmd beacon; |
5d08cd1d CH |
340 | u8 raw[IEEE80211_FRAME_LEN]; |
341 | u8 cmd[360]; | |
342 | } u; | |
343 | struct list_head list; | |
344 | }; | |
345 | ||
5d08cd1d CH |
346 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
347 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
348 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
349 | ||
350 | enum { | |
c587de0b TW |
351 | CMD_SYNC = 0, |
352 | CMD_SIZE_NORMAL = 0, | |
353 | CMD_NO_SKB = 0, | |
5d08cd1d | 354 | CMD_SIZE_HUGE = (1 << 0), |
5d08cd1d | 355 | CMD_ASYNC = (1 << 1), |
5d08cd1d CH |
356 | CMD_WANT_SKB = (1 << 2), |
357 | }; | |
358 | ||
d2f18bfd | 359 | #define IWL_CMD_MAX_PAYLOAD 320 |
bd68fb6f | 360 | |
bc47279f | 361 | /** |
c2acea8e | 362 | * struct iwl_device_cmd |
bc47279f BC |
363 | * |
364 | * For allocation of the command and tx queues, this establishes the overall | |
365 | * size of the largest command we send to uCode, except for a scan command | |
366 | * (which is relatively huge; space is allocated separately). | |
367 | */ | |
c2acea8e | 368 | struct iwl_device_cmd { |
857485c0 | 369 | struct iwl_cmd_header hdr; /* uCode API */ |
5d08cd1d | 370 | union { |
5d08cd1d CH |
371 | u32 flags; |
372 | u8 val8; | |
373 | u16 val16; | |
374 | u32 val32; | |
83d527d9 | 375 | struct iwl_tx_cmd tx; |
bd68fb6f | 376 | u8 payload[IWL_CMD_MAX_PAYLOAD]; |
5d08cd1d CH |
377 | } __attribute__ ((packed)) cmd; |
378 | } __attribute__ ((packed)); | |
379 | ||
c2acea8e JB |
380 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) |
381 | ||
3257e5d4 | 382 | |
857485c0 | 383 | struct iwl_host_cmd { |
5d08cd1d | 384 | const void *data; |
c2acea8e | 385 | struct sk_buff *reply_skb; |
5696aea6 JB |
386 | void (*callback)(struct iwl_priv *priv, |
387 | struct iwl_device_cmd *cmd, | |
388 | struct sk_buff *skb); | |
c2acea8e JB |
389 | u32 flags; |
390 | u16 len; | |
391 | u8 id; | |
5d08cd1d CH |
392 | }; |
393 | ||
5d08cd1d CH |
394 | /* |
395 | * RX related structures and functions | |
396 | */ | |
397 | #define RX_FREE_BUFFERS 64 | |
398 | #define RX_LOW_WATERMARK 8 | |
399 | ||
400 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 | |
401 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
402 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
403 | ||
404 | /** | |
a55360e4 | 405 | * struct iwl_rx_queue - Rx queue |
df833b1d RC |
406 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) |
407 | * @dma_addr: bus address of buffer of receive buffer descriptors (rbd) | |
5d08cd1d CH |
408 | * @read: Shared index to newest available Rx buffer |
409 | * @write: Shared index to oldest written Rx packet | |
410 | * @free_count: Number of pre-allocated buffers in rx_free | |
411 | * @rx_free: list of free SKBs for use | |
412 | * @rx_used: List of Rx buffers with no SKB | |
413 | * @need_update: flag to indicate we need to update read/write index | |
df833b1d RC |
414 | * @rb_stts: driver's pointer to receive buffer status |
415 | * @rb_stts_dma: bus address of receive buffer status | |
5d08cd1d | 416 | * |
a55360e4 | 417 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers |
5d08cd1d | 418 | */ |
a55360e4 | 419 | struct iwl_rx_queue { |
5d08cd1d CH |
420 | __le32 *bd; |
421 | dma_addr_t dma_addr; | |
a55360e4 TW |
422 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; |
423 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
5d08cd1d CH |
424 | u32 read; |
425 | u32 write; | |
426 | u32 free_count; | |
4752c93c | 427 | u32 write_actual; |
5d08cd1d CH |
428 | struct list_head rx_free; |
429 | struct list_head rx_used; | |
430 | int need_update; | |
8d86422a WT |
431 | struct iwl_rb_status *rb_stts; |
432 | dma_addr_t rb_stts_dma; | |
5d08cd1d CH |
433 | spinlock_t lock; |
434 | }; | |
435 | ||
436 | #define IWL_SUPPORTED_RATES_IE_LEN 8 | |
437 | ||
5d08cd1d CH |
438 | #define MAX_TID_COUNT 9 |
439 | ||
440 | #define IWL_INVALID_RATE 0xFF | |
441 | #define IWL_INVALID_VALUE -1 | |
442 | ||
bc47279f | 443 | /** |
6def9761 | 444 | * struct iwl_ht_agg -- aggregation status while waiting for block-ack |
bc47279f BC |
445 | * @txq_id: Tx queue used for Tx attempt |
446 | * @frame_count: # frames attempted by Tx command | |
447 | * @wait_for_ba: Expect block-ack before next Tx reply | |
448 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window | |
449 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window | |
450 | * @bitmap1: High order, one bit for each frame pending ACK in Tx window | |
451 | * @rate_n_flags: Rate at which Tx was attempted | |
452 | * | |
453 | * If REPLY_TX indicates that aggregation was attempted, driver must wait | |
454 | * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info | |
455 | * until block ack arrives. | |
456 | */ | |
6def9761 | 457 | struct iwl_ht_agg { |
5d08cd1d CH |
458 | u16 txq_id; |
459 | u16 frame_count; | |
460 | u16 wait_for_ba; | |
461 | u16 start_idx; | |
fe01b477 | 462 | u64 bitmap; |
5d08cd1d | 463 | u32 rate_n_flags; |
fe01b477 RR |
464 | #define IWL_AGG_OFF 0 |
465 | #define IWL_AGG_ON 1 | |
466 | #define IWL_EMPTYING_HW_QUEUE_ADDBA 2 | |
467 | #define IWL_EMPTYING_HW_QUEUE_DELBA 3 | |
468 | u8 state; | |
5d08cd1d | 469 | }; |
fe01b477 | 470 | |
5d08cd1d | 471 | |
6def9761 | 472 | struct iwl_tid_data { |
5d08cd1d | 473 | u16 seq_number; |
fe01b477 | 474 | u16 tfds_in_queue; |
6def9761 | 475 | struct iwl_ht_agg agg; |
5d08cd1d CH |
476 | }; |
477 | ||
6def9761 | 478 | struct iwl_hw_key { |
5d08cd1d CH |
479 | enum ieee80211_key_alg alg; |
480 | int keylen; | |
0211ddda | 481 | u8 keyidx; |
5d08cd1d CH |
482 | u8 key[32]; |
483 | }; | |
484 | ||
a78fe754 | 485 | union iwl_ht_rate_supp { |
5d08cd1d CH |
486 | u16 rates; |
487 | struct { | |
488 | u8 siso_rate; | |
489 | u8 mimo_rate; | |
490 | }; | |
491 | }; | |
492 | ||
5d08cd1d | 493 | #define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3) |
bcc693a1 WYG |
494 | |
495 | /* | |
496 | * Maximal MPDU density for TX aggregation | |
497 | * 4 - 2us density | |
498 | * 5 - 4us density | |
499 | * 6 - 8us density | |
500 | * 7 - 16us density | |
501 | */ | |
502 | #define CFG_HT_MPDU_DENSITY_4USEC (0x5) | |
503 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC | |
5d08cd1d | 504 | |
fad95bf5 | 505 | struct iwl_ht_config { |
9e0cc6de | 506 | /* self configuration data */ |
c812ee24 JB |
507 | bool is_ht; |
508 | bool is_40mhz; | |
12837be1 | 509 | u8 sm_ps; |
d9fe60de | 510 | struct ieee80211_mcs_info mcs; |
9e0cc6de | 511 | /* BSS related data */ |
5d08cd1d | 512 | u8 extension_chan_offset; |
9e0cc6de RR |
513 | u8 ht_protection; |
514 | u8 non_GF_STA_present; | |
5d08cd1d | 515 | }; |
5d08cd1d | 516 | |
1ff50bda | 517 | union iwl_qos_capabity { |
5d08cd1d CH |
518 | struct { |
519 | u8 edca_count:4; /* bit 0-3 */ | |
520 | u8 q_ack:1; /* bit 4 */ | |
521 | u8 queue_request:1; /* bit 5 */ | |
522 | u8 txop_request:1; /* bit 6 */ | |
523 | u8 reserved:1; /* bit 7 */ | |
524 | } q_AP; | |
525 | struct { | |
526 | u8 acvo_APSD:1; /* bit 0 */ | |
527 | u8 acvi_APSD:1; /* bit 1 */ | |
528 | u8 ac_bk_APSD:1; /* bit 2 */ | |
529 | u8 ac_be_APSD:1; /* bit 3 */ | |
530 | u8 q_ack:1; /* bit 4 */ | |
531 | u8 max_len:2; /* bit 5-6 */ | |
532 | u8 more_data_ack:1; /* bit 7 */ | |
533 | } q_STA; | |
534 | u8 val; | |
535 | }; | |
536 | ||
537 | /* QoS structures */ | |
1ff50bda | 538 | struct iwl_qos_info { |
5d08cd1d | 539 | int qos_active; |
1ff50bda EG |
540 | union iwl_qos_capabity qos_cap; |
541 | struct iwl_qosparam_cmd def_qos_parm; | |
5d08cd1d | 542 | }; |
5d08cd1d CH |
543 | |
544 | #define STA_PS_STATUS_WAKE 0 | |
545 | #define STA_PS_STATUS_SLEEP 1 | |
546 | ||
85d41495 KA |
547 | |
548 | struct iwl3945_station_entry { | |
549 | struct iwl3945_addsta_cmd sta; | |
c15ff610 | 550 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
85d41495 KA |
551 | u8 used; |
552 | u8 ps_status; | |
bed420d9 | 553 | struct iwl_hw_key keyinfo; |
85d41495 KA |
554 | }; |
555 | ||
6def9761 | 556 | struct iwl_station_entry { |
133636de | 557 | struct iwl_addsta_cmd sta; |
6def9761 | 558 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
5d08cd1d CH |
559 | u8 used; |
560 | u8 ps_status; | |
6def9761 | 561 | struct iwl_hw_key keyinfo; |
5d08cd1d CH |
562 | }; |
563 | ||
564 | /* one for each uCode image (inst/data, boot/init/runtime) */ | |
565 | struct fw_desc { | |
566 | void *v_addr; /* access by driver */ | |
567 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
568 | u32 len; /* bytes */ | |
569 | }; | |
570 | ||
571 | /* uCode file layout */ | |
cc0f555d JS |
572 | struct iwl_ucode_header { |
573 | __le32 ver; /* major/minor/API/serial */ | |
574 | union { | |
575 | struct { | |
576 | __le32 inst_size; /* bytes of runtime code */ | |
577 | __le32 data_size; /* bytes of runtime data */ | |
578 | __le32 init_size; /* bytes of init code */ | |
579 | __le32 init_data_size; /* bytes of init data */ | |
580 | __le32 boot_size; /* bytes of bootstrap code */ | |
581 | u8 data[0]; /* in same order as sizes */ | |
582 | } v1; | |
583 | struct { | |
584 | __le32 build; /* build number */ | |
585 | __le32 inst_size; /* bytes of runtime code */ | |
586 | __le32 data_size; /* bytes of runtime data */ | |
587 | __le32 init_size; /* bytes of init code */ | |
588 | __le32 init_data_size; /* bytes of init data */ | |
589 | __le32 boot_size; /* bytes of bootstrap code */ | |
590 | u8 data[0]; /* in same order as sizes */ | |
591 | } v2; | |
592 | } u; | |
5d08cd1d | 593 | }; |
cc0f555d | 594 | #define UCODE_HEADER_SIZE(ver) ((ver) == 1 ? 24 : 28) |
5d08cd1d | 595 | |
bb8c093b | 596 | struct iwl4965_ibss_seq { |
5d08cd1d CH |
597 | u8 mac[ETH_ALEN]; |
598 | u16 seq_num; | |
599 | u16 frag_num; | |
600 | unsigned long packet_time; | |
601 | struct list_head list; | |
602 | }; | |
603 | ||
f0832f13 EG |
604 | struct iwl_sensitivity_ranges { |
605 | u16 min_nrg_cck; | |
606 | u16 max_nrg_cck; | |
607 | ||
608 | u16 nrg_th_cck; | |
609 | u16 nrg_th_ofdm; | |
610 | ||
611 | u16 auto_corr_min_ofdm; | |
612 | u16 auto_corr_min_ofdm_mrc; | |
613 | u16 auto_corr_min_ofdm_x1; | |
614 | u16 auto_corr_min_ofdm_mrc_x1; | |
615 | ||
616 | u16 auto_corr_max_ofdm; | |
617 | u16 auto_corr_max_ofdm_mrc; | |
618 | u16 auto_corr_max_ofdm_x1; | |
619 | u16 auto_corr_max_ofdm_mrc_x1; | |
620 | ||
621 | u16 auto_corr_max_cck; | |
622 | u16 auto_corr_max_cck_mrc; | |
623 | u16 auto_corr_min_cck; | |
624 | u16 auto_corr_min_cck_mrc; | |
625 | }; | |
626 | ||
099b40b7 | 627 | |
b5047f78 TW |
628 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
629 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
630 | ||
631 | ||
bc47279f | 632 | /** |
5425e490 | 633 | * struct iwl_hw_params |
bc47279f | 634 | * @max_txq_num: Max # Tx queues supported |
f3f911d1 | 635 | * @dma_chnl_num: Number of Tx DMA/FIFO channels |
4ddbb7d0 | 636 | * @scd_bc_tbls_size: size of scheduler byte count tables |
a8e74e27 | 637 | * @tfd_size: TFD size |
099b40b7 RR |
638 | * @tx/rx_chains_num: Number of TX/RX chains |
639 | * @valid_tx/rx_ant: usable antennas | |
bc47279f | 640 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) |
bc47279f | 641 | * @max_rxq_log: Log-base-2 of max_rxq_size |
099b40b7 | 642 | * @rx_buf_size: Rx buffer size |
141c43a3 | 643 | * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR |
bc47279f BC |
644 | * @max_stations: |
645 | * @bcast_sta_id: | |
7aafef1c | 646 | * @ht40_channel: is 40MHz width possible in band 2.4 |
099b40b7 RR |
647 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) |
648 | * @sw_crypto: 0 for hw, 1 for sw | |
649 | * @max_xxx_size: for ucode uses | |
650 | * @ct_kill_threshold: temperature threshold | |
a96a27f9 | 651 | * @calib_init_cfg: setup initial calibrations for the hw |
f0832f13 | 652 | * @struct iwl_sensitivity_ranges: range of sensitivity values |
bc47279f | 653 | */ |
5425e490 | 654 | struct iwl_hw_params { |
f3f911d1 ZY |
655 | u8 max_txq_num; |
656 | u8 dma_chnl_num; | |
4ddbb7d0 | 657 | u16 scd_bc_tbls_size; |
a8e74e27 | 658 | u32 tfd_size; |
ec35cf2a TW |
659 | u8 tx_chains_num; |
660 | u8 rx_chains_num; | |
661 | u8 valid_tx_ant; | |
662 | u8 valid_rx_ant; | |
5d08cd1d | 663 | u16 max_rxq_size; |
ec35cf2a | 664 | u16 max_rxq_log; |
9ee1ba47 | 665 | u32 rx_buf_size; |
141c43a3 | 666 | u32 rx_wrt_ptr_reg; |
9ee1ba47 | 667 | u32 max_pkt_size; |
5d08cd1d CH |
668 | u8 max_stations; |
669 | u8 bcast_sta_id; | |
7aafef1c | 670 | u8 ht40_channel; |
2c2f3b33 | 671 | u8 max_beacon_itrvl; /* in 1024 ms */ |
099b40b7 RR |
672 | u32 max_inst_size; |
673 | u32 max_data_size; | |
674 | u32 max_bsm_size; | |
675 | u32 ct_kill_threshold; /* value in hw-dependent units */ | |
672639de WYG |
676 | u32 ct_kill_exit_threshold; /* value in hw-dependent units */ |
677 | /* for 1000, 6000 series and up */ | |
be5d56ed | 678 | u32 calib_init_cfg; |
f0832f13 | 679 | const struct iwl_sensitivity_ranges *sens; |
5d08cd1d CH |
680 | }; |
681 | ||
5d08cd1d | 682 | |
5d08cd1d CH |
683 | /****************************************************************************** |
684 | * | |
a33c2f47 EG |
685 | * Functions implemented in core module which are forward declared here |
686 | * for use by iwl-[4-5].c | |
5d08cd1d | 687 | * |
a33c2f47 EG |
688 | * NOTE: The implementation of these functions are not hardware specific |
689 | * which is why they are in the core module files. | |
5d08cd1d CH |
690 | * |
691 | * Naming convention -- | |
a33c2f47 | 692 | * iwl_ <-- Is part of iwlwifi |
5d08cd1d | 693 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) |
bb8c093b CH |
694 | * iwl4965_bg_ <-- Called from work queue context |
695 | * iwl4965_mac_ <-- mac80211 callback | |
5d08cd1d CH |
696 | * |
697 | ****************************************************************************/ | |
5b9f8cd3 EG |
698 | extern void iwl_update_chain_flags(struct iwl_priv *priv); |
699 | extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src); | |
a33c2f47 | 700 | extern const u8 iwl_bcast_addr[ETH_ALEN]; |
b3bbacb7 | 701 | extern int iwl_rxq_stop(struct iwl_priv *priv); |
da1bc453 | 702 | extern void iwl_txq_ctx_stop(struct iwl_priv *priv); |
443cfd45 | 703 | extern int iwl_queue_space(const struct iwl_queue *q); |
fd4abac5 TW |
704 | static inline int iwl_queue_used(const struct iwl_queue *q, int i) |
705 | { | |
706 | return q->write_ptr > q->read_ptr ? | |
707 | (i >= q->read_ptr && i < q->write_ptr) : | |
708 | !(i < q->read_ptr && i >= q->write_ptr); | |
709 | } | |
710 | ||
711 | ||
712 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge) | |
713 | { | |
714 | /* This is for scan command, the big buffer at end of command array */ | |
715 | if (is_huge) | |
716 | return q->n_window; /* must be power of 2 */ | |
717 | ||
718 | /* Otherwise, use normal size buffers */ | |
719 | return index & (q->n_window - 1); | |
720 | } | |
721 | ||
722 | ||
4ddbb7d0 TW |
723 | struct iwl_dma_ptr { |
724 | dma_addr_t dma; | |
725 | void *addr; | |
b481de9c ZY |
726 | size_t size; |
727 | }; | |
728 | ||
b481de9c ZY |
729 | #define IWL_OPERATION_MODE_AUTO 0 |
730 | #define IWL_OPERATION_MODE_HT_ONLY 1 | |
731 | #define IWL_OPERATION_MODE_MIXED 2 | |
732 | #define IWL_OPERATION_MODE_20MHZ 3 | |
733 | ||
3195cdb7 TW |
734 | #define IWL_TX_CRC_SIZE 4 |
735 | #define IWL_TX_DELIMITER_SIZE 4 | |
b481de9c | 736 | |
b481de9c | 737 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 |
b481de9c | 738 | |
b481de9c | 739 | /* Sensitivity and chain noise calibration */ |
b481de9c ZY |
740 | #define INITIALIZATION_VALUE 0xFFFF |
741 | #define CAL_NUM_OF_BEACONS 20 | |
742 | #define MAXIMUM_ALLOWED_PATHLOSS 15 | |
743 | ||
b481de9c ZY |
744 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 |
745 | ||
746 | #define MAX_FA_OFDM 50 | |
747 | #define MIN_FA_OFDM 5 | |
748 | #define MAX_FA_CCK 50 | |
749 | #define MIN_FA_CCK 5 | |
750 | ||
b481de9c ZY |
751 | #define AUTO_CORR_STEP_OFDM 1 |
752 | ||
b481de9c ZY |
753 | #define AUTO_CORR_STEP_CCK 3 |
754 | #define AUTO_CORR_MAX_TH_CCK 160 | |
755 | ||
b481de9c ZY |
756 | #define NRG_DIFF 2 |
757 | #define NRG_STEP_CCK 2 | |
758 | #define NRG_MARGIN 8 | |
759 | #define MAX_NUMBER_CCK_NO_FA 100 | |
760 | ||
761 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
762 | ||
763 | #define CHAIN_A 0 | |
764 | #define CHAIN_B 1 | |
765 | #define CHAIN_C 2 | |
766 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
767 | #define ALL_BAND_FILTER 0xFF00 | |
768 | #define IN_BAND_FILTER 0xFF | |
769 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
770 | ||
3195cdb7 TW |
771 | #define NRG_NUM_PREV_STAT_L 20 |
772 | #define NUM_RX_CHAINS 3 | |
773 | ||
bb8c093b | 774 | enum iwl4965_false_alarm_state { |
b481de9c ZY |
775 | IWL_FA_TOO_MANY = 0, |
776 | IWL_FA_TOO_FEW = 1, | |
777 | IWL_FA_GOOD_RANGE = 2, | |
778 | }; | |
779 | ||
bb8c093b | 780 | enum iwl4965_chain_noise_state { |
b481de9c | 781 | IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
04816448 GE |
782 | IWL_CHAIN_NOISE_ACCUMULATE, |
783 | IWL_CHAIN_NOISE_CALIBRATED, | |
784 | IWL_CHAIN_NOISE_DONE, | |
b481de9c ZY |
785 | }; |
786 | ||
bb8c093b | 787 | enum iwl4965_calib_enabled_state { |
b481de9c ZY |
788 | IWL_CALIB_DISABLED = 0, /* must be 0 */ |
789 | IWL_CALIB_ENABLED = 1, | |
790 | }; | |
791 | ||
f69f42a6 TW |
792 | |
793 | /* | |
794 | * enum iwl_calib | |
795 | * defines the order in which results of initial calibrations | |
796 | * should be sent to the runtime uCode | |
797 | */ | |
798 | enum iwl_calib { | |
799 | IWL_CALIB_XTAL, | |
819500c5 | 800 | IWL_CALIB_DC, |
f69f42a6 TW |
801 | IWL_CALIB_LO, |
802 | IWL_CALIB_TX_IQ, | |
803 | IWL_CALIB_TX_IQ_PERD, | |
201706ac | 804 | IWL_CALIB_BASE_BAND, |
f69f42a6 TW |
805 | IWL_CALIB_MAX |
806 | }; | |
807 | ||
6e21f2c1 TW |
808 | /* Opaque calibration results */ |
809 | struct iwl_calib_result { | |
810 | void *buf; | |
811 | size_t buf_len; | |
7c616cba TW |
812 | }; |
813 | ||
dbb983b7 RR |
814 | enum ucode_type { |
815 | UCODE_NONE = 0, | |
816 | UCODE_INIT, | |
817 | UCODE_RT | |
818 | }; | |
819 | ||
b481de9c | 820 | /* Sensitivity calib data */ |
f0832f13 | 821 | struct iwl_sensitivity_data { |
b481de9c ZY |
822 | u32 auto_corr_ofdm; |
823 | u32 auto_corr_ofdm_mrc; | |
824 | u32 auto_corr_ofdm_x1; | |
825 | u32 auto_corr_ofdm_mrc_x1; | |
826 | u32 auto_corr_cck; | |
827 | u32 auto_corr_cck_mrc; | |
828 | ||
829 | u32 last_bad_plcp_cnt_ofdm; | |
830 | u32 last_fa_cnt_ofdm; | |
831 | u32 last_bad_plcp_cnt_cck; | |
832 | u32 last_fa_cnt_cck; | |
833 | ||
834 | u32 nrg_curr_state; | |
835 | u32 nrg_prev_state; | |
836 | u32 nrg_value[10]; | |
837 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; | |
838 | u32 nrg_silence_ref; | |
839 | u32 nrg_energy_idx; | |
840 | u32 nrg_silence_idx; | |
841 | u32 nrg_th_cck; | |
842 | s32 nrg_auto_corr_silence_diff; | |
843 | u32 num_in_cck_no_fa; | |
844 | u32 nrg_th_ofdm; | |
b481de9c ZY |
845 | }; |
846 | ||
847 | /* Chain noise (differential Rx gain) calib data */ | |
f0832f13 | 848 | struct iwl_chain_noise_data { |
04816448 | 849 | u32 active_chains; |
b481de9c ZY |
850 | u32 chain_noise_a; |
851 | u32 chain_noise_b; | |
852 | u32 chain_noise_c; | |
853 | u32 chain_signal_a; | |
854 | u32 chain_signal_b; | |
855 | u32 chain_signal_c; | |
04816448 | 856 | u16 beacon_count; |
b481de9c ZY |
857 | u8 disconn_array[NUM_RX_CHAINS]; |
858 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
859 | u8 radio_write; | |
04816448 | 860 | u8 state; |
b481de9c ZY |
861 | }; |
862 | ||
abceddb4 BC |
863 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
864 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
b481de9c | 865 | |
20594eb0 WYG |
866 | #define IWL_TRAFFIC_ENTRIES (256) |
867 | #define IWL_TRAFFIC_ENTRY_SIZE (64) | |
5d08cd1d | 868 | |
5d08cd1d CH |
869 | enum { |
870 | MEASUREMENT_READY = (1 << 0), | |
871 | MEASUREMENT_ACTIVE = (1 << 1), | |
872 | }; | |
873 | ||
0848e297 WYG |
874 | enum iwl_nvm_type { |
875 | NVM_DEVICE_TYPE_EEPROM = 0, | |
876 | NVM_DEVICE_TYPE_OTP, | |
877 | }; | |
878 | ||
415e4993 WYG |
879 | /* |
880 | * Two types of OTP memory access modes | |
881 | * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode, | |
882 | * based on physical memory addressing | |
883 | * IWL_OTP_ACCESS_RELATIVE - relative address mode, | |
884 | * based on logical memory addressing | |
885 | */ | |
886 | enum iwl_access_mode { | |
887 | IWL_OTP_ACCESS_ABSOLUTE, | |
888 | IWL_OTP_ACCESS_RELATIVE, | |
889 | }; | |
65b7998a WYG |
890 | |
891 | /** | |
892 | * enum iwl_pa_type - Power Amplifier type | |
893 | * @IWL_PA_SYSTEM: based on uCode configuration | |
894 | * @IWL_PA_HYBRID: use both Internal and external PA | |
895 | * @IWL_PA_INTERNAL: use Internal only | |
896 | */ | |
897 | enum iwl_pa_type { | |
898 | IWL_PA_SYSTEM = 0, | |
899 | IWL_PA_HYBRID = 1, | |
900 | IWL_PA_INTERNAL = 2, | |
901 | }; | |
902 | ||
a83b9141 WYG |
903 | /* interrupt statistics */ |
904 | struct isr_statistics { | |
905 | u32 hw; | |
906 | u32 sw; | |
907 | u32 sw_err; | |
908 | u32 sch; | |
909 | u32 alive; | |
910 | u32 rfkill; | |
911 | u32 ctkill; | |
912 | u32 wakeup; | |
913 | u32 rx; | |
914 | u32 rx_handlers[REPLY_MAX]; | |
915 | u32 tx; | |
916 | u32 unhandled; | |
917 | }; | |
5d08cd1d | 918 | |
22fdf3c9 WYG |
919 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
920 | /* management statistics */ | |
921 | enum iwl_mgmt_stats { | |
922 | MANAGEMENT_ASSOC_REQ = 0, | |
923 | MANAGEMENT_ASSOC_RESP, | |
924 | MANAGEMENT_REASSOC_REQ, | |
925 | MANAGEMENT_REASSOC_RESP, | |
926 | MANAGEMENT_PROBE_REQ, | |
927 | MANAGEMENT_PROBE_RESP, | |
928 | MANAGEMENT_BEACON, | |
929 | MANAGEMENT_ATIM, | |
930 | MANAGEMENT_DISASSOC, | |
931 | MANAGEMENT_AUTH, | |
932 | MANAGEMENT_DEAUTH, | |
933 | MANAGEMENT_ACTION, | |
934 | MANAGEMENT_MAX, | |
935 | }; | |
936 | /* control statistics */ | |
937 | enum iwl_ctrl_stats { | |
938 | CONTROL_BACK_REQ = 0, | |
939 | CONTROL_BACK, | |
940 | CONTROL_PSPOLL, | |
941 | CONTROL_RTS, | |
942 | CONTROL_CTS, | |
943 | CONTROL_ACK, | |
944 | CONTROL_CFEND, | |
945 | CONTROL_CFENDACK, | |
946 | CONTROL_MAX, | |
947 | }; | |
948 | ||
949 | struct traffic_stats { | |
950 | u32 mgmt[MANAGEMENT_MAX]; | |
951 | u32 ctrl[CONTROL_MAX]; | |
952 | u32 data_cnt; | |
953 | u64 data_bytes; | |
954 | }; | |
955 | #else | |
956 | struct traffic_stats { | |
957 | u64 data_bytes; | |
958 | }; | |
959 | #endif | |
960 | ||
dfe7d458 RR |
961 | #define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */ |
962 | ||
c79dd5b5 | 963 | struct iwl_priv { |
5d08cd1d CH |
964 | |
965 | /* ieee device used by generic ieee processing code */ | |
966 | struct ieee80211_hw *hw; | |
967 | struct ieee80211_channel *ieee_channels; | |
968 | struct ieee80211_rate *ieee_rates; | |
82b9a121 | 969 | struct iwl_cfg *cfg; |
5d08cd1d CH |
970 | |
971 | /* temporary frame storage list */ | |
972 | struct list_head free_frames; | |
973 | int frames_count; | |
974 | ||
8318d78a | 975 | enum ieee80211_band band; |
5d08cd1d CH |
976 | int alloc_rxb_skb; |
977 | ||
c79dd5b5 | 978 | void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv, |
a55360e4 | 979 | struct iwl_rx_mem_buffer *rxb); |
5d08cd1d | 980 | |
8318d78a | 981 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; |
5d08cd1d | 982 | |
80bc5393 | 983 | #if defined(CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT) || defined(CONFIG_IWL3945_SPECTRUM_MEASUREMENT) |
5d08cd1d | 984 | /* spectrum measurement report caching */ |
2aa6ab86 | 985 | struct iwl_spectrum_notification measure_report; |
5d08cd1d CH |
986 | u8 measurement_status; |
987 | #endif | |
988 | /* ucode beacon time */ | |
989 | u32 ucode_beacon_time; | |
990 | ||
bb8c093b | 991 | /* we allocate array of iwl4965_channel_info for NIC's valid channels. |
5d08cd1d | 992 | * Access via channel # using indirect index array */ |
bf85ea4f | 993 | struct iwl_channel_info *channel_info; /* channel info array */ |
5d08cd1d CH |
994 | u8 channel_count; /* # of channels */ |
995 | ||
85d41495 KA |
996 | /* each calibration channel group in the EEPROM has a derived |
997 | * clip setting for each rate. 3945 only.*/ | |
998 | const struct iwl3945_clip_group clip39_groups[5]; | |
999 | ||
5d08cd1d CH |
1000 | /* thermal calibration */ |
1001 | s32 temperature; /* degrees Kelvin */ | |
1002 | s32 last_temperature; | |
1003 | ||
7c616cba | 1004 | /* init calibration results */ |
6e21f2c1 | 1005 | struct iwl_calib_result calib_results[IWL_CALIB_MAX]; |
7c616cba | 1006 | |
5d08cd1d CH |
1007 | /* Scan related variables */ |
1008 | unsigned long last_scan_jiffies; | |
7878a5a4 | 1009 | unsigned long next_scan_jiffies; |
5d08cd1d CH |
1010 | unsigned long scan_start; |
1011 | unsigned long scan_pass_start; | |
1012 | unsigned long scan_start_tsf; | |
805cee5b | 1013 | void *scan; |
5d08cd1d | 1014 | int scan_bands; |
1ecf9fc1 | 1015 | struct cfg80211_scan_request *scan_request; |
76eff18b TW |
1016 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; |
1017 | u8 mgmt_tx_ant; | |
5d08cd1d CH |
1018 | |
1019 | /* spinlock */ | |
1020 | spinlock_t lock; /* protect general shared data */ | |
1021 | spinlock_t hcmd_lock; /* protect hcmd */ | |
a8b50a0a | 1022 | spinlock_t reg_lock; /* protect hw register access */ |
5d08cd1d CH |
1023 | struct mutex mutex; |
1024 | ||
1025 | /* basic pci-network driver stuff */ | |
1026 | struct pci_dev *pci_dev; | |
1027 | ||
1028 | /* pci hardware address support */ | |
1029 | void __iomem *hw_base; | |
b661c819 TW |
1030 | u32 hw_rev; |
1031 | u32 hw_wa_rev; | |
1032 | u8 rev_id; | |
5d08cd1d CH |
1033 | |
1034 | /* uCode images, save to reload in case of failure */ | |
c02b3acd CR |
1035 | u32 ucode_ver; /* version of ucode, copy of |
1036 | iwl_ucode.ver */ | |
5d08cd1d CH |
1037 | struct fw_desc ucode_code; /* runtime inst */ |
1038 | struct fw_desc ucode_data; /* runtime data original */ | |
1039 | struct fw_desc ucode_data_backup; /* runtime data save/restore */ | |
1040 | struct fw_desc ucode_init; /* initialization inst */ | |
1041 | struct fw_desc ucode_init_data; /* initialization data */ | |
1042 | struct fw_desc ucode_boot; /* bootstrap inst */ | |
dbb983b7 RR |
1043 | enum ucode_type ucode_type; |
1044 | u8 ucode_write_complete; /* the image write is complete */ | |
5d08cd1d CH |
1045 | |
1046 | ||
3195c1f3 | 1047 | struct iwl_rxon_time_cmd rxon_timing; |
5d08cd1d CH |
1048 | |
1049 | /* We declare this const so it can only be | |
1050 | * changed via explicit cast within the | |
1051 | * routines that actually update the physical | |
1052 | * hardware */ | |
c1adf9fb GG |
1053 | const struct iwl_rxon_cmd active_rxon; |
1054 | struct iwl_rxon_cmd staging_rxon; | |
5d08cd1d | 1055 | |
c1adf9fb | 1056 | struct iwl_rxon_cmd recovery_rxon; |
5d08cd1d CH |
1057 | |
1058 | /* 1st responses from initialize and runtime uCode images. | |
1059 | * 4965's initialize alive response contains some calibration data. */ | |
885ba202 TW |
1060 | struct iwl_init_alive_resp card_alive_init; |
1061 | struct iwl_alive_resp card_alive; | |
5d08cd1d | 1062 | |
5c8df2d5 | 1063 | #ifdef CONFIG_IWLWIFI_LEDS |
ab53d8af MA |
1064 | unsigned long last_blink_time; |
1065 | u8 last_blink_rate; | |
1066 | u8 allow_blinking; | |
1067 | u64 led_tpt; | |
4a8a4322 | 1068 | struct iwl_led led[IWL_LED_TRG_MAX]; |
4a8a4322 AK |
1069 | unsigned int rxtxpackets; |
1070 | #endif | |
5d08cd1d CH |
1071 | u16 active_rate; |
1072 | u16 active_rate_basic; | |
1073 | ||
5d08cd1d | 1074 | u8 assoc_station_added; |
5d08cd1d | 1075 | u8 start_calib; |
f0832f13 EG |
1076 | struct iwl_sensitivity_data sensitivity_data; |
1077 | struct iwl_chain_noise_data chain_noise_data; | |
5d08cd1d | 1078 | __le16 sensitivity_tbl[HD_TABLE_SIZE]; |
5d08cd1d | 1079 | |
fad95bf5 | 1080 | struct iwl_ht_config current_ht_config; |
5d08cd1d CH |
1081 | u8 last_phy_res[100]; |
1082 | ||
5d08cd1d CH |
1083 | /* Rate scaling data */ |
1084 | s8 data_retry_limit; | |
1085 | u8 retry_rate; | |
1086 | ||
1087 | wait_queue_head_t wait_command_queue; | |
1088 | ||
1089 | int activity_timer_active; | |
1090 | ||
1091 | /* Rx and Tx DMA processing queues */ | |
a55360e4 | 1092 | struct iwl_rx_queue rxq; |
16466903 | 1093 | struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES]; |
5d08cd1d | 1094 | unsigned long txq_ctx_active_msk; |
4ddbb7d0 TW |
1095 | struct iwl_dma_ptr kw; /* keep warm address */ |
1096 | struct iwl_dma_ptr scd_bc_tbls; | |
1097 | ||
5d08cd1d CH |
1098 | u32 scd_base_addr; /* scheduler sram base address */ |
1099 | ||
1100 | unsigned long status; | |
5d08cd1d | 1101 | |
a96a27f9 | 1102 | int last_rx_rssi; /* From Rx packet statistics */ |
5d08cd1d CH |
1103 | int last_rx_noise; /* From beacon statistics */ |
1104 | ||
19758bef | 1105 | /* counts mgmt, ctl, and data packets */ |
22fdf3c9 WYG |
1106 | struct traffic_stats tx_stats; |
1107 | struct traffic_stats rx_stats; | |
19758bef | 1108 | |
a83b9141 WYG |
1109 | /* counts interrupts */ |
1110 | struct isr_statistics isr_stats; | |
1111 | ||
5da4b55f | 1112 | struct iwl_power_mgr power_data; |
3ad3b92a | 1113 | struct iwl_tt_mgmt thermal_throttle; |
5d08cd1d | 1114 | |
8f91aecb | 1115 | struct iwl_notif_statistics statistics; |
5d08cd1d CH |
1116 | unsigned long last_statistics_time; |
1117 | ||
1118 | /* context information */ | |
5d08cd1d CH |
1119 | u16 rates_mask; |
1120 | ||
5d08cd1d CH |
1121 | u8 bssid[ETH_ALEN]; |
1122 | u16 rts_threshold; | |
1123 | u8 mac_addr[ETH_ALEN]; | |
1124 | ||
1125 | /*station table variables */ | |
1126 | spinlock_t sta_lock; | |
1127 | int num_stations; | |
6def9761 | 1128 | struct iwl_station_entry stations[IWL_STATION_COUNT]; |
6974e363 EG |
1129 | struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; |
1130 | u8 default_wep_key; | |
1131 | u8 key_mapping_key; | |
80fb47a1 | 1132 | unsigned long ucode_key_table; |
5d08cd1d | 1133 | |
e4e72fb4 JB |
1134 | /* queue refcounts */ |
1135 | #define IWL_MAX_HW_QUEUES 32 | |
1136 | unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; | |
1137 | /* for each AC */ | |
1138 | atomic_t queue_stop_count[4]; | |
1139 | ||
5d08cd1d | 1140 | /* Indication if ieee80211_ops->open has been called */ |
69dc5d9d | 1141 | u8 is_open; |
5d08cd1d CH |
1142 | |
1143 | u8 mac80211_registered; | |
5d08cd1d | 1144 | |
5d08cd1d CH |
1145 | /* Rx'd packet timing information */ |
1146 | u32 last_beacon_time; | |
1147 | u64 last_tsf; | |
1148 | ||
5d08cd1d | 1149 | /* eeprom */ |
073d3f5f | 1150 | u8 *eeprom; |
0848e297 | 1151 | int nvm_device_type; |
073d3f5f | 1152 | struct iwl_eeprom_calib_info *calib_info; |
5d08cd1d | 1153 | |
05c914fe | 1154 | enum nl80211_iftype iw_mode; |
5d08cd1d CH |
1155 | |
1156 | struct sk_buff *ibss_beacon; | |
1157 | ||
1158 | /* Last Rx'd beacon timestamp */ | |
3109ece1 | 1159 | u64 timestamp; |
5d08cd1d | 1160 | u16 beacon_int; |
32bfd35d | 1161 | struct ieee80211_vif *vif; |
5d08cd1d | 1162 | |
8cd812bc | 1163 | /*Added for 3945 */ |
3832ec9d AK |
1164 | void *shared_virt; |
1165 | dma_addr_t shared_phys; | |
1166 | /*End*/ | |
5425e490 | 1167 | struct iwl_hw_params hw_params; |
4ddbb7d0 | 1168 | |
ef850d7c | 1169 | /* INT ICT Table */ |
1303dcfd | 1170 | __le32 *ict_tbl; |
ef850d7c MA |
1171 | dma_addr_t ict_tbl_dma; |
1172 | dma_addr_t aligned_ict_tbl_dma; | |
1173 | int ict_index; | |
1174 | void *ict_tbl_vir; | |
1175 | u32 inta; | |
1176 | bool use_ict; | |
059ff826 | 1177 | |
40cefda9 | 1178 | u32 inta_mask; |
5d08cd1d CH |
1179 | /* Current association information needed to configure the |
1180 | * hardware */ | |
1181 | u16 assoc_id; | |
1182 | u16 assoc_capability; | |
5d08cd1d | 1183 | |
1ff50bda | 1184 | struct iwl_qos_info qos_data; |
5d08cd1d CH |
1185 | |
1186 | struct workqueue_struct *workqueue; | |
1187 | ||
1188 | struct work_struct up; | |
1189 | struct work_struct restart; | |
1190 | struct work_struct calibrated_work; | |
1191 | struct work_struct scan_completed; | |
1192 | struct work_struct rx_replenish; | |
5d08cd1d CH |
1193 | struct work_struct abort_scan; |
1194 | struct work_struct update_link_led; | |
1195 | struct work_struct auth_work; | |
1196 | struct work_struct report_work; | |
1197 | struct work_struct request_scan; | |
1198 | struct work_struct beacon_update; | |
a28027cd WYG |
1199 | struct work_struct tt_work; |
1200 | struct work_struct ct_enter; | |
1201 | struct work_struct ct_exit; | |
5d08cd1d CH |
1202 | |
1203 | struct tasklet_struct irq_tasklet; | |
1204 | ||
1205 | struct delayed_work init_alive_start; | |
1206 | struct delayed_work alive_start; | |
5d08cd1d | 1207 | struct delayed_work scan_check; |
4a8a4322 AK |
1208 | |
1209 | /*For 3945 only*/ | |
1210 | struct delayed_work thermal_periodic; | |
2663516d | 1211 | struct delayed_work rfkill_poll; |
4a8a4322 | 1212 | |
630fe9b6 TW |
1213 | /* TX Power */ |
1214 | s8 tx_power_user_lmt; | |
dc1b0973 | 1215 | s8 tx_power_device_lmt; |
5d08cd1d | 1216 | |
5d08cd1d | 1217 | |
d08853a3 | 1218 | #ifdef CONFIG_IWLWIFI_DEBUG |
5d08cd1d | 1219 | /* debugging info */ |
3d816c77 RC |
1220 | u32 debug_level; /* per device debugging will override global |
1221 | iwl_debug_level if set */ | |
5d08cd1d CH |
1222 | u32 framecnt_to_us; |
1223 | atomic_t restrict_refcnt; | |
1e4247d4 | 1224 | bool disable_ht40; |
712b6cf5 TW |
1225 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1226 | /* debugfs */ | |
20594eb0 WYG |
1227 | u16 tx_traffic_idx; |
1228 | u16 rx_traffic_idx; | |
1229 | u8 *tx_traffic; | |
1230 | u8 *rx_traffic; | |
712b6cf5 TW |
1231 | struct iwl_debugfs *dbgfs; |
1232 | #endif /* CONFIG_IWLWIFI_DEBUGFS */ | |
1233 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
5d08cd1d CH |
1234 | |
1235 | struct work_struct txpower_work; | |
445c2dff TW |
1236 | u32 disable_sens_cal; |
1237 | u32 disable_chain_noise_cal; | |
203566f3 | 1238 | u32 disable_tx_power_cal; |
16e727e8 | 1239 | struct work_struct run_time_calib_work; |
5d08cd1d | 1240 | struct timer_list statistics_periodic; |
086ed117 | 1241 | bool hw_ready; |
4a8a4322 AK |
1242 | /*For 3945*/ |
1243 | #define IWL_DEFAULT_TX_POWER 0x0F | |
4a8a4322 | 1244 | |
4a8a4322 AK |
1245 | struct iwl3945_notif_statistics statistics_39; |
1246 | ||
4a8a4322 | 1247 | u32 sta_supp_rates; |
c79dd5b5 | 1248 | }; /*iwl_priv */ |
5d08cd1d | 1249 | |
36470749 RR |
1250 | static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id) |
1251 | { | |
1252 | set_bit(txq_id, &priv->txq_ctx_active_msk); | |
1253 | } | |
1254 | ||
1255 | static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id) | |
1256 | { | |
1257 | clear_bit(txq_id, &priv->txq_ctx_active_msk); | |
1258 | } | |
1259 | ||
994d31f7 | 1260 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 | 1261 | const char *iwl_get_tx_fail_reason(u32 status); |
3d816c77 RC |
1262 | /* |
1263 | * iwl_get_debug_level: Return active debug level for device | |
1264 | * | |
1265 | * Using sysfs it is possible to set per device debug level. This debug | |
1266 | * level will be used if set, otherwise the global debug level which can be | |
1267 | * set via module parameter is used. | |
1268 | */ | |
1269 | static inline u32 iwl_get_debug_level(struct iwl_priv *priv) | |
1270 | { | |
1271 | if (priv->debug_level) | |
1272 | return priv->debug_level; | |
1273 | else | |
1274 | return iwl_debug_level; | |
1275 | } | |
a332f8d6 TW |
1276 | #else |
1277 | static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; } | |
3d816c77 RC |
1278 | |
1279 | static inline u32 iwl_get_debug_level(struct iwl_priv *priv) | |
1280 | { | |
1281 | return iwl_debug_level; | |
1282 | } | |
a332f8d6 TW |
1283 | #endif |
1284 | ||
1285 | ||
a332f8d6 TW |
1286 | static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv, |
1287 | int txq_id, int idx) | |
1288 | { | |
1289 | if (priv->txq[txq_id].txb[idx].skb[0]) | |
1290 | return (struct ieee80211_hdr *)priv->txq[txq_id]. | |
1291 | txb[idx].skb[0]->data; | |
1292 | return NULL; | |
1293 | } | |
a332f8d6 TW |
1294 | |
1295 | ||
3109ece1 | 1296 | static inline int iwl_is_associated(struct iwl_priv *priv) |
5d08cd1d CH |
1297 | { |
1298 | return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; | |
1299 | } | |
1300 | ||
bf85ea4f | 1301 | static inline int is_channel_valid(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1302 | { |
1303 | if (ch_info == NULL) | |
1304 | return 0; | |
1305 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1306 | } | |
1307 | ||
bf85ea4f | 1308 | static inline int is_channel_radar(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1309 | { |
1310 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1311 | } | |
1312 | ||
bf85ea4f | 1313 | static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1314 | { |
8318d78a | 1315 | return ch_info->band == IEEE80211_BAND_5GHZ; |
5d08cd1d CH |
1316 | } |
1317 | ||
bf85ea4f | 1318 | static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1319 | { |
8318d78a | 1320 | return ch_info->band == IEEE80211_BAND_2GHZ; |
5d08cd1d CH |
1321 | } |
1322 | ||
bf85ea4f | 1323 | static inline int is_channel_passive(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1324 | { |
1325 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1326 | } | |
1327 | ||
bf85ea4f | 1328 | static inline int is_channel_ibss(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1329 | { |
1330 | return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0; | |
1331 | } | |
1332 | ||
be1f3ab6 | 1333 | #endif /* __iwl_dev_h__ */ |