[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / iwlwifi / iwl-power.c

/******************************************************************************
 *
 * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *****************************************************************************/


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>

#include <net/mac80211.h>

#include "iwl-eeprom.h"
#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-commands.h"
#include "iwl-debug.h"
#include "iwl-power.h"

/*
 * Setting power level allows the card to go to sleep when not busy.
 *
 * We calculate a sleep command based on the required latency, which
 * we get from mac80211. In order to handle thermal throttling, we can
 * also use pre-defined power levels.
 */

/*
 * For now, keep using power level 1 instead of automatically
 * adjusting ...
 */
bool no_sleep_autoadjust = true;
module_param(no_sleep_autoadjust, bool, S_IRUGO);
MODULE_PARM_DESC(no_sleep_autoadjust,
		 "don't automatically adjust sleep level "
		 "according to maximum network latency");

/*
 * This defines the old power levels. They are still used by default
 * (level 1) and for thermal throttle (levels 3 through 5)
 */

struct iwl_power_vec_entry {
	struct iwl_powertable_cmd cmd;
	u8 no_dtim;	/* number of skip dtim */
};

#define IWL_DTIM_RANGE_0_MAX	2
#define IWL_DTIM_RANGE_1_MAX	10

#define NOSLP cpu_to_le16(0), 0, 0
#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
#define TU_TO_USEC 1024
#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
				     cpu_to_le32(X1), \
				     cpu_to_le32(X2), \
				     cpu_to_le32(X3), \
				     cpu_to_le32(X4)}
/* default power management (not Tx power) table values */
/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
};


/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
};

/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
};

static void iwl_static_sleep_cmd(struct iwl_priv *priv,
				 struct iwl_powertable_cmd *cmd,
				 enum iwl_power_level lvl, int period)
{
	const struct iwl_power_vec_entry *table;
	int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
	int i;
	u8 skip;
	u32 slp_itrvl;

	table = range_2;
	if (period <= IWL_DTIM_RANGE_1_MAX)
		table = range_1;
	if (period <= IWL_DTIM_RANGE_0_MAX)
		table = range_0;

	BUG_ON(lvl < 0 || lvl >= IWL_POWER_NUM);

	*cmd = table[lvl].cmd;

	if (period == 0) {
		skip = 0;
		period = 1;
		for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
			max_sleep[i] =  1;

	} else {
		skip = table[lvl].no_dtim;
		for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
			max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
		max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
	}

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	/* figure out the listen interval based on dtim period and skip */
	if (slp_itrvl == 0xFF)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32(period * (skip + 1));

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	if (slp_itrvl > period)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32((slp_itrvl / period) * period);

	if (skip)
		cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
	else
		cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);

	/* enforce max sleep interval */
	for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
		if (le32_to_cpu(cmd->sleep_interval[i]) >
		    (max_sleep[i] * period))
			cmd->sleep_interval[i] =
				cpu_to_le32(max_sleep[i] * period);
		if (i != (IWL_POWER_VEC_SIZE - 1)) {
			if (le32_to_cpu(cmd->sleep_interval[i]) >
			    le32_to_cpu(cmd->sleep_interval[i+1]))
				cmd->sleep_interval[i] =
					cmd->sleep_interval[i+1];
		}
	}

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;
	else
		cmd->flags &= ~IWL_POWER_PCI_PM_MSK;

	IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
			skip, period);
	IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
}

static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
				    struct iwl_powertable_cmd *cmd)
{
	memset(cmd, 0, sizeof(*cmd));

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;

	IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
}

static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
				     struct iwl_powertable_cmd *cmd,
				     int dynps_ms, int wakeup_period)
{
	/*
	 * These are the original power level 3 sleep successions. The
	 * device may behave better with such succession and was also
	 * only tested with that. Just like the original sleep commands,
	 * also adjust the succession here to the wakeup_period below.
	 * The ranges are the same as for the sleep commands, 0-2, 3-9
	 * and >10, which is selected based on the DTIM interval for
	 * the sleep index but here we use the wakeup period since that
	 * is what we need to do for the latency requirements.
	 */
	static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
	static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
	static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
	const u8 *slp_succ = slp_succ_r0;
	int i;

	if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
		slp_succ = slp_succ_r1;
	if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
		slp_succ = slp_succ_r2;

	memset(cmd, 0, sizeof(*cmd));

	cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
		     IWL_POWER_FAST_PD; /* no use seeing frames for others */

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;

	cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
	cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);

	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
		cmd->sleep_interval[i] =
			cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));

	IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
}

static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
{
	IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
			le32_to_cpu(cmd->sleep_interval[0]),
			le32_to_cpu(cmd->sleep_interval[1]),
			le32_to_cpu(cmd->sleep_interval[2]),
			le32_to_cpu(cmd->sleep_interval[3]),
			le32_to_cpu(cmd->sleep_interval[4]));

	return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
				sizeof(struct iwl_powertable_cmd), cmd);
}

/* priv->mutex must be held */
int iwl_power_update_mode(struct iwl_priv *priv, bool force)
{
	int ret = 0;
	bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
	bool update_chains;
	struct iwl_powertable_cmd cmd;
	int dtimper;

	/* Don't update the RX chain when chain noise calibration is running */
	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
			priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;

	dtimper = priv->hw->conf.ps_dtim_period ?: 1;

	if (priv->cfg->base_params->broken_powersave)
		iwl_power_sleep_cam_cmd(priv, &cmd);
	else if (priv->cfg->base_params->supports_idle &&
		 priv->hw->conf.flags & IEEE80211_CONF_IDLE)
		iwl_static_sleep_cmd(priv, &cmd, IWL_POWER_INDEX_5, 20);
	else if (priv->cfg->ops->lib->tt_ops.lower_power_detection &&
		 priv->cfg->ops->lib->tt_ops.tt_power_mode &&
		 priv->cfg->ops->lib->tt_ops.lower_power_detection(priv)) {
		/* in thermal throttling low power state */
		iwl_static_sleep_cmd(priv, &cmd,
		    priv->cfg->ops->lib->tt_ops.tt_power_mode(priv), dtimper);
	} else if (!enabled)
		iwl_power_sleep_cam_cmd(priv, &cmd);
	else if (priv->power_data.debug_sleep_level_override >= 0)
		iwl_static_sleep_cmd(priv, &cmd,
				     priv->power_data.debug_sleep_level_override,
				     dtimper);
	else if (no_sleep_autoadjust)
		iwl_static_sleep_cmd(priv, &cmd, IWL_POWER_INDEX_1, dtimper);
	else
		iwl_power_fill_sleep_cmd(priv, &cmd,
					 priv->hw->conf.dynamic_ps_timeout,
					 priv->hw->conf.max_sleep_period);

	if (iwl_is_ready_rf(priv) &&
	    (memcmp(&priv->power_data.sleep_cmd, &cmd, sizeof(cmd)) || force)) {
		if (cmd.flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
			set_bit(STATUS_POWER_PMI, &priv->status);

		ret = iwl_set_power(priv, &cmd);
		if (!ret) {
			if (!(cmd.flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
				clear_bit(STATUS_POWER_PMI, &priv->status);

			if (priv->cfg->ops->lib->update_chain_flags &&
			    update_chains)
				priv->cfg->ops->lib->update_chain_flags(priv);
			else if (priv->cfg->ops->lib->update_chain_flags)
				IWL_DEBUG_POWER(priv,
					"Cannot update the power, chain noise "
					"calibration running: %d\n",
					priv->chain_noise_data.state);
			memcpy(&priv->power_data.sleep_cmd, &cmd, sizeof(cmd));
		} else
			IWL_ERR(priv, "set power fail, ret = %d", ret);
	}

	return ret;
}
EXPORT_SYMBOL(iwl_power_update_mode);

/* initialize to default */
void iwl_power_initialize(struct iwl_priv *priv)
{
	u16 lctl = iwl_pcie_link_ctl(priv);

	priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);

	priv->power_data.debug_sleep_level_override = -1;

	memset(&priv->power_data.sleep_cmd, 0,
		sizeof(priv->power_data.sleep_cmd));
}
EXPORT_SYMBOL(iwl_power_initialize);
Commit	Line	Data
5da4b55f MA	1	/******************************************************************************
5da4b55f MA	2	*
1f447808	3	* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
5da4b55f MA	4	*
	5	* Portions of this file are derived from the ipw3945 project, as well
	6	* as portions of the ieee80211 subsystem header files.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of version 2 of the GNU General Public License as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	20	*
	21	* The full GNU General Public License is included in this distribution in the
	22	* file called LICENSE.
	23	*
	24	* Contact Information:
759ef89f	25	* Intel Linux Wireless <ilw@linux.intel.com>
5da4b55f MA	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*****************************************************************************/
	28
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
5a0e3ad6	32	#include <linux/slab.h>
5da4b55f MA	33	#include <linux/init.h>
	34
	35	#include <net/mac80211.h>
	36
	37	#include "iwl-eeprom.h"
3e0d4cb1	38	#include "iwl-dev.h"
5da4b55f	39	#include "iwl-core.h"
39b73fb1	40	#include "iwl-io.h"
5a36ba0e	41	#include "iwl-commands.h"
5da4b55f MA	42	#include "iwl-debug.h"
5da4b55f MA	43	#include "iwl-power.h"
5da4b55f MA	44
5da4b55f MA	45	/*
e312c24c	46	* Setting power level allows the card to go to sleep when not busy.
5da4b55f	47	*
e312c24c JB	48	* We calculate a sleep command based on the required latency, which
	49	* we get from mac80211. In order to handle thermal throttling, we can
	50	* also use pre-defined power levels.
5da4b55f MA	51	*/
5da4b55f MA	52
e312c24c JB	53	/*
	54	* For now, keep using power level 1 instead of automatically
	55	* adjusting ...
	56	*/
	57	bool no_sleep_autoadjust = true;
	58	module_param(no_sleep_autoadjust, bool, S_IRUGO);
	59	MODULE_PARM_DESC(no_sleep_autoadjust,
	60	"don't automatically adjust sleep level "
	61	"according to maximum network latency");
5da4b55f	62
e312c24c JB	63	/*
	64	* This defines the old power levels. They are still used by default
	65	* (level 1) and for thermal throttle (levels 3 through 5)
	66	*/
	67
	68	struct iwl_power_vec_entry {
	69	struct iwl_powertable_cmd cmd;
4ad177b5	70	u8 no_dtim; /* number of skip dtim */
e312c24c JB	71	};
	72
	73	#define IWL_DTIM_RANGE_0_MAX 2
	74	#define IWL_DTIM_RANGE_1_MAX 10
5da4b55f	75
7af2c460 JB	76	#define NOSLP cpu_to_le16(0), 0, 0
	77	#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
	78	#define TU_TO_USEC 1024
	79	#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
	80	#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
	81	cpu_to_le32(X1), \
	82	cpu_to_le32(X2), \
	83	cpu_to_le32(X3), \
	84	cpu_to_le32(X4)}
5da4b55f	85	/* default power management (not Tx power) table values */
e312c24c	86	/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
4ad177b5	87	/* DTIM 0 - 2 */
7af2c460	88	static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
4ad177b5	89	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
5da4b55f MA	90	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	91	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	92	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	93	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
	94	};
	95
	96
e312c24c	97	/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
4ad177b5	98	/* DTIM 3 - 10 */
7af2c460	99	static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
5da4b55f MA	100	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	101	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	102	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	103	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
4ad177b5	104	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
5da4b55f MA	105	};
5da4b55f MA	106
e312c24c	107	/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
4ad177b5	108	/* DTIM 11 - */
7af2c460	109	static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
5da4b55f MA	110	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	111	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	112	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	113	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	114	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
	115	};
	116
e312c24c JB	117	static void iwl_static_sleep_cmd(struct iwl_priv *priv,
	118	struct iwl_powertable_cmd *cmd,
	119	enum iwl_power_level lvl, int period)
	120	{
	121	const struct iwl_power_vec_entry *table;
4ad177b5 WYG	122	int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
	123	int i;
	124	u8 skip;
	125	u32 slp_itrvl;
e312c24c JB	126
e312c24c JB	127	table = range_2;
4ad177b5	128	if (period <= IWL_DTIM_RANGE_1_MAX)
e312c24c	129	table = range_1;
4ad177b5	130	if (period <= IWL_DTIM_RANGE_0_MAX)
e312c24c JB	131	table = range_0;
	132
	133	BUG_ON(lvl < 0 \|\| lvl >= IWL_POWER_NUM);
	134
	135	*cmd = table[lvl].cmd;
	136
	137	if (period == 0) {
4ad177b5	138	skip = 0;
e312c24c	139	period = 1;
4ad177b5 WYG	140	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
	141	max_sleep[i] = 1;
	142
e312c24c	143	} else {
4ad177b5 WYG	144	skip = table[lvl].no_dtim;
	145	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
	146	max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
	147	max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
e312c24c JB	148	}
e312c24c JB	149
4ad177b5 WYG	150	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	151	/* figure out the listen interval based on dtim period and skip */
	152	if (slp_itrvl == 0xFF)
	153	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
	154	cpu_to_le32(period * (skip + 1));
	155
	156	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	157	if (slp_itrvl > period)
	158	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
	159	cpu_to_le32((slp_itrvl / period) * period);
	160
	161	if (skip)
e312c24c	162	cmd->flags \|= IWL_POWER_SLEEP_OVER_DTIM_MSK;
4ad177b5	163	else
e312c24c	164	cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
e312c24c	165
4ad177b5	166	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
570af86e	167	if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
4ad177b5	168	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
570af86e	169	cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
4ad177b5 WYG	170
	171	/* enforce max sleep interval */
	172	for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
	173	if (le32_to_cpu(cmd->sleep_interval[i]) >
	174	(max_sleep[i] * period))
	175	cmd->sleep_interval[i] =
	176	cpu_to_le32(max_sleep[i] * period);
	177	if (i != (IWL_POWER_VEC_SIZE - 1)) {
	178	if (le32_to_cpu(cmd->sleep_interval[i]) >
	179	le32_to_cpu(cmd->sleep_interval[i+1]))
	180	cmd->sleep_interval[i] =
	181	cmd->sleep_interval[i+1];
	182	}
	183	}
e312c24c JB	184
	185	if (priv->power_data.pci_pm)
	186	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
	187	else
	188	cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
	189
4ad177b5 WYG	190	IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
4ad177b5 WYG	191	skip, period);
e312c24c JB	192	IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
	193	}
	194
e312c24c JB	195	static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
e312c24c JB	196	struct iwl_powertable_cmd *cmd)
5da4b55f	197	{
e312c24c	198	memset(cmd, 0, sizeof(*cmd));
5da4b55f	199
e312c24c JB	200	if (priv->power_data.pci_pm)
e312c24c JB	201	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
5da4b55f	202
e312c24c	203	IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
5da4b55f MA	204	}
5da4b55f MA	205
e312c24c JB	206	static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
	207	struct iwl_powertable_cmd *cmd,
	208	int dynps_ms, int wakeup_period)
5da4b55f	209	{
4c561a02 JB	210	/*
	211	* These are the original power level 3 sleep successions. The
	212	* device may behave better with such succession and was also
	213	* only tested with that. Just like the original sleep commands,
	214	* also adjust the succession here to the wakeup_period below.
	215	* The ranges are the same as for the sleep commands, 0-2, 3-9
	216	* and >10, which is selected based on the DTIM interval for
	217	* the sleep index but here we use the wakeup period since that
	218	* is what we need to do for the latency requirements.
	219	*/
	220	static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
	221	static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
	222	static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
	223	const u8 *slp_succ = slp_succ_r0;
5cd19c5f	224	int i;
5da4b55f	225
4c561a02 JB	226	if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
	227	slp_succ = slp_succ_r1;
	228	if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
	229	slp_succ = slp_succ_r2;
	230
e312c24c	231	memset(cmd, 0, sizeof(*cmd));
5cd19c5f	232
e312c24c JB	233	cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK \|
e312c24c JB	234	IWL_POWER_FAST_PD; /* no use seeing frames for others */
5da4b55f	235
e312c24c JB	236	if (priv->power_data.pci_pm)
e312c24c JB	237	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
5da4b55f	238
e312c24c JB	239	cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
e312c24c JB	240	cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);
5da4b55f	241
5cd19c5f	242	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
4c561a02 JB	243	cmd->sleep_interval[i] =
4c561a02 JB	244	cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));
e312c24c JB	245
	246	IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
	247	}
5da4b55f	248
e312c24c JB	249	static int iwl_set_power(struct iwl_priv priv, struct iwl_powertable_cmd cmd)
	250	{
	251	IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
e1623446 TW	252	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	253	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	254	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	255	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
5da4b55f MA	256	le32_to_cpu(cmd->sleep_interval[0]),
	257	le32_to_cpu(cmd->sleep_interval[1]),
	258	le32_to_cpu(cmd->sleep_interval[2]),
	259	le32_to_cpu(cmd->sleep_interval[3]),
	260	le32_to_cpu(cmd->sleep_interval[4]));
	261
e312c24c JB	262	return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
e312c24c JB	263	sizeof(struct iwl_powertable_cmd), cmd);
5da4b55f MA	264	}
5da4b55f MA	265
d3a57197	266	/* priv->mutex must be held */
04816448	267	int iwl_power_update_mode(struct iwl_priv *priv, bool force)
5da4b55f	268	{
5da4b55f	269	int ret = 0;
4d695921	270	bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
a71c8f62	271	bool update_chains;
e312c24c JB	272	struct iwl_powertable_cmd cmd;
e312c24c JB	273	int dtimper;
5da4b55f	274
04816448	275	/* Don't update the RX chain when chain noise calibration is running */
a71c8f62 WT	276	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE \|\|
a71c8f62 WT	277	priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
04816448	278
3a065ab3	279	dtimper = priv->hw->conf.ps_dtim_period ?: 1;
e312c24c	280
7cb1b088	281	if (priv->cfg->base_params->broken_powersave)
559a4741	282	iwl_power_sleep_cam_cmd(priv, &cmd);
7cb1b088	283	else if (priv->cfg->base_params->supports_idle &&
78f5fb7f JB	284	priv->hw->conf.flags & IEEE80211_CONF_IDLE)
78f5fb7f JB	285	iwl_static_sleep_cmd(priv, &cmd, IWL_POWER_INDEX_5, 20);
0975cc8f	286	else if (priv->cfg->ops->lib->tt_ops.lower_power_detection &&
6ddbf8cd WYG	287	priv->cfg->ops->lib->tt_ops.tt_power_mode &&
	288	priv->cfg->ops->lib->tt_ops.lower_power_detection(priv)) {
	289	/* in thermal throttling low power state */
	290	iwl_static_sleep_cmd(priv, &cmd,
	291	priv->cfg->ops->lib->tt_ops.tt_power_mode(priv), dtimper);
0975cc8f	292	} else if (!enabled)
e312c24c JB	293	iwl_power_sleep_cam_cmd(priv, &cmd);
	294	else if (priv->power_data.debug_sleep_level_override >= 0)
	295	iwl_static_sleep_cmd(priv, &cmd,
	296	priv->power_data.debug_sleep_level_override,
	297	dtimper);
	298	else if (no_sleep_autoadjust)
	299	iwl_static_sleep_cmd(priv, &cmd, IWL_POWER_INDEX_1, dtimper);
	300	else
	301	iwl_power_fill_sleep_cmd(priv, &cmd,
	302	priv->hw->conf.dynamic_ps_timeout,
	303	priv->hw->conf.max_sleep_period);
5da4b55f	304
7af2c460	305	if (iwl_is_ready_rf(priv) &&
e312c24c JB	306	(memcmp(&priv->power_data.sleep_cmd, &cmd, sizeof(cmd)) \|\| force)) {
e312c24c JB	307	if (cmd.flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
5da4b55f MA	308	set_bit(STATUS_POWER_PMI, &priv->status);
5da4b55f MA	309
ca579617	310	ret = iwl_set_power(priv, &cmd);
3a780d25	311	if (!ret) {
e312c24c	312	if (!(cmd.flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
3a780d25 WYG	313	clear_bit(STATUS_POWER_PMI, &priv->status);
	314
	315	if (priv->cfg->ops->lib->update_chain_flags &&
	316	update_chains)
	317	priv->cfg->ops->lib->update_chain_flags(priv);
b57d46aa	318	else if (priv->cfg->ops->lib->update_chain_flags)
3a780d25 WYG	319	IWL_DEBUG_POWER(priv,
3a780d25 WYG	320	"Cannot update the power, chain noise "
a71c8f62 WT	321	"calibration running: %d\n",
a71c8f62 WT	322	priv->chain_noise_data.state);
e312c24c	323	memcpy(&priv->power_data.sleep_cmd, &cmd, sizeof(cmd));
3a780d25 WYG	324	} else
3a780d25 WYG	325	IWL_ERR(priv, "set power fail, ret = %d", ret);
5da4b55f MA	326	}
	327
	328	return ret;
	329	}
	330	EXPORT_SYMBOL(iwl_power_update_mode);
	331
a96a27f9	332	/* initialize to default */
5da4b55f MA	333	void iwl_power_initialize(struct iwl_priv *priv)
5da4b55f MA	334	{
e312c24c JB	335	u16 lctl = iwl_pcie_link_ctl(priv);
	336
	337	priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
	338
	339	priv->power_data.debug_sleep_level_override = -1;
	340
	341	memset(&priv->power_data.sleep_cmd, 0,
	342	sizeof(priv->power_data.sleep_cmd));
5da4b55f MA	343	}
5da4b55f MA	344	EXPORT_SYMBOL(iwl_power_initialize);