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1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | #ifndef __iwl_trans_int_pcie_h__ | |
30 | #define __iwl_trans_int_pcie_h__ | |
31 | ||
32 | /*This file includes the declaration that are internal to the | |
33 | * trans_pcie layer */ | |
34 | ||
1f7b6172 EG |
35 | /** |
36 | * struct isr_statistics - interrupt statistics | |
37 | * | |
38 | */ | |
39 | struct isr_statistics { | |
40 | u32 hw; | |
41 | u32 sw; | |
42 | u32 err_code; | |
43 | u32 sch; | |
44 | u32 alive; | |
45 | u32 rfkill; | |
46 | u32 ctkill; | |
47 | u32 wakeup; | |
48 | u32 rx; | |
49 | u32 tx; | |
50 | u32 unhandled; | |
51 | }; | |
52 | ||
5a878bf6 EG |
53 | /** |
54 | * struct iwl_rx_queue - Rx queue | |
55 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) | |
56 | * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) | |
57 | * @pool: | |
58 | * @queue: | |
59 | * @read: Shared index to newest available Rx buffer | |
60 | * @write: Shared index to oldest written Rx packet | |
61 | * @free_count: Number of pre-allocated buffers in rx_free | |
62 | * @write_actual: | |
63 | * @rx_free: list of free SKBs for use | |
64 | * @rx_used: List of Rx buffers with no SKB | |
65 | * @need_update: flag to indicate we need to update read/write index | |
66 | * @rb_stts: driver's pointer to receive buffer status | |
67 | * @rb_stts_dma: bus address of receive buffer status | |
68 | * @lock: | |
69 | * | |
70 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers | |
71 | */ | |
72 | struct iwl_rx_queue { | |
73 | __le32 *bd; | |
74 | dma_addr_t bd_dma; | |
75 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; | |
76 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
77 | u32 read; | |
78 | u32 write; | |
79 | u32 free_count; | |
80 | u32 write_actual; | |
81 | struct list_head rx_free; | |
82 | struct list_head rx_used; | |
83 | int need_update; | |
84 | struct iwl_rb_status *rb_stts; | |
85 | dma_addr_t rb_stts_dma; | |
86 | spinlock_t lock; | |
87 | }; | |
88 | ||
e6bb4c9c EG |
89 | /** |
90 | * struct iwl_trans_pcie - PCIe transport specific data | |
5a878bf6 EG |
91 | * @rxq: all the RX queue data |
92 | * @rx_replenish: work that will be called when buffers need to be allocated | |
93 | * @trans: pointer to the generic transport area | |
105183b1 EG |
94 | * @scd_base_addr: scheduler sram base address in SRAM |
95 | * @scd_bc_tbls: pointer to the byte count table of the scheduler | |
e6bb4c9c EG |
96 | */ |
97 | struct iwl_trans_pcie { | |
5a878bf6 EG |
98 | struct iwl_rx_queue rxq; |
99 | struct work_struct rx_replenish; | |
100 | struct iwl_trans *trans; | |
0c325769 EG |
101 | |
102 | /* INT ICT Table */ | |
103 | __le32 *ict_tbl; | |
104 | void *ict_tbl_vir; | |
105 | dma_addr_t ict_tbl_dma; | |
106 | dma_addr_t aligned_ict_tbl_dma; | |
107 | int ict_index; | |
108 | u32 inta; | |
109 | bool use_ict; | |
110 | struct tasklet_struct irq_tasklet; | |
1f7b6172 | 111 | struct isr_statistics isr_stats; |
0c325769 EG |
112 | |
113 | u32 inta_mask; | |
105183b1 EG |
114 | u32 scd_base_addr; |
115 | struct iwl_dma_ptr scd_bc_tbls; | |
e6bb4c9c EG |
116 | }; |
117 | ||
5a878bf6 EG |
118 | #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \ |
119 | ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific)) | |
120 | ||
253a634c EG |
121 | /***************************************************** |
122 | * RX | |
123 | ******************************************************/ | |
ab697a9f | 124 | void iwl_bg_rx_replenish(struct work_struct *data); |
0c325769 | 125 | void iwl_irq_tasklet(struct iwl_trans *trans); |
5a878bf6 EG |
126 | void iwlagn_rx_replenish(struct iwl_trans *trans); |
127 | void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, | |
ab697a9f EG |
128 | struct iwl_rx_queue *q); |
129 | ||
1a361cd8 EG |
130 | /***************************************************** |
131 | * ICT | |
132 | ******************************************************/ | |
133 | int iwl_reset_ict(struct iwl_priv *priv); | |
0c325769 EG |
134 | void iwl_disable_ict(struct iwl_trans *trans); |
135 | int iwl_alloc_isr_ict(struct iwl_trans *trans); | |
136 | void iwl_free_isr_ict(struct iwl_trans *trans); | |
1a361cd8 EG |
137 | irqreturn_t iwl_isr_ict(int irq, void *data); |
138 | ||
253a634c EG |
139 | /***************************************************** |
140 | * TX / HCMD | |
141 | ******************************************************/ | |
142 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq); | |
6d8f6eeb | 143 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
253a634c EG |
144 | struct iwl_tx_queue *txq, |
145 | dma_addr_t addr, u16 len, u8 reset); | |
6d8f6eeb EG |
146 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id); |
147 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); | |
148 | int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, | |
e6bb4c9c | 149 | u32 flags, u16 len, const void *data); |
253a634c | 150 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb); |
6d8f6eeb | 151 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
152 | struct iwl_tx_queue *txq, |
153 | u16 byte_cnt); | |
e6bb4c9c | 154 | int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
48d42c42 | 155 | u16 ssn_idx, u8 tx_fifo); |
6d8f6eeb | 156 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index); |
48d42c42 EG |
157 | void iwl_trans_tx_queue_set_status(struct iwl_priv *priv, |
158 | struct iwl_tx_queue *txq, | |
159 | int tx_fifo_id, int scd_retry); | |
e6bb4c9c | 160 | void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid, |
48d42c42 | 161 | int frame_limit); |
6d8f6eeb | 162 | void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
04e1cabe EG |
163 | int index); |
164 | void iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, | |
165 | struct sk_buff_head *skbs); | |
253a634c | 166 | |
7ff94706 EG |
167 | /***************************************************** |
168 | * Error handling | |
169 | ******************************************************/ | |
170 | int iwl_dump_nic_event_log(struct iwl_priv *priv, | |
171 | bool full_log, char **buf, bool display); | |
172 | ||
0c325769 EG |
173 | static inline void iwl_disable_interrupts(struct iwl_trans *trans) |
174 | { | |
175 | clear_bit(STATUS_INT_ENABLED, &trans->shrd->status); | |
176 | ||
177 | /* disable interrupts from uCode/NIC to host */ | |
178 | iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000); | |
179 | ||
180 | /* acknowledge/clear/reset any interrupts still pending | |
181 | * from uCode or flow handler (Rx/Tx DMA) */ | |
182 | iwl_write32(priv(trans), CSR_INT, 0xffffffff); | |
183 | iwl_write32(priv(trans), CSR_FH_INT_STATUS, 0xffffffff); | |
184 | IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); | |
185 | } | |
186 | ||
187 | static inline void iwl_enable_interrupts(struct iwl_trans *trans) | |
188 | { | |
189 | struct iwl_trans_pcie *trans_pcie = | |
190 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
191 | ||
192 | IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); | |
193 | set_bit(STATUS_INT_ENABLED, &trans->shrd->status); | |
194 | iwl_write32(priv(trans), CSR_INT_MASK, trans_pcie->inta_mask); | |
195 | } | |
196 | ||
ab697a9f | 197 | #endif /* __iwl_trans_int_pcie_h__ */ |