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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
4e318262 | 8 | * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
4e318262 | 33 | * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
c85eb619 | 71 | #include "iwl-trans.h" |
c17d0681 | 72 | #include "iwl-trans-pcie-int.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
48f20d35 | 75 | #include "iwl-shared.h" |
522376d2 | 76 | #include "iwl-eeprom.h" |
7a10e3e4 | 77 | #include "iwl-agn-hw.h" |
c85eb619 | 78 | |
0439bb62 JB |
79 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
80 | ||
c6f600fc MV |
81 | #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \ |
82 | (((1<<cfg(trans)->base_params->num_of_queues) - 1) &\ | |
83 | (~(1<<(trans_pcie)->cmd_queue))) | |
84 | ||
5a878bf6 | 85 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
c85eb619 | 86 | { |
5a878bf6 EG |
87 | struct iwl_trans_pcie *trans_pcie = |
88 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
89 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
1042db2a | 90 | struct device *dev = trans->dev; |
c85eb619 | 91 | |
5a878bf6 | 92 | memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); |
c85eb619 EG |
93 | |
94 | spin_lock_init(&rxq->lock); | |
c85eb619 EG |
95 | |
96 | if (WARN_ON(rxq->bd || rxq->rb_stts)) | |
97 | return -EINVAL; | |
98 | ||
99 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ | |
84c816da DH |
100 | rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
101 | &rxq->bd_dma, GFP_KERNEL); | |
c85eb619 EG |
102 | if (!rxq->bd) |
103 | goto err_bd; | |
c85eb619 EG |
104 | |
105 | /*Allocate the driver's pointer to receive buffer status */ | |
84c816da DH |
106 | rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), |
107 | &rxq->rb_stts_dma, GFP_KERNEL); | |
c85eb619 EG |
108 | if (!rxq->rb_stts) |
109 | goto err_rb_stts; | |
c85eb619 EG |
110 | |
111 | return 0; | |
112 | ||
113 | err_rb_stts: | |
a0f6b0a2 EG |
114 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
115 | rxq->bd, rxq->bd_dma); | |
c85eb619 EG |
116 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
117 | rxq->bd = NULL; | |
118 | err_bd: | |
119 | return -ENOMEM; | |
120 | } | |
121 | ||
5a878bf6 | 122 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans) |
c85eb619 | 123 | { |
5a878bf6 EG |
124 | struct iwl_trans_pcie *trans_pcie = |
125 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
126 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
a0f6b0a2 | 127 | int i; |
c85eb619 EG |
128 | |
129 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
130 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
131 | /* In the reset function, these buffers may have been allocated | |
132 | * to an SKB, so we need to unmap and free potential storage */ | |
133 | if (rxq->pool[i].page != NULL) { | |
1042db2a | 134 | dma_unmap_page(trans->dev, rxq->pool[i].page_dma, |
5a878bf6 | 135 | PAGE_SIZE << hw_params(trans).rx_page_order, |
c85eb619 | 136 | DMA_FROM_DEVICE); |
790428b6 EG |
137 | __free_pages(rxq->pool[i].page, |
138 | hw_params(trans).rx_page_order); | |
c85eb619 EG |
139 | rxq->pool[i].page = NULL; |
140 | } | |
141 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
142 | } | |
a0f6b0a2 EG |
143 | } |
144 | ||
fd656935 | 145 | static void iwl_trans_rx_hw_init(struct iwl_trans *trans, |
ab697a9f EG |
146 | struct iwl_rx_queue *rxq) |
147 | { | |
148 | u32 rb_size; | |
149 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
c17d0681 | 150 | u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
ab697a9f EG |
151 | |
152 | if (iwlagn_mod_params.amsdu_size_8K) | |
153 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
154 | else | |
155 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
156 | ||
157 | /* Stop Rx DMA */ | |
1042db2a | 158 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
ab697a9f EG |
159 | |
160 | /* Reset driver's Rx queue write index */ | |
1042db2a | 161 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
ab697a9f EG |
162 | |
163 | /* Tell device where to find RBD circular buffer in DRAM */ | |
1042db2a | 164 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
ab697a9f EG |
165 | (u32)(rxq->bd_dma >> 8)); |
166 | ||
167 | /* Tell device where in DRAM to update its Rx status */ | |
1042db2a | 168 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, |
ab697a9f EG |
169 | rxq->rb_stts_dma >> 4); |
170 | ||
171 | /* Enable Rx DMA | |
172 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in | |
173 | * the credit mechanism in 5000 HW RX FIFO | |
174 | * Direct rx interrupts to hosts | |
175 | * Rx buffer size 4 or 8k | |
176 | * RB timeout 0x10 | |
177 | * 256 RBDs | |
178 | */ | |
1042db2a | 179 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
ab697a9f EG |
180 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
181 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | | |
182 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
183 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | | |
184 | rb_size| | |
185 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
186 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
187 | ||
188 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
1042db2a | 189 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); |
ab697a9f EG |
190 | } |
191 | ||
5a878bf6 | 192 | static int iwl_rx_init(struct iwl_trans *trans) |
a0f6b0a2 | 193 | { |
5a878bf6 EG |
194 | struct iwl_trans_pcie *trans_pcie = |
195 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
196 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
197 | ||
a0f6b0a2 EG |
198 | int i, err; |
199 | unsigned long flags; | |
200 | ||
201 | if (!rxq->bd) { | |
5a878bf6 | 202 | err = iwl_trans_rx_alloc(trans); |
a0f6b0a2 EG |
203 | if (err) |
204 | return err; | |
205 | } | |
206 | ||
207 | spin_lock_irqsave(&rxq->lock, flags); | |
208 | INIT_LIST_HEAD(&rxq->rx_free); | |
209 | INIT_LIST_HEAD(&rxq->rx_used); | |
210 | ||
5a878bf6 | 211 | iwl_trans_rxq_free_rx_bufs(trans); |
c85eb619 EG |
212 | |
213 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
214 | rxq->queue[i] = NULL; | |
215 | ||
216 | /* Set us so that we have processed and used all buffers, but have | |
217 | * not restocked the Rx queue with fresh buffers */ | |
218 | rxq->read = rxq->write = 0; | |
219 | rxq->write_actual = 0; | |
220 | rxq->free_count = 0; | |
221 | spin_unlock_irqrestore(&rxq->lock, flags); | |
222 | ||
5a878bf6 | 223 | iwlagn_rx_replenish(trans); |
ab697a9f | 224 | |
fd656935 | 225 | iwl_trans_rx_hw_init(trans, rxq); |
ab697a9f | 226 | |
7b11488f | 227 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ab697a9f | 228 | rxq->need_update = 1; |
5a878bf6 | 229 | iwl_rx_queue_update_write_ptr(trans, rxq); |
7b11488f | 230 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ab697a9f | 231 | |
c85eb619 EG |
232 | return 0; |
233 | } | |
234 | ||
5a878bf6 | 235 | static void iwl_trans_pcie_rx_free(struct iwl_trans *trans) |
a0f6b0a2 | 236 | { |
5a878bf6 EG |
237 | struct iwl_trans_pcie *trans_pcie = |
238 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
239 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
240 | ||
a0f6b0a2 EG |
241 | unsigned long flags; |
242 | ||
243 | /*if rxq->bd is NULL, it means that nothing has been allocated, | |
244 | * exit now */ | |
245 | if (!rxq->bd) { | |
5a878bf6 | 246 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
a0f6b0a2 EG |
247 | return; |
248 | } | |
249 | ||
250 | spin_lock_irqsave(&rxq->lock, flags); | |
5a878bf6 | 251 | iwl_trans_rxq_free_rx_bufs(trans); |
a0f6b0a2 EG |
252 | spin_unlock_irqrestore(&rxq->lock, flags); |
253 | ||
1042db2a | 254 | dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE, |
a0f6b0a2 EG |
255 | rxq->bd, rxq->bd_dma); |
256 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); | |
257 | rxq->bd = NULL; | |
258 | ||
259 | if (rxq->rb_stts) | |
1042db2a | 260 | dma_free_coherent(trans->dev, |
a0f6b0a2 EG |
261 | sizeof(struct iwl_rb_status), |
262 | rxq->rb_stts, rxq->rb_stts_dma); | |
263 | else | |
5a878bf6 | 264 | IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n"); |
a0f6b0a2 EG |
265 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); |
266 | rxq->rb_stts = NULL; | |
267 | } | |
268 | ||
6d8f6eeb | 269 | static int iwl_trans_rx_stop(struct iwl_trans *trans) |
c2c52e8b EG |
270 | { |
271 | ||
272 | /* stop Rx DMA */ | |
1042db2a EG |
273 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
274 | return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, | |
c2c52e8b EG |
275 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
276 | } | |
277 | ||
6d8f6eeb | 278 | static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans, |
02aca585 EG |
279 | struct iwl_dma_ptr *ptr, size_t size) |
280 | { | |
281 | if (WARN_ON(ptr->addr)) | |
282 | return -EINVAL; | |
283 | ||
1042db2a | 284 | ptr->addr = dma_alloc_coherent(trans->dev, size, |
02aca585 EG |
285 | &ptr->dma, GFP_KERNEL); |
286 | if (!ptr->addr) | |
287 | return -ENOMEM; | |
288 | ptr->size = size; | |
289 | return 0; | |
290 | } | |
291 | ||
6d8f6eeb | 292 | static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans, |
1359ca4f EG |
293 | struct iwl_dma_ptr *ptr) |
294 | { | |
295 | if (unlikely(!ptr->addr)) | |
296 | return; | |
297 | ||
1042db2a | 298 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); |
1359ca4f EG |
299 | memset(ptr, 0, sizeof(*ptr)); |
300 | } | |
301 | ||
6d8f6eeb EG |
302 | static int iwl_trans_txq_alloc(struct iwl_trans *trans, |
303 | struct iwl_tx_queue *txq, int slots_num, | |
304 | u32 txq_id) | |
02aca585 | 305 | { |
ab9e212e | 306 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; |
02aca585 | 307 | int i; |
c6f600fc | 308 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 309 | |
2c452297 | 310 | if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds)) |
02aca585 EG |
311 | return -EINVAL; |
312 | ||
1359ca4f EG |
313 | txq->q.n_window = slots_num; |
314 | ||
7f90dce1 EG |
315 | txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL); |
316 | txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL); | |
02aca585 EG |
317 | |
318 | if (!txq->meta || !txq->cmd) | |
319 | goto error; | |
320 | ||
c6f600fc | 321 | if (txq_id == trans_pcie->cmd_queue) |
dfa2bdba EG |
322 | for (i = 0; i < slots_num; i++) { |
323 | txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd), | |
324 | GFP_KERNEL); | |
325 | if (!txq->cmd[i]) | |
326 | goto error; | |
327 | } | |
02aca585 EG |
328 | |
329 | /* Alloc driver data array and TFD circular buffer */ | |
330 | /* Driver private data, only for Tx (not command) queues, | |
331 | * not shared with device. */ | |
c6f600fc | 332 | if (txq_id != trans_pcie->cmd_queue) { |
7f90dce1 EG |
333 | txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]), |
334 | GFP_KERNEL); | |
2c452297 | 335 | if (!txq->skbs) { |
6d8f6eeb | 336 | IWL_ERR(trans, "kmalloc for auxiliary BD " |
02aca585 EG |
337 | "structures failed\n"); |
338 | goto error; | |
339 | } | |
340 | } else { | |
2c452297 | 341 | txq->skbs = NULL; |
02aca585 EG |
342 | } |
343 | ||
344 | /* Circular buffer of transmit frame descriptors (TFDs), | |
345 | * shared with device */ | |
1042db2a | 346 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, |
6d8f6eeb | 347 | &txq->q.dma_addr, GFP_KERNEL); |
02aca585 | 348 | if (!txq->tfds) { |
6d8f6eeb | 349 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); |
02aca585 EG |
350 | goto error; |
351 | } | |
352 | txq->q.id = txq_id; | |
353 | ||
354 | return 0; | |
355 | error: | |
2c452297 EG |
356 | kfree(txq->skbs); |
357 | txq->skbs = NULL; | |
02aca585 EG |
358 | /* since txq->cmd has been zeroed, |
359 | * all non allocated cmd[i] will be NULL */ | |
c6f600fc | 360 | if (txq->cmd && txq_id == trans_pcie->cmd_queue) |
02aca585 EG |
361 | for (i = 0; i < slots_num; i++) |
362 | kfree(txq->cmd[i]); | |
363 | kfree(txq->meta); | |
364 | kfree(txq->cmd); | |
365 | txq->meta = NULL; | |
366 | txq->cmd = NULL; | |
367 | ||
368 | return -ENOMEM; | |
369 | ||
370 | } | |
371 | ||
6d8f6eeb | 372 | static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
02aca585 EG |
373 | int slots_num, u32 txq_id) |
374 | { | |
375 | int ret; | |
376 | ||
377 | txq->need_update = 0; | |
378 | memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num); | |
379 | ||
380 | /* | |
381 | * For the default queues 0-3, set up the swq_id | |
382 | * already -- all others need to get one later | |
383 | * (if they need one at all). | |
384 | */ | |
385 | if (txq_id < 4) | |
386 | iwl_set_swq_id(txq, txq_id, txq_id); | |
387 | ||
388 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
389 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
390 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
391 | ||
392 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
6d8f6eeb | 393 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, |
02aca585 EG |
394 | txq_id); |
395 | if (ret) | |
396 | return ret; | |
397 | ||
015c15e1 JB |
398 | spin_lock_init(&txq->lock); |
399 | ||
02aca585 EG |
400 | /* |
401 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
402 | * given Tx queue, and enable the DMA channel used for that queue. | |
403 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
1042db2a | 404 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), |
02aca585 EG |
405 | txq->q.dma_addr >> 8); |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
c170b867 EG |
410 | /** |
411 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
412 | */ | |
6d8f6eeb | 413 | static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id) |
c170b867 | 414 | { |
8ad71bef EG |
415 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
416 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
c170b867 | 417 | struct iwl_queue *q = &txq->q; |
39644e9a | 418 | enum dma_data_direction dma_dir; |
c170b867 EG |
419 | |
420 | if (!q->n_bd) | |
421 | return; | |
422 | ||
39644e9a EG |
423 | /* In the command queue, all the TBs are mapped as BIDI |
424 | * so unmap them as such. | |
425 | */ | |
c6f600fc | 426 | if (txq_id == trans_pcie->cmd_queue) |
39644e9a | 427 | dma_dir = DMA_BIDIRECTIONAL; |
015c15e1 | 428 | else |
39644e9a EG |
429 | dma_dir = DMA_TO_DEVICE; |
430 | ||
015c15e1 | 431 | spin_lock_bh(&txq->lock); |
c170b867 EG |
432 | while (q->write_ptr != q->read_ptr) { |
433 | /* The read_ptr needs to bound by q->n_window */ | |
39644e9a EG |
434 | iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr), |
435 | dma_dir); | |
c170b867 EG |
436 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
437 | } | |
015c15e1 | 438 | spin_unlock_bh(&txq->lock); |
c170b867 EG |
439 | } |
440 | ||
1359ca4f EG |
441 | /** |
442 | * iwl_tx_queue_free - Deallocate DMA queue. | |
443 | * @txq: Transmit queue to deallocate. | |
444 | * | |
445 | * Empty queue by removing and destroying all BD's. | |
446 | * Free all buffers. | |
447 | * 0-fill, but do not free "txq" descriptor structure. | |
448 | */ | |
6d8f6eeb | 449 | static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id) |
1359ca4f | 450 | { |
8ad71bef EG |
451 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
452 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
1042db2a | 453 | struct device *dev = trans->dev; |
1359ca4f EG |
454 | int i; |
455 | if (WARN_ON(!txq)) | |
456 | return; | |
457 | ||
6d8f6eeb | 458 | iwl_tx_queue_unmap(trans, txq_id); |
1359ca4f EG |
459 | |
460 | /* De-alloc array of command/tx buffers */ | |
dfa2bdba | 461 | |
c6f600fc | 462 | if (txq_id == trans_pcie->cmd_queue) |
dfa2bdba EG |
463 | for (i = 0; i < txq->q.n_window; i++) |
464 | kfree(txq->cmd[i]); | |
1359ca4f EG |
465 | |
466 | /* De-alloc circular buffer of TFDs */ | |
467 | if (txq->q.n_bd) { | |
ab9e212e | 468 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * |
1359ca4f EG |
469 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
470 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
471 | } | |
472 | ||
473 | /* De-alloc array of per-TFD driver data */ | |
2c452297 EG |
474 | kfree(txq->skbs); |
475 | txq->skbs = NULL; | |
1359ca4f EG |
476 | |
477 | /* deallocate arrays */ | |
478 | kfree(txq->cmd); | |
479 | kfree(txq->meta); | |
480 | txq->cmd = NULL; | |
481 | txq->meta = NULL; | |
482 | ||
483 | /* 0-fill queue descriptor structure */ | |
484 | memset(txq, 0, sizeof(*txq)); | |
485 | } | |
486 | ||
487 | /** | |
488 | * iwl_trans_tx_free - Free TXQ Context | |
489 | * | |
490 | * Destroy all TX DMA queues and structures | |
491 | */ | |
6d8f6eeb | 492 | static void iwl_trans_pcie_tx_free(struct iwl_trans *trans) |
1359ca4f EG |
493 | { |
494 | int txq_id; | |
8ad71bef | 495 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1359ca4f EG |
496 | |
497 | /* Tx queues */ | |
8ad71bef | 498 | if (trans_pcie->txq) { |
d6189124 | 499 | for (txq_id = 0; |
1745e440 | 500 | txq_id < cfg(trans)->base_params->num_of_queues; txq_id++) |
6d8f6eeb | 501 | iwl_tx_queue_free(trans, txq_id); |
1359ca4f EG |
502 | } |
503 | ||
8ad71bef EG |
504 | kfree(trans_pcie->txq); |
505 | trans_pcie->txq = NULL; | |
1359ca4f | 506 | |
9d6b2cb1 | 507 | iwlagn_free_dma_ptr(trans, &trans_pcie->kw); |
1359ca4f | 508 | |
6d8f6eeb | 509 | iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); |
1359ca4f EG |
510 | } |
511 | ||
02aca585 EG |
512 | /** |
513 | * iwl_trans_tx_alloc - allocate TX context | |
514 | * Allocate all Tx DMA structures and initialize them | |
515 | * | |
516 | * @param priv | |
517 | * @return error code | |
518 | */ | |
6d8f6eeb | 519 | static int iwl_trans_tx_alloc(struct iwl_trans *trans) |
02aca585 EG |
520 | { |
521 | int ret; | |
522 | int txq_id, slots_num; | |
8ad71bef | 523 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 524 | |
1745e440 | 525 | u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues * |
ab9e212e EG |
526 | sizeof(struct iwlagn_scd_bc_tbl); |
527 | ||
02aca585 EG |
528 | /*It is not allowed to alloc twice, so warn when this happens. |
529 | * We cannot rely on the previous allocation, so free and fail */ | |
8ad71bef | 530 | if (WARN_ON(trans_pcie->txq)) { |
02aca585 EG |
531 | ret = -EINVAL; |
532 | goto error; | |
533 | } | |
534 | ||
6d8f6eeb | 535 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, |
ab9e212e | 536 | scd_bc_tbls_size); |
02aca585 | 537 | if (ret) { |
6d8f6eeb | 538 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); |
02aca585 EG |
539 | goto error; |
540 | } | |
541 | ||
542 | /* Alloc keep-warm buffer */ | |
9d6b2cb1 | 543 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); |
02aca585 | 544 | if (ret) { |
6d8f6eeb | 545 | IWL_ERR(trans, "Keep Warm allocation failed\n"); |
02aca585 EG |
546 | goto error; |
547 | } | |
548 | ||
1745e440 | 549 | trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues, |
7f90dce1 | 550 | sizeof(struct iwl_tx_queue), GFP_KERNEL); |
8ad71bef | 551 | if (!trans_pcie->txq) { |
6d8f6eeb | 552 | IWL_ERR(trans, "Not enough memory for txq\n"); |
02aca585 EG |
553 | ret = ENOMEM; |
554 | goto error; | |
555 | } | |
556 | ||
557 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
1745e440 WYG |
558 | for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues; |
559 | txq_id++) { | |
9ba1947a | 560 | slots_num = (txq_id == trans_pcie->cmd_queue) ? |
02aca585 | 561 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
562 | ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id], |
563 | slots_num, txq_id); | |
02aca585 | 564 | if (ret) { |
6d8f6eeb | 565 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); |
02aca585 EG |
566 | goto error; |
567 | } | |
568 | } | |
569 | ||
570 | return 0; | |
571 | ||
572 | error: | |
ae2c30bf | 573 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
574 | |
575 | return ret; | |
576 | } | |
6d8f6eeb | 577 | static int iwl_tx_init(struct iwl_trans *trans) |
02aca585 EG |
578 | { |
579 | int ret; | |
580 | int txq_id, slots_num; | |
581 | unsigned long flags; | |
582 | bool alloc = false; | |
8ad71bef | 583 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 584 | |
8ad71bef | 585 | if (!trans_pcie->txq) { |
6d8f6eeb | 586 | ret = iwl_trans_tx_alloc(trans); |
02aca585 EG |
587 | if (ret) |
588 | goto error; | |
589 | alloc = true; | |
590 | } | |
591 | ||
7b11488f | 592 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
02aca585 EG |
593 | |
594 | /* Turn off all Tx DMA fifos */ | |
1042db2a | 595 | iwl_write_prph(trans, SCD_TXFACT, 0); |
02aca585 EG |
596 | |
597 | /* Tell NIC where to find the "keep warm" buffer */ | |
1042db2a | 598 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, |
83ed9015 | 599 | trans_pcie->kw.dma >> 4); |
02aca585 | 600 | |
7b11488f | 601 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
02aca585 EG |
602 | |
603 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
1745e440 WYG |
604 | for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues; |
605 | txq_id++) { | |
9ba1947a | 606 | slots_num = (txq_id == trans_pcie->cmd_queue) ? |
02aca585 | 607 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
608 | ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id], |
609 | slots_num, txq_id); | |
02aca585 | 610 | if (ret) { |
6d8f6eeb | 611 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); |
02aca585 EG |
612 | goto error; |
613 | } | |
614 | } | |
615 | ||
616 | return 0; | |
617 | error: | |
618 | /*Upon error, free only if we allocated something */ | |
619 | if (alloc) | |
ae2c30bf | 620 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
621 | return ret; |
622 | } | |
623 | ||
3e10caeb | 624 | static void iwl_set_pwr_vmain(struct iwl_trans *trans) |
392f8b78 EG |
625 | { |
626 | /* | |
627 | * (for documentation purposes) | |
628 | * to set power to V_AUX, do: | |
629 | ||
630 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
1042db2a | 631 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
632 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
633 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
634 | */ | |
635 | ||
1042db2a | 636 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
637 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
638 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
639 | } | |
640 | ||
af634bee EG |
641 | /* PCI registers */ |
642 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
643 | #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 | |
644 | #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 | |
645 | ||
646 | static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans) | |
647 | { | |
648 | int pos; | |
649 | u16 pci_lnk_ctl; | |
650 | struct iwl_trans_pcie *trans_pcie = | |
651 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
652 | ||
653 | struct pci_dev *pci_dev = trans_pcie->pci_dev; | |
654 | ||
655 | pos = pci_pcie_cap(pci_dev); | |
656 | pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl); | |
657 | return pci_lnk_ctl; | |
658 | } | |
659 | ||
660 | static void iwl_apm_config(struct iwl_trans *trans) | |
661 | { | |
662 | /* | |
663 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
664 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
665 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
666 | * costs negligible amount of power savings. | |
667 | * If not (unlikely), enable L0S, so there is at least some | |
668 | * power savings, even without L1. | |
669 | */ | |
670 | u16 lctl = iwl_pciexp_link_ctrl(trans); | |
671 | ||
672 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == | |
673 | PCI_CFG_LINK_CTRL_VAL_L1_EN) { | |
674 | /* L1-ASPM enabled; disable(!) L0S */ | |
675 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
676 | dev_printk(KERN_INFO, trans->dev, | |
677 | "L1 Enabled; Disabling L0S\n"); | |
678 | } else { | |
679 | /* L1-ASPM disabled; enable(!) L0S */ | |
680 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
681 | dev_printk(KERN_INFO, trans->dev, | |
682 | "L1 Disabled; Enabling L0S\n"); | |
683 | } | |
f6d0e9be | 684 | trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); |
af634bee EG |
685 | } |
686 | ||
a6c684ee EG |
687 | /* |
688 | * Start up NIC's basic functionality after it has been reset | |
689 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) | |
690 | * NOTE: This does not load uCode nor start the embedded processor | |
691 | */ | |
692 | static int iwl_apm_init(struct iwl_trans *trans) | |
693 | { | |
83626404 | 694 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a6c684ee EG |
695 | int ret = 0; |
696 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
697 | ||
698 | /* | |
699 | * Use "set_bit" below rather than "write", to preserve any hardware | |
700 | * bits already set by default after reset. | |
701 | */ | |
702 | ||
703 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
704 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
705 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
706 | ||
707 | /* | |
708 | * Disable L0s without affecting L1; | |
709 | * don't wait for ICH L0s (ICH bug W/A) | |
710 | */ | |
711 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
712 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
713 | ||
714 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
715 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
716 | ||
717 | /* | |
718 | * Enable HAP INTA (interrupt from management bus) to | |
719 | * wake device's PCI Express link L1a -> L0s | |
720 | */ | |
721 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
722 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
723 | ||
af634bee | 724 | iwl_apm_config(trans); |
a6c684ee EG |
725 | |
726 | /* Configure analog phase-lock-loop before activating to D0A */ | |
727 | if (cfg(trans)->base_params->pll_cfg_val) | |
728 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, | |
729 | cfg(trans)->base_params->pll_cfg_val); | |
730 | ||
731 | /* | |
732 | * Set "initialization complete" bit to move adapter from | |
733 | * D0U* --> D0A* (powered-up active) state. | |
734 | */ | |
735 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
736 | ||
737 | /* | |
738 | * Wait for clock stabilization; once stabilized, access to | |
739 | * device-internal resources is supported, e.g. iwl_write_prph() | |
740 | * and accesses to uCode SRAM. | |
741 | */ | |
742 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
743 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
744 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
745 | if (ret < 0) { | |
746 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
747 | goto out; | |
748 | } | |
749 | ||
750 | /* | |
751 | * Enable DMA clock and wait for it to stabilize. | |
752 | * | |
753 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
754 | * do not disable clocks. This preserves any hardware bits already | |
755 | * set by default in "CLK_CTRL_REG" after reset. | |
756 | */ | |
757 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
758 | udelay(20); | |
759 | ||
760 | /* Disable L1-Active */ | |
761 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
762 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
763 | ||
83626404 | 764 | set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
a6c684ee EG |
765 | |
766 | out: | |
767 | return ret; | |
768 | } | |
769 | ||
cc56feb2 EG |
770 | static int iwl_apm_stop_master(struct iwl_trans *trans) |
771 | { | |
772 | int ret = 0; | |
773 | ||
774 | /* stop device's busmaster DMA activity */ | |
775 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
776 | ||
777 | ret = iwl_poll_bit(trans, CSR_RESET, | |
778 | CSR_RESET_REG_FLAG_MASTER_DISABLED, | |
779 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
780 | if (ret) | |
781 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
782 | ||
783 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
784 | ||
785 | return ret; | |
786 | } | |
787 | ||
788 | static void iwl_apm_stop(struct iwl_trans *trans) | |
789 | { | |
83626404 | 790 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cc56feb2 EG |
791 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); |
792 | ||
83626404 | 793 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
cc56feb2 EG |
794 | |
795 | /* Stop device's DMA activity */ | |
796 | iwl_apm_stop_master(trans); | |
797 | ||
798 | /* Reset the entire device */ | |
799 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
800 | ||
801 | udelay(10); | |
802 | ||
803 | /* | |
804 | * Clear "initialization complete" bit to move adapter from | |
805 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
806 | */ | |
807 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
808 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
809 | } | |
810 | ||
6d8f6eeb | 811 | static int iwl_nic_init(struct iwl_trans *trans) |
392f8b78 | 812 | { |
7b11488f | 813 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
814 | unsigned long flags; |
815 | ||
816 | /* nic_init */ | |
7b11488f | 817 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
a6c684ee | 818 | iwl_apm_init(trans); |
392f8b78 EG |
819 | |
820 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
1042db2a | 821 | iwl_write8(trans, CSR_INT_COALESCING, |
83ed9015 | 822 | IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
392f8b78 | 823 | |
7b11488f | 824 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 825 | |
3e10caeb | 826 | iwl_set_pwr_vmain(trans); |
392f8b78 | 827 | |
ecdb975c | 828 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 | 829 | |
a5916977 | 830 | #ifndef CONFIG_IWLWIFI_IDI |
392f8b78 | 831 | /* Allocate the RX queue, or reset if it is already allocated */ |
6d8f6eeb | 832 | iwl_rx_init(trans); |
a5916977 | 833 | #endif |
392f8b78 EG |
834 | |
835 | /* Allocate or reset and init all Tx and Command queues */ | |
6d8f6eeb | 836 | if (iwl_tx_init(trans)) |
392f8b78 EG |
837 | return -ENOMEM; |
838 | ||
0dde86b2 | 839 | if (cfg(trans)->base_params->shadow_reg_enable) { |
392f8b78 | 840 | /* enable shadow regs in HW */ |
1042db2a | 841 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, |
392f8b78 EG |
842 | 0x800FFFFF); |
843 | } | |
844 | ||
392f8b78 EG |
845 | return 0; |
846 | } | |
847 | ||
848 | #define HW_READY_TIMEOUT (50) | |
849 | ||
850 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
6d8f6eeb | 851 | static int iwl_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
852 | { |
853 | int ret; | |
854 | ||
1042db2a | 855 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
856 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
857 | ||
858 | /* See if we got it */ | |
1042db2a | 859 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
860 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
861 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
862 | HW_READY_TIMEOUT); | |
863 | ||
6d8f6eeb | 864 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
865 | return ret; |
866 | } | |
867 | ||
868 | /* Note: returns standard 0/-ERROR code */ | |
ebb7678d | 869 | static int iwl_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
870 | { |
871 | int ret; | |
872 | ||
6d8f6eeb | 873 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 874 | |
6d8f6eeb | 875 | ret = iwl_set_hw_ready(trans); |
ebb7678d | 876 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
877 | if (ret >= 0) |
878 | return 0; | |
879 | ||
880 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 881 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
882 | CSR_HW_IF_CONFIG_REG_PREPARE); |
883 | ||
1042db2a | 884 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
885 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, |
886 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
887 | ||
888 | if (ret < 0) | |
889 | return ret; | |
890 | ||
891 | /* HW should be ready by now, check again. */ | |
6d8f6eeb | 892 | ret = iwl_set_hw_ready(trans); |
392f8b78 EG |
893 | if (ret >= 0) |
894 | return 0; | |
895 | return ret; | |
896 | } | |
897 | ||
e13c0c59 EG |
898 | #define IWL_AC_UNSET -1 |
899 | ||
900 | struct queue_to_fifo_ac { | |
901 | s8 fifo, ac; | |
902 | }; | |
903 | ||
904 | static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = { | |
905 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
906 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
907 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
908 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
909 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
910 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
911 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
912 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
913 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
914 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
915 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
916 | }; | |
917 | ||
918 | static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = { | |
919 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
920 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
921 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
922 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
923 | { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, }, | |
924 | { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, }, | |
925 | { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, }, | |
926 | { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, }, | |
927 | { IWL_TX_FIFO_BE_IPAN, 2, }, | |
928 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
929 | { IWL_TX_FIFO_AUX, IWL_AC_UNSET, }, | |
930 | }; | |
931 | ||
932 | static const u8 iwlagn_bss_ac_to_fifo[] = { | |
933 | IWL_TX_FIFO_VO, | |
934 | IWL_TX_FIFO_VI, | |
935 | IWL_TX_FIFO_BE, | |
936 | IWL_TX_FIFO_BK, | |
937 | }; | |
938 | static const u8 iwlagn_bss_ac_to_queue[] = { | |
939 | 0, 1, 2, 3, | |
940 | }; | |
941 | static const u8 iwlagn_pan_ac_to_fifo[] = { | |
942 | IWL_TX_FIFO_VO_IPAN, | |
943 | IWL_TX_FIFO_VI_IPAN, | |
944 | IWL_TX_FIFO_BE_IPAN, | |
945 | IWL_TX_FIFO_BK_IPAN, | |
946 | }; | |
947 | static const u8 iwlagn_pan_ac_to_queue[] = { | |
948 | 7, 6, 5, 4, | |
949 | }; | |
950 | ||
cf614297 EG |
951 | /* |
952 | * ucode | |
953 | */ | |
954 | static int iwl_load_section(struct iwl_trans *trans, const char *name, | |
0692fe41 | 955 | const struct fw_desc *image, u32 dst_addr) |
cf614297 | 956 | { |
13df1aab | 957 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
958 | dma_addr_t phy_addr = image->p_addr; |
959 | u32 byte_cnt = image->len; | |
960 | int ret; | |
961 | ||
13df1aab | 962 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
963 | |
964 | iwl_write_direct32(trans, | |
965 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
966 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
967 | ||
968 | iwl_write_direct32(trans, | |
969 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); | |
970 | ||
971 | iwl_write_direct32(trans, | |
972 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
973 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
974 | ||
975 | iwl_write_direct32(trans, | |
976 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), | |
977 | (iwl_get_dma_hi_addr(phy_addr) | |
978 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
979 | ||
980 | iwl_write_direct32(trans, | |
981 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
982 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
983 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
984 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
985 | ||
986 | iwl_write_direct32(trans, | |
987 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
988 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
989 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
990 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
991 | ||
992 | IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name); | |
13df1aab JB |
993 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
994 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 EG |
995 | if (!ret) { |
996 | IWL_ERR(trans, "Could not load the %s uCode section\n", | |
997 | name); | |
998 | return -ETIMEDOUT; | |
999 | } | |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | ||
0692fe41 JB |
1004 | static int iwl_load_given_ucode(struct iwl_trans *trans, |
1005 | const struct fw_img *image) | |
cf614297 EG |
1006 | { |
1007 | int ret = 0; | |
1008 | ||
1009 | ret = iwl_load_section(trans, "INST", &image->code, | |
1010 | IWLAGN_RTC_INST_LOWER_BOUND); | |
1011 | if (ret) | |
1012 | return ret; | |
1013 | ||
1014 | ret = iwl_load_section(trans, "DATA", &image->data, | |
1015 | IWLAGN_RTC_DATA_LOWER_BOUND); | |
1016 | if (ret) | |
1017 | return ret; | |
1018 | ||
1019 | /* Remove all resets to allow NIC to operate */ | |
1020 | iwl_write32(trans, CSR_RESET, 0); | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
0692fe41 JB |
1025 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
1026 | const struct fw_img *fw) | |
392f8b78 EG |
1027 | { |
1028 | int ret; | |
e13c0c59 EG |
1029 | struct iwl_trans_pcie *trans_pcie = |
1030 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
c9eec95c | 1031 | bool hw_rfkill; |
392f8b78 | 1032 | |
e13c0c59 EG |
1033 | trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue; |
1034 | trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue; | |
1035 | ||
1036 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo; | |
1037 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo; | |
1038 | ||
1039 | trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0; | |
1040 | trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE; | |
392f8b78 | 1041 | |
496bab39 JB |
1042 | /* This may fail if AMT took ownership of the device */ |
1043 | if (iwl_prepare_card_hw(trans)) { | |
6d8f6eeb | 1044 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
1045 | return -EIO; |
1046 | } | |
1047 | ||
1048 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
c9eec95c JB |
1049 | hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) & |
1050 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
1051 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
392f8b78 | 1052 | |
c9eec95c | 1053 | if (hw_rfkill) { |
8722c899 | 1054 | iwl_enable_rfkill_int(trans); |
392f8b78 EG |
1055 | return -ERFKILL; |
1056 | } | |
1057 | ||
1042db2a | 1058 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 1059 | |
6d8f6eeb | 1060 | ret = iwl_nic_init(trans); |
392f8b78 | 1061 | if (ret) { |
6d8f6eeb | 1062 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
1063 | return ret; |
1064 | } | |
1065 | ||
1066 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
1067 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1068 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
1069 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1070 | ||
1071 | /* clear (again), then enable host interrupts */ | |
1042db2a | 1072 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 1073 | iwl_enable_interrupts(trans); |
392f8b78 EG |
1074 | |
1075 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
1076 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1077 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 1078 | |
cf614297 | 1079 | /* Load the given image to the HW */ |
9441b85d | 1080 | return iwl_load_given_ucode(trans, fw); |
392f8b78 EG |
1081 | } |
1082 | ||
b3c2ce13 EG |
1083 | /* |
1084 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
7b11488f | 1085 | * must be called under the irq lock and with MAC access |
b3c2ce13 | 1086 | */ |
6d8f6eeb | 1087 | static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) |
b3c2ce13 | 1088 | { |
7b11488f JB |
1089 | struct iwl_trans_pcie __maybe_unused *trans_pcie = |
1090 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1091 | ||
1092 | lockdep_assert_held(&trans_pcie->irq_lock); | |
1093 | ||
1042db2a | 1094 | iwl_write_prph(trans, SCD_TXFACT, mask); |
b3c2ce13 EG |
1095 | } |
1096 | ||
ed6a3803 | 1097 | static void iwl_tx_start(struct iwl_trans *trans) |
b3c2ce13 EG |
1098 | { |
1099 | const struct queue_to_fifo_ac *queue_to_fifo; | |
105183b1 EG |
1100 | struct iwl_trans_pcie *trans_pcie = |
1101 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
b3c2ce13 EG |
1102 | u32 a; |
1103 | unsigned long flags; | |
1104 | int i, chan; | |
1105 | u32 reg_val; | |
1106 | ||
7b11488f | 1107 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
b3c2ce13 | 1108 | |
83ed9015 | 1109 | trans_pcie->scd_base_addr = |
1042db2a | 1110 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); |
105183b1 | 1111 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; |
b3c2ce13 | 1112 | /* reset conext data memory */ |
105183b1 | 1113 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
b3c2ce13 | 1114 | a += 4) |
1042db2a | 1115 | iwl_write_targ_mem(trans, a, 0); |
b3c2ce13 | 1116 | /* reset tx status memory */ |
105183b1 | 1117 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
b3c2ce13 | 1118 | a += 4) |
1042db2a | 1119 | iwl_write_targ_mem(trans, a, 0); |
105183b1 | 1120 | for (; a < trans_pcie->scd_base_addr + |
1745e440 WYG |
1121 | SCD_TRANS_TBL_OFFSET_QUEUE( |
1122 | cfg(trans)->base_params->num_of_queues); | |
d6189124 | 1123 | a += 4) |
1042db2a | 1124 | iwl_write_targ_mem(trans, a, 0); |
b3c2ce13 | 1125 | |
1042db2a | 1126 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, |
105183b1 | 1127 | trans_pcie->scd_bc_tbls.dma >> 10); |
b3c2ce13 EG |
1128 | |
1129 | /* Enable DMA channel */ | |
1130 | for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) | |
1042db2a | 1131 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
b3c2ce13 EG |
1132 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
1133 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
1134 | ||
1135 | /* Update FH chicken bits */ | |
1042db2a EG |
1136 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); |
1137 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
b3c2ce13 EG |
1138 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
1139 | ||
1042db2a | 1140 | iwl_write_prph(trans, SCD_QUEUECHAIN_SEL, |
c6f600fc | 1141 | SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)); |
1042db2a | 1142 | iwl_write_prph(trans, SCD_AGGR_SEL, 0); |
b3c2ce13 EG |
1143 | |
1144 | /* initiate the queues */ | |
1745e440 | 1145 | for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) { |
1042db2a EG |
1146 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0); |
1147 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
1148 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + | |
b3c2ce13 | 1149 | SCD_CONTEXT_QUEUE_OFFSET(i), 0); |
1042db2a | 1150 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
b3c2ce13 EG |
1151 | SCD_CONTEXT_QUEUE_OFFSET(i) + |
1152 | sizeof(u32), | |
1153 | ((SCD_WIN_SIZE << | |
1154 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1155 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1156 | ((SCD_FRAME_LIMIT << | |
1157 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1158 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
1159 | } | |
1160 | ||
1042db2a | 1161 | iwl_write_prph(trans, SCD_INTERRUPT_MASK, |
1745e440 | 1162 | IWL_MASK(0, cfg(trans)->base_params->num_of_queues)); |
b3c2ce13 EG |
1163 | |
1164 | /* Activate all Tx DMA/FIFO channels */ | |
6d8f6eeb | 1165 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); |
b3c2ce13 EG |
1166 | |
1167 | /* map queues to FIFOs */ | |
7a10e3e4 | 1168 | if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
b3c2ce13 EG |
1169 | queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo; |
1170 | else | |
1171 | queue_to_fifo = iwlagn_default_queue_to_tx_fifo; | |
1172 | ||
c6f600fc | 1173 | iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0); |
b3c2ce13 EG |
1174 | |
1175 | /* make sure all queue are not stopped */ | |
8ad71bef EG |
1176 | memset(&trans_pcie->queue_stopped[0], 0, |
1177 | sizeof(trans_pcie->queue_stopped)); | |
b3c2ce13 | 1178 | for (i = 0; i < 4; i++) |
8ad71bef | 1179 | atomic_set(&trans_pcie->queue_stop_count[i], 0); |
b3c2ce13 EG |
1180 | |
1181 | /* reset to 0 to enable all the queue first */ | |
8ad71bef | 1182 | trans_pcie->txq_ctx_active_msk = 0; |
b3c2ce13 | 1183 | |
effcea16 | 1184 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) < |
72c04ce0 | 1185 | IWLAGN_FIRST_AMPDU_QUEUE); |
effcea16 | 1186 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) < |
72c04ce0 | 1187 | IWLAGN_FIRST_AMPDU_QUEUE); |
b3c2ce13 | 1188 | |
72c04ce0 | 1189 | for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) { |
b3c2ce13 EG |
1190 | int fifo = queue_to_fifo[i].fifo; |
1191 | int ac = queue_to_fifo[i].ac; | |
1192 | ||
8ad71bef | 1193 | iwl_txq_ctx_activate(trans_pcie, i); |
b3c2ce13 EG |
1194 | |
1195 | if (fifo == IWL_TX_FIFO_UNUSED) | |
1196 | continue; | |
1197 | ||
1198 | if (ac != IWL_AC_UNSET) | |
8ad71bef EG |
1199 | iwl_set_swq_id(&trans_pcie->txq[i], ac, i); |
1200 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i], | |
1201 | fifo, 0); | |
b3c2ce13 EG |
1202 | } |
1203 | ||
7b11488f | 1204 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
b3c2ce13 EG |
1205 | |
1206 | /* Enable L1-Active */ | |
1042db2a | 1207 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, |
b3c2ce13 EG |
1208 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
1209 | } | |
1210 | ||
ed6a3803 EG |
1211 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans) |
1212 | { | |
1213 | iwl_reset_ict(trans); | |
1214 | iwl_tx_start(trans); | |
1215 | } | |
1216 | ||
c170b867 EG |
1217 | /** |
1218 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels | |
1219 | */ | |
6d8f6eeb | 1220 | static int iwl_trans_tx_stop(struct iwl_trans *trans) |
c170b867 | 1221 | { |
c2945f39 | 1222 | int ch, txq_id, ret; |
c170b867 | 1223 | unsigned long flags; |
8ad71bef | 1224 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c170b867 EG |
1225 | |
1226 | /* Turn off all Tx DMA fifos */ | |
7b11488f | 1227 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
c170b867 | 1228 | |
6d8f6eeb | 1229 | iwl_trans_txq_set_sched(trans, 0); |
c170b867 EG |
1230 | |
1231 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
02f6f659 | 1232 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
1042db2a | 1233 | iwl_write_direct32(trans, |
6d8f6eeb | 1234 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
c2945f39 | 1235 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, |
c170b867 | 1236 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
c2945f39 SG |
1237 | 1000); |
1238 | if (ret < 0) | |
6d8f6eeb | 1239 | IWL_ERR(trans, "Failing on timeout while stopping" |
c170b867 | 1240 | " DMA channel %d [0x%08x]", ch, |
1042db2a | 1241 | iwl_read_direct32(trans, |
6d8f6eeb | 1242 | FH_TSSR_TX_STATUS_REG)); |
c170b867 | 1243 | } |
7b11488f | 1244 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
c170b867 | 1245 | |
8ad71bef | 1246 | if (!trans_pcie->txq) { |
6d8f6eeb | 1247 | IWL_WARN(trans, "Stopping tx queues that aren't allocated..."); |
c170b867 EG |
1248 | return 0; |
1249 | } | |
1250 | ||
1251 | /* Unmap DMA from host system and free skb's */ | |
1745e440 WYG |
1252 | for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues; |
1253 | txq_id++) | |
6d8f6eeb | 1254 | iwl_tx_queue_unmap(trans, txq_id); |
c170b867 EG |
1255 | |
1256 | return 0; | |
1257 | } | |
1258 | ||
43e58856 | 1259 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf EG |
1260 | { |
1261 | unsigned long flags; | |
43e58856 | 1262 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ae2c30bf | 1263 | |
43e58856 | 1264 | /* tell the device to stop sending interrupts */ |
7b11488f | 1265 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 1266 | iwl_disable_interrupts(trans); |
7b11488f | 1267 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 1268 | |
ab6cf8e8 | 1269 | /* device going down, Stop using ICT table */ |
6d8f6eeb | 1270 | iwl_disable_ict(trans); |
ab6cf8e8 EG |
1271 | |
1272 | /* | |
1273 | * If a HW restart happens during firmware loading, | |
1274 | * then the firmware loading might call this function | |
1275 | * and later it might be called again due to the | |
1276 | * restart. So don't process again if the device is | |
1277 | * already dead. | |
1278 | */ | |
83626404 | 1279 | if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) { |
6d8f6eeb | 1280 | iwl_trans_tx_stop(trans); |
a5916977 | 1281 | #ifndef CONFIG_IWLWIFI_IDI |
6d8f6eeb | 1282 | iwl_trans_rx_stop(trans); |
a5916977 | 1283 | #endif |
ab6cf8e8 | 1284 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 1285 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
1286 | APMG_CLK_VAL_DMA_CLK_RQT); |
1287 | udelay(5); | |
1288 | } | |
1289 | ||
1290 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1291 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
6d8f6eeb | 1292 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1293 | |
1294 | /* Stop the device, and put it in low power state */ | |
cc56feb2 | 1295 | iwl_apm_stop(trans); |
43e58856 EG |
1296 | |
1297 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1298 | * Clean again the interrupt here | |
1299 | */ | |
7b11488f | 1300 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 1301 | iwl_disable_interrupts(trans); |
7b11488f | 1302 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 EG |
1303 | |
1304 | /* wait to make sure we flush pending tasklet*/ | |
75595536 | 1305 | synchronize_irq(trans_pcie->irq); |
43e58856 EG |
1306 | tasklet_kill(&trans_pcie->irq_tasklet); |
1307 | ||
1ee158d8 JB |
1308 | cancel_work_sync(&trans_pcie->rx_replenish); |
1309 | ||
43e58856 | 1310 | /* stop and reset the on-board processor */ |
1042db2a | 1311 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
ab6cf8e8 EG |
1312 | } |
1313 | ||
2dd4f9f7 JB |
1314 | static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans) |
1315 | { | |
1316 | /* let the ucode operate on its own */ | |
1317 | iwl_write32(trans, CSR_UCODE_DRV_GP1_SET, | |
1318 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
1319 | ||
1320 | iwl_disable_interrupts(trans); | |
1321 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
1322 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1323 | } | |
1324 | ||
e13c0c59 | 1325 | static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
14991a9d | 1326 | struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx, |
34b5321e | 1327 | u8 sta_id, u8 tid) |
47c1b496 | 1328 | { |
e13c0c59 EG |
1329 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1330 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
1331 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
132f98c2 | 1332 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload; |
47c1b496 | 1333 | struct iwl_cmd_meta *out_meta; |
e13c0c59 EG |
1334 | struct iwl_tx_queue *txq; |
1335 | struct iwl_queue *q; | |
47c1b496 EG |
1336 | |
1337 | dma_addr_t phys_addr = 0; | |
1338 | dma_addr_t txcmd_phys; | |
1339 | dma_addr_t scratch_phys; | |
1340 | u16 len, firstlen, secondlen; | |
1341 | u8 wait_write_ptr = 0; | |
e13c0c59 | 1342 | u8 txq_id; |
e13c0c59 EG |
1343 | bool is_agg = false; |
1344 | __le16 fc = hdr->frame_control; | |
47c1b496 | 1345 | u8 hdr_len = ieee80211_hdrlen(fc); |
631b84c5 | 1346 | u16 __maybe_unused wifi_seq; |
47c1b496 | 1347 | |
e13c0c59 EG |
1348 | /* |
1349 | * Send this frame after DTIM -- there's a special queue | |
1350 | * reserved for this for contexts that support AP mode. | |
1351 | */ | |
1352 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { | |
1353 | txq_id = trans_pcie->mcast_queue[ctx]; | |
1354 | ||
1355 | /* | |
1356 | * The microcode will clear the more data | |
1357 | * bit in the last frame it transmits. | |
1358 | */ | |
1359 | hdr->frame_control |= | |
1360 | cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
1361 | } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) | |
1362 | txq_id = IWL_AUX_QUEUE; | |
1363 | else | |
1364 | txq_id = | |
1365 | trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)]; | |
1366 | ||
97756fb1 EG |
1367 | /* aggregation is on for this <sta,tid> */ |
1368 | if (info->flags & IEEE80211_TX_CTL_AMPDU) { | |
1369 | WARN_ON(tid >= IWL_MAX_TID_COUNT); | |
1370 | txq_id = trans_pcie->agg_txq[sta_id][tid]; | |
1371 | is_agg = true; | |
e13c0c59 EG |
1372 | } |
1373 | ||
8ad71bef | 1374 | txq = &trans_pcie->txq[txq_id]; |
e13c0c59 EG |
1375 | q = &txq->q; |
1376 | ||
015c15e1 JB |
1377 | spin_lock(&txq->lock); |
1378 | ||
631b84c5 EG |
1379 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1380 | * sequence number. This is a HW requirements to help the SCD to parse | |
1381 | * the BA. | |
1382 | * Check here that the packets are in the right place on the ring. | |
1383 | */ | |
1384 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1385 | wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); | |
1386 | WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr), | |
1387 | "Q: %d WiFi Seq %d tfdNum %d", | |
1388 | txq_id, wifi_seq, q->write_ptr); | |
1389 | #endif | |
1390 | ||
47c1b496 | 1391 | /* Set up driver data for this TFD */ |
2c452297 | 1392 | txq->skbs[q->write_ptr] = skb; |
dfa2bdba EG |
1393 | txq->cmd[q->write_ptr] = dev_cmd; |
1394 | ||
1395 | dev_cmd->hdr.cmd = REPLY_TX; | |
1396 | dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1397 | INDEX_TO_SEQ(q->write_ptr))); | |
47c1b496 EG |
1398 | |
1399 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1400 | out_meta = &txq->meta[q->write_ptr]; | |
1401 | ||
1402 | /* | |
1403 | * Use the first empty entry in this queue's command buffer array | |
1404 | * to contain the Tx command and MAC header concatenated together | |
1405 | * (payload data will be in another buffer). | |
1406 | * Size of this varies, due to varying MAC header length. | |
1407 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1408 | * of the MAC header (device reads on dword boundaries). | |
1409 | * We'll tell device about this padding later. | |
1410 | */ | |
1411 | len = sizeof(struct iwl_tx_cmd) + | |
1412 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1413 | firstlen = (len + 3) & ~3; | |
1414 | ||
1415 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1416 | if (firstlen != len) | |
1417 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1418 | ||
1419 | /* Physical address of this Tx command's header (not MAC header!), | |
1420 | * within command buffer array. */ | |
1042db2a | 1421 | txcmd_phys = dma_map_single(trans->dev, |
47c1b496 EG |
1422 | &dev_cmd->hdr, firstlen, |
1423 | DMA_BIDIRECTIONAL); | |
1042db2a | 1424 | if (unlikely(dma_mapping_error(trans->dev, txcmd_phys))) |
015c15e1 | 1425 | goto out_err; |
47c1b496 EG |
1426 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
1427 | dma_unmap_len_set(out_meta, len, firstlen); | |
1428 | ||
1429 | if (!ieee80211_has_morefrags(fc)) { | |
1430 | txq->need_update = 1; | |
1431 | } else { | |
1432 | wait_write_ptr = 1; | |
1433 | txq->need_update = 0; | |
1434 | } | |
1435 | ||
1436 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
1437 | * if any (802.11 null frames have no payload). */ | |
1438 | secondlen = skb->len - hdr_len; | |
1439 | if (secondlen > 0) { | |
1042db2a | 1440 | phys_addr = dma_map_single(trans->dev, skb->data + hdr_len, |
47c1b496 | 1441 | secondlen, DMA_TO_DEVICE); |
1042db2a EG |
1442 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
1443 | dma_unmap_single(trans->dev, | |
47c1b496 EG |
1444 | dma_unmap_addr(out_meta, mapping), |
1445 | dma_unmap_len(out_meta, len), | |
1446 | DMA_BIDIRECTIONAL); | |
015c15e1 | 1447 | goto out_err; |
47c1b496 EG |
1448 | } |
1449 | } | |
1450 | ||
1451 | /* Attach buffers to TFD */ | |
e13c0c59 | 1452 | iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1); |
47c1b496 | 1453 | if (secondlen > 0) |
e13c0c59 | 1454 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
47c1b496 EG |
1455 | secondlen, 0); |
1456 | ||
1457 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
1458 | offsetof(struct iwl_tx_cmd, scratch); | |
1459 | ||
1460 | /* take back ownership of DMA buffer to enable update */ | |
1042db2a | 1461 | dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1462 | DMA_BIDIRECTIONAL); |
1463 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1464 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1465 | ||
e13c0c59 | 1466 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
47c1b496 | 1467 | le16_to_cpu(dev_cmd->hdr.sequence)); |
e13c0c59 | 1468 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
47c1b496 EG |
1469 | |
1470 | /* Set up entry for this TFD in Tx byte-count array */ | |
96f1f05a | 1471 | iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); |
47c1b496 | 1472 | |
1042db2a | 1473 | dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1474 | DMA_BIDIRECTIONAL); |
1475 | ||
6c1011e1 | 1476 | trace_iwlwifi_dev_tx(trans->dev, |
47c1b496 EG |
1477 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], |
1478 | sizeof(struct iwl_tfd), | |
1479 | &dev_cmd->hdr, firstlen, | |
1480 | skb->data + hdr_len, secondlen); | |
1481 | ||
1482 | /* Tell device the write index *just past* this latest filled TFD */ | |
1483 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
e13c0c59 EG |
1484 | iwl_txq_update_write_ptr(trans, txq); |
1485 | ||
47c1b496 EG |
1486 | /* |
1487 | * At this point the frame is "transmitted" successfully | |
1488 | * and we will get a TX status notification eventually, | |
1489 | * regardless of the value of ret. "ret" only indicates | |
1490 | * whether or not we should update the write pointer. | |
1491 | */ | |
a0eaad71 | 1492 | if (iwl_queue_space(q) < q->high_mark) { |
47c1b496 EG |
1493 | if (wait_write_ptr) { |
1494 | txq->need_update = 1; | |
e13c0c59 | 1495 | iwl_txq_update_write_ptr(trans, txq); |
47c1b496 | 1496 | } else { |
bada991b | 1497 | iwl_stop_queue(trans, txq); |
47c1b496 EG |
1498 | } |
1499 | } | |
015c15e1 | 1500 | spin_unlock(&txq->lock); |
47c1b496 | 1501 | return 0; |
015c15e1 JB |
1502 | out_err: |
1503 | spin_unlock(&txq->lock); | |
1504 | return -1; | |
47c1b496 EG |
1505 | } |
1506 | ||
57a1dc89 | 1507 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 1508 | { |
5a878bf6 EG |
1509 | struct iwl_trans_pcie *trans_pcie = |
1510 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
e6bb4c9c | 1511 | int err; |
c9eec95c | 1512 | bool hw_rfkill; |
e6bb4c9c | 1513 | |
0c325769 EG |
1514 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1515 | ||
57a1dc89 EG |
1516 | if (!trans_pcie->irq_requested) { |
1517 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
1518 | iwl_irq_tasklet, (unsigned long)trans); | |
e6bb4c9c | 1519 | |
57a1dc89 | 1520 | iwl_alloc_isr_ict(trans); |
e6bb4c9c | 1521 | |
75595536 | 1522 | err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED, |
57a1dc89 EG |
1523 | DRV_NAME, trans); |
1524 | if (err) { | |
1525 | IWL_ERR(trans, "Error allocating IRQ %d\n", | |
75595536 | 1526 | trans_pcie->irq); |
ebb7678d | 1527 | goto error; |
57a1dc89 EG |
1528 | } |
1529 | ||
1530 | INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish); | |
1531 | trans_pcie->irq_requested = true; | |
e6bb4c9c EG |
1532 | } |
1533 | ||
ebb7678d EG |
1534 | err = iwl_prepare_card_hw(trans); |
1535 | if (err) { | |
1536 | IWL_ERR(trans, "Error while preparing HW: %d", err); | |
f057ac4e | 1537 | goto err_free_irq; |
ebb7678d | 1538 | } |
a6c684ee EG |
1539 | |
1540 | iwl_apm_init(trans); | |
1541 | ||
c9eec95c JB |
1542 | hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) & |
1543 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
1544 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
d48e2074 | 1545 | |
ebb7678d EG |
1546 | return err; |
1547 | ||
f057ac4e | 1548 | err_free_irq: |
75595536 | 1549 | free_irq(trans_pcie->irq, trans); |
ebb7678d EG |
1550 | error: |
1551 | iwl_free_isr_ict(trans); | |
1552 | tasklet_kill(&trans_pcie->irq_tasklet); | |
1553 | return err; | |
e6bb4c9c EG |
1554 | } |
1555 | ||
cc56feb2 EG |
1556 | static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans) |
1557 | { | |
1558 | iwl_apm_stop(trans); | |
1559 | ||
1df06bdc EG |
1560 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
1561 | ||
cc56feb2 | 1562 | /* Even if we stop the HW, we still want the RF kill interrupt */ |
8722c899 | 1563 | iwl_enable_rfkill_int(trans); |
cc56feb2 EG |
1564 | } |
1565 | ||
76bc10fc | 1566 | static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid, |
e755f882 | 1567 | int txq_id, int ssn, struct sk_buff_head *skbs) |
464021ff | 1568 | { |
8ad71bef EG |
1569 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1570 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 EG |
1571 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
1572 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
464021ff | 1573 | int freed = 0; |
a0eaad71 | 1574 | |
015c15e1 JB |
1575 | spin_lock(&txq->lock); |
1576 | ||
8ad71bef EG |
1577 | txq->time_stamp = jiffies; |
1578 | ||
76bc10fc | 1579 | if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE && |
3d29dd9b | 1580 | tid != IWL_TID_NON_QOS && |
76bc10fc EG |
1581 | txq_id != trans_pcie->agg_txq[sta_id][tid])) { |
1582 | /* | |
1583 | * FIXME: this is a uCode bug which need to be addressed, | |
1584 | * log the information and return for now. | |
1585 | * Since it is can possibly happen very often and in order | |
1586 | * not to fill the syslog, don't use IWL_ERR or IWL_WARN | |
1587 | */ | |
1588 | IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, " | |
1589 | "agg_txq[sta_id[tid] %d", txq_id, | |
1590 | trans_pcie->agg_txq[sta_id][tid]); | |
015c15e1 | 1591 | spin_unlock(&txq->lock); |
76bc10fc | 1592 | return 1; |
a0eaad71 EG |
1593 | } |
1594 | ||
1595 | if (txq->q.read_ptr != tfd_num) { | |
1daf04b8 EG |
1596 | IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n", |
1597 | txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr, | |
1598 | tfd_num, ssn); | |
464021ff | 1599 | freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs); |
e755f882 | 1600 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
bada991b | 1601 | iwl_wake_queue(trans, txq); |
a0eaad71 | 1602 | } |
015c15e1 JB |
1603 | |
1604 | spin_unlock(&txq->lock); | |
76bc10fc | 1605 | return 0; |
a0eaad71 EG |
1606 | } |
1607 | ||
03905495 EG |
1608 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1609 | { | |
05f5b97e | 1610 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1611 | } |
1612 | ||
1613 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1614 | { | |
05f5b97e | 1615 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1616 | } |
1617 | ||
1618 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1619 | { | |
05f5b97e | 1620 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1621 | } |
1622 | ||
c6f600fc MV |
1623 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
1624 | const struct iwl_trans_config *trans_cfg) | |
1625 | { | |
1626 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1627 | ||
1628 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
1629 | } | |
1630 | ||
6d8f6eeb | 1631 | static void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1632 | { |
a42a1844 EG |
1633 | struct iwl_trans_pcie *trans_pcie = |
1634 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1635 | ||
ae2c30bf | 1636 | iwl_trans_pcie_tx_free(trans); |
a5916977 | 1637 | #ifndef CONFIG_IWLWIFI_IDI |
ae2c30bf | 1638 | iwl_trans_pcie_rx_free(trans); |
a5916977 | 1639 | #endif |
57a1dc89 | 1640 | if (trans_pcie->irq_requested == true) { |
75595536 | 1641 | free_irq(trans_pcie->irq, trans); |
57a1dc89 EG |
1642 | iwl_free_isr_ict(trans); |
1643 | } | |
a42a1844 EG |
1644 | |
1645 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 1646 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
1647 | pci_release_regions(trans_pcie->pci_dev); |
1648 | pci_disable_device(trans_pcie->pci_dev); | |
1649 | ||
6d8f6eeb EG |
1650 | trans->shrd->trans = NULL; |
1651 | kfree(trans); | |
34c1b7ba EG |
1652 | } |
1653 | ||
c01a4047 | 1654 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1655 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
1656 | { | |
57210f7c EG |
1657 | return 0; |
1658 | } | |
1659 | ||
1660 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
1661 | { | |
c9eec95c | 1662 | bool hw_rfkill; |
57210f7c | 1663 | |
c9eec95c JB |
1664 | hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) & |
1665 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
8722c899 SG |
1666 | |
1667 | if (hw_rfkill) | |
1668 | iwl_enable_rfkill_int(trans); | |
1669 | else | |
1670 | iwl_enable_interrupts(trans); | |
1671 | ||
7120d989 | 1672 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
57210f7c EG |
1673 | |
1674 | return 0; | |
1675 | } | |
c01a4047 | 1676 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 1677 | |
5f178cd2 EG |
1678 | #define IWL_FLUSH_WAIT_MS 2000 |
1679 | ||
1680 | static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans) | |
1681 | { | |
8ad71bef | 1682 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5f178cd2 EG |
1683 | struct iwl_tx_queue *txq; |
1684 | struct iwl_queue *q; | |
1685 | int cnt; | |
1686 | unsigned long now = jiffies; | |
1687 | int ret = 0; | |
1688 | ||
1689 | /* waiting for all the tx frames complete might take a while */ | |
1745e440 | 1690 | for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) { |
9ba1947a | 1691 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 1692 | continue; |
8ad71bef | 1693 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
1694 | q = &txq->q; |
1695 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1696 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1697 | msleep(1); | |
1698 | ||
1699 | if (q->read_ptr != q->write_ptr) { | |
1700 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); | |
1701 | ret = -ETIMEDOUT; | |
1702 | break; | |
1703 | } | |
1704 | } | |
1705 | return ret; | |
1706 | } | |
1707 | ||
f22be624 EG |
1708 | /* |
1709 | * On every watchdog tick we check (latest) time stamp. If it does not | |
1710 | * change during timeout period and queue is not empty we reset firmware. | |
1711 | */ | |
1712 | static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt) | |
1713 | { | |
8ad71bef EG |
1714 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1715 | struct iwl_tx_queue *txq = &trans_pcie->txq[cnt]; | |
f22be624 EG |
1716 | struct iwl_queue *q = &txq->q; |
1717 | unsigned long timeout; | |
1718 | ||
1719 | if (q->read_ptr == q->write_ptr) { | |
1720 | txq->time_stamp = jiffies; | |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | timeout = txq->time_stamp + | |
1725 | msecs_to_jiffies(hw_params(trans).wd_timeout); | |
1726 | ||
1727 | if (time_after(jiffies, timeout)) { | |
1728 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id, | |
1729 | hw_params(trans).wd_timeout); | |
08d1700d | 1730 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
05f8a09f | 1731 | q->read_ptr, q->write_ptr); |
08d1700d | 1732 | IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n", |
1042db2a | 1733 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) |
08d1700d | 1734 | & (TFD_QUEUE_SIZE_MAX - 1), |
1042db2a | 1735 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); |
f22be624 EG |
1736 | return 1; |
1737 | } | |
1738 | ||
1739 | return 0; | |
1740 | } | |
1741 | ||
ff620849 EG |
1742 | static const char *get_fh_string(int cmd) |
1743 | { | |
1744 | switch (cmd) { | |
1745 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
1746 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1747 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
1748 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
1749 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
1750 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
1751 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1752 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
1753 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
1754 | default: | |
1755 | return "UNKNOWN"; | |
1756 | } | |
1757 | } | |
1758 | ||
1759 | int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display) | |
1760 | { | |
1761 | int i; | |
1762 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1763 | int pos = 0; | |
1764 | size_t bufsz = 0; | |
1765 | #endif | |
1766 | static const u32 fh_tbl[] = { | |
1767 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
1768 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1769 | FH_RSCSR_CHNL0_WPTR, | |
1770 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
1771 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
1772 | FH_MEM_RSSR_RX_STATUS_REG, | |
1773 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1774 | FH_TSSR_TX_STATUS_REG, | |
1775 | FH_TSSR_TX_ERROR_REG | |
1776 | }; | |
1777 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1778 | if (display) { | |
1779 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1780 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1781 | if (!*buf) | |
1782 | return -ENOMEM; | |
1783 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1784 | "FH register values:\n"); | |
1785 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1786 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1787 | " %34s: 0X%08x\n", | |
1788 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1789 | iwl_read_direct32(trans, fh_tbl[i])); |
ff620849 EG |
1790 | } |
1791 | return pos; | |
1792 | } | |
1793 | #endif | |
1794 | IWL_ERR(trans, "FH register values:\n"); | |
1795 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1796 | IWL_ERR(trans, " %34s: 0X%08x\n", | |
1797 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1798 | iwl_read_direct32(trans, fh_tbl[i])); |
ff620849 EG |
1799 | } |
1800 | return 0; | |
1801 | } | |
1802 | ||
1803 | static const char *get_csr_string(int cmd) | |
1804 | { | |
1805 | switch (cmd) { | |
1806 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1807 | IWL_CMD(CSR_INT_COALESCING); | |
1808 | IWL_CMD(CSR_INT); | |
1809 | IWL_CMD(CSR_INT_MASK); | |
1810 | IWL_CMD(CSR_FH_INT_STATUS); | |
1811 | IWL_CMD(CSR_GPIO_IN); | |
1812 | IWL_CMD(CSR_RESET); | |
1813 | IWL_CMD(CSR_GP_CNTRL); | |
1814 | IWL_CMD(CSR_HW_REV); | |
1815 | IWL_CMD(CSR_EEPROM_REG); | |
1816 | IWL_CMD(CSR_EEPROM_GP); | |
1817 | IWL_CMD(CSR_OTP_GP_REG); | |
1818 | IWL_CMD(CSR_GIO_REG); | |
1819 | IWL_CMD(CSR_GP_UCODE_REG); | |
1820 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1821 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1822 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1823 | IWL_CMD(CSR_LED_REG); | |
1824 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1825 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1826 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1827 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1828 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1829 | default: | |
1830 | return "UNKNOWN"; | |
1831 | } | |
1832 | } | |
1833 | ||
1834 | void iwl_dump_csr(struct iwl_trans *trans) | |
1835 | { | |
1836 | int i; | |
1837 | static const u32 csr_tbl[] = { | |
1838 | CSR_HW_IF_CONFIG_REG, | |
1839 | CSR_INT_COALESCING, | |
1840 | CSR_INT, | |
1841 | CSR_INT_MASK, | |
1842 | CSR_FH_INT_STATUS, | |
1843 | CSR_GPIO_IN, | |
1844 | CSR_RESET, | |
1845 | CSR_GP_CNTRL, | |
1846 | CSR_HW_REV, | |
1847 | CSR_EEPROM_REG, | |
1848 | CSR_EEPROM_GP, | |
1849 | CSR_OTP_GP_REG, | |
1850 | CSR_GIO_REG, | |
1851 | CSR_GP_UCODE_REG, | |
1852 | CSR_GP_DRIVER_REG, | |
1853 | CSR_UCODE_DRV_GP1, | |
1854 | CSR_UCODE_DRV_GP2, | |
1855 | CSR_LED_REG, | |
1856 | CSR_DRAM_INT_TBL_REG, | |
1857 | CSR_GIO_CHICKEN_BITS, | |
1858 | CSR_ANA_PLL_CFG, | |
1859 | CSR_HW_REV_WA_REG, | |
1860 | CSR_DBG_HPET_MEM_REG | |
1861 | }; | |
1862 | IWL_ERR(trans, "CSR values:\n"); | |
1863 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1864 | "CSR_INT_PERIODIC_REG)\n"); | |
1865 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1866 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1867 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1868 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1869 | } |
1870 | } | |
1871 | ||
87e5666c EG |
1872 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1873 | /* create and remove of files */ | |
1874 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1875 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c EG |
1876 | &iwl_dbgfs_##name##_ops)) \ |
1877 | return -ENOMEM; \ | |
1878 | } while (0) | |
1879 | ||
1880 | /* file operation */ | |
1881 | #define DEBUGFS_READ_FUNC(name) \ | |
1882 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1883 | char __user *user_buf, \ | |
1884 | size_t count, loff_t *ppos); | |
1885 | ||
1886 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1887 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1888 | const char __user *user_buf, \ | |
1889 | size_t count, loff_t *ppos); | |
1890 | ||
1891 | ||
1892 | static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file) | |
1893 | { | |
1894 | file->private_data = inode->i_private; | |
1895 | return 0; | |
1896 | } | |
1897 | ||
1898 | #define DEBUGFS_READ_FILE_OPS(name) \ | |
1899 | DEBUGFS_READ_FUNC(name); \ | |
1900 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1901 | .read = iwl_dbgfs_##name##_read, \ | |
1902 | .open = iwl_dbgfs_open_file_generic, \ | |
1903 | .llseek = generic_file_llseek, \ | |
1904 | }; | |
1905 | ||
16db88ba EG |
1906 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1907 | DEBUGFS_WRITE_FUNC(name); \ | |
1908 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1909 | .write = iwl_dbgfs_##name##_write, \ | |
1910 | .open = iwl_dbgfs_open_file_generic, \ | |
1911 | .llseek = generic_file_llseek, \ | |
1912 | }; | |
1913 | ||
87e5666c EG |
1914 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1915 | DEBUGFS_READ_FUNC(name); \ | |
1916 | DEBUGFS_WRITE_FUNC(name); \ | |
1917 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1918 | .write = iwl_dbgfs_##name##_write, \ | |
1919 | .read = iwl_dbgfs_##name##_read, \ | |
1920 | .open = iwl_dbgfs_open_file_generic, \ | |
1921 | .llseek = generic_file_llseek, \ | |
1922 | }; | |
1923 | ||
87e5666c EG |
1924 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
1925 | char __user *user_buf, | |
8ad71bef EG |
1926 | size_t count, loff_t *ppos) |
1927 | { | |
5a878bf6 | 1928 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1929 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
87e5666c EG |
1930 | struct iwl_tx_queue *txq; |
1931 | struct iwl_queue *q; | |
1932 | char *buf; | |
1933 | int pos = 0; | |
1934 | int cnt; | |
1935 | int ret; | |
1745e440 WYG |
1936 | size_t bufsz; |
1937 | ||
1938 | bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues; | |
87e5666c | 1939 | |
8ad71bef | 1940 | if (!trans_pcie->txq) { |
3e10caeb | 1941 | IWL_ERR(trans, "txq not ready\n"); |
87e5666c EG |
1942 | return -EAGAIN; |
1943 | } | |
1944 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1945 | if (!buf) | |
1946 | return -ENOMEM; | |
1947 | ||
1745e440 | 1948 | for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) { |
8ad71bef | 1949 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1950 | q = &txq->q; |
1951 | pos += scnprintf(buf + pos, bufsz - pos, | |
1952 | "hwq %.2d: read=%u write=%u stop=%d" | |
1953 | " swq_id=%#.2x (ac %d/hwq %d)\n", | |
1954 | cnt, q->read_ptr, q->write_ptr, | |
8ad71bef | 1955 | !!test_bit(cnt, trans_pcie->queue_stopped), |
87e5666c EG |
1956 | txq->swq_id, txq->swq_id & 3, |
1957 | (txq->swq_id >> 2) & 0x1f); | |
1958 | if (cnt >= 4) | |
1959 | continue; | |
1960 | /* for the ACs, display the stop count too */ | |
1961 | pos += scnprintf(buf + pos, bufsz - pos, | |
8ad71bef EG |
1962 | " stop-count: %d\n", |
1963 | atomic_read(&trans_pcie->queue_stop_count[cnt])); | |
87e5666c EG |
1964 | } |
1965 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1966 | kfree(buf); | |
1967 | return ret; | |
1968 | } | |
1969 | ||
1970 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
1971 | char __user *user_buf, | |
1972 | size_t count, loff_t *ppos) { | |
5a878bf6 EG |
1973 | struct iwl_trans *trans = file->private_data; |
1974 | struct iwl_trans_pcie *trans_pcie = | |
1975 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1976 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
87e5666c EG |
1977 | char buf[256]; |
1978 | int pos = 0; | |
1979 | const size_t bufsz = sizeof(buf); | |
1980 | ||
1981 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1982 | rxq->read); | |
1983 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1984 | rxq->write); | |
1985 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1986 | rxq->free_count); | |
1987 | if (rxq->rb_stts) { | |
1988 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1989 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1990 | } else { | |
1991 | pos += scnprintf(buf + pos, bufsz - pos, | |
1992 | "closed_rb_num: Not Allocated\n"); | |
1993 | } | |
1994 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1995 | } | |
1996 | ||
7ff94706 EG |
1997 | static ssize_t iwl_dbgfs_log_event_read(struct file *file, |
1998 | char __user *user_buf, | |
1999 | size_t count, loff_t *ppos) | |
2000 | { | |
2001 | struct iwl_trans *trans = file->private_data; | |
2002 | char *buf; | |
2003 | int pos = 0; | |
2004 | ssize_t ret = -ENOMEM; | |
2005 | ||
6bb78847 | 2006 | ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true); |
7ff94706 EG |
2007 | if (buf) { |
2008 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2009 | kfree(buf); | |
2010 | } | |
2011 | return ret; | |
2012 | } | |
2013 | ||
2014 | static ssize_t iwl_dbgfs_log_event_write(struct file *file, | |
2015 | const char __user *user_buf, | |
2016 | size_t count, loff_t *ppos) | |
2017 | { | |
2018 | struct iwl_trans *trans = file->private_data; | |
2019 | u32 event_log_flag; | |
2020 | char buf[8]; | |
2021 | int buf_size; | |
2022 | ||
2023 | memset(buf, 0, sizeof(buf)); | |
2024 | buf_size = min(count, sizeof(buf) - 1); | |
2025 | if (copy_from_user(buf, user_buf, buf_size)) | |
2026 | return -EFAULT; | |
2027 | if (sscanf(buf, "%d", &event_log_flag) != 1) | |
2028 | return -EFAULT; | |
2029 | if (event_log_flag == 1) | |
6bb78847 | 2030 | iwl_dump_nic_event_log(trans, true, NULL, false); |
7ff94706 EG |
2031 | |
2032 | return count; | |
2033 | } | |
2034 | ||
1f7b6172 EG |
2035 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
2036 | char __user *user_buf, | |
2037 | size_t count, loff_t *ppos) { | |
2038 | ||
2039 | struct iwl_trans *trans = file->private_data; | |
2040 | struct iwl_trans_pcie *trans_pcie = | |
2041 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
2042 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
2043 | ||
2044 | int pos = 0; | |
2045 | char *buf; | |
2046 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
2047 | ssize_t ret; | |
2048 | ||
2049 | buf = kzalloc(bufsz, GFP_KERNEL); | |
2050 | if (!buf) { | |
2051 | IWL_ERR(trans, "Can not allocate Buffer\n"); | |
2052 | return -ENOMEM; | |
2053 | } | |
2054 | ||
2055 | pos += scnprintf(buf + pos, bufsz - pos, | |
2056 | "Interrupt Statistics Report:\n"); | |
2057 | ||
2058 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
2059 | isr_stats->hw); | |
2060 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
2061 | isr_stats->sw); | |
2062 | if (isr_stats->sw || isr_stats->hw) { | |
2063 | pos += scnprintf(buf + pos, bufsz - pos, | |
2064 | "\tLast Restarting Code: 0x%X\n", | |
2065 | isr_stats->err_code); | |
2066 | } | |
2067 | #ifdef CONFIG_IWLWIFI_DEBUG | |
2068 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
2069 | isr_stats->sch); | |
2070 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
2071 | isr_stats->alive); | |
2072 | #endif | |
2073 | pos += scnprintf(buf + pos, bufsz - pos, | |
2074 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
2075 | ||
2076 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
2077 | isr_stats->ctkill); | |
2078 | ||
2079 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
2080 | isr_stats->wakeup); | |
2081 | ||
2082 | pos += scnprintf(buf + pos, bufsz - pos, | |
2083 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
2084 | ||
2085 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
2086 | isr_stats->tx); | |
2087 | ||
2088 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
2089 | isr_stats->unhandled); | |
2090 | ||
2091 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
2092 | kfree(buf); | |
2093 | return ret; | |
2094 | } | |
2095 | ||
2096 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
2097 | const char __user *user_buf, | |
2098 | size_t count, loff_t *ppos) | |
2099 | { | |
2100 | struct iwl_trans *trans = file->private_data; | |
2101 | struct iwl_trans_pcie *trans_pcie = | |
2102 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
2103 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
2104 | ||
2105 | char buf[8]; | |
2106 | int buf_size; | |
2107 | u32 reset_flag; | |
2108 | ||
2109 | memset(buf, 0, sizeof(buf)); | |
2110 | buf_size = min(count, sizeof(buf) - 1); | |
2111 | if (copy_from_user(buf, user_buf, buf_size)) | |
2112 | return -EFAULT; | |
2113 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
2114 | return -EFAULT; | |
2115 | if (reset_flag == 0) | |
2116 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
2117 | ||
2118 | return count; | |
2119 | } | |
2120 | ||
16db88ba EG |
2121 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
2122 | const char __user *user_buf, | |
2123 | size_t count, loff_t *ppos) | |
2124 | { | |
2125 | struct iwl_trans *trans = file->private_data; | |
2126 | char buf[8]; | |
2127 | int buf_size; | |
2128 | int csr; | |
2129 | ||
2130 | memset(buf, 0, sizeof(buf)); | |
2131 | buf_size = min(count, sizeof(buf) - 1); | |
2132 | if (copy_from_user(buf, user_buf, buf_size)) | |
2133 | return -EFAULT; | |
2134 | if (sscanf(buf, "%d", &csr) != 1) | |
2135 | return -EFAULT; | |
2136 | ||
2137 | iwl_dump_csr(trans); | |
2138 | ||
2139 | return count; | |
2140 | } | |
2141 | ||
16db88ba EG |
2142 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
2143 | char __user *user_buf, | |
2144 | size_t count, loff_t *ppos) | |
2145 | { | |
2146 | struct iwl_trans *trans = file->private_data; | |
2147 | char *buf; | |
2148 | int pos = 0; | |
2149 | ssize_t ret = -EFAULT; | |
2150 | ||
2151 | ret = pos = iwl_dump_fh(trans, &buf, true); | |
2152 | if (buf) { | |
2153 | ret = simple_read_from_buffer(user_buf, | |
2154 | count, ppos, buf, pos); | |
2155 | kfree(buf); | |
2156 | } | |
2157 | ||
2158 | return ret; | |
2159 | } | |
2160 | ||
7ff94706 | 2161 | DEBUGFS_READ_WRITE_FILE_OPS(log_event); |
1f7b6172 | 2162 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 2163 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
2164 | DEBUGFS_READ_FILE_OPS(rx_queue); |
2165 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 2166 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c EG |
2167 | |
2168 | /* | |
2169 | * Create the debugfs files and directories | |
2170 | * | |
2171 | */ | |
2172 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
2173 | struct dentry *dir) | |
2174 | { | |
87e5666c EG |
2175 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
2176 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
7ff94706 | 2177 | DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR); |
1f7b6172 | 2178 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
2179 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
2180 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c EG |
2181 | return 0; |
2182 | } | |
2183 | #else | |
2184 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
2185 | struct dentry *dir) | |
2186 | { return 0; } | |
2187 | ||
2188 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ | |
2189 | ||
e6bb4c9c | 2190 | const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 2191 | .start_hw = iwl_trans_pcie_start_hw, |
cc56feb2 | 2192 | .stop_hw = iwl_trans_pcie_stop_hw, |
ed6a3803 | 2193 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 2194 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 2195 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 2196 | |
2dd4f9f7 JB |
2197 | .wowlan_suspend = iwl_trans_pcie_wowlan_suspend, |
2198 | ||
e6bb4c9c | 2199 | .send_cmd = iwl_trans_pcie_send_cmd, |
c85eb619 | 2200 | |
e6bb4c9c | 2201 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 2202 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 2203 | |
7f01d567 | 2204 | .tx_agg_disable = iwl_trans_pcie_tx_agg_disable, |
288712a6 | 2205 | .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc, |
c91bd124 | 2206 | .tx_agg_setup = iwl_trans_pcie_tx_agg_setup, |
34c1b7ba | 2207 | |
e6bb4c9c | 2208 | .free = iwl_trans_pcie_free, |
87e5666c EG |
2209 | |
2210 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, | |
5f178cd2 EG |
2211 | |
2212 | .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty, | |
f22be624 | 2213 | .check_stuck_queue = iwl_trans_pcie_check_stuck_queue, |
5f178cd2 | 2214 | |
c01a4047 | 2215 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
2216 | .suspend = iwl_trans_pcie_suspend, |
2217 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 2218 | #endif |
03905495 EG |
2219 | .write8 = iwl_trans_pcie_write8, |
2220 | .write32 = iwl_trans_pcie_write32, | |
2221 | .read32 = iwl_trans_pcie_read32, | |
c6f600fc | 2222 | .configure = iwl_trans_pcie_configure, |
e6bb4c9c | 2223 | }; |
a42a1844 | 2224 | |
a42a1844 EG |
2225 | struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd, |
2226 | struct pci_dev *pdev, | |
2227 | const struct pci_device_id *ent) | |
2228 | { | |
a42a1844 EG |
2229 | struct iwl_trans_pcie *trans_pcie; |
2230 | struct iwl_trans *trans; | |
2231 | u16 pci_cmd; | |
2232 | int err; | |
2233 | ||
2234 | trans = kzalloc(sizeof(struct iwl_trans) + | |
2235 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); | |
2236 | ||
2237 | if (WARN_ON(!trans)) | |
2238 | return NULL; | |
2239 | ||
2240 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2241 | ||
2242 | trans->ops = &trans_ops_pcie; | |
2243 | trans->shrd = shrd; | |
2244 | trans_pcie->trans = trans; | |
7b11488f | 2245 | spin_lock_init(&trans_pcie->irq_lock); |
13df1aab | 2246 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 EG |
2247 | |
2248 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
2249 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
2250 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
2251 | PCIE_LINK_STATE_CLKPM); | |
2252 | ||
2253 | if (pci_enable_device(pdev)) { | |
2254 | err = -ENODEV; | |
2255 | goto out_no_pci; | |
2256 | } | |
2257 | ||
2258 | pci_set_master(pdev); | |
2259 | ||
2260 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2261 | if (!err) | |
2262 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2263 | if (err) { | |
2264 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2265 | if (!err) | |
2266 | err = pci_set_consistent_dma_mask(pdev, | |
2267 | DMA_BIT_MASK(32)); | |
2268 | /* both attempts failed: */ | |
2269 | if (err) { | |
2270 | dev_printk(KERN_ERR, &pdev->dev, | |
2271 | "No suitable DMA available.\n"); | |
2272 | goto out_pci_disable_device; | |
2273 | } | |
2274 | } | |
2275 | ||
2276 | err = pci_request_regions(pdev, DRV_NAME); | |
2277 | if (err) { | |
2278 | dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed"); | |
2279 | goto out_pci_disable_device; | |
2280 | } | |
2281 | ||
05f5b97e | 2282 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 2283 | if (!trans_pcie->hw_base) { |
05f5b97e | 2284 | dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed"); |
a42a1844 EG |
2285 | err = -ENODEV; |
2286 | goto out_pci_release_regions; | |
2287 | } | |
2288 | ||
a42a1844 EG |
2289 | dev_printk(KERN_INFO, &pdev->dev, |
2290 | "pci_resource_len = 0x%08llx\n", | |
2291 | (unsigned long long) pci_resource_len(pdev, 0)); | |
2292 | dev_printk(KERN_INFO, &pdev->dev, | |
2293 | "pci_resource_base = %p\n", trans_pcie->hw_base); | |
2294 | ||
2295 | dev_printk(KERN_INFO, &pdev->dev, | |
2296 | "HW Revision ID = 0x%X\n", pdev->revision); | |
2297 | ||
2298 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
2299 | * PCI Tx retries from interfering with C3 CPU state */ | |
2300 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2301 | ||
2302 | err = pci_enable_msi(pdev); | |
2303 | if (err) | |
2304 | dev_printk(KERN_ERR, &pdev->dev, | |
2305 | "pci_enable_msi failed(0X%x)", err); | |
2306 | ||
2307 | trans->dev = &pdev->dev; | |
75595536 | 2308 | trans_pcie->irq = pdev->irq; |
a42a1844 | 2309 | trans_pcie->pci_dev = pdev; |
08079a49 | 2310 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 2311 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
2312 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
2313 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 EG |
2314 | |
2315 | /* TODO: Move this away, not needed if not MSI */ | |
2316 | /* enable rfkill interrupt: hw bug w/a */ | |
2317 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
2318 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2319 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2320 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
2321 | } | |
2322 | ||
2323 | return trans; | |
2324 | ||
2325 | out_pci_release_regions: | |
2326 | pci_release_regions(pdev); | |
2327 | out_pci_disable_device: | |
2328 | pci_disable_device(pdev); | |
2329 | out_no_pci: | |
2330 | kfree(trans); | |
2331 | return NULL; | |
2332 | } | |
2333 |