]>
Commit | Line | Data |
---|---|---|
c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
4e318262 | 8 | * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
4e318262 | 33 | * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
e6bb4c9c | 63 | #include <linux/interrupt.h> |
87e5666c | 64 | #include <linux/debugfs.h> |
6d8f6eeb EG |
65 | #include <linux/bitops.h> |
66 | #include <linux/gfp.h> | |
e6bb4c9c | 67 | |
c85eb619 | 68 | #include "iwl-trans.h" |
c17d0681 | 69 | #include "iwl-trans-pcie-int.h" |
522376d2 EG |
70 | #include "iwl-csr.h" |
71 | #include "iwl-prph.h" | |
48f20d35 | 72 | #include "iwl-shared.h" |
522376d2 | 73 | #include "iwl-eeprom.h" |
7a10e3e4 | 74 | #include "iwl-agn-hw.h" |
c85eb619 | 75 | |
5a878bf6 | 76 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
c85eb619 | 77 | { |
5a878bf6 EG |
78 | struct iwl_trans_pcie *trans_pcie = |
79 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
80 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
81 | struct device *dev = bus(trans)->dev; | |
c85eb619 | 82 | |
5a878bf6 | 83 | memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); |
c85eb619 EG |
84 | |
85 | spin_lock_init(&rxq->lock); | |
c85eb619 EG |
86 | |
87 | if (WARN_ON(rxq->bd || rxq->rb_stts)) | |
88 | return -EINVAL; | |
89 | ||
90 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ | |
84c816da DH |
91 | rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
92 | &rxq->bd_dma, GFP_KERNEL); | |
c85eb619 EG |
93 | if (!rxq->bd) |
94 | goto err_bd; | |
c85eb619 EG |
95 | |
96 | /*Allocate the driver's pointer to receive buffer status */ | |
84c816da DH |
97 | rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), |
98 | &rxq->rb_stts_dma, GFP_KERNEL); | |
c85eb619 EG |
99 | if (!rxq->rb_stts) |
100 | goto err_rb_stts; | |
c85eb619 EG |
101 | |
102 | return 0; | |
103 | ||
104 | err_rb_stts: | |
a0f6b0a2 EG |
105 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
106 | rxq->bd, rxq->bd_dma); | |
c85eb619 EG |
107 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
108 | rxq->bd = NULL; | |
109 | err_bd: | |
110 | return -ENOMEM; | |
111 | } | |
112 | ||
5a878bf6 | 113 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans) |
c85eb619 | 114 | { |
5a878bf6 EG |
115 | struct iwl_trans_pcie *trans_pcie = |
116 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
117 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
a0f6b0a2 | 118 | int i; |
c85eb619 EG |
119 | |
120 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
121 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
122 | /* In the reset function, these buffers may have been allocated | |
123 | * to an SKB, so we need to unmap and free potential storage */ | |
124 | if (rxq->pool[i].page != NULL) { | |
5a878bf6 EG |
125 | dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma, |
126 | PAGE_SIZE << hw_params(trans).rx_page_order, | |
c85eb619 | 127 | DMA_FROM_DEVICE); |
790428b6 EG |
128 | __free_pages(rxq->pool[i].page, |
129 | hw_params(trans).rx_page_order); | |
c85eb619 EG |
130 | rxq->pool[i].page = NULL; |
131 | } | |
132 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
133 | } | |
a0f6b0a2 EG |
134 | } |
135 | ||
fd656935 | 136 | static void iwl_trans_rx_hw_init(struct iwl_trans *trans, |
ab697a9f EG |
137 | struct iwl_rx_queue *rxq) |
138 | { | |
139 | u32 rb_size; | |
140 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
c17d0681 | 141 | u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
ab697a9f EG |
142 | |
143 | if (iwlagn_mod_params.amsdu_size_8K) | |
144 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
145 | else | |
146 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
147 | ||
148 | /* Stop Rx DMA */ | |
83ed9015 | 149 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
ab697a9f EG |
150 | |
151 | /* Reset driver's Rx queue write index */ | |
83ed9015 | 152 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
ab697a9f EG |
153 | |
154 | /* Tell device where to find RBD circular buffer in DRAM */ | |
83ed9015 | 155 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
ab697a9f EG |
156 | (u32)(rxq->bd_dma >> 8)); |
157 | ||
158 | /* Tell device where in DRAM to update its Rx status */ | |
83ed9015 | 159 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG, |
ab697a9f EG |
160 | rxq->rb_stts_dma >> 4); |
161 | ||
162 | /* Enable Rx DMA | |
163 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in | |
164 | * the credit mechanism in 5000 HW RX FIFO | |
165 | * Direct rx interrupts to hosts | |
166 | * Rx buffer size 4 or 8k | |
167 | * RB timeout 0x10 | |
168 | * 256 RBDs | |
169 | */ | |
83ed9015 | 170 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, |
ab697a9f EG |
171 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
172 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | | |
173 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
174 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | | |
175 | rb_size| | |
176 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
177 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
178 | ||
179 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
83ed9015 | 180 | iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); |
ab697a9f EG |
181 | } |
182 | ||
5a878bf6 | 183 | static int iwl_rx_init(struct iwl_trans *trans) |
a0f6b0a2 | 184 | { |
5a878bf6 EG |
185 | struct iwl_trans_pcie *trans_pcie = |
186 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
187 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
188 | ||
a0f6b0a2 EG |
189 | int i, err; |
190 | unsigned long flags; | |
191 | ||
192 | if (!rxq->bd) { | |
5a878bf6 | 193 | err = iwl_trans_rx_alloc(trans); |
a0f6b0a2 EG |
194 | if (err) |
195 | return err; | |
196 | } | |
197 | ||
198 | spin_lock_irqsave(&rxq->lock, flags); | |
199 | INIT_LIST_HEAD(&rxq->rx_free); | |
200 | INIT_LIST_HEAD(&rxq->rx_used); | |
201 | ||
5a878bf6 | 202 | iwl_trans_rxq_free_rx_bufs(trans); |
c85eb619 EG |
203 | |
204 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
205 | rxq->queue[i] = NULL; | |
206 | ||
207 | /* Set us so that we have processed and used all buffers, but have | |
208 | * not restocked the Rx queue with fresh buffers */ | |
209 | rxq->read = rxq->write = 0; | |
210 | rxq->write_actual = 0; | |
211 | rxq->free_count = 0; | |
212 | spin_unlock_irqrestore(&rxq->lock, flags); | |
213 | ||
5a878bf6 | 214 | iwlagn_rx_replenish(trans); |
ab697a9f | 215 | |
fd656935 | 216 | iwl_trans_rx_hw_init(trans, rxq); |
ab697a9f | 217 | |
5a878bf6 | 218 | spin_lock_irqsave(&trans->shrd->lock, flags); |
ab697a9f | 219 | rxq->need_update = 1; |
5a878bf6 EG |
220 | iwl_rx_queue_update_write_ptr(trans, rxq); |
221 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
ab697a9f | 222 | |
c85eb619 EG |
223 | return 0; |
224 | } | |
225 | ||
5a878bf6 | 226 | static void iwl_trans_pcie_rx_free(struct iwl_trans *trans) |
a0f6b0a2 | 227 | { |
5a878bf6 EG |
228 | struct iwl_trans_pcie *trans_pcie = |
229 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
230 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
231 | ||
a0f6b0a2 EG |
232 | unsigned long flags; |
233 | ||
234 | /*if rxq->bd is NULL, it means that nothing has been allocated, | |
235 | * exit now */ | |
236 | if (!rxq->bd) { | |
5a878bf6 | 237 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
a0f6b0a2 EG |
238 | return; |
239 | } | |
240 | ||
241 | spin_lock_irqsave(&rxq->lock, flags); | |
5a878bf6 | 242 | iwl_trans_rxq_free_rx_bufs(trans); |
a0f6b0a2 EG |
243 | spin_unlock_irqrestore(&rxq->lock, flags); |
244 | ||
5a878bf6 | 245 | dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE, |
a0f6b0a2 EG |
246 | rxq->bd, rxq->bd_dma); |
247 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); | |
248 | rxq->bd = NULL; | |
249 | ||
250 | if (rxq->rb_stts) | |
5a878bf6 | 251 | dma_free_coherent(bus(trans)->dev, |
a0f6b0a2 EG |
252 | sizeof(struct iwl_rb_status), |
253 | rxq->rb_stts, rxq->rb_stts_dma); | |
254 | else | |
5a878bf6 | 255 | IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n"); |
a0f6b0a2 EG |
256 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); |
257 | rxq->rb_stts = NULL; | |
258 | } | |
259 | ||
6d8f6eeb | 260 | static int iwl_trans_rx_stop(struct iwl_trans *trans) |
c2c52e8b EG |
261 | { |
262 | ||
263 | /* stop Rx DMA */ | |
83ed9015 EG |
264 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
265 | return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG, | |
c2c52e8b EG |
266 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
267 | } | |
268 | ||
6d8f6eeb | 269 | static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans, |
02aca585 EG |
270 | struct iwl_dma_ptr *ptr, size_t size) |
271 | { | |
272 | if (WARN_ON(ptr->addr)) | |
273 | return -EINVAL; | |
274 | ||
6d8f6eeb | 275 | ptr->addr = dma_alloc_coherent(bus(trans)->dev, size, |
02aca585 EG |
276 | &ptr->dma, GFP_KERNEL); |
277 | if (!ptr->addr) | |
278 | return -ENOMEM; | |
279 | ptr->size = size; | |
280 | return 0; | |
281 | } | |
282 | ||
6d8f6eeb | 283 | static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans, |
1359ca4f EG |
284 | struct iwl_dma_ptr *ptr) |
285 | { | |
286 | if (unlikely(!ptr->addr)) | |
287 | return; | |
288 | ||
6d8f6eeb | 289 | dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma); |
1359ca4f EG |
290 | memset(ptr, 0, sizeof(*ptr)); |
291 | } | |
292 | ||
6d8f6eeb EG |
293 | static int iwl_trans_txq_alloc(struct iwl_trans *trans, |
294 | struct iwl_tx_queue *txq, int slots_num, | |
295 | u32 txq_id) | |
02aca585 | 296 | { |
ab9e212e | 297 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; |
02aca585 EG |
298 | int i; |
299 | ||
2c452297 | 300 | if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds)) |
02aca585 EG |
301 | return -EINVAL; |
302 | ||
1359ca4f EG |
303 | txq->q.n_window = slots_num; |
304 | ||
7f90dce1 EG |
305 | txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL); |
306 | txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL); | |
02aca585 EG |
307 | |
308 | if (!txq->meta || !txq->cmd) | |
309 | goto error; | |
310 | ||
dfa2bdba EG |
311 | if (txq_id == trans->shrd->cmd_queue) |
312 | for (i = 0; i < slots_num; i++) { | |
313 | txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd), | |
314 | GFP_KERNEL); | |
315 | if (!txq->cmd[i]) | |
316 | goto error; | |
317 | } | |
02aca585 EG |
318 | |
319 | /* Alloc driver data array and TFD circular buffer */ | |
320 | /* Driver private data, only for Tx (not command) queues, | |
321 | * not shared with device. */ | |
6d8f6eeb | 322 | if (txq_id != trans->shrd->cmd_queue) { |
7f90dce1 EG |
323 | txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]), |
324 | GFP_KERNEL); | |
2c452297 | 325 | if (!txq->skbs) { |
6d8f6eeb | 326 | IWL_ERR(trans, "kmalloc for auxiliary BD " |
02aca585 EG |
327 | "structures failed\n"); |
328 | goto error; | |
329 | } | |
330 | } else { | |
2c452297 | 331 | txq->skbs = NULL; |
02aca585 EG |
332 | } |
333 | ||
334 | /* Circular buffer of transmit frame descriptors (TFDs), | |
335 | * shared with device */ | |
6d8f6eeb EG |
336 | txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz, |
337 | &txq->q.dma_addr, GFP_KERNEL); | |
02aca585 | 338 | if (!txq->tfds) { |
6d8f6eeb | 339 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); |
02aca585 EG |
340 | goto error; |
341 | } | |
342 | txq->q.id = txq_id; | |
343 | ||
344 | return 0; | |
345 | error: | |
2c452297 EG |
346 | kfree(txq->skbs); |
347 | txq->skbs = NULL; | |
02aca585 EG |
348 | /* since txq->cmd has been zeroed, |
349 | * all non allocated cmd[i] will be NULL */ | |
dfa2bdba | 350 | if (txq->cmd && txq_id == trans->shrd->cmd_queue) |
02aca585 EG |
351 | for (i = 0; i < slots_num; i++) |
352 | kfree(txq->cmd[i]); | |
353 | kfree(txq->meta); | |
354 | kfree(txq->cmd); | |
355 | txq->meta = NULL; | |
356 | txq->cmd = NULL; | |
357 | ||
358 | return -ENOMEM; | |
359 | ||
360 | } | |
361 | ||
6d8f6eeb | 362 | static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
02aca585 EG |
363 | int slots_num, u32 txq_id) |
364 | { | |
365 | int ret; | |
366 | ||
367 | txq->need_update = 0; | |
368 | memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num); | |
369 | ||
370 | /* | |
371 | * For the default queues 0-3, set up the swq_id | |
372 | * already -- all others need to get one later | |
373 | * (if they need one at all). | |
374 | */ | |
375 | if (txq_id < 4) | |
376 | iwl_set_swq_id(txq, txq_id, txq_id); | |
377 | ||
378 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
379 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
380 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
381 | ||
382 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
6d8f6eeb | 383 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, |
02aca585 EG |
384 | txq_id); |
385 | if (ret) | |
386 | return ret; | |
387 | ||
388 | /* | |
389 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
390 | * given Tx queue, and enable the DMA channel used for that queue. | |
391 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
83ed9015 | 392 | iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id), |
02aca585 EG |
393 | txq->q.dma_addr >> 8); |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
c170b867 EG |
398 | /** |
399 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
400 | */ | |
6d8f6eeb | 401 | static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id) |
c170b867 | 402 | { |
8ad71bef EG |
403 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
404 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
c170b867 | 405 | struct iwl_queue *q = &txq->q; |
39644e9a | 406 | enum dma_data_direction dma_dir; |
984ecb92 | 407 | unsigned long flags; |
cda4ee3f | 408 | spinlock_t *lock; |
c170b867 EG |
409 | |
410 | if (!q->n_bd) | |
411 | return; | |
412 | ||
39644e9a EG |
413 | /* In the command queue, all the TBs are mapped as BIDI |
414 | * so unmap them as such. | |
415 | */ | |
cda4ee3f | 416 | if (txq_id == trans->shrd->cmd_queue) { |
39644e9a | 417 | dma_dir = DMA_BIDIRECTIONAL; |
cda4ee3f EG |
418 | lock = &trans->hcmd_lock; |
419 | } else { | |
39644e9a | 420 | dma_dir = DMA_TO_DEVICE; |
cda4ee3f EG |
421 | lock = &trans->shrd->sta_lock; |
422 | } | |
39644e9a | 423 | |
cda4ee3f | 424 | spin_lock_irqsave(lock, flags); |
c170b867 EG |
425 | while (q->write_ptr != q->read_ptr) { |
426 | /* The read_ptr needs to bound by q->n_window */ | |
39644e9a EG |
427 | iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr), |
428 | dma_dir); | |
c170b867 EG |
429 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
430 | } | |
cda4ee3f | 431 | spin_unlock_irqrestore(lock, flags); |
c170b867 EG |
432 | } |
433 | ||
1359ca4f EG |
434 | /** |
435 | * iwl_tx_queue_free - Deallocate DMA queue. | |
436 | * @txq: Transmit queue to deallocate. | |
437 | * | |
438 | * Empty queue by removing and destroying all BD's. | |
439 | * Free all buffers. | |
440 | * 0-fill, but do not free "txq" descriptor structure. | |
441 | */ | |
6d8f6eeb | 442 | static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id) |
1359ca4f | 443 | { |
8ad71bef EG |
444 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
445 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
6d8f6eeb | 446 | struct device *dev = bus(trans)->dev; |
1359ca4f EG |
447 | int i; |
448 | if (WARN_ON(!txq)) | |
449 | return; | |
450 | ||
6d8f6eeb | 451 | iwl_tx_queue_unmap(trans, txq_id); |
1359ca4f EG |
452 | |
453 | /* De-alloc array of command/tx buffers */ | |
dfa2bdba EG |
454 | |
455 | if (txq_id == trans->shrd->cmd_queue) | |
456 | for (i = 0; i < txq->q.n_window; i++) | |
457 | kfree(txq->cmd[i]); | |
1359ca4f EG |
458 | |
459 | /* De-alloc circular buffer of TFDs */ | |
460 | if (txq->q.n_bd) { | |
ab9e212e | 461 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * |
1359ca4f EG |
462 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
463 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
464 | } | |
465 | ||
466 | /* De-alloc array of per-TFD driver data */ | |
2c452297 EG |
467 | kfree(txq->skbs); |
468 | txq->skbs = NULL; | |
1359ca4f EG |
469 | |
470 | /* deallocate arrays */ | |
471 | kfree(txq->cmd); | |
472 | kfree(txq->meta); | |
473 | txq->cmd = NULL; | |
474 | txq->meta = NULL; | |
475 | ||
476 | /* 0-fill queue descriptor structure */ | |
477 | memset(txq, 0, sizeof(*txq)); | |
478 | } | |
479 | ||
480 | /** | |
481 | * iwl_trans_tx_free - Free TXQ Context | |
482 | * | |
483 | * Destroy all TX DMA queues and structures | |
484 | */ | |
6d8f6eeb | 485 | static void iwl_trans_pcie_tx_free(struct iwl_trans *trans) |
1359ca4f EG |
486 | { |
487 | int txq_id; | |
8ad71bef | 488 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1359ca4f EG |
489 | |
490 | /* Tx queues */ | |
8ad71bef | 491 | if (trans_pcie->txq) { |
d6189124 | 492 | for (txq_id = 0; |
6d8f6eeb EG |
493 | txq_id < hw_params(trans).max_txq_num; txq_id++) |
494 | iwl_tx_queue_free(trans, txq_id); | |
1359ca4f EG |
495 | } |
496 | ||
8ad71bef EG |
497 | kfree(trans_pcie->txq); |
498 | trans_pcie->txq = NULL; | |
1359ca4f | 499 | |
9d6b2cb1 | 500 | iwlagn_free_dma_ptr(trans, &trans_pcie->kw); |
1359ca4f | 501 | |
6d8f6eeb | 502 | iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); |
1359ca4f EG |
503 | } |
504 | ||
02aca585 EG |
505 | /** |
506 | * iwl_trans_tx_alloc - allocate TX context | |
507 | * Allocate all Tx DMA structures and initialize them | |
508 | * | |
509 | * @param priv | |
510 | * @return error code | |
511 | */ | |
6d8f6eeb | 512 | static int iwl_trans_tx_alloc(struct iwl_trans *trans) |
02aca585 EG |
513 | { |
514 | int ret; | |
515 | int txq_id, slots_num; | |
8ad71bef | 516 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 517 | |
fd656935 | 518 | u16 scd_bc_tbls_size = hw_params(trans).max_txq_num * |
ab9e212e EG |
519 | sizeof(struct iwlagn_scd_bc_tbl); |
520 | ||
02aca585 EG |
521 | /*It is not allowed to alloc twice, so warn when this happens. |
522 | * We cannot rely on the previous allocation, so free and fail */ | |
8ad71bef | 523 | if (WARN_ON(trans_pcie->txq)) { |
02aca585 EG |
524 | ret = -EINVAL; |
525 | goto error; | |
526 | } | |
527 | ||
6d8f6eeb | 528 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, |
ab9e212e | 529 | scd_bc_tbls_size); |
02aca585 | 530 | if (ret) { |
6d8f6eeb | 531 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); |
02aca585 EG |
532 | goto error; |
533 | } | |
534 | ||
535 | /* Alloc keep-warm buffer */ | |
9d6b2cb1 | 536 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); |
02aca585 | 537 | if (ret) { |
6d8f6eeb | 538 | IWL_ERR(trans, "Keep Warm allocation failed\n"); |
02aca585 EG |
539 | goto error; |
540 | } | |
541 | ||
7f90dce1 EG |
542 | trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num, |
543 | sizeof(struct iwl_tx_queue), GFP_KERNEL); | |
8ad71bef | 544 | if (!trans_pcie->txq) { |
6d8f6eeb | 545 | IWL_ERR(trans, "Not enough memory for txq\n"); |
02aca585 EG |
546 | ret = ENOMEM; |
547 | goto error; | |
548 | } | |
549 | ||
550 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
6d8f6eeb EG |
551 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) { |
552 | slots_num = (txq_id == trans->shrd->cmd_queue) ? | |
02aca585 | 553 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
554 | ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id], |
555 | slots_num, txq_id); | |
02aca585 | 556 | if (ret) { |
6d8f6eeb | 557 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); |
02aca585 EG |
558 | goto error; |
559 | } | |
560 | } | |
561 | ||
562 | return 0; | |
563 | ||
564 | error: | |
ae2c30bf | 565 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
566 | |
567 | return ret; | |
568 | } | |
6d8f6eeb | 569 | static int iwl_tx_init(struct iwl_trans *trans) |
02aca585 EG |
570 | { |
571 | int ret; | |
572 | int txq_id, slots_num; | |
573 | unsigned long flags; | |
574 | bool alloc = false; | |
8ad71bef | 575 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 576 | |
8ad71bef | 577 | if (!trans_pcie->txq) { |
6d8f6eeb | 578 | ret = iwl_trans_tx_alloc(trans); |
02aca585 EG |
579 | if (ret) |
580 | goto error; | |
581 | alloc = true; | |
582 | } | |
583 | ||
6d8f6eeb | 584 | spin_lock_irqsave(&trans->shrd->lock, flags); |
02aca585 EG |
585 | |
586 | /* Turn off all Tx DMA fifos */ | |
83ed9015 | 587 | iwl_write_prph(bus(trans), SCD_TXFACT, 0); |
02aca585 EG |
588 | |
589 | /* Tell NIC where to find the "keep warm" buffer */ | |
83ed9015 EG |
590 | iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG, |
591 | trans_pcie->kw.dma >> 4); | |
02aca585 | 592 | |
6d8f6eeb | 593 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
02aca585 EG |
594 | |
595 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
6d8f6eeb EG |
596 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) { |
597 | slots_num = (txq_id == trans->shrd->cmd_queue) ? | |
02aca585 | 598 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
599 | ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id], |
600 | slots_num, txq_id); | |
02aca585 | 601 | if (ret) { |
6d8f6eeb | 602 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); |
02aca585 EG |
603 | goto error; |
604 | } | |
605 | } | |
606 | ||
607 | return 0; | |
608 | error: | |
609 | /*Upon error, free only if we allocated something */ | |
610 | if (alloc) | |
ae2c30bf | 611 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
612 | return ret; |
613 | } | |
614 | ||
3e10caeb | 615 | static void iwl_set_pwr_vmain(struct iwl_trans *trans) |
392f8b78 EG |
616 | { |
617 | /* | |
618 | * (for documentation purposes) | |
619 | * to set power to V_AUX, do: | |
620 | ||
621 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
83ed9015 | 622 | iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG, |
392f8b78 EG |
623 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
624 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
625 | */ | |
626 | ||
83ed9015 | 627 | iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG, |
392f8b78 EG |
628 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
629 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
630 | } | |
631 | ||
6d8f6eeb | 632 | static int iwl_nic_init(struct iwl_trans *trans) |
392f8b78 EG |
633 | { |
634 | unsigned long flags; | |
635 | ||
636 | /* nic_init */ | |
6d8f6eeb | 637 | spin_lock_irqsave(&trans->shrd->lock, flags); |
3e10caeb | 638 | iwl_apm_init(priv(trans)); |
392f8b78 EG |
639 | |
640 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
83ed9015 EG |
641 | iwl_write8(bus(trans), CSR_INT_COALESCING, |
642 | IWL_HOST_INT_CALIB_TIMEOUT_DEF); | |
392f8b78 | 643 | |
6d8f6eeb | 644 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
392f8b78 | 645 | |
3e10caeb | 646 | iwl_set_pwr_vmain(trans); |
392f8b78 | 647 | |
7a10e3e4 | 648 | iwl_nic_config(priv(trans)); |
392f8b78 | 649 | |
a5916977 | 650 | #ifndef CONFIG_IWLWIFI_IDI |
392f8b78 | 651 | /* Allocate the RX queue, or reset if it is already allocated */ |
6d8f6eeb | 652 | iwl_rx_init(trans); |
a5916977 | 653 | #endif |
392f8b78 EG |
654 | |
655 | /* Allocate or reset and init all Tx and Command queues */ | |
6d8f6eeb | 656 | if (iwl_tx_init(trans)) |
392f8b78 EG |
657 | return -ENOMEM; |
658 | ||
fd656935 | 659 | if (hw_params(trans).shadow_reg_enable) { |
392f8b78 | 660 | /* enable shadow regs in HW */ |
83ed9015 | 661 | iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL, |
392f8b78 EG |
662 | 0x800FFFFF); |
663 | } | |
664 | ||
6d8f6eeb | 665 | set_bit(STATUS_INIT, &trans->shrd->status); |
392f8b78 EG |
666 | |
667 | return 0; | |
668 | } | |
669 | ||
670 | #define HW_READY_TIMEOUT (50) | |
671 | ||
672 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
6d8f6eeb | 673 | static int iwl_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
674 | { |
675 | int ret; | |
676 | ||
83ed9015 | 677 | iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
678 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
679 | ||
680 | /* See if we got it */ | |
83ed9015 | 681 | ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
682 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
683 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
684 | HW_READY_TIMEOUT); | |
685 | ||
6d8f6eeb | 686 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
687 | return ret; |
688 | } | |
689 | ||
690 | /* Note: returns standard 0/-ERROR code */ | |
6d8f6eeb | 691 | static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
692 | { |
693 | int ret; | |
694 | ||
6d8f6eeb | 695 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 696 | |
6d8f6eeb | 697 | ret = iwl_set_hw_ready(trans); |
392f8b78 EG |
698 | if (ret >= 0) |
699 | return 0; | |
700 | ||
701 | /* If HW is not ready, prepare the conditions to check again */ | |
83ed9015 | 702 | iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
703 | CSR_HW_IF_CONFIG_REG_PREPARE); |
704 | ||
83ed9015 | 705 | ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
706 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, |
707 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
708 | ||
709 | if (ret < 0) | |
710 | return ret; | |
711 | ||
712 | /* HW should be ready by now, check again. */ | |
6d8f6eeb | 713 | ret = iwl_set_hw_ready(trans); |
392f8b78 EG |
714 | if (ret >= 0) |
715 | return 0; | |
716 | return ret; | |
717 | } | |
718 | ||
e13c0c59 EG |
719 | #define IWL_AC_UNSET -1 |
720 | ||
721 | struct queue_to_fifo_ac { | |
722 | s8 fifo, ac; | |
723 | }; | |
724 | ||
725 | static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = { | |
726 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
727 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
728 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
729 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
730 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
731 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
732 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
733 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
734 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
735 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
736 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
737 | }; | |
738 | ||
739 | static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = { | |
740 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
741 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
742 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
743 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
744 | { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, }, | |
745 | { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, }, | |
746 | { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, }, | |
747 | { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, }, | |
748 | { IWL_TX_FIFO_BE_IPAN, 2, }, | |
749 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
750 | { IWL_TX_FIFO_AUX, IWL_AC_UNSET, }, | |
751 | }; | |
752 | ||
753 | static const u8 iwlagn_bss_ac_to_fifo[] = { | |
754 | IWL_TX_FIFO_VO, | |
755 | IWL_TX_FIFO_VI, | |
756 | IWL_TX_FIFO_BE, | |
757 | IWL_TX_FIFO_BK, | |
758 | }; | |
759 | static const u8 iwlagn_bss_ac_to_queue[] = { | |
760 | 0, 1, 2, 3, | |
761 | }; | |
762 | static const u8 iwlagn_pan_ac_to_fifo[] = { | |
763 | IWL_TX_FIFO_VO_IPAN, | |
764 | IWL_TX_FIFO_VI_IPAN, | |
765 | IWL_TX_FIFO_BE_IPAN, | |
766 | IWL_TX_FIFO_BK_IPAN, | |
767 | }; | |
768 | static const u8 iwlagn_pan_ac_to_queue[] = { | |
769 | 7, 6, 5, 4, | |
770 | }; | |
771 | ||
6d8f6eeb | 772 | static int iwl_trans_pcie_start_device(struct iwl_trans *trans) |
392f8b78 EG |
773 | { |
774 | int ret; | |
e13c0c59 EG |
775 | struct iwl_trans_pcie *trans_pcie = |
776 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
392f8b78 | 777 | |
c91bd124 | 778 | trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER; |
e13c0c59 EG |
779 | trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue; |
780 | trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue; | |
781 | ||
782 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo; | |
783 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo; | |
784 | ||
785 | trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0; | |
786 | trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE; | |
392f8b78 | 787 | |
c91bd124 | 788 | if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) && |
6d8f6eeb EG |
789 | iwl_trans_pcie_prepare_card_hw(trans)) { |
790 | IWL_WARN(trans, "Exit HW not ready\n"); | |
392f8b78 EG |
791 | return -EIO; |
792 | } | |
793 | ||
794 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
83ed9015 | 795 | if (iwl_read32(bus(trans), CSR_GP_CNTRL) & |
392f8b78 | 796 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
6d8f6eeb | 797 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
392f8b78 | 798 | else |
6d8f6eeb | 799 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
392f8b78 | 800 | |
6d8f6eeb | 801 | if (iwl_is_rfkill(trans->shrd)) { |
3e10caeb | 802 | iwl_set_hw_rfkill_state(priv(trans), true); |
6d8f6eeb | 803 | iwl_enable_interrupts(trans); |
392f8b78 EG |
804 | return -ERFKILL; |
805 | } | |
806 | ||
83ed9015 | 807 | iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF); |
392f8b78 | 808 | |
6d8f6eeb | 809 | ret = iwl_nic_init(trans); |
392f8b78 | 810 | if (ret) { |
6d8f6eeb | 811 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
812 | return ret; |
813 | } | |
814 | ||
815 | /* make sure rfkill handshake bits are cleared */ | |
83ed9015 EG |
816 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
817 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
818 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
819 | ||
820 | /* clear (again), then enable host interrupts */ | |
83ed9015 | 821 | iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 822 | iwl_enable_interrupts(trans); |
392f8b78 EG |
823 | |
824 | /* really make sure rfkill handshake bits are cleared */ | |
83ed9015 EG |
825 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
826 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 EG |
827 | |
828 | return 0; | |
829 | } | |
830 | ||
b3c2ce13 EG |
831 | /* |
832 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
10b15e6f | 833 | * must be called under priv->shrd->lock and mac access |
b3c2ce13 | 834 | */ |
6d8f6eeb | 835 | static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) |
b3c2ce13 | 836 | { |
83ed9015 | 837 | iwl_write_prph(bus(trans), SCD_TXFACT, mask); |
b3c2ce13 EG |
838 | } |
839 | ||
ed6a3803 | 840 | static void iwl_tx_start(struct iwl_trans *trans) |
b3c2ce13 EG |
841 | { |
842 | const struct queue_to_fifo_ac *queue_to_fifo; | |
105183b1 EG |
843 | struct iwl_trans_pcie *trans_pcie = |
844 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
b3c2ce13 EG |
845 | u32 a; |
846 | unsigned long flags; | |
847 | int i, chan; | |
848 | u32 reg_val; | |
849 | ||
105183b1 | 850 | spin_lock_irqsave(&trans->shrd->lock, flags); |
b3c2ce13 | 851 | |
83ed9015 EG |
852 | trans_pcie->scd_base_addr = |
853 | iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR); | |
105183b1 | 854 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; |
b3c2ce13 | 855 | /* reset conext data memory */ |
105183b1 | 856 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
b3c2ce13 | 857 | a += 4) |
83ed9015 | 858 | iwl_write_targ_mem(bus(trans), a, 0); |
b3c2ce13 | 859 | /* reset tx status memory */ |
105183b1 | 860 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
b3c2ce13 | 861 | a += 4) |
83ed9015 | 862 | iwl_write_targ_mem(bus(trans), a, 0); |
105183b1 | 863 | for (; a < trans_pcie->scd_base_addr + |
c91bd124 | 864 | SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num); |
d6189124 | 865 | a += 4) |
83ed9015 | 866 | iwl_write_targ_mem(bus(trans), a, 0); |
b3c2ce13 | 867 | |
83ed9015 | 868 | iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR, |
105183b1 | 869 | trans_pcie->scd_bc_tbls.dma >> 10); |
b3c2ce13 EG |
870 | |
871 | /* Enable DMA channel */ | |
872 | for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) | |
83ed9015 | 873 | iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
b3c2ce13 EG |
874 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
875 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
876 | ||
877 | /* Update FH chicken bits */ | |
83ed9015 EG |
878 | reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG); |
879 | iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG, | |
b3c2ce13 EG |
880 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
881 | ||
83ed9015 | 882 | iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL, |
c91bd124 | 883 | SCD_QUEUECHAIN_SEL_ALL(trans)); |
83ed9015 | 884 | iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0); |
b3c2ce13 EG |
885 | |
886 | /* initiate the queues */ | |
c91bd124 | 887 | for (i = 0; i < hw_params(trans).max_txq_num; i++) { |
83ed9015 EG |
888 | iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0); |
889 | iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8)); | |
890 | iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + | |
b3c2ce13 | 891 | SCD_CONTEXT_QUEUE_OFFSET(i), 0); |
83ed9015 | 892 | iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + |
b3c2ce13 EG |
893 | SCD_CONTEXT_QUEUE_OFFSET(i) + |
894 | sizeof(u32), | |
895 | ((SCD_WIN_SIZE << | |
896 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
897 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
898 | ((SCD_FRAME_LIMIT << | |
899 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
900 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
901 | } | |
902 | ||
83ed9015 | 903 | iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK, |
105183b1 | 904 | IWL_MASK(0, hw_params(trans).max_txq_num)); |
b3c2ce13 EG |
905 | |
906 | /* Activate all Tx DMA/FIFO channels */ | |
6d8f6eeb | 907 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); |
b3c2ce13 EG |
908 | |
909 | /* map queues to FIFOs */ | |
7a10e3e4 | 910 | if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
b3c2ce13 EG |
911 | queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo; |
912 | else | |
913 | queue_to_fifo = iwlagn_default_queue_to_tx_fifo; | |
914 | ||
6d8f6eeb | 915 | iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0); |
b3c2ce13 EG |
916 | |
917 | /* make sure all queue are not stopped */ | |
8ad71bef EG |
918 | memset(&trans_pcie->queue_stopped[0], 0, |
919 | sizeof(trans_pcie->queue_stopped)); | |
b3c2ce13 | 920 | for (i = 0; i < 4; i++) |
8ad71bef | 921 | atomic_set(&trans_pcie->queue_stop_count[i], 0); |
b3c2ce13 EG |
922 | |
923 | /* reset to 0 to enable all the queue first */ | |
8ad71bef | 924 | trans_pcie->txq_ctx_active_msk = 0; |
b3c2ce13 | 925 | |
effcea16 | 926 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) < |
72c04ce0 | 927 | IWLAGN_FIRST_AMPDU_QUEUE); |
effcea16 | 928 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) < |
72c04ce0 | 929 | IWLAGN_FIRST_AMPDU_QUEUE); |
b3c2ce13 | 930 | |
72c04ce0 | 931 | for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) { |
b3c2ce13 EG |
932 | int fifo = queue_to_fifo[i].fifo; |
933 | int ac = queue_to_fifo[i].ac; | |
934 | ||
8ad71bef | 935 | iwl_txq_ctx_activate(trans_pcie, i); |
b3c2ce13 EG |
936 | |
937 | if (fifo == IWL_TX_FIFO_UNUSED) | |
938 | continue; | |
939 | ||
940 | if (ac != IWL_AC_UNSET) | |
8ad71bef EG |
941 | iwl_set_swq_id(&trans_pcie->txq[i], ac, i); |
942 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i], | |
943 | fifo, 0); | |
b3c2ce13 EG |
944 | } |
945 | ||
6d8f6eeb | 946 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
b3c2ce13 EG |
947 | |
948 | /* Enable L1-Active */ | |
83ed9015 | 949 | iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG, |
b3c2ce13 EG |
950 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
951 | } | |
952 | ||
ed6a3803 EG |
953 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans) |
954 | { | |
955 | iwl_reset_ict(trans); | |
956 | iwl_tx_start(trans); | |
957 | } | |
958 | ||
c170b867 EG |
959 | /** |
960 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels | |
961 | */ | |
6d8f6eeb | 962 | static int iwl_trans_tx_stop(struct iwl_trans *trans) |
c170b867 EG |
963 | { |
964 | int ch, txq_id; | |
965 | unsigned long flags; | |
8ad71bef | 966 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c170b867 EG |
967 | |
968 | /* Turn off all Tx DMA fifos */ | |
6d8f6eeb | 969 | spin_lock_irqsave(&trans->shrd->lock, flags); |
c170b867 | 970 | |
6d8f6eeb | 971 | iwl_trans_txq_set_sched(trans, 0); |
c170b867 EG |
972 | |
973 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
02f6f659 | 974 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
83ed9015 | 975 | iwl_write_direct32(bus(trans), |
6d8f6eeb | 976 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
83ed9015 | 977 | if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG, |
c170b867 EG |
978 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
979 | 1000)) | |
6d8f6eeb | 980 | IWL_ERR(trans, "Failing on timeout while stopping" |
c170b867 | 981 | " DMA channel %d [0x%08x]", ch, |
83ed9015 | 982 | iwl_read_direct32(bus(trans), |
6d8f6eeb | 983 | FH_TSSR_TX_STATUS_REG)); |
c170b867 | 984 | } |
6d8f6eeb | 985 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
c170b867 | 986 | |
8ad71bef | 987 | if (!trans_pcie->txq) { |
6d8f6eeb | 988 | IWL_WARN(trans, "Stopping tx queues that aren't allocated..."); |
c170b867 EG |
989 | return 0; |
990 | } | |
991 | ||
992 | /* Unmap DMA from host system and free skb's */ | |
6d8f6eeb EG |
993 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) |
994 | iwl_tx_queue_unmap(trans, txq_id); | |
c170b867 EG |
995 | |
996 | return 0; | |
997 | } | |
998 | ||
43e58856 | 999 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf EG |
1000 | { |
1001 | unsigned long flags; | |
43e58856 | 1002 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ae2c30bf | 1003 | |
43e58856 | 1004 | /* tell the device to stop sending interrupts */ |
ae2c30bf EG |
1005 | spin_lock_irqsave(&trans->shrd->lock, flags); |
1006 | iwl_disable_interrupts(trans); | |
1007 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
1008 | ||
ab6cf8e8 | 1009 | /* device going down, Stop using ICT table */ |
6d8f6eeb | 1010 | iwl_disable_ict(trans); |
ab6cf8e8 EG |
1011 | |
1012 | /* | |
1013 | * If a HW restart happens during firmware loading, | |
1014 | * then the firmware loading might call this function | |
1015 | * and later it might be called again due to the | |
1016 | * restart. So don't process again if the device is | |
1017 | * already dead. | |
1018 | */ | |
6d8f6eeb EG |
1019 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) { |
1020 | iwl_trans_tx_stop(trans); | |
a5916977 | 1021 | #ifndef CONFIG_IWLWIFI_IDI |
6d8f6eeb | 1022 | iwl_trans_rx_stop(trans); |
a5916977 | 1023 | #endif |
ab6cf8e8 | 1024 | /* Power-down device's busmaster DMA clocks */ |
83ed9015 | 1025 | iwl_write_prph(bus(trans), APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
1026 | APMG_CLK_VAL_DMA_CLK_RQT); |
1027 | udelay(5); | |
1028 | } | |
1029 | ||
1030 | /* Make sure (redundant) we've released our request to stay awake */ | |
83ed9015 | 1031 | iwl_clear_bit(bus(trans), CSR_GP_CNTRL, |
6d8f6eeb | 1032 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1033 | |
1034 | /* Stop the device, and put it in low power state */ | |
6d8f6eeb | 1035 | iwl_apm_stop(priv(trans)); |
43e58856 EG |
1036 | |
1037 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1038 | * Clean again the interrupt here | |
1039 | */ | |
1040 | spin_lock_irqsave(&trans->shrd->lock, flags); | |
1041 | iwl_disable_interrupts(trans); | |
1042 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
1043 | ||
1044 | /* wait to make sure we flush pending tasklet*/ | |
1045 | synchronize_irq(bus(trans)->irq); | |
1046 | tasklet_kill(&trans_pcie->irq_tasklet); | |
1047 | ||
1048 | /* stop and reset the on-board processor */ | |
1049 | iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
ab6cf8e8 EG |
1050 | } |
1051 | ||
e13c0c59 | 1052 | static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
14991a9d | 1053 | struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx, |
34b5321e | 1054 | u8 sta_id, u8 tid) |
47c1b496 | 1055 | { |
e13c0c59 EG |
1056 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1057 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
1058 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
132f98c2 | 1059 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload; |
47c1b496 | 1060 | struct iwl_cmd_meta *out_meta; |
e13c0c59 EG |
1061 | struct iwl_tx_queue *txq; |
1062 | struct iwl_queue *q; | |
47c1b496 EG |
1063 | |
1064 | dma_addr_t phys_addr = 0; | |
1065 | dma_addr_t txcmd_phys; | |
1066 | dma_addr_t scratch_phys; | |
1067 | u16 len, firstlen, secondlen; | |
1068 | u8 wait_write_ptr = 0; | |
e13c0c59 | 1069 | u8 txq_id; |
e13c0c59 EG |
1070 | bool is_agg = false; |
1071 | __le16 fc = hdr->frame_control; | |
47c1b496 | 1072 | u8 hdr_len = ieee80211_hdrlen(fc); |
631b84c5 | 1073 | u16 __maybe_unused wifi_seq; |
47c1b496 | 1074 | |
e13c0c59 EG |
1075 | /* |
1076 | * Send this frame after DTIM -- there's a special queue | |
1077 | * reserved for this for contexts that support AP mode. | |
1078 | */ | |
1079 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { | |
1080 | txq_id = trans_pcie->mcast_queue[ctx]; | |
1081 | ||
1082 | /* | |
1083 | * The microcode will clear the more data | |
1084 | * bit in the last frame it transmits. | |
1085 | */ | |
1086 | hdr->frame_control |= | |
1087 | cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
1088 | } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) | |
1089 | txq_id = IWL_AUX_QUEUE; | |
1090 | else | |
1091 | txq_id = | |
1092 | trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)]; | |
1093 | ||
97756fb1 EG |
1094 | /* aggregation is on for this <sta,tid> */ |
1095 | if (info->flags & IEEE80211_TX_CTL_AMPDU) { | |
1096 | WARN_ON(tid >= IWL_MAX_TID_COUNT); | |
1097 | txq_id = trans_pcie->agg_txq[sta_id][tid]; | |
1098 | is_agg = true; | |
e13c0c59 EG |
1099 | } |
1100 | ||
8ad71bef | 1101 | txq = &trans_pcie->txq[txq_id]; |
e13c0c59 EG |
1102 | q = &txq->q; |
1103 | ||
631b84c5 EG |
1104 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1105 | * sequence number. This is a HW requirements to help the SCD to parse | |
1106 | * the BA. | |
1107 | * Check here that the packets are in the right place on the ring. | |
1108 | */ | |
1109 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1110 | wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); | |
1111 | WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr), | |
1112 | "Q: %d WiFi Seq %d tfdNum %d", | |
1113 | txq_id, wifi_seq, q->write_ptr); | |
1114 | #endif | |
1115 | ||
47c1b496 | 1116 | /* Set up driver data for this TFD */ |
2c452297 | 1117 | txq->skbs[q->write_ptr] = skb; |
dfa2bdba EG |
1118 | txq->cmd[q->write_ptr] = dev_cmd; |
1119 | ||
1120 | dev_cmd->hdr.cmd = REPLY_TX; | |
1121 | dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1122 | INDEX_TO_SEQ(q->write_ptr))); | |
47c1b496 EG |
1123 | |
1124 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1125 | out_meta = &txq->meta[q->write_ptr]; | |
1126 | ||
1127 | /* | |
1128 | * Use the first empty entry in this queue's command buffer array | |
1129 | * to contain the Tx command and MAC header concatenated together | |
1130 | * (payload data will be in another buffer). | |
1131 | * Size of this varies, due to varying MAC header length. | |
1132 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1133 | * of the MAC header (device reads on dword boundaries). | |
1134 | * We'll tell device about this padding later. | |
1135 | */ | |
1136 | len = sizeof(struct iwl_tx_cmd) + | |
1137 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1138 | firstlen = (len + 3) & ~3; | |
1139 | ||
1140 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1141 | if (firstlen != len) | |
1142 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1143 | ||
1144 | /* Physical address of this Tx command's header (not MAC header!), | |
1145 | * within command buffer array. */ | |
e13c0c59 | 1146 | txcmd_phys = dma_map_single(bus(trans)->dev, |
47c1b496 EG |
1147 | &dev_cmd->hdr, firstlen, |
1148 | DMA_BIDIRECTIONAL); | |
e13c0c59 | 1149 | if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys))) |
47c1b496 EG |
1150 | return -1; |
1151 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); | |
1152 | dma_unmap_len_set(out_meta, len, firstlen); | |
1153 | ||
1154 | if (!ieee80211_has_morefrags(fc)) { | |
1155 | txq->need_update = 1; | |
1156 | } else { | |
1157 | wait_write_ptr = 1; | |
1158 | txq->need_update = 0; | |
1159 | } | |
1160 | ||
1161 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
1162 | * if any (802.11 null frames have no payload). */ | |
1163 | secondlen = skb->len - hdr_len; | |
1164 | if (secondlen > 0) { | |
e13c0c59 | 1165 | phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len, |
47c1b496 | 1166 | secondlen, DMA_TO_DEVICE); |
e13c0c59 EG |
1167 | if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) { |
1168 | dma_unmap_single(bus(trans)->dev, | |
47c1b496 EG |
1169 | dma_unmap_addr(out_meta, mapping), |
1170 | dma_unmap_len(out_meta, len), | |
1171 | DMA_BIDIRECTIONAL); | |
1172 | return -1; | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | /* Attach buffers to TFD */ | |
e13c0c59 | 1177 | iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1); |
47c1b496 | 1178 | if (secondlen > 0) |
e13c0c59 | 1179 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
47c1b496 EG |
1180 | secondlen, 0); |
1181 | ||
1182 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
1183 | offsetof(struct iwl_tx_cmd, scratch); | |
1184 | ||
1185 | /* take back ownership of DMA buffer to enable update */ | |
e13c0c59 | 1186 | dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1187 | DMA_BIDIRECTIONAL); |
1188 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1189 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1190 | ||
e13c0c59 | 1191 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
47c1b496 | 1192 | le16_to_cpu(dev_cmd->hdr.sequence)); |
e13c0c59 EG |
1193 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
1194 | iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
1195 | iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
47c1b496 EG |
1196 | |
1197 | /* Set up entry for this TFD in Tx byte-count array */ | |
96f1f05a | 1198 | iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); |
47c1b496 | 1199 | |
e13c0c59 | 1200 | dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1201 | DMA_BIDIRECTIONAL); |
1202 | ||
e13c0c59 | 1203 | trace_iwlwifi_dev_tx(priv(trans), |
47c1b496 EG |
1204 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], |
1205 | sizeof(struct iwl_tfd), | |
1206 | &dev_cmd->hdr, firstlen, | |
1207 | skb->data + hdr_len, secondlen); | |
1208 | ||
1209 | /* Tell device the write index *just past* this latest filled TFD */ | |
1210 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
e13c0c59 EG |
1211 | iwl_txq_update_write_ptr(trans, txq); |
1212 | ||
47c1b496 EG |
1213 | /* |
1214 | * At this point the frame is "transmitted" successfully | |
1215 | * and we will get a TX status notification eventually, | |
1216 | * regardless of the value of ret. "ret" only indicates | |
1217 | * whether or not we should update the write pointer. | |
1218 | */ | |
a0eaad71 | 1219 | if (iwl_queue_space(q) < q->high_mark) { |
47c1b496 EG |
1220 | if (wait_write_ptr) { |
1221 | txq->need_update = 1; | |
e13c0c59 | 1222 | iwl_txq_update_write_ptr(trans, txq); |
47c1b496 | 1223 | } else { |
81a3de1c | 1224 | iwl_stop_queue(trans, txq, "Queue is full"); |
47c1b496 EG |
1225 | } |
1226 | } | |
1227 | return 0; | |
1228 | } | |
1229 | ||
6d8f6eeb | 1230 | static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans) |
56d90f4c EG |
1231 | { |
1232 | /* Remove all resets to allow NIC to operate */ | |
83ed9015 | 1233 | iwl_write32(bus(trans), CSR_RESET, 0); |
56d90f4c EG |
1234 | } |
1235 | ||
e6bb4c9c EG |
1236 | static int iwl_trans_pcie_request_irq(struct iwl_trans *trans) |
1237 | { | |
5a878bf6 EG |
1238 | struct iwl_trans_pcie *trans_pcie = |
1239 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
e6bb4c9c EG |
1240 | int err; |
1241 | ||
0c325769 EG |
1242 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1243 | ||
1244 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
1245 | iwl_irq_tasklet, (unsigned long)trans); | |
e6bb4c9c | 1246 | |
0c325769 | 1247 | iwl_alloc_isr_ict(trans); |
e6bb4c9c EG |
1248 | |
1249 | err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED, | |
0c325769 | 1250 | DRV_NAME, trans); |
e6bb4c9c | 1251 | if (err) { |
0c325769 EG |
1252 | IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq); |
1253 | iwl_free_isr_ict(trans); | |
e6bb4c9c EG |
1254 | return err; |
1255 | } | |
1256 | ||
5a878bf6 | 1257 | INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish); |
e6bb4c9c EG |
1258 | return 0; |
1259 | } | |
1260 | ||
76bc10fc | 1261 | static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid, |
464021ff EG |
1262 | int txq_id, int ssn, u32 status, |
1263 | struct sk_buff_head *skbs) | |
1264 | { | |
8ad71bef EG |
1265 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1266 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 EG |
1267 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
1268 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
464021ff | 1269 | int freed = 0; |
a0eaad71 | 1270 | |
8ad71bef EG |
1271 | txq->time_stamp = jiffies; |
1272 | ||
76bc10fc EG |
1273 | if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE && |
1274 | txq_id != trans_pcie->agg_txq[sta_id][tid])) { | |
1275 | /* | |
1276 | * FIXME: this is a uCode bug which need to be addressed, | |
1277 | * log the information and return for now. | |
1278 | * Since it is can possibly happen very often and in order | |
1279 | * not to fill the syslog, don't use IWL_ERR or IWL_WARN | |
1280 | */ | |
1281 | IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, " | |
1282 | "agg_txq[sta_id[tid] %d", txq_id, | |
1283 | trans_pcie->agg_txq[sta_id][tid]); | |
1284 | return 1; | |
a0eaad71 EG |
1285 | } |
1286 | ||
1287 | if (txq->q.read_ptr != tfd_num) { | |
1daf04b8 EG |
1288 | IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n", |
1289 | txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr, | |
1290 | tfd_num, ssn); | |
464021ff | 1291 | freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs); |
1ba42da4 EG |
1292 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && |
1293 | (!txq->sched_retry || | |
1294 | status != TX_STATUS_FAIL_PASSIVE_NO_RX)) | |
81a3de1c | 1295 | iwl_wake_queue(trans, txq, "Packets reclaimed"); |
a0eaad71 | 1296 | } |
76bc10fc | 1297 | return 0; |
a0eaad71 EG |
1298 | } |
1299 | ||
6d8f6eeb | 1300 | static void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1301 | { |
45c30dba | 1302 | iwl_calib_free_results(trans); |
ae2c30bf | 1303 | iwl_trans_pcie_tx_free(trans); |
a5916977 | 1304 | #ifndef CONFIG_IWLWIFI_IDI |
ae2c30bf | 1305 | iwl_trans_pcie_rx_free(trans); |
a5916977 | 1306 | #endif |
6d8f6eeb EG |
1307 | free_irq(bus(trans)->irq, trans); |
1308 | iwl_free_isr_ict(trans); | |
1309 | trans->shrd->trans = NULL; | |
1310 | kfree(trans); | |
34c1b7ba EG |
1311 | } |
1312 | ||
c01a4047 | 1313 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1314 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
1315 | { | |
1316 | /* | |
1317 | * This function is called when system goes into suspend state | |
ade4c649 WYG |
1318 | * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend |
1319 | * function first but since iwlagn_mac_stop() has no knowledge of | |
1320 | * who the caller is, | |
57210f7c EG |
1321 | * it will not call apm_ops.stop() to stop the DMA operation. |
1322 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
1323 | * | |
1324 | * But of course ... if we have configured WoWLAN then we did other | |
1325 | * things already :-) | |
1326 | */ | |
d36120c6 | 1327 | if (!trans->shrd->wowlan) { |
57210f7c | 1328 | iwl_apm_stop(priv(trans)); |
d36120c6 JB |
1329 | } else { |
1330 | iwl_disable_interrupts(trans); | |
1331 | iwl_clear_bit(bus(trans), CSR_GP_CNTRL, | |
1332 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1333 | } | |
57210f7c EG |
1334 | |
1335 | return 0; | |
1336 | } | |
1337 | ||
1338 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
1339 | { | |
1340 | bool hw_rfkill = false; | |
1341 | ||
0c325769 | 1342 | iwl_enable_interrupts(trans); |
57210f7c | 1343 | |
83ed9015 | 1344 | if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) & |
57210f7c EG |
1345 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1346 | hw_rfkill = true; | |
1347 | ||
1348 | if (hw_rfkill) | |
1349 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); | |
1350 | else | |
1351 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); | |
1352 | ||
3e10caeb | 1353 | iwl_set_hw_rfkill_state(priv(trans), hw_rfkill); |
57210f7c EG |
1354 | |
1355 | return 0; | |
1356 | } | |
c01a4047 | 1357 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 1358 | |
e13c0c59 | 1359 | static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans, |
81a3de1c EG |
1360 | enum iwl_rxon_context_id ctx, |
1361 | const char *msg) | |
e13c0c59 EG |
1362 | { |
1363 | u8 ac, txq_id; | |
1364 | struct iwl_trans_pcie *trans_pcie = | |
1365 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1366 | ||
1367 | for (ac = 0; ac < AC_NUM; ac++) { | |
1368 | txq_id = trans_pcie->ac_to_queue[ctx][ac]; | |
81a3de1c | 1369 | IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n", |
e13c0c59 | 1370 | ac, |
8ad71bef | 1371 | (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0) |
e13c0c59 | 1372 | ? "stopped" : "awake"); |
81a3de1c | 1373 | iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg); |
e13c0c59 EG |
1374 | } |
1375 | } | |
1376 | ||
e6bb4c9c | 1377 | const struct iwl_trans_ops trans_ops_pcie; |
e419d62d | 1378 | |
b52e7ea1 EG |
1379 | struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd, |
1380 | struct pci_dev *pdev, | |
1381 | const struct pci_device_id *ent) | |
e6bb4c9c | 1382 | { |
b52e7ea1 | 1383 | struct iwl_trans_pcie *trans_pcie; |
e6bb4c9c EG |
1384 | struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) + |
1385 | sizeof(struct iwl_trans_pcie), | |
1386 | GFP_KERNEL); | |
b52e7ea1 EG |
1387 | |
1388 | if (WARN_ON(!iwl_trans)) | |
1389 | return NULL; | |
1390 | ||
1391 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(iwl_trans); | |
1392 | ||
1393 | iwl_trans->ops = &trans_ops_pcie; | |
1394 | iwl_trans->shrd = shrd; | |
1395 | trans_pcie->trans = iwl_trans; | |
1396 | spin_lock_init(&iwl_trans->hcmd_lock); | |
ab6cf8e8 | 1397 | |
e6bb4c9c EG |
1398 | return iwl_trans; |
1399 | } | |
47c1b496 | 1400 | |
81a3de1c EG |
1401 | static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id, |
1402 | const char *msg) | |
e20d4341 | 1403 | { |
8ad71bef EG |
1404 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1405 | ||
81a3de1c | 1406 | iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg); |
e20d4341 EG |
1407 | } |
1408 | ||
5f178cd2 EG |
1409 | #define IWL_FLUSH_WAIT_MS 2000 |
1410 | ||
1411 | static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans) | |
1412 | { | |
8ad71bef | 1413 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5f178cd2 EG |
1414 | struct iwl_tx_queue *txq; |
1415 | struct iwl_queue *q; | |
1416 | int cnt; | |
1417 | unsigned long now = jiffies; | |
1418 | int ret = 0; | |
1419 | ||
1420 | /* waiting for all the tx frames complete might take a while */ | |
1421 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { | |
1422 | if (cnt == trans->shrd->cmd_queue) | |
1423 | continue; | |
8ad71bef | 1424 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
1425 | q = &txq->q; |
1426 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1427 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1428 | msleep(1); | |
1429 | ||
1430 | if (q->read_ptr != q->write_ptr) { | |
1431 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); | |
1432 | ret = -ETIMEDOUT; | |
1433 | break; | |
1434 | } | |
1435 | } | |
1436 | return ret; | |
1437 | } | |
1438 | ||
f22be624 EG |
1439 | /* |
1440 | * On every watchdog tick we check (latest) time stamp. If it does not | |
1441 | * change during timeout period and queue is not empty we reset firmware. | |
1442 | */ | |
1443 | static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt) | |
1444 | { | |
8ad71bef EG |
1445 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1446 | struct iwl_tx_queue *txq = &trans_pcie->txq[cnt]; | |
f22be624 EG |
1447 | struct iwl_queue *q = &txq->q; |
1448 | unsigned long timeout; | |
1449 | ||
1450 | if (q->read_ptr == q->write_ptr) { | |
1451 | txq->time_stamp = jiffies; | |
1452 | return 0; | |
1453 | } | |
1454 | ||
1455 | timeout = txq->time_stamp + | |
1456 | msecs_to_jiffies(hw_params(trans).wd_timeout); | |
1457 | ||
1458 | if (time_after(jiffies, timeout)) { | |
1459 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id, | |
1460 | hw_params(trans).wd_timeout); | |
08d1700d | 1461 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
05f8a09f | 1462 | q->read_ptr, q->write_ptr); |
08d1700d EG |
1463 | IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n", |
1464 | iwl_read_prph(bus(trans), SCD_QUEUE_RDPTR(cnt)) | |
1465 | & (TFD_QUEUE_SIZE_MAX - 1), | |
1466 | iwl_read_prph(bus(trans), SCD_QUEUE_WRPTR(cnt))); | |
f22be624 EG |
1467 | return 1; |
1468 | } | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
ff620849 EG |
1473 | static const char *get_fh_string(int cmd) |
1474 | { | |
1475 | switch (cmd) { | |
1476 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
1477 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1478 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
1479 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
1480 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
1481 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
1482 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1483 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
1484 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
1485 | default: | |
1486 | return "UNKNOWN"; | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display) | |
1491 | { | |
1492 | int i; | |
1493 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1494 | int pos = 0; | |
1495 | size_t bufsz = 0; | |
1496 | #endif | |
1497 | static const u32 fh_tbl[] = { | |
1498 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
1499 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1500 | FH_RSCSR_CHNL0_WPTR, | |
1501 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
1502 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
1503 | FH_MEM_RSSR_RX_STATUS_REG, | |
1504 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1505 | FH_TSSR_TX_STATUS_REG, | |
1506 | FH_TSSR_TX_ERROR_REG | |
1507 | }; | |
1508 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1509 | if (display) { | |
1510 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1511 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1512 | if (!*buf) | |
1513 | return -ENOMEM; | |
1514 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1515 | "FH register values:\n"); | |
1516 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1517 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1518 | " %34s: 0X%08x\n", | |
1519 | get_fh_string(fh_tbl[i]), | |
1520 | iwl_read_direct32(bus(trans), fh_tbl[i])); | |
1521 | } | |
1522 | return pos; | |
1523 | } | |
1524 | #endif | |
1525 | IWL_ERR(trans, "FH register values:\n"); | |
1526 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1527 | IWL_ERR(trans, " %34s: 0X%08x\n", | |
1528 | get_fh_string(fh_tbl[i]), | |
1529 | iwl_read_direct32(bus(trans), fh_tbl[i])); | |
1530 | } | |
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | static const char *get_csr_string(int cmd) | |
1535 | { | |
1536 | switch (cmd) { | |
1537 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1538 | IWL_CMD(CSR_INT_COALESCING); | |
1539 | IWL_CMD(CSR_INT); | |
1540 | IWL_CMD(CSR_INT_MASK); | |
1541 | IWL_CMD(CSR_FH_INT_STATUS); | |
1542 | IWL_CMD(CSR_GPIO_IN); | |
1543 | IWL_CMD(CSR_RESET); | |
1544 | IWL_CMD(CSR_GP_CNTRL); | |
1545 | IWL_CMD(CSR_HW_REV); | |
1546 | IWL_CMD(CSR_EEPROM_REG); | |
1547 | IWL_CMD(CSR_EEPROM_GP); | |
1548 | IWL_CMD(CSR_OTP_GP_REG); | |
1549 | IWL_CMD(CSR_GIO_REG); | |
1550 | IWL_CMD(CSR_GP_UCODE_REG); | |
1551 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1552 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1553 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1554 | IWL_CMD(CSR_LED_REG); | |
1555 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1556 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1557 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1558 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1559 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1560 | default: | |
1561 | return "UNKNOWN"; | |
1562 | } | |
1563 | } | |
1564 | ||
1565 | void iwl_dump_csr(struct iwl_trans *trans) | |
1566 | { | |
1567 | int i; | |
1568 | static const u32 csr_tbl[] = { | |
1569 | CSR_HW_IF_CONFIG_REG, | |
1570 | CSR_INT_COALESCING, | |
1571 | CSR_INT, | |
1572 | CSR_INT_MASK, | |
1573 | CSR_FH_INT_STATUS, | |
1574 | CSR_GPIO_IN, | |
1575 | CSR_RESET, | |
1576 | CSR_GP_CNTRL, | |
1577 | CSR_HW_REV, | |
1578 | CSR_EEPROM_REG, | |
1579 | CSR_EEPROM_GP, | |
1580 | CSR_OTP_GP_REG, | |
1581 | CSR_GIO_REG, | |
1582 | CSR_GP_UCODE_REG, | |
1583 | CSR_GP_DRIVER_REG, | |
1584 | CSR_UCODE_DRV_GP1, | |
1585 | CSR_UCODE_DRV_GP2, | |
1586 | CSR_LED_REG, | |
1587 | CSR_DRAM_INT_TBL_REG, | |
1588 | CSR_GIO_CHICKEN_BITS, | |
1589 | CSR_ANA_PLL_CFG, | |
1590 | CSR_HW_REV_WA_REG, | |
1591 | CSR_DBG_HPET_MEM_REG | |
1592 | }; | |
1593 | IWL_ERR(trans, "CSR values:\n"); | |
1594 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1595 | "CSR_INT_PERIODIC_REG)\n"); | |
1596 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1597 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1598 | get_csr_string(csr_tbl[i]), | |
1599 | iwl_read32(bus(trans), csr_tbl[i])); | |
1600 | } | |
1601 | } | |
1602 | ||
87e5666c EG |
1603 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1604 | /* create and remove of files */ | |
1605 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1606 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c EG |
1607 | &iwl_dbgfs_##name##_ops)) \ |
1608 | return -ENOMEM; \ | |
1609 | } while (0) | |
1610 | ||
1611 | /* file operation */ | |
1612 | #define DEBUGFS_READ_FUNC(name) \ | |
1613 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1614 | char __user *user_buf, \ | |
1615 | size_t count, loff_t *ppos); | |
1616 | ||
1617 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1618 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1619 | const char __user *user_buf, \ | |
1620 | size_t count, loff_t *ppos); | |
1621 | ||
1622 | ||
1623 | static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file) | |
1624 | { | |
1625 | file->private_data = inode->i_private; | |
1626 | return 0; | |
1627 | } | |
1628 | ||
1629 | #define DEBUGFS_READ_FILE_OPS(name) \ | |
1630 | DEBUGFS_READ_FUNC(name); \ | |
1631 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1632 | .read = iwl_dbgfs_##name##_read, \ | |
1633 | .open = iwl_dbgfs_open_file_generic, \ | |
1634 | .llseek = generic_file_llseek, \ | |
1635 | }; | |
1636 | ||
16db88ba EG |
1637 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1638 | DEBUGFS_WRITE_FUNC(name); \ | |
1639 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1640 | .write = iwl_dbgfs_##name##_write, \ | |
1641 | .open = iwl_dbgfs_open_file_generic, \ | |
1642 | .llseek = generic_file_llseek, \ | |
1643 | }; | |
1644 | ||
87e5666c EG |
1645 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1646 | DEBUGFS_READ_FUNC(name); \ | |
1647 | DEBUGFS_WRITE_FUNC(name); \ | |
1648 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1649 | .write = iwl_dbgfs_##name##_write, \ | |
1650 | .read = iwl_dbgfs_##name##_read, \ | |
1651 | .open = iwl_dbgfs_open_file_generic, \ | |
1652 | .llseek = generic_file_llseek, \ | |
1653 | }; | |
1654 | ||
87e5666c EG |
1655 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
1656 | char __user *user_buf, | |
8ad71bef EG |
1657 | size_t count, loff_t *ppos) |
1658 | { | |
5a878bf6 | 1659 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1660 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
87e5666c EG |
1661 | struct iwl_tx_queue *txq; |
1662 | struct iwl_queue *q; | |
1663 | char *buf; | |
1664 | int pos = 0; | |
1665 | int cnt; | |
1666 | int ret; | |
fd656935 | 1667 | const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num; |
87e5666c | 1668 | |
8ad71bef | 1669 | if (!trans_pcie->txq) { |
3e10caeb | 1670 | IWL_ERR(trans, "txq not ready\n"); |
87e5666c EG |
1671 | return -EAGAIN; |
1672 | } | |
1673 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1674 | if (!buf) | |
1675 | return -ENOMEM; | |
1676 | ||
5a878bf6 | 1677 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { |
8ad71bef | 1678 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1679 | q = &txq->q; |
1680 | pos += scnprintf(buf + pos, bufsz - pos, | |
1681 | "hwq %.2d: read=%u write=%u stop=%d" | |
1682 | " swq_id=%#.2x (ac %d/hwq %d)\n", | |
1683 | cnt, q->read_ptr, q->write_ptr, | |
8ad71bef | 1684 | !!test_bit(cnt, trans_pcie->queue_stopped), |
87e5666c EG |
1685 | txq->swq_id, txq->swq_id & 3, |
1686 | (txq->swq_id >> 2) & 0x1f); | |
1687 | if (cnt >= 4) | |
1688 | continue; | |
1689 | /* for the ACs, display the stop count too */ | |
1690 | pos += scnprintf(buf + pos, bufsz - pos, | |
8ad71bef EG |
1691 | " stop-count: %d\n", |
1692 | atomic_read(&trans_pcie->queue_stop_count[cnt])); | |
87e5666c EG |
1693 | } |
1694 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1695 | kfree(buf); | |
1696 | return ret; | |
1697 | } | |
1698 | ||
1699 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
1700 | char __user *user_buf, | |
1701 | size_t count, loff_t *ppos) { | |
5a878bf6 EG |
1702 | struct iwl_trans *trans = file->private_data; |
1703 | struct iwl_trans_pcie *trans_pcie = | |
1704 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1705 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
87e5666c EG |
1706 | char buf[256]; |
1707 | int pos = 0; | |
1708 | const size_t bufsz = sizeof(buf); | |
1709 | ||
1710 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1711 | rxq->read); | |
1712 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1713 | rxq->write); | |
1714 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1715 | rxq->free_count); | |
1716 | if (rxq->rb_stts) { | |
1717 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1718 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1719 | } else { | |
1720 | pos += scnprintf(buf + pos, bufsz - pos, | |
1721 | "closed_rb_num: Not Allocated\n"); | |
1722 | } | |
1723 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1724 | } | |
1725 | ||
7ff94706 EG |
1726 | static ssize_t iwl_dbgfs_log_event_read(struct file *file, |
1727 | char __user *user_buf, | |
1728 | size_t count, loff_t *ppos) | |
1729 | { | |
1730 | struct iwl_trans *trans = file->private_data; | |
1731 | char *buf; | |
1732 | int pos = 0; | |
1733 | ssize_t ret = -ENOMEM; | |
1734 | ||
6bb78847 | 1735 | ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true); |
7ff94706 EG |
1736 | if (buf) { |
1737 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1738 | kfree(buf); | |
1739 | } | |
1740 | return ret; | |
1741 | } | |
1742 | ||
1743 | static ssize_t iwl_dbgfs_log_event_write(struct file *file, | |
1744 | const char __user *user_buf, | |
1745 | size_t count, loff_t *ppos) | |
1746 | { | |
1747 | struct iwl_trans *trans = file->private_data; | |
1748 | u32 event_log_flag; | |
1749 | char buf[8]; | |
1750 | int buf_size; | |
1751 | ||
1752 | memset(buf, 0, sizeof(buf)); | |
1753 | buf_size = min(count, sizeof(buf) - 1); | |
1754 | if (copy_from_user(buf, user_buf, buf_size)) | |
1755 | return -EFAULT; | |
1756 | if (sscanf(buf, "%d", &event_log_flag) != 1) | |
1757 | return -EFAULT; | |
1758 | if (event_log_flag == 1) | |
6bb78847 | 1759 | iwl_dump_nic_event_log(trans, true, NULL, false); |
7ff94706 EG |
1760 | |
1761 | return count; | |
1762 | } | |
1763 | ||
1f7b6172 EG |
1764 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1765 | char __user *user_buf, | |
1766 | size_t count, loff_t *ppos) { | |
1767 | ||
1768 | struct iwl_trans *trans = file->private_data; | |
1769 | struct iwl_trans_pcie *trans_pcie = | |
1770 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1771 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
1772 | ||
1773 | int pos = 0; | |
1774 | char *buf; | |
1775 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1776 | ssize_t ret; | |
1777 | ||
1778 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1779 | if (!buf) { | |
1780 | IWL_ERR(trans, "Can not allocate Buffer\n"); | |
1781 | return -ENOMEM; | |
1782 | } | |
1783 | ||
1784 | pos += scnprintf(buf + pos, bufsz - pos, | |
1785 | "Interrupt Statistics Report:\n"); | |
1786 | ||
1787 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1788 | isr_stats->hw); | |
1789 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1790 | isr_stats->sw); | |
1791 | if (isr_stats->sw || isr_stats->hw) { | |
1792 | pos += scnprintf(buf + pos, bufsz - pos, | |
1793 | "\tLast Restarting Code: 0x%X\n", | |
1794 | isr_stats->err_code); | |
1795 | } | |
1796 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1797 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1798 | isr_stats->sch); | |
1799 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1800 | isr_stats->alive); | |
1801 | #endif | |
1802 | pos += scnprintf(buf + pos, bufsz - pos, | |
1803 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1804 | ||
1805 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1806 | isr_stats->ctkill); | |
1807 | ||
1808 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1809 | isr_stats->wakeup); | |
1810 | ||
1811 | pos += scnprintf(buf + pos, bufsz - pos, | |
1812 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1813 | ||
1814 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1815 | isr_stats->tx); | |
1816 | ||
1817 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1818 | isr_stats->unhandled); | |
1819 | ||
1820 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1821 | kfree(buf); | |
1822 | return ret; | |
1823 | } | |
1824 | ||
1825 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1826 | const char __user *user_buf, | |
1827 | size_t count, loff_t *ppos) | |
1828 | { | |
1829 | struct iwl_trans *trans = file->private_data; | |
1830 | struct iwl_trans_pcie *trans_pcie = | |
1831 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1832 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
1833 | ||
1834 | char buf[8]; | |
1835 | int buf_size; | |
1836 | u32 reset_flag; | |
1837 | ||
1838 | memset(buf, 0, sizeof(buf)); | |
1839 | buf_size = min(count, sizeof(buf) - 1); | |
1840 | if (copy_from_user(buf, user_buf, buf_size)) | |
1841 | return -EFAULT; | |
1842 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1843 | return -EFAULT; | |
1844 | if (reset_flag == 0) | |
1845 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1846 | ||
1847 | return count; | |
1848 | } | |
1849 | ||
16db88ba EG |
1850 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
1851 | const char __user *user_buf, | |
1852 | size_t count, loff_t *ppos) | |
1853 | { | |
1854 | struct iwl_trans *trans = file->private_data; | |
1855 | char buf[8]; | |
1856 | int buf_size; | |
1857 | int csr; | |
1858 | ||
1859 | memset(buf, 0, sizeof(buf)); | |
1860 | buf_size = min(count, sizeof(buf) - 1); | |
1861 | if (copy_from_user(buf, user_buf, buf_size)) | |
1862 | return -EFAULT; | |
1863 | if (sscanf(buf, "%d", &csr) != 1) | |
1864 | return -EFAULT; | |
1865 | ||
1866 | iwl_dump_csr(trans); | |
1867 | ||
1868 | return count; | |
1869 | } | |
1870 | ||
16db88ba EG |
1871 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
1872 | char __user *user_buf, | |
1873 | size_t count, loff_t *ppos) | |
1874 | { | |
1875 | struct iwl_trans *trans = file->private_data; | |
1876 | char *buf; | |
1877 | int pos = 0; | |
1878 | ssize_t ret = -EFAULT; | |
1879 | ||
1880 | ret = pos = iwl_dump_fh(trans, &buf, true); | |
1881 | if (buf) { | |
1882 | ret = simple_read_from_buffer(user_buf, | |
1883 | count, ppos, buf, pos); | |
1884 | kfree(buf); | |
1885 | } | |
1886 | ||
1887 | return ret; | |
1888 | } | |
1889 | ||
7ff94706 | 1890 | DEBUGFS_READ_WRITE_FILE_OPS(log_event); |
1f7b6172 | 1891 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1892 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1893 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1894 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1895 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c EG |
1896 | |
1897 | /* | |
1898 | * Create the debugfs files and directories | |
1899 | * | |
1900 | */ | |
1901 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1902 | struct dentry *dir) | |
1903 | { | |
87e5666c EG |
1904 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1905 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
7ff94706 | 1906 | DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR); |
1f7b6172 | 1907 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1908 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1909 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c EG |
1910 | return 0; |
1911 | } | |
1912 | #else | |
1913 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1914 | struct dentry *dir) | |
1915 | { return 0; } | |
1916 | ||
1917 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ | |
1918 | ||
e6bb4c9c | 1919 | const struct iwl_trans_ops trans_ops_pcie = { |
e6bb4c9c | 1920 | .request_irq = iwl_trans_pcie_request_irq, |
ed6a3803 | 1921 | .fw_alive = iwl_trans_pcie_fw_alive, |
e6bb4c9c EG |
1922 | .start_device = iwl_trans_pcie_start_device, |
1923 | .prepare_card_hw = iwl_trans_pcie_prepare_card_hw, | |
1924 | .stop_device = iwl_trans_pcie_stop_device, | |
48d42c42 | 1925 | |
e13c0c59 | 1926 | .wake_any_queue = iwl_trans_pcie_wake_any_queue, |
48d42c42 | 1927 | |
e6bb4c9c | 1928 | .send_cmd = iwl_trans_pcie_send_cmd, |
c85eb619 | 1929 | |
e6bb4c9c | 1930 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 1931 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1932 | |
7f01d567 | 1933 | .tx_agg_disable = iwl_trans_pcie_tx_agg_disable, |
288712a6 | 1934 | .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc, |
c91bd124 | 1935 | .tx_agg_setup = iwl_trans_pcie_tx_agg_setup, |
34c1b7ba | 1936 | |
e6bb4c9c | 1937 | .kick_nic = iwl_trans_pcie_kick_nic, |
1e89cbac | 1938 | |
e6bb4c9c | 1939 | .free = iwl_trans_pcie_free, |
e20d4341 | 1940 | .stop_queue = iwl_trans_pcie_stop_queue, |
87e5666c EG |
1941 | |
1942 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, | |
5f178cd2 EG |
1943 | |
1944 | .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty, | |
f22be624 | 1945 | .check_stuck_queue = iwl_trans_pcie_check_stuck_queue, |
5f178cd2 | 1946 | |
c01a4047 | 1947 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1948 | .suspend = iwl_trans_pcie_suspend, |
1949 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 1950 | #endif |
e6bb4c9c | 1951 | }; |